HPM SDK
HPMicro Software Development Kit
hpm_ppor_regs.h
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_PPOR_H
10 #define HPM_PPOR_H
11 
12 typedef struct {
13  __W uint32_t RESET_FLAG; /* 0x0: flag indicate reset source */
14  __R uint32_t RESET_STATUS; /* 0x4: reset source status */
15  __RW uint32_t RESET_HOLD; /* 0x8: reset hold attribute */
16  __RW uint32_t RESET_ENABLE; /* 0xC: reset source enable */
17  __RW uint32_t RESET_TYPE; /* 0x10: reset type triggered by reset */
18  __R uint8_t RESERVED0[8]; /* 0x14 - 0x1B: Reserved */
19  __RW uint32_t SOFTWARE_RESET; /* 0x1C: Software reset counter */
20 } PPOR_Type;
21 
22 
23 /* Bitfield definition for register: RESET_FLAG */
24 /*
25  * FLAG (W1C)
26  *
27  * reset reason of last hard reset, write 1 to clear each bit
28  * 0: brownout
29  * 1: temperature
30  * 4: debug reset
31  * 5: jtag soft reset
32  * 8: cpu0 lockup(not available)
33  * 9: cpu1 lockup(not available)
34  * 10: cpu0 request(not available)
35  * 11: cpu1 request(not available)
36  * 16: watch dog 0
37  * 17: watch dog 1
38  * 18: watch dog 2(not available)
39  * 19: watch dog 3(not available)
40  * 24: pmic watch dog
41  * 30: jtag ieee reset
42  * 31: software
43  */
44 #define PPOR_RESET_FLAG_FLAG_MASK (0xFFFFFFFFUL)
45 #define PPOR_RESET_FLAG_FLAG_SHIFT (0U)
46 #define PPOR_RESET_FLAG_FLAG_SET(x) (((uint32_t)(x) << PPOR_RESET_FLAG_FLAG_SHIFT) & PPOR_RESET_FLAG_FLAG_MASK)
47 #define PPOR_RESET_FLAG_FLAG_GET(x) (((uint32_t)(x) & PPOR_RESET_FLAG_FLAG_MASK) >> PPOR_RESET_FLAG_FLAG_SHIFT)
48 
49 /* Bitfield definition for register: RESET_STATUS */
50 /*
51  * STATUS (RO)
52  *
53  * current status of reset sources
54  * 0: brownout
55  * 1: temperature
56  * 4: debug reset
57  * 5: jtag soft reset
58  * 8: cpu0 lockup(not available)
59  * 9: cpu1 lockup(not available)
60  * 10: cpu0 request(not available)
61  * 11: cpu1 request(not available)
62  * 16: watch dog 0
63  * 17: watch dog 1
64  * 18: watch dog 2(not available)
65  * 19: watch dog 3(not available)
66  * 24: pmic watch dog
67  * 30: jtag ieee reset
68  * 31: software
69  */
70 #define PPOR_RESET_STATUS_STATUS_MASK (0xFFFFFFFFUL)
71 #define PPOR_RESET_STATUS_STATUS_SHIFT (0U)
72 #define PPOR_RESET_STATUS_STATUS_GET(x) (((uint32_t)(x) & PPOR_RESET_STATUS_STATUS_MASK) >> PPOR_RESET_STATUS_STATUS_SHIFT)
73 
74 /* Bitfield definition for register: RESET_HOLD */
75 /*
76  * HOLD (RW)
77  *
78  * hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status
79  * 0: brownout
80  * 1: temperature
81  * 4: debug reset
82  * 5: jtag soft reset
83  * 8: cpu0 lockup(not available)
84  * 9: cpu1 lockup(not available)
85  * 10: cpu0 request(not available)
86  * 11: cpu1 request(not available)
87  * 16: watch dog 0
88  * 17: watch dog 1
89  * 18: watch dog 2(not available)
90  * 19: watch dog 3(not available)
91  * 24: pmic watch dog
92  * 30: jtag ieee reset
93  * 31: software
94  */
95 #define PPOR_RESET_HOLD_HOLD_MASK (0xFFFFFFFFUL)
96 #define PPOR_RESET_HOLD_HOLD_SHIFT (0U)
97 #define PPOR_RESET_HOLD_HOLD_SET(x) (((uint32_t)(x) << PPOR_RESET_HOLD_HOLD_SHIFT) & PPOR_RESET_HOLD_HOLD_MASK)
98 #define PPOR_RESET_HOLD_HOLD_GET(x) (((uint32_t)(x) & PPOR_RESET_HOLD_HOLD_MASK) >> PPOR_RESET_HOLD_HOLD_SHIFT)
99 
100 /* Bitfield definition for register: RESET_ENABLE */
101 /*
102  * ENABLE (RW)
103  *
104  * enable of reset sources
105  * 0: brownout
106  * 1: temperature
107  * 4: debug reset
108  * 5: jtag soft reset
109  * 8: cpu0 lockup(not available)
110  * 9: cpu1 lockup(not available)
111  * 10: cpu0 request(not available)
112  * 11: cpu1 request(not available)
113  * 16: watch dog 0
114  * 17: watch dog 1
115  * 18: watch dog 2(not available)
116  * 19: watch dog 3(not available)
117  * 24: pmic watch dog
118  * 30: jtag ieee reset
119  * 31: software
120  */
121 #define PPOR_RESET_ENABLE_ENABLE_MASK (0xFFFFFFFFUL)
122 #define PPOR_RESET_ENABLE_ENABLE_SHIFT (0U)
123 #define PPOR_RESET_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << PPOR_RESET_ENABLE_ENABLE_SHIFT) & PPOR_RESET_ENABLE_ENABLE_MASK)
124 #define PPOR_RESET_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & PPOR_RESET_ENABLE_ENABLE_MASK) >> PPOR_RESET_ENABLE_ENABLE_SHIFT)
125 
126 /* Bitfield definition for register: RESET_TYPE */
127 /*
128  * TYPE (RW)
129  *
130  * reset type of reset sources, 0 for cold reset, all system control setting cleared except debug/fuse/ioc; 1 for hot reset, keep system control setting and debug/fuse/ioc setting, only clear some subsystem
131  * 0: brownout
132  * 1: temperature
133  * 4: debug reset
134  * 5: jtag soft reset
135  * 8: cpu0 lockup(not available)
136  * 9: cpu1 lockup(not available)
137  * 10: cpu0 request(not available)
138  * 11: cpu1 request(not available)
139  * 16: watch dog 0
140  * 17: watch dog 1
141  * 18: watch dog 2(not available)
142  * 19: watch dog 3(not available)
143  * 24: pmic watch dog
144  * 30: jtag ieee reset
145  * 31: software
146  */
147 #define PPOR_RESET_TYPE_TYPE_MASK (0xFFFFFFFFUL)
148 #define PPOR_RESET_TYPE_TYPE_SHIFT (0U)
149 #define PPOR_RESET_TYPE_TYPE_SET(x) (((uint32_t)(x) << PPOR_RESET_TYPE_TYPE_SHIFT) & PPOR_RESET_TYPE_TYPE_MASK)
150 #define PPOR_RESET_TYPE_TYPE_GET(x) (((uint32_t)(x) & PPOR_RESET_TYPE_TYPE_MASK) >> PPOR_RESET_TYPE_TYPE_SHIFT)
151 
152 /* Bitfield definition for register: SOFTWARE_RESET */
153 /*
154  * COUNTER (RW)
155  *
156  * counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset
157  */
158 #define PPOR_SOFTWARE_RESET_COUNTER_MASK (0xFFFFFFFFUL)
159 #define PPOR_SOFTWARE_RESET_COUNTER_SHIFT (0U)
160 #define PPOR_SOFTWARE_RESET_COUNTER_SET(x) (((uint32_t)(x) << PPOR_SOFTWARE_RESET_COUNTER_SHIFT) & PPOR_SOFTWARE_RESET_COUNTER_MASK)
161 #define PPOR_SOFTWARE_RESET_COUNTER_GET(x) (((uint32_t)(x) & PPOR_SOFTWARE_RESET_COUNTER_MASK) >> PPOR_SOFTWARE_RESET_COUNTER_SHIFT)
162 
163 
164 
165 
166 #endif /* HPM_PPOR_H */
PPOR_Type
Definition: hpm_ppor_regs.h:12