HPM SDK
HPMicro Software Development Kit
hpm_sysctl_regs.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_SYSCTL_H
10 #define HPM_SYSCTL_H
11 
12 typedef struct {
13  __RW uint32_t RESOURCE[321]; /* 0x0 - 0x500: Resource control register for cpu0_core */
14  __R uint8_t RESERVED0[764]; /* 0x504 - 0x7FF: Reserved */
15  struct {
16  __RW uint32_t VALUE; /* 0x800: Group setting */
17  __RW uint32_t SET; /* 0x804: Group setting */
18  __RW uint32_t CLEAR; /* 0x808: Group setting */
19  __RW uint32_t TOGGLE; /* 0x80C: Group setting */
20  } GROUP0[4];
21  struct {
22  __RW uint32_t VALUE; /* 0x840: Group setting */
23  __RW uint32_t SET; /* 0x844: Group setting */
24  __RW uint32_t CLEAR; /* 0x848: Group setting */
25  __RW uint32_t TOGGLE; /* 0x84C: Group setting */
26  } GROUP1[4];
27  __R uint8_t RESERVED1[128]; /* 0x880 - 0x8FF: Reserved */
28  struct {
29  __RW uint32_t VALUE; /* 0x900: Affiliate of Group */
30  __RW uint32_t SET; /* 0x904: Affiliate of Group */
31  __RW uint32_t CLEAR; /* 0x908: Affiliate of Group */
32  __RW uint32_t TOGGLE; /* 0x90C: Affiliate of Group */
33  } AFFILIATE[1];
34  __R uint8_t RESERVED2[16]; /* 0x910 - 0x91F: Reserved */
35  struct {
36  __RW uint32_t VALUE; /* 0x920: Retention Contol */
37  __RW uint32_t SET; /* 0x924: Retention Contol */
38  __RW uint32_t CLEAR; /* 0x928: Retention Contol */
39  __RW uint32_t TOGGLE; /* 0x92C: Retention Contol */
40  } RETENTION[1];
41  __R uint8_t RESERVED3[1744]; /* 0x930 - 0xFFF: Reserved */
42  struct {
43  __RW uint32_t STATUS; /* 0x1000: Power Setting */
44  __RW uint32_t LF_WAIT; /* 0x1004: Power Setting */
45  __R uint8_t RESERVED0[4]; /* 0x1008 - 0x100B: Reserved */
46  __RW uint32_t OFF_WAIT; /* 0x100C: Power Setting */
47  } POWER[1];
48  __R uint8_t RESERVED4[1008]; /* 0x1010 - 0x13FF: Reserved */
49  struct {
50  __RW uint32_t CONTROL; /* 0x1400: Reset Setting */
51  __RW uint32_t CONFIG; /* 0x1404: Reset Setting */
52  __R uint8_t RESERVED0[4]; /* 0x1408 - 0x140B: Reserved */
53  __RW uint32_t COUNTER; /* 0x140C: Reset Setting */
54  } RESET[2];
55  __R uint8_t RESERVED5[992]; /* 0x1420 - 0x17FF: Reserved */
56  __RW uint32_t CLOCK[41]; /* 0x1800 - 0x18A0: Clock setting */
57  __R uint8_t RESERVED6[860]; /* 0x18A4 - 0x1BFF: Reserved */
58  __RW uint32_t ADCCLK[2]; /* 0x1C00 - 0x1C04: Clock setting */
59  __R uint8_t RESERVED7[1016]; /* 0x1C08 - 0x1FFF: Reserved */
60  __RW uint32_t GLOBAL00; /* 0x2000: Clock senario */
61  __R uint8_t RESERVED8[1020]; /* 0x2004 - 0x23FF: Reserved */
62  struct {
63  __RW uint32_t CONTROL; /* 0x2400: Clock measure and monitor control */
64  __R uint32_t CURRENT; /* 0x2404: Clock measure result */
65  __RW uint32_t LOW_LIMIT; /* 0x2408: Clock lower limit */
66  __RW uint32_t HIGH_LIMIT; /* 0x240C: Clock upper limit */
67  __R uint8_t RESERVED0[16]; /* 0x2410 - 0x241F: Reserved */
68  } MONITOR[4];
69  __R uint8_t RESERVED9[896]; /* 0x2480 - 0x27FF: Reserved */
70  struct {
71  __RW uint32_t LP; /* 0x2800: CPU0 LP control */
72  __RW uint32_t LOCK; /* 0x2804: CPU0 Lock GPR */
73  __RW uint32_t GPR[14]; /* 0x2808 - 0x283C: CPU0 GPR0 */
74  __R uint32_t WAKEUP_STATUS[6]; /* 0x2840 - 0x2854: CPU0 wakeup IRQ status */
75  __R uint8_t RESERVED0[40]; /* 0x2858 - 0x287F: Reserved */
76  __RW uint32_t WAKEUP_ENABLE[6]; /* 0x2880 - 0x2894: CPU0 wakeup IRQ enable */
77  __R uint8_t RESERVED1[872]; /* 0x2898 - 0x2BFF: Reserved */
78  } CPU[1];
79 } SYSCTL_Type;
80 
81 
82 /* Bitfield definition for register array: RESOURCE */
83 /*
84  * GLB_BUSY (RO)
85  *
86  * global busy
87  * 0: no changes pending to any nodes
88  * 1: any of nodes is changing status
89  */
90 #define SYSCTL_RESOURCE_GLB_BUSY_MASK (0x80000000UL)
91 #define SYSCTL_RESOURCE_GLB_BUSY_SHIFT (31U)
92 #define SYSCTL_RESOURCE_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_GLB_BUSY_MASK) >> SYSCTL_RESOURCE_GLB_BUSY_SHIFT)
93 
94 /*
95  * LOC_BUSY (RO)
96  *
97  * local busy
98  * 0: no change is pending for current node
99  * 1: current node is changing status
100  */
101 #define SYSCTL_RESOURCE_LOC_BUSY_MASK (0x40000000UL)
102 #define SYSCTL_RESOURCE_LOC_BUSY_SHIFT (30U)
103 #define SYSCTL_RESOURCE_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_LOC_BUSY_MASK) >> SYSCTL_RESOURCE_LOC_BUSY_SHIFT)
104 
105 /*
106  * MODE (RW)
107  *
108  * resource work mode
109  * 0:auto turn on and off as system required(recommended)
110  * 1:always on
111  * 2:always off
112  * 3:reserved
113  */
114 #define SYSCTL_RESOURCE_MODE_MASK (0x3U)
115 #define SYSCTL_RESOURCE_MODE_SHIFT (0U)
116 #define SYSCTL_RESOURCE_MODE_SET(x) (((uint32_t)(x) << SYSCTL_RESOURCE_MODE_SHIFT) & SYSCTL_RESOURCE_MODE_MASK)
117 #define SYSCTL_RESOURCE_MODE_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_MODE_MASK) >> SYSCTL_RESOURCE_MODE_SHIFT)
118 
119 /* Bitfield definition for register of struct array GROUP0: VALUE */
120 /*
121  * LINK (RW)
122  *
123  * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral
124  * 0: peripheral is not needed
125  * 1: periphera is needed
126  */
127 #define SYSCTL_GROUP0_VALUE_LINK_MASK (0xFFFFFFFFUL)
128 #define SYSCTL_GROUP0_VALUE_LINK_SHIFT (0U)
129 #define SYSCTL_GROUP0_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_VALUE_LINK_SHIFT) & SYSCTL_GROUP0_VALUE_LINK_MASK)
130 #define SYSCTL_GROUP0_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_VALUE_LINK_MASK) >> SYSCTL_GROUP0_VALUE_LINK_SHIFT)
131 
132 /* Bitfield definition for register of struct array GROUP0: SET */
133 /*
134  * LINK (RW)
135  *
136  * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral
137  * 0: no effect
138  * 1: add periphera into this group，periphera is needed
139  */
140 #define SYSCTL_GROUP0_SET_LINK_MASK (0xFFFFFFFFUL)
141 #define SYSCTL_GROUP0_SET_LINK_SHIFT (0U)
142 #define SYSCTL_GROUP0_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_SET_LINK_SHIFT) & SYSCTL_GROUP0_SET_LINK_MASK)
143 #define SYSCTL_GROUP0_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_SET_LINK_MASK) >> SYSCTL_GROUP0_SET_LINK_SHIFT)
144 
145 /* Bitfield definition for register of struct array GROUP0: CLEAR */
146 /*
147  * LINK (RW)
148  *
149  * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral
150  * 0: no effect
151  * 1: delete periphera in this group，periphera is not needed
152  */
153 #define SYSCTL_GROUP0_CLEAR_LINK_MASK (0xFFFFFFFFUL)
154 #define SYSCTL_GROUP0_CLEAR_LINK_SHIFT (0U)
155 #define SYSCTL_GROUP0_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_CLEAR_LINK_SHIFT) & SYSCTL_GROUP0_CLEAR_LINK_MASK)
156 #define SYSCTL_GROUP0_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_CLEAR_LINK_MASK) >> SYSCTL_GROUP0_CLEAR_LINK_SHIFT)
157 
158 /* Bitfield definition for register of struct array GROUP0: TOGGLE */
159 /*
160  * LINK (RW)
161  *
162  * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral
163  * 0: no effect
164  * 1: toggle the result that whether periphera is needed before
165  */
166 #define SYSCTL_GROUP0_TOGGLE_LINK_MASK (0xFFFFFFFFUL)
167 #define SYSCTL_GROUP0_TOGGLE_LINK_SHIFT (0U)
168 #define SYSCTL_GROUP0_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_TOGGLE_LINK_SHIFT) & SYSCTL_GROUP0_TOGGLE_LINK_MASK)
169 #define SYSCTL_GROUP0_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_TOGGLE_LINK_MASK) >> SYSCTL_GROUP0_TOGGLE_LINK_SHIFT)
170 
171 /* Bitfield definition for register of struct array GROUP1: VALUE */
172 /*
173  * LINK (RW)
174  *
175  * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral
176  * 0: peripheral is not needed
177  * 1: periphera is needed
178  */
179 #define SYSCTL_GROUP1_VALUE_LINK_MASK (0xFFFFFFFFUL)
180 #define SYSCTL_GROUP1_VALUE_LINK_SHIFT (0U)
181 #define SYSCTL_GROUP1_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_VALUE_LINK_SHIFT) & SYSCTL_GROUP1_VALUE_LINK_MASK)
182 #define SYSCTL_GROUP1_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_VALUE_LINK_MASK) >> SYSCTL_GROUP1_VALUE_LINK_SHIFT)
183 
184 /* Bitfield definition for register of struct array GROUP1: SET */
185 /*
186  * LINK (RW)
187  *
188  * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral
189  * 0: no effect
190  * 1: add periphera into this group，periphera is needed
191  */
192 #define SYSCTL_GROUP1_SET_LINK_MASK (0xFFFFFFFFUL)
193 #define SYSCTL_GROUP1_SET_LINK_SHIFT (0U)
194 #define SYSCTL_GROUP1_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_SET_LINK_SHIFT) & SYSCTL_GROUP1_SET_LINK_MASK)
195 #define SYSCTL_GROUP1_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_SET_LINK_MASK) >> SYSCTL_GROUP1_SET_LINK_SHIFT)
196 
197 /* Bitfield definition for register of struct array GROUP1: CLEAR */
198 /*
199  * LINK (RW)
200  *
201  * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral
202  * 0: no effect
203  * 1: delete periphera in this group，periphera is not needed
204  */
205 #define SYSCTL_GROUP1_CLEAR_LINK_MASK (0xFFFFFFFFUL)
206 #define SYSCTL_GROUP1_CLEAR_LINK_SHIFT (0U)
207 #define SYSCTL_GROUP1_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_CLEAR_LINK_SHIFT) & SYSCTL_GROUP1_CLEAR_LINK_MASK)
208 #define SYSCTL_GROUP1_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_CLEAR_LINK_MASK) >> SYSCTL_GROUP1_CLEAR_LINK_SHIFT)
209 
210 /* Bitfield definition for register of struct array GROUP1: TOGGLE */
211 /*
212  * LINK (RW)
213  *
214  * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral
215  * 0: no effect
216  * 1: toggle the result that whether periphera is needed before
217  */
218 #define SYSCTL_GROUP1_TOGGLE_LINK_MASK (0xFFFFFFFFUL)
219 #define SYSCTL_GROUP1_TOGGLE_LINK_SHIFT (0U)
220 #define SYSCTL_GROUP1_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_TOGGLE_LINK_SHIFT) & SYSCTL_GROUP1_TOGGLE_LINK_MASK)
221 #define SYSCTL_GROUP1_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_TOGGLE_LINK_MASK) >> SYSCTL_GROUP1_TOGGLE_LINK_SHIFT)
222 
223 /* Bitfield definition for register of struct array AFFILIATE: VALUE */
224 /*
225  * LINK (RW)
226  *
227  * Affiliate groups of cpu0, each bit represents a group
228  * bit0: cpu0 depends on group0
229  * bit1: cpu0 depends on group1
230  * bit2: cpu0 depends on group2
231  * bit3: cpu0 depends on group3
232  */
233 #define SYSCTL_AFFILIATE_VALUE_LINK_MASK (0xFU)
234 #define SYSCTL_AFFILIATE_VALUE_LINK_SHIFT (0U)
235 #define SYSCTL_AFFILIATE_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_VALUE_LINK_SHIFT) & SYSCTL_AFFILIATE_VALUE_LINK_MASK)
236 #define SYSCTL_AFFILIATE_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_VALUE_LINK_MASK) >> SYSCTL_AFFILIATE_VALUE_LINK_SHIFT)
237 
238 /* Bitfield definition for register of struct array AFFILIATE: SET */
239 /*
240  * LINK (RW)
241  *
242  * Affiliate groups of cpu0，each bit represents a group
243  * 0: no effect
244  * 1: the group is assigned to CPU0
245  */
246 #define SYSCTL_AFFILIATE_SET_LINK_MASK (0xFU)
247 #define SYSCTL_AFFILIATE_SET_LINK_SHIFT (0U)
248 #define SYSCTL_AFFILIATE_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_SET_LINK_SHIFT) & SYSCTL_AFFILIATE_SET_LINK_MASK)
249 #define SYSCTL_AFFILIATE_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_SET_LINK_MASK) >> SYSCTL_AFFILIATE_SET_LINK_SHIFT)
250 
251 /* Bitfield definition for register of struct array AFFILIATE: CLEAR */
252 /*
253  * LINK (RW)
254  *
255  * Affiliate groups of cpu0, each bit represents a group
256  * 0: no effect
257  * 1: the group is not assigned to CPU0
258  */
259 #define SYSCTL_AFFILIATE_CLEAR_LINK_MASK (0xFU)
260 #define SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT (0U)
261 #define SYSCTL_AFFILIATE_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK)
262 #define SYSCTL_AFFILIATE_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK) >> SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT)
263 
264 /* Bitfield definition for register of struct array AFFILIATE: TOGGLE */
265 /*
266  * LINK (RW)
267  *
268  * Affiliate groups of cpu0, each bit represents a group
269  * 0: no effect
270  * 1: toggle the result that whether the group is assigned to CPU0 before
271  */
272 #define SYSCTL_AFFILIATE_TOGGLE_LINK_MASK (0xFU)
273 #define SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT (0U)
274 #define SYSCTL_AFFILIATE_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK)
275 #define SYSCTL_AFFILIATE_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK) >> SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT)
276 
277 /* Bitfield definition for register of struct array RETENTION: VALUE */
278 /*
279  * LINK (RW)
280  *
281  * retention setting while CPU0 enter stop mode, each bit represents a resource
282  * bit00: soc_mem is kept on while cpu0 stop
283  * bit01: soc_ctx is kept on while cpu0 stop
284  * bit02: cpu0_mem is kept on while cpu0 stop
285  * bit03: cpu0_ctx is kept on while cpu0 stop
286  * bit04: xtal_hold is kept on while cpu0 stop
287  * bit05: pll0_hold is kept on while cpu0 stop
288  * bit06: pll1_hold is kept on while cpu0 stop
289  */
290 #define SYSCTL_RETENTION_VALUE_LINK_MASK (0x7FFFU)
291 #define SYSCTL_RETENTION_VALUE_LINK_SHIFT (0U)
292 #define SYSCTL_RETENTION_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_VALUE_LINK_SHIFT) & SYSCTL_RETENTION_VALUE_LINK_MASK)
293 #define SYSCTL_RETENTION_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_VALUE_LINK_MASK) >> SYSCTL_RETENTION_VALUE_LINK_SHIFT)
294 
295 /* Bitfield definition for register of struct array RETENTION: SET */
296 /*
297  * LINK (RW)
298  *
299  * retention setting while CPU0 enter stop mode, each bit represents a resource
300  * 0: no effect
301  * 1: keep
302  */
303 #define SYSCTL_RETENTION_SET_LINK_MASK (0x7FFFU)
304 #define SYSCTL_RETENTION_SET_LINK_SHIFT (0U)
305 #define SYSCTL_RETENTION_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_SET_LINK_SHIFT) & SYSCTL_RETENTION_SET_LINK_MASK)
306 #define SYSCTL_RETENTION_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_SET_LINK_MASK) >> SYSCTL_RETENTION_SET_LINK_SHIFT)
307 
308 /* Bitfield definition for register of struct array RETENTION: CLEAR */
309 /*
310  * LINK (RW)
311  *
312  * retention setting while CPU0 enter stop mode, each bit represents a resource
313  * 0: no effect
314  * 1: no keep
315  */
316 #define SYSCTL_RETENTION_CLEAR_LINK_MASK (0x7FFFU)
317 #define SYSCTL_RETENTION_CLEAR_LINK_SHIFT (0U)
318 #define SYSCTL_RETENTION_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_CLEAR_LINK_SHIFT) & SYSCTL_RETENTION_CLEAR_LINK_MASK)
319 #define SYSCTL_RETENTION_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_CLEAR_LINK_MASK) >> SYSCTL_RETENTION_CLEAR_LINK_SHIFT)
320 
321 /* Bitfield definition for register of struct array RETENTION: TOGGLE */
322 /*
323  * LINK (RW)
324  *
325  * retention setting while CPU0 enter stop mode, each bit represents a resource
326  * 0: no effect
327  * 1: toggle the result that whether the resource is kept on while CPU0 stop before
328  */
329 #define SYSCTL_RETENTION_TOGGLE_LINK_MASK (0x7FFFU)
330 #define SYSCTL_RETENTION_TOGGLE_LINK_SHIFT (0U)
331 #define SYSCTL_RETENTION_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_TOGGLE_LINK_SHIFT) & SYSCTL_RETENTION_TOGGLE_LINK_MASK)
332 #define SYSCTL_RETENTION_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_TOGGLE_LINK_MASK) >> SYSCTL_RETENTION_TOGGLE_LINK_SHIFT)
333 
334 /* Bitfield definition for register of struct array POWER: STATUS */
335 /*
336  * FLAG (RW)
337  *
338  * flag represents power cycle happened from last clear of this bit
339  * 0: power domain did not edurance power cycle since last clear of this bit
340  * 1: power domain enduranced power cycle since last clear of this bit
341  */
342 #define SYSCTL_POWER_STATUS_FLAG_MASK (0x80000000UL)
343 #define SYSCTL_POWER_STATUS_FLAG_SHIFT (31U)
344 #define SYSCTL_POWER_STATUS_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_SHIFT) & SYSCTL_POWER_STATUS_FLAG_MASK)
345 #define SYSCTL_POWER_STATUS_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_MASK) >> SYSCTL_POWER_STATUS_FLAG_SHIFT)
346 
347 /*
348  * FLAG_WAKE (RW)
349  *
350  * flag represents wakeup power cycle happened from last clear of this bit
351  * 0: power domain did not edurance wakeup power cycle since last clear of this bit
352  * 1: power domain enduranced wakeup power cycle since last clear of this bit
353  */
354 #define SYSCTL_POWER_STATUS_FLAG_WAKE_MASK (0x40000000UL)
355 #define SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT (30U)
356 #define SYSCTL_POWER_STATUS_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK)
357 #define SYSCTL_POWER_STATUS_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK) >> SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT)
358 
359 /*
360  * MEM_RET_N (RO)
361  *
362  * memory info retention control signal
363  * 0: memory enter retention mode
364  * 1: memory exit retention mode
365  */
366 #define SYSCTL_POWER_STATUS_MEM_RET_N_MASK (0x20000UL)
367 #define SYSCTL_POWER_STATUS_MEM_RET_N_SHIFT (17U)
368 #define SYSCTL_POWER_STATUS_MEM_RET_N_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_MEM_RET_N_MASK) >> SYSCTL_POWER_STATUS_MEM_RET_N_SHIFT)
369 
370 /*
371  * MEM_RET_P (RO)
372  *
373  * memory info retention control signal
374  * 0: memory not enterexitretention mode
375  * 1: memory enter retention mode
376  */
377 #define SYSCTL_POWER_STATUS_MEM_RET_P_MASK (0x10000UL)
378 #define SYSCTL_POWER_STATUS_MEM_RET_P_SHIFT (16U)
379 #define SYSCTL_POWER_STATUS_MEM_RET_P_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_MEM_RET_P_MASK) >> SYSCTL_POWER_STATUS_MEM_RET_P_SHIFT)
380 
381 /*
382  * LF_DISABLE (RO)
383  *
384  * low fanout power switch disable
385  * 0: low fanout power switches are turned on
386  * 1: low fanout power switches are truned off
387  */
388 #define SYSCTL_POWER_STATUS_LF_DISABLE_MASK (0x1000U)
389 #define SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT (12U)
390 #define SYSCTL_POWER_STATUS_LF_DISABLE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_DISABLE_MASK) >> SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT)
391 
392 /*
393  * LF_ACK (RO)
394  *
395  * low fanout power switch feedback
396  * 0: low fanout power switches are turned on
397  * 1: low fanout power switches are truned off
398  */
399 #define SYSCTL_POWER_STATUS_LF_ACK_MASK (0x100U)
400 #define SYSCTL_POWER_STATUS_LF_ACK_SHIFT (8U)
401 #define SYSCTL_POWER_STATUS_LF_ACK_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_ACK_MASK) >> SYSCTL_POWER_STATUS_LF_ACK_SHIFT)
402 
403 /* Bitfield definition for register of struct array POWER: LF_WAIT */
404 /*
405  * WAIT (RW)
406  *
407  * wait time for low fan out power switch turn on, default value is 255
408  * 0: 0 clock cycle
409  * 1: 1 clock cycles
410  * . . .
411  * clock cycles count on 24MHz
412  */
413 #define SYSCTL_POWER_LF_WAIT_WAIT_MASK (0xFFFFFUL)
414 #define SYSCTL_POWER_LF_WAIT_WAIT_SHIFT (0U)
415 #define SYSCTL_POWER_LF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_LF_WAIT_WAIT_MASK)
416 #define SYSCTL_POWER_LF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_LF_WAIT_WAIT_MASK) >> SYSCTL_POWER_LF_WAIT_WAIT_SHIFT)
417 
418 /* Bitfield definition for register of struct array POWER: OFF_WAIT */
419 /*
420  * WAIT (RW)
421  *
422  * wait time for power switch turn off, default value is 15
423  * 0: 0 clock cycle
424  * 1: 1 clock cycles
425  * . . .
426  * clock cycles count on 24MHz
427  */
428 #define SYSCTL_POWER_OFF_WAIT_WAIT_MASK (0xFFFFFUL)
429 #define SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT (0U)
430 #define SYSCTL_POWER_OFF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK)
431 #define SYSCTL_POWER_OFF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK) >> SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT)
432 
433 /* Bitfield definition for register of struct array RESET: CONTROL */
434 /*
435  * FLAG (RW)
436  *
437  * flag represents reset happened from last clear of this bit
438  * 0: domain did not edurance reset cycle since last clear of this bit
439  * 1: domain enduranced reset cycle since last clear of this bit
440  */
441 #define SYSCTL_RESET_CONTROL_FLAG_MASK (0x80000000UL)
442 #define SYSCTL_RESET_CONTROL_FLAG_SHIFT (31U)
443 #define SYSCTL_RESET_CONTROL_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_MASK)
444 #define SYSCTL_RESET_CONTROL_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_MASK) >> SYSCTL_RESET_CONTROL_FLAG_SHIFT)
445 
446 /*
447  * FLAG_WAKE (RW)
448  *
449  * flag represents wakeup reset happened from last clear of this bit
450  * 0: domain did not edurance wakeup reset cycle since last clear of this bit
451  * 1: domain enduranced wakeup reset cycle since last clear of this bit
452  */
453 #define SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK (0x40000000UL)
454 #define SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT (30U)
455 #define SYSCTL_RESET_CONTROL_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK)
456 #define SYSCTL_RESET_CONTROL_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK) >> SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT)
457 
458 /*
459  * HOLD (RW)
460  *
461  * perform reset and hold in reset, until ths bit cleared by software
462  * 0: reset is released for function
463  * 1: reset is assert and hold
464  */
465 #define SYSCTL_RESET_CONTROL_HOLD_MASK (0x10U)
466 #define SYSCTL_RESET_CONTROL_HOLD_SHIFT (4U)
467 #define SYSCTL_RESET_CONTROL_HOLD_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_HOLD_SHIFT) & SYSCTL_RESET_CONTROL_HOLD_MASK)
468 #define SYSCTL_RESET_CONTROL_HOLD_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_HOLD_MASK) >> SYSCTL_RESET_CONTROL_HOLD_SHIFT)
469 
470 /*
471  * RESET (RW)
472  *
473  * perform reset and release imediately
474  * 0: reset is released
475  * 1 reset is asserted and will release automaticly
476  */
477 #define SYSCTL_RESET_CONTROL_RESET_MASK (0x1U)
478 #define SYSCTL_RESET_CONTROL_RESET_SHIFT (0U)
479 #define SYSCTL_RESET_CONTROL_RESET_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_RESET_SHIFT) & SYSCTL_RESET_CONTROL_RESET_MASK)
480 #define SYSCTL_RESET_CONTROL_RESET_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_RESET_MASK) >> SYSCTL_RESET_CONTROL_RESET_SHIFT)
481 
482 /* Bitfield definition for register of struct array RESET: CONFIG */
483 /*
484  * PRE_WAIT (RW)
485  *
486  * wait cycle numbers before assert reset
487  * 0: wait 0 cycle
488  * 1: wait 1 cycles
489  * . . .
490  * Note, clock cycle is base on 24M
491  */
492 #define SYSCTL_RESET_CONFIG_PRE_WAIT_MASK (0xFF0000UL)
493 #define SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT (16U)
494 #define SYSCTL_RESET_CONFIG_PRE_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK)
495 #define SYSCTL_RESET_CONFIG_PRE_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK) >> SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT)
496 
497 /*
498  * RSTCLK_NUM (RW)
499  *
500  * reset clock number(must be even number)
501  * 0: 0 cycle
502  * 1: 0 cycles
503  * 2: 2 cycles
504  * 3: 2 cycles
505  * . . .
506  * Note, clock cycle is base on 24M
507  */
508 #define SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK (0xFF00U)
509 #define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT (8U)
510 #define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK)
511 #define SYSCTL_RESET_CONFIG_RSTCLK_NUM_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK) >> SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT)
512 
513 /*
514  * POST_WAIT (RW)
515  *
516  * time guard band for reset release
517  * 0: wait 0 cycle
518  * 1: wait 1 cycles
519  * . . .
520  * Note, clock cycle is base on 24M
521  */
522 #define SYSCTL_RESET_CONFIG_POST_WAIT_MASK (0xFFU)
523 #define SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT (0U)
524 #define SYSCTL_RESET_CONFIG_POST_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK)
525 #define SYSCTL_RESET_CONFIG_POST_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK) >> SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT)
526 
527 /* Bitfield definition for register of struct array RESET: COUNTER */
528 /*
529  * COUNTER (RW)
530  *
531  * self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset
532  * 0: wait 0 cycle
533  * 1: wait 1 cycles
534  * . . .
535  * Note, clock cycle is base on 24M
536  */
537 #define SYSCTL_RESET_COUNTER_COUNTER_MASK (0xFFFFFUL)
538 #define SYSCTL_RESET_COUNTER_COUNTER_SHIFT (0U)
539 #define SYSCTL_RESET_COUNTER_COUNTER_SET(x) (((uint32_t)(x) << SYSCTL_RESET_COUNTER_COUNTER_SHIFT) & SYSCTL_RESET_COUNTER_COUNTER_MASK)
540 #define SYSCTL_RESET_COUNTER_COUNTER_GET(x) (((uint32_t)(x) & SYSCTL_RESET_COUNTER_COUNTER_MASK) >> SYSCTL_RESET_COUNTER_COUNTER_SHIFT)
541 
542 /* Bitfield definition for register array: CLOCK */
543 /*
544  * GLB_BUSY (RO)
545  *
546  * global busy
547  * 0: no changes pending to any clock
548  * 1: any of nodes is changing status
549  */
550 #define SYSCTL_CLOCK_GLB_BUSY_MASK (0x80000000UL)
551 #define SYSCTL_CLOCK_GLB_BUSY_SHIFT (31U)
552 #define SYSCTL_CLOCK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_GLB_BUSY_MASK) >> SYSCTL_CLOCK_GLB_BUSY_SHIFT)
553 
554 /*
555  * LOC_BUSY (RO)
556  *
557  * local busy
558  * 0: a change is pending for current node
559  * 1: current node is changing status
560  */
561 #define SYSCTL_CLOCK_LOC_BUSY_MASK (0x40000000UL)
562 #define SYSCTL_CLOCK_LOC_BUSY_SHIFT (30U)
563 #define SYSCTL_CLOCK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_LOC_BUSY_MASK) >> SYSCTL_CLOCK_LOC_BUSY_SHIFT)
564 
565 /*
566  * PRESERVE (RW)
567  *
568  * preserve function against global select
569  * 0: select global clock setting
570  * 1: not select global clock setting
571  */
572 #define SYSCTL_CLOCK_PRESERVE_MASK (0x10000000UL)
573 #define SYSCTL_CLOCK_PRESERVE_SHIFT (28U)
574 #define SYSCTL_CLOCK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_PRESERVE_SHIFT) & SYSCTL_CLOCK_PRESERVE_MASK)
575 #define SYSCTL_CLOCK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_PRESERVE_MASK) >> SYSCTL_CLOCK_PRESERVE_SHIFT)
576 
577 /*
578  * MUX (RW)
579  *
580  * current mux in clock component
581  * 0:osc0_clk0
582  * 1:pll0_clk0
583  * 2:pll0_clk1
584  * 3:pll1_clk0
585  * 4:pll1_clk1
586  * 5:pll1_clk2
587  * 6:pll2_clk0
588  * 7:pll2_clk1
589  */
590 #define SYSCTL_CLOCK_MUX_MASK (0x700U)
591 #define SYSCTL_CLOCK_MUX_SHIFT (8U)
592 #define SYSCTL_CLOCK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_MUX_SHIFT) & SYSCTL_CLOCK_MUX_MASK)
593 #define SYSCTL_CLOCK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_MUX_MASK) >> SYSCTL_CLOCK_MUX_SHIFT)
594 
595 /*
596  * DIV (RW)
597  *
598  * clock divider
599  * 0: divider by 1
600  * 1: divider by 2
601  * 2: divider by 3
602  * . . .
603  * 255: divider by 256
604  */
605 #define SYSCTL_CLOCK_DIV_MASK (0xFFU)
606 #define SYSCTL_CLOCK_DIV_SHIFT (0U)
607 #define SYSCTL_CLOCK_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_DIV_SHIFT) & SYSCTL_CLOCK_DIV_MASK)
608 #define SYSCTL_CLOCK_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_DIV_MASK) >> SYSCTL_CLOCK_DIV_SHIFT)
609 
610 /* Bitfield definition for register array: ADCCLK */
611 /*
612  * GLB_BUSY (RO)
613  *
614  * global busy
615  * 0: no changes pending to any clock
616  * 1: any of nodes is changing status
617  */
618 #define SYSCTL_ADCCLK_GLB_BUSY_MASK (0x80000000UL)
619 #define SYSCTL_ADCCLK_GLB_BUSY_SHIFT (31U)
620 #define SYSCTL_ADCCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_GLB_BUSY_MASK) >> SYSCTL_ADCCLK_GLB_BUSY_SHIFT)
621 
622 /*
623  * LOC_BUSY (RO)
624  *
625  * local busy
626  * 0: a change is pending for current node
627  * 1: current node is changing status
628  */
629 #define SYSCTL_ADCCLK_LOC_BUSY_MASK (0x40000000UL)
630 #define SYSCTL_ADCCLK_LOC_BUSY_SHIFT (30U)
631 #define SYSCTL_ADCCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_LOC_BUSY_MASK) >> SYSCTL_ADCCLK_LOC_BUSY_SHIFT)
632 
633 /*
634  * PRESERVE (RW)
635  *
636  * preserve function against global select
637  * 0: select global clock setting
638  * 1: not select global clock setting
639  */
640 #define SYSCTL_ADCCLK_PRESERVE_MASK (0x10000000UL)
641 #define SYSCTL_ADCCLK_PRESERVE_SHIFT (28U)
642 #define SYSCTL_ADCCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_PRESERVE_SHIFT) & SYSCTL_ADCCLK_PRESERVE_MASK)
643 #define SYSCTL_ADCCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_PRESERVE_MASK) >> SYSCTL_ADCCLK_PRESERVE_SHIFT)
644 
645 /*
646  * MUX (RW)
647  *
648  * current mux
649  * 0: ahb0 clock N
650  * 1: ana clock
651  */
652 #define SYSCTL_ADCCLK_MUX_MASK (0x100U)
653 #define SYSCTL_ADCCLK_MUX_SHIFT (8U)
654 #define SYSCTL_ADCCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_MUX_SHIFT) & SYSCTL_ADCCLK_MUX_MASK)
655 #define SYSCTL_ADCCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_MUX_MASK) >> SYSCTL_ADCCLK_MUX_SHIFT)
656 
657 /* Bitfield definition for register: GLOBAL00 */
658 /*
659  * MUX (RW)
660  *
661  * global clock override request
662  * bit0: override to preset0
663  * bit1: override to preset1
664  * bit2: override to preset2
665  * bit3: override to preset3
666  * bit4: override to preset4
667  * bit5: override to preset5
668  * bit6: override to preset6
669  * bit7: override to preset7
670  */
671 #define SYSCTL_GLOBAL00_MUX_MASK (0xFFU)
672 #define SYSCTL_GLOBAL00_MUX_SHIFT (0U)
673 #define SYSCTL_GLOBAL00_MUX_SET(x) (((uint32_t)(x) << SYSCTL_GLOBAL00_MUX_SHIFT) & SYSCTL_GLOBAL00_MUX_MASK)
674 #define SYSCTL_GLOBAL00_MUX_GET(x) (((uint32_t)(x) & SYSCTL_GLOBAL00_MUX_MASK) >> SYSCTL_GLOBAL00_MUX_SHIFT)
675 
676 /* Bitfield definition for register of struct array MONITOR: CONTROL */
677 /*
678  * VALID (RW)
679  *
680  * result is ready for read
681  * 0: not ready
682  * 1: result is ready
683  */
684 #define SYSCTL_MONITOR_CONTROL_VALID_MASK (0x80000000UL)
685 #define SYSCTL_MONITOR_CONTROL_VALID_SHIFT (31U)
686 #define SYSCTL_MONITOR_CONTROL_VALID_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_VALID_SHIFT) & SYSCTL_MONITOR_CONTROL_VALID_MASK)
687 #define SYSCTL_MONITOR_CONTROL_VALID_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_VALID_MASK) >> SYSCTL_MONITOR_CONTROL_VALID_SHIFT)
688 
689 /*
690  * DIV_BUSY (RO)
691  *
692  * divider is applying new setting
693  */
694 #define SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK (0x8000000UL)
695 #define SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT (27U)
696 #define SYSCTL_MONITOR_CONTROL_DIV_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT)
697 
698 /*
699  * OUTEN (RW)
700  *
701  * enable clock output
702  */
703 #define SYSCTL_MONITOR_CONTROL_OUTEN_MASK (0x1000000UL)
704 #define SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT (24U)
705 #define SYSCTL_MONITOR_CONTROL_OUTEN_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK)
706 #define SYSCTL_MONITOR_CONTROL_OUTEN_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK) >> SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT)
707 
708 /*
709  * DIV (RW)
710  *
711  * output divider
712  */
713 #define SYSCTL_MONITOR_CONTROL_DIV_MASK (0xFF0000UL)
714 #define SYSCTL_MONITOR_CONTROL_DIV_SHIFT (16U)
715 #define SYSCTL_MONITOR_CONTROL_DIV_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_DIV_SHIFT) & SYSCTL_MONITOR_CONTROL_DIV_MASK)
716 #define SYSCTL_MONITOR_CONTROL_DIV_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_SHIFT)
717 
718 /*
719  * HIGH (RW)
720  *
721  * clock frequency higher than upper limit
722  */
723 #define SYSCTL_MONITOR_CONTROL_HIGH_MASK (0x8000U)
724 #define SYSCTL_MONITOR_CONTROL_HIGH_SHIFT (15U)
725 #define SYSCTL_MONITOR_CONTROL_HIGH_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_HIGH_SHIFT) & SYSCTL_MONITOR_CONTROL_HIGH_MASK)
726 #define SYSCTL_MONITOR_CONTROL_HIGH_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_HIGH_MASK) >> SYSCTL_MONITOR_CONTROL_HIGH_SHIFT)
727 
728 /*
729  * LOW (RW)
730  *
731  * clock frequency lower than lower limit
732  */
733 #define SYSCTL_MONITOR_CONTROL_LOW_MASK (0x4000U)
734 #define SYSCTL_MONITOR_CONTROL_LOW_SHIFT (14U)
735 #define SYSCTL_MONITOR_CONTROL_LOW_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_LOW_SHIFT) & SYSCTL_MONITOR_CONTROL_LOW_MASK)
736 #define SYSCTL_MONITOR_CONTROL_LOW_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_LOW_MASK) >> SYSCTL_MONITOR_CONTROL_LOW_SHIFT)
737 
738 /*
739  * START (RW)
740  *
741  * start measurement
742  */
743 #define SYSCTL_MONITOR_CONTROL_START_MASK (0x1000U)
744 #define SYSCTL_MONITOR_CONTROL_START_SHIFT (12U)
745 #define SYSCTL_MONITOR_CONTROL_START_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_START_SHIFT) & SYSCTL_MONITOR_CONTROL_START_MASK)
746 #define SYSCTL_MONITOR_CONTROL_START_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_START_MASK) >> SYSCTL_MONITOR_CONTROL_START_SHIFT)
747 
748 /*
749  * MODE (RW)
750  *
751  * work mode,
752  * 0: register value will be compared to measurement
753  * 1: upper and lower value will be recordered in register
754  */
755 #define SYSCTL_MONITOR_CONTROL_MODE_MASK (0x400U)
756 #define SYSCTL_MONITOR_CONTROL_MODE_SHIFT (10U)
757 #define SYSCTL_MONITOR_CONTROL_MODE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_MODE_SHIFT) & SYSCTL_MONITOR_CONTROL_MODE_MASK)
758 #define SYSCTL_MONITOR_CONTROL_MODE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_MODE_MASK) >> SYSCTL_MONITOR_CONTROL_MODE_SHIFT)
759 
760 /*
761  * ACCURACY (RW)
762  *
763  * measurement accuracy,
764  * 0: resolution is 1kHz
765  * 1: resolution is 1Hz
766  */
767 #define SYSCTL_MONITOR_CONTROL_ACCURACY_MASK (0x200U)
768 #define SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT (9U)
769 #define SYSCTL_MONITOR_CONTROL_ACCURACY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK)
770 #define SYSCTL_MONITOR_CONTROL_ACCURACY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK) >> SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT)
771 
772 /*
773  * REFERENCE (RW)
774  *
775  * refrence clock selection,
776  * 0: 32k
777  * 1: 24M
778  */
779 #define SYSCTL_MONITOR_CONTROL_REFERENCE_MASK (0x100U)
780 #define SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT (8U)
781 #define SYSCTL_MONITOR_CONTROL_REFERENCE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK)
782 #define SYSCTL_MONITOR_CONTROL_REFERENCE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK) >> SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT)
783 
784 /*
785  * SELECTION (RW)
786  *
787  * clock measurement selection
788  */
789 #define SYSCTL_MONITOR_CONTROL_SELECTION_MASK (0xFFU)
790 #define SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT (0U)
791 #define SYSCTL_MONITOR_CONTROL_SELECTION_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK)
792 #define SYSCTL_MONITOR_CONTROL_SELECTION_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK) >> SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT)
793 
794 /* Bitfield definition for register of struct array MONITOR: CURRENT */
795 /*
796  * FREQUENCY (RO)
797  *
798  * self updating measure result
799  */
800 #define SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK (0xFFFFFFFFUL)
801 #define SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT (0U)
802 #define SYSCTL_MONITOR_CURRENT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK) >> SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT)
803 
804 /* Bitfield definition for register of struct array MONITOR: LOW_LIMIT */
805 /*
806  * FREQUENCY (RW)
807  *
808  * lower frequency
809  */
810 #define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL)
811 #define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT (0U)
812 #define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK)
813 #define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT)
814 
815 /* Bitfield definition for register of struct array MONITOR: HIGH_LIMIT */
816 /*
817  * FREQUENCY (RW)
818  *
819  * upper frequency
820  */
821 #define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL)
822 #define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT (0U)
823 #define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK)
824 #define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT)
825 
826 /* Bitfield definition for register of struct array CPU: LP */
827 /*
828  * WAKE_CNT (RW)
829  *
830  * CPU0 wake up counter, counter satuated at 255, write 0x00 to clear
831  */
832 #define SYSCTL_CPU_LP_WAKE_CNT_MASK (0xFF000000UL)
833 #define SYSCTL_CPU_LP_WAKE_CNT_SHIFT (24U)
834 #define SYSCTL_CPU_LP_WAKE_CNT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_CNT_SHIFT) & SYSCTL_CPU_LP_WAKE_CNT_MASK)
835 #define SYSCTL_CPU_LP_WAKE_CNT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_CNT_MASK) >> SYSCTL_CPU_LP_WAKE_CNT_SHIFT)
836 
837 /*
838  * HALT (RW)
839  *
840  * halt request for CPU0,
841  * 0: CPU0 will start to execute after reset or receive wakeup request
842  * 1: CPU0 will not start after reset, or wakeup after WFI
843  */
844 #define SYSCTL_CPU_LP_HALT_MASK (0x10000UL)
845 #define SYSCTL_CPU_LP_HALT_SHIFT (16U)
846 #define SYSCTL_CPU_LP_HALT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_HALT_SHIFT) & SYSCTL_CPU_LP_HALT_MASK)
847 #define SYSCTL_CPU_LP_HALT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_HALT_MASK) >> SYSCTL_CPU_LP_HALT_SHIFT)
848 
849 /*
850  * WAKE (RO)
851  *
852  * CPU0 is waking up
853  * 0: CPU0 wake up not asserted
854  * 1: CPU0 wake up asserted
855  */
856 #define SYSCTL_CPU_LP_WAKE_MASK (0x2000U)
857 #define SYSCTL_CPU_LP_WAKE_SHIFT (13U)
858 #define SYSCTL_CPU_LP_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_MASK) >> SYSCTL_CPU_LP_WAKE_SHIFT)
859 
860 /*
861  * EXEC (RO)
862  *
863  * CPU0 is executing
864  * 0: CPU0 is not executing
865  * 1: CPU0 is executing
866  */
867 #define SYSCTL_CPU_LP_EXEC_MASK (0x1000U)
868 #define SYSCTL_CPU_LP_EXEC_SHIFT (12U)
869 #define SYSCTL_CPU_LP_EXEC_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_EXEC_MASK) >> SYSCTL_CPU_LP_EXEC_SHIFT)
870 
871 /*
872  * WAKE_FLAG (RW)
873  *
874  * CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit
875  * 0: CPU0 wakeup not happened
876  * 1: CPU0 wake up happened
877  */
878 #define SYSCTL_CPU_LP_WAKE_FLAG_MASK (0x400U)
879 #define SYSCTL_CPU_LP_WAKE_FLAG_SHIFT (10U)
880 #define SYSCTL_CPU_LP_WAKE_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_FLAG_SHIFT) & SYSCTL_CPU_LP_WAKE_FLAG_MASK)
881 #define SYSCTL_CPU_LP_WAKE_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_FLAG_MASK) >> SYSCTL_CPU_LP_WAKE_FLAG_SHIFT)
882 
883 /*
884  * SLEEP_FLAG (RW)
885  *
886  * CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit
887  * 0: CPU0 sleep not happened
888  * 1: CPU0 sleep happened
889  */
890 #define SYSCTL_CPU_LP_SLEEP_FLAG_MASK (0x200U)
891 #define SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT (9U)
892 #define SYSCTL_CPU_LP_SLEEP_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK)
893 #define SYSCTL_CPU_LP_SLEEP_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK) >> SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT)
894 
895 /*
896  * RESET_FLAG (RW)
897  *
898  * CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit
899  * 0: CPU0 reset not happened
900  * 1: CPU0 reset happened
901  */
902 #define SYSCTL_CPU_LP_RESET_FLAG_MASK (0x100U)
903 #define SYSCTL_CPU_LP_RESET_FLAG_SHIFT (8U)
904 #define SYSCTL_CPU_LP_RESET_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_RESET_FLAG_SHIFT) & SYSCTL_CPU_LP_RESET_FLAG_MASK)
905 #define SYSCTL_CPU_LP_RESET_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_RESET_FLAG_MASK) >> SYSCTL_CPU_LP_RESET_FLAG_SHIFT)
906 
907 /*
908  * MODE (RW)
909  *
910  * Low power mode, system behavior after WFI
911  * 00: CPU clock stop after WFI
912  * 01: System enter low power mode after WFI
913  * 10: Keep running after WFI
914  * 11: reserved
915  */
916 #define SYSCTL_CPU_LP_MODE_MASK (0x3U)
917 #define SYSCTL_CPU_LP_MODE_SHIFT (0U)
918 #define SYSCTL_CPU_LP_MODE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_MODE_SHIFT) & SYSCTL_CPU_LP_MODE_MASK)
919 #define SYSCTL_CPU_LP_MODE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_MODE_MASK) >> SYSCTL_CPU_LP_MODE_SHIFT)
920 
921 /* Bitfield definition for register of struct array CPU: LOCK */
922 /*
923  * GPR (RW)
924  *
925  * Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset
926  */
927 #define SYSCTL_CPU_LOCK_GPR_MASK (0xFFFCU)
928 #define SYSCTL_CPU_LOCK_GPR_SHIFT (2U)
929 #define SYSCTL_CPU_LOCK_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_GPR_SHIFT) & SYSCTL_CPU_LOCK_GPR_MASK)
930 #define SYSCTL_CPU_LOCK_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_GPR_MASK) >> SYSCTL_CPU_LOCK_GPR_SHIFT)
931 
932 /*
933  * LOCK (RW)
934  *
935  * Lock bit for CPU_LOCK
936  */
937 #define SYSCTL_CPU_LOCK_LOCK_MASK (0x2U)
938 #define SYSCTL_CPU_LOCK_LOCK_SHIFT (1U)
939 #define SYSCTL_CPU_LOCK_LOCK_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_LOCK_SHIFT) & SYSCTL_CPU_LOCK_LOCK_MASK)
940 #define SYSCTL_CPU_LOCK_LOCK_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_LOCK_MASK) >> SYSCTL_CPU_LOCK_LOCK_SHIFT)
941 
942 /* Bitfield definition for register of struct array CPU: GPR0 */
943 /*
944  * GPR (RW)
945  *
946  * register for software to handle resume, can save resume address or status
947  */
948 #define SYSCTL_CPU_GPR_GPR_MASK (0xFFFFFFFFUL)
949 #define SYSCTL_CPU_GPR_GPR_SHIFT (0U)
950 #define SYSCTL_CPU_GPR_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_GPR_GPR_SHIFT) & SYSCTL_CPU_GPR_GPR_MASK)
951 #define SYSCTL_CPU_GPR_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_GPR_GPR_MASK) >> SYSCTL_CPU_GPR_GPR_SHIFT)
952 
953 /* Bitfield definition for register of struct array CPU: STATUS0 */
954 /*
955  * STATUS (RO)
956  *
957  * IRQ values
958  */
959 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK (0xFFFFFFFFUL)
960 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT (0U)
961 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK) >> SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT)
962 
963 /* Bitfield definition for register of struct array CPU: ENABLE0 */
964 /*
965  * ENABLE (RW)
966  *
967  * IRQ wakeup enable
968  */
969 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK (0xFFFFFFFFUL)
970 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT (0U)
971 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK)
972 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK) >> SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT)
973 
974 
975 
976 /* RESOURCE register group index macro definition */
977 #define SYSCTL_RESOURCE_CPU0 (0UL)
978 #define SYSCTL_RESOURCE_CPX0 (1UL)
979 #define SYSCTL_RESOURCE_PMIC (20UL)
980 #define SYSCTL_RESOURCE_POW_CPU0 (21UL)
981 #define SYSCTL_RESOURCE_RST_SOC (23UL)
982 #define SYSCTL_RESOURCE_RST_CPU0 (24UL)
983 #define SYSCTL_RESOURCE_CLK_SRC_XTAL (32UL)
984 #define SYSCTL_RESOURCE_CLK_SRC_PLL0 (33UL)
985 #define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL0 (34UL)
986 #define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL0 (35UL)
987 #define SYSCTL_RESOURCE_CLK_SRC_PLL1 (36UL)
988 #define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL1 (37UL)
989 #define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL1 (38UL)
990 #define SYSCTL_RESOURCE_CLK_SRC_CLK2_PLL1 (39UL)
991 #define SYSCTL_RESOURCE_CLK_SRC_PLL2 (40UL)
992 #define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL2 (41UL)
993 #define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL2 (42UL)
994 #define SYSCTL_RESOURCE_CLK_SRC_PLL0_REF (43UL)
995 #define SYSCTL_RESOURCE_CLK_SRC_PLL1_REF (44UL)
996 #define SYSCTL_RESOURCE_CLK_SRC_PLL2_REF (45UL)
997 #define SYSCTL_RESOURCE_CLK_TOP_CPU0 (64UL)
998 #define SYSCTL_RESOURCE_CLK_TOP_MCT0 (65UL)
999 #define SYSCTL_RESOURCE_CLK_TOP_AHB0 (66UL)
1000 #define SYSCTL_RESOURCE_CLK_TOP_AXIF (67UL)
1001 #define SYSCTL_RESOURCE_CLK_TOP_AXIS (68UL)
1002 #define SYSCTL_RESOURCE_CLK_TOP_AXIC (69UL)
1003 #define SYSCTL_RESOURCE_CLK_TOP_TMR0 (70UL)
1004 #define SYSCTL_RESOURCE_CLK_TOP_TMR1 (71UL)
1005 #define SYSCTL_RESOURCE_CLK_TOP_TMR2 (72UL)
1006 #define SYSCTL_RESOURCE_CLK_TOP_TMR3 (73UL)
1007 #define SYSCTL_RESOURCE_CLK_TOP_OWR0 (74UL)
1008 #define SYSCTL_RESOURCE_CLK_TOP_OWR1 (75UL)
1009 #define SYSCTL_RESOURCE_CLK_TOP_I2C0 (76UL)
1010 #define SYSCTL_RESOURCE_CLK_TOP_I2C1 (77UL)
1011 #define SYSCTL_RESOURCE_CLK_TOP_I2C2 (78UL)
1012 #define SYSCTL_RESOURCE_CLK_TOP_I2C3 (79UL)
1013 #define SYSCTL_RESOURCE_CLK_TOP_SPI0 (80UL)
1014 #define SYSCTL_RESOURCE_CLK_TOP_SPI1 (81UL)
1015 #define SYSCTL_RESOURCE_CLK_TOP_SPI2 (82UL)
1016 #define SYSCTL_RESOURCE_CLK_TOP_SPI3 (83UL)
1017 #define SYSCTL_RESOURCE_CLK_TOP_URT0 (84UL)
1018 #define SYSCTL_RESOURCE_CLK_TOP_URT1 (85UL)
1019 #define SYSCTL_RESOURCE_CLK_TOP_URT2 (86UL)
1020 #define SYSCTL_RESOURCE_CLK_TOP_URT3 (87UL)
1021 #define SYSCTL_RESOURCE_CLK_TOP_URT4 (88UL)
1022 #define SYSCTL_RESOURCE_CLK_TOP_URT5 (89UL)
1023 #define SYSCTL_RESOURCE_CLK_TOP_URT6 (90UL)
1024 #define SYSCTL_RESOURCE_CLK_TOP_URT7 (91UL)
1025 #define SYSCTL_RESOURCE_CLK_TOP_CAN0 (92UL)
1026 #define SYSCTL_RESOURCE_CLK_TOP_CAN1 (93UL)
1027 #define SYSCTL_RESOURCE_CLK_TOP_CAN2 (94UL)
1028 #define SYSCTL_RESOURCE_CLK_TOP_CAN3 (95UL)
1029 #define SYSCTL_RESOURCE_CLK_TOP_XPI0 (96UL)
1030 #define SYSCTL_RESOURCE_CLK_TOP_ESC0 (97UL)
1031 #define SYSCTL_RESOURCE_CLK_TOP_ETH0 (98UL)
1032 #define SYSCTL_RESOURCE_CLK_TOP_PTP0 (99UL)
1033 #define SYSCTL_RESOURCE_CLK_TOP_REF0 (100UL)
1034 #define SYSCTL_RESOURCE_CLK_TOP_REF1 (101UL)
1035 #define SYSCTL_RESOURCE_CLK_TOP_NTM0 (102UL)
1036 #define SYSCTL_RESOURCE_CLK_TOP_ANA0 (103UL)
1037 #define SYSCTL_RESOURCE_CLK_TOP_ANA1 (104UL)
1038 #define SYSCTL_RESOURCE_CLK_TOP_ADC0 (105UL)
1039 #define SYSCTL_RESOURCE_CLK_TOP_ADC1 (106UL)
1040 #define SYSCTL_RESOURCE_AHBP (256UL)
1041 #define SYSCTL_RESOURCE_AXIS (257UL)
1042 #define SYSCTL_RESOURCE_AXIC (258UL)
1043 #define SYSCTL_RESOURCE_ROM0 (259UL)
1044 #define SYSCTL_RESOURCE_LMM0 (260UL)
1045 #define SYSCTL_RESOURCE_MCT0 (261UL)
1046 #define SYSCTL_RESOURCE_TMR0 (262UL)
1047 #define SYSCTL_RESOURCE_TMR1 (263UL)
1048 #define SYSCTL_RESOURCE_TMR2 (264UL)
1049 #define SYSCTL_RESOURCE_TMR3 (265UL)
1050 #define SYSCTL_RESOURCE_OWR0 (266UL)
1051 #define SYSCTL_RESOURCE_OWR1 (267UL)
1052 #define SYSCTL_RESOURCE_EUI0 (268UL)
1053 #define SYSCTL_RESOURCE_EUI1 (269UL)
1054 #define SYSCTL_RESOURCE_I2C0 (270UL)
1055 #define SYSCTL_RESOURCE_I2C1 (271UL)
1056 #define SYSCTL_RESOURCE_I2C2 (272UL)
1057 #define SYSCTL_RESOURCE_I2C3 (273UL)
1058 #define SYSCTL_RESOURCE_SPI0 (274UL)
1059 #define SYSCTL_RESOURCE_SPI1 (275UL)
1060 #define SYSCTL_RESOURCE_SPI2 (276UL)
1061 #define SYSCTL_RESOURCE_SPI3 (277UL)
1062 #define SYSCTL_RESOURCE_URT0 (278UL)
1063 #define SYSCTL_RESOURCE_URT1 (279UL)
1064 #define SYSCTL_RESOURCE_URT2 (280UL)
1065 #define SYSCTL_RESOURCE_URT3 (281UL)
1066 #define SYSCTL_RESOURCE_URT4 (282UL)
1067 #define SYSCTL_RESOURCE_URT5 (283UL)
1068 #define SYSCTL_RESOURCE_URT6 (284UL)
1069 #define SYSCTL_RESOURCE_URT7 (285UL)
1070 #define SYSCTL_RESOURCE_CRC0 (286UL)
1071 #define SYSCTL_RESOURCE_TSNS (287UL)
1072 #define SYSCTL_RESOURCE_WDG0 (288UL)
1073 #define SYSCTL_RESOURCE_WDG1 (289UL)
1074 #define SYSCTL_RESOURCE_MBX0 (290UL)
1075 #define SYSCTL_RESOURCE_GPIO (291UL)
1076 #define SYSCTL_RESOURCE_PPI0 (292UL)
1077 #define SYSCTL_RESOURCE_HDMA (293UL)
1078 #define SYSCTL_RESOURCE_LOBS (294UL)
1079 #define SYSCTL_RESOURCE_ADC0 (295UL)
1080 #define SYSCTL_RESOURCE_ADC1 (296UL)
1081 #define SYSCTL_RESOURCE_CMP0 (297UL)
1082 #define SYSCTL_RESOURCE_CAN0 (298UL)
1083 #define SYSCTL_RESOURCE_CAN1 (299UL)
1084 #define SYSCTL_RESOURCE_CAN2 (300UL)
1085 #define SYSCTL_RESOURCE_CAN3 (301UL)
1086 #define SYSCTL_RESOURCE_PTPC (302UL)
1087 #define SYSCTL_RESOURCE_QEI0 (303UL)
1088 #define SYSCTL_RESOURCE_QEI1 (304UL)
1089 #define SYSCTL_RESOURCE_QEO0 (305UL)
1090 #define SYSCTL_RESOURCE_QEO1 (306UL)
1091 #define SYSCTL_RESOURCE_SDM0 (307UL)
1092 #define SYSCTL_RESOURCE_PLB0 (308UL)
1093 #define SYSCTL_RESOURCE_PWM0 (309UL)
1094 #define SYSCTL_RESOURCE_PWM1 (310UL)
1095 #define SYSCTL_RESOURCE_EMDS (311UL)
1096 #define SYSCTL_RESOURCE_XPI0 (312UL)
1097 #define SYSCTL_RESOURCE_RAM0 (313UL)
1098 #define SYSCTL_RESOURCE_XDMA (314UL)
1099 #define SYSCTL_RESOURCE_ESC0 (315UL)
1100 #define SYSCTL_RESOURCE_ETH0 (316UL)
1101 #define SYSCTL_RESOURCE_USB0 (317UL)
1102 #define SYSCTL_RESOURCE_NTM0 (318UL)
1103 #define SYSCTL_RESOURCE_REF0 (319UL)
1104 #define SYSCTL_RESOURCE_REF1 (320UL)
1105 
1106 /* GROUP0 register group index macro definition */
1107 #define SYSCTL_GROUP0_LINK0 (0UL)
1108 #define SYSCTL_GROUP0_LINK1 (1UL)
1109 #define SYSCTL_GROUP0_LINK2 (2UL)
1110 #define SYSCTL_GROUP0_LINK3 (3UL)
1111 
1112 /* GROUP1 register group index macro definition */
1113 #define SYSCTL_GROUP1_LINK0 (0UL)
1114 #define SYSCTL_GROUP1_LINK1 (1UL)
1115 #define SYSCTL_GROUP1_LINK2 (2UL)
1116 #define SYSCTL_GROUP1_LINK3 (3UL)
1117 
1118 /* AFFILIATE register group index macro definition */
1119 #define SYSCTL_AFFILIATE_CPU0 (0UL)
1120 
1121 /* RETENTION register group index macro definition */
1122 #define SYSCTL_RETENTION_CPU0 (0UL)
1123 
1124 /* POWER register group index macro definition */
1125 #define SYSCTL_POWER_CPU0 (0UL)
1126 
1127 /* RESET register group index macro definition */
1128 #define SYSCTL_RESET_SOC (0UL)
1129 #define SYSCTL_RESET_CPU0 (1UL)
1130 
1131 /* CLOCK register group index macro definition */
1132 #define SYSCTL_CLOCK_CLK_TOP_CPU0 (0UL)
1133 #define SYSCTL_CLOCK_CLK_TOP_MCT0 (1UL)
1134 #define SYSCTL_CLOCK_CLK_TOP_AHB0 (2UL)
1135 #define SYSCTL_CLOCK_CLK_TOP_AXIF (3UL)
1136 #define SYSCTL_CLOCK_CLK_TOP_AXIS (4UL)
1137 #define SYSCTL_CLOCK_CLK_TOP_AXIC (5UL)
1138 #define SYSCTL_CLOCK_CLK_TOP_TMR0 (6UL)
1139 #define SYSCTL_CLOCK_CLK_TOP_TMR1 (7UL)
1140 #define SYSCTL_CLOCK_CLK_TOP_TMR2 (8UL)
1141 #define SYSCTL_CLOCK_CLK_TOP_TMR3 (9UL)
1142 #define SYSCTL_CLOCK_CLK_TOP_OWR0 (10UL)
1143 #define SYSCTL_CLOCK_CLK_TOP_OWR1 (11UL)
1144 #define SYSCTL_CLOCK_CLK_TOP_I2C0 (12UL)
1145 #define SYSCTL_CLOCK_CLK_TOP_I2C1 (13UL)
1146 #define SYSCTL_CLOCK_CLK_TOP_I2C2 (14UL)
1147 #define SYSCTL_CLOCK_CLK_TOP_I2C3 (15UL)
1148 #define SYSCTL_CLOCK_CLK_TOP_SPI0 (16UL)
1149 #define SYSCTL_CLOCK_CLK_TOP_SPI1 (17UL)
1150 #define SYSCTL_CLOCK_CLK_TOP_SPI2 (18UL)
1151 #define SYSCTL_CLOCK_CLK_TOP_SPI3 (19UL)
1152 #define SYSCTL_CLOCK_CLK_TOP_URT0 (20UL)
1153 #define SYSCTL_CLOCK_CLK_TOP_URT1 (21UL)
1154 #define SYSCTL_CLOCK_CLK_TOP_URT2 (22UL)
1155 #define SYSCTL_CLOCK_CLK_TOP_URT3 (23UL)
1156 #define SYSCTL_CLOCK_CLK_TOP_URT4 (24UL)
1157 #define SYSCTL_CLOCK_CLK_TOP_URT5 (25UL)
1158 #define SYSCTL_CLOCK_CLK_TOP_URT6 (26UL)
1159 #define SYSCTL_CLOCK_CLK_TOP_URT7 (27UL)
1160 #define SYSCTL_CLOCK_CLK_TOP_CAN0 (28UL)
1161 #define SYSCTL_CLOCK_CLK_TOP_CAN1 (29UL)
1162 #define SYSCTL_CLOCK_CLK_TOP_CAN2 (30UL)
1163 #define SYSCTL_CLOCK_CLK_TOP_CAN3 (31UL)
1164 #define SYSCTL_CLOCK_CLK_TOP_XPI0 (32UL)
1165 #define SYSCTL_CLOCK_CLK_TOP_ESC0 (33UL)
1166 #define SYSCTL_CLOCK_CLK_TOP_ETH0 (34UL)
1167 #define SYSCTL_CLOCK_CLK_TOP_PTP0 (35UL)
1168 #define SYSCTL_CLOCK_CLK_TOP_REF0 (36UL)
1169 #define SYSCTL_CLOCK_CLK_TOP_REF1 (37UL)
1170 #define SYSCTL_CLOCK_CLK_TOP_NTM0 (38UL)
1171 #define SYSCTL_CLOCK_CLK_TOP_ANA0 (39UL)
1172 #define SYSCTL_CLOCK_CLK_TOP_ANA1 (40UL)
1173 
1174 /* ADCCLK register group index macro definition */
1175 #define SYSCTL_ADCCLK_CLK_TOP_ADC0 (0UL)
1176 #define SYSCTL_ADCCLK_CLK_TOP_ADC1 (1UL)
1177 
1178 /* MONITOR register group index macro definition */
1179 #define SYSCTL_MONITOR_SLICE0 (0UL)
1180 #define SYSCTL_MONITOR_SLICE1 (1UL)
1181 #define SYSCTL_MONITOR_SLICE2 (2UL)
1182 #define SYSCTL_MONITOR_SLICE3 (3UL)
1183 
1184 /* GPR register group index macro definition */
1185 #define SYSCTL_CPU_GPR_GPR0 (0UL)
1186 #define SYSCTL_CPU_GPR_GPR1 (1UL)
1187 #define SYSCTL_CPU_GPR_GPR2 (2UL)
1188 #define SYSCTL_CPU_GPR_GPR3 (3UL)
1189 #define SYSCTL_CPU_GPR_GPR4 (4UL)
1190 #define SYSCTL_CPU_GPR_GPR5 (5UL)
1191 #define SYSCTL_CPU_GPR_GPR6 (6UL)
1192 #define SYSCTL_CPU_GPR_GPR7 (7UL)
1193 #define SYSCTL_CPU_GPR_GPR8 (8UL)
1194 #define SYSCTL_CPU_GPR_GPR9 (9UL)
1195 #define SYSCTL_CPU_GPR_GPR10 (10UL)
1196 #define SYSCTL_CPU_GPR_GPR11 (11UL)
1197 #define SYSCTL_CPU_GPR_GPR12 (12UL)
1198 #define SYSCTL_CPU_GPR_GPR13 (13UL)
1199 
1200 /* WAKEUP_STATUS register group index macro definition */
1201 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS0 (0UL)
1202 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS1 (1UL)
1203 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS2 (2UL)
1204 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS3 (3UL)
1205 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS4 (4UL)
1206 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS5 (5UL)
1207 
1208 /* WAKEUP_ENABLE register group index macro definition */
1209 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE0 (0UL)
1210 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE1 (1UL)
1211 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE2 (2UL)
1212 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE3 (3UL)
1213 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE4 (4UL)
1214 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE5 (5UL)
1215 
1216 /* CPU register group index macro definition */
1217 #define SYSCTL_CPU_CPU0 (0UL)
1218 
1219 
1220 #endif /* HPM_SYSCTL_H */
SYSCTL_Type
Definition: hpm_sysctl_regs.h:12