latest/api_doc/HPM5E00_2ip_2hpm__trgm__regs_8h_source.html

 /*

  * Copyright (c) 2021-2025 HPMicro

  *

  * SPDX-License-Identifier: BSD-3-Clause

  *

  */


 #ifndef HPM_TRGM_H

 #define HPM_TRGM_H


 typedef struct {

     __RW uint32_t FILTCFG[32];                 /* 0x0 - 0x7C: Filter configure register */

     __R  uint8_t  RESERVED0[896];              /* 0x80 - 0x3FF: Reserved */

     __RW uint32_t DMACFG[8];                   /* 0x400 - 0x41C: DMA request configure register */

     __R  uint8_t  RESERVED1[224];              /* 0x420 - 0x4FF: Reserved */

     __RW uint32_t GCR;                         /* 0x500:  */

     __R  uint8_t  RESERVED2[60];               /* 0x504 - 0x53F: Reserved */

     __RW uint32_t ADC_MATRIX_SEL0;             /* 0x540: adc matrix select register0 */

     __R  uint8_t  RESERVED3[60];               /* 0x544 - 0x57F: Reserved */

     __RW uint32_t DAC_MATRIX_SEL0;             /* 0x580: dac matrix select register0 */

     __RW uint32_t DAC_MATRIX_SEL1;             /* 0x584: dac matrix select register1 */

     __RW uint32_t DAC_MATRIX_SEL2;             /* 0x588: dac matrix select register2 */

     __R  uint8_t  RESERVED4[52];               /* 0x58C - 0x5BF: Reserved */

     __RW uint32_t POS_MATRIX_SEL0;             /* 0x5C0: position matrix select register0 */

     __R  uint8_t  RESERVED5[60];               /* 0x5C4 - 0x5FF: Reserved */

     __R  uint32_t TRGM_IN[5];                  /* 0x600 - 0x610: trigmux input read register0 */

     __R  uint8_t  RESERVED6[108];              /* 0x614 - 0x67F: Reserved */

     __R  uint32_t TRGM_OUT[5];                 /* 0x680 - 0x690: trigmux output read register0 */

     __R  uint8_t  RESERVED7[364];              /* 0x694 - 0x7FF: Reserved */

     __RW uint32_t PWM_DELAY_CFG;               /* 0x800: pwm delay chain config register */

     __RW uint32_t PWM_CALIB_CFG;               /* 0x804: pwm delay chain calibration control register */

     __R  uint8_t  RESERVED8[2040];             /* 0x808 - 0xFFF: Reserved */

     __RW uint32_t TRGOCFG[159];                /* 0x1000 - 0x1278: Trigger manager output configure register */

 } TRGM_Type;


 /* Bitfield definition for register array: FILTCFG */

 /*

  * OUTINV (RW)

  *

  * 1- Filter will invert the output

  * 0- Filter will not invert the output

  */

 #define TRGM_FILTCFG_OUTINV_MASK (0x10000UL)

 #define TRGM_FILTCFG_OUTINV_SHIFT (16U)

 #define TRGM_FILTCFG_OUTINV_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_OUTINV_SHIFT) & TRGM_FILTCFG_OUTINV_MASK)

 #define TRGM_FILTCFG_OUTINV_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_OUTINV_MASK) >> TRGM_FILTCFG_OUTINV_SHIFT)


 /*

  * MODE (RW)

  *

  * This bitfields defines the filter mode

  * 000-bypass;

  * 100-rapid change mode;

  * 101-delay filter mode;

  * 110-stalbe low mode;

  * 111-stable high mode

  */

 #define TRGM_FILTCFG_MODE_MASK (0xE000U)

 #define TRGM_FILTCFG_MODE_SHIFT (13U)

 #define TRGM_FILTCFG_MODE_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_MODE_SHIFT) & TRGM_FILTCFG_MODE_MASK)

 #define TRGM_FILTCFG_MODE_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_MODE_MASK) >> TRGM_FILTCFG_MODE_SHIFT)


 /*

  * SYNCEN (RW)

  *

  * set to enable sychronization input signal with TRGM clock

  */

 #define TRGM_FILTCFG_SYNCEN_MASK (0x1000U)

 #define TRGM_FILTCFG_SYNCEN_SHIFT (12U)

 #define TRGM_FILTCFG_SYNCEN_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_SYNCEN_SHIFT) & TRGM_FILTCFG_SYNCEN_MASK)

 #define TRGM_FILTCFG_SYNCEN_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_SYNCEN_MASK) >> TRGM_FILTCFG_SYNCEN_SHIFT)


 /*

  * FILTLEN_SHIFT (RW)

  *

  */

 #define TRGM_FILTCFG_FILTLEN_SHIFT_MASK (0xE00U)

 #define TRGM_FILTCFG_FILTLEN_SHIFT_SHIFT (9U)

 #define TRGM_FILTCFG_FILTLEN_SHIFT_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_FILTLEN_SHIFT_SHIFT) & TRGM_FILTCFG_FILTLEN_SHIFT_MASK)

 #define TRGM_FILTCFG_FILTLEN_SHIFT_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_FILTLEN_SHIFT_MASK) >> TRGM_FILTCFG_FILTLEN_SHIFT_SHIFT)


 /*

  * FILTLEN_BASE (RW)

  *

  * This bitfields defines the filter counter length.

  */

 #define TRGM_FILTCFG_FILTLEN_BASE_MASK (0x1FFU)

 #define TRGM_FILTCFG_FILTLEN_BASE_SHIFT (0U)

 #define TRGM_FILTCFG_FILTLEN_BASE_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_FILTLEN_BASE_SHIFT) & TRGM_FILTCFG_FILTLEN_BASE_MASK)

 #define TRGM_FILTCFG_FILTLEN_BASE_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_FILTLEN_BASE_MASK) >> TRGM_FILTCFG_FILTLEN_BASE_SHIFT)


 /* Bitfield definition for register array: DMACFG */

 /*

  * DMAMUX_EN (RW)

  *

  */

 #define TRGM_DMACFG_DMAMUX_EN_MASK (0x80000000UL)

 #define TRGM_DMACFG_DMAMUX_EN_SHIFT (31U)

 #define TRGM_DMACFG_DMAMUX_EN_SET(x) (((uint32_t)(x) << TRGM_DMACFG_DMAMUX_EN_SHIFT) & TRGM_DMACFG_DMAMUX_EN_MASK)

 #define TRGM_DMACFG_DMAMUX_EN_GET(x) (((uint32_t)(x) & TRGM_DMACFG_DMAMUX_EN_MASK) >> TRGM_DMACFG_DMAMUX_EN_SHIFT)


 /*

  * DMASRCSEL (RW)

  *

  */

 #define TRGM_DMACFG_DMASRCSEL_MASK (0x3FU)

 #define TRGM_DMACFG_DMASRCSEL_SHIFT (0U)

 #define TRGM_DMACFG_DMASRCSEL_SET(x) (((uint32_t)(x) << TRGM_DMACFG_DMASRCSEL_SHIFT) & TRGM_DMACFG_DMASRCSEL_MASK)

 #define TRGM_DMACFG_DMASRCSEL_GET(x) (((uint32_t)(x) & TRGM_DMACFG_DMASRCSEL_MASK) >> TRGM_DMACFG_DMASRCSEL_SHIFT)


 /* Bitfield definition for register: GCR */

 /*

  * TRGOPEN (RW)

  *

  */

 #define TRGM_GCR_TRGOPEN_MASK (0xFFFFFFFFUL)

 #define TRGM_GCR_TRGOPEN_SHIFT (0U)

 #define TRGM_GCR_TRGOPEN_SET(x) (((uint32_t)(x) << TRGM_GCR_TRGOPEN_SHIFT) & TRGM_GCR_TRGOPEN_MASK)

 #define TRGM_GCR_TRGOPEN_GET(x) (((uint32_t)(x) & TRGM_GCR_TRGOPEN_MASK) >> TRGM_GCR_TRGOPEN_SHIFT)


 /* Bitfield definition for register: ADC_MATRIX_SEL0 */

 /*

  * QEI1_ADC1_SEL (RW)

  *

  */

 #define TRGM_ADC_MATRIX_SEL0_QEI1_ADC1_SEL_MASK (0xFF000000UL)

 #define TRGM_ADC_MATRIX_SEL0_QEI1_ADC1_SEL_SHIFT (24U)

 #define TRGM_ADC_MATRIX_SEL0_QEI1_ADC1_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL0_QEI1_ADC1_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL0_QEI1_ADC1_SEL_MASK)

 #define TRGM_ADC_MATRIX_SEL0_QEI1_ADC1_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL0_QEI1_ADC1_SEL_MASK) >> TRGM_ADC_MATRIX_SEL0_QEI1_ADC1_SEL_SHIFT)


 /*

  * QEI1_ADC0_SEL (RW)

  *

  */

 #define TRGM_ADC_MATRIX_SEL0_QEI1_ADC0_SEL_MASK (0xFF0000UL)

 #define TRGM_ADC_MATRIX_SEL0_QEI1_ADC0_SEL_SHIFT (16U)

 #define TRGM_ADC_MATRIX_SEL0_QEI1_ADC0_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL0_QEI1_ADC0_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL0_QEI1_ADC0_SEL_MASK)

 #define TRGM_ADC_MATRIX_SEL0_QEI1_ADC0_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL0_QEI1_ADC0_SEL_MASK) >> TRGM_ADC_MATRIX_SEL0_QEI1_ADC0_SEL_SHIFT)


 /*

  * QEI0_ADC1_SEL (RW)

  *

  */

 #define TRGM_ADC_MATRIX_SEL0_QEI0_ADC1_SEL_MASK (0xFF00U)

 #define TRGM_ADC_MATRIX_SEL0_QEI0_ADC1_SEL_SHIFT (8U)

 #define TRGM_ADC_MATRIX_SEL0_QEI0_ADC1_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL0_QEI0_ADC1_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL0_QEI0_ADC1_SEL_MASK)

 #define TRGM_ADC_MATRIX_SEL0_QEI0_ADC1_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL0_QEI0_ADC1_SEL_MASK) >> TRGM_ADC_MATRIX_SEL0_QEI0_ADC1_SEL_SHIFT)


 /*

  * QEI0_ADC0_SEL (RW)

  *

  */

 #define TRGM_ADC_MATRIX_SEL0_QEI0_ADC0_SEL_MASK (0xFFU)

 #define TRGM_ADC_MATRIX_SEL0_QEI0_ADC0_SEL_SHIFT (0U)

 #define TRGM_ADC_MATRIX_SEL0_QEI0_ADC0_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL0_QEI0_ADC0_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL0_QEI0_ADC0_SEL_MASK)

 #define TRGM_ADC_MATRIX_SEL0_QEI0_ADC0_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL0_QEI0_ADC0_SEL_MASK) >> TRGM_ADC_MATRIX_SEL0_QEI0_ADC0_SEL_SHIFT)


 /* Bitfield definition for register: DAC_MATRIX_SEL0 */

 /*

  * PWM0_DAC1_SEL (RW)

  *

  */

 #define TRGM_DAC_MATRIX_SEL0_PWM0_DAC1_SEL_MASK (0xFF000000UL)

 #define TRGM_DAC_MATRIX_SEL0_PWM0_DAC1_SEL_SHIFT (24U)

 #define TRGM_DAC_MATRIX_SEL0_PWM0_DAC1_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL0_PWM0_DAC1_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL0_PWM0_DAC1_SEL_MASK)

 #define TRGM_DAC_MATRIX_SEL0_PWM0_DAC1_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL0_PWM0_DAC1_SEL_MASK) >> TRGM_DAC_MATRIX_SEL0_PWM0_DAC1_SEL_SHIFT)


 /*

  * PWM0_DAC0_SEL (RW)

  *

  */

 #define TRGM_DAC_MATRIX_SEL0_PWM0_DAC0_SEL_MASK (0xFF0000UL)

 #define TRGM_DAC_MATRIX_SEL0_PWM0_DAC0_SEL_SHIFT (16U)

 #define TRGM_DAC_MATRIX_SEL0_PWM0_DAC0_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL0_PWM0_DAC0_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL0_PWM0_DAC0_SEL_MASK)

 #define TRGM_DAC_MATRIX_SEL0_PWM0_DAC0_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL0_PWM0_DAC0_SEL_MASK) >> TRGM_DAC_MATRIX_SEL0_PWM0_DAC0_SEL_SHIFT)


 /*

  * ACMP0_CH1_DAC_SEL (RW)

  *

  */

 #define TRGM_DAC_MATRIX_SEL0_ACMP0_CH1_DAC_SEL_MASK (0xFF00U)

 #define TRGM_DAC_MATRIX_SEL0_ACMP0_CH1_DAC_SEL_SHIFT (8U)

 #define TRGM_DAC_MATRIX_SEL0_ACMP0_CH1_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL0_ACMP0_CH1_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL0_ACMP0_CH1_DAC_SEL_MASK)

 #define TRGM_DAC_MATRIX_SEL0_ACMP0_CH1_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL0_ACMP0_CH1_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL0_ACMP0_CH1_DAC_SEL_SHIFT)


 /*

  * ACMP0_CH0_DAC_SEL (RW)

  *

  */

 #define TRGM_DAC_MATRIX_SEL0_ACMP0_CH0_DAC_SEL_MASK (0xFFU)

 #define TRGM_DAC_MATRIX_SEL0_ACMP0_CH0_DAC_SEL_SHIFT (0U)

 #define TRGM_DAC_MATRIX_SEL0_ACMP0_CH0_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL0_ACMP0_CH0_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL0_ACMP0_CH0_DAC_SEL_MASK)

 #define TRGM_DAC_MATRIX_SEL0_ACMP0_CH0_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL0_ACMP0_CH0_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL0_ACMP0_CH0_DAC_SEL_SHIFT)


 /* Bitfield definition for register: DAC_MATRIX_SEL1 */

 /*

  * PWM1_DAC1_SEL (RW)

  *

  */

 #define TRGM_DAC_MATRIX_SEL1_PWM1_DAC1_SEL_MASK (0xFF000000UL)

 #define TRGM_DAC_MATRIX_SEL1_PWM1_DAC1_SEL_SHIFT (24U)

 #define TRGM_DAC_MATRIX_SEL1_PWM1_DAC1_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL1_PWM1_DAC1_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL1_PWM1_DAC1_SEL_MASK)

 #define TRGM_DAC_MATRIX_SEL1_PWM1_DAC1_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL1_PWM1_DAC1_SEL_MASK) >> TRGM_DAC_MATRIX_SEL1_PWM1_DAC1_SEL_SHIFT)


 /*

  * PWM1_DAC0_SEL (RW)

  *

  */

 #define TRGM_DAC_MATRIX_SEL1_PWM1_DAC0_SEL_MASK (0xFF0000UL)

 #define TRGM_DAC_MATRIX_SEL1_PWM1_DAC0_SEL_SHIFT (16U)

 #define TRGM_DAC_MATRIX_SEL1_PWM1_DAC0_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL1_PWM1_DAC0_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL1_PWM1_DAC0_SEL_MASK)

 #define TRGM_DAC_MATRIX_SEL1_PWM1_DAC0_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL1_PWM1_DAC0_SEL_MASK) >> TRGM_DAC_MATRIX_SEL1_PWM1_DAC0_SEL_SHIFT)


 /*

  * PWM0_DAC3_SEL (RW)

  *

  */

 #define TRGM_DAC_MATRIX_SEL1_PWM0_DAC3_SEL_MASK (0xFF00U)

 #define TRGM_DAC_MATRIX_SEL1_PWM0_DAC3_SEL_SHIFT (8U)

 #define TRGM_DAC_MATRIX_SEL1_PWM0_DAC3_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL1_PWM0_DAC3_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL1_PWM0_DAC3_SEL_MASK)

 #define TRGM_DAC_MATRIX_SEL1_PWM0_DAC3_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL1_PWM0_DAC3_SEL_MASK) >> TRGM_DAC_MATRIX_SEL1_PWM0_DAC3_SEL_SHIFT)


 /*

  * PWM0_DAC2_SEL (RW)

  *

  */

 #define TRGM_DAC_MATRIX_SEL1_PWM0_DAC2_SEL_MASK (0xFFU)

 #define TRGM_DAC_MATRIX_SEL1_PWM0_DAC2_SEL_SHIFT (0U)

 #define TRGM_DAC_MATRIX_SEL1_PWM0_DAC2_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL1_PWM0_DAC2_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL1_PWM0_DAC2_SEL_MASK)

 #define TRGM_DAC_MATRIX_SEL1_PWM0_DAC2_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL1_PWM0_DAC2_SEL_MASK) >> TRGM_DAC_MATRIX_SEL1_PWM0_DAC2_SEL_SHIFT)


 /* Bitfield definition for register: DAC_MATRIX_SEL2 */

 /*

  * PWM1_DAC3_SEL (RW)

  *

  */

 #define TRGM_DAC_MATRIX_SEL2_PWM1_DAC3_SEL_MASK (0xFF00U)

 #define TRGM_DAC_MATRIX_SEL2_PWM1_DAC3_SEL_SHIFT (8U)

 #define TRGM_DAC_MATRIX_SEL2_PWM1_DAC3_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL2_PWM1_DAC3_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL2_PWM1_DAC3_SEL_MASK)

 #define TRGM_DAC_MATRIX_SEL2_PWM1_DAC3_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL2_PWM1_DAC3_SEL_MASK) >> TRGM_DAC_MATRIX_SEL2_PWM1_DAC3_SEL_SHIFT)


 /*

  * PWM1_DAC2_SEL (RW)

  *

  */

 #define TRGM_DAC_MATRIX_SEL2_PWM1_DAC2_SEL_MASK (0xFFU)

 #define TRGM_DAC_MATRIX_SEL2_PWM1_DAC2_SEL_SHIFT (0U)

 #define TRGM_DAC_MATRIX_SEL2_PWM1_DAC2_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL2_PWM1_DAC2_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL2_PWM1_DAC2_SEL_MASK)

 #define TRGM_DAC_MATRIX_SEL2_PWM1_DAC2_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL2_PWM1_DAC2_SEL_MASK) >> TRGM_DAC_MATRIX_SEL2_PWM1_DAC2_SEL_SHIFT)


 /* Bitfield definition for register: POS_MATRIX_SEL0 */

 /*

  * QEO1_POSIN_SEL (RW)

  *

  */

 #define TRGM_POS_MATRIX_SEL0_QEO1_POSIN_SEL_MASK (0xFF00U)

 #define TRGM_POS_MATRIX_SEL0_QEO1_POSIN_SEL_SHIFT (8U)

 #define TRGM_POS_MATRIX_SEL0_QEO1_POSIN_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL0_QEO1_POSIN_SEL_SHIFT) & TRGM_POS_MATRIX_SEL0_QEO1_POSIN_SEL_MASK)

 #define TRGM_POS_MATRIX_SEL0_QEO1_POSIN_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL0_QEO1_POSIN_SEL_MASK) >> TRGM_POS_MATRIX_SEL0_QEO1_POSIN_SEL_SHIFT)


 /*

  * QEO0_POSIN_SEL (RW)

  *

  */

 #define TRGM_POS_MATRIX_SEL0_QEO0_POSIN_SEL_MASK (0xFFU)

 #define TRGM_POS_MATRIX_SEL0_QEO0_POSIN_SEL_SHIFT (0U)

 #define TRGM_POS_MATRIX_SEL0_QEO0_POSIN_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL0_QEO0_POSIN_SEL_SHIFT) & TRGM_POS_MATRIX_SEL0_QEO0_POSIN_SEL_MASK)

 #define TRGM_POS_MATRIX_SEL0_QEO0_POSIN_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL0_QEO0_POSIN_SEL_MASK) >> TRGM_POS_MATRIX_SEL0_QEO0_POSIN_SEL_SHIFT)


 /* Bitfield definition for register array: TRGM_IN */

 /*

  * TRGM_IN (RO)

  *

  */

 #define TRGM_TRGM_IN_TRGM_IN_MASK (0xFFFFFFFFUL)

 #define TRGM_TRGM_IN_TRGM_IN_SHIFT (0U)

 #define TRGM_TRGM_IN_TRGM_IN_GET(x) (((uint32_t)(x) & TRGM_TRGM_IN_TRGM_IN_MASK) >> TRGM_TRGM_IN_TRGM_IN_SHIFT)


 /* Bitfield definition for register array: TRGM_OUT */

 /*

  * TRGM_OUT (RO)

  *

  */

 #define TRGM_TRGM_OUT_TRGM_OUT_MASK (0xFFFFFFFFUL)

 #define TRGM_TRGM_OUT_TRGM_OUT_SHIFT (0U)

 #define TRGM_TRGM_OUT_TRGM_OUT_GET(x) (((uint32_t)(x) & TRGM_TRGM_OUT_TRGM_OUT_MASK) >> TRGM_TRGM_OUT_TRGM_OUT_SHIFT)


 /* Bitfield definition for register: PWM_DELAY_CFG */

 /*

  * DELAY_CHAN_CALIB_SW (RW)

  *

  */

 #define TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_SW_MASK (0x3FU)

 #define TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_SW_SHIFT (0U)

 #define TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_SW_SET(x) (((uint32_t)(x) << TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_SW_SHIFT) & TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_SW_MASK)

 #define TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_SW_GET(x) (((uint32_t)(x) & TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_SW_MASK) >> TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_SW_SHIFT)


 /* Bitfield definition for register: PWM_CALIB_CFG */

 /*

  * CALIB_SW_START (RW)

  *

  */

 #define TRGM_PWM_CALIB_CFG_CALIB_SW_START_MASK (0x8000U)

 #define TRGM_PWM_CALIB_CFG_CALIB_SW_START_SHIFT (15U)

 #define TRGM_PWM_CALIB_CFG_CALIB_SW_START_SET(x) (((uint32_t)(x) << TRGM_PWM_CALIB_CFG_CALIB_SW_START_SHIFT) & TRGM_PWM_CALIB_CFG_CALIB_SW_START_MASK)

 #define TRGM_PWM_CALIB_CFG_CALIB_SW_START_GET(x) (((uint32_t)(x) & TRGM_PWM_CALIB_CFG_CALIB_SW_START_MASK) >> TRGM_PWM_CALIB_CFG_CALIB_SW_START_SHIFT)


 /*

  * CALIB_PERIOD (RW)

  *

  */

 #define TRGM_PWM_CALIB_CFG_CALIB_PERIOD_MASK (0x1FU)

 #define TRGM_PWM_CALIB_CFG_CALIB_PERIOD_SHIFT (0U)

 #define TRGM_PWM_CALIB_CFG_CALIB_PERIOD_SET(x) (((uint32_t)(x) << TRGM_PWM_CALIB_CFG_CALIB_PERIOD_SHIFT) & TRGM_PWM_CALIB_CFG_CALIB_PERIOD_MASK)

 #define TRGM_PWM_CALIB_CFG_CALIB_PERIOD_GET(x) (((uint32_t)(x) & TRGM_PWM_CALIB_CFG_CALIB_PERIOD_MASK) >> TRGM_PWM_CALIB_CFG_CALIB_PERIOD_SHIFT)


 /* Bitfield definition for register array: TRGOCFG */

 /*

  * OUTINV (RW)

  *

  * 1- Invert the output

  */

 #define TRGM_TRGOCFG_OUTINV_MASK (0x40000UL)

 #define TRGM_TRGOCFG_OUTINV_SHIFT (18U)

 #define TRGM_TRGOCFG_OUTINV_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_OUTINV_SHIFT) & TRGM_TRGOCFG_OUTINV_MASK)

 #define TRGM_TRGOCFG_OUTINV_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_OUTINV_MASK) >> TRGM_TRGOCFG_OUTINV_SHIFT)


 /*

  * FEDG2PEN (RW)

  *

  * 1- The selected input signal falling edge will be convert to an pulse on output. The output pulse can be stably used within the motor control system. When connecting the signal outside the motor system, due to the asynchronization of the clock systems, the clock frequency and signal active length need to be considered.

  */

 #define TRGM_TRGOCFG_FEDG2PEN_MASK (0x20000UL)

 #define TRGM_TRGOCFG_FEDG2PEN_SHIFT (17U)

 #define TRGM_TRGOCFG_FEDG2PEN_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_FEDG2PEN_SHIFT) & TRGM_TRGOCFG_FEDG2PEN_MASK)

 #define TRGM_TRGOCFG_FEDG2PEN_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_FEDG2PEN_MASK) >> TRGM_TRGOCFG_FEDG2PEN_SHIFT)


 /*

  * REDG2PEN (RW)

  *

  * 1- The selected input signal rising edge will be convert to an pulse on output. The output pulse can be stably used within the motor control system. When connecting the signal outside the motor system, due to the asynchronization of the clock systems, the clock frequency and signal active length need to be considered.

  */

 #define TRGM_TRGOCFG_REDG2PEN_MASK (0x10000UL)

 #define TRGM_TRGOCFG_REDG2PEN_SHIFT (16U)

 #define TRGM_TRGOCFG_REDG2PEN_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_REDG2PEN_SHIFT) & TRGM_TRGOCFG_REDG2PEN_MASK)

 #define TRGM_TRGOCFG_REDG2PEN_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_REDG2PEN_MASK) >> TRGM_TRGOCFG_REDG2PEN_SHIFT)


 /*

  * TRIGOSEL (RW)

  *

  * This bitfield selects one of the TRGM inputs as output.

  */

 #define TRGM_TRGOCFG_TRIGOSEL_MASK (0xFFU)

 #define TRGM_TRGOCFG_TRIGOSEL_SHIFT (0U)

 #define TRGM_TRGOCFG_TRIGOSEL_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_TRIGOSEL_SHIFT) & TRGM_TRGOCFG_TRIGOSEL_MASK)

 #define TRGM_TRGOCFG_TRIGOSEL_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_TRIGOSEL_MASK) >> TRGM_TRGOCFG_TRIGOSEL_SHIFT)


 /* FILTCFG register group index macro definition */

 #define TRGM_FILTCFG_PWM0_IN0 (0UL)

 #define TRGM_FILTCFG_PWM0_IN1 (1UL)

 #define TRGM_FILTCFG_PWM0_IN2 (2UL)

 #define TRGM_FILTCFG_PWM0_IN3 (3UL)

 #define TRGM_FILTCFG_PWM0_IN4 (4UL)

 #define TRGM_FILTCFG_PWM0_IN5 (5UL)

 #define TRGM_FILTCFG_PWM0_IN6 (6UL)

 #define TRGM_FILTCFG_PWM0_IN7 (7UL)

 #define TRGM_FILTCFG_PWM1_IN0 (8UL)

 #define TRGM_FILTCFG_PWM1_IN1 (9UL)

 #define TRGM_FILTCFG_PWM1_IN2 (10UL)

 #define TRGM_FILTCFG_PWM1_IN3 (11UL)

 #define TRGM_FILTCFG_PWM1_IN4 (12UL)

 #define TRGM_FILTCFG_PWM1_IN5 (13UL)

 #define TRGM_FILTCFG_PWM1_IN6 (14UL)

 #define TRGM_FILTCFG_PWM1_IN7 (15UL)

 #define TRGM_FILTCFG_TRGM_P_00 (16UL)

 #define TRGM_FILTCFG_TRGM_P_01 (17UL)

 #define TRGM_FILTCFG_TRGM_P_02 (18UL)

 #define TRGM_FILTCFG_TRGM_P_03 (19UL)

 #define TRGM_FILTCFG_TRGM_P_04 (20UL)

 #define TRGM_FILTCFG_TRGM_P_05 (21UL)

 #define TRGM_FILTCFG_TRGM_P_06 (22UL)

 #define TRGM_FILTCFG_TRGM_P_07 (23UL)

 #define TRGM_FILTCFG_TRGM_P_08 (24UL)

 #define TRGM_FILTCFG_TRGM_P_09 (25UL)

 #define TRGM_FILTCFG_TRGM_P_10 (26UL)

 #define TRGM_FILTCFG_TRGM_P_11 (27UL)

 #define TRGM_FILTCFG_TRGM_P_12 (28UL)

 #define TRGM_FILTCFG_TRGM_P_13 (29UL)

 #define TRGM_FILTCFG_TRGM_P_14 (30UL)

 #define TRGM_FILTCFG_TRGM_P_15 (31UL)


 /* DMACFG register group index macro definition */

 #define TRGM_DMACFG_0 (0UL)

 #define TRGM_DMACFG_1 (1UL)

 #define TRGM_DMACFG_2 (2UL)

 #define TRGM_DMACFG_3 (3UL)

 #define TRGM_DMACFG_4 (4UL)

 #define TRGM_DMACFG_5 (5UL)

 #define TRGM_DMACFG_6 (6UL)

 #define TRGM_DMACFG_7 (7UL)


 /* TRGM_IN register group index macro definition */

 #define TRGM_TRGM_IN_0 (0UL)

 #define TRGM_TRGM_IN_1 (1UL)

 #define TRGM_TRGM_IN_2 (2UL)

 #define TRGM_TRGM_IN_3 (3UL)

 #define TRGM_TRGM_IN_4 (4UL)


 /* TRGM_OUT register group index macro definition */

 #define TRGM_TRGM_OUT_0 (0UL)

 #define TRGM_TRGM_OUT_1 (1UL)

 #define TRGM_TRGM_OUT_2 (2UL)

 #define TRGM_TRGM_OUT_3 (3UL)

 #define TRGM_TRGM_OUT_4 (4UL)


 /* TRGOCFG register group index macro definition */

 #define TRGM_TRGOCFG_TRGM_P_00 (0UL)

 #define TRGM_TRGOCFG_TRGM_P_01 (1UL)

 #define TRGM_TRGOCFG_TRGM_P_02 (2UL)

 #define TRGM_TRGOCFG_TRGM_P_03 (3UL)

 #define TRGM_TRGOCFG_TRGM_P_04 (4UL)

 #define TRGM_TRGOCFG_TRGM_P_05 (5UL)

 #define TRGM_TRGOCFG_TRGM_P_06 (6UL)

 #define TRGM_TRGOCFG_TRGM_P_07 (7UL)

 #define TRGM_TRGOCFG_TRGM_P_08 (8UL)

 #define TRGM_TRGOCFG_TRGM_P_09 (9UL)

 #define TRGM_TRGOCFG_TRGM_P_10 (10UL)

 #define TRGM_TRGOCFG_TRGM_P_11 (11UL)

 #define TRGM_TRGOCFG_TRGM_P_12 (12UL)

 #define TRGM_TRGOCFG_TRGM_P_13 (13UL)

 #define TRGM_TRGOCFG_TRGM_P_14 (14UL)

 #define TRGM_TRGOCFG_TRGM_P_15 (15UL)

 #define TRGM_TRGOCFG_PWM0_TRIG_IN0 (16UL)

 #define TRGM_TRGOCFG_PWM0_TRIG_IN1 (17UL)

 #define TRGM_TRGOCFG_PWM0_TRIG_IN2 (18UL)

 #define TRGM_TRGOCFG_PWM0_TRIG_IN3 (19UL)

 #define TRGM_TRGOCFG_PWM0_TRIG_IN4 (20UL)

 #define TRGM_TRGOCFG_PWM0_TRIG_IN5 (21UL)

 #define TRGM_TRGOCFG_PWM0_TRIG_IN6 (22UL)

 #define TRGM_TRGOCFG_PWM0_TRIG_IN7 (23UL)

 #define TRGM_TRGOCFG_PWM1_TRIG_IN0 (24UL)

 #define TRGM_TRGOCFG_PWM1_TRIG_IN1 (25UL)

 #define TRGM_TRGOCFG_PWM1_TRIG_IN2 (26UL)

 #define TRGM_TRGOCFG_PWM1_TRIG_IN3 (27UL)

 #define TRGM_TRGOCFG_PWM1_TRIG_IN4 (28UL)

 #define TRGM_TRGOCFG_PWM1_TRIG_IN5 (29UL)

 #define TRGM_TRGOCFG_PWM1_TRIG_IN6 (30UL)

 #define TRGM_TRGOCFG_PWM1_TRIG_IN7 (31UL)

 #define TRGM_TRGOCFG_ADC0_STRGI (32UL)

 #define TRGM_TRGOCFG_ADC1_STRGI (33UL)

 #define TRGM_TRGOCFG_ADCX_PTRGI0A (34UL)

 #define TRGM_TRGOCFG_ADCX_PTRGI0B (35UL)

 #define TRGM_TRGOCFG_ADCX_PTRGI0C (36UL)

 #define TRGM_TRGOCFG_ADCX_PTRGI1A (37UL)

 #define TRGM_TRGOCFG_ADCX_PTRGI1B (38UL)

 #define TRGM_TRGOCFG_ADCX_PTRGI1C (39UL)

 #define TRGM_TRGOCFG_ADCX_PTRGI2A (40UL)

 #define TRGM_TRGOCFG_ADCX_PTRGI2B (41UL)

 #define TRGM_TRGOCFG_ADCX_PTRGI2C (42UL)

 #define TRGM_TRGOCFG_ADCX_PTRGI3A (43UL)

 #define TRGM_TRGOCFG_ADCX_PTRGI3B (44UL)

 #define TRGM_TRGOCFG_ADCX_PTRGI3C (45UL)

 #define TRGM_TRGOCFG_QEI0_TRIG_IN (46UL)

 #define TRGM_TRGOCFG_QEI1_TRIG_IN (47UL)

 #define TRGM_TRGOCFG_QEI0_PAUSE (48UL)

 #define TRGM_TRGOCFG_QEI1_PAUSE (49UL)

 #define TRGM_TRGOCFG_QEO0_TRIG_IN0 (50UL)

 #define TRGM_TRGOCFG_QEO0_TRIG_IN1 (51UL)

 #define TRGM_TRGOCFG_QEO1_TRIG_IN0 (52UL)

 #define TRGM_TRGOCFG_QEO1_TRIG_IN1 (53UL)

 #define TRGM_TRGOCFG_ACMP0_CH0_WIN (54UL)

 #define TRGM_TRGOCFG_ACMP0_CH1_WIN (55UL)

 #define TRGM_TRGOCFG_GPTMR0_IN2 (56UL)

 #define TRGM_TRGOCFG_GPTMR0_IN3 (57UL)

 #define TRGM_TRGOCFG_GPTMR1_IN2 (58UL)

 #define TRGM_TRGOCFG_GPTMR1_IN3 (59UL)

 #define TRGM_TRGOCFG_GPTMR2_IN2 (60UL)

 #define TRGM_TRGOCFG_GPTMR2_IN3 (61UL)

 #define TRGM_TRGOCFG_GPTMR3_IN2 (62UL)

 #define TRGM_TRGOCFG_GPTMR3_IN3 (63UL)

 #define TRGM_TRGOCFG_GPTMR0_SYNCI (64UL)

 #define TRGM_TRGOCFG_GPTMR1_SYNCI (65UL)

 #define TRGM_TRGOCFG_GPTMR2_SYNCI (66UL)

 #define TRGM_TRGOCFG_GPTMR3_SYNCI (67UL)

 #define TRGM_TRGOCFG_CAN_PTPC0_CAP (68UL)

 #define TRGM_TRGOCFG_CAN_PTPC1_CAP (69UL)

 #define TRGM_TRGOCFG_UART_TRIG0 (70UL)

 #define TRGM_TRGOCFG_UART_TRIG1 (71UL)

 #define TRGM_TRGOCFG_SDM_PWM_SOC0 (72UL)

 #define TRGM_TRGOCFG_SDM_PWM_SOC1 (73UL)

 #define TRGM_TRGOCFG_SDM_PWM_SOC2 (74UL)

 #define TRGM_TRGOCFG_SDM_PWM_SOC3 (75UL)

 #define TRGM_TRGOCFG_SDM_PWM_SOC4 (76UL)

 #define TRGM_TRGOCFG_SDM_PWM_SOC5 (77UL)

 #define TRGM_TRGOCFG_SDM_PWM_SOC6 (78UL)

 #define TRGM_TRGOCFG_SDM_PWM_SOC7 (79UL)

 #define TRGM_TRGOCFG_SDM_PWM_SOC8 (80UL)

 #define TRGM_TRGOCFG_SDM_PWM_SOC9 (81UL)

 #define TRGM_TRGOCFG_SDM_PWM_SOC10 (82UL)

 #define TRGM_TRGOCFG_SDM_PWM_SOC11 (83UL)

 #define TRGM_TRGOCFG_SDM_PWM_SOC12 (84UL)

 #define TRGM_TRGOCFG_SDM_PWM_SOC13 (85UL)

 #define TRGM_TRGOCFG_SDM_PWM_SOC14 (86UL)

 #define TRGM_TRGOCFG_SDM_PWM_SOC15 (87UL)

 #define TRGM_TRGOCFG_PLB_IN_00 (88UL)

 #define TRGM_TRGOCFG_PLB_IN_01 (89UL)

 #define TRGM_TRGOCFG_PLB_IN_02 (90UL)

 #define TRGM_TRGOCFG_PLB_IN_03 (91UL)

 #define TRGM_TRGOCFG_PLB_IN_04 (92UL)

 #define TRGM_TRGOCFG_PLB_IN_05 (93UL)

 #define TRGM_TRGOCFG_PLB_IN_06 (94UL)

 #define TRGM_TRGOCFG_PLB_IN_07 (95UL)

 #define TRGM_TRGOCFG_PLB_IN_08 (96UL)

 #define TRGM_TRGOCFG_PLB_IN_09 (97UL)

 #define TRGM_TRGOCFG_PLB_IN_10 (98UL)

 #define TRGM_TRGOCFG_PLB_IN_11 (99UL)

 #define TRGM_TRGOCFG_PLB_IN_12 (100UL)

 #define TRGM_TRGOCFG_PLB_IN_13 (101UL)

 #define TRGM_TRGOCFG_PLB_IN_14 (102UL)

 #define TRGM_TRGOCFG_PLB_IN_15 (103UL)

 #define TRGM_TRGOCFG_PLB_IN_16 (104UL)

 #define TRGM_TRGOCFG_PLB_IN_17 (105UL)

 #define TRGM_TRGOCFG_PLB_IN_18 (106UL)

 #define TRGM_TRGOCFG_PLB_IN_19 (107UL)

 #define TRGM_TRGOCFG_PLB_IN_20 (108UL)

 #define TRGM_TRGOCFG_PLB_IN_21 (109UL)

 #define TRGM_TRGOCFG_PLB_IN_22 (110UL)

 #define TRGM_TRGOCFG_PLB_IN_23 (111UL)

 #define TRGM_TRGOCFG_PLB_IN_24 (112UL)

 #define TRGM_TRGOCFG_PLB_IN_25 (113UL)

 #define TRGM_TRGOCFG_PLB_IN_26 (114UL)

 #define TRGM_TRGOCFG_PLB_IN_27 (115UL)

 #define TRGM_TRGOCFG_PLB_IN_28 (116UL)

 #define TRGM_TRGOCFG_PLB_IN_29 (117UL)

 #define TRGM_TRGOCFG_PLB_IN_30 (118UL)

 #define TRGM_TRGOCFG_PLB_IN_31 (119UL)

 #define TRGM_TRGOCFG_PLB_IN_32 (120UL)

 #define TRGM_TRGOCFG_PLB_IN_33 (121UL)

 #define TRGM_TRGOCFG_PLB_IN_34 (122UL)

 #define TRGM_TRGOCFG_PLB_IN_35 (123UL)

 #define TRGM_TRGOCFG_PLB_IN_36 (124UL)

 #define TRGM_TRGOCFG_PLB_IN_37 (125UL)

 #define TRGM_TRGOCFG_PLB_IN_38 (126UL)

 #define TRGM_TRGOCFG_PLB_IN_39 (127UL)

 #define TRGM_TRGOCFG_PLB_IN_40 (128UL)

 #define TRGM_TRGOCFG_PLB_IN_41 (129UL)

 #define TRGM_TRGOCFG_PLB_IN_42 (130UL)

 #define TRGM_TRGOCFG_PLB_IN_43 (131UL)

 #define TRGM_TRGOCFG_PLB_IN_44 (132UL)

 #define TRGM_TRGOCFG_PLB_IN_45 (133UL)

 #define TRGM_TRGOCFG_PLB_IN_46 (134UL)

 #define TRGM_TRGOCFG_PLB_IN_47 (135UL)

 #define TRGM_TRGOCFG_PLB_IN_48 (136UL)

 #define TRGM_TRGOCFG_PLB_IN_49 (137UL)

 #define TRGM_TRGOCFG_PLB_IN_50 (138UL)

 #define TRGM_TRGOCFG_PLB_IN_51 (139UL)

 #define TRGM_TRGOCFG_PLB_IN_52 (140UL)

 #define TRGM_TRGOCFG_PLB_IN_53 (141UL)

 #define TRGM_TRGOCFG_PLB_IN_54 (142UL)

 #define TRGM_TRGOCFG_PLB_IN_55 (143UL)

 #define TRGM_TRGOCFG_PLB_IN_56 (144UL)

 #define TRGM_TRGOCFG_PLB_IN_57 (145UL)

 #define TRGM_TRGOCFG_PLB_IN_58 (146UL)

 #define TRGM_TRGOCFG_PLB_IN_59 (147UL)

 #define TRGM_TRGOCFG_PLB_IN_60 (148UL)

 #define TRGM_TRGOCFG_PLB_IN_61 (149UL)

 #define TRGM_TRGOCFG_PLB_IN_62 (150UL)

 #define TRGM_TRGOCFG_PLB_IN_63 (151UL)

 #define TRGM_TRGOCFG_SYNCTIMER_TRIG (152UL)

 #define TRGM_TRGOCFG_DCCS_TRIG (153UL)

 #define TRGM_TRGOCFG_TRGM_IRQ0 (154UL)

 #define TRGM_TRGOCFG_TRGM_IRQ1 (155UL)

 #define TRGM_TRGOCFG_TRGM_DMA0 (156UL)

 #define TRGM_TRGOCFG_TRGM_DMA1 (157UL)

 #define TRGM_TRGOCFG_ESC_TRIG_IN (158UL)


 #endif /* HPM_TRGM_H */

TRGM_Type
Definition: hpm_trgm_regs.h:12