HPM SDK
HPMicro Software Development Kit
hpm_ppor_regs.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_PPOR_H
10 #define HPM_PPOR_H
11 
12 typedef struct {
13  __W uint32_t RESET_FLAG; /* 0x0: flag indicate reset source */
14  __RW uint32_t RESET_STATUS; /* 0x4: reset source status */
15  __RW uint32_t RESET_HOLD; /* 0x8: reset hold attribute */
16  __RW uint32_t RESET_ENABLE; /* 0xC: reset source enable */
17  __RW uint32_t RESET_HOT; /* 0x10: reset type triggered by reset */
18  __RW uint32_t RESET_COLD; /* 0x14: reset type attribute */
19  __R uint8_t RESERVED0[4]; /* 0x18 - 0x1B: Reserved */
20  __RW uint32_t SOFTWARE_RESET; /* 0x1C: Software reset counter */
21 } PPOR_Type;
22 
23 
24 /* Bitfield definition for register: RESET_FLAG */
25 /*
26  * FLAG (W1C)
27  *
28  * reset reason of last hard reset, write 1 to clear each bit
29  * 0: brownout
30  * 1: temperature(not available)
31  * 2: resetpin(not available)
32  * 4: debug reset
33  * 5: jtag reset
34  * 8: cpu0 lockup(not available)
35  * 9: cpu1 lockup(not available)
36  * 10: cpu0 request(not available)
37  * 11: cpu1 request(not available)
38  * 16: watch dog 0
39  * 17: watch dog 1
40  * 18: watch dog 2
41  * 19: watch dog 3
42  * 20: pmic watch dog
43  * 31: software
44  */
45 #define PPOR_RESET_FLAG_FLAG_MASK (0xFFFFFFFFUL)
46 #define PPOR_RESET_FLAG_FLAG_SHIFT (0U)
47 #define PPOR_RESET_FLAG_FLAG_SET(x) (((uint32_t)(x) << PPOR_RESET_FLAG_FLAG_SHIFT) & PPOR_RESET_FLAG_FLAG_MASK)
48 #define PPOR_RESET_FLAG_FLAG_GET(x) (((uint32_t)(x) & PPOR_RESET_FLAG_FLAG_MASK) >> PPOR_RESET_FLAG_FLAG_SHIFT)
49 
50 /* Bitfield definition for register: RESET_STATUS */
51 /*
52  * STATUS (RW)
53  *
54  * current status of reset sources
55  * 0: brownout
56  * 1: temperature(not available)
57  * 2: resetpin(not available)
58  * 4: debug reset
59  * 5: jtag reset
60  * 8: cpu0 lockup(not available)
61  * 9: cpu1 lockup(not available)
62  * 10: cpu0 request(not available)
63  * 11: cpu1 request(not available)
64  * 16: watch dog 0
65  * 17: watch dog 1
66  * 18: watch dog 2
67  * 19: watch dog 3
68  * 20: pmic watch dog
69  * 31: software
70  */
71 #define PPOR_RESET_STATUS_STATUS_MASK (0xFFFFFFFFUL)
72 #define PPOR_RESET_STATUS_STATUS_SHIFT (0U)
73 #define PPOR_RESET_STATUS_STATUS_SET(x) (((uint32_t)(x) << PPOR_RESET_STATUS_STATUS_SHIFT) & PPOR_RESET_STATUS_STATUS_MASK)
74 #define PPOR_RESET_STATUS_STATUS_GET(x) (((uint32_t)(x) & PPOR_RESET_STATUS_STATUS_MASK) >> PPOR_RESET_STATUS_STATUS_SHIFT)
75 
76 /* Bitfield definition for register: RESET_HOLD */
77 /*
78  * STATUS (RW)
79  *
80  * hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status
81  * 0: brownout
82  * 1: temperature(not available)
83  * 2: resetpin(not available)
84  * 4: debug reset
85  * 5: jtag reset
86  * 8: cpu0 lockup(not available)
87  * 9: cpu1 lockup(not available)
88  * 10: cpu0 request(not available)
89  * 11: cpu1 request(not available)
90  * 16: watch dog 0
91  * 17: watch dog 1
92  * 18: watch dog 2
93  * 19: watch dog 3
94  * 20: pmic watch dog
95  * 31: software
96  */
97 #define PPOR_RESET_HOLD_STATUS_MASK (0xFFFFFFFFUL)
98 #define PPOR_RESET_HOLD_STATUS_SHIFT (0U)
99 #define PPOR_RESET_HOLD_STATUS_SET(x) (((uint32_t)(x) << PPOR_RESET_HOLD_STATUS_SHIFT) & PPOR_RESET_HOLD_STATUS_MASK)
100 #define PPOR_RESET_HOLD_STATUS_GET(x) (((uint32_t)(x) & PPOR_RESET_HOLD_STATUS_MASK) >> PPOR_RESET_HOLD_STATUS_SHIFT)
101 
102 /* Bitfield definition for register: RESET_ENABLE */
103 /*
104  * ENABLE (RW)
105  *
106  * enable of reset sources
107  * 0: brownout
108  * 1: temperature(not available)
109  * 2: resetpin(not available)
110  * 4: debug reset
111  * 5: jtag reset
112  * 8: cpu0 lockup(not available)
113  * 9: cpu1 lockup(not available)
114  * 10: cpu0 request(not available)
115  * 11: cpu1 request(not available)
116  * 16: watch dog 0
117  * 17: watch dog 1
118  * 18: watch dog 2
119  * 19: watch dog 3
120  * 20: pmic watch dog
121  * 31: software
122  */
123 #define PPOR_RESET_ENABLE_ENABLE_MASK (0xFFFFFFFFUL)
124 #define PPOR_RESET_ENABLE_ENABLE_SHIFT (0U)
125 #define PPOR_RESET_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << PPOR_RESET_ENABLE_ENABLE_SHIFT) & PPOR_RESET_ENABLE_ENABLE_MASK)
126 #define PPOR_RESET_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & PPOR_RESET_ENABLE_ENABLE_MASK) >> PPOR_RESET_ENABLE_ENABLE_SHIFT)
127 
128 /* Bitfield definition for register: RESET_HOT */
129 /*
130  * TYPE (RW)
131  *
132  * reset type of reset sources, 0 for cold/warm reset, all system control setting cleared including clock, ioc; 1 for hot reset, system control, ioc setting kept, peripheral setting cleared.
133  * 0: brownout
134  * 1: temperature(not available)
135  * 2: resetpin(not available)
136  * 4: debug reset
137  * 5: jtag reset
138  * 8: cpu0 lockup(not available)
139  * 9: cpu1 lockup(not available)
140  * 10: cpu0 request(not available)
141  * 11: cpu1 request(not available)
142  * 16: watch dog 0
143  * 17: watch dog 1
144  * 18: watch dog 2
145  * 19: watch dog 3
146  * 20: pmic watch dog
147  * 31: software
148  */
149 #define PPOR_RESET_HOT_TYPE_MASK (0xFFFFFFFFUL)
150 #define PPOR_RESET_HOT_TYPE_SHIFT (0U)
151 #define PPOR_RESET_HOT_TYPE_SET(x) (((uint32_t)(x) << PPOR_RESET_HOT_TYPE_SHIFT) & PPOR_RESET_HOT_TYPE_MASK)
152 #define PPOR_RESET_HOT_TYPE_GET(x) (((uint32_t)(x) & PPOR_RESET_HOT_TYPE_MASK) >> PPOR_RESET_HOT_TYPE_SHIFT)
153 
154 /* Bitfield definition for register: RESET_COLD */
155 /*
156  * FLAG (RW)
157  *
158  * perform cold or warm reset of chip, 0 for warm reset, fuse value and debug connection preserved; 1 for cold reset, fuse value reloaded and debug connection corrupted. This bit is ignored when hot reset selected
159  * 0: brownout
160  * 1: temperature(not available)
161  * 2: resetpin(not available)
162  * 4: debug reset
163  * 5: jtag reset
164  * 8: cpu0 lockup(not available)
165  * 9: cpu1 lockup(not available)
166  * 10: cpu0 request(not available)
167  * 11: cpu1 request(not available)
168  * 16: watch dog 0
169  * 17: watch dog 1
170  * 18: watch dog 2
171  * 19: watch dog 3
172  * 20: pmic watch dog
173  * 31: software
174  */
175 #define PPOR_RESET_COLD_FLAG_MASK (0xFFFFFFFFUL)
176 #define PPOR_RESET_COLD_FLAG_SHIFT (0U)
177 #define PPOR_RESET_COLD_FLAG_SET(x) (((uint32_t)(x) << PPOR_RESET_COLD_FLAG_SHIFT) & PPOR_RESET_COLD_FLAG_MASK)
178 #define PPOR_RESET_COLD_FLAG_GET(x) (((uint32_t)(x) & PPOR_RESET_COLD_FLAG_MASK) >> PPOR_RESET_COLD_FLAG_SHIFT)
179 
180 /* Bitfield definition for register: SOFTWARE_RESET */
181 /*
182  * COUNTER (RW)
183  *
184  * counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset
185  */
186 #define PPOR_SOFTWARE_RESET_COUNTER_MASK (0xFFFFFFFFUL)
187 #define PPOR_SOFTWARE_RESET_COUNTER_SHIFT (0U)
188 #define PPOR_SOFTWARE_RESET_COUNTER_SET(x) (((uint32_t)(x) << PPOR_SOFTWARE_RESET_COUNTER_SHIFT) & PPOR_SOFTWARE_RESET_COUNTER_MASK)
189 #define PPOR_SOFTWARE_RESET_COUNTER_GET(x) (((uint32_t)(x) & PPOR_SOFTWARE_RESET_COUNTER_MASK) >> PPOR_SOFTWARE_RESET_COUNTER_SHIFT)
190 
191 
192 
193 
194 #endif /* HPM_PPOR_H */
PPOR_Type
Definition: hpm_ppor_regs.h:12