HPM SDK
HPMicro Software Development Kit
hpm_ppor_regs.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_PPOR_H
10 #define HPM_PPOR_H
11 
12 typedef struct {
13  __W uint32_t RESET_FLAG; /* 0x0: flag indicate reset source */
14  __R uint32_t RESET_STATUS; /* 0x4: reset source status */
15  __RW uint32_t RESET_HOLD; /* 0x8: reset hold attribute */
16  __RW uint32_t RESET_ENABLE; /* 0xC: reset source enable */
17  __R uint8_t RESERVED0[12]; /* 0x10 - 0x1B: Reserved */
18  __RW uint32_t SOFTWARE_RESET; /* 0x1C: Software reset counter */
19 } PPOR_Type;
20 
21 
22 /* Bitfield definition for register: RESET_FLAG */
23 /*
24  * FLAG (W1C)
25  *
26  * reset reason of last hard reset, write 1 to clear each bit
27  * 0: brownout
28  * 1: temperature(not available)
29  * 4: debug reset
30  * 5: jtag soft reset
31  * 8: cpu0 lockup(not available)
32  * 9: cpu1 lockup(not available)
33  * 10: cpu0 request(not available)
34  * 11: cpu1 request(not available)
35  * 16: watch dog 0
36  * 17: watch dog 1
37  * 18: watch dog 2(not available)
38  * 19: watch dog 3(not available)
39  * 24: pmic watch dog
40  * 30: jtag ieee reset
41  * 31: software
42  */
43 #define PPOR_RESET_FLAG_FLAG_MASK (0xFFFFFFFFUL)
44 #define PPOR_RESET_FLAG_FLAG_SHIFT (0U)
45 #define PPOR_RESET_FLAG_FLAG_SET(x) (((uint32_t)(x) << PPOR_RESET_FLAG_FLAG_SHIFT) & PPOR_RESET_FLAG_FLAG_MASK)
46 #define PPOR_RESET_FLAG_FLAG_GET(x) (((uint32_t)(x) & PPOR_RESET_FLAG_FLAG_MASK) >> PPOR_RESET_FLAG_FLAG_SHIFT)
47 
48 /* Bitfield definition for register: RESET_STATUS */
49 /*
50  * STATUS (RO)
51  *
52  * current status of reset sources
53  * 0: brownout
54  * 1: temperature(not available)
55  * 4: debug reset
56  * 5: jtag soft reset
57  * 8: cpu0 lockup(not available)
58  * 9: cpu1 lockup(not available)
59  * 10: cpu0 request(not available)
60  * 11: cpu1 request(not available)
61  * 16: watch dog 0
62  * 17: watch dog 1
63  * 18: watch dog 2(not available)
64  * 19: watch dog 3(not available)
65  * 24: pmic watch dog
66  * 30: jtag ieee reset
67  * 31: software
68  */
69 #define PPOR_RESET_STATUS_STATUS_MASK (0xFFFFFFFFUL)
70 #define PPOR_RESET_STATUS_STATUS_SHIFT (0U)
71 #define PPOR_RESET_STATUS_STATUS_GET(x) (((uint32_t)(x) & PPOR_RESET_STATUS_STATUS_MASK) >> PPOR_RESET_STATUS_STATUS_SHIFT)
72 
73 /* Bitfield definition for register: RESET_HOLD */
74 /*
75  * HOLD (RW)
76  *
77  * hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status
78  * 0: brownout
79  * 1: temperature(not available)
80  * 4: debug reset
81  * 5: jtag soft reset
82  * 8: cpu0 lockup(not available)
83  * 9: cpu1 lockup(not available)
84  * 10: cpu0 request(not available)
85  * 11: cpu1 request(not available)
86  * 16: watch dog 0
87  * 17: watch dog 1
88  * 18: watch dog 2(not available)
89  * 19: watch dog 3(not available)
90  * 24: pmic watch dog
91  * 30: jtag ieee reset
92  * 31: software
93  */
94 #define PPOR_RESET_HOLD_HOLD_MASK (0xFFFFFFFFUL)
95 #define PPOR_RESET_HOLD_HOLD_SHIFT (0U)
96 #define PPOR_RESET_HOLD_HOLD_SET(x) (((uint32_t)(x) << PPOR_RESET_HOLD_HOLD_SHIFT) & PPOR_RESET_HOLD_HOLD_MASK)
97 #define PPOR_RESET_HOLD_HOLD_GET(x) (((uint32_t)(x) & PPOR_RESET_HOLD_HOLD_MASK) >> PPOR_RESET_HOLD_HOLD_SHIFT)
98 
99 /* Bitfield definition for register: RESET_ENABLE */
100 /*
101  * ENABLE (RW)
102  *
103  * enable of reset sources
104  * 0: brownout
105  * 1: temperature(not available)
106  * 4: debug reset
107  * 5: jtag soft reset
108  * 8: cpu0 lockup(not available)
109  * 9: cpu1 lockup(not available)
110  * 10: cpu0 request(not available)
111  * 11: cpu1 request(not available)
112  * 16: watch dog 0
113  * 17: watch dog 1
114  * 18: watch dog 2(not available)
115  * 19: watch dog 3(not available)
116  * 24: pmic watch dog
117  * 30: jtag ieee reset
118  * 31: software
119  */
120 #define PPOR_RESET_ENABLE_ENABLE_MASK (0xFFFFFFFFUL)
121 #define PPOR_RESET_ENABLE_ENABLE_SHIFT (0U)
122 #define PPOR_RESET_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << PPOR_RESET_ENABLE_ENABLE_SHIFT) & PPOR_RESET_ENABLE_ENABLE_MASK)
123 #define PPOR_RESET_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & PPOR_RESET_ENABLE_ENABLE_MASK) >> PPOR_RESET_ENABLE_ENABLE_SHIFT)
124 
125 /* Bitfield definition for register: SOFTWARE_RESET */
126 /*
127  * COUNTER (RW)
128  *
129  * counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset
130  */
131 #define PPOR_SOFTWARE_RESET_COUNTER_MASK (0xFFFFFFFFUL)
132 #define PPOR_SOFTWARE_RESET_COUNTER_SHIFT (0U)
133 #define PPOR_SOFTWARE_RESET_COUNTER_SET(x) (((uint32_t)(x) << PPOR_SOFTWARE_RESET_COUNTER_SHIFT) & PPOR_SOFTWARE_RESET_COUNTER_MASK)
134 #define PPOR_SOFTWARE_RESET_COUNTER_GET(x) (((uint32_t)(x) & PPOR_SOFTWARE_RESET_COUNTER_MASK) >> PPOR_SOFTWARE_RESET_COUNTER_SHIFT)
135 
136 
137 
138 
139 #endif /* HPM_PPOR_H */
PPOR_Type
Definition: hpm_ppor_regs.h:12