HPM SDK
HPMicro Software Development Kit
hpm_ppor_regs.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_PPOR_H
10 #define HPM_PPOR_H
11 
12 typedef struct {
13  __W uint32_t RESET_FLAG; /* 0x0: flag indicate reset source */
14  __R uint32_t RESET_STATUS; /* 0x4: reset source status */
15  __RW uint32_t RESET_HOLD; /* 0x8: reset hold attribute */
16  __RW uint32_t RESET_ENABLE; /* 0xC: reset source enable */
17  __RW uint32_t RESET_TYPE; /* 0x10: reset type triggered by reset */
18  __R uint8_t RESERVED0[8]; /* 0x14 - 0x1B: Reserved */
19  __RW uint32_t SOFTWARE_RESET; /* 0x1C: Software reset counter */
20 } PPOR_Type;
21 
22 
23 /* Bitfield definition for register: RESET_FLAG */
24 /*
25  * FLAG (W1C)
26  *
27  * reset reason of last hard reset, write 1 to clear each bit
28  * 0: brownout
29  * 1: temperature
30  * 4: debug reset
31  * 5: jtag soft reset
32  * 16: watch dog 0
33  * 17: watch dog 1
34  * 18: watch dog 2
35  * 19: watch dog 3
36  * 24: pmic watch dog
37  * 30: jtag ieee reset
38  * 31: software
39  */
40 #define PPOR_RESET_FLAG_FLAG_MASK (0xFFFFFFFFUL)
41 #define PPOR_RESET_FLAG_FLAG_SHIFT (0U)
42 #define PPOR_RESET_FLAG_FLAG_SET(x) (((uint32_t)(x) << PPOR_RESET_FLAG_FLAG_SHIFT) & PPOR_RESET_FLAG_FLAG_MASK)
43 #define PPOR_RESET_FLAG_FLAG_GET(x) (((uint32_t)(x) & PPOR_RESET_FLAG_FLAG_MASK) >> PPOR_RESET_FLAG_FLAG_SHIFT)
44 
45 /* Bitfield definition for register: RESET_STATUS */
46 /*
47  * STATUS (RO)
48  *
49  * current status of reset sources
50  * 0: brownout
51  * 1: temperature
52  * 4: debug reset
53  * 5: jtag soft reset
54  * 16: watch dog 0
55  * 17: watch dog 1
56  * 18: watch dog 2
57  * 19: watch dog 3
58  * 24: pmic watch dog
59  * 30: jtag ieee reset
60  * 31: software
61  */
62 #define PPOR_RESET_STATUS_STATUS_MASK (0xFFFFFFFFUL)
63 #define PPOR_RESET_STATUS_STATUS_SHIFT (0U)
64 #define PPOR_RESET_STATUS_STATUS_GET(x) (((uint32_t)(x) & PPOR_RESET_STATUS_STATUS_MASK) >> PPOR_RESET_STATUS_STATUS_SHIFT)
65 
66 /* Bitfield definition for register: RESET_HOLD */
67 /*
68  * HOLD (RW)
69  *
70  * hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status
71  * 0: brownout
72  * 1: temperature
73  * 4: debug reset
74  * 5: jtag soft reset
75  * 8: cpu0 lockup(not available)
76  * 9: cpu1 lockup(not available)
77  * 10: cpu0 request(not available)
78  * 11: cpu1 request(not available)
79  * 16: watch dog 0
80  * 17: watch dog 1
81  * 18: watch dog 2
82  * 19: watch dog 3
83  * 24: pmic watch dog
84  * 30: jtag ieee reset
85  * 31: software
86  */
87 #define PPOR_RESET_HOLD_HOLD_MASK (0xFFFFFFFFUL)
88 #define PPOR_RESET_HOLD_HOLD_SHIFT (0U)
89 #define PPOR_RESET_HOLD_HOLD_SET(x) (((uint32_t)(x) << PPOR_RESET_HOLD_HOLD_SHIFT) & PPOR_RESET_HOLD_HOLD_MASK)
90 #define PPOR_RESET_HOLD_HOLD_GET(x) (((uint32_t)(x) & PPOR_RESET_HOLD_HOLD_MASK) >> PPOR_RESET_HOLD_HOLD_SHIFT)
91 
92 /* Bitfield definition for register: RESET_ENABLE */
93 /*
94  * ENABLE (RW)
95  *
96  * enable of reset sources
97  * 0: brownout
98  * 1: temperature
99  * 4: debug reset
100  * 5: jtag soft reset
101  * 8: cpu0 lockup(not available)
102  * 9: cpu1 lockup(not available)
103  * 10: cpu0 request(not available)
104  * 11: cpu1 request(not available)
105  * 16: watch dog 0
106  * 17: watch dog 1
107  * 18: watch dog 2
108  * 19: watch dog 3
109  * 24: pmic watch dog
110  * 30: jtag ieee reset
111  * 31: software
112  */
113 #define PPOR_RESET_ENABLE_ENABLE_MASK (0xFFFFFFFFUL)
114 #define PPOR_RESET_ENABLE_ENABLE_SHIFT (0U)
115 #define PPOR_RESET_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << PPOR_RESET_ENABLE_ENABLE_SHIFT) & PPOR_RESET_ENABLE_ENABLE_MASK)
116 #define PPOR_RESET_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & PPOR_RESET_ENABLE_ENABLE_MASK) >> PPOR_RESET_ENABLE_ENABLE_SHIFT)
117 
118 /* Bitfield definition for register: RESET_TYPE */
119 /*
120  * TYPE (RW)
121  *
122  * reset type of reset sources, 0 for cold reset, all system control setting cleared except debug/fuse/ioc; 1 for hot reset, keep system control setting and debug/fuse/ioc setting, only clear some subsystem
123  * 0: brownout
124  * 1: temperature
125  * 4: debug reset
126  * 5: jtag soft reset
127  * 8: cpu0 lockup(not available)
128  * 9: cpu1 lockup(not available)
129  * 10: cpu0 request(not available)
130  * 11: cpu1 request(not available)
131  * 16: watch dog 0
132  * 17: watch dog 1
133  * 18: watch dog 2
134  * 19: watch dog 3
135  * 24: pmic watch dog
136  * 30: jtag ieee reset
137  * 31: software
138  */
139 #define PPOR_RESET_TYPE_TYPE_MASK (0xFFFFFFFFUL)
140 #define PPOR_RESET_TYPE_TYPE_SHIFT (0U)
141 #define PPOR_RESET_TYPE_TYPE_SET(x) (((uint32_t)(x) << PPOR_RESET_TYPE_TYPE_SHIFT) & PPOR_RESET_TYPE_TYPE_MASK)
142 #define PPOR_RESET_TYPE_TYPE_GET(x) (((uint32_t)(x) & PPOR_RESET_TYPE_TYPE_MASK) >> PPOR_RESET_TYPE_TYPE_SHIFT)
143 
144 /* Bitfield definition for register: SOFTWARE_RESET */
145 /*
146  * COUNTER (RW)
147  *
148  * counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset
149  */
150 #define PPOR_SOFTWARE_RESET_COUNTER_MASK (0xFFFFFFFFUL)
151 #define PPOR_SOFTWARE_RESET_COUNTER_SHIFT (0U)
152 #define PPOR_SOFTWARE_RESET_COUNTER_SET(x) (((uint32_t)(x) << PPOR_SOFTWARE_RESET_COUNTER_SHIFT) & PPOR_SOFTWARE_RESET_COUNTER_MASK)
153 #define PPOR_SOFTWARE_RESET_COUNTER_GET(x) (((uint32_t)(x) & PPOR_SOFTWARE_RESET_COUNTER_MASK) >> PPOR_SOFTWARE_RESET_COUNTER_SHIFT)
154 
155 
156 
157 
158 #endif /* HPM_PPOR_H */
PPOR_Type
Definition: hpm_ppor_regs.h:12