HPM SDK
HPMicro Software Development Kit
hpm_sei_regs.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_SEI_H
10 #define HPM_SEI_H
11 
12 typedef struct {
13  struct {
14  struct {
15  __RW uint32_t CTRL; /* 0x0: Engine control register */
16  __RW uint32_t PTR_CFG; /* 0x4: Pointer configuration register */
17  __RW uint32_t WDG_CFG; /* 0x8: Watch dog configuration register */
18  __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */
19  __R uint32_t EXE_STA; /* 0x10: Execution status */
20  __R uint32_t EXE_PTR; /* 0x14: Execution pointer */
21  __R uint32_t EXE_INST; /* 0x18: Execution instruction */
22  __R uint32_t WDG_STA; /* 0x1C: Watch dog status */
23  } ENGINE;
24  struct {
25  __RW uint32_t CTRL; /* 0x20: Transceiver control register */
26  __RW uint32_t TYPE_CFG; /* 0x24: Transceiver configuration register */
27  __RW uint32_t BAUD_CFG; /* 0x28: Transceiver baud rate register */
28  __RW uint32_t DATA_CFG; /* 0x2C: Transceiver data timing configuration */
29  __RW uint32_t CLK_CFG; /* 0x30: Transceiver clock timing configuration */
30  __R uint8_t RESERVED0[4]; /* 0x34 - 0x37: Reserved */
31  __R uint32_t PIN; /* 0x38: Transceiver pin status */
32  __R uint32_t STATE; /* 0x3C: FSM of asynchronous */
33  } XCVR;
34  struct {
35  __RW uint32_t IN_CFG; /* 0x40: Trigger input configuration */
36  __W uint32_t SW; /* 0x44: Software trigger */
37  __RW uint32_t PRD_CFG; /* 0x48: Period trigger configuration */
38  __RW uint32_t PRD; /* 0x4C: Trigger period */
39  __RW uint32_t OUT_CFG; /* 0x50: Trigger output configuration */
40  __R uint8_t RESERVED0[12]; /* 0x54 - 0x5F: Reserved */
41  __R uint32_t PRD_STS; /* 0x60: Period trigger status */
42  __R uint32_t PRD_CNT; /* 0x64: Period trigger counter */
43  __R uint8_t RESERVED1[24]; /* 0x68 - 0x7F: Reserved */
44  } TRG;
45  struct {
46  __RW uint32_t CMD[4]; /* 0x80 - 0x8C: Trigger command */
47  __R uint8_t RESERVED0[16]; /* 0x90 - 0x9F: Reserved */
48  __R uint32_t TIME[4]; /* 0xA0 - 0xAC: Trigger Time */
49  __R uint8_t RESERVED1[16]; /* 0xB0 - 0xBF: Reserved */
50  } TRG_TABLE;
51  struct {
52  __RW uint32_t MODE; /* 0xC0: command register mode */
53  __RW uint32_t IDX; /* 0xC4: command register configuration */
54  __R uint8_t RESERVED0[24]; /* 0xC8 - 0xDF: Reserved */
55  __RW uint32_t CMD; /* 0xE0: command */
56  __RW uint32_t SET; /* 0xE4: command bit set register */
57  __RW uint32_t CLR; /* 0xE8: command bit clear register */
58  __RW uint32_t INV; /* 0xEC: command bit invert register */
59  __R uint32_t IN; /* 0xF0: Commad input */
60  __R uint32_t OUT; /* 0xF4: Command output */
61  __RW uint32_t STS; /* 0xF8: Command status */
62  __R uint8_t RESERVED1[4]; /* 0xFC - 0xFF: Reserved */
63  } CMD;
64  struct {
65  __RW uint32_t MIN; /* 0x100: command start value */
66  __RW uint32_t MAX; /* 0x104: command end value */
67  __RW uint32_t MSK; /* 0x108: command compare bit enable */
68  __R uint8_t RESERVED0[4]; /* 0x10C - 0x10F: Reserved */
69  __RW uint32_t PTA; /* 0x110: command pointer 0 - 3 */
70  __RW uint32_t PTB; /* 0x114: command pointer 4 - 7 */
71  __R uint8_t RESERVED1[8]; /* 0x118 - 0x11F: Reserved */
72  } CMD_TABLE[8];
73  struct {
74  __RW uint32_t TRAN[4]; /* 0x200 - 0x20C: Latch state transition configuration */
75  __RW uint32_t CFG; /* 0x210: Latch configuration */
76  __R uint8_t RESERVED0[4]; /* 0x214 - 0x217: Reserved */
77  __R uint32_t TIME; /* 0x218: Latch time */
78  __R uint32_t STS; /* 0x21C: Latch status */
79  } LATCH[4];
80  struct {
81  __RW uint32_t SMP_EN; /* 0x280: Sample selection register */
82  __RW uint32_t SMP_CFG; /* 0x284: Sample configuration */
83  __RW uint32_t SMP_DAT; /* 0x288: Sample data */
84  __R uint8_t RESERVED0[4]; /* 0x28C - 0x28F: Reserved */
85  __RW uint32_t SMP_POS; /* 0x290: Sample override position */
86  __RW uint32_t SMP_REV; /* 0x294: Sample override revolution */
87  __RW uint32_t SMP_SPD; /* 0x298: Sample override speed */
88  __RW uint32_t SMP_ACC; /* 0x29C: Sample override accelerate */
89  __RW uint32_t UPD_EN; /* 0x2A0: Update configuration */
90  __RW uint32_t UPD_CFG; /* 0x2A4: Update configuration */
91  __RW uint32_t UPD_DAT; /* 0x2A8: Update data */
92  __RW uint32_t UPD_TIME; /* 0x2AC: Update overide time */
93  __RW uint32_t UPD_POS; /* 0x2B0: Update override position */
94  __RW uint32_t UPD_REV; /* 0x2B4: Update override revolution */
95  __RW uint32_t UPD_SPD; /* 0x2B8: Update override speed */
96  __RW uint32_t UPD_ACC; /* 0x2BC: Update override accelerate */
97  __R uint32_t SMP_VAL; /* 0x2C0: Sample valid */
98  __R uint32_t SMP_STS; /* 0x2C4: Sample status */
99  __R uint8_t RESERVED1[4]; /* 0x2C8 - 0x2CB: Reserved */
100  __R uint32_t TIME_IN; /* 0x2CC: input time */
101  __R uint32_t POS_IN; /* 0x2D0: Input position */
102  __R uint32_t REV_IN; /* 0x2D4: Input revolution */
103  __R uint32_t SPD_IN; /* 0x2D8: Input speed */
104  __R uint32_t ACC_IN; /* 0x2DC: Input accelerate */
105  __R uint8_t RESERVED2[4]; /* 0x2E0 - 0x2E3: Reserved */
106  __R uint32_t UPD_STS; /* 0x2E4: Update status */
107  __R uint8_t RESERVED3[24]; /* 0x2E8 - 0x2FF: Reserved */
108  } POS;
109  struct {
110  __RW uint32_t INT_EN; /* 0x300: Interrupt Enable */
111  __W uint32_t INT_FLAG; /* 0x304: Interrupt flag */
112  __R uint32_t INT_STS; /* 0x308: Interrupt status */
113  __R uint8_t RESERVED0[4]; /* 0x30C - 0x30F: Reserved */
114  __RW uint32_t POINTER0; /* 0x310: Match pointer 0 */
115  __RW uint32_t POINTER1; /* 0x314: Match pointer 1 */
116  __RW uint32_t INSTR0; /* 0x318: Match instruction 0 */
117  __RW uint32_t INSTR1; /* 0x31C: Match instruction 1 */
118  } IRQ;
119  __RW uint32_t DMA_EN; /* 0x320: DMA Enable */
120  __R uint8_t RESERVED0[220]; /* 0x324 - 0x3FF: Reserved */
121  } CTRL[4];
122  __R uint8_t RESERVED0[9216]; /* 0x1000 - 0x33FF: Reserved */
123  __RW uint32_t INSTR[128]; /* 0x3400 - 0x35FC: Instructions */
124  __R uint8_t RESERVED1[512]; /* 0x3600 - 0x37FF: Reserved */
125  struct {
126  __RW uint32_t MODE; /* 0x3800: */
127  __RW uint32_t IDX; /* 0x3804: Data register bit index */
128  __RW uint32_t GOLD; /* 0x3808: Gold data for data check */
129  __RW uint32_t CRCINIT; /* 0x380C: CRC calculation initial vector */
130  __RW uint32_t CRCPOLY; /* 0x3810: CRC calculation polynomial */
131  __R uint8_t RESERVED0[12]; /* 0x3814 - 0x381F: Reserved */
132  __RW uint32_t DATA; /* 0x3820: Data value */
133  __RW uint32_t SET; /* 0x3824: Data bit set */
134  __RW uint32_t CLR; /* 0x3828: Data bit clear */
135  __RW uint32_t INV; /* 0x382C: Data bit invert */
136  __R uint32_t IN; /* 0x3830: Data input */
137  __R uint32_t OUT; /* 0x3834: Data output */
138  __RW uint32_t STS; /* 0x3838: Data status */
139  __R uint8_t RESERVED1[4]; /* 0x383C - 0x383F: Reserved */
140  } DAT[18];
141 } SEI_Type;
142 
143 
144 /* Bitfield definition for register of struct array CTRL: CTRL */
145 /*
146  * WATCH (RW)
147  *
148  * Enable watch dog
149  * 0: Watch dog disabled
150  * 1: Watch dog enabled
151  */
152 #define SEI_CTRL_ENGINE_CTRL_WATCH_MASK (0x1000000UL)
153 #define SEI_CTRL_ENGINE_CTRL_WATCH_SHIFT (24U)
154 #define SEI_CTRL_ENGINE_CTRL_WATCH_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_WATCH_SHIFT) & SEI_CTRL_ENGINE_CTRL_WATCH_MASK)
155 #define SEI_CTRL_ENGINE_CTRL_WATCH_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_WATCH_MASK) >> SEI_CTRL_ENGINE_CTRL_WATCH_SHIFT)
156 
157 /*
158  * ARMING (RW)
159  *
160  * Wait for trigger before excuting
161  * 0: Execute on enable
162  * 1: Wait trigger before exection after enabled
163  */
164 #define SEI_CTRL_ENGINE_CTRL_ARMING_MASK (0x10000UL)
165 #define SEI_CTRL_ENGINE_CTRL_ARMING_SHIFT (16U)
166 #define SEI_CTRL_ENGINE_CTRL_ARMING_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_ARMING_SHIFT) & SEI_CTRL_ENGINE_CTRL_ARMING_MASK)
167 #define SEI_CTRL_ENGINE_CTRL_ARMING_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_ARMING_MASK) >> SEI_CTRL_ENGINE_CTRL_ARMING_SHIFT)
168 
169 /*
170  * EXCEPT (RW)
171  *
172  * Explain timout as exception
173  * 0: when timeout, pointer move to next instruction
174  * 1: when timeout, pointer jump to timeout vector
175  */
176 #define SEI_CTRL_ENGINE_CTRL_EXCEPT_MASK (0x100U)
177 #define SEI_CTRL_ENGINE_CTRL_EXCEPT_SHIFT (8U)
178 #define SEI_CTRL_ENGINE_CTRL_EXCEPT_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_EXCEPT_SHIFT) & SEI_CTRL_ENGINE_CTRL_EXCEPT_MASK)
179 #define SEI_CTRL_ENGINE_CTRL_EXCEPT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_EXCEPT_MASK) >> SEI_CTRL_ENGINE_CTRL_EXCEPT_SHIFT)
180 
181 /*
182  * REWIND (RW)
183  *
184  * Rewind execution pointer
185  * 0: run
186  * 1: clean status and rewind
187  */
188 #define SEI_CTRL_ENGINE_CTRL_REWIND_MASK (0x10U)
189 #define SEI_CTRL_ENGINE_CTRL_REWIND_SHIFT (4U)
190 #define SEI_CTRL_ENGINE_CTRL_REWIND_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_REWIND_SHIFT) & SEI_CTRL_ENGINE_CTRL_REWIND_MASK)
191 #define SEI_CTRL_ENGINE_CTRL_REWIND_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_REWIND_MASK) >> SEI_CTRL_ENGINE_CTRL_REWIND_SHIFT)
192 
193 /*
194  * ENABLE (RW)
195  *
196  * Enable
197  * 0: disable
198  * 1: enable
199  */
200 #define SEI_CTRL_ENGINE_CTRL_ENABLE_MASK (0x1U)
201 #define SEI_CTRL_ENGINE_CTRL_ENABLE_SHIFT (0U)
202 #define SEI_CTRL_ENGINE_CTRL_ENABLE_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_ENABLE_SHIFT) & SEI_CTRL_ENGINE_CTRL_ENABLE_MASK)
203 #define SEI_CTRL_ENGINE_CTRL_ENABLE_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_ENABLE_MASK) >> SEI_CTRL_ENGINE_CTRL_ENABLE_SHIFT)
204 
205 /* Bitfield definition for register of struct array CTRL: PTR_CFG */
206 /*
207  * DAT_CDM (RW)
208  *
209  * Select DATA register to receive CDM bit in BiSSC slave mode
210  * 0: ignore
211  * 1: command
212  * 2: data register 2
213  * 3: data register 3
214  * ...
215  * 29:data register 29
216  * 30: value 0 when send, ignore in receive
217  * 31: value1 when send, ignore in receive
218  */
219 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_MASK (0x1F000000UL)
220 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SHIFT (24U)
221 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_MASK)
222 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SHIFT)
223 
224 /*
225  * DAT_BASE (RW)
226  *
227  * Bias for data register access, if calculated index bigger than 32, index will wrap around
228  * 0: real data index
229  * 1: access index is 1 greater than instruction address
230  * 2: access index is 2 greater than instruction address
231  * ...
232  * 31: access index is 31 greater than instruction address
233  */
234 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_MASK (0x1F0000UL)
235 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SHIFT (16U)
236 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_MASK)
237 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SHIFT)
238 
239 /*
240  * POINTER_WDOG (RW)
241  *
242  * Pointer to the instruction that the program starts executing after the instruction timeout. The timeout is WDOG_TIME
243  */
244 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_MASK (0xFF00U)
245 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SHIFT (8U)
246 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_MASK)
247 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SHIFT)
248 
249 /*
250  * POINTER_INIT (RW)
251  *
252  * Initial execute pointer
253  */
254 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_MASK (0xFFU)
255 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SHIFT (0U)
256 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_MASK)
257 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SHIFT)
258 
259 /* Bitfield definition for register of struct array CTRL: WDG_CFG */
260 /*
261  * WDOG_TIME (RW)
262  *
263  * Time out count for each instruction, counter in bit time.
264  */
265 #define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_MASK (0xFFFFU)
266 #define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SHIFT (0U)
267 #define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SHIFT) & SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_MASK)
268 #define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_MASK) >> SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SHIFT)
269 
270 /* Bitfield definition for register of struct array CTRL: EXE_STA */
271 /*
272  * TRIGERED (RO)
273  *
274  * Execution has been triggered
275  * 0: Execution not triggered
276  * 1: Execution triggered
277  */
278 #define SEI_CTRL_ENGINE_EXE_STA_TRIGERED_MASK (0x100000UL)
279 #define SEI_CTRL_ENGINE_EXE_STA_TRIGERED_SHIFT (20U)
280 #define SEI_CTRL_ENGINE_EXE_STA_TRIGERED_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_TRIGERED_MASK) >> SEI_CTRL_ENGINE_EXE_STA_TRIGERED_SHIFT)
281 
282 /*
283  * ARMED (RO)
284  *
285  * Waiting for trigger for execution
286  * 0: Not in waiting status
287  * 1: In waiting status
288  */
289 #define SEI_CTRL_ENGINE_EXE_STA_ARMED_MASK (0x10000UL)
290 #define SEI_CTRL_ENGINE_EXE_STA_ARMED_SHIFT (16U)
291 #define SEI_CTRL_ENGINE_EXE_STA_ARMED_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_ARMED_MASK) >> SEI_CTRL_ENGINE_EXE_STA_ARMED_SHIFT)
292 
293 /*
294  * EXPIRE (RO)
295  *
296  * Watchdog timer expired
297  * 0: Not expired
298  * 1: Expired
299  */
300 #define SEI_CTRL_ENGINE_EXE_STA_EXPIRE_MASK (0x100U)
301 #define SEI_CTRL_ENGINE_EXE_STA_EXPIRE_SHIFT (8U)
302 #define SEI_CTRL_ENGINE_EXE_STA_EXPIRE_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_EXPIRE_MASK) >> SEI_CTRL_ENGINE_EXE_STA_EXPIRE_SHIFT)
303 
304 /*
305  * STALL (RO)
306  *
307  * Program finished
308  * 0: Program is executing
309  * 1: Program finished
310  */
311 #define SEI_CTRL_ENGINE_EXE_STA_STALL_MASK (0x1U)
312 #define SEI_CTRL_ENGINE_EXE_STA_STALL_SHIFT (0U)
313 #define SEI_CTRL_ENGINE_EXE_STA_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_STALL_MASK) >> SEI_CTRL_ENGINE_EXE_STA_STALL_SHIFT)
314 
315 /* Bitfield definition for register of struct array CTRL: EXE_PTR */
316 /*
317  * HALT_CNT (RO)
318  *
319  * Halt count in halt instrution
320  */
321 #define SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_MASK (0x1F000000UL)
322 #define SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_SHIFT (24U)
323 #define SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_MASK) >> SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_SHIFT)
324 
325 /*
326  * BIT_CNT (RO)
327  *
328  * Bit count in send and receive instruction execution
329  */
330 #define SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_MASK (0x1F0000UL)
331 #define SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_SHIFT (16U)
332 #define SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_MASK) >> SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_SHIFT)
333 
334 /*
335  * POINTER (RO)
336  *
337  * Current program pointer
338  */
339 #define SEI_CTRL_ENGINE_EXE_PTR_POINTER_MASK (0xFFU)
340 #define SEI_CTRL_ENGINE_EXE_PTR_POINTER_SHIFT (0U)
341 #define SEI_CTRL_ENGINE_EXE_PTR_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_PTR_POINTER_MASK) >> SEI_CTRL_ENGINE_EXE_PTR_POINTER_SHIFT)
342 
343 /* Bitfield definition for register of struct array CTRL: EXE_INST */
344 /*
345  * INST (RO)
346  *
347  * Current instruction
348  */
349 #define SEI_CTRL_ENGINE_EXE_INST_INST_MASK (0xFFFFFFFFUL)
350 #define SEI_CTRL_ENGINE_EXE_INST_INST_SHIFT (0U)
351 #define SEI_CTRL_ENGINE_EXE_INST_INST_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_INST_INST_MASK) >> SEI_CTRL_ENGINE_EXE_INST_INST_SHIFT)
352 
353 /* Bitfield definition for register of struct array CTRL: WDG_STA */
354 /*
355  * WDOG_CNT (RO)
356  *
357  * Current watch dog counter value
358  */
359 #define SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_MASK (0xFFFFU)
360 #define SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_SHIFT (0U)
361 #define SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_MASK) >> SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_SHIFT)
362 
363 /* Bitfield definition for register of struct array CTRL: CTRL */
364 /*
365  * TRISMP (RW)
366  *
367  * Tipple sampe
368  * 0: sample 1 time for data transition
369  * 1: sample 3 times in receive and result in 2oo3
370  */
371 #define SEI_CTRL_XCVR_CTRL_TRISMP_MASK (0x1000U)
372 #define SEI_CTRL_XCVR_CTRL_TRISMP_SHIFT (12U)
373 #define SEI_CTRL_XCVR_CTRL_TRISMP_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_TRISMP_SHIFT) & SEI_CTRL_XCVR_CTRL_TRISMP_MASK)
374 #define SEI_CTRL_XCVR_CTRL_TRISMP_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_TRISMP_MASK) >> SEI_CTRL_XCVR_CTRL_TRISMP_SHIFT)
375 
376 /*
377  * PAR_CLR (WC)
378  *
379  * Clear parity error, this is a self clear bit
380  * 0: no effect
381  * 1: clear parity error
382  */
383 #define SEI_CTRL_XCVR_CTRL_PAR_CLR_MASK (0x100U)
384 #define SEI_CTRL_XCVR_CTRL_PAR_CLR_SHIFT (8U)
385 #define SEI_CTRL_XCVR_CTRL_PAR_CLR_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_PAR_CLR_SHIFT) & SEI_CTRL_XCVR_CTRL_PAR_CLR_MASK)
386 #define SEI_CTRL_XCVR_CTRL_PAR_CLR_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_PAR_CLR_MASK) >> SEI_CTRL_XCVR_CTRL_PAR_CLR_SHIFT)
387 
388 /*
389  * RESTART (WC)
390  *
391  * Restart transceiver, this is a self clear bit
392  * 0: no effect
393  * 1: reset transceiver
394  */
395 #define SEI_CTRL_XCVR_CTRL_RESTART_MASK (0x10U)
396 #define SEI_CTRL_XCVR_CTRL_RESTART_SHIFT (4U)
397 #define SEI_CTRL_XCVR_CTRL_RESTART_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_RESTART_SHIFT) & SEI_CTRL_XCVR_CTRL_RESTART_MASK)
398 #define SEI_CTRL_XCVR_CTRL_RESTART_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_RESTART_MASK) >> SEI_CTRL_XCVR_CTRL_RESTART_SHIFT)
399 
400 /*
401  * MODE (RW)
402  *
403  * Transceiver mode
404  * 0: synchronous master
405  * 1: synchronous slave
406  * 2: asynchronous mode
407  * 3: asynchronous mode
408  */
409 #define SEI_CTRL_XCVR_CTRL_MODE_MASK (0x3U)
410 #define SEI_CTRL_XCVR_CTRL_MODE_SHIFT (0U)
411 #define SEI_CTRL_XCVR_CTRL_MODE_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_MODE_SHIFT) & SEI_CTRL_XCVR_CTRL_MODE_MASK)
412 #define SEI_CTRL_XCVR_CTRL_MODE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_MODE_MASK) >> SEI_CTRL_XCVR_CTRL_MODE_SHIFT)
413 
414 /* Bitfield definition for register of struct array CTRL: TYPE_CFG */
415 /*
416  * WAIT_LEN (RW)
417  *
418  * Number of extra stop bit for asynchronous mode
419  * 0: 1 bit
420  * 1: 2 bit
421  * ...
422  * 255: 256 bit
423  */
424 #define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_MASK (0xFF000000UL)
425 #define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SHIFT (24U)
426 #define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_MASK)
427 #define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SHIFT)
428 
429 /*
430  * DATA_LEN (RW)
431  *
432  * Number of data bit for asynchronous mode
433  * 0: 1 bit
434  * 1: 2 bit
435  * ...
436  * 31: 32 bit
437  */
438 #define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_MASK (0x1F0000UL)
439 #define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SHIFT (16U)
440 #define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_MASK)
441 #define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SHIFT)
442 
443 /*
444  * PAR_POL (RW)
445  *
446  * Polarity of parity for asynchronous mode
447  * 0: even
448  * 1: odd
449  */
450 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_MASK (0x200U)
451 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SHIFT (9U)
452 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_MASK)
453 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SHIFT)
454 
455 /*
456  * PAR_EN (RW)
457  *
458  * enable parity check for asynchronous mode
459  * 0: disable
460  * 1: enable
461  */
462 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_MASK (0x100U)
463 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SHIFT (8U)
464 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_MASK)
465 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SHIFT)
466 
467 /*
468  * DA_IDLEZ (RW)
469  *
470  * Idle state driver of data line
471  * 0: output
472  * 1: high-Z
473  */
474 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_MASK (0x8U)
475 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SHIFT (3U)
476 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_MASK)
477 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SHIFT)
478 
479 /*
480  * CK_IDLEZ (RW)
481  *
482  * Idle state driver of clock line
483  * 0: output
484  * 1: high-Z
485  */
486 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_MASK (0x4U)
487 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SHIFT (2U)
488 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_MASK)
489 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SHIFT)
490 
491 /*
492  * DA_IDLEV (RW)
493  *
494  * Idle state value of data line
495  * 0: data'0'
496  * 1: data'1'
497  */
498 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_MASK (0x2U)
499 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SHIFT (1U)
500 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_MASK)
501 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SHIFT)
502 
503 /*
504  * CK_IDLEV (RW)
505  *
506  * Idle state value of clock line
507  * 0: data'0'
508  * 1: data'1'
509  */
510 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_MASK (0x1U)
511 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SHIFT (0U)
512 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_MASK)
513 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SHIFT)
514 
515 /* Bitfield definition for register of struct array CTRL: BAUD_CFG */
516 /*
517  * SYNC_POINT (RW)
518  *
519  * Baud synchronous time, minmum bit time
520  */
521 #define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_MASK (0xFFFF0000UL)
522 #define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SHIFT (16U)
523 #define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SHIFT) & SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_MASK)
524 #define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_MASK) >> SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SHIFT)
525 
526 /*
527  * BAUD_DIV (RW)
528  *
529  * Baud rate, bit time in system clock cycle
530  */
531 #define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_MASK (0xFFFFU)
532 #define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SHIFT (0U)
533 #define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SHIFT) & SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_MASK)
534 #define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_MASK) >> SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SHIFT)
535 
536 /* Bitfield definition for register of struct array CTRL: DATA_CFG */
537 /*
538  * TXD_POINT (RW)
539  *
540  * data transmit point in system clcok cycle
541  */
542 #define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_MASK (0xFFFF0000UL)
543 #define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SHIFT (16U)
544 #define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SHIFT) & SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_MASK)
545 #define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_MASK) >> SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SHIFT)
546 
547 /*
548  * RXD_POINT (RW)
549  *
550  * data receive point in system clcok cycle
551  */
552 #define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_MASK (0xFFFFU)
553 #define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SHIFT (0U)
554 #define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SHIFT) & SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_MASK)
555 #define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_MASK) >> SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SHIFT)
556 
557 /* Bitfield definition for register of struct array CTRL: CLK_CFG */
558 /*
559  * CK1_POINT (RW)
560  *
561  * clock point 1 in system clcok cycle
562  */
563 #define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_MASK (0xFFFF0000UL)
564 #define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SHIFT (16U)
565 #define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SHIFT) & SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_MASK)
566 #define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_MASK) >> SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SHIFT)
567 
568 /*
569  * CK0_POINT (RW)
570  *
571  * clock point 0 in system clcok cycle
572  */
573 #define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_MASK (0xFFFFU)
574 #define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SHIFT (0U)
575 #define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SHIFT) & SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_MASK)
576 #define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_MASK) >> SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SHIFT)
577 
578 /* Bitfield definition for register of struct array CTRL: PIN */
579 /*
580  * OE_CK (RO)
581  *
582  * CK drive state
583  * 0: input
584  * 1: output
585  */
586 #define SEI_CTRL_XCVR_PIN_OE_CK_MASK (0x4000000UL)
587 #define SEI_CTRL_XCVR_PIN_OE_CK_SHIFT (26U)
588 #define SEI_CTRL_XCVR_PIN_OE_CK_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_CK_MASK) >> SEI_CTRL_XCVR_PIN_OE_CK_SHIFT)
589 
590 /*
591  * DI_CK (RO)
592  *
593  * CK state
594  * 0: data 0
595  * 1: data 1
596  */
597 #define SEI_CTRL_XCVR_PIN_DI_CK_MASK (0x2000000UL)
598 #define SEI_CTRL_XCVR_PIN_DI_CK_SHIFT (25U)
599 #define SEI_CTRL_XCVR_PIN_DI_CK_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_CK_MASK) >> SEI_CTRL_XCVR_PIN_DI_CK_SHIFT)
600 
601 /*
602  * DO_CK (RO)
603  *
604  * CK output
605  * 0: data 0
606  * 1: data 1
607  */
608 #define SEI_CTRL_XCVR_PIN_DO_CK_MASK (0x1000000UL)
609 #define SEI_CTRL_XCVR_PIN_DO_CK_SHIFT (24U)
610 #define SEI_CTRL_XCVR_PIN_DO_CK_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_CK_MASK) >> SEI_CTRL_XCVR_PIN_DO_CK_SHIFT)
611 
612 /*
613  * OE_RX (RO)
614  *
615  * RX drive state
616  * 0: input
617  * 1: output
618  */
619 #define SEI_CTRL_XCVR_PIN_OE_RX_MASK (0x40000UL)
620 #define SEI_CTRL_XCVR_PIN_OE_RX_SHIFT (18U)
621 #define SEI_CTRL_XCVR_PIN_OE_RX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_RX_MASK) >> SEI_CTRL_XCVR_PIN_OE_RX_SHIFT)
622 
623 /*
624  * DI_RX (RO)
625  *
626  * RX state
627  * 0: data 0
628  * 1: data 1
629  */
630 #define SEI_CTRL_XCVR_PIN_DI_RX_MASK (0x20000UL)
631 #define SEI_CTRL_XCVR_PIN_DI_RX_SHIFT (17U)
632 #define SEI_CTRL_XCVR_PIN_DI_RX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_RX_MASK) >> SEI_CTRL_XCVR_PIN_DI_RX_SHIFT)
633 
634 /*
635  * DO_RX (RO)
636  *
637  * RX output
638  * 0: data 0
639  * 1: data 1
640  */
641 #define SEI_CTRL_XCVR_PIN_DO_RX_MASK (0x10000UL)
642 #define SEI_CTRL_XCVR_PIN_DO_RX_SHIFT (16U)
643 #define SEI_CTRL_XCVR_PIN_DO_RX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_RX_MASK) >> SEI_CTRL_XCVR_PIN_DO_RX_SHIFT)
644 
645 /*
646  * OE_DE (RO)
647  *
648  * DE drive state
649  * 0: input
650  * 1: output
651  */
652 #define SEI_CTRL_XCVR_PIN_OE_DE_MASK (0x400U)
653 #define SEI_CTRL_XCVR_PIN_OE_DE_SHIFT (10U)
654 #define SEI_CTRL_XCVR_PIN_OE_DE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_DE_MASK) >> SEI_CTRL_XCVR_PIN_OE_DE_SHIFT)
655 
656 /*
657  * DI_DE (RO)
658  *
659  * DE state
660  * 0: data 0
661  * 1: data 1
662  */
663 #define SEI_CTRL_XCVR_PIN_DI_DE_MASK (0x200U)
664 #define SEI_CTRL_XCVR_PIN_DI_DE_SHIFT (9U)
665 #define SEI_CTRL_XCVR_PIN_DI_DE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_DE_MASK) >> SEI_CTRL_XCVR_PIN_DI_DE_SHIFT)
666 
667 /*
668  * DO_DE (RO)
669  *
670  * DE output
671  * 0: data 0
672  * 1: data 1
673  */
674 #define SEI_CTRL_XCVR_PIN_DO_DE_MASK (0x100U)
675 #define SEI_CTRL_XCVR_PIN_DO_DE_SHIFT (8U)
676 #define SEI_CTRL_XCVR_PIN_DO_DE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_DE_MASK) >> SEI_CTRL_XCVR_PIN_DO_DE_SHIFT)
677 
678 /*
679  * OE_TX (RO)
680  *
681  * TX drive state
682  * 0: input
683  * 1: output
684  */
685 #define SEI_CTRL_XCVR_PIN_OE_TX_MASK (0x4U)
686 #define SEI_CTRL_XCVR_PIN_OE_TX_SHIFT (2U)
687 #define SEI_CTRL_XCVR_PIN_OE_TX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_TX_MASK) >> SEI_CTRL_XCVR_PIN_OE_TX_SHIFT)
688 
689 /*
690  * DI_TX (RO)
691  *
692  * TX state
693  * 0: data 0
694  * 1: data 1
695  */
696 #define SEI_CTRL_XCVR_PIN_DI_TX_MASK (0x2U)
697 #define SEI_CTRL_XCVR_PIN_DI_TX_SHIFT (1U)
698 #define SEI_CTRL_XCVR_PIN_DI_TX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_TX_MASK) >> SEI_CTRL_XCVR_PIN_DI_TX_SHIFT)
699 
700 /*
701  * DO_TX (RO)
702  *
703  * TX output
704  * 0: data 0
705  * 1: data 1
706  */
707 #define SEI_CTRL_XCVR_PIN_DO_TX_MASK (0x1U)
708 #define SEI_CTRL_XCVR_PIN_DO_TX_SHIFT (0U)
709 #define SEI_CTRL_XCVR_PIN_DO_TX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_TX_MASK) >> SEI_CTRL_XCVR_PIN_DO_TX_SHIFT)
710 
711 /* Bitfield definition for register of struct array CTRL: STATE */
712 /*
713  * RECV_STATE (RO)
714  *
715  * FSM of asynchronous receive
716  */
717 #define SEI_CTRL_XCVR_STATE_RECV_STATE_MASK (0x7000000UL)
718 #define SEI_CTRL_XCVR_STATE_RECV_STATE_SHIFT (24U)
719 #define SEI_CTRL_XCVR_STATE_RECV_STATE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_STATE_RECV_STATE_MASK) >> SEI_CTRL_XCVR_STATE_RECV_STATE_SHIFT)
720 
721 /*
722  * SEND_STATE (RO)
723  *
724  * FSM of asynchronous transmit
725  */
726 #define SEI_CTRL_XCVR_STATE_SEND_STATE_MASK (0x70000UL)
727 #define SEI_CTRL_XCVR_STATE_SEND_STATE_SHIFT (16U)
728 #define SEI_CTRL_XCVR_STATE_SEND_STATE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_STATE_SEND_STATE_MASK) >> SEI_CTRL_XCVR_STATE_SEND_STATE_SHIFT)
729 
730 /* Bitfield definition for register of struct array CTRL: IN_CFG */
731 /*
732  * REWIND_EN (RW)
733  *
734  * enable rewind cmd register by LATCH
735  */
736 #define SEI_CTRL_TRG_IN_CFG_REWIND_EN_MASK (0x80000000UL)
737 #define SEI_CTRL_TRG_IN_CFG_REWIND_EN_SHIFT (31U)
738 #define SEI_CTRL_TRG_IN_CFG_REWIND_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_REWIND_EN_SHIFT) & SEI_CTRL_TRG_IN_CFG_REWIND_EN_MASK)
739 #define SEI_CTRL_TRG_IN_CFG_REWIND_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_REWIND_EN_MASK) >> SEI_CTRL_TRG_IN_CFG_REWIND_EN_SHIFT)
740 
741 /*
742  * REWIND_SEL (RW)
743  *
744  * select one LATCH to rewind CMD register
745  * 0:LATCH[0]
746  * 1:LATCH[1]
747  * 2:LATCH[2]
748  * 3:LATCH[3]
749  */
750 #define SEI_CTRL_TRG_IN_CFG_REWIND_SEL_MASK (0x3000000UL)
751 #define SEI_CTRL_TRG_IN_CFG_REWIND_SEL_SHIFT (24U)
752 #define SEI_CTRL_TRG_IN_CFG_REWIND_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_REWIND_SEL_SHIFT) & SEI_CTRL_TRG_IN_CFG_REWIND_SEL_MASK)
753 #define SEI_CTRL_TRG_IN_CFG_REWIND_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_REWIND_SEL_MASK) >> SEI_CTRL_TRG_IN_CFG_REWIND_SEL_SHIFT)
754 
755 /*
756  * PRD_EN (RW)
757  *
758  * Enable period trigger (tigger 2)
759  * 0: periodical trigger disabled
760  * 1: periodical trigger enabled
761  */
762 #define SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK (0x800000UL)
763 #define SEI_CTRL_TRG_IN_CFG_PRD_EN_SHIFT (23U)
764 #define SEI_CTRL_TRG_IN_CFG_PRD_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_PRD_EN_SHIFT) & SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK)
765 #define SEI_CTRL_TRG_IN_CFG_PRD_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK) >> SEI_CTRL_TRG_IN_CFG_PRD_EN_SHIFT)
766 
767 /*
768  * SYNC_SEL (RW)
769  *
770  * Synchronize sigal selection (tigger 2)
771  * 0: trigger in 0
772  * 1: trigger in 1
773  * ...
774  * 7: trigger in 7
775  */
776 #define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_MASK (0x70000UL)
777 #define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SHIFT (16U)
778 #define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SHIFT) & SEI_CTRL_TRG_IN_CFG_SYNC_SEL_MASK)
779 #define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_SYNC_SEL_MASK) >> SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SHIFT)
780 
781 /*
782  * IN1_EN (RW)
783  *
784  * Enable trigger 1
785  * 0: disable trigger 1
786  * 1: enable trigger 1
787  */
788 #define SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK (0x8000U)
789 #define SEI_CTRL_TRG_IN_CFG_IN1_EN_SHIFT (15U)
790 #define SEI_CTRL_TRG_IN_CFG_IN1_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN1_EN_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK)
791 #define SEI_CTRL_TRG_IN_CFG_IN1_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK) >> SEI_CTRL_TRG_IN_CFG_IN1_EN_SHIFT)
792 
793 /*
794  * IN1_SEL (RW)
795  *
796  * Trigger 1 sigal selection
797  * 0: trigger in 0
798  * 1: trigger in 1
799  * ...
800  * 7: trigger in 7
801  */
802 #define SEI_CTRL_TRG_IN_CFG_IN1_SEL_MASK (0x700U)
803 #define SEI_CTRL_TRG_IN_CFG_IN1_SEL_SHIFT (8U)
804 #define SEI_CTRL_TRG_IN_CFG_IN1_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN1_SEL_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN1_SEL_MASK)
805 #define SEI_CTRL_TRG_IN_CFG_IN1_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN1_SEL_MASK) >> SEI_CTRL_TRG_IN_CFG_IN1_SEL_SHIFT)
806 
807 /*
808  * IN0_EN (RW)
809  *
810  * Enable trigger 0
811  * 0: disable trigger 1
812  * 1: enable trigger 1
813  */
814 #define SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK (0x80U)
815 #define SEI_CTRL_TRG_IN_CFG_IN0_EN_SHIFT (7U)
816 #define SEI_CTRL_TRG_IN_CFG_IN0_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN0_EN_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK)
817 #define SEI_CTRL_TRG_IN_CFG_IN0_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK) >> SEI_CTRL_TRG_IN_CFG_IN0_EN_SHIFT)
818 
819 /*
820  * IN0_SEL (RW)
821  *
822  * Trigger 0 sigal selection
823  * 0: trigger in 0
824  * 1: trigger in 1
825  * ...
826  * 7: trigger in 7
827  */
828 #define SEI_CTRL_TRG_IN_CFG_IN0_SEL_MASK (0x7U)
829 #define SEI_CTRL_TRG_IN_CFG_IN0_SEL_SHIFT (0U)
830 #define SEI_CTRL_TRG_IN_CFG_IN0_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN0_SEL_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN0_SEL_MASK)
831 #define SEI_CTRL_TRG_IN_CFG_IN0_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN0_SEL_MASK) >> SEI_CTRL_TRG_IN_CFG_IN0_SEL_SHIFT)
832 
833 /* Bitfield definition for register of struct array CTRL: SW */
834 /*
835  * SOFT (WC)
836  *
837  * Software trigger (tigger 3). this bit is self-clear
838  * 0: trigger source disabled
839  * 1: trigger source enabled
840  */
841 #define SEI_CTRL_TRG_SW_SOFT_MASK (0x1U)
842 #define SEI_CTRL_TRG_SW_SOFT_SHIFT (0U)
843 #define SEI_CTRL_TRG_SW_SOFT_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_SW_SOFT_SHIFT) & SEI_CTRL_TRG_SW_SOFT_MASK)
844 #define SEI_CTRL_TRG_SW_SOFT_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_SW_SOFT_MASK) >> SEI_CTRL_TRG_SW_SOFT_SHIFT)
845 
846 /* Bitfield definition for register of struct array CTRL: PRD_CFG */
847 /*
848  * ARMING (RW)
849  *
850  * Wait for trigger synchronous before trigger
851  * 0: Trigger directly
852  * 1: Wait trigger source before period trigger
853  */
854 #define SEI_CTRL_TRG_PRD_CFG_ARMING_MASK (0x10000UL)
855 #define SEI_CTRL_TRG_PRD_CFG_ARMING_SHIFT (16U)
856 #define SEI_CTRL_TRG_PRD_CFG_ARMING_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_PRD_CFG_ARMING_SHIFT) & SEI_CTRL_TRG_PRD_CFG_ARMING_MASK)
857 #define SEI_CTRL_TRG_PRD_CFG_ARMING_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_CFG_ARMING_MASK) >> SEI_CTRL_TRG_PRD_CFG_ARMING_SHIFT)
858 
859 /*
860  * SYNC (RW)
861  *
862  * Synchronous
863  * 0: Not synchronous
864  * 1: Synchronous every trigger source
865  */
866 #define SEI_CTRL_TRG_PRD_CFG_SYNC_MASK (0x1U)
867 #define SEI_CTRL_TRG_PRD_CFG_SYNC_SHIFT (0U)
868 #define SEI_CTRL_TRG_PRD_CFG_SYNC_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_PRD_CFG_SYNC_SHIFT) & SEI_CTRL_TRG_PRD_CFG_SYNC_MASK)
869 #define SEI_CTRL_TRG_PRD_CFG_SYNC_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_CFG_SYNC_MASK) >> SEI_CTRL_TRG_PRD_CFG_SYNC_SHIFT)
870 
871 /* Bitfield definition for register of struct array CTRL: PRD */
872 /*
873  * PERIOD (RW)
874  *
875  * Trigger period
876  */
877 #define SEI_CTRL_TRG_PRD_PERIOD_MASK (0xFFFFFFFFUL)
878 #define SEI_CTRL_TRG_PRD_PERIOD_SHIFT (0U)
879 #define SEI_CTRL_TRG_PRD_PERIOD_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_PRD_PERIOD_SHIFT) & SEI_CTRL_TRG_PRD_PERIOD_MASK)
880 #define SEI_CTRL_TRG_PRD_PERIOD_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_PERIOD_MASK) >> SEI_CTRL_TRG_PRD_PERIOD_SHIFT)
881 
882 /* Bitfield definition for register of struct array CTRL: OUT_CFG */
883 /*
884  * OUT3_EN (RW)
885  *
886  * Enable trigger 3
887  * 0: disable trigger 3
888  * 1: enable trigger 3
889  */
890 #define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_MASK (0x80000000UL)
891 #define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SHIFT (31U)
892 #define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT3_EN_MASK)
893 #define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT3_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SHIFT)
894 
895 /*
896  * OUT3_SEL (RW)
897  *
898  * Trigger 3 sigal selection
899  * 0: trigger out 0
900  * 1: trigger out 1
901  * ...
902  * 7: trigger out 7
903  */
904 #define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_MASK (0x7000000UL)
905 #define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SHIFT (24U)
906 #define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_MASK)
907 #define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SHIFT)
908 
909 /*
910  * OUT2_EN (RW)
911  *
912  * Enable trigger 2
913  * 0: disable trigger 2
914  * 1: enable trigger 2
915  */
916 #define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_MASK (0x800000UL)
917 #define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SHIFT (23U)
918 #define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT2_EN_MASK)
919 #define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT2_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SHIFT)
920 
921 /*
922  * OUT2_SEL (RW)
923  *
924  * Trigger 2 sigal selection
925  * 0: trigger out 0
926  * 1: trigger out 1
927  * ...
928  * 7: trigger out 7
929  */
930 #define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_MASK (0x70000UL)
931 #define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SHIFT (16U)
932 #define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_MASK)
933 #define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SHIFT)
934 
935 /*
936  * OUT1_EN (RW)
937  *
938  * Enable trigger 1
939  * 0: disable trigger 1
940  * 1: enable trigger 1
941  */
942 #define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_MASK (0x8000U)
943 #define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SHIFT (15U)
944 #define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT1_EN_MASK)
945 #define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT1_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SHIFT)
946 
947 /*
948  * OUT1_SEL (RW)
949  *
950  * Trigger 1 sigal selection
951  * 0: trigger out 0
952  * 1: trigger out 1
953  * ...
954  * 7: trigger out 7
955  */
956 #define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_MASK (0x700U)
957 #define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SHIFT (8U)
958 #define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_MASK)
959 #define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SHIFT)
960 
961 /*
962  * OUT0_EN (RW)
963  *
964  * Enable trigger 0
965  * 0: disable trigger 1
966  * 1: enable trigger 1
967  */
968 #define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_MASK (0x80U)
969 #define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SHIFT (7U)
970 #define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT0_EN_MASK)
971 #define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT0_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SHIFT)
972 
973 /*
974  * OUT0_SEL (RW)
975  *
976  * Trigger 0 sigal selection
977  * 0: trigger out 0
978  * 1: trigger out 1
979  * ...
980  * 7: trigger out 7
981  */
982 #define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_MASK (0x7U)
983 #define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SHIFT (0U)
984 #define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_MASK)
985 #define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SHIFT)
986 
987 /* Bitfield definition for register of struct array CTRL: PRD_STS */
988 /*
989  * TRIGERED (RO)
990  *
991  * Period has been triggered
992  * 0: Not triggered
993  * 1: Triggered
994  */
995 #define SEI_CTRL_TRG_PRD_STS_TRIGERED_MASK (0x100000UL)
996 #define SEI_CTRL_TRG_PRD_STS_TRIGERED_SHIFT (20U)
997 #define SEI_CTRL_TRG_PRD_STS_TRIGERED_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_STS_TRIGERED_MASK) >> SEI_CTRL_TRG_PRD_STS_TRIGERED_SHIFT)
998 
999 /*
1000  * ARMED (RO)
1001  *
1002  * Waiting for trigger
1003  * 0: Not in waiting status
1004  * 1: In waiting status
1005  */
1006 #define SEI_CTRL_TRG_PRD_STS_ARMED_MASK (0x10000UL)
1007 #define SEI_CTRL_TRG_PRD_STS_ARMED_SHIFT (16U)
1008 #define SEI_CTRL_TRG_PRD_STS_ARMED_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_STS_ARMED_MASK) >> SEI_CTRL_TRG_PRD_STS_ARMED_SHIFT)
1009 
1010 /* Bitfield definition for register of struct array CTRL: PRD_CNT */
1011 /*
1012  * PERIOD_CNT (RO)
1013  *
1014  * Trigger period counter
1015  */
1016 #define SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_MASK (0xFFFFFFFFUL)
1017 #define SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_SHIFT (0U)
1018 #define SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_MASK) >> SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_SHIFT)
1019 
1020 /* Bitfield definition for register of struct array CTRL: 0 */
1021 /*
1022  * CMD_TRIGGER0 (RW)
1023  *
1024  * Trigger command
1025  */
1026 #define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_MASK (0xFFFFFFFFUL)
1027 #define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SHIFT (0U)
1028 #define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SHIFT) & SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_MASK)
1029 #define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_MASK) >> SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SHIFT)
1030 
1031 /* Bitfield definition for register of struct array CTRL: 0 */
1032 /*
1033  * TRIGGER0_TIME (RO)
1034  *
1035  * Trigger time
1036  */
1037 #define SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_MASK (0xFFFFFFFFUL)
1038 #define SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_SHIFT (0U)
1039 #define SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_MASK) >> SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_SHIFT)
1040 
1041 /* Bitfield definition for register of struct array CTRL: MODE */
1042 /*
1043  * WLEN (RW)
1044  *
1045  * word length
1046  * 0: 1 bit
1047  * 1: 2 bit
1048  * ...
1049  * 31: 32 bit
1050  */
1051 #define SEI_CTRL_CMD_MODE_WLEN_MASK (0x1F0000UL)
1052 #define SEI_CTRL_CMD_MODE_WLEN_SHIFT (16U)
1053 #define SEI_CTRL_CMD_MODE_WLEN_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_WLEN_SHIFT) & SEI_CTRL_CMD_MODE_WLEN_MASK)
1054 #define SEI_CTRL_CMD_MODE_WLEN_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_WLEN_MASK) >> SEI_CTRL_CMD_MODE_WLEN_SHIFT)
1055 
1056 /*
1057  * WORDER (RW)
1058  *
1059  * word order
1060  * 0: sample as bit order
1061  * 1: different from bit order
1062  */
1063 #define SEI_CTRL_CMD_MODE_WORDER_MASK (0x800U)
1064 #define SEI_CTRL_CMD_MODE_WORDER_SHIFT (11U)
1065 #define SEI_CTRL_CMD_MODE_WORDER_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_WORDER_SHIFT) & SEI_CTRL_CMD_MODE_WORDER_MASK)
1066 #define SEI_CTRL_CMD_MODE_WORDER_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_WORDER_MASK) >> SEI_CTRL_CMD_MODE_WORDER_SHIFT)
1067 
1068 /*
1069  * BORDER (RW)
1070  *
1071  * bit order
1072  * 0: LSB first
1073  * 1: MSB first
1074  */
1075 #define SEI_CTRL_CMD_MODE_BORDER_MASK (0x400U)
1076 #define SEI_CTRL_CMD_MODE_BORDER_SHIFT (10U)
1077 #define SEI_CTRL_CMD_MODE_BORDER_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_BORDER_SHIFT) & SEI_CTRL_CMD_MODE_BORDER_MASK)
1078 #define SEI_CTRL_CMD_MODE_BORDER_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_BORDER_MASK) >> SEI_CTRL_CMD_MODE_BORDER_SHIFT)
1079 
1080 /*
1081  * SIGNED (RW)
1082  *
1083  * Signed
1084  * 0: unsigned value
1085  * 1: signed value
1086  */
1087 #define SEI_CTRL_CMD_MODE_SIGNED_MASK (0x200U)
1088 #define SEI_CTRL_CMD_MODE_SIGNED_SHIFT (9U)
1089 #define SEI_CTRL_CMD_MODE_SIGNED_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_SIGNED_SHIFT) & SEI_CTRL_CMD_MODE_SIGNED_MASK)
1090 #define SEI_CTRL_CMD_MODE_SIGNED_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_SIGNED_MASK) >> SEI_CTRL_CMD_MODE_SIGNED_SHIFT)
1091 
1092 /*
1093  * REWIND (WC)
1094  *
1095  * Write 1 to rewind read/write pointer, this is a self clear bit
1096  */
1097 #define SEI_CTRL_CMD_MODE_REWIND_MASK (0x100U)
1098 #define SEI_CTRL_CMD_MODE_REWIND_SHIFT (8U)
1099 #define SEI_CTRL_CMD_MODE_REWIND_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_REWIND_SHIFT) & SEI_CTRL_CMD_MODE_REWIND_MASK)
1100 #define SEI_CTRL_CMD_MODE_REWIND_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_REWIND_MASK) >> SEI_CTRL_CMD_MODE_REWIND_SHIFT)
1101 
1102 /*
1103  * MODE (RW)
1104  *
1105  * Data mode(CMD register only support data mode)
1106  * 0: data mode
1107  * 1: check mode
1108  * 2: CRC mode
1109  */
1110 #define SEI_CTRL_CMD_MODE_MODE_MASK (0x3U)
1111 #define SEI_CTRL_CMD_MODE_MODE_SHIFT (0U)
1112 #define SEI_CTRL_CMD_MODE_MODE_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_MODE_SHIFT) & SEI_CTRL_CMD_MODE_MODE_MASK)
1113 #define SEI_CTRL_CMD_MODE_MODE_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_MODE_MASK) >> SEI_CTRL_CMD_MODE_MODE_SHIFT)
1114 
1115 /* Bitfield definition for register of struct array CTRL: IDX */
1116 /*
1117  * LAST_BIT (RW)
1118  *
1119  * Last bit index for tranceive
1120  */
1121 #define SEI_CTRL_CMD_IDX_LAST_BIT_MASK (0x1F000000UL)
1122 #define SEI_CTRL_CMD_IDX_LAST_BIT_SHIFT (24U)
1123 #define SEI_CTRL_CMD_IDX_LAST_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_LAST_BIT_SHIFT) & SEI_CTRL_CMD_IDX_LAST_BIT_MASK)
1124 #define SEI_CTRL_CMD_IDX_LAST_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_LAST_BIT_MASK) >> SEI_CTRL_CMD_IDX_LAST_BIT_SHIFT)
1125 
1126 /*
1127  * FIRST_BIT (RW)
1128  *
1129  * First bit index for tranceive
1130  */
1131 #define SEI_CTRL_CMD_IDX_FIRST_BIT_MASK (0x1F0000UL)
1132 #define SEI_CTRL_CMD_IDX_FIRST_BIT_SHIFT (16U)
1133 #define SEI_CTRL_CMD_IDX_FIRST_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_FIRST_BIT_SHIFT) & SEI_CTRL_CMD_IDX_FIRST_BIT_MASK)
1134 #define SEI_CTRL_CMD_IDX_FIRST_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_FIRST_BIT_MASK) >> SEI_CTRL_CMD_IDX_FIRST_BIT_SHIFT)
1135 
1136 /*
1137  * MAX_BIT (RW)
1138  *
1139  * Highest bit index
1140  */
1141 #define SEI_CTRL_CMD_IDX_MAX_BIT_MASK (0x1F00U)
1142 #define SEI_CTRL_CMD_IDX_MAX_BIT_SHIFT (8U)
1143 #define SEI_CTRL_CMD_IDX_MAX_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_MAX_BIT_SHIFT) & SEI_CTRL_CMD_IDX_MAX_BIT_MASK)
1144 #define SEI_CTRL_CMD_IDX_MAX_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_MAX_BIT_MASK) >> SEI_CTRL_CMD_IDX_MAX_BIT_SHIFT)
1145 
1146 /*
1147  * MIN_BIT (RW)
1148  *
1149  * Lowest bit index
1150  */
1151 #define SEI_CTRL_CMD_IDX_MIN_BIT_MASK (0x1FU)
1152 #define SEI_CTRL_CMD_IDX_MIN_BIT_SHIFT (0U)
1153 #define SEI_CTRL_CMD_IDX_MIN_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_MIN_BIT_SHIFT) & SEI_CTRL_CMD_IDX_MIN_BIT_MASK)
1154 #define SEI_CTRL_CMD_IDX_MIN_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_MIN_BIT_MASK) >> SEI_CTRL_CMD_IDX_MIN_BIT_SHIFT)
1155 
1156 /* Bitfield definition for register of struct array CTRL: CMD */
1157 /*
1158  * DATA (RW)
1159  *
1160  * DATA
1161  */
1162 #define SEI_CTRL_CMD_CMD_DATA_MASK (0xFFFFFFFFUL)
1163 #define SEI_CTRL_CMD_CMD_DATA_SHIFT (0U)
1164 #define SEI_CTRL_CMD_CMD_DATA_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_CMD_DATA_SHIFT) & SEI_CTRL_CMD_CMD_DATA_MASK)
1165 #define SEI_CTRL_CMD_CMD_DATA_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_CMD_DATA_MASK) >> SEI_CTRL_CMD_CMD_DATA_SHIFT)
1166 
1167 /* Bitfield definition for register of struct array CTRL: SET */
1168 /*
1169  * DATA_SET (RW)
1170  *
1171  * DATA bit set
1172  */
1173 #define SEI_CTRL_CMD_SET_DATA_SET_MASK (0xFFFFFFFFUL)
1174 #define SEI_CTRL_CMD_SET_DATA_SET_SHIFT (0U)
1175 #define SEI_CTRL_CMD_SET_DATA_SET_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_SET_DATA_SET_SHIFT) & SEI_CTRL_CMD_SET_DATA_SET_MASK)
1176 #define SEI_CTRL_CMD_SET_DATA_SET_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_SET_DATA_SET_MASK) >> SEI_CTRL_CMD_SET_DATA_SET_SHIFT)
1177 
1178 /* Bitfield definition for register of struct array CTRL: CLR */
1179 /*
1180  * DATA_CLR (RW)
1181  *
1182  * DATA bit clear
1183  */
1184 #define SEI_CTRL_CMD_CLR_DATA_CLR_MASK (0xFFFFFFFFUL)
1185 #define SEI_CTRL_CMD_CLR_DATA_CLR_SHIFT (0U)
1186 #define SEI_CTRL_CMD_CLR_DATA_CLR_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_CLR_DATA_CLR_SHIFT) & SEI_CTRL_CMD_CLR_DATA_CLR_MASK)
1187 #define SEI_CTRL_CMD_CLR_DATA_CLR_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_CLR_DATA_CLR_MASK) >> SEI_CTRL_CMD_CLR_DATA_CLR_SHIFT)
1188 
1189 /* Bitfield definition for register of struct array CTRL: INV */
1190 /*
1191  * DATA_TGL (RW)
1192  *
1193  * DATA bit toggle
1194  */
1195 #define SEI_CTRL_CMD_INV_DATA_TGL_MASK (0xFFFFFFFFUL)
1196 #define SEI_CTRL_CMD_INV_DATA_TGL_SHIFT (0U)
1197 #define SEI_CTRL_CMD_INV_DATA_TGL_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_INV_DATA_TGL_SHIFT) & SEI_CTRL_CMD_INV_DATA_TGL_MASK)
1198 #define SEI_CTRL_CMD_INV_DATA_TGL_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_INV_DATA_TGL_MASK) >> SEI_CTRL_CMD_INV_DATA_TGL_SHIFT)
1199 
1200 /* Bitfield definition for register of struct array CTRL: IN */
1201 /*
1202  * DATA_IN (RO)
1203  *
1204  * Commad input
1205  */
1206 #define SEI_CTRL_CMD_IN_DATA_IN_MASK (0xFFFFFFFFUL)
1207 #define SEI_CTRL_CMD_IN_DATA_IN_SHIFT (0U)
1208 #define SEI_CTRL_CMD_IN_DATA_IN_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IN_DATA_IN_MASK) >> SEI_CTRL_CMD_IN_DATA_IN_SHIFT)
1209 
1210 /* Bitfield definition for register of struct array CTRL: OUT */
1211 /*
1212  * DATA_OUT (RO)
1213  *
1214  * Command output
1215  */
1216 #define SEI_CTRL_CMD_OUT_DATA_OUT_MASK (0xFFFFFFFFUL)
1217 #define SEI_CTRL_CMD_OUT_DATA_OUT_SHIFT (0U)
1218 #define SEI_CTRL_CMD_OUT_DATA_OUT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_OUT_DATA_OUT_MASK) >> SEI_CTRL_CMD_OUT_DATA_OUT_SHIFT)
1219 
1220 /* Bitfield definition for register of struct array CTRL: STS */
1221 /*
1222  * WORD_IDX (RO)
1223  *
1224  * Word index
1225  */
1226 #define SEI_CTRL_CMD_STS_WORD_IDX_MASK (0x1F0000UL)
1227 #define SEI_CTRL_CMD_STS_WORD_IDX_SHIFT (16U)
1228 #define SEI_CTRL_CMD_STS_WORD_IDX_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_STS_WORD_IDX_MASK) >> SEI_CTRL_CMD_STS_WORD_IDX_SHIFT)
1229 
1230 /*
1231  * WORD_CNT (RO)
1232  *
1233  * Word counter
1234  */
1235 #define SEI_CTRL_CMD_STS_WORD_CNT_MASK (0x1F00U)
1236 #define SEI_CTRL_CMD_STS_WORD_CNT_SHIFT (8U)
1237 #define SEI_CTRL_CMD_STS_WORD_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_STS_WORD_CNT_MASK) >> SEI_CTRL_CMD_STS_WORD_CNT_SHIFT)
1238 
1239 /*
1240  * BIT_IDX (RO)
1241  *
1242  * Bit index
1243  */
1244 #define SEI_CTRL_CMD_STS_BIT_IDX_MASK (0x1FU)
1245 #define SEI_CTRL_CMD_STS_BIT_IDX_SHIFT (0U)
1246 #define SEI_CTRL_CMD_STS_BIT_IDX_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_STS_BIT_IDX_MASK) >> SEI_CTRL_CMD_STS_BIT_IDX_SHIFT)
1247 
1248 /* Bitfield definition for register of struct array CTRL: MIN */
1249 /*
1250  * CMD_MIN (RW)
1251  *
1252  * minimum command value
1253  */
1254 #define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_MASK (0xFFFFFFFFUL)
1255 #define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SHIFT (0U)
1256 #define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SHIFT) & SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_MASK)
1257 #define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_MASK) >> SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SHIFT)
1258 
1259 /* Bitfield definition for register of struct array CTRL: MAX */
1260 /*
1261  * CMD_MAX (RW)
1262  *
1263  * maximum command value
1264  */
1265 #define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_MASK (0xFFFFFFFFUL)
1266 #define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SHIFT (0U)
1267 #define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SHIFT) & SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_MASK)
1268 #define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_MASK) >> SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SHIFT)
1269 
1270 /* Bitfield definition for register of struct array CTRL: MSK */
1271 /*
1272  * CMD_MASK (RW)
1273  *
1274  * compare mask
1275  */
1276 #define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_MASK (0xFFFFFFFFUL)
1277 #define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SHIFT (0U)
1278 #define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SHIFT) & SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_MASK)
1279 #define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_MASK) >> SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SHIFT)
1280 
1281 /* Bitfield definition for register of struct array CTRL: PTA */
1282 /*
1283  * PTR3 (RW)
1284  *
1285  * pointer3
1286  */
1287 #define SEI_CTRL_CMD_TABLE_PTA_PTR3_MASK (0xFF000000UL)
1288 #define SEI_CTRL_CMD_TABLE_PTA_PTR3_SHIFT (24U)
1289 #define SEI_CTRL_CMD_TABLE_PTA_PTR3_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR3_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR3_MASK)
1290 #define SEI_CTRL_CMD_TABLE_PTA_PTR3_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR3_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR3_SHIFT)
1291 
1292 /*
1293  * PTR2 (RW)
1294  *
1295  * pointer2
1296  */
1297 #define SEI_CTRL_CMD_TABLE_PTA_PTR2_MASK (0xFF0000UL)
1298 #define SEI_CTRL_CMD_TABLE_PTA_PTR2_SHIFT (16U)
1299 #define SEI_CTRL_CMD_TABLE_PTA_PTR2_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR2_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR2_MASK)
1300 #define SEI_CTRL_CMD_TABLE_PTA_PTR2_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR2_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR2_SHIFT)
1301 
1302 /*
1303  * PTR1 (RW)
1304  *
1305  * pointer1
1306  */
1307 #define SEI_CTRL_CMD_TABLE_PTA_PTR1_MASK (0xFF00U)
1308 #define SEI_CTRL_CMD_TABLE_PTA_PTR1_SHIFT (8U)
1309 #define SEI_CTRL_CMD_TABLE_PTA_PTR1_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR1_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR1_MASK)
1310 #define SEI_CTRL_CMD_TABLE_PTA_PTR1_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR1_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR1_SHIFT)
1311 
1312 /*
1313  * PTR0 (RW)
1314  *
1315  * pointer0
1316  */
1317 #define SEI_CTRL_CMD_TABLE_PTA_PTR0_MASK (0xFFU)
1318 #define SEI_CTRL_CMD_TABLE_PTA_PTR0_SHIFT (0U)
1319 #define SEI_CTRL_CMD_TABLE_PTA_PTR0_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR0_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR0_MASK)
1320 #define SEI_CTRL_CMD_TABLE_PTA_PTR0_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR0_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR0_SHIFT)
1321 
1322 /* Bitfield definition for register of struct array CTRL: PTB */
1323 /*
1324  * PTR7 (RW)
1325  *
1326  * pointer7
1327  */
1328 #define SEI_CTRL_CMD_TABLE_PTB_PTR7_MASK (0xFF000000UL)
1329 #define SEI_CTRL_CMD_TABLE_PTB_PTR7_SHIFT (24U)
1330 #define SEI_CTRL_CMD_TABLE_PTB_PTR7_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR7_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR7_MASK)
1331 #define SEI_CTRL_CMD_TABLE_PTB_PTR7_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR7_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR7_SHIFT)
1332 
1333 /*
1334  * PTR6 (RW)
1335  *
1336  * pointer6
1337  */
1338 #define SEI_CTRL_CMD_TABLE_PTB_PTR6_MASK (0xFF0000UL)
1339 #define SEI_CTRL_CMD_TABLE_PTB_PTR6_SHIFT (16U)
1340 #define SEI_CTRL_CMD_TABLE_PTB_PTR6_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR6_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR6_MASK)
1341 #define SEI_CTRL_CMD_TABLE_PTB_PTR6_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR6_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR6_SHIFT)
1342 
1343 /*
1344  * PTR5 (RW)
1345  *
1346  * pointer5
1347  */
1348 #define SEI_CTRL_CMD_TABLE_PTB_PTR5_MASK (0xFF00U)
1349 #define SEI_CTRL_CMD_TABLE_PTB_PTR5_SHIFT (8U)
1350 #define SEI_CTRL_CMD_TABLE_PTB_PTR5_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR5_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR5_MASK)
1351 #define SEI_CTRL_CMD_TABLE_PTB_PTR5_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR5_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR5_SHIFT)
1352 
1353 /*
1354  * PTR4 (RW)
1355  *
1356  * pointer4
1357  */
1358 #define SEI_CTRL_CMD_TABLE_PTB_PTR4_MASK (0xFFU)
1359 #define SEI_CTRL_CMD_TABLE_PTB_PTR4_SHIFT (0U)
1360 #define SEI_CTRL_CMD_TABLE_PTB_PTR4_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR4_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR4_MASK)
1361 #define SEI_CTRL_CMD_TABLE_PTB_PTR4_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR4_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR4_SHIFT)
1362 
1363 /* Bitfield definition for register of struct array CTRL: 0_1 */
1364 /*
1365  * POINTER (RW)
1366  *
1367  * pointer
1368  */
1369 #define SEI_CTRL_LATCH_TRAN_POINTER_MASK (0xFF000000UL)
1370 #define SEI_CTRL_LATCH_TRAN_POINTER_SHIFT (24U)
1371 #define SEI_CTRL_LATCH_TRAN_POINTER_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_POINTER_SHIFT) & SEI_CTRL_LATCH_TRAN_POINTER_MASK)
1372 #define SEI_CTRL_LATCH_TRAN_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_POINTER_MASK) >> SEI_CTRL_LATCH_TRAN_POINTER_SHIFT)
1373 
1374 /*
1375  * CFG_TM (RW)
1376  *
1377  * timeout
1378  * 0: high
1379  * 1: low
1380  * 2: rise
1381  * 3: fall
1382  */
1383 #define SEI_CTRL_LATCH_TRAN_CFG_TM_MASK (0x30000UL)
1384 #define SEI_CTRL_LATCH_TRAN_CFG_TM_SHIFT (16U)
1385 #define SEI_CTRL_LATCH_TRAN_CFG_TM_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_TM_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_TM_MASK)
1386 #define SEI_CTRL_LATCH_TRAN_CFG_TM_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_TM_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_TM_SHIFT)
1387 
1388 /*
1389  * CFG_RXD (RW)
1390  *
1391  * data received
1392  * 0: high
1393  * 1: low
1394  * 2: rise
1395  * 3: fall
1396  */
1397 #define SEI_CTRL_LATCH_TRAN_CFG_RXD_MASK (0xC000U)
1398 #define SEI_CTRL_LATCH_TRAN_CFG_RXD_SHIFT (14U)
1399 #define SEI_CTRL_LATCH_TRAN_CFG_RXD_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_RXD_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_RXD_MASK)
1400 #define SEI_CTRL_LATCH_TRAN_CFG_RXD_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_RXD_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_RXD_SHIFT)
1401 
1402 /*
1403  * CFG_TXD (RW)
1404  *
1405  * data send
1406  * 0: high
1407  * 1: low
1408  * 2: rise
1409  * 3: fall
1410  */
1411 #define SEI_CTRL_LATCH_TRAN_CFG_TXD_MASK (0x3000U)
1412 #define SEI_CTRL_LATCH_TRAN_CFG_TXD_SHIFT (12U)
1413 #define SEI_CTRL_LATCH_TRAN_CFG_TXD_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_TXD_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_TXD_MASK)
1414 #define SEI_CTRL_LATCH_TRAN_CFG_TXD_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_TXD_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_TXD_SHIFT)
1415 
1416 /*
1417  * CFG_CLK (RW)
1418  *
1419  * clock
1420  * 0: high
1421  * 1: low
1422  * 2: rise
1423  * 3: fall
1424  */
1425 #define SEI_CTRL_LATCH_TRAN_CFG_CLK_MASK (0xC00U)
1426 #define SEI_CTRL_LATCH_TRAN_CFG_CLK_SHIFT (10U)
1427 #define SEI_CTRL_LATCH_TRAN_CFG_CLK_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_CLK_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_CLK_MASK)
1428 #define SEI_CTRL_LATCH_TRAN_CFG_CLK_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_CLK_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_CLK_SHIFT)
1429 
1430 /*
1431  * CFG_PTR (RW)
1432  *
1433  * pointer
1434  * 0: match
1435  * 1: not match
1436  * 2:entry
1437  * 3:leave
1438  */
1439 #define SEI_CTRL_LATCH_TRAN_CFG_PTR_MASK (0x300U)
1440 #define SEI_CTRL_LATCH_TRAN_CFG_PTR_SHIFT (8U)
1441 #define SEI_CTRL_LATCH_TRAN_CFG_PTR_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_PTR_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_PTR_MASK)
1442 #define SEI_CTRL_LATCH_TRAN_CFG_PTR_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_PTR_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_PTR_SHIFT)
1443 
1444 /*
1445  * OV_TM (RW)
1446  *
1447  * override timeout check
1448  */
1449 #define SEI_CTRL_LATCH_TRAN_OV_TM_MASK (0x10U)
1450 #define SEI_CTRL_LATCH_TRAN_OV_TM_SHIFT (4U)
1451 #define SEI_CTRL_LATCH_TRAN_OV_TM_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_TM_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_TM_MASK)
1452 #define SEI_CTRL_LATCH_TRAN_OV_TM_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_TM_MASK) >> SEI_CTRL_LATCH_TRAN_OV_TM_SHIFT)
1453 
1454 /*
1455  * OV_RXD (RW)
1456  *
1457  * override RX data check
1458  */
1459 #define SEI_CTRL_LATCH_TRAN_OV_RXD_MASK (0x8U)
1460 #define SEI_CTRL_LATCH_TRAN_OV_RXD_SHIFT (3U)
1461 #define SEI_CTRL_LATCH_TRAN_OV_RXD_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_RXD_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_RXD_MASK)
1462 #define SEI_CTRL_LATCH_TRAN_OV_RXD_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_RXD_MASK) >> SEI_CTRL_LATCH_TRAN_OV_RXD_SHIFT)
1463 
1464 /*
1465  * OV_TXD (RW)
1466  *
1467  * override TX data check
1468  */
1469 #define SEI_CTRL_LATCH_TRAN_OV_TXD_MASK (0x4U)
1470 #define SEI_CTRL_LATCH_TRAN_OV_TXD_SHIFT (2U)
1471 #define SEI_CTRL_LATCH_TRAN_OV_TXD_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_TXD_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_TXD_MASK)
1472 #define SEI_CTRL_LATCH_TRAN_OV_TXD_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_TXD_MASK) >> SEI_CTRL_LATCH_TRAN_OV_TXD_SHIFT)
1473 
1474 /*
1475  * OV_CLK (RW)
1476  *
1477  * override clock check
1478  */
1479 #define SEI_CTRL_LATCH_TRAN_OV_CLK_MASK (0x2U)
1480 #define SEI_CTRL_LATCH_TRAN_OV_CLK_SHIFT (1U)
1481 #define SEI_CTRL_LATCH_TRAN_OV_CLK_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_CLK_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_CLK_MASK)
1482 #define SEI_CTRL_LATCH_TRAN_OV_CLK_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_CLK_MASK) >> SEI_CTRL_LATCH_TRAN_OV_CLK_SHIFT)
1483 
1484 /*
1485  * OV_PTR (RW)
1486  *
1487  * override pointer check
1488  */
1489 #define SEI_CTRL_LATCH_TRAN_OV_PTR_MASK (0x1U)
1490 #define SEI_CTRL_LATCH_TRAN_OV_PTR_SHIFT (0U)
1491 #define SEI_CTRL_LATCH_TRAN_OV_PTR_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_PTR_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_PTR_MASK)
1492 #define SEI_CTRL_LATCH_TRAN_OV_PTR_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_PTR_MASK) >> SEI_CTRL_LATCH_TRAN_OV_PTR_SHIFT)
1493 
1494 /* Bitfield definition for register of struct array CTRL: CFG */
1495 /*
1496  * EN (RW)
1497  *
1498  * Enable latch
1499  * 0: disable
1500  * 1: enable
1501  */
1502 #define SEI_CTRL_LATCH_CFG_EN_MASK (0x80000000UL)
1503 #define SEI_CTRL_LATCH_CFG_EN_SHIFT (31U)
1504 #define SEI_CTRL_LATCH_CFG_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_CFG_EN_SHIFT) & SEI_CTRL_LATCH_CFG_EN_MASK)
1505 #define SEI_CTRL_LATCH_CFG_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_CFG_EN_MASK) >> SEI_CTRL_LATCH_CFG_EN_SHIFT)
1506 
1507 /*
1508  * SELECT (RW)
1509  *
1510  * Output select
1511  * 0: state0-state1
1512  * 1: state1-state2
1513  * 2: state2-state3
1514  * 3: state3-state0
1515  */
1516 #define SEI_CTRL_LATCH_CFG_SELECT_MASK (0x7000000UL)
1517 #define SEI_CTRL_LATCH_CFG_SELECT_SHIFT (24U)
1518 #define SEI_CTRL_LATCH_CFG_SELECT_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_CFG_SELECT_SHIFT) & SEI_CTRL_LATCH_CFG_SELECT_MASK)
1519 #define SEI_CTRL_LATCH_CFG_SELECT_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_CFG_SELECT_MASK) >> SEI_CTRL_LATCH_CFG_SELECT_SHIFT)
1520 
1521 /*
1522  * DELAY (RW)
1523  *
1524  * Delay in system clock cycle, for state transition
1525  */
1526 #define SEI_CTRL_LATCH_CFG_DELAY_MASK (0xFFFFU)
1527 #define SEI_CTRL_LATCH_CFG_DELAY_SHIFT (0U)
1528 #define SEI_CTRL_LATCH_CFG_DELAY_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_CFG_DELAY_SHIFT) & SEI_CTRL_LATCH_CFG_DELAY_MASK)
1529 #define SEI_CTRL_LATCH_CFG_DELAY_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_CFG_DELAY_MASK) >> SEI_CTRL_LATCH_CFG_DELAY_SHIFT)
1530 
1531 /* Bitfield definition for register of struct array CTRL: TIME */
1532 /*
1533  * LAT_TIME (RO)
1534  *
1535  * Latch time
1536  */
1537 #define SEI_CTRL_LATCH_TIME_LAT_TIME_MASK (0xFFFFFFFFUL)
1538 #define SEI_CTRL_LATCH_TIME_LAT_TIME_SHIFT (0U)
1539 #define SEI_CTRL_LATCH_TIME_LAT_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TIME_LAT_TIME_MASK) >> SEI_CTRL_LATCH_TIME_LAT_TIME_SHIFT)
1540 
1541 /* Bitfield definition for register of struct array CTRL: STS */
1542 /*
1543  * STATE (RO)
1544  *
1545  * State
1546  */
1547 #define SEI_CTRL_LATCH_STS_STATE_MASK (0x7000000UL)
1548 #define SEI_CTRL_LATCH_STS_STATE_SHIFT (24U)
1549 #define SEI_CTRL_LATCH_STS_STATE_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_STS_STATE_MASK) >> SEI_CTRL_LATCH_STS_STATE_SHIFT)
1550 
1551 /*
1552  * LAT_CNT (RO)
1553  *
1554  * Latch counter
1555  */
1556 #define SEI_CTRL_LATCH_STS_LAT_CNT_MASK (0xFFFFU)
1557 #define SEI_CTRL_LATCH_STS_LAT_CNT_SHIFT (0U)
1558 #define SEI_CTRL_LATCH_STS_LAT_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_STS_LAT_CNT_MASK) >> SEI_CTRL_LATCH_STS_LAT_CNT_SHIFT)
1559 
1560 /* Bitfield definition for register of struct array CTRL: SMP_EN */
1561 /*
1562  * ACC_EN (RW)
1563  *
1564  * Position include acceleration
1565  * 0: use acceleration from sample override acceleration register
1566  * 1: use acceleration from motor group
1567  */
1568 #define SEI_CTRL_POS_SMP_EN_ACC_EN_MASK (0x80000000UL)
1569 #define SEI_CTRL_POS_SMP_EN_ACC_EN_SHIFT (31U)
1570 #define SEI_CTRL_POS_SMP_EN_ACC_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_ACC_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_ACC_EN_MASK)
1571 #define SEI_CTRL_POS_SMP_EN_ACC_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_ACC_EN_MASK) >> SEI_CTRL_POS_SMP_EN_ACC_EN_SHIFT)
1572 
1573 /*
1574  * ACC_SEL (RW)
1575  *
1576  * Data register for acceleration transfer
1577  */
1578 #define SEI_CTRL_POS_SMP_EN_ACC_SEL_MASK (0x1F000000UL)
1579 #define SEI_CTRL_POS_SMP_EN_ACC_SEL_SHIFT (24U)
1580 #define SEI_CTRL_POS_SMP_EN_ACC_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_ACC_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_ACC_SEL_MASK)
1581 #define SEI_CTRL_POS_SMP_EN_ACC_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_ACC_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_ACC_SEL_SHIFT)
1582 
1583 /*
1584  * SPD_EN (RW)
1585  *
1586  * Position include speed
1587  * 0: use speed from sample override speed register
1588  * 1: use speed from motor group
1589  */
1590 #define SEI_CTRL_POS_SMP_EN_SPD_EN_MASK (0x800000UL)
1591 #define SEI_CTRL_POS_SMP_EN_SPD_EN_SHIFT (23U)
1592 #define SEI_CTRL_POS_SMP_EN_SPD_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_SPD_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_SPD_EN_MASK)
1593 #define SEI_CTRL_POS_SMP_EN_SPD_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_SPD_EN_MASK) >> SEI_CTRL_POS_SMP_EN_SPD_EN_SHIFT)
1594 
1595 /*
1596  * SPD_SEL (RW)
1597  *
1598  * Data register for speed transfer
1599  */
1600 #define SEI_CTRL_POS_SMP_EN_SPD_SEL_MASK (0x1F0000UL)
1601 #define SEI_CTRL_POS_SMP_EN_SPD_SEL_SHIFT (16U)
1602 #define SEI_CTRL_POS_SMP_EN_SPD_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_SPD_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_SPD_SEL_MASK)
1603 #define SEI_CTRL_POS_SMP_EN_SPD_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_SPD_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_SPD_SEL_SHIFT)
1604 
1605 /*
1606  * REV_EN (RW)
1607  *
1608  * Position include revolution
1609  * 0: use revolution from sample override revolution register
1610  * 1: use revolution from motor group
1611  */
1612 #define SEI_CTRL_POS_SMP_EN_REV_EN_MASK (0x8000U)
1613 #define SEI_CTRL_POS_SMP_EN_REV_EN_SHIFT (15U)
1614 #define SEI_CTRL_POS_SMP_EN_REV_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_REV_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_REV_EN_MASK)
1615 #define SEI_CTRL_POS_SMP_EN_REV_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_REV_EN_MASK) >> SEI_CTRL_POS_SMP_EN_REV_EN_SHIFT)
1616 
1617 /*
1618  * REV_SEL (RW)
1619  *
1620  * Data register for revolution transfer
1621  */
1622 #define SEI_CTRL_POS_SMP_EN_REV_SEL_MASK (0x1F00U)
1623 #define SEI_CTRL_POS_SMP_EN_REV_SEL_SHIFT (8U)
1624 #define SEI_CTRL_POS_SMP_EN_REV_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_REV_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_REV_SEL_MASK)
1625 #define SEI_CTRL_POS_SMP_EN_REV_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_REV_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_REV_SEL_SHIFT)
1626 
1627 /*
1628  * POS_EN (RW)
1629  *
1630  * Position include position
1631  * 0: use position from sample override position register
1632  * 1: use position from motor group
1633  */
1634 #define SEI_CTRL_POS_SMP_EN_POS_EN_MASK (0x80U)
1635 #define SEI_CTRL_POS_SMP_EN_POS_EN_SHIFT (7U)
1636 #define SEI_CTRL_POS_SMP_EN_POS_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_POS_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_POS_EN_MASK)
1637 #define SEI_CTRL_POS_SMP_EN_POS_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_POS_EN_MASK) >> SEI_CTRL_POS_SMP_EN_POS_EN_SHIFT)
1638 
1639 /*
1640  * POS_SEL (RW)
1641  *
1642  * Data register for position transfer
1643  */
1644 #define SEI_CTRL_POS_SMP_EN_POS_SEL_MASK (0x1FU)
1645 #define SEI_CTRL_POS_SMP_EN_POS_SEL_SHIFT (0U)
1646 #define SEI_CTRL_POS_SMP_EN_POS_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_POS_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_POS_SEL_MASK)
1647 #define SEI_CTRL_POS_SMP_EN_POS_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_POS_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_POS_SEL_SHIFT)
1648 
1649 /* Bitfield definition for register of struct array CTRL: SMP_CFG */
1650 /*
1651  * ONCE (RW)
1652  *
1653  * Sample one time
1654  * 0: Sample during windows time
1655  * 1: Close sample window after first sample
1656  */
1657 #define SEI_CTRL_POS_SMP_CFG_ONCE_MASK (0x1000000UL)
1658 #define SEI_CTRL_POS_SMP_CFG_ONCE_SHIFT (24U)
1659 #define SEI_CTRL_POS_SMP_CFG_ONCE_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_CFG_ONCE_SHIFT) & SEI_CTRL_POS_SMP_CFG_ONCE_MASK)
1660 #define SEI_CTRL_POS_SMP_CFG_ONCE_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_CFG_ONCE_MASK) >> SEI_CTRL_POS_SMP_CFG_ONCE_SHIFT)
1661 
1662 /*
1663  * LAT_SEL (RW)
1664  *
1665  * Latch selection
1666  * 0: latch 0
1667  * 1: latch 1
1668  * 2: latch 2
1669  * 3: latch 3
1670  */
1671 #define SEI_CTRL_POS_SMP_CFG_LAT_SEL_MASK (0x30000UL)
1672 #define SEI_CTRL_POS_SMP_CFG_LAT_SEL_SHIFT (16U)
1673 #define SEI_CTRL_POS_SMP_CFG_LAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_CFG_LAT_SEL_SHIFT) & SEI_CTRL_POS_SMP_CFG_LAT_SEL_MASK)
1674 #define SEI_CTRL_POS_SMP_CFG_LAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_CFG_LAT_SEL_MASK) >> SEI_CTRL_POS_SMP_CFG_LAT_SEL_SHIFT)
1675 
1676 /*
1677  * WINDOW (RW)
1678  *
1679  * Sample window, in clock cycle
1680  */
1681 #define SEI_CTRL_POS_SMP_CFG_WINDOW_MASK (0xFFFFU)
1682 #define SEI_CTRL_POS_SMP_CFG_WINDOW_SHIFT (0U)
1683 #define SEI_CTRL_POS_SMP_CFG_WINDOW_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_CFG_WINDOW_SHIFT) & SEI_CTRL_POS_SMP_CFG_WINDOW_MASK)
1684 #define SEI_CTRL_POS_SMP_CFG_WINDOW_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_CFG_WINDOW_MASK) >> SEI_CTRL_POS_SMP_CFG_WINDOW_SHIFT)
1685 
1686 /* Bitfield definition for register of struct array CTRL: SMP_DAT */
1687 /*
1688  * DAT_SEL (RW)
1689  *
1690  * Data register sampled, each bit represent a data register, select the DATA registers need to be updated when SAMPLE happens.
1691  * Note: CRC register will be cleared automatically by SAMPLE if select the DATA register used for CRC.
1692  */
1693 #define SEI_CTRL_POS_SMP_DAT_DAT_SEL_MASK (0xFFFFFFFFUL)
1694 #define SEI_CTRL_POS_SMP_DAT_DAT_SEL_SHIFT (0U)
1695 #define SEI_CTRL_POS_SMP_DAT_DAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_DAT_DAT_SEL_SHIFT) & SEI_CTRL_POS_SMP_DAT_DAT_SEL_MASK)
1696 #define SEI_CTRL_POS_SMP_DAT_DAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_DAT_DAT_SEL_MASK) >> SEI_CTRL_POS_SMP_DAT_DAT_SEL_SHIFT)
1697 
1698 /* Bitfield definition for register of struct array CTRL: SMP_POS */
1699 /*
1700  * POS (RW)
1701  *
1702  * Sample override position
1703  */
1704 #define SEI_CTRL_POS_SMP_POS_POS_MASK (0xFFFFFFFFUL)
1705 #define SEI_CTRL_POS_SMP_POS_POS_SHIFT (0U)
1706 #define SEI_CTRL_POS_SMP_POS_POS_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_POS_POS_SHIFT) & SEI_CTRL_POS_SMP_POS_POS_MASK)
1707 #define SEI_CTRL_POS_SMP_POS_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_POS_POS_MASK) >> SEI_CTRL_POS_SMP_POS_POS_SHIFT)
1708 
1709 /* Bitfield definition for register of struct array CTRL: SMP_REV */
1710 /*
1711  * REV (RW)
1712  *
1713  * Sample override revolution
1714  */
1715 #define SEI_CTRL_POS_SMP_REV_REV_MASK (0xFFFFFFFFUL)
1716 #define SEI_CTRL_POS_SMP_REV_REV_SHIFT (0U)
1717 #define SEI_CTRL_POS_SMP_REV_REV_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_REV_REV_SHIFT) & SEI_CTRL_POS_SMP_REV_REV_MASK)
1718 #define SEI_CTRL_POS_SMP_REV_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_REV_REV_MASK) >> SEI_CTRL_POS_SMP_REV_REV_SHIFT)
1719 
1720 /* Bitfield definition for register of struct array CTRL: SMP_SPD */
1721 /*
1722  * SPD (RW)
1723  *
1724  * Sample override speed
1725  */
1726 #define SEI_CTRL_POS_SMP_SPD_SPD_MASK (0xFFFFFFFFUL)
1727 #define SEI_CTRL_POS_SMP_SPD_SPD_SHIFT (0U)
1728 #define SEI_CTRL_POS_SMP_SPD_SPD_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_SPD_SPD_SHIFT) & SEI_CTRL_POS_SMP_SPD_SPD_MASK)
1729 #define SEI_CTRL_POS_SMP_SPD_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_SPD_SPD_MASK) >> SEI_CTRL_POS_SMP_SPD_SPD_SHIFT)
1730 
1731 /* Bitfield definition for register of struct array CTRL: SMP_ACC */
1732 /*
1733  * ACC (RW)
1734  *
1735  * Sample override accelerate
1736  */
1737 #define SEI_CTRL_POS_SMP_ACC_ACC_MASK (0xFFFFFFFFUL)
1738 #define SEI_CTRL_POS_SMP_ACC_ACC_SHIFT (0U)
1739 #define SEI_CTRL_POS_SMP_ACC_ACC_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_ACC_ACC_SHIFT) & SEI_CTRL_POS_SMP_ACC_ACC_MASK)
1740 #define SEI_CTRL_POS_SMP_ACC_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_ACC_ACC_MASK) >> SEI_CTRL_POS_SMP_ACC_ACC_SHIFT)
1741 
1742 /* Bitfield definition for register of struct array CTRL: UPD_EN */
1743 /*
1744  * ACC_EN (RW)
1745  *
1746  * Position include acceleration
1747  * 0: use acceleration from update override acceleration register
1748  * 1: use acceleration from data register
1749  */
1750 #define SEI_CTRL_POS_UPD_EN_ACC_EN_MASK (0x80000000UL)
1751 #define SEI_CTRL_POS_UPD_EN_ACC_EN_SHIFT (31U)
1752 #define SEI_CTRL_POS_UPD_EN_ACC_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_ACC_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_ACC_EN_MASK)
1753 #define SEI_CTRL_POS_UPD_EN_ACC_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_ACC_EN_MASK) >> SEI_CTRL_POS_UPD_EN_ACC_EN_SHIFT)
1754 
1755 /*
1756  * ACC_SEL (RW)
1757  *
1758  * Data register for acceleration transfer
1759  */
1760 #define SEI_CTRL_POS_UPD_EN_ACC_SEL_MASK (0x1F000000UL)
1761 #define SEI_CTRL_POS_UPD_EN_ACC_SEL_SHIFT (24U)
1762 #define SEI_CTRL_POS_UPD_EN_ACC_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_ACC_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_ACC_SEL_MASK)
1763 #define SEI_CTRL_POS_UPD_EN_ACC_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_ACC_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_ACC_SEL_SHIFT)
1764 
1765 /*
1766  * SPD_EN (RW)
1767  *
1768  * Position include speed
1769  * 0: use speed from update override speed register
1770  * 1: use speed from data register
1771  */
1772 #define SEI_CTRL_POS_UPD_EN_SPD_EN_MASK (0x800000UL)
1773 #define SEI_CTRL_POS_UPD_EN_SPD_EN_SHIFT (23U)
1774 #define SEI_CTRL_POS_UPD_EN_SPD_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_SPD_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_SPD_EN_MASK)
1775 #define SEI_CTRL_POS_UPD_EN_SPD_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_SPD_EN_MASK) >> SEI_CTRL_POS_UPD_EN_SPD_EN_SHIFT)
1776 
1777 /*
1778  * SPD_SEL (RW)
1779  *
1780  * Data register for speed transfer
1781  */
1782 #define SEI_CTRL_POS_UPD_EN_SPD_SEL_MASK (0x1F0000UL)
1783 #define SEI_CTRL_POS_UPD_EN_SPD_SEL_SHIFT (16U)
1784 #define SEI_CTRL_POS_UPD_EN_SPD_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_SPD_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_SPD_SEL_MASK)
1785 #define SEI_CTRL_POS_UPD_EN_SPD_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_SPD_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_SPD_SEL_SHIFT)
1786 
1787 /*
1788  * REV_EN (RW)
1789  *
1790  * Position include revolution
1791  * 0: use revolution from update override revolution register
1792  * 1: use revolution from data register
1793  */
1794 #define SEI_CTRL_POS_UPD_EN_REV_EN_MASK (0x8000U)
1795 #define SEI_CTRL_POS_UPD_EN_REV_EN_SHIFT (15U)
1796 #define SEI_CTRL_POS_UPD_EN_REV_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_REV_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_REV_EN_MASK)
1797 #define SEI_CTRL_POS_UPD_EN_REV_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_REV_EN_MASK) >> SEI_CTRL_POS_UPD_EN_REV_EN_SHIFT)
1798 
1799 /*
1800  * REV_SEL (RW)
1801  *
1802  * Data register for revolution transfer
1803  */
1804 #define SEI_CTRL_POS_UPD_EN_REV_SEL_MASK (0x1F00U)
1805 #define SEI_CTRL_POS_UPD_EN_REV_SEL_SHIFT (8U)
1806 #define SEI_CTRL_POS_UPD_EN_REV_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_REV_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_REV_SEL_MASK)
1807 #define SEI_CTRL_POS_UPD_EN_REV_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_REV_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_REV_SEL_SHIFT)
1808 
1809 /*
1810  * POS_EN (RW)
1811  *
1812  * Position include position
1813  * 0: use position from update override position register
1814  * 1: use position from data register
1815  */
1816 #define SEI_CTRL_POS_UPD_EN_POS_EN_MASK (0x80U)
1817 #define SEI_CTRL_POS_UPD_EN_POS_EN_SHIFT (7U)
1818 #define SEI_CTRL_POS_UPD_EN_POS_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_POS_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_POS_EN_MASK)
1819 #define SEI_CTRL_POS_UPD_EN_POS_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_POS_EN_MASK) >> SEI_CTRL_POS_UPD_EN_POS_EN_SHIFT)
1820 
1821 /*
1822  * POS_SEL (RW)
1823  *
1824  * Data register for position transfer
1825  */
1826 #define SEI_CTRL_POS_UPD_EN_POS_SEL_MASK (0x1FU)
1827 #define SEI_CTRL_POS_UPD_EN_POS_SEL_SHIFT (0U)
1828 #define SEI_CTRL_POS_UPD_EN_POS_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_POS_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_POS_SEL_MASK)
1829 #define SEI_CTRL_POS_UPD_EN_POS_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_POS_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_POS_SEL_SHIFT)
1830 
1831 /* Bitfield definition for register of struct array CTRL: UPD_CFG */
1832 /*
1833  * TIME_OVRD (RW)
1834  *
1835  * Use override time
1836  * 0: use time sample from motor group
1837  * 1: use override time
1838  */
1839 #define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_MASK (0x80000000UL)
1840 #define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SHIFT (31U)
1841 #define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SHIFT) & SEI_CTRL_POS_UPD_CFG_TIME_OVRD_MASK)
1842 #define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_CFG_TIME_OVRD_MASK) >> SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SHIFT)
1843 
1844 /*
1845  * ONERR (RW)
1846  *
1847  * Sample one time
1848  * 0: Sample during windows time
1849  * 1: Close sample window after first sample
1850  */
1851 #define SEI_CTRL_POS_UPD_CFG_ONERR_MASK (0x1000000UL)
1852 #define SEI_CTRL_POS_UPD_CFG_ONERR_SHIFT (24U)
1853 #define SEI_CTRL_POS_UPD_CFG_ONERR_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_CFG_ONERR_SHIFT) & SEI_CTRL_POS_UPD_CFG_ONERR_MASK)
1854 #define SEI_CTRL_POS_UPD_CFG_ONERR_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_CFG_ONERR_MASK) >> SEI_CTRL_POS_UPD_CFG_ONERR_SHIFT)
1855 
1856 /*
1857  * LAT_SEL (RW)
1858  *
1859  * Latch selection
1860  * 0: latch 0
1861  * 1: latch 1
1862  * 2: latch 2
1863  * 3: latch 3
1864  */
1865 #define SEI_CTRL_POS_UPD_CFG_LAT_SEL_MASK (0x30000UL)
1866 #define SEI_CTRL_POS_UPD_CFG_LAT_SEL_SHIFT (16U)
1867 #define SEI_CTRL_POS_UPD_CFG_LAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_CFG_LAT_SEL_SHIFT) & SEI_CTRL_POS_UPD_CFG_LAT_SEL_MASK)
1868 #define SEI_CTRL_POS_UPD_CFG_LAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_CFG_LAT_SEL_MASK) >> SEI_CTRL_POS_UPD_CFG_LAT_SEL_SHIFT)
1869 
1870 /* Bitfield definition for register of struct array CTRL: UPD_DAT */
1871 /*
1872  * DAT_SEL (RW)
1873  *
1874  * Data register sampled, each bit represent a data register, select the DATA registers need to be updated when UPDATE happen.
1875  * Note: CRC register will be cleared automatically by UPDATE if select the DATA register used for CRC.
1876  */
1877 #define SEI_CTRL_POS_UPD_DAT_DAT_SEL_MASK (0xFFFFFFFFUL)
1878 #define SEI_CTRL_POS_UPD_DAT_DAT_SEL_SHIFT (0U)
1879 #define SEI_CTRL_POS_UPD_DAT_DAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_DAT_DAT_SEL_SHIFT) & SEI_CTRL_POS_UPD_DAT_DAT_SEL_MASK)
1880 #define SEI_CTRL_POS_UPD_DAT_DAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_DAT_DAT_SEL_MASK) >> SEI_CTRL_POS_UPD_DAT_DAT_SEL_SHIFT)
1881 
1882 /* Bitfield definition for register of struct array CTRL: UPD_TIME */
1883 /*
1884  * TIME (RW)
1885  *
1886  * Update override time
1887  */
1888 #define SEI_CTRL_POS_UPD_TIME_TIME_MASK (0xFFFFFFFFUL)
1889 #define SEI_CTRL_POS_UPD_TIME_TIME_SHIFT (0U)
1890 #define SEI_CTRL_POS_UPD_TIME_TIME_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_TIME_TIME_SHIFT) & SEI_CTRL_POS_UPD_TIME_TIME_MASK)
1891 #define SEI_CTRL_POS_UPD_TIME_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_TIME_TIME_MASK) >> SEI_CTRL_POS_UPD_TIME_TIME_SHIFT)
1892 
1893 /* Bitfield definition for register of struct array CTRL: UPD_POS */
1894 /*
1895  * POS (RW)
1896  *
1897  * Update override position
1898  */
1899 #define SEI_CTRL_POS_UPD_POS_POS_MASK (0xFFFFFFFFUL)
1900 #define SEI_CTRL_POS_UPD_POS_POS_SHIFT (0U)
1901 #define SEI_CTRL_POS_UPD_POS_POS_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_POS_POS_SHIFT) & SEI_CTRL_POS_UPD_POS_POS_MASK)
1902 #define SEI_CTRL_POS_UPD_POS_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_POS_POS_MASK) >> SEI_CTRL_POS_UPD_POS_POS_SHIFT)
1903 
1904 /* Bitfield definition for register of struct array CTRL: UPD_REV */
1905 /*
1906  * REV (RW)
1907  *
1908  * Update override revolution
1909  */
1910 #define SEI_CTRL_POS_UPD_REV_REV_MASK (0xFFFFFFFFUL)
1911 #define SEI_CTRL_POS_UPD_REV_REV_SHIFT (0U)
1912 #define SEI_CTRL_POS_UPD_REV_REV_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_REV_REV_SHIFT) & SEI_CTRL_POS_UPD_REV_REV_MASK)
1913 #define SEI_CTRL_POS_UPD_REV_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_REV_REV_MASK) >> SEI_CTRL_POS_UPD_REV_REV_SHIFT)
1914 
1915 /* Bitfield definition for register of struct array CTRL: UPD_SPD */
1916 /*
1917  * SPD (RW)
1918  *
1919  * Update override speed
1920  */
1921 #define SEI_CTRL_POS_UPD_SPD_SPD_MASK (0xFFFFFFFFUL)
1922 #define SEI_CTRL_POS_UPD_SPD_SPD_SHIFT (0U)
1923 #define SEI_CTRL_POS_UPD_SPD_SPD_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_SPD_SPD_SHIFT) & SEI_CTRL_POS_UPD_SPD_SPD_MASK)
1924 #define SEI_CTRL_POS_UPD_SPD_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_SPD_SPD_MASK) >> SEI_CTRL_POS_UPD_SPD_SPD_SHIFT)
1925 
1926 /* Bitfield definition for register of struct array CTRL: UPD_ACC */
1927 /*
1928  * ACC (RW)
1929  *
1930  * Update override accelerate
1931  */
1932 #define SEI_CTRL_POS_UPD_ACC_ACC_MASK (0xFFFFFFFFUL)
1933 #define SEI_CTRL_POS_UPD_ACC_ACC_SHIFT (0U)
1934 #define SEI_CTRL_POS_UPD_ACC_ACC_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_ACC_ACC_SHIFT) & SEI_CTRL_POS_UPD_ACC_ACC_MASK)
1935 #define SEI_CTRL_POS_UPD_ACC_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_ACC_ACC_MASK) >> SEI_CTRL_POS_UPD_ACC_ACC_SHIFT)
1936 
1937 /* Bitfield definition for register of struct array CTRL: SMP_VAL */
1938 /*
1939  * ACC (RO)
1940  *
1941  * Position include acceleration
1942  */
1943 #define SEI_CTRL_POS_SMP_VAL_ACC_MASK (0x80000000UL)
1944 #define SEI_CTRL_POS_SMP_VAL_ACC_SHIFT (31U)
1945 #define SEI_CTRL_POS_SMP_VAL_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_ACC_MASK) >> SEI_CTRL_POS_SMP_VAL_ACC_SHIFT)
1946 
1947 /*
1948  * SPD (RO)
1949  *
1950  * Position include speed
1951  */
1952 #define SEI_CTRL_POS_SMP_VAL_SPD_MASK (0x800000UL)
1953 #define SEI_CTRL_POS_SMP_VAL_SPD_SHIFT (23U)
1954 #define SEI_CTRL_POS_SMP_VAL_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_SPD_MASK) >> SEI_CTRL_POS_SMP_VAL_SPD_SHIFT)
1955 
1956 /*
1957  * REV (RO)
1958  *
1959  * Position include revolution
1960  */
1961 #define SEI_CTRL_POS_SMP_VAL_REV_MASK (0x8000U)
1962 #define SEI_CTRL_POS_SMP_VAL_REV_SHIFT (15U)
1963 #define SEI_CTRL_POS_SMP_VAL_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_REV_MASK) >> SEI_CTRL_POS_SMP_VAL_REV_SHIFT)
1964 
1965 /*
1966  * POS (RO)
1967  *
1968  * Position include position
1969  */
1970 #define SEI_CTRL_POS_SMP_VAL_POS_MASK (0x80U)
1971 #define SEI_CTRL_POS_SMP_VAL_POS_SHIFT (7U)
1972 #define SEI_CTRL_POS_SMP_VAL_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_POS_MASK) >> SEI_CTRL_POS_SMP_VAL_POS_SHIFT)
1973 
1974 /* Bitfield definition for register of struct array CTRL: SMP_STS */
1975 /*
1976  * OCCUR (RO)
1977  *
1978  * Sample occured
1979  * 0: Sample not happened
1980  * 1: Sample occured
1981  */
1982 #define SEI_CTRL_POS_SMP_STS_OCCUR_MASK (0x1000000UL)
1983 #define SEI_CTRL_POS_SMP_STS_OCCUR_SHIFT (24U)
1984 #define SEI_CTRL_POS_SMP_STS_OCCUR_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_STS_OCCUR_MASK) >> SEI_CTRL_POS_SMP_STS_OCCUR_SHIFT)
1985 
1986 /*
1987  * WIN_CNT (RO)
1988  *
1989  * Sample window counter
1990  */
1991 #define SEI_CTRL_POS_SMP_STS_WIN_CNT_MASK (0xFFFFU)
1992 #define SEI_CTRL_POS_SMP_STS_WIN_CNT_SHIFT (0U)
1993 #define SEI_CTRL_POS_SMP_STS_WIN_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_STS_WIN_CNT_MASK) >> SEI_CTRL_POS_SMP_STS_WIN_CNT_SHIFT)
1994 
1995 /* Bitfield definition for register of struct array CTRL: TIME_IN */
1996 /*
1997  * TIME (RO)
1998  *
1999  * input time
2000  */
2001 #define SEI_CTRL_POS_TIME_IN_TIME_MASK (0xFFFFFFFFUL)
2002 #define SEI_CTRL_POS_TIME_IN_TIME_SHIFT (0U)
2003 #define SEI_CTRL_POS_TIME_IN_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_TIME_IN_TIME_MASK) >> SEI_CTRL_POS_TIME_IN_TIME_SHIFT)
2004 
2005 /* Bitfield definition for register of struct array CTRL: POS_IN */
2006 /*
2007  * POS (RO)
2008  *
2009  * Input position
2010  */
2011 #define SEI_CTRL_POS_POS_IN_POS_MASK (0xFFFFFFFFUL)
2012 #define SEI_CTRL_POS_POS_IN_POS_SHIFT (0U)
2013 #define SEI_CTRL_POS_POS_IN_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_POS_IN_POS_MASK) >> SEI_CTRL_POS_POS_IN_POS_SHIFT)
2014 
2015 /* Bitfield definition for register of struct array CTRL: REV_IN */
2016 /*
2017  * REV (RO)
2018  *
2019  * Input revolution
2020  */
2021 #define SEI_CTRL_POS_REV_IN_REV_MASK (0xFFFFFFFFUL)
2022 #define SEI_CTRL_POS_REV_IN_REV_SHIFT (0U)
2023 #define SEI_CTRL_POS_REV_IN_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_REV_IN_REV_MASK) >> SEI_CTRL_POS_REV_IN_REV_SHIFT)
2024 
2025 /* Bitfield definition for register of struct array CTRL: SPD_IN */
2026 /*
2027  * SPD (RO)
2028  *
2029  * Input speed
2030  */
2031 #define SEI_CTRL_POS_SPD_IN_SPD_MASK (0xFFFFFFFFUL)
2032 #define SEI_CTRL_POS_SPD_IN_SPD_SHIFT (0U)
2033 #define SEI_CTRL_POS_SPD_IN_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SPD_IN_SPD_MASK) >> SEI_CTRL_POS_SPD_IN_SPD_SHIFT)
2034 
2035 /* Bitfield definition for register of struct array CTRL: ACC_IN */
2036 /*
2037  * ACC (RO)
2038  *
2039  * Input accelerate
2040  */
2041 #define SEI_CTRL_POS_ACC_IN_ACC_MASK (0xFFFFFFFFUL)
2042 #define SEI_CTRL_POS_ACC_IN_ACC_SHIFT (0U)
2043 #define SEI_CTRL_POS_ACC_IN_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_ACC_IN_ACC_MASK) >> SEI_CTRL_POS_ACC_IN_ACC_SHIFT)
2044 
2045 /* Bitfield definition for register of struct array CTRL: UPD_STS */
2046 /*
2047  * UPD_ERR (RO)
2048  *
2049  * Update error
2050  * 0: data receive normally
2051  * 1: data receive error
2052  */
2053 #define SEI_CTRL_POS_UPD_STS_UPD_ERR_MASK (0x1000000UL)
2054 #define SEI_CTRL_POS_UPD_STS_UPD_ERR_SHIFT (24U)
2055 #define SEI_CTRL_POS_UPD_STS_UPD_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_STS_UPD_ERR_MASK) >> SEI_CTRL_POS_UPD_STS_UPD_ERR_SHIFT)
2056 
2057 /* Bitfield definition for register of struct array CTRL: INT_EN */
2058 /*
2059  * TRG_ERR3 (RW)
2060  *
2061  * Trigger3 failed
2062  */
2063 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_MASK (0x80000000UL)
2064 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SHIFT (31U)
2065 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR3_MASK)
2066 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR3_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SHIFT)
2067 
2068 /*
2069  * TRG_ERR2 (RW)
2070  *
2071  * Trigger2 failed
2072  */
2073 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_MASK (0x40000000UL)
2074 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SHIFT (30U)
2075 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR2_MASK)
2076 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR2_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SHIFT)
2077 
2078 /*
2079  * TRG_ERR1 (RW)
2080  *
2081  * Trigger1 failed
2082  */
2083 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_MASK (0x20000000UL)
2084 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SHIFT (29U)
2085 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR1_MASK)
2086 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR1_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SHIFT)
2087 
2088 /*
2089  * TRG_ERR0 (RW)
2090  *
2091  * Trigger0 failed
2092  */
2093 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_MASK (0x10000000UL)
2094 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SHIFT (28U)
2095 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR0_MASK)
2096 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR0_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SHIFT)
2097 
2098 /*
2099  * TRIGER3 (RW)
2100  *
2101  * Trigger3
2102  */
2103 #define SEI_CTRL_IRQ_INT_EN_TRIGER3_MASK (0x8000000UL)
2104 #define SEI_CTRL_IRQ_INT_EN_TRIGER3_SHIFT (27U)
2105 #define SEI_CTRL_IRQ_INT_EN_TRIGER3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER3_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER3_MASK)
2106 #define SEI_CTRL_IRQ_INT_EN_TRIGER3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER3_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER3_SHIFT)
2107 
2108 /*
2109  * TRIGER2 (RW)
2110  *
2111  * Trigger2
2112  */
2113 #define SEI_CTRL_IRQ_INT_EN_TRIGER2_MASK (0x4000000UL)
2114 #define SEI_CTRL_IRQ_INT_EN_TRIGER2_SHIFT (26U)
2115 #define SEI_CTRL_IRQ_INT_EN_TRIGER2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER2_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER2_MASK)
2116 #define SEI_CTRL_IRQ_INT_EN_TRIGER2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER2_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER2_SHIFT)
2117 
2118 /*
2119  * TRIGER1 (RW)
2120  *
2121  * Trigger1
2122  */
2123 #define SEI_CTRL_IRQ_INT_EN_TRIGER1_MASK (0x2000000UL)
2124 #define SEI_CTRL_IRQ_INT_EN_TRIGER1_SHIFT (25U)
2125 #define SEI_CTRL_IRQ_INT_EN_TRIGER1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER1_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER1_MASK)
2126 #define SEI_CTRL_IRQ_INT_EN_TRIGER1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER1_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER1_SHIFT)
2127 
2128 /*
2129  * TRIGER0 (RW)
2130  *
2131  * Trigger0
2132  */
2133 #define SEI_CTRL_IRQ_INT_EN_TRIGER0_MASK (0x1000000UL)
2134 #define SEI_CTRL_IRQ_INT_EN_TRIGER0_SHIFT (24U)
2135 #define SEI_CTRL_IRQ_INT_EN_TRIGER0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER0_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER0_MASK)
2136 #define SEI_CTRL_IRQ_INT_EN_TRIGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER0_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER0_SHIFT)
2137 
2138 /*
2139  * SMP_ERR (RW)
2140  *
2141  * Sample error
2142  */
2143 #define SEI_CTRL_IRQ_INT_EN_SMP_ERR_MASK (0x100000UL)
2144 #define SEI_CTRL_IRQ_INT_EN_SMP_ERR_SHIFT (20U)
2145 #define SEI_CTRL_IRQ_INT_EN_SMP_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_SMP_ERR_SHIFT) & SEI_CTRL_IRQ_INT_EN_SMP_ERR_MASK)
2146 #define SEI_CTRL_IRQ_INT_EN_SMP_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_SMP_ERR_MASK) >> SEI_CTRL_IRQ_INT_EN_SMP_ERR_SHIFT)
2147 
2148 /*
2149  * LATCH3 (RW)
2150  *
2151  * Latch3
2152  */
2153 #define SEI_CTRL_IRQ_INT_EN_LATCH3_MASK (0x80000UL)
2154 #define SEI_CTRL_IRQ_INT_EN_LATCH3_SHIFT (19U)
2155 #define SEI_CTRL_IRQ_INT_EN_LATCH3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH3_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH3_MASK)
2156 #define SEI_CTRL_IRQ_INT_EN_LATCH3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH3_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH3_SHIFT)
2157 
2158 /*
2159  * LATCH2 (RW)
2160  *
2161  * Latch2
2162  */
2163 #define SEI_CTRL_IRQ_INT_EN_LATCH2_MASK (0x40000UL)
2164 #define SEI_CTRL_IRQ_INT_EN_LATCH2_SHIFT (18U)
2165 #define SEI_CTRL_IRQ_INT_EN_LATCH2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH2_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH2_MASK)
2166 #define SEI_CTRL_IRQ_INT_EN_LATCH2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH2_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH2_SHIFT)
2167 
2168 /*
2169  * LATCH1 (RW)
2170  *
2171  * Latch1
2172  */
2173 #define SEI_CTRL_IRQ_INT_EN_LATCH1_MASK (0x20000UL)
2174 #define SEI_CTRL_IRQ_INT_EN_LATCH1_SHIFT (17U)
2175 #define SEI_CTRL_IRQ_INT_EN_LATCH1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH1_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH1_MASK)
2176 #define SEI_CTRL_IRQ_INT_EN_LATCH1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH1_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH1_SHIFT)
2177 
2178 /*
2179  * LATCH0 (RW)
2180  *
2181  * Latch0
2182  */
2183 #define SEI_CTRL_IRQ_INT_EN_LATCH0_MASK (0x10000UL)
2184 #define SEI_CTRL_IRQ_INT_EN_LATCH0_SHIFT (16U)
2185 #define SEI_CTRL_IRQ_INT_EN_LATCH0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH0_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH0_MASK)
2186 #define SEI_CTRL_IRQ_INT_EN_LATCH0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH0_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH0_SHIFT)
2187 
2188 /*
2189  * TIMEOUT (RW)
2190  *
2191  * Timeout
2192  */
2193 #define SEI_CTRL_IRQ_INT_EN_TIMEOUT_MASK (0x2000U)
2194 #define SEI_CTRL_IRQ_INT_EN_TIMEOUT_SHIFT (13U)
2195 #define SEI_CTRL_IRQ_INT_EN_TIMEOUT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TIMEOUT_SHIFT) & SEI_CTRL_IRQ_INT_EN_TIMEOUT_MASK)
2196 #define SEI_CTRL_IRQ_INT_EN_TIMEOUT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TIMEOUT_MASK) >> SEI_CTRL_IRQ_INT_EN_TIMEOUT_SHIFT)
2197 
2198 /*
2199  * TRX_ERR (RW)
2200  *
2201  * Transfer error
2202  */
2203 #define SEI_CTRL_IRQ_INT_EN_TRX_ERR_MASK (0x1000U)
2204 #define SEI_CTRL_IRQ_INT_EN_TRX_ERR_SHIFT (12U)
2205 #define SEI_CTRL_IRQ_INT_EN_TRX_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRX_ERR_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRX_ERR_MASK)
2206 #define SEI_CTRL_IRQ_INT_EN_TRX_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRX_ERR_MASK) >> SEI_CTRL_IRQ_INT_EN_TRX_ERR_SHIFT)
2207 
2208 /*
2209  * INSTR1_END (RW)
2210  *
2211  * Instruction 1 end
2212  */
2213 #define SEI_CTRL_IRQ_INT_EN_INSTR1_END_MASK (0x800U)
2214 #define SEI_CTRL_IRQ_INT_EN_INSTR1_END_SHIFT (11U)
2215 #define SEI_CTRL_IRQ_INT_EN_INSTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR1_END_MASK)
2216 #define SEI_CTRL_IRQ_INT_EN_INSTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR1_END_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR1_END_SHIFT)
2217 
2218 /*
2219  * INSTR0_END (RW)
2220  *
2221  * Instruction 0 end
2222  */
2223 #define SEI_CTRL_IRQ_INT_EN_INSTR0_END_MASK (0x400U)
2224 #define SEI_CTRL_IRQ_INT_EN_INSTR0_END_SHIFT (10U)
2225 #define SEI_CTRL_IRQ_INT_EN_INSTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR0_END_MASK)
2226 #define SEI_CTRL_IRQ_INT_EN_INSTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR0_END_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR0_END_SHIFT)
2227 
2228 /*
2229  * PTR1_END (RW)
2230  *
2231  * Pointer 1 end
2232  */
2233 #define SEI_CTRL_IRQ_INT_EN_PTR1_END_MASK (0x200U)
2234 #define SEI_CTRL_IRQ_INT_EN_PTR1_END_SHIFT (9U)
2235 #define SEI_CTRL_IRQ_INT_EN_PTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR1_END_MASK)
2236 #define SEI_CTRL_IRQ_INT_EN_PTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR1_END_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR1_END_SHIFT)
2237 
2238 /*
2239  * PTR0_END (RW)
2240  *
2241  * Pointer 0 end
2242  */
2243 #define SEI_CTRL_IRQ_INT_EN_PTR0_END_MASK (0x100U)
2244 #define SEI_CTRL_IRQ_INT_EN_PTR0_END_SHIFT (8U)
2245 #define SEI_CTRL_IRQ_INT_EN_PTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR0_END_MASK)
2246 #define SEI_CTRL_IRQ_INT_EN_PTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR0_END_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR0_END_SHIFT)
2247 
2248 /*
2249  * INSTR1_ST (RW)
2250  *
2251  * Instruction 1 start
2252  */
2253 #define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_MASK (0x80U)
2254 #define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SHIFT (7U)
2255 #define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR1_ST_MASK)
2256 #define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SHIFT)
2257 
2258 /*
2259  * INSTR0_ST (RW)
2260  *
2261  * Instruction 0 start
2262  */
2263 #define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_MASK (0x40U)
2264 #define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SHIFT (6U)
2265 #define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR0_ST_MASK)
2266 #define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SHIFT)
2267 
2268 /*
2269  * PTR1_ST (RW)
2270  *
2271  * Pointer 1 start
2272  */
2273 #define SEI_CTRL_IRQ_INT_EN_PTR1_ST_MASK (0x20U)
2274 #define SEI_CTRL_IRQ_INT_EN_PTR1_ST_SHIFT (5U)
2275 #define SEI_CTRL_IRQ_INT_EN_PTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR1_ST_MASK)
2276 #define SEI_CTRL_IRQ_INT_EN_PTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR1_ST_SHIFT)
2277 
2278 /*
2279  * PTR0_ST (RW)
2280  *
2281  * Pointer 0 start
2282  */
2283 #define SEI_CTRL_IRQ_INT_EN_PTR0_ST_MASK (0x10U)
2284 #define SEI_CTRL_IRQ_INT_EN_PTR0_ST_SHIFT (4U)
2285 #define SEI_CTRL_IRQ_INT_EN_PTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR0_ST_MASK)
2286 #define SEI_CTRL_IRQ_INT_EN_PTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR0_ST_SHIFT)
2287 
2288 /*
2289  * WDOG (RW)
2290  *
2291  * Watch dog
2292  */
2293 #define SEI_CTRL_IRQ_INT_EN_WDOG_MASK (0x4U)
2294 #define SEI_CTRL_IRQ_INT_EN_WDOG_SHIFT (2U)
2295 #define SEI_CTRL_IRQ_INT_EN_WDOG_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_WDOG_SHIFT) & SEI_CTRL_IRQ_INT_EN_WDOG_MASK)
2296 #define SEI_CTRL_IRQ_INT_EN_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_WDOG_MASK) >> SEI_CTRL_IRQ_INT_EN_WDOG_SHIFT)
2297 
2298 /*
2299  * EXCEPT (RW)
2300  *
2301  * Exception
2302  */
2303 #define SEI_CTRL_IRQ_INT_EN_EXCEPT_MASK (0x2U)
2304 #define SEI_CTRL_IRQ_INT_EN_EXCEPT_SHIFT (1U)
2305 #define SEI_CTRL_IRQ_INT_EN_EXCEPT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_EXCEPT_SHIFT) & SEI_CTRL_IRQ_INT_EN_EXCEPT_MASK)
2306 #define SEI_CTRL_IRQ_INT_EN_EXCEPT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_EXCEPT_MASK) >> SEI_CTRL_IRQ_INT_EN_EXCEPT_SHIFT)
2307 
2308 /*
2309  * STALL (RW)
2310  *
2311  * Stall
2312  */
2313 #define SEI_CTRL_IRQ_INT_EN_STALL_MASK (0x1U)
2314 #define SEI_CTRL_IRQ_INT_EN_STALL_SHIFT (0U)
2315 #define SEI_CTRL_IRQ_INT_EN_STALL_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_STALL_SHIFT) & SEI_CTRL_IRQ_INT_EN_STALL_MASK)
2316 #define SEI_CTRL_IRQ_INT_EN_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_STALL_MASK) >> SEI_CTRL_IRQ_INT_EN_STALL_SHIFT)
2317 
2318 /* Bitfield definition for register of struct array CTRL: INT_FLAG */
2319 /*
2320  * TRG_ERR3 (W1C)
2321  *
2322  * Trigger3 failed
2323  */
2324 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_MASK (0x80000000UL)
2325 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SHIFT (31U)
2326 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_MASK)
2327 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SHIFT)
2328 
2329 /*
2330  * TRG_ERR2 (W1C)
2331  *
2332  * Trigger2 failed
2333  */
2334 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_MASK (0x40000000UL)
2335 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SHIFT (30U)
2336 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_MASK)
2337 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SHIFT)
2338 
2339 /*
2340  * TRG_ERR1 (W1C)
2341  *
2342  * Trigger1 failed
2343  */
2344 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_MASK (0x20000000UL)
2345 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SHIFT (29U)
2346 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_MASK)
2347 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SHIFT)
2348 
2349 /*
2350  * TRG_ERR0 (W1C)
2351  *
2352  * Trigger0 failed
2353  */
2354 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_MASK (0x10000000UL)
2355 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SHIFT (28U)
2356 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_MASK)
2357 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SHIFT)
2358 
2359 /*
2360  * TRIGER3 (W1C)
2361  *
2362  * Trigger3
2363  */
2364 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_MASK (0x8000000UL)
2365 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SHIFT (27U)
2366 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER3_MASK)
2367 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER3_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SHIFT)
2368 
2369 /*
2370  * TRIGER2 (W1C)
2371  *
2372  * Trigger2
2373  */
2374 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_MASK (0x4000000UL)
2375 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SHIFT (26U)
2376 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER2_MASK)
2377 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER2_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SHIFT)
2378 
2379 /*
2380  * TRIGER1 (W1C)
2381  *
2382  * Trigger1
2383  */
2384 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_MASK (0x2000000UL)
2385 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SHIFT (25U)
2386 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER1_MASK)
2387 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER1_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SHIFT)
2388 
2389 /*
2390  * TRIGER0 (W1C)
2391  *
2392  * Trigger0
2393  */
2394 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_MASK (0x1000000UL)
2395 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SHIFT (24U)
2396 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER0_MASK)
2397 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER0_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SHIFT)
2398 
2399 /*
2400  * SMP_ERR (W1C)
2401  *
2402  * Sample error
2403  */
2404 #define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_MASK (0x100000UL)
2405 #define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SHIFT (20U)
2406 #define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_MASK)
2407 #define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_MASK) >> SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SHIFT)
2408 
2409 /*
2410  * LATCH3 (W1C)
2411  *
2412  * Latch3
2413  */
2414 #define SEI_CTRL_IRQ_INT_FLAG_LATCH3_MASK (0x80000UL)
2415 #define SEI_CTRL_IRQ_INT_FLAG_LATCH3_SHIFT (19U)
2416 #define SEI_CTRL_IRQ_INT_FLAG_LATCH3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH3_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH3_MASK)
2417 #define SEI_CTRL_IRQ_INT_FLAG_LATCH3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH3_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH3_SHIFT)
2418 
2419 /*
2420  * LATCH2 (W1C)
2421  *
2422  * Latch2
2423  */
2424 #define SEI_CTRL_IRQ_INT_FLAG_LATCH2_MASK (0x40000UL)
2425 #define SEI_CTRL_IRQ_INT_FLAG_LATCH2_SHIFT (18U)
2426 #define SEI_CTRL_IRQ_INT_FLAG_LATCH2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH2_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH2_MASK)
2427 #define SEI_CTRL_IRQ_INT_FLAG_LATCH2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH2_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH2_SHIFT)
2428 
2429 /*
2430  * LATCH1 (W1C)
2431  *
2432  * Latch1
2433  */
2434 #define SEI_CTRL_IRQ_INT_FLAG_LATCH1_MASK (0x20000UL)
2435 #define SEI_CTRL_IRQ_INT_FLAG_LATCH1_SHIFT (17U)
2436 #define SEI_CTRL_IRQ_INT_FLAG_LATCH1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH1_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH1_MASK)
2437 #define SEI_CTRL_IRQ_INT_FLAG_LATCH1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH1_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH1_SHIFT)
2438 
2439 /*
2440  * LATCH0 (W1C)
2441  *
2442  * Latch0
2443  */
2444 #define SEI_CTRL_IRQ_INT_FLAG_LATCH0_MASK (0x10000UL)
2445 #define SEI_CTRL_IRQ_INT_FLAG_LATCH0_SHIFT (16U)
2446 #define SEI_CTRL_IRQ_INT_FLAG_LATCH0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH0_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH0_MASK)
2447 #define SEI_CTRL_IRQ_INT_FLAG_LATCH0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH0_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH0_SHIFT)
2448 
2449 /*
2450  * TIMEOUT (W1C)
2451  *
2452  * Timeout
2453  */
2454 #define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_MASK (0x2000U)
2455 #define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SHIFT (13U)
2456 #define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_MASK)
2457 #define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SHIFT)
2458 
2459 /*
2460  * TRX_ERR (W1C)
2461  *
2462  * Transfer error
2463  */
2464 #define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_MASK (0x1000U)
2465 #define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SHIFT (12U)
2466 #define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_MASK)
2467 #define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SHIFT)
2468 
2469 /*
2470  * INSTR1_END (W1C)
2471  *
2472  * Instruction 1 end
2473  */
2474 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_MASK (0x800U)
2475 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SHIFT (11U)
2476 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_MASK)
2477 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SHIFT)
2478 
2479 /*
2480  * INSTR0_END (W1C)
2481  *
2482  * Instruction 0 end
2483  */
2484 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_MASK (0x400U)
2485 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SHIFT (10U)
2486 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_MASK)
2487 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SHIFT)
2488 
2489 /*
2490  * PTR1_END (W1C)
2491  *
2492  * Pointer 1 end
2493  */
2494 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_MASK (0x200U)
2495 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SHIFT (9U)
2496 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR1_END_MASK)
2497 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR1_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SHIFT)
2498 
2499 /*
2500  * PTR0_END (W1C)
2501  *
2502  * Pointer 0 end
2503  */
2504 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_MASK (0x100U)
2505 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SHIFT (8U)
2506 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR0_END_MASK)
2507 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR0_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SHIFT)
2508 
2509 /*
2510  * INSTR1_ST (W1C)
2511  *
2512  * Instruction 1 start
2513  */
2514 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_MASK (0x80U)
2515 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SHIFT (7U)
2516 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_MASK)
2517 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SHIFT)
2518 
2519 /*
2520  * INSTR0_ST (W1C)
2521  *
2522  * Instruction 0 start
2523  */
2524 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_MASK (0x40U)
2525 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SHIFT (6U)
2526 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_MASK)
2527 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SHIFT)
2528 
2529 /*
2530  * PTR1_ST (W1C)
2531  *
2532  * Pointer 1 start
2533  */
2534 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_MASK (0x20U)
2535 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SHIFT (5U)
2536 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_MASK)
2537 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SHIFT)
2538 
2539 /*
2540  * PTR0_ST (W1C)
2541  *
2542  * Pointer 0 start
2543  */
2544 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_MASK (0x10U)
2545 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SHIFT (4U)
2546 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_MASK)
2547 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SHIFT)
2548 
2549 /*
2550  * WDOG (W1C)
2551  *
2552  * Watch dog
2553  */
2554 #define SEI_CTRL_IRQ_INT_FLAG_WDOG_MASK (0x4U)
2555 #define SEI_CTRL_IRQ_INT_FLAG_WDOG_SHIFT (2U)
2556 #define SEI_CTRL_IRQ_INT_FLAG_WDOG_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_WDOG_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_WDOG_MASK)
2557 #define SEI_CTRL_IRQ_INT_FLAG_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_WDOG_MASK) >> SEI_CTRL_IRQ_INT_FLAG_WDOG_SHIFT)
2558 
2559 /*
2560  * EXCEPT (W1C)
2561  *
2562  * Exception
2563  */
2564 #define SEI_CTRL_IRQ_INT_FLAG_EXCEPT_MASK (0x2U)
2565 #define SEI_CTRL_IRQ_INT_FLAG_EXCEPT_SHIFT (1U)
2566 #define SEI_CTRL_IRQ_INT_FLAG_EXCEPT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_EXCEPT_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_EXCEPT_MASK)
2567 #define SEI_CTRL_IRQ_INT_FLAG_EXCEPT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_EXCEPT_MASK) >> SEI_CTRL_IRQ_INT_FLAG_EXCEPT_SHIFT)
2568 
2569 /*
2570  * STALL (W1C)
2571  *
2572  * Stall
2573  */
2574 #define SEI_CTRL_IRQ_INT_FLAG_STALL_MASK (0x1U)
2575 #define SEI_CTRL_IRQ_INT_FLAG_STALL_SHIFT (0U)
2576 #define SEI_CTRL_IRQ_INT_FLAG_STALL_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_STALL_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_STALL_MASK)
2577 #define SEI_CTRL_IRQ_INT_FLAG_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_STALL_MASK) >> SEI_CTRL_IRQ_INT_FLAG_STALL_SHIFT)
2578 
2579 /* Bitfield definition for register of struct array CTRL: INT_STS */
2580 /*
2581  * TRG_ERR3 (RO)
2582  *
2583  * Trigger3 failed
2584  */
2585 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR3_MASK (0x80000000UL)
2586 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR3_SHIFT (31U)
2587 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR3_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR3_SHIFT)
2588 
2589 /*
2590  * TRG_ERR2 (RO)
2591  *
2592  * Trigger2 failed
2593  */
2594 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR2_MASK (0x40000000UL)
2595 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR2_SHIFT (30U)
2596 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR2_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR2_SHIFT)
2597 
2598 /*
2599  * TRG_ERR1 (RO)
2600  *
2601  * Trigger1 failed
2602  */
2603 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR1_MASK (0x20000000UL)
2604 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR1_SHIFT (29U)
2605 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR1_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR1_SHIFT)
2606 
2607 /*
2608  * TRG_ERR0 (RO)
2609  *
2610  * Trigger0 failed
2611  */
2612 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR0_MASK (0x10000000UL)
2613 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR0_SHIFT (28U)
2614 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR0_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR0_SHIFT)
2615 
2616 /*
2617  * TRIGER3 (RO)
2618  *
2619  * Trigger3
2620  */
2621 #define SEI_CTRL_IRQ_INT_STS_TRIGER3_MASK (0x8000000UL)
2622 #define SEI_CTRL_IRQ_INT_STS_TRIGER3_SHIFT (27U)
2623 #define SEI_CTRL_IRQ_INT_STS_TRIGER3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER3_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER3_SHIFT)
2624 
2625 /*
2626  * TRIGER2 (RO)
2627  *
2628  * Trigger2
2629  */
2630 #define SEI_CTRL_IRQ_INT_STS_TRIGER2_MASK (0x4000000UL)
2631 #define SEI_CTRL_IRQ_INT_STS_TRIGER2_SHIFT (26U)
2632 #define SEI_CTRL_IRQ_INT_STS_TRIGER2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER2_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER2_SHIFT)
2633 
2634 /*
2635  * TRIGER1 (RO)
2636  *
2637  * Trigger1
2638  */
2639 #define SEI_CTRL_IRQ_INT_STS_TRIGER1_MASK (0x2000000UL)
2640 #define SEI_CTRL_IRQ_INT_STS_TRIGER1_SHIFT (25U)
2641 #define SEI_CTRL_IRQ_INT_STS_TRIGER1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER1_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER1_SHIFT)
2642 
2643 /*
2644  * TRIGER0 (RO)
2645  *
2646  * Trigger0
2647  */
2648 #define SEI_CTRL_IRQ_INT_STS_TRIGER0_MASK (0x1000000UL)
2649 #define SEI_CTRL_IRQ_INT_STS_TRIGER0_SHIFT (24U)
2650 #define SEI_CTRL_IRQ_INT_STS_TRIGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER0_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER0_SHIFT)
2651 
2652 /*
2653  * SMP_ERR (RO)
2654  *
2655  * Sample error
2656  */
2657 #define SEI_CTRL_IRQ_INT_STS_SMP_ERR_MASK (0x100000UL)
2658 #define SEI_CTRL_IRQ_INT_STS_SMP_ERR_SHIFT (20U)
2659 #define SEI_CTRL_IRQ_INT_STS_SMP_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_SMP_ERR_MASK) >> SEI_CTRL_IRQ_INT_STS_SMP_ERR_SHIFT)
2660 
2661 /*
2662  * LATCH3 (RO)
2663  *
2664  * Latch3
2665  */
2666 #define SEI_CTRL_IRQ_INT_STS_LATCH3_MASK (0x80000UL)
2667 #define SEI_CTRL_IRQ_INT_STS_LATCH3_SHIFT (19U)
2668 #define SEI_CTRL_IRQ_INT_STS_LATCH3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH3_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH3_SHIFT)
2669 
2670 /*
2671  * LATCH2 (RO)
2672  *
2673  * Latch2
2674  */
2675 #define SEI_CTRL_IRQ_INT_STS_LATCH2_MASK (0x40000UL)
2676 #define SEI_CTRL_IRQ_INT_STS_LATCH2_SHIFT (18U)
2677 #define SEI_CTRL_IRQ_INT_STS_LATCH2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH2_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH2_SHIFT)
2678 
2679 /*
2680  * LATCH1 (RO)
2681  *
2682  * Latch1
2683  */
2684 #define SEI_CTRL_IRQ_INT_STS_LATCH1_MASK (0x20000UL)
2685 #define SEI_CTRL_IRQ_INT_STS_LATCH1_SHIFT (17U)
2686 #define SEI_CTRL_IRQ_INT_STS_LATCH1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH1_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH1_SHIFT)
2687 
2688 /*
2689  * LATCH0 (RO)
2690  *
2691  * Latch0
2692  */
2693 #define SEI_CTRL_IRQ_INT_STS_LATCH0_MASK (0x10000UL)
2694 #define SEI_CTRL_IRQ_INT_STS_LATCH0_SHIFT (16U)
2695 #define SEI_CTRL_IRQ_INT_STS_LATCH0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH0_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH0_SHIFT)
2696 
2697 /*
2698  * TIMEOUT (RO)
2699  *
2700  * Timeout
2701  */
2702 #define SEI_CTRL_IRQ_INT_STS_TIMEOUT_MASK (0x2000U)
2703 #define SEI_CTRL_IRQ_INT_STS_TIMEOUT_SHIFT (13U)
2704 #define SEI_CTRL_IRQ_INT_STS_TIMEOUT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TIMEOUT_MASK) >> SEI_CTRL_IRQ_INT_STS_TIMEOUT_SHIFT)
2705 
2706 /*
2707  * TRX_ERR (RO)
2708  *
2709  * Transfer error
2710  */
2711 #define SEI_CTRL_IRQ_INT_STS_TRX_ERR_MASK (0x1000U)
2712 #define SEI_CTRL_IRQ_INT_STS_TRX_ERR_SHIFT (12U)
2713 #define SEI_CTRL_IRQ_INT_STS_TRX_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRX_ERR_MASK) >> SEI_CTRL_IRQ_INT_STS_TRX_ERR_SHIFT)
2714 
2715 /*
2716  * INSTR1_END (RO)
2717  *
2718  * Instruction 1 end
2719  */
2720 #define SEI_CTRL_IRQ_INT_STS_INSTR1_END_MASK (0x800U)
2721 #define SEI_CTRL_IRQ_INT_STS_INSTR1_END_SHIFT (11U)
2722 #define SEI_CTRL_IRQ_INT_STS_INSTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR1_END_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR1_END_SHIFT)
2723 
2724 /*
2725  * INSTR0_END (RO)
2726  *
2727  * Instruction 0 end
2728  */
2729 #define SEI_CTRL_IRQ_INT_STS_INSTR0_END_MASK (0x400U)
2730 #define SEI_CTRL_IRQ_INT_STS_INSTR0_END_SHIFT (10U)
2731 #define SEI_CTRL_IRQ_INT_STS_INSTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR0_END_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR0_END_SHIFT)
2732 
2733 /*
2734  * PTR1_END (RO)
2735  *
2736  * Pointer 1 end
2737  */
2738 #define SEI_CTRL_IRQ_INT_STS_PTR1_END_MASK (0x200U)
2739 #define SEI_CTRL_IRQ_INT_STS_PTR1_END_SHIFT (9U)
2740 #define SEI_CTRL_IRQ_INT_STS_PTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR1_END_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR1_END_SHIFT)
2741 
2742 /*
2743  * PTR0_END (RO)
2744  *
2745  * Pointer 0 end
2746  */
2747 #define SEI_CTRL_IRQ_INT_STS_PTR0_END_MASK (0x100U)
2748 #define SEI_CTRL_IRQ_INT_STS_PTR0_END_SHIFT (8U)
2749 #define SEI_CTRL_IRQ_INT_STS_PTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR0_END_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR0_END_SHIFT)
2750 
2751 /*
2752  * INSTR1_ST (RO)
2753  *
2754  * Instruction 1 start
2755  */
2756 #define SEI_CTRL_IRQ_INT_STS_INSTR1_ST_MASK (0x80U)
2757 #define SEI_CTRL_IRQ_INT_STS_INSTR1_ST_SHIFT (7U)
2758 #define SEI_CTRL_IRQ_INT_STS_INSTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR1_ST_SHIFT)
2759 
2760 /*
2761  * INSTR0_ST (RO)
2762  *
2763  * Instruction 0 start
2764  */
2765 #define SEI_CTRL_IRQ_INT_STS_INSTR0_ST_MASK (0x40U)
2766 #define SEI_CTRL_IRQ_INT_STS_INSTR0_ST_SHIFT (6U)
2767 #define SEI_CTRL_IRQ_INT_STS_INSTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR0_ST_SHIFT)
2768 
2769 /*
2770  * PTR1_ST (RO)
2771  *
2772  * Pointer 1 start
2773  */
2774 #define SEI_CTRL_IRQ_INT_STS_PTR1_ST_MASK (0x20U)
2775 #define SEI_CTRL_IRQ_INT_STS_PTR1_ST_SHIFT (5U)
2776 #define SEI_CTRL_IRQ_INT_STS_PTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR1_ST_SHIFT)
2777 
2778 /*
2779  * PTR0_ST (RO)
2780  *
2781  * Pointer 0 start
2782  */
2783 #define SEI_CTRL_IRQ_INT_STS_PTR0_ST_MASK (0x10U)
2784 #define SEI_CTRL_IRQ_INT_STS_PTR0_ST_SHIFT (4U)
2785 #define SEI_CTRL_IRQ_INT_STS_PTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR0_ST_SHIFT)
2786 
2787 /*
2788  * WDOG (RO)
2789  *
2790  * Watch dog
2791  */
2792 #define SEI_CTRL_IRQ_INT_STS_WDOG_MASK (0x4U)
2793 #define SEI_CTRL_IRQ_INT_STS_WDOG_SHIFT (2U)
2794 #define SEI_CTRL_IRQ_INT_STS_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_WDOG_MASK) >> SEI_CTRL_IRQ_INT_STS_WDOG_SHIFT)
2795 
2796 /*
2797  * EXCEPT (RO)
2798  *
2799  * Exception
2800  */
2801 #define SEI_CTRL_IRQ_INT_STS_EXCEPT_MASK (0x2U)
2802 #define SEI_CTRL_IRQ_INT_STS_EXCEPT_SHIFT (1U)
2803 #define SEI_CTRL_IRQ_INT_STS_EXCEPT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_EXCEPT_MASK) >> SEI_CTRL_IRQ_INT_STS_EXCEPT_SHIFT)
2804 
2805 /*
2806  * STALL (RO)
2807  *
2808  * Stall
2809  */
2810 #define SEI_CTRL_IRQ_INT_STS_STALL_MASK (0x1U)
2811 #define SEI_CTRL_IRQ_INT_STS_STALL_SHIFT (0U)
2812 #define SEI_CTRL_IRQ_INT_STS_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_STALL_MASK) >> SEI_CTRL_IRQ_INT_STS_STALL_SHIFT)
2813 
2814 /* Bitfield definition for register of struct array CTRL: POINTER0 */
2815 /*
2816  * POINTER (RW)
2817  *
2818  * Match pointer 0
2819  */
2820 #define SEI_CTRL_IRQ_POINTER0_POINTER_MASK (0xFFU)
2821 #define SEI_CTRL_IRQ_POINTER0_POINTER_SHIFT (0U)
2822 #define SEI_CTRL_IRQ_POINTER0_POINTER_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_POINTER0_POINTER_SHIFT) & SEI_CTRL_IRQ_POINTER0_POINTER_MASK)
2823 #define SEI_CTRL_IRQ_POINTER0_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_POINTER0_POINTER_MASK) >> SEI_CTRL_IRQ_POINTER0_POINTER_SHIFT)
2824 
2825 /* Bitfield definition for register of struct array CTRL: POINTER1 */
2826 /*
2827  * POINTER (RW)
2828  *
2829  * Match pointer 1
2830  */
2831 #define SEI_CTRL_IRQ_POINTER1_POINTER_MASK (0xFFU)
2832 #define SEI_CTRL_IRQ_POINTER1_POINTER_SHIFT (0U)
2833 #define SEI_CTRL_IRQ_POINTER1_POINTER_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_POINTER1_POINTER_SHIFT) & SEI_CTRL_IRQ_POINTER1_POINTER_MASK)
2834 #define SEI_CTRL_IRQ_POINTER1_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_POINTER1_POINTER_MASK) >> SEI_CTRL_IRQ_POINTER1_POINTER_SHIFT)
2835 
2836 /* Bitfield definition for register of struct array CTRL: INSTR0 */
2837 /*
2838  * INSTR (RW)
2839  *
2840  * Match instruction 0
2841  */
2842 #define SEI_CTRL_IRQ_INSTR0_INSTR_MASK (0xFFFFFFFFUL)
2843 #define SEI_CTRL_IRQ_INSTR0_INSTR_SHIFT (0U)
2844 #define SEI_CTRL_IRQ_INSTR0_INSTR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INSTR0_INSTR_SHIFT) & SEI_CTRL_IRQ_INSTR0_INSTR_MASK)
2845 #define SEI_CTRL_IRQ_INSTR0_INSTR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INSTR0_INSTR_MASK) >> SEI_CTRL_IRQ_INSTR0_INSTR_SHIFT)
2846 
2847 /* Bitfield definition for register of struct array CTRL: INSTR1 */
2848 /*
2849  * INSTR (RW)
2850  *
2851  * Match instruction 1
2852  */
2853 #define SEI_CTRL_IRQ_INSTR1_INSTR_MASK (0xFFFFFFFFUL)
2854 #define SEI_CTRL_IRQ_INSTR1_INSTR_SHIFT (0U)
2855 #define SEI_CTRL_IRQ_INSTR1_INSTR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INSTR1_INSTR_SHIFT) & SEI_CTRL_IRQ_INSTR1_INSTR_MASK)
2856 #define SEI_CTRL_IRQ_INSTR1_INSTR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INSTR1_INSTR_MASK) >> SEI_CTRL_IRQ_INSTR1_INSTR_SHIFT)
2857 
2858 /* Bitfield definition for register of struct array CTRL: DMA_EN */
2859 /*
2860  * TRG_ERR3 (RW)
2861  *
2862  * Trigger3 failed
2863  */
2864 #define SEI_CTRL_DMA_EN_TRG_ERR3_MASK (0x80000000UL)
2865 #define SEI_CTRL_DMA_EN_TRG_ERR3_SHIFT (31U)
2866 #define SEI_CTRL_DMA_EN_TRG_ERR3_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRG_ERR3_SHIFT) & SEI_CTRL_DMA_EN_TRG_ERR3_MASK)
2867 #define SEI_CTRL_DMA_EN_TRG_ERR3_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRG_ERR3_MASK) >> SEI_CTRL_DMA_EN_TRG_ERR3_SHIFT)
2868 
2869 /*
2870  * TRG_ERR2 (RW)
2871  *
2872  * Trigger2 failed
2873  */
2874 #define SEI_CTRL_DMA_EN_TRG_ERR2_MASK (0x40000000UL)
2875 #define SEI_CTRL_DMA_EN_TRG_ERR2_SHIFT (30U)
2876 #define SEI_CTRL_DMA_EN_TRG_ERR2_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRG_ERR2_SHIFT) & SEI_CTRL_DMA_EN_TRG_ERR2_MASK)
2877 #define SEI_CTRL_DMA_EN_TRG_ERR2_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRG_ERR2_MASK) >> SEI_CTRL_DMA_EN_TRG_ERR2_SHIFT)
2878 
2879 /*
2880  * TRG_ERR1 (RW)
2881  *
2882  * Trigger1 failed
2883  */
2884 #define SEI_CTRL_DMA_EN_TRG_ERR1_MASK (0x20000000UL)
2885 #define SEI_CTRL_DMA_EN_TRG_ERR1_SHIFT (29U)
2886 #define SEI_CTRL_DMA_EN_TRG_ERR1_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRG_ERR1_SHIFT) & SEI_CTRL_DMA_EN_TRG_ERR1_MASK)
2887 #define SEI_CTRL_DMA_EN_TRG_ERR1_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRG_ERR1_MASK) >> SEI_CTRL_DMA_EN_TRG_ERR1_SHIFT)
2888 
2889 /*
2890  * TRG_ERR0 (RW)
2891  *
2892  * Trigger0 failed
2893  */
2894 #define SEI_CTRL_DMA_EN_TRG_ERR0_MASK (0x10000000UL)
2895 #define SEI_CTRL_DMA_EN_TRG_ERR0_SHIFT (28U)
2896 #define SEI_CTRL_DMA_EN_TRG_ERR0_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRG_ERR0_SHIFT) & SEI_CTRL_DMA_EN_TRG_ERR0_MASK)
2897 #define SEI_CTRL_DMA_EN_TRG_ERR0_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRG_ERR0_MASK) >> SEI_CTRL_DMA_EN_TRG_ERR0_SHIFT)
2898 
2899 /*
2900  * TRIGER3 (RW)
2901  *
2902  * Trigger3
2903  */
2904 #define SEI_CTRL_DMA_EN_TRIGER3_MASK (0x8000000UL)
2905 #define SEI_CTRL_DMA_EN_TRIGER3_SHIFT (27U)
2906 #define SEI_CTRL_DMA_EN_TRIGER3_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRIGER3_SHIFT) & SEI_CTRL_DMA_EN_TRIGER3_MASK)
2907 #define SEI_CTRL_DMA_EN_TRIGER3_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRIGER3_MASK) >> SEI_CTRL_DMA_EN_TRIGER3_SHIFT)
2908 
2909 /*
2910  * TRIGER2 (RW)
2911  *
2912  * Trigger2
2913  */
2914 #define SEI_CTRL_DMA_EN_TRIGER2_MASK (0x4000000UL)
2915 #define SEI_CTRL_DMA_EN_TRIGER2_SHIFT (26U)
2916 #define SEI_CTRL_DMA_EN_TRIGER2_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRIGER2_SHIFT) & SEI_CTRL_DMA_EN_TRIGER2_MASK)
2917 #define SEI_CTRL_DMA_EN_TRIGER2_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRIGER2_MASK) >> SEI_CTRL_DMA_EN_TRIGER2_SHIFT)
2918 
2919 /*
2920  * TRIGER1 (RW)
2921  *
2922  * Trigger1
2923  */
2924 #define SEI_CTRL_DMA_EN_TRIGER1_MASK (0x2000000UL)
2925 #define SEI_CTRL_DMA_EN_TRIGER1_SHIFT (25U)
2926 #define SEI_CTRL_DMA_EN_TRIGER1_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRIGER1_SHIFT) & SEI_CTRL_DMA_EN_TRIGER1_MASK)
2927 #define SEI_CTRL_DMA_EN_TRIGER1_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRIGER1_MASK) >> SEI_CTRL_DMA_EN_TRIGER1_SHIFT)
2928 
2929 /*
2930  * TRIGER0 (RW)
2931  *
2932  * Trigger0
2933  */
2934 #define SEI_CTRL_DMA_EN_TRIGER0_MASK (0x1000000UL)
2935 #define SEI_CTRL_DMA_EN_TRIGER0_SHIFT (24U)
2936 #define SEI_CTRL_DMA_EN_TRIGER0_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRIGER0_SHIFT) & SEI_CTRL_DMA_EN_TRIGER0_MASK)
2937 #define SEI_CTRL_DMA_EN_TRIGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRIGER0_MASK) >> SEI_CTRL_DMA_EN_TRIGER0_SHIFT)
2938 
2939 /*
2940  * SMP_ERR (RW)
2941  *
2942  * Sample error
2943  */
2944 #define SEI_CTRL_DMA_EN_SMP_ERR_MASK (0x100000UL)
2945 #define SEI_CTRL_DMA_EN_SMP_ERR_SHIFT (20U)
2946 #define SEI_CTRL_DMA_EN_SMP_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_SMP_ERR_SHIFT) & SEI_CTRL_DMA_EN_SMP_ERR_MASK)
2947 #define SEI_CTRL_DMA_EN_SMP_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_SMP_ERR_MASK) >> SEI_CTRL_DMA_EN_SMP_ERR_SHIFT)
2948 
2949 /*
2950  * LATCH3 (RW)
2951  *
2952  * Latch3
2953  */
2954 #define SEI_CTRL_DMA_EN_LATCH3_MASK (0x80000UL)
2955 #define SEI_CTRL_DMA_EN_LATCH3_SHIFT (19U)
2956 #define SEI_CTRL_DMA_EN_LATCH3_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_LATCH3_SHIFT) & SEI_CTRL_DMA_EN_LATCH3_MASK)
2957 #define SEI_CTRL_DMA_EN_LATCH3_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_LATCH3_MASK) >> SEI_CTRL_DMA_EN_LATCH3_SHIFT)
2958 
2959 /*
2960  * LATCH2 (RW)
2961  *
2962  * Latch2
2963  */
2964 #define SEI_CTRL_DMA_EN_LATCH2_MASK (0x40000UL)
2965 #define SEI_CTRL_DMA_EN_LATCH2_SHIFT (18U)
2966 #define SEI_CTRL_DMA_EN_LATCH2_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_LATCH2_SHIFT) & SEI_CTRL_DMA_EN_LATCH2_MASK)
2967 #define SEI_CTRL_DMA_EN_LATCH2_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_LATCH2_MASK) >> SEI_CTRL_DMA_EN_LATCH2_SHIFT)
2968 
2969 /*
2970  * LATCH1 (RW)
2971  *
2972  * Latch1
2973  */
2974 #define SEI_CTRL_DMA_EN_LATCH1_MASK (0x20000UL)
2975 #define SEI_CTRL_DMA_EN_LATCH1_SHIFT (17U)
2976 #define SEI_CTRL_DMA_EN_LATCH1_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_LATCH1_SHIFT) & SEI_CTRL_DMA_EN_LATCH1_MASK)
2977 #define SEI_CTRL_DMA_EN_LATCH1_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_LATCH1_MASK) >> SEI_CTRL_DMA_EN_LATCH1_SHIFT)
2978 
2979 /*
2980  * LATCH0 (RW)
2981  *
2982  * Latch0
2983  */
2984 #define SEI_CTRL_DMA_EN_LATCH0_MASK (0x10000UL)
2985 #define SEI_CTRL_DMA_EN_LATCH0_SHIFT (16U)
2986 #define SEI_CTRL_DMA_EN_LATCH0_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_LATCH0_SHIFT) & SEI_CTRL_DMA_EN_LATCH0_MASK)
2987 #define SEI_CTRL_DMA_EN_LATCH0_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_LATCH0_MASK) >> SEI_CTRL_DMA_EN_LATCH0_SHIFT)
2988 
2989 /*
2990  * TIMEOUT (RW)
2991  *
2992  * Timeout
2993  */
2994 #define SEI_CTRL_DMA_EN_TIMEOUT_MASK (0x2000U)
2995 #define SEI_CTRL_DMA_EN_TIMEOUT_SHIFT (13U)
2996 #define SEI_CTRL_DMA_EN_TIMEOUT_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TIMEOUT_SHIFT) & SEI_CTRL_DMA_EN_TIMEOUT_MASK)
2997 #define SEI_CTRL_DMA_EN_TIMEOUT_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TIMEOUT_MASK) >> SEI_CTRL_DMA_EN_TIMEOUT_SHIFT)
2998 
2999 /*
3000  * TRX_ERR (RW)
3001  *
3002  * Transfer error
3003  */
3004 #define SEI_CTRL_DMA_EN_TRX_ERR_MASK (0x1000U)
3005 #define SEI_CTRL_DMA_EN_TRX_ERR_SHIFT (12U)
3006 #define SEI_CTRL_DMA_EN_TRX_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRX_ERR_SHIFT) & SEI_CTRL_DMA_EN_TRX_ERR_MASK)
3007 #define SEI_CTRL_DMA_EN_TRX_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRX_ERR_MASK) >> SEI_CTRL_DMA_EN_TRX_ERR_SHIFT)
3008 
3009 /*
3010  * INSTR1_END (RW)
3011  *
3012  * Instruction 1 end
3013  */
3014 #define SEI_CTRL_DMA_EN_INSTR1_END_MASK (0x800U)
3015 #define SEI_CTRL_DMA_EN_INSTR1_END_SHIFT (11U)
3016 #define SEI_CTRL_DMA_EN_INSTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_INSTR1_END_SHIFT) & SEI_CTRL_DMA_EN_INSTR1_END_MASK)
3017 #define SEI_CTRL_DMA_EN_INSTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_INSTR1_END_MASK) >> SEI_CTRL_DMA_EN_INSTR1_END_SHIFT)
3018 
3019 /*
3020  * INSTR0_END (RW)
3021  *
3022  * Instruction 0 end
3023  */
3024 #define SEI_CTRL_DMA_EN_INSTR0_END_MASK (0x400U)
3025 #define SEI_CTRL_DMA_EN_INSTR0_END_SHIFT (10U)
3026 #define SEI_CTRL_DMA_EN_INSTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_INSTR0_END_SHIFT) & SEI_CTRL_DMA_EN_INSTR0_END_MASK)
3027 #define SEI_CTRL_DMA_EN_INSTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_INSTR0_END_MASK) >> SEI_CTRL_DMA_EN_INSTR0_END_SHIFT)
3028 
3029 /*
3030  * PTR1_END (RW)
3031  *
3032  * Pointer 1 end
3033  */
3034 #define SEI_CTRL_DMA_EN_PTR1_END_MASK (0x200U)
3035 #define SEI_CTRL_DMA_EN_PTR1_END_SHIFT (9U)
3036 #define SEI_CTRL_DMA_EN_PTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_PTR1_END_SHIFT) & SEI_CTRL_DMA_EN_PTR1_END_MASK)
3037 #define SEI_CTRL_DMA_EN_PTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_PTR1_END_MASK) >> SEI_CTRL_DMA_EN_PTR1_END_SHIFT)
3038 
3039 /*
3040  * PTR0_END (RW)
3041  *
3042  * Pointer 0 end
3043  */
3044 #define SEI_CTRL_DMA_EN_PTR0_END_MASK (0x100U)
3045 #define SEI_CTRL_DMA_EN_PTR0_END_SHIFT (8U)
3046 #define SEI_CTRL_DMA_EN_PTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_PTR0_END_SHIFT) & SEI_CTRL_DMA_EN_PTR0_END_MASK)
3047 #define SEI_CTRL_DMA_EN_PTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_PTR0_END_MASK) >> SEI_CTRL_DMA_EN_PTR0_END_SHIFT)
3048 
3049 /*
3050  * INSTR1_ST (RW)
3051  *
3052  * Instruction 1 start
3053  */
3054 #define SEI_CTRL_DMA_EN_INSTR1_ST_MASK (0x80U)
3055 #define SEI_CTRL_DMA_EN_INSTR1_ST_SHIFT (7U)
3056 #define SEI_CTRL_DMA_EN_INSTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_INSTR1_ST_SHIFT) & SEI_CTRL_DMA_EN_INSTR1_ST_MASK)
3057 #define SEI_CTRL_DMA_EN_INSTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_INSTR1_ST_MASK) >> SEI_CTRL_DMA_EN_INSTR1_ST_SHIFT)
3058 
3059 /*
3060  * INSTR0_ST (RW)
3061  *
3062  * Instruction 0 start
3063  */
3064 #define SEI_CTRL_DMA_EN_INSTR0_ST_MASK (0x40U)
3065 #define SEI_CTRL_DMA_EN_INSTR0_ST_SHIFT (6U)
3066 #define SEI_CTRL_DMA_EN_INSTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_INSTR0_ST_SHIFT) & SEI_CTRL_DMA_EN_INSTR0_ST_MASK)
3067 #define SEI_CTRL_DMA_EN_INSTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_INSTR0_ST_MASK) >> SEI_CTRL_DMA_EN_INSTR0_ST_SHIFT)
3068 
3069 /*
3070  * PTR1_ST (RW)
3071  *
3072  * Pointer 1 start
3073  */
3074 #define SEI_CTRL_DMA_EN_PTR1_ST_MASK (0x20U)
3075 #define SEI_CTRL_DMA_EN_PTR1_ST_SHIFT (5U)
3076 #define SEI_CTRL_DMA_EN_PTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_PTR1_ST_SHIFT) & SEI_CTRL_DMA_EN_PTR1_ST_MASK)
3077 #define SEI_CTRL_DMA_EN_PTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_PTR1_ST_MASK) >> SEI_CTRL_DMA_EN_PTR1_ST_SHIFT)
3078 
3079 /*
3080  * PTR0_ST (RW)
3081  *
3082  * Pointer 0 start
3083  */
3084 #define SEI_CTRL_DMA_EN_PTR0_ST_MASK (0x10U)
3085 #define SEI_CTRL_DMA_EN_PTR0_ST_SHIFT (4U)
3086 #define SEI_CTRL_DMA_EN_PTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_PTR0_ST_SHIFT) & SEI_CTRL_DMA_EN_PTR0_ST_MASK)
3087 #define SEI_CTRL_DMA_EN_PTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_PTR0_ST_MASK) >> SEI_CTRL_DMA_EN_PTR0_ST_SHIFT)
3088 
3089 /*
3090  * WDOG (RW)
3091  *
3092  * Watch dog
3093  */
3094 #define SEI_CTRL_DMA_EN_WDOG_MASK (0x4U)
3095 #define SEI_CTRL_DMA_EN_WDOG_SHIFT (2U)
3096 #define SEI_CTRL_DMA_EN_WDOG_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_WDOG_SHIFT) & SEI_CTRL_DMA_EN_WDOG_MASK)
3097 #define SEI_CTRL_DMA_EN_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_WDOG_MASK) >> SEI_CTRL_DMA_EN_WDOG_SHIFT)
3098 
3099 /*
3100  * EXCEPT (RW)
3101  *
3102  * Exception
3103  */
3104 #define SEI_CTRL_DMA_EN_EXCEPT_MASK (0x2U)
3105 #define SEI_CTRL_DMA_EN_EXCEPT_SHIFT (1U)
3106 #define SEI_CTRL_DMA_EN_EXCEPT_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_EXCEPT_SHIFT) & SEI_CTRL_DMA_EN_EXCEPT_MASK)
3107 #define SEI_CTRL_DMA_EN_EXCEPT_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_EXCEPT_MASK) >> SEI_CTRL_DMA_EN_EXCEPT_SHIFT)
3108 
3109 /*
3110  * STALL (RW)
3111  *
3112  * Stall
3113  */
3114 #define SEI_CTRL_DMA_EN_STALL_MASK (0x1U)
3115 #define SEI_CTRL_DMA_EN_STALL_SHIFT (0U)
3116 #define SEI_CTRL_DMA_EN_STALL_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_STALL_SHIFT) & SEI_CTRL_DMA_EN_STALL_MASK)
3117 #define SEI_CTRL_DMA_EN_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_STALL_MASK) >> SEI_CTRL_DMA_EN_STALL_SHIFT)
3118 
3119 /* Bitfield definition for register array: INSTR */
3120 /*
3121  * OP (RW)
3122  *
3123  * operation
3124  * 0: halt
3125  * 1: jump
3126  * 2: send with timeout check
3127  * 3: send without timout check
3128  * 4: wait with timeout check
3129  * 5: wait without timout check
3130  * 6: receive with timeout check
3131  * 7: receive without timout check
3132  */
3133 #define SEI_INSTR_OP_MASK (0x1C000000UL)
3134 #define SEI_INSTR_OP_SHIFT (26U)
3135 #define SEI_INSTR_OP_SET(x) (((uint32_t)(x) << SEI_INSTR_OP_SHIFT) & SEI_INSTR_OP_MASK)
3136 #define SEI_INSTR_OP_GET(x) (((uint32_t)(x) & SEI_INSTR_OP_MASK) >> SEI_INSTR_OP_SHIFT)
3137 
3138 /*
3139  * CK (RW)
3140  *
3141  * clock state configure
3142  * a. In synchronous master mode:
3143  * 0: low
3144  * 1: rise-fall
3145  * 2: fall-rise
3146  * 3: high
3147  * b. In synchronous slave mode:
3148  * 0：Use TX_POINT and RX_POINT as the timing for data transmission and reception. Disable the TIMEOUT function in the communication protocol( this is not WDG).
3149  * 1：Switch the timing for data transmission and reception (e.g., switching edges for receive/transmit in an EnDat Encoder communication cycle). Disable the TIMEOUT function in the communication protocol.
3150  * 2：Use TX_POINT and RX_POINT as the timing for data transmission and receptionï¼›Enable the TIMEOUT function in the communication protocol.
3151  * 3：Switch the timing for data transmission and reception. Enable the TIMEOUT function in the communication protocol.
3152  * c. In asynchronous mode: please keep 0.
3153  */
3154 #define SEI_INSTR_CK_MASK (0x3000000UL)
3155 #define SEI_INSTR_CK_SHIFT (24U)
3156 #define SEI_INSTR_CK_SET(x) (((uint32_t)(x) << SEI_INSTR_CK_SHIFT) & SEI_INSTR_CK_MASK)
3157 #define SEI_INSTR_CK_GET(x) (((uint32_t)(x) & SEI_INSTR_CK_MASK) >> SEI_INSTR_CK_SHIFT)
3158 
3159 /*
3160  * CRC (RW)
3161  *
3162  * CRC register
3163  * 0: don't calculate CRC
3164  * 1: do not set this value
3165  * 2: data register 2
3166  * 3: data register 3
3167  * ...
3168  * 29: data register 29
3169  * 30: do not set this value
3170  * 31: do not set this value
3171  */
3172 #define SEI_INSTR_CRC_MASK (0x1F0000UL)
3173 #define SEI_INSTR_CRC_SHIFT (16U)
3174 #define SEI_INSTR_CRC_SET(x) (((uint32_t)(x) << SEI_INSTR_CRC_SHIFT) & SEI_INSTR_CRC_MASK)
3175 #define SEI_INSTR_CRC_GET(x) (((uint32_t)(x) & SEI_INSTR_CRC_MASK) >> SEI_INSTR_CRC_SHIFT)
3176 
3177 /*
3178  * DAT (RW)
3179  *
3180  * DATA register
3181  * 0: ignore data
3182  * 1: command
3183  * 2: data register 2
3184  * 3: data register 3
3185  * ...
3186  * 29: data register 29
3187  * 30: value 0 when send, wait 0 in receive
3188  * 31: value1 when send, wait 1 in receive
3189  */
3190 #define SEI_INSTR_DAT_MASK (0x1F00U)
3191 #define SEI_INSTR_DAT_SHIFT (8U)
3192 #define SEI_INSTR_DAT_SET(x) (((uint32_t)(x) << SEI_INSTR_DAT_SHIFT) & SEI_INSTR_DAT_MASK)
3193 #define SEI_INSTR_DAT_GET(x) (((uint32_t)(x) & SEI_INSTR_DAT_MASK) >> SEI_INSTR_DAT_SHIFT)
3194 
3195 /*
3196  * OPR (RW)
3197  *
3198  * a. When OP is 0, this area is the halt time in baudrate, 0 represents infinite time.
3199  * b. When OP is 1, this area is the the pointer to the command table.
3200  * OPR[4]=1, OPR[3:0] value is CMD_TABLE instruct pointer;
3201  * OPR[4]=0, OPR[3:0]=0 is INIT_POINTER;
3202  * OPR[4]=0, OPR[3:0]=1 is WDG_POINTER.
3203  * c. When OP is 2-7, this area is the data length as fellow:
3204  * 0: 1 bit
3205  * 1: 2 bit
3206  * ...
3207  * 31: 32 bit
3208  */
3209 #define SEI_INSTR_OPR_MASK (0x1FU)
3210 #define SEI_INSTR_OPR_SHIFT (0U)
3211 #define SEI_INSTR_OPR_SET(x) (((uint32_t)(x) << SEI_INSTR_OPR_SHIFT) & SEI_INSTR_OPR_MASK)
3212 #define SEI_INSTR_OPR_GET(x) (((uint32_t)(x) & SEI_INSTR_OPR_MASK) >> SEI_INSTR_OPR_SHIFT)
3213 
3214 /* Bitfield definition for register of struct array DAT: MODE */
3215 /*
3216  * CRC_LEN (RW)
3217  *
3218  * CRC length
3219  * 0: 1 bit
3220  * 1: 2 bit
3221  * ...
3222  * 31: 32 bit
3223  */
3224 #define SEI_DAT_MODE_CRC_LEN_MASK (0x1F000000UL)
3225 #define SEI_DAT_MODE_CRC_LEN_SHIFT (24U)
3226 #define SEI_DAT_MODE_CRC_LEN_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_CRC_LEN_SHIFT) & SEI_DAT_MODE_CRC_LEN_MASK)
3227 #define SEI_DAT_MODE_CRC_LEN_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_CRC_LEN_MASK) >> SEI_DAT_MODE_CRC_LEN_SHIFT)
3228 
3229 /*
3230  * WLEN (RW)
3231  *
3232  * word length
3233  * 0: 1 bit
3234  * 1: 2 bit
3235  * ...
3236  * 31: 32 bit
3237  */
3238 #define SEI_DAT_MODE_WLEN_MASK (0x1F0000UL)
3239 #define SEI_DAT_MODE_WLEN_SHIFT (16U)
3240 #define SEI_DAT_MODE_WLEN_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_WLEN_SHIFT) & SEI_DAT_MODE_WLEN_MASK)
3241 #define SEI_DAT_MODE_WLEN_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_WLEN_MASK) >> SEI_DAT_MODE_WLEN_SHIFT)
3242 
3243 /*
3244  * CRC_SHIFT (RW)
3245  *
3246  * CRC shift mode, this mode is used to perform repeat code check
3247  * 0: CRC
3248  * 1: shift mode
3249  */
3250 #define SEI_DAT_MODE_CRC_SHIFT_MASK (0x2000U)
3251 #define SEI_DAT_MODE_CRC_SHIFT_SHIFT (13U)
3252 #define SEI_DAT_MODE_CRC_SHIFT_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_CRC_SHIFT_SHIFT) & SEI_DAT_MODE_CRC_SHIFT_MASK)
3253 #define SEI_DAT_MODE_CRC_SHIFT_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_CRC_SHIFT_MASK) >> SEI_DAT_MODE_CRC_SHIFT_SHIFT)
3254 
3255 /*
3256  * CRC_INV (RW)
3257  *
3258  * CRC invert
3259  * 0: use CRC
3260  * 1: use inverted CRC
3261  */
3262 #define SEI_DAT_MODE_CRC_INV_MASK (0x1000U)
3263 #define SEI_DAT_MODE_CRC_INV_SHIFT (12U)
3264 #define SEI_DAT_MODE_CRC_INV_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_CRC_INV_SHIFT) & SEI_DAT_MODE_CRC_INV_MASK)
3265 #define SEI_DAT_MODE_CRC_INV_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_CRC_INV_MASK) >> SEI_DAT_MODE_CRC_INV_SHIFT)
3266 
3267 /*
3268  * WORDER (RW)
3269  *
3270  * word order
3271  * 0: sample as bit order
3272  * 1: different from bit order
3273  */
3274 #define SEI_DAT_MODE_WORDER_MASK (0x800U)
3275 #define SEI_DAT_MODE_WORDER_SHIFT (11U)
3276 #define SEI_DAT_MODE_WORDER_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_WORDER_SHIFT) & SEI_DAT_MODE_WORDER_MASK)
3277 #define SEI_DAT_MODE_WORDER_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_WORDER_MASK) >> SEI_DAT_MODE_WORDER_SHIFT)
3278 
3279 /*
3280  * BORDER (RW)
3281  *
3282  * bit order
3283  * 0: LSB first
3284  * 1: MSB first
3285  */
3286 #define SEI_DAT_MODE_BORDER_MASK (0x400U)
3287 #define SEI_DAT_MODE_BORDER_SHIFT (10U)
3288 #define SEI_DAT_MODE_BORDER_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_BORDER_SHIFT) & SEI_DAT_MODE_BORDER_MASK)
3289 #define SEI_DAT_MODE_BORDER_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_BORDER_MASK) >> SEI_DAT_MODE_BORDER_SHIFT)
3290 
3291 /*
3292  * SIGNED (RW)
3293  *
3294  * Signed
3295  * 0: unsigned value
3296  * 1: signed value
3297  */
3298 #define SEI_DAT_MODE_SIGNED_MASK (0x200U)
3299 #define SEI_DAT_MODE_SIGNED_SHIFT (9U)
3300 #define SEI_DAT_MODE_SIGNED_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_SIGNED_SHIFT) & SEI_DAT_MODE_SIGNED_MASK)
3301 #define SEI_DAT_MODE_SIGNED_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_SIGNED_MASK) >> SEI_DAT_MODE_SIGNED_SHIFT)
3302 
3303 /*
3304  * REWIND (RW)
3305  *
3306  * Write 1 to rewind read/write pointer, this is a self clear bit
3307  */
3308 #define SEI_DAT_MODE_REWIND_MASK (0x100U)
3309 #define SEI_DAT_MODE_REWIND_SHIFT (8U)
3310 #define SEI_DAT_MODE_REWIND_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_REWIND_SHIFT) & SEI_DAT_MODE_REWIND_MASK)
3311 #define SEI_DAT_MODE_REWIND_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_REWIND_MASK) >> SEI_DAT_MODE_REWIND_SHIFT)
3312 
3313 /*
3314  * MODE (RW)
3315  *
3316  * Data mode
3317  * 0: data mode
3318  * 1: check mode
3319  * 2: CRC mode
3320  */
3321 #define SEI_DAT_MODE_MODE_MASK (0x3U)
3322 #define SEI_DAT_MODE_MODE_SHIFT (0U)
3323 #define SEI_DAT_MODE_MODE_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_MODE_SHIFT) & SEI_DAT_MODE_MODE_MASK)
3324 #define SEI_DAT_MODE_MODE_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_MODE_MASK) >> SEI_DAT_MODE_MODE_SHIFT)
3325 
3326 /* Bitfield definition for register of struct array DAT: IDX */
3327 /*
3328  * LAST_BIT (RW)
3329  *
3330  * Last bit index for tranceive
3331  */
3332 #define SEI_DAT_IDX_LAST_BIT_MASK (0x1F000000UL)
3333 #define SEI_DAT_IDX_LAST_BIT_SHIFT (24U)
3334 #define SEI_DAT_IDX_LAST_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_LAST_BIT_SHIFT) & SEI_DAT_IDX_LAST_BIT_MASK)
3335 #define SEI_DAT_IDX_LAST_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_LAST_BIT_MASK) >> SEI_DAT_IDX_LAST_BIT_SHIFT)
3336 
3337 /*
3338  * FIRST_BIT (RW)
3339  *
3340  * First bit index for tranceive
3341  */
3342 #define SEI_DAT_IDX_FIRST_BIT_MASK (0x1F0000UL)
3343 #define SEI_DAT_IDX_FIRST_BIT_SHIFT (16U)
3344 #define SEI_DAT_IDX_FIRST_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_FIRST_BIT_SHIFT) & SEI_DAT_IDX_FIRST_BIT_MASK)
3345 #define SEI_DAT_IDX_FIRST_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_FIRST_BIT_MASK) >> SEI_DAT_IDX_FIRST_BIT_SHIFT)
3346 
3347 /*
3348  * MAX_BIT (RW)
3349  *
3350  * Highest bit index
3351  */
3352 #define SEI_DAT_IDX_MAX_BIT_MASK (0x1F00U)
3353 #define SEI_DAT_IDX_MAX_BIT_SHIFT (8U)
3354 #define SEI_DAT_IDX_MAX_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_MAX_BIT_SHIFT) & SEI_DAT_IDX_MAX_BIT_MASK)
3355 #define SEI_DAT_IDX_MAX_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_MAX_BIT_MASK) >> SEI_DAT_IDX_MAX_BIT_SHIFT)
3356 
3357 /*
3358  * MIN_BIT (RW)
3359  *
3360  * Lowest bit index
3361  */
3362 #define SEI_DAT_IDX_MIN_BIT_MASK (0x1FU)
3363 #define SEI_DAT_IDX_MIN_BIT_SHIFT (0U)
3364 #define SEI_DAT_IDX_MIN_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_MIN_BIT_SHIFT) & SEI_DAT_IDX_MIN_BIT_MASK)
3365 #define SEI_DAT_IDX_MIN_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_MIN_BIT_MASK) >> SEI_DAT_IDX_MIN_BIT_SHIFT)
3366 
3367 /* Bitfield definition for register of struct array DAT: GOLD */
3368 /*
3369  * GOLD_VALUE (RW)
3370  *
3371  * Gold value for check mode
3372  */
3373 #define SEI_DAT_GOLD_GOLD_VALUE_MASK (0xFFFFFFFFUL)
3374 #define SEI_DAT_GOLD_GOLD_VALUE_SHIFT (0U)
3375 #define SEI_DAT_GOLD_GOLD_VALUE_SET(x) (((uint32_t)(x) << SEI_DAT_GOLD_GOLD_VALUE_SHIFT) & SEI_DAT_GOLD_GOLD_VALUE_MASK)
3376 #define SEI_DAT_GOLD_GOLD_VALUE_GET(x) (((uint32_t)(x) & SEI_DAT_GOLD_GOLD_VALUE_MASK) >> SEI_DAT_GOLD_GOLD_VALUE_SHIFT)
3377 
3378 /* Bitfield definition for register of struct array DAT: CRCINIT */
3379 /*
3380  * CRC_INIT (RW)
3381  *
3382  * CRC initial value
3383  */
3384 #define SEI_DAT_CRCINIT_CRC_INIT_MASK (0xFFFFFFFFUL)
3385 #define SEI_DAT_CRCINIT_CRC_INIT_SHIFT (0U)
3386 #define SEI_DAT_CRCINIT_CRC_INIT_SET(x) (((uint32_t)(x) << SEI_DAT_CRCINIT_CRC_INIT_SHIFT) & SEI_DAT_CRCINIT_CRC_INIT_MASK)
3387 #define SEI_DAT_CRCINIT_CRC_INIT_GET(x) (((uint32_t)(x) & SEI_DAT_CRCINIT_CRC_INIT_MASK) >> SEI_DAT_CRCINIT_CRC_INIT_SHIFT)
3388 
3389 /* Bitfield definition for register of struct array DAT: CRCPOLY */
3390 /*
3391  * CRC_POLY (RW)
3392  *
3393  * CRC polymonial
3394  */
3395 #define SEI_DAT_CRCPOLY_CRC_POLY_MASK (0xFFFFFFFFUL)
3396 #define SEI_DAT_CRCPOLY_CRC_POLY_SHIFT (0U)
3397 #define SEI_DAT_CRCPOLY_CRC_POLY_SET(x) (((uint32_t)(x) << SEI_DAT_CRCPOLY_CRC_POLY_SHIFT) & SEI_DAT_CRCPOLY_CRC_POLY_MASK)
3398 #define SEI_DAT_CRCPOLY_CRC_POLY_GET(x) (((uint32_t)(x) & SEI_DAT_CRCPOLY_CRC_POLY_MASK) >> SEI_DAT_CRCPOLY_CRC_POLY_SHIFT)
3399 
3400 /* Bitfield definition for register of struct array DAT: DATA */
3401 /*
3402  * DATA (RW)
3403  *
3404  * DATA
3405  */
3406 #define SEI_DAT_DATA_DATA_MASK (0xFFFFFFFFUL)
3407 #define SEI_DAT_DATA_DATA_SHIFT (0U)
3408 #define SEI_DAT_DATA_DATA_SET(x) (((uint32_t)(x) << SEI_DAT_DATA_DATA_SHIFT) & SEI_DAT_DATA_DATA_MASK)
3409 #define SEI_DAT_DATA_DATA_GET(x) (((uint32_t)(x) & SEI_DAT_DATA_DATA_MASK) >> SEI_DAT_DATA_DATA_SHIFT)
3410 
3411 /* Bitfield definition for register of struct array DAT: SET */
3412 /*
3413  * DATA_SET (RW)
3414  *
3415  * DATA bit set
3416  */
3417 #define SEI_DAT_SET_DATA_SET_MASK (0xFFFFFFFFUL)
3418 #define SEI_DAT_SET_DATA_SET_SHIFT (0U)
3419 #define SEI_DAT_SET_DATA_SET_SET(x) (((uint32_t)(x) << SEI_DAT_SET_DATA_SET_SHIFT) & SEI_DAT_SET_DATA_SET_MASK)
3420 #define SEI_DAT_SET_DATA_SET_GET(x) (((uint32_t)(x) & SEI_DAT_SET_DATA_SET_MASK) >> SEI_DAT_SET_DATA_SET_SHIFT)
3421 
3422 /* Bitfield definition for register of struct array DAT: CLR */
3423 /*
3424  * DATA_CLR (RW)
3425  *
3426  * DATA bit clear
3427  */
3428 #define SEI_DAT_CLR_DATA_CLR_MASK (0xFFFFFFFFUL)
3429 #define SEI_DAT_CLR_DATA_CLR_SHIFT (0U)
3430 #define SEI_DAT_CLR_DATA_CLR_SET(x) (((uint32_t)(x) << SEI_DAT_CLR_DATA_CLR_SHIFT) & SEI_DAT_CLR_DATA_CLR_MASK)
3431 #define SEI_DAT_CLR_DATA_CLR_GET(x) (((uint32_t)(x) & SEI_DAT_CLR_DATA_CLR_MASK) >> SEI_DAT_CLR_DATA_CLR_SHIFT)
3432 
3433 /* Bitfield definition for register of struct array DAT: INV */
3434 /*
3435  * DATA_INV (RW)
3436  *
3437  * DATA bit toggle
3438  */
3439 #define SEI_DAT_INV_DATA_INV_MASK (0xFFFFFFFFUL)
3440 #define SEI_DAT_INV_DATA_INV_SHIFT (0U)
3441 #define SEI_DAT_INV_DATA_INV_SET(x) (((uint32_t)(x) << SEI_DAT_INV_DATA_INV_SHIFT) & SEI_DAT_INV_DATA_INV_MASK)
3442 #define SEI_DAT_INV_DATA_INV_GET(x) (((uint32_t)(x) & SEI_DAT_INV_DATA_INV_MASK) >> SEI_DAT_INV_DATA_INV_SHIFT)
3443 
3444 /* Bitfield definition for register of struct array DAT: IN */
3445 /*
3446  * DATA_IN (RO)
3447  *
3448  * Data input
3449  */
3450 #define SEI_DAT_IN_DATA_IN_MASK (0xFFFFFFFFUL)
3451 #define SEI_DAT_IN_DATA_IN_SHIFT (0U)
3452 #define SEI_DAT_IN_DATA_IN_GET(x) (((uint32_t)(x) & SEI_DAT_IN_DATA_IN_MASK) >> SEI_DAT_IN_DATA_IN_SHIFT)
3453 
3454 /* Bitfield definition for register of struct array DAT: OUT */
3455 /*
3456  * DATA_OUT (RO)
3457  *
3458  * Data output
3459  */
3460 #define SEI_DAT_OUT_DATA_OUT_MASK (0xFFFFFFFFUL)
3461 #define SEI_DAT_OUT_DATA_OUT_SHIFT (0U)
3462 #define SEI_DAT_OUT_DATA_OUT_GET(x) (((uint32_t)(x) & SEI_DAT_OUT_DATA_OUT_MASK) >> SEI_DAT_OUT_DATA_OUT_SHIFT)
3463 
3464 /* Bitfield definition for register of struct array DAT: STS */
3465 /*
3466  * CRC_IDX (RO)
3467  *
3468  * CRC index
3469  */
3470 #define SEI_DAT_STS_CRC_IDX_MASK (0x1F000000UL)
3471 #define SEI_DAT_STS_CRC_IDX_SHIFT (24U)
3472 #define SEI_DAT_STS_CRC_IDX_GET(x) (((uint32_t)(x) & SEI_DAT_STS_CRC_IDX_MASK) >> SEI_DAT_STS_CRC_IDX_SHIFT)
3473 
3474 /*
3475  * WORD_IDX (RO)
3476  *
3477  * Word index
3478  */
3479 #define SEI_DAT_STS_WORD_IDX_MASK (0x1F0000UL)
3480 #define SEI_DAT_STS_WORD_IDX_SHIFT (16U)
3481 #define SEI_DAT_STS_WORD_IDX_GET(x) (((uint32_t)(x) & SEI_DAT_STS_WORD_IDX_MASK) >> SEI_DAT_STS_WORD_IDX_SHIFT)
3482 
3483 /*
3484  * WORD_CNT (RO)
3485  *
3486  * Word counter
3487  */
3488 #define SEI_DAT_STS_WORD_CNT_MASK (0x1F00U)
3489 #define SEI_DAT_STS_WORD_CNT_SHIFT (8U)
3490 #define SEI_DAT_STS_WORD_CNT_GET(x) (((uint32_t)(x) & SEI_DAT_STS_WORD_CNT_MASK) >> SEI_DAT_STS_WORD_CNT_SHIFT)
3491 
3492 /*
3493  * BIT_IDX (RO)
3494  *
3495  * Bit index
3496  */
3497 #define SEI_DAT_STS_BIT_IDX_MASK (0x1FU)
3498 #define SEI_DAT_STS_BIT_IDX_SHIFT (0U)
3499 #define SEI_DAT_STS_BIT_IDX_GET(x) (((uint32_t)(x) & SEI_DAT_STS_BIT_IDX_MASK) >> SEI_DAT_STS_BIT_IDX_SHIFT)
3500 
3501 
3502 
3503 /* CMD register group index macro definition */
3504 #define SEI_CTRL_TRG_TABLE_CMD_0 (0UL)
3505 #define SEI_CTRL_TRG_TABLE_CMD_1 (1UL)
3506 #define SEI_CTRL_TRG_TABLE_CMD_2 (2UL)
3507 #define SEI_CTRL_TRG_TABLE_CMD_3 (3UL)
3508 
3509 /* TIME register group index macro definition */
3510 #define SEI_CTRL_TRG_TABLE_TIME_0 (0UL)
3511 #define SEI_CTRL_TRG_TABLE_TIME_1 (1UL)
3512 #define SEI_CTRL_TRG_TABLE_TIME_2 (2UL)
3513 #define SEI_CTRL_TRG_TABLE_TIME_3 (3UL)
3514 
3515 /* CMD_TABLE register group index macro definition */
3516 #define SEI_CMD_TABLE_0 (0UL)
3517 #define SEI_CMD_TABLE_1 (1UL)
3518 #define SEI_CMD_TABLE_2 (2UL)
3519 #define SEI_CMD_TABLE_3 (3UL)
3520 #define SEI_CMD_TABLE_4 (4UL)
3521 #define SEI_CMD_TABLE_5 (5UL)
3522 #define SEI_CMD_TABLE_6 (6UL)
3523 #define SEI_CMD_TABLE_7 (7UL)
3524 
3525 /* TRAN register group index macro definition */
3526 #define SEI_CTRL_LATCH_TRAN_0_1 (0UL)
3527 #define SEI_CTRL_LATCH_TRAN_1_2 (1UL)
3528 #define SEI_CTRL_LATCH_TRAN_2_3 (2UL)
3529 #define SEI_CTRL_LATCH_TRAN_3_0 (3UL)
3530 
3531 /* LATCH register group index macro definition */
3532 #define SEI_LATCH_0 (0UL)
3533 #define SEI_LATCH_1 (1UL)
3534 #define SEI_LATCH_2 (2UL)
3535 #define SEI_LATCH_3 (3UL)
3536 
3537 /* CTRL register group index macro definition */
3538 #define SEI_CTRL_0 (0UL)
3539 #define SEI_CTRL_1 (1UL)
3540 #define SEI_CTRL_2 (2UL)
3541 #define SEI_CTRL_3 (3UL)
3542 
3543 /* INSTR register group index macro definition */
3544 #define SEI_INSTR_0 (0UL)
3545 #define SEI_INSTR_1 (1UL)
3546 #define SEI_INSTR_2 (2UL)
3547 #define SEI_INSTR_3 (3UL)
3548 #define SEI_INSTR_4 (4UL)
3549 #define SEI_INSTR_5 (5UL)
3550 #define SEI_INSTR_6 (6UL)
3551 #define SEI_INSTR_7 (7UL)
3552 #define SEI_INSTR_8 (8UL)
3553 #define SEI_INSTR_9 (9UL)
3554 #define SEI_INSTR_10 (10UL)
3555 #define SEI_INSTR_11 (11UL)
3556 #define SEI_INSTR_12 (12UL)
3557 #define SEI_INSTR_13 (13UL)
3558 #define SEI_INSTR_14 (14UL)
3559 #define SEI_INSTR_15 (15UL)
3560 #define SEI_INSTR_16 (16UL)
3561 #define SEI_INSTR_17 (17UL)
3562 #define SEI_INSTR_18 (18UL)
3563 #define SEI_INSTR_19 (19UL)
3564 #define SEI_INSTR_20 (20UL)
3565 #define SEI_INSTR_21 (21UL)
3566 #define SEI_INSTR_22 (22UL)
3567 #define SEI_INSTR_23 (23UL)
3568 #define SEI_INSTR_24 (24UL)
3569 #define SEI_INSTR_25 (25UL)
3570 #define SEI_INSTR_26 (26UL)
3571 #define SEI_INSTR_27 (27UL)
3572 #define SEI_INSTR_28 (28UL)
3573 #define SEI_INSTR_29 (29UL)
3574 #define SEI_INSTR_30 (30UL)
3575 #define SEI_INSTR_31 (31UL)
3576 #define SEI_INSTR_32 (32UL)
3577 #define SEI_INSTR_33 (33UL)
3578 #define SEI_INSTR_34 (34UL)
3579 #define SEI_INSTR_35 (35UL)
3580 #define SEI_INSTR_36 (36UL)
3581 #define SEI_INSTR_37 (37UL)
3582 #define SEI_INSTR_38 (38UL)
3583 #define SEI_INSTR_39 (39UL)
3584 #define SEI_INSTR_40 (40UL)
3585 #define SEI_INSTR_41 (41UL)
3586 #define SEI_INSTR_42 (42UL)
3587 #define SEI_INSTR_43 (43UL)
3588 #define SEI_INSTR_44 (44UL)
3589 #define SEI_INSTR_45 (45UL)
3590 #define SEI_INSTR_46 (46UL)
3591 #define SEI_INSTR_47 (47UL)
3592 #define SEI_INSTR_48 (48UL)
3593 #define SEI_INSTR_49 (49UL)
3594 #define SEI_INSTR_50 (50UL)
3595 #define SEI_INSTR_51 (51UL)
3596 #define SEI_INSTR_52 (52UL)
3597 #define SEI_INSTR_53 (53UL)
3598 #define SEI_INSTR_54 (54UL)
3599 #define SEI_INSTR_55 (55UL)
3600 #define SEI_INSTR_56 (56UL)
3601 #define SEI_INSTR_57 (57UL)
3602 #define SEI_INSTR_58 (58UL)
3603 #define SEI_INSTR_59 (59UL)
3604 #define SEI_INSTR_60 (60UL)
3605 #define SEI_INSTR_61 (61UL)
3606 #define SEI_INSTR_62 (62UL)
3607 #define SEI_INSTR_63 (63UL)
3608 #define SEI_INSTR_64 (64UL)
3609 #define SEI_INSTR_65 (65UL)
3610 #define SEI_INSTR_66 (66UL)
3611 #define SEI_INSTR_67 (67UL)
3612 #define SEI_INSTR_68 (68UL)
3613 #define SEI_INSTR_69 (69UL)
3614 #define SEI_INSTR_70 (70UL)
3615 #define SEI_INSTR_71 (71UL)
3616 #define SEI_INSTR_72 (72UL)
3617 #define SEI_INSTR_73 (73UL)
3618 #define SEI_INSTR_74 (74UL)
3619 #define SEI_INSTR_75 (75UL)
3620 #define SEI_INSTR_76 (76UL)
3621 #define SEI_INSTR_77 (77UL)
3622 #define SEI_INSTR_78 (78UL)
3623 #define SEI_INSTR_79 (79UL)
3624 #define SEI_INSTR_80 (80UL)
3625 #define SEI_INSTR_81 (81UL)
3626 #define SEI_INSTR_82 (82UL)
3627 #define SEI_INSTR_83 (83UL)
3628 #define SEI_INSTR_84 (84UL)
3629 #define SEI_INSTR_85 (85UL)
3630 #define SEI_INSTR_86 (86UL)
3631 #define SEI_INSTR_87 (87UL)
3632 #define SEI_INSTR_88 (88UL)
3633 #define SEI_INSTR_89 (89UL)
3634 #define SEI_INSTR_90 (90UL)
3635 #define SEI_INSTR_91 (91UL)
3636 #define SEI_INSTR_92 (92UL)
3637 #define SEI_INSTR_93 (93UL)
3638 #define SEI_INSTR_94 (94UL)
3639 #define SEI_INSTR_95 (95UL)
3640 #define SEI_INSTR_96 (96UL)
3641 #define SEI_INSTR_97 (97UL)
3642 #define SEI_INSTR_98 (98UL)
3643 #define SEI_INSTR_99 (99UL)
3644 #define SEI_INSTR_100 (100UL)
3645 #define SEI_INSTR_101 (101UL)
3646 #define SEI_INSTR_102 (102UL)
3647 #define SEI_INSTR_103 (103UL)
3648 #define SEI_INSTR_104 (104UL)
3649 #define SEI_INSTR_105 (105UL)
3650 #define SEI_INSTR_106 (106UL)
3651 #define SEI_INSTR_107 (107UL)
3652 #define SEI_INSTR_108 (108UL)
3653 #define SEI_INSTR_109 (109UL)
3654 #define SEI_INSTR_110 (110UL)
3655 #define SEI_INSTR_111 (111UL)
3656 #define SEI_INSTR_112 (112UL)
3657 #define SEI_INSTR_113 (113UL)
3658 #define SEI_INSTR_114 (114UL)
3659 #define SEI_INSTR_115 (115UL)
3660 #define SEI_INSTR_116 (116UL)
3661 #define SEI_INSTR_117 (117UL)
3662 #define SEI_INSTR_118 (118UL)
3663 #define SEI_INSTR_119 (119UL)
3664 #define SEI_INSTR_120 (120UL)
3665 #define SEI_INSTR_121 (121UL)
3666 #define SEI_INSTR_122 (122UL)
3667 #define SEI_INSTR_123 (123UL)
3668 #define SEI_INSTR_124 (124UL)
3669 #define SEI_INSTR_125 (125UL)
3670 #define SEI_INSTR_126 (126UL)
3671 #define SEI_INSTR_127 (127UL)
3672 
3673 /* DAT register group index macro definition */
3674 #define SEI_DAT_0 (0UL)
3675 #define SEI_DAT_1 (1UL)
3676 #define SEI_DAT_2 (2UL)
3677 #define SEI_DAT_3 (3UL)
3678 #define SEI_DAT_4 (4UL)
3679 #define SEI_DAT_5 (5UL)
3680 #define SEI_DAT_6 (6UL)
3681 #define SEI_DAT_7 (7UL)
3682 #define SEI_DAT_8 (8UL)
3683 #define SEI_DAT_9 (9UL)
3684 #define SEI_DAT_10 (10UL)
3685 #define SEI_DAT_11 (11UL)
3686 #define SEI_DAT_12 (12UL)
3687 #define SEI_DAT_13 (13UL)
3688 #define SEI_DAT_14 (14UL)
3689 #define SEI_DAT_15 (15UL)
3690 #define SEI_DAT_16 (16UL)
3691 #define SEI_DAT_17 (17UL)
3692 
3693 
3694 #endif /* HPM_SEI_H */
MIN
#define MIN(a, b)
Definition: hpm_common.h:49
MAX
#define MAX(a, b)
Definition: hpm_common.h:46
SEI_Type
Definition: hpm_sei_regs.h:12