HPM SDK
HPMicro Software Development Kit
hpm_pdmlite_regs.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_PDMLITE_H
10 #define HPM_PDMLITE_H
11 
12 typedef struct {
13  __RW uint32_t CTRL; /* 0x0: Control Register */
14  __RW uint32_t CH_CTRL; /* 0x4: Channel Control Register */
15  __W uint32_t ST; /* 0x8: Status Register */
16  __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */
17  __RW uint32_t CIC_CFG; /* 0x10: CIC configuration register */
18  __R uint8_t RESERVED1[12]; /* 0x14 - 0x1F: Reserved */
19  __RW uint32_t RUN; /* 0x20: Run Register */
20 } PDMLITE_Type;
21 
22 
23 /* Bitfield definition for register: CTRL */
24 /*
25  * SFTRST (RW)
26  *
27  * software reset the module. Self-clear.
28  */
29 #define PDMLITE_CTRL_SFTRST_MASK (0x80000000UL)
30 #define PDMLITE_CTRL_SFTRST_SHIFT (31U)
31 #define PDMLITE_CTRL_SFTRST_SET(x) (((uint32_t)(x) << PDMLITE_CTRL_SFTRST_SHIFT) & PDMLITE_CTRL_SFTRST_MASK)
32 #define PDMLITE_CTRL_SFTRST_GET(x) (((uint32_t)(x) & PDMLITE_CTRL_SFTRST_MASK) >> PDMLITE_CTRL_SFTRST_SHIFT)
33 
34 /*
35  * SOF_FEDGE (RW)
36  *
37  * asserted if the falling edge of the ref fclk from DAO is the start of a new frame. This is used to to align DAO feedback signal.
38  */
39 #define PDMLITE_CTRL_SOF_FEDGE_MASK (0x800000UL)
40 #define PDMLITE_CTRL_SOF_FEDGE_SHIFT (23U)
41 #define PDMLITE_CTRL_SOF_FEDGE_SET(x) (((uint32_t)(x) << PDMLITE_CTRL_SOF_FEDGE_SHIFT) & PDMLITE_CTRL_SOF_FEDGE_MASK)
42 #define PDMLITE_CTRL_SOF_FEDGE_GET(x) (((uint32_t)(x) & PDMLITE_CTRL_SOF_FEDGE_MASK) >> PDMLITE_CTRL_SOF_FEDGE_SHIFT)
43 
44 /*
45  * OFIFO_OVFL_ERR_IE (RW)
46  *
47  * output fifo overflow error interrupt enable
48  */
49 #define PDMLITE_CTRL_OFIFO_OVFL_ERR_IE_MASK (0x40000UL)
50 #define PDMLITE_CTRL_OFIFO_OVFL_ERR_IE_SHIFT (18U)
51 #define PDMLITE_CTRL_OFIFO_OVFL_ERR_IE_SET(x) (((uint32_t)(x) << PDMLITE_CTRL_OFIFO_OVFL_ERR_IE_SHIFT) & PDMLITE_CTRL_OFIFO_OVFL_ERR_IE_MASK)
52 #define PDMLITE_CTRL_OFIFO_OVFL_ERR_IE_GET(x) (((uint32_t)(x) & PDMLITE_CTRL_OFIFO_OVFL_ERR_IE_MASK) >> PDMLITE_CTRL_OFIFO_OVFL_ERR_IE_SHIFT)
53 
54 /*
55  * CIC_OVLD_ERR_IE (RW)
56  *
57  * CIC overload error interrupt enable
58  */
59 #define PDMLITE_CTRL_CIC_OVLD_ERR_IE_MASK (0x20000UL)
60 #define PDMLITE_CTRL_CIC_OVLD_ERR_IE_SHIFT (17U)
61 #define PDMLITE_CTRL_CIC_OVLD_ERR_IE_SET(x) (((uint32_t)(x) << PDMLITE_CTRL_CIC_OVLD_ERR_IE_SHIFT) & PDMLITE_CTRL_CIC_OVLD_ERR_IE_MASK)
62 #define PDMLITE_CTRL_CIC_OVLD_ERR_IE_GET(x) (((uint32_t)(x) & PDMLITE_CTRL_CIC_OVLD_ERR_IE_MASK) >> PDMLITE_CTRL_CIC_OVLD_ERR_IE_SHIFT)
63 
64 /*
65  * CIC_SAT_ERR_IE (RW)
66  *
67  * Error interrupt enable
68  * This bit controls the generation of an interrupt when an error condition (CIC saturation) occurs.
69  * 0: Error interrupt is masked
70  * 1: Error interrupt is enabled
71  */
72 #define PDMLITE_CTRL_CIC_SAT_ERR_IE_MASK (0x10000UL)
73 #define PDMLITE_CTRL_CIC_SAT_ERR_IE_SHIFT (16U)
74 #define PDMLITE_CTRL_CIC_SAT_ERR_IE_SET(x) (((uint32_t)(x) << PDMLITE_CTRL_CIC_SAT_ERR_IE_SHIFT) & PDMLITE_CTRL_CIC_SAT_ERR_IE_MASK)
75 #define PDMLITE_CTRL_CIC_SAT_ERR_IE_GET(x) (((uint32_t)(x) & PDMLITE_CTRL_CIC_SAT_ERR_IE_MASK) >> PDMLITE_CTRL_CIC_SAT_ERR_IE_SHIFT)
76 
77 /*
78  * CAPT_DLY (RW)
79  *
80  * Capture cycle delay>=0, should be less than PDM_CLK_HFDIV
81  */
82 #define PDMLITE_CTRL_CAPT_DLY_MASK (0x780U)
83 #define PDMLITE_CTRL_CAPT_DLY_SHIFT (7U)
84 #define PDMLITE_CTRL_CAPT_DLY_SET(x) (((uint32_t)(x) << PDMLITE_CTRL_CAPT_DLY_SHIFT) & PDMLITE_CTRL_CAPT_DLY_MASK)
85 #define PDMLITE_CTRL_CAPT_DLY_GET(x) (((uint32_t)(x) & PDMLITE_CTRL_CAPT_DLY_MASK) >> PDMLITE_CTRL_CAPT_DLY_SHIFT)
86 
87 /*
88  * PDM_CLK_HFDIV (RW)
89  *
90  * The clock divider will work at least 4.
91  * 0: div-by-2,
92  * 1: div-by-4
93  * . . .
94  * n: div-by-2*(n+1)
95  */
96 #define PDMLITE_CTRL_PDM_CLK_HFDIV_MASK (0x78U)
97 #define PDMLITE_CTRL_PDM_CLK_HFDIV_SHIFT (3U)
98 #define PDMLITE_CTRL_PDM_CLK_HFDIV_SET(x) (((uint32_t)(x) << PDMLITE_CTRL_PDM_CLK_HFDIV_SHIFT) & PDMLITE_CTRL_PDM_CLK_HFDIV_MASK)
99 #define PDMLITE_CTRL_PDM_CLK_HFDIV_GET(x) (((uint32_t)(x) & PDMLITE_CTRL_PDM_CLK_HFDIV_MASK) >> PDMLITE_CTRL_PDM_CLK_HFDIV_SHIFT)
100 
101 /*
102  * PDM_CLK_DIV_BYPASS (RW)
103  *
104  * asserted to bypass the pdm clock divider
105  */
106 #define PDMLITE_CTRL_PDM_CLK_DIV_BYPASS_MASK (0x4U)
107 #define PDMLITE_CTRL_PDM_CLK_DIV_BYPASS_SHIFT (2U)
108 #define PDMLITE_CTRL_PDM_CLK_DIV_BYPASS_SET(x) (((uint32_t)(x) << PDMLITE_CTRL_PDM_CLK_DIV_BYPASS_SHIFT) & PDMLITE_CTRL_PDM_CLK_DIV_BYPASS_MASK)
109 #define PDMLITE_CTRL_PDM_CLK_DIV_BYPASS_GET(x) (((uint32_t)(x) & PDMLITE_CTRL_PDM_CLK_DIV_BYPASS_MASK) >> PDMLITE_CTRL_PDM_CLK_DIV_BYPASS_SHIFT)
110 
111 /*
112  * PDM_CLK_OE (RW)
113  *
114  * pdm_clk_output_en
115  */
116 #define PDMLITE_CTRL_PDM_CLK_OE_MASK (0x2U)
117 #define PDMLITE_CTRL_PDM_CLK_OE_SHIFT (1U)
118 #define PDMLITE_CTRL_PDM_CLK_OE_SET(x) (((uint32_t)(x) << PDMLITE_CTRL_PDM_CLK_OE_SHIFT) & PDMLITE_CTRL_PDM_CLK_OE_MASK)
119 #define PDMLITE_CTRL_PDM_CLK_OE_GET(x) (((uint32_t)(x) & PDMLITE_CTRL_PDM_CLK_OE_MASK) >> PDMLITE_CTRL_PDM_CLK_OE_SHIFT)
120 
121 /* Bitfield definition for register: CH_CTRL */
122 /*
123  * CH_POL (RW)
124  *
125  * Asserted to select PDM_CLK high level captured, otherwise to select PDM_CLK low level captured.
126  */
127 #define PDMLITE_CH_CTRL_CH_POL_MASK (0xFF0000UL)
128 #define PDMLITE_CH_CTRL_CH_POL_SHIFT (16U)
129 #define PDMLITE_CH_CTRL_CH_POL_SET(x) (((uint32_t)(x) << PDMLITE_CH_CTRL_CH_POL_SHIFT) & PDMLITE_CH_CTRL_CH_POL_MASK)
130 #define PDMLITE_CH_CTRL_CH_POL_GET(x) (((uint32_t)(x) & PDMLITE_CH_CTRL_CH_POL_MASK) >> PDMLITE_CH_CTRL_CH_POL_SHIFT)
131 
132 /*
133  * CH_EN (RW)
134  *
135  * Asserted to enable the channel.
136  * Ch8 & 9 are refs.
137  * Ch0-7 are pdm mics.
138  */
139 #define PDMLITE_CH_CTRL_CH_EN_MASK (0x3FFU)
140 #define PDMLITE_CH_CTRL_CH_EN_SHIFT (0U)
141 #define PDMLITE_CH_CTRL_CH_EN_SET(x) (((uint32_t)(x) << PDMLITE_CH_CTRL_CH_EN_SHIFT) & PDMLITE_CH_CTRL_CH_EN_MASK)
142 #define PDMLITE_CH_CTRL_CH_EN_GET(x) (((uint32_t)(x) & PDMLITE_CH_CTRL_CH_EN_MASK) >> PDMLITE_CH_CTRL_CH_EN_SHIFT)
143 
144 /* Bitfield definition for register: ST */
145 /*
146  * OFIFO_OVFL_ERR (W1C)
147  *
148  * output fifo overflow error. The reason may be sampling frequency mismatch, either fast or slow.
149  */
150 #define PDMLITE_ST_OFIFO_OVFL_ERR_MASK (0x4U)
151 #define PDMLITE_ST_OFIFO_OVFL_ERR_SHIFT (2U)
152 #define PDMLITE_ST_OFIFO_OVFL_ERR_SET(x) (((uint32_t)(x) << PDMLITE_ST_OFIFO_OVFL_ERR_SHIFT) & PDMLITE_ST_OFIFO_OVFL_ERR_MASK)
153 #define PDMLITE_ST_OFIFO_OVFL_ERR_GET(x) (((uint32_t)(x) & PDMLITE_ST_OFIFO_OVFL_ERR_MASK) >> PDMLITE_ST_OFIFO_OVFL_ERR_SHIFT)
154 
155 /*
156  * CIC_OVLD_ERR (W1C)
157  *
158  * CIC overload error. write 1 clear
159  */
160 #define PDMLITE_ST_CIC_OVLD_ERR_MASK (0x2U)
161 #define PDMLITE_ST_CIC_OVLD_ERR_SHIFT (1U)
162 #define PDMLITE_ST_CIC_OVLD_ERR_SET(x) (((uint32_t)(x) << PDMLITE_ST_CIC_OVLD_ERR_SHIFT) & PDMLITE_ST_CIC_OVLD_ERR_MASK)
163 #define PDMLITE_ST_CIC_OVLD_ERR_GET(x) (((uint32_t)(x) & PDMLITE_ST_CIC_OVLD_ERR_MASK) >> PDMLITE_ST_CIC_OVLD_ERR_SHIFT)
164 
165 /*
166  * CIC_SAT_ERR (W1C)
167  *
168  * CIC saturation. Write 1 clear
169  */
170 #define PDMLITE_ST_CIC_SAT_ERR_MASK (0x1U)
171 #define PDMLITE_ST_CIC_SAT_ERR_SHIFT (0U)
172 #define PDMLITE_ST_CIC_SAT_ERR_SET(x) (((uint32_t)(x) << PDMLITE_ST_CIC_SAT_ERR_SHIFT) & PDMLITE_ST_CIC_SAT_ERR_MASK)
173 #define PDMLITE_ST_CIC_SAT_ERR_GET(x) (((uint32_t)(x) & PDMLITE_ST_CIC_SAT_ERR_MASK) >> PDMLITE_ST_CIC_SAT_ERR_SHIFT)
174 
175 /* Bitfield definition for register: CIC_CFG */
176 /*
177  * POST_SCALE (RW)
178  *
179  * the shift value after CIC results.
180  */
181 #define PDMLITE_CIC_CFG_POST_SCALE_MASK (0xFC00U)
182 #define PDMLITE_CIC_CFG_POST_SCALE_SHIFT (10U)
183 #define PDMLITE_CIC_CFG_POST_SCALE_SET(x) (((uint32_t)(x) << PDMLITE_CIC_CFG_POST_SCALE_SHIFT) & PDMLITE_CIC_CFG_POST_SCALE_MASK)
184 #define PDMLITE_CIC_CFG_POST_SCALE_GET(x) (((uint32_t)(x) & PDMLITE_CIC_CFG_POST_SCALE_MASK) >> PDMLITE_CIC_CFG_POST_SCALE_SHIFT)
185 
186 /*
187  * SGD (RW)
188  *
189  * Sigma_delta_order[1:0]
190  * 2'b00: 7
191  * 2'b01: 6
192  * 2'b10: 5
193  * Others: unused
194  */
195 #define PDMLITE_CIC_CFG_SGD_MASK (0x300U)
196 #define PDMLITE_CIC_CFG_SGD_SHIFT (8U)
197 #define PDMLITE_CIC_CFG_SGD_SET(x) (((uint32_t)(x) << PDMLITE_CIC_CFG_SGD_SHIFT) & PDMLITE_CIC_CFG_SGD_MASK)
198 #define PDMLITE_CIC_CFG_SGD_GET(x) (((uint32_t)(x) & PDMLITE_CIC_CFG_SGD_MASK) >> PDMLITE_CIC_CFG_SGD_SHIFT)
199 
200 /*
201  * CIC_DEC_RATIO (RW)
202  *
203  * CIC decimation factor
204  */
205 #define PDMLITE_CIC_CFG_CIC_DEC_RATIO_MASK (0xFFU)
206 #define PDMLITE_CIC_CFG_CIC_DEC_RATIO_SHIFT (0U)
207 #define PDMLITE_CIC_CFG_CIC_DEC_RATIO_SET(x) (((uint32_t)(x) << PDMLITE_CIC_CFG_CIC_DEC_RATIO_SHIFT) & PDMLITE_CIC_CFG_CIC_DEC_RATIO_MASK)
208 #define PDMLITE_CIC_CFG_CIC_DEC_RATIO_GET(x) (((uint32_t)(x) & PDMLITE_CIC_CFG_CIC_DEC_RATIO_MASK) >> PDMLITE_CIC_CFG_CIC_DEC_RATIO_SHIFT)
209 
210 /* Bitfield definition for register: RUN */
211 /*
212  * PDM_EN (RW)
213  *
214  * Asserted to enable the module
215  */
216 #define PDMLITE_RUN_PDM_EN_MASK (0x1U)
217 #define PDMLITE_RUN_PDM_EN_SHIFT (0U)
218 #define PDMLITE_RUN_PDM_EN_SET(x) (((uint32_t)(x) << PDMLITE_RUN_PDM_EN_SHIFT) & PDMLITE_RUN_PDM_EN_MASK)
219 #define PDMLITE_RUN_PDM_EN_GET(x) (((uint32_t)(x) & PDMLITE_RUN_PDM_EN_MASK) >> PDMLITE_RUN_PDM_EN_SHIFT)
220 
221 
222 
223 
224 #endif /* HPM_PDMLITE_H */
PDMLITE_Type
Definition: hpm_pdmlite_regs.h:12