HPM SDK
HPMicro Software Development Kit
hpm_sei_regs.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_SEI_H
10 #define HPM_SEI_H
11 
12 typedef struct {
13  struct {
14  struct {
15  __RW uint32_t CTRL; /* 0x0: Engine control register */
16  __RW uint32_t PTR_CFG; /* 0x4: Pointer configuration register */
17  __RW uint32_t WDG_CFG; /* 0x8: Watch dog configuration register */
18  __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */
19  __R uint32_t EXE_STA; /* 0x10: Execution status */
20  __R uint32_t EXE_PTR; /* 0x14: Execution pointer */
21  __R uint32_t EXE_INST; /* 0x18: Execution instruction */
22  __R uint32_t WDG_STA; /* 0x1C: Watch dog status */
23  } ENGINE;
24  struct {
25  __RW uint32_t CTRL; /* 0x20: Transceiver control register */
26  __RW uint32_t TYPE_CFG; /* 0x24: Transceiver configuration register */
27  __RW uint32_t BAUD_CFG; /* 0x28: Transceiver baud rate register */
28  __RW uint32_t DATA_CFG; /* 0x2C: Transceiver data timing configuration */
29  __RW uint32_t CLK_CFG; /* 0x30: Transceiver clock timing configuration */
30  __R uint8_t RESERVED0[4]; /* 0x34 - 0x37: Reserved */
31  __R uint32_t PIN; /* 0x38: Transceiver pin status */
32  __R uint32_t STATE; /* 0x3C: FSM of asynchronous */
33  } XCVR;
34  struct {
35  __RW uint32_t IN_CFG; /* 0x40: Trigger input configuration */
36  __W uint32_t SW; /* 0x44: Software trigger */
37  __RW uint32_t PRD_CFG; /* 0x48: Period trigger configuration */
38  __RW uint32_t PRD; /* 0x4C: Trigger period */
39  __RW uint32_t OUT_CFG; /* 0x50: Trigger output configuration */
40  __RW uint32_t IN_DIV; /* 0x54: Trigger input divider */
41  __R uint8_t RESERVED0[8]; /* 0x58 - 0x5F: Reserved */
42  __R uint32_t PRD_STS; /* 0x60: Period trigger status */
43  __R uint32_t PRD_CNT; /* 0x64: Period trigger counter */
44  __R uint32_t DIV_STS; /* 0x68: Trigger input divider status */
45  __R uint8_t RESERVED1[20]; /* 0x6C - 0x7F: Reserved */
46  } TRG;
47  struct {
48  __RW uint32_t CMD[4]; /* 0x80 - 0x8C: Trigger command */
49  __R uint8_t RESERVED0[16]; /* 0x90 - 0x9F: Reserved */
50  __R uint32_t TIME[4]; /* 0xA0 - 0xAC: Trigger Time */
51  __R uint8_t RESERVED1[16]; /* 0xB0 - 0xBF: Reserved */
52  } TRG_TABLE;
53  struct {
54  __RW uint32_t MODE; /* 0xC0: command register mode */
55  __RW uint32_t IDX; /* 0xC4: command register configuration */
56  __R uint8_t RESERVED0[24]; /* 0xC8 - 0xDF: Reserved */
57  __RW uint32_t CMD; /* 0xE0: command */
58  __RW uint32_t SET; /* 0xE4: command bit set register */
59  __RW uint32_t CLR; /* 0xE8: command bit clear register */
60  __RW uint32_t INV; /* 0xEC: command bit invert register */
61  __R uint32_t IN; /* 0xF0: Commad input */
62  __R uint32_t OUT; /* 0xF4: Command output */
63  __RW uint32_t STS; /* 0xF8: Command status */
64  __R uint8_t RESERVED1[4]; /* 0xFC - 0xFF: Reserved */
65  } CMD;
66  struct {
67  __RW uint32_t MIN; /* 0x100: command start value */
68  __RW uint32_t MAX; /* 0x104: command end value */
69  __RW uint32_t MSK; /* 0x108: command compare bit enable */
70  __R uint8_t RESERVED0[4]; /* 0x10C - 0x10F: Reserved */
71  __RW uint32_t PTA; /* 0x110: command pointer 0 - 3 */
72  __RW uint32_t PTB; /* 0x114: command pointer 4 - 7 */
73  __R uint8_t RESERVED1[8]; /* 0x118 - 0x11F: Reserved */
74  } CMD_TABLE[8];
75  struct {
76  __RW uint32_t TRAN[4]; /* 0x200 - 0x20C: Latch state transition configuration */
77  __RW uint32_t CFG; /* 0x210: Latch configuration */
78  __R uint8_t RESERVED0[4]; /* 0x214 - 0x217: Reserved */
79  __R uint32_t TIME; /* 0x218: Latch time */
80  __R uint32_t STS; /* 0x21C: Latch status */
81  } LATCH[4];
82  struct {
83  __RW uint32_t SMP_EN; /* 0x280: Sample selection register */
84  __RW uint32_t SMP_CFG; /* 0x284: Sample configuration */
85  __RW uint32_t SMP_DAT; /* 0x288: Sample data */
86  __R uint8_t RESERVED0[4]; /* 0x28C - 0x28F: Reserved */
87  __RW uint32_t SMP_POS; /* 0x290: Sample override position */
88  __RW uint32_t SMP_REV; /* 0x294: Sample override revolution */
89  __RW uint32_t SMP_SPD; /* 0x298: Sample override speed */
90  __RW uint32_t SMP_ACC; /* 0x29C: Sample override accelerate */
91  __RW uint32_t UPD_EN; /* 0x2A0: Update configuration */
92  __RW uint32_t UPD_CFG; /* 0x2A4: Update configuration */
93  __RW uint32_t UPD_DAT; /* 0x2A8: Update data */
94  __RW uint32_t UPD_TIME; /* 0x2AC: Update overide time */
95  __RW uint32_t UPD_POS; /* 0x2B0: Update override position */
96  __RW uint32_t UPD_REV; /* 0x2B4: Update override revolution */
97  __RW uint32_t UPD_SPD; /* 0x2B8: Update override speed */
98  __RW uint32_t UPD_ACC; /* 0x2BC: Update override accelerate */
99  __R uint32_t SMP_VAL; /* 0x2C0: Sample valid */
100  __R uint32_t SMP_STS; /* 0x2C4: Sample status */
101  __R uint8_t RESERVED1[4]; /* 0x2C8 - 0x2CB: Reserved */
102  __R uint32_t TIME_IN; /* 0x2CC: input time */
103  __R uint32_t POS_IN; /* 0x2D0: Input position */
104  __R uint32_t REV_IN; /* 0x2D4: Input revolution */
105  __R uint32_t SPD_IN; /* 0x2D8: Input speed */
106  __R uint32_t ACC_IN; /* 0x2DC: Input accelerate */
107  __R uint8_t RESERVED2[4]; /* 0x2E0 - 0x2E3: Reserved */
108  __R uint32_t UPD_STS; /* 0x2E4: Update status */
109  __R uint8_t RESERVED3[24]; /* 0x2E8 - 0x2FF: Reserved */
110  } POS;
111  struct {
112  __RW uint32_t INT_EN; /* 0x300: Interrupt Enable */
113  __W uint32_t INT_FLAG; /* 0x304: Interrupt flag */
114  __R uint32_t INT_STS; /* 0x308: Interrupt status */
115  __R uint8_t RESERVED0[4]; /* 0x30C - 0x30F: Reserved */
116  __RW uint32_t POINTER0; /* 0x310: Match pointer 0 */
117  __RW uint32_t POINTER1; /* 0x314: Match pointer 1 */
118  __RW uint32_t INSTR0; /* 0x318: Match instruction 0 */
119  __RW uint32_t INSTR1; /* 0x31C: Match instruction 1 */
120  } IRQ;
121  __RW uint32_t DMA_EN; /* 0x320: DMA Enable */
122  __R uint8_t RESERVED0[220]; /* 0x324 - 0x3FF: Reserved */
123  } CTRL[2];
124  __R uint8_t RESERVED0[11264]; /* 0x800 - 0x33FF: Reserved */
125  __RW uint32_t INSTR[128]; /* 0x3400 - 0x35FC: Instructions */
126  __R uint8_t RESERVED1[512]; /* 0x3600 - 0x37FF: Reserved */
127  struct {
128  __RW uint32_t MODE; /* 0x3800: */
129  __RW uint32_t IDX; /* 0x3804: Data register bit index */
130  __RW uint32_t GOLD; /* 0x3808: Gold data for data check */
131  __RW uint32_t CRCINIT; /* 0x380C: CRC calculation initial vector */
132  __RW uint32_t CRCPOLY; /* 0x3810: CRC calculation polynomial */
133  __R uint8_t RESERVED0[12]; /* 0x3814 - 0x381F: Reserved */
134  __RW uint32_t DATA; /* 0x3820: Data value */
135  __RW uint32_t SET; /* 0x3824: Data bit set */
136  __RW uint32_t CLR; /* 0x3828: Data bit clear */
137  __RW uint32_t INV; /* 0x382C: Data bit invert */
138  __R uint32_t IN; /* 0x3830: Data input */
139  __R uint32_t OUT; /* 0x3834: Data output */
140  __RW uint32_t STS; /* 0x3838: Data status */
141  __R uint8_t RESERVED1[4]; /* 0x383C - 0x383F: Reserved */
142  } DAT[18];
143 } SEI_Type;
144 
145 
146 /* Bitfield definition for register of struct array CTRL: CTRL */
147 /*
148  * WATCH (RW)
149  *
150  * Enable watch dog
151  * 0: Watch dog disabled
152  * 1: Watch dog enabled
153  */
154 #define SEI_CTRL_ENGINE_CTRL_WATCH_MASK (0x1000000UL)
155 #define SEI_CTRL_ENGINE_CTRL_WATCH_SHIFT (24U)
156 #define SEI_CTRL_ENGINE_CTRL_WATCH_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_WATCH_SHIFT) & SEI_CTRL_ENGINE_CTRL_WATCH_MASK)
157 #define SEI_CTRL_ENGINE_CTRL_WATCH_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_WATCH_MASK) >> SEI_CTRL_ENGINE_CTRL_WATCH_SHIFT)
158 
159 /*
160  * ARMING (RW)
161  *
162  * Wait for trigger before excuting
163  * 0: Execute on enable
164  * 1: Wait trigger before exection after enabled
165  */
166 #define SEI_CTRL_ENGINE_CTRL_ARMING_MASK (0x10000UL)
167 #define SEI_CTRL_ENGINE_CTRL_ARMING_SHIFT (16U)
168 #define SEI_CTRL_ENGINE_CTRL_ARMING_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_ARMING_SHIFT) & SEI_CTRL_ENGINE_CTRL_ARMING_MASK)
169 #define SEI_CTRL_ENGINE_CTRL_ARMING_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_ARMING_MASK) >> SEI_CTRL_ENGINE_CTRL_ARMING_SHIFT)
170 
171 /*
172  * EXCEPT (RW)
173  *
174  * Explain timout as exception
175  * 0: when timeout, pointer move to next instruction
176  * 1: when timeout, pointer jump to timeout vector
177  */
178 #define SEI_CTRL_ENGINE_CTRL_EXCEPT_MASK (0x100U)
179 #define SEI_CTRL_ENGINE_CTRL_EXCEPT_SHIFT (8U)
180 #define SEI_CTRL_ENGINE_CTRL_EXCEPT_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_EXCEPT_SHIFT) & SEI_CTRL_ENGINE_CTRL_EXCEPT_MASK)
181 #define SEI_CTRL_ENGINE_CTRL_EXCEPT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_EXCEPT_MASK) >> SEI_CTRL_ENGINE_CTRL_EXCEPT_SHIFT)
182 
183 /*
184  * REWIND (RW)
185  *
186  * Rewind execution pointer
187  * 0: run
188  * 1: clean status and rewind
189  */
190 #define SEI_CTRL_ENGINE_CTRL_REWIND_MASK (0x10U)
191 #define SEI_CTRL_ENGINE_CTRL_REWIND_SHIFT (4U)
192 #define SEI_CTRL_ENGINE_CTRL_REWIND_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_REWIND_SHIFT) & SEI_CTRL_ENGINE_CTRL_REWIND_MASK)
193 #define SEI_CTRL_ENGINE_CTRL_REWIND_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_REWIND_MASK) >> SEI_CTRL_ENGINE_CTRL_REWIND_SHIFT)
194 
195 /*
196  * ENABLE (RW)
197  *
198  * Enable
199  * 0: disable
200  * 1: enable
201  */
202 #define SEI_CTRL_ENGINE_CTRL_ENABLE_MASK (0x1U)
203 #define SEI_CTRL_ENGINE_CTRL_ENABLE_SHIFT (0U)
204 #define SEI_CTRL_ENGINE_CTRL_ENABLE_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_ENABLE_SHIFT) & SEI_CTRL_ENGINE_CTRL_ENABLE_MASK)
205 #define SEI_CTRL_ENGINE_CTRL_ENABLE_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_ENABLE_MASK) >> SEI_CTRL_ENGINE_CTRL_ENABLE_SHIFT)
206 
207 /* Bitfield definition for register of struct array CTRL: PTR_CFG */
208 /*
209  * DAT_CDM (RW)
210  *
211  * Select DATA register to receive CDM bit in BiSSC slave mode
212  * 0: ignore
213  * 1: command
214  * 2: data register 2
215  * 3: data register 3
216  * ...
217  * 29:data register 29
218  * 30: value 0 when send, ignore in receive
219  * 31: value1 when send, ignore in receive
220  */
221 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_MASK (0x1F000000UL)
222 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SHIFT (24U)
223 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_MASK)
224 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SHIFT)
225 
226 /*
227  * DAT_BASE (RW)
228  *
229  * Bias for data register access, if calculated index bigger than 32, index will wrap around
230  * 0: real data index
231  * 1: access index is 1 greater than instruction address
232  * 2: access index is 2 greater than instruction address
233  * ...
234  * 31: access index is 31 greater than instruction address
235  */
236 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_MASK (0x1F0000UL)
237 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SHIFT (16U)
238 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_MASK)
239 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SHIFT)
240 
241 /*
242  * POINTER_WDOG (RW)
243  *
244  * Pointer to the instruction that the program starts executing after the instruction timeout. The timeout is WDOG_TIME
245  */
246 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_MASK (0xFF00U)
247 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SHIFT (8U)
248 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_MASK)
249 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SHIFT)
250 
251 /*
252  * POINTER_INIT (RW)
253  *
254  * Initial execute pointer
255  */
256 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_MASK (0xFFU)
257 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SHIFT (0U)
258 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_MASK)
259 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SHIFT)
260 
261 /* Bitfield definition for register of struct array CTRL: WDG_CFG */
262 /*
263  * WDOG_TIME (RW)
264  *
265  * Time out count for each instruction, counter in bit time.
266  */
267 #define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_MASK (0xFFFFU)
268 #define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SHIFT (0U)
269 #define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SHIFT) & SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_MASK)
270 #define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_MASK) >> SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SHIFT)
271 
272 /* Bitfield definition for register of struct array CTRL: EXE_STA */
273 /*
274  * TRIGERED (RO)
275  *
276  * Execution has been triggered
277  * 0: Execution not triggered
278  * 1: Execution triggered
279  */
280 #define SEI_CTRL_ENGINE_EXE_STA_TRIGERED_MASK (0x100000UL)
281 #define SEI_CTRL_ENGINE_EXE_STA_TRIGERED_SHIFT (20U)
282 #define SEI_CTRL_ENGINE_EXE_STA_TRIGERED_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_TRIGERED_MASK) >> SEI_CTRL_ENGINE_EXE_STA_TRIGERED_SHIFT)
283 
284 /*
285  * ARMED (RO)
286  *
287  * Waiting for trigger for execution
288  * 0: Not in waiting status
289  * 1: In waiting status
290  */
291 #define SEI_CTRL_ENGINE_EXE_STA_ARMED_MASK (0x10000UL)
292 #define SEI_CTRL_ENGINE_EXE_STA_ARMED_SHIFT (16U)
293 #define SEI_CTRL_ENGINE_EXE_STA_ARMED_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_ARMED_MASK) >> SEI_CTRL_ENGINE_EXE_STA_ARMED_SHIFT)
294 
295 /*
296  * EXPIRE (RO)
297  *
298  * Watchdog timer expired
299  * 0: Not expired
300  * 1: Expired
301  */
302 #define SEI_CTRL_ENGINE_EXE_STA_EXPIRE_MASK (0x100U)
303 #define SEI_CTRL_ENGINE_EXE_STA_EXPIRE_SHIFT (8U)
304 #define SEI_CTRL_ENGINE_EXE_STA_EXPIRE_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_EXPIRE_MASK) >> SEI_CTRL_ENGINE_EXE_STA_EXPIRE_SHIFT)
305 
306 /*
307  * STALL (RO)
308  *
309  * Program finished
310  * 0: Program is executing
311  * 1: Program finished
312  */
313 #define SEI_CTRL_ENGINE_EXE_STA_STALL_MASK (0x1U)
314 #define SEI_CTRL_ENGINE_EXE_STA_STALL_SHIFT (0U)
315 #define SEI_CTRL_ENGINE_EXE_STA_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_STALL_MASK) >> SEI_CTRL_ENGINE_EXE_STA_STALL_SHIFT)
316 
317 /* Bitfield definition for register of struct array CTRL: EXE_PTR */
318 /*
319  * HALT_CNT (RO)
320  *
321  * Halt count in halt instrution
322  */
323 #define SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_MASK (0x1F000000UL)
324 #define SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_SHIFT (24U)
325 #define SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_MASK) >> SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_SHIFT)
326 
327 /*
328  * BIT_CNT (RO)
329  *
330  * Bit count in send and receive instruction execution
331  */
332 #define SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_MASK (0x1F0000UL)
333 #define SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_SHIFT (16U)
334 #define SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_MASK) >> SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_SHIFT)
335 
336 /*
337  * POINTER (RO)
338  *
339  * Current program pointer
340  */
341 #define SEI_CTRL_ENGINE_EXE_PTR_POINTER_MASK (0xFFU)
342 #define SEI_CTRL_ENGINE_EXE_PTR_POINTER_SHIFT (0U)
343 #define SEI_CTRL_ENGINE_EXE_PTR_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_PTR_POINTER_MASK) >> SEI_CTRL_ENGINE_EXE_PTR_POINTER_SHIFT)
344 
345 /* Bitfield definition for register of struct array CTRL: EXE_INST */
346 /*
347  * INST (RO)
348  *
349  * Current instruction
350  */
351 #define SEI_CTRL_ENGINE_EXE_INST_INST_MASK (0xFFFFFFFFUL)
352 #define SEI_CTRL_ENGINE_EXE_INST_INST_SHIFT (0U)
353 #define SEI_CTRL_ENGINE_EXE_INST_INST_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_INST_INST_MASK) >> SEI_CTRL_ENGINE_EXE_INST_INST_SHIFT)
354 
355 /* Bitfield definition for register of struct array CTRL: WDG_STA */
356 /*
357  * WDOG_CNT (RO)
358  *
359  * Current watch dog counter value
360  */
361 #define SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_MASK (0xFFFFU)
362 #define SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_SHIFT (0U)
363 #define SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_MASK) >> SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_SHIFT)
364 
365 /* Bitfield definition for register of struct array CTRL: CTRL */
366 /*
367  * TRISMP (RW)
368  *
369  * Tipple sampe
370  * 0: sample 1 time for data transition
371  * 1: sample 3 times in receive and result in 2oo3
372  */
373 #define SEI_CTRL_XCVR_CTRL_TRISMP_MASK (0x1000U)
374 #define SEI_CTRL_XCVR_CTRL_TRISMP_SHIFT (12U)
375 #define SEI_CTRL_XCVR_CTRL_TRISMP_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_TRISMP_SHIFT) & SEI_CTRL_XCVR_CTRL_TRISMP_MASK)
376 #define SEI_CTRL_XCVR_CTRL_TRISMP_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_TRISMP_MASK) >> SEI_CTRL_XCVR_CTRL_TRISMP_SHIFT)
377 
378 /*
379  * PAR_CLR (WC)
380  *
381  * Clear parity error, this is a self clear bit
382  * 0: no effect
383  * 1: clear parity error
384  */
385 #define SEI_CTRL_XCVR_CTRL_PAR_CLR_MASK (0x100U)
386 #define SEI_CTRL_XCVR_CTRL_PAR_CLR_SHIFT (8U)
387 #define SEI_CTRL_XCVR_CTRL_PAR_CLR_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_PAR_CLR_SHIFT) & SEI_CTRL_XCVR_CTRL_PAR_CLR_MASK)
388 #define SEI_CTRL_XCVR_CTRL_PAR_CLR_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_PAR_CLR_MASK) >> SEI_CTRL_XCVR_CTRL_PAR_CLR_SHIFT)
389 
390 /*
391  * RESTART (WC)
392  *
393  * Restart transceiver, this is a self clear bit
394  * 0: no effect
395  * 1: reset transceiver
396  */
397 #define SEI_CTRL_XCVR_CTRL_RESTART_MASK (0x10U)
398 #define SEI_CTRL_XCVR_CTRL_RESTART_SHIFT (4U)
399 #define SEI_CTRL_XCVR_CTRL_RESTART_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_RESTART_SHIFT) & SEI_CTRL_XCVR_CTRL_RESTART_MASK)
400 #define SEI_CTRL_XCVR_CTRL_RESTART_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_RESTART_MASK) >> SEI_CTRL_XCVR_CTRL_RESTART_SHIFT)
401 
402 /*
403  * MODE (RW)
404  *
405  * Transceiver mode
406  * 0: synchronous master
407  * 1: synchronous slave
408  * 2: asynchronous mode
409  * 3: asynchronous mode
410  */
411 #define SEI_CTRL_XCVR_CTRL_MODE_MASK (0x3U)
412 #define SEI_CTRL_XCVR_CTRL_MODE_SHIFT (0U)
413 #define SEI_CTRL_XCVR_CTRL_MODE_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_MODE_SHIFT) & SEI_CTRL_XCVR_CTRL_MODE_MASK)
414 #define SEI_CTRL_XCVR_CTRL_MODE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_MODE_MASK) >> SEI_CTRL_XCVR_CTRL_MODE_SHIFT)
415 
416 /* Bitfield definition for register of struct array CTRL: TYPE_CFG */
417 /*
418  * WAIT_LEN (RW)
419  *
420  * Number of extra stop bit for asynchronous mode
421  * 0: 1 bit
422  * 1: 2 bit
423  * ...
424  * 255: 256 bit
425  */
426 #define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_MASK (0xFF000000UL)
427 #define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SHIFT (24U)
428 #define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_MASK)
429 #define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SHIFT)
430 
431 /*
432  * DATA_LEN (RW)
433  *
434  * Number of data bit for asynchronous mode
435  * 0: 1 bit
436  * 1: 2 bit
437  * ...
438  * 31: 32 bit
439  */
440 #define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_MASK (0x1F0000UL)
441 #define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SHIFT (16U)
442 #define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_MASK)
443 #define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SHIFT)
444 
445 /*
446  * PAR_POL (RW)
447  *
448  * Polarity of parity for asynchronous mode
449  * 0: even
450  * 1: odd
451  */
452 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_MASK (0x200U)
453 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SHIFT (9U)
454 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_MASK)
455 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SHIFT)
456 
457 /*
458  * PAR_EN (RW)
459  *
460  * enable parity check for asynchronous mode
461  * 0: disable
462  * 1: enable
463  */
464 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_MASK (0x100U)
465 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SHIFT (8U)
466 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_MASK)
467 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SHIFT)
468 
469 /*
470  * DA_IDLEZ (RW)
471  *
472  * Idle state driver of data line
473  * 0: output
474  * 1: high-Z
475  */
476 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_MASK (0x8U)
477 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SHIFT (3U)
478 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_MASK)
479 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SHIFT)
480 
481 /*
482  * CK_IDLEZ (RW)
483  *
484  * Idle state driver of clock line
485  * 0: output
486  * 1: high-Z
487  */
488 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_MASK (0x4U)
489 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SHIFT (2U)
490 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_MASK)
491 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SHIFT)
492 
493 /*
494  * DA_IDLEV (RW)
495  *
496  * Idle state value of data line
497  * 0: data'0'
498  * 1: data'1'
499  */
500 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_MASK (0x2U)
501 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SHIFT (1U)
502 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_MASK)
503 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SHIFT)
504 
505 /*
506  * CK_IDLEV (RW)
507  *
508  * Idle state value of clock line
509  * 0: data'0'
510  * 1: data'1'
511  */
512 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_MASK (0x1U)
513 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SHIFT (0U)
514 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_MASK)
515 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SHIFT)
516 
517 /* Bitfield definition for register of struct array CTRL: BAUD_CFG */
518 /*
519  * SYNC_POINT (RW)
520  *
521  * Baud synchronous time, minmum bit time
522  */
523 #define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_MASK (0xFFFF0000UL)
524 #define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SHIFT (16U)
525 #define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SHIFT) & SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_MASK)
526 #define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_MASK) >> SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SHIFT)
527 
528 /*
529  * BAUD_DIV (RW)
530  *
531  * Baud rate, bit time in system clock cycle
532  */
533 #define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_MASK (0xFFFFU)
534 #define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SHIFT (0U)
535 #define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SHIFT) & SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_MASK)
536 #define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_MASK) >> SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SHIFT)
537 
538 /* Bitfield definition for register of struct array CTRL: DATA_CFG */
539 /*
540  * TXD_POINT (RW)
541  *
542  * data transmit point in system clcok cycle
543  */
544 #define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_MASK (0xFFFF0000UL)
545 #define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SHIFT (16U)
546 #define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SHIFT) & SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_MASK)
547 #define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_MASK) >> SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SHIFT)
548 
549 /*
550  * RXD_POINT (RW)
551  *
552  * data receive point in system clcok cycle
553  */
554 #define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_MASK (0xFFFFU)
555 #define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SHIFT (0U)
556 #define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SHIFT) & SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_MASK)
557 #define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_MASK) >> SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SHIFT)
558 
559 /* Bitfield definition for register of struct array CTRL: CLK_CFG */
560 /*
561  * CK1_POINT (RW)
562  *
563  * clock point 1 in system clcok cycle
564  */
565 #define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_MASK (0xFFFF0000UL)
566 #define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SHIFT (16U)
567 #define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SHIFT) & SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_MASK)
568 #define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_MASK) >> SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SHIFT)
569 
570 /*
571  * CK0_POINT (RW)
572  *
573  * clock point 0 in system clcok cycle
574  */
575 #define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_MASK (0xFFFFU)
576 #define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SHIFT (0U)
577 #define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SHIFT) & SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_MASK)
578 #define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_MASK) >> SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SHIFT)
579 
580 /* Bitfield definition for register of struct array CTRL: PIN */
581 /*
582  * OE_CK (RO)
583  *
584  * CK drive state
585  * 0: input
586  * 1: output
587  */
588 #define SEI_CTRL_XCVR_PIN_OE_CK_MASK (0x4000000UL)
589 #define SEI_CTRL_XCVR_PIN_OE_CK_SHIFT (26U)
590 #define SEI_CTRL_XCVR_PIN_OE_CK_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_CK_MASK) >> SEI_CTRL_XCVR_PIN_OE_CK_SHIFT)
591 
592 /*
593  * DI_CK (RO)
594  *
595  * CK state
596  * 0: data 0
597  * 1: data 1
598  */
599 #define SEI_CTRL_XCVR_PIN_DI_CK_MASK (0x2000000UL)
600 #define SEI_CTRL_XCVR_PIN_DI_CK_SHIFT (25U)
601 #define SEI_CTRL_XCVR_PIN_DI_CK_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_CK_MASK) >> SEI_CTRL_XCVR_PIN_DI_CK_SHIFT)
602 
603 /*
604  * DO_CK (RO)
605  *
606  * CK output
607  * 0: data 0
608  * 1: data 1
609  */
610 #define SEI_CTRL_XCVR_PIN_DO_CK_MASK (0x1000000UL)
611 #define SEI_CTRL_XCVR_PIN_DO_CK_SHIFT (24U)
612 #define SEI_CTRL_XCVR_PIN_DO_CK_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_CK_MASK) >> SEI_CTRL_XCVR_PIN_DO_CK_SHIFT)
613 
614 /*
615  * OE_RX (RO)
616  *
617  * RX drive state
618  * 0: input
619  * 1: output
620  */
621 #define SEI_CTRL_XCVR_PIN_OE_RX_MASK (0x40000UL)
622 #define SEI_CTRL_XCVR_PIN_OE_RX_SHIFT (18U)
623 #define SEI_CTRL_XCVR_PIN_OE_RX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_RX_MASK) >> SEI_CTRL_XCVR_PIN_OE_RX_SHIFT)
624 
625 /*
626  * DI_RX (RO)
627  *
628  * RX state
629  * 0: data 0
630  * 1: data 1
631  */
632 #define SEI_CTRL_XCVR_PIN_DI_RX_MASK (0x20000UL)
633 #define SEI_CTRL_XCVR_PIN_DI_RX_SHIFT (17U)
634 #define SEI_CTRL_XCVR_PIN_DI_RX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_RX_MASK) >> SEI_CTRL_XCVR_PIN_DI_RX_SHIFT)
635 
636 /*
637  * DO_RX (RO)
638  *
639  * RX output
640  * 0: data 0
641  * 1: data 1
642  */
643 #define SEI_CTRL_XCVR_PIN_DO_RX_MASK (0x10000UL)
644 #define SEI_CTRL_XCVR_PIN_DO_RX_SHIFT (16U)
645 #define SEI_CTRL_XCVR_PIN_DO_RX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_RX_MASK) >> SEI_CTRL_XCVR_PIN_DO_RX_SHIFT)
646 
647 /*
648  * OE_DE (RO)
649  *
650  * DE drive state
651  * 0: input
652  * 1: output
653  */
654 #define SEI_CTRL_XCVR_PIN_OE_DE_MASK (0x400U)
655 #define SEI_CTRL_XCVR_PIN_OE_DE_SHIFT (10U)
656 #define SEI_CTRL_XCVR_PIN_OE_DE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_DE_MASK) >> SEI_CTRL_XCVR_PIN_OE_DE_SHIFT)
657 
658 /*
659  * DI_DE (RO)
660  *
661  * DE state
662  * 0: data 0
663  * 1: data 1
664  */
665 #define SEI_CTRL_XCVR_PIN_DI_DE_MASK (0x200U)
666 #define SEI_CTRL_XCVR_PIN_DI_DE_SHIFT (9U)
667 #define SEI_CTRL_XCVR_PIN_DI_DE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_DE_MASK) >> SEI_CTRL_XCVR_PIN_DI_DE_SHIFT)
668 
669 /*
670  * DO_DE (RO)
671  *
672  * DE output
673  * 0: data 0
674  * 1: data 1
675  */
676 #define SEI_CTRL_XCVR_PIN_DO_DE_MASK (0x100U)
677 #define SEI_CTRL_XCVR_PIN_DO_DE_SHIFT (8U)
678 #define SEI_CTRL_XCVR_PIN_DO_DE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_DE_MASK) >> SEI_CTRL_XCVR_PIN_DO_DE_SHIFT)
679 
680 /*
681  * OE_TX (RO)
682  *
683  * TX drive state
684  * 0: input
685  * 1: output
686  */
687 #define SEI_CTRL_XCVR_PIN_OE_TX_MASK (0x4U)
688 #define SEI_CTRL_XCVR_PIN_OE_TX_SHIFT (2U)
689 #define SEI_CTRL_XCVR_PIN_OE_TX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_TX_MASK) >> SEI_CTRL_XCVR_PIN_OE_TX_SHIFT)
690 
691 /*
692  * DI_TX (RO)
693  *
694  * TX state
695  * 0: data 0
696  * 1: data 1
697  */
698 #define SEI_CTRL_XCVR_PIN_DI_TX_MASK (0x2U)
699 #define SEI_CTRL_XCVR_PIN_DI_TX_SHIFT (1U)
700 #define SEI_CTRL_XCVR_PIN_DI_TX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_TX_MASK) >> SEI_CTRL_XCVR_PIN_DI_TX_SHIFT)
701 
702 /*
703  * DO_TX (RO)
704  *
705  * TX output
706  * 0: data 0
707  * 1: data 1
708  */
709 #define SEI_CTRL_XCVR_PIN_DO_TX_MASK (0x1U)
710 #define SEI_CTRL_XCVR_PIN_DO_TX_SHIFT (0U)
711 #define SEI_CTRL_XCVR_PIN_DO_TX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_TX_MASK) >> SEI_CTRL_XCVR_PIN_DO_TX_SHIFT)
712 
713 /* Bitfield definition for register of struct array CTRL: STATE */
714 /*
715  * RECV_STATE (RO)
716  *
717  * FSM of asynchronous receive
718  */
719 #define SEI_CTRL_XCVR_STATE_RECV_STATE_MASK (0x7000000UL)
720 #define SEI_CTRL_XCVR_STATE_RECV_STATE_SHIFT (24U)
721 #define SEI_CTRL_XCVR_STATE_RECV_STATE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_STATE_RECV_STATE_MASK) >> SEI_CTRL_XCVR_STATE_RECV_STATE_SHIFT)
722 
723 /*
724  * SEND_STATE (RO)
725  *
726  * FSM of asynchronous transmit
727  */
728 #define SEI_CTRL_XCVR_STATE_SEND_STATE_MASK (0x70000UL)
729 #define SEI_CTRL_XCVR_STATE_SEND_STATE_SHIFT (16U)
730 #define SEI_CTRL_XCVR_STATE_SEND_STATE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_STATE_SEND_STATE_MASK) >> SEI_CTRL_XCVR_STATE_SEND_STATE_SHIFT)
731 
732 /*
733  * PAR_ERR (RO)
734  *
735  * Parity bit error
736  */
737 #define SEI_CTRL_XCVR_STATE_PAR_ERR_MASK (0x100U)
738 #define SEI_CTRL_XCVR_STATE_PAR_ERR_SHIFT (8U)
739 #define SEI_CTRL_XCVR_STATE_PAR_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_STATE_PAR_ERR_MASK) >> SEI_CTRL_XCVR_STATE_PAR_ERR_SHIFT)
740 
741 /* Bitfield definition for register of struct array CTRL: IN_CFG */
742 /*
743  * REWIND_EN (RW)
744  *
745  * enable rewind cmd register by LATCH
746  */
747 #define SEI_CTRL_TRG_IN_CFG_REWIND_EN_MASK (0x80000000UL)
748 #define SEI_CTRL_TRG_IN_CFG_REWIND_EN_SHIFT (31U)
749 #define SEI_CTRL_TRG_IN_CFG_REWIND_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_REWIND_EN_SHIFT) & SEI_CTRL_TRG_IN_CFG_REWIND_EN_MASK)
750 #define SEI_CTRL_TRG_IN_CFG_REWIND_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_REWIND_EN_MASK) >> SEI_CTRL_TRG_IN_CFG_REWIND_EN_SHIFT)
751 
752 /*
753  * REWIND_SEL (RW)
754  *
755  * select one LATCH to rewind CMD register
756  * 0:LATCH[0]
757  * 1:LATCH[1]
758  * 2:LATCH[2]
759  * 3:LATCH[3]
760  */
761 #define SEI_CTRL_TRG_IN_CFG_REWIND_SEL_MASK (0x3000000UL)
762 #define SEI_CTRL_TRG_IN_CFG_REWIND_SEL_SHIFT (24U)
763 #define SEI_CTRL_TRG_IN_CFG_REWIND_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_REWIND_SEL_SHIFT) & SEI_CTRL_TRG_IN_CFG_REWIND_SEL_MASK)
764 #define SEI_CTRL_TRG_IN_CFG_REWIND_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_REWIND_SEL_MASK) >> SEI_CTRL_TRG_IN_CFG_REWIND_SEL_SHIFT)
765 
766 /*
767  * PRD_EN (RW)
768  *
769  * Enable period trigger (tigger 2)
770  * 0: periodical trigger disabled
771  * 1: periodical trigger enabled
772  */
773 #define SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK (0x800000UL)
774 #define SEI_CTRL_TRG_IN_CFG_PRD_EN_SHIFT (23U)
775 #define SEI_CTRL_TRG_IN_CFG_PRD_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_PRD_EN_SHIFT) & SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK)
776 #define SEI_CTRL_TRG_IN_CFG_PRD_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK) >> SEI_CTRL_TRG_IN_CFG_PRD_EN_SHIFT)
777 
778 /*
779  * SYNC_SEL (RW)
780  *
781  * Synchronize sigal selection (tigger 2)
782  * 0: trigger in 0
783  * 1: trigger in 1
784  * ...
785  * 7: trigger in 7
786  */
787 #define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_MASK (0x70000UL)
788 #define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SHIFT (16U)
789 #define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SHIFT) & SEI_CTRL_TRG_IN_CFG_SYNC_SEL_MASK)
790 #define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_SYNC_SEL_MASK) >> SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SHIFT)
791 
792 /*
793  * IN1_EN (RW)
794  *
795  * Enable trigger 1
796  * 0: disable trigger 1
797  * 1: enable trigger 1
798  */
799 #define SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK (0x8000U)
800 #define SEI_CTRL_TRG_IN_CFG_IN1_EN_SHIFT (15U)
801 #define SEI_CTRL_TRG_IN_CFG_IN1_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN1_EN_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK)
802 #define SEI_CTRL_TRG_IN_CFG_IN1_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK) >> SEI_CTRL_TRG_IN_CFG_IN1_EN_SHIFT)
803 
804 /*
805  * IN1_SEL (RW)
806  *
807  * Trigger 1 sigal selection
808  * 0: trigger in 0
809  * 1: trigger in 1
810  * ...
811  * 7: trigger in 7
812  */
813 #define SEI_CTRL_TRG_IN_CFG_IN1_SEL_MASK (0x700U)
814 #define SEI_CTRL_TRG_IN_CFG_IN1_SEL_SHIFT (8U)
815 #define SEI_CTRL_TRG_IN_CFG_IN1_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN1_SEL_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN1_SEL_MASK)
816 #define SEI_CTRL_TRG_IN_CFG_IN1_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN1_SEL_MASK) >> SEI_CTRL_TRG_IN_CFG_IN1_SEL_SHIFT)
817 
818 /*
819  * IN0_EN (RW)
820  *
821  * Enable trigger 0
822  * 0: disable trigger 1
823  * 1: enable trigger 1
824  */
825 #define SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK (0x80U)
826 #define SEI_CTRL_TRG_IN_CFG_IN0_EN_SHIFT (7U)
827 #define SEI_CTRL_TRG_IN_CFG_IN0_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN0_EN_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK)
828 #define SEI_CTRL_TRG_IN_CFG_IN0_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK) >> SEI_CTRL_TRG_IN_CFG_IN0_EN_SHIFT)
829 
830 /*
831  * IN0_SEL (RW)
832  *
833  * Trigger 0 sigal selection
834  * 0: trigger in 0
835  * 1: trigger in 1
836  * ...
837  * 7: trigger in 7
838  */
839 #define SEI_CTRL_TRG_IN_CFG_IN0_SEL_MASK (0x7U)
840 #define SEI_CTRL_TRG_IN_CFG_IN0_SEL_SHIFT (0U)
841 #define SEI_CTRL_TRG_IN_CFG_IN0_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN0_SEL_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN0_SEL_MASK)
842 #define SEI_CTRL_TRG_IN_CFG_IN0_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN0_SEL_MASK) >> SEI_CTRL_TRG_IN_CFG_IN0_SEL_SHIFT)
843 
844 /* Bitfield definition for register of struct array CTRL: SW */
845 /*
846  * SOFT (WC)
847  *
848  * Software trigger (tigger 3). this bit is self-clear
849  * 0: trigger source disabled
850  * 1: trigger source enabled
851  */
852 #define SEI_CTRL_TRG_SW_SOFT_MASK (0x1U)
853 #define SEI_CTRL_TRG_SW_SOFT_SHIFT (0U)
854 #define SEI_CTRL_TRG_SW_SOFT_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_SW_SOFT_SHIFT) & SEI_CTRL_TRG_SW_SOFT_MASK)
855 #define SEI_CTRL_TRG_SW_SOFT_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_SW_SOFT_MASK) >> SEI_CTRL_TRG_SW_SOFT_SHIFT)
856 
857 /* Bitfield definition for register of struct array CTRL: PRD_CFG */
858 /*
859  * ARMING (RW)
860  *
861  * Wait for trigger synchronous before trigger
862  * 0: Trigger directly
863  * 1: Wait trigger source before period trigger
864  */
865 #define SEI_CTRL_TRG_PRD_CFG_ARMING_MASK (0x10000UL)
866 #define SEI_CTRL_TRG_PRD_CFG_ARMING_SHIFT (16U)
867 #define SEI_CTRL_TRG_PRD_CFG_ARMING_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_PRD_CFG_ARMING_SHIFT) & SEI_CTRL_TRG_PRD_CFG_ARMING_MASK)
868 #define SEI_CTRL_TRG_PRD_CFG_ARMING_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_CFG_ARMING_MASK) >> SEI_CTRL_TRG_PRD_CFG_ARMING_SHIFT)
869 
870 /*
871  * SYNC (RW)
872  *
873  * Synchronous
874  * 0: Not synchronous
875  * 1: Synchronous every trigger source
876  */
877 #define SEI_CTRL_TRG_PRD_CFG_SYNC_MASK (0x1U)
878 #define SEI_CTRL_TRG_PRD_CFG_SYNC_SHIFT (0U)
879 #define SEI_CTRL_TRG_PRD_CFG_SYNC_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_PRD_CFG_SYNC_SHIFT) & SEI_CTRL_TRG_PRD_CFG_SYNC_MASK)
880 #define SEI_CTRL_TRG_PRD_CFG_SYNC_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_CFG_SYNC_MASK) >> SEI_CTRL_TRG_PRD_CFG_SYNC_SHIFT)
881 
882 /* Bitfield definition for register of struct array CTRL: PRD */
883 /*
884  * PERIOD (RW)
885  *
886  * Trigger period
887  */
888 #define SEI_CTRL_TRG_PRD_PERIOD_MASK (0xFFFFFFFFUL)
889 #define SEI_CTRL_TRG_PRD_PERIOD_SHIFT (0U)
890 #define SEI_CTRL_TRG_PRD_PERIOD_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_PRD_PERIOD_SHIFT) & SEI_CTRL_TRG_PRD_PERIOD_MASK)
891 #define SEI_CTRL_TRG_PRD_PERIOD_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_PERIOD_MASK) >> SEI_CTRL_TRG_PRD_PERIOD_SHIFT)
892 
893 /* Bitfield definition for register of struct array CTRL: OUT_CFG */
894 /*
895  * OUT3_EN (RW)
896  *
897  * Enable trigger 3
898  * 0: disable trigger 3
899  * 1: enable trigger 3
900  */
901 #define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_MASK (0x80000000UL)
902 #define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SHIFT (31U)
903 #define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT3_EN_MASK)
904 #define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT3_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SHIFT)
905 
906 /*
907  * OUT3_SEL (RW)
908  *
909  * Trigger 3 sigal selection
910  * 0: trigger out 0
911  * 1: trigger out 1
912  * ...
913  * 7: trigger out 7
914  */
915 #define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_MASK (0x7000000UL)
916 #define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SHIFT (24U)
917 #define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_MASK)
918 #define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SHIFT)
919 
920 /*
921  * OUT2_EN (RW)
922  *
923  * Enable trigger 2
924  * 0: disable trigger 2
925  * 1: enable trigger 2
926  */
927 #define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_MASK (0x800000UL)
928 #define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SHIFT (23U)
929 #define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT2_EN_MASK)
930 #define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT2_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SHIFT)
931 
932 /*
933  * OUT2_SEL (RW)
934  *
935  * Trigger 2 sigal selection
936  * 0: trigger out 0
937  * 1: trigger out 1
938  * ...
939  * 7: trigger out 7
940  */
941 #define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_MASK (0x70000UL)
942 #define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SHIFT (16U)
943 #define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_MASK)
944 #define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SHIFT)
945 
946 /*
947  * OUT1_EN (RW)
948  *
949  * Enable trigger 1
950  * 0: disable trigger 1
951  * 1: enable trigger 1
952  */
953 #define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_MASK (0x8000U)
954 #define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SHIFT (15U)
955 #define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT1_EN_MASK)
956 #define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT1_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SHIFT)
957 
958 /*
959  * OUT1_SEL (RW)
960  *
961  * Trigger 1 sigal selection
962  * 0: trigger out 0
963  * 1: trigger out 1
964  * ...
965  * 7: trigger out 7
966  */
967 #define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_MASK (0x700U)
968 #define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SHIFT (8U)
969 #define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_MASK)
970 #define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SHIFT)
971 
972 /*
973  * OUT0_EN (RW)
974  *
975  * Enable trigger 0
976  * 0: disable trigger 1
977  * 1: enable trigger 1
978  */
979 #define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_MASK (0x80U)
980 #define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SHIFT (7U)
981 #define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT0_EN_MASK)
982 #define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT0_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SHIFT)
983 
984 /*
985  * OUT0_SEL (RW)
986  *
987  * Trigger 0 sigal selection
988  * 0: trigger out 0
989  * 1: trigger out 1
990  * ...
991  * 7: trigger out 7
992  */
993 #define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_MASK (0x7U)
994 #define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SHIFT (0U)
995 #define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_MASK)
996 #define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SHIFT)
997 
998 /* Bitfield definition for register of struct array CTRL: IN_DIV */
999 /*
1000  * IN1_DIV (RW)
1001  *
1002  * The divider of trigger in 1.
1003  * 0x0: disable divider
1004  * 0x1: divider by 2
1005  * 0x2: divider by 3
1006  * ...
1007  * 0xFF: divider by 256
1008  */
1009 #define SEI_CTRL_TRG_IN_DIV_IN1_DIV_MASK (0xFF00U)
1010 #define SEI_CTRL_TRG_IN_DIV_IN1_DIV_SHIFT (8U)
1011 #define SEI_CTRL_TRG_IN_DIV_IN1_DIV_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_DIV_IN1_DIV_SHIFT) & SEI_CTRL_TRG_IN_DIV_IN1_DIV_MASK)
1012 #define SEI_CTRL_TRG_IN_DIV_IN1_DIV_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_DIV_IN1_DIV_MASK) >> SEI_CTRL_TRG_IN_DIV_IN1_DIV_SHIFT)
1013 
1014 /*
1015  * IN0_DIV (RW)
1016  *
1017  * The divider of trigger in 0.
1018  * 0x0: disable divider
1019  * 0x1: divider by 2
1020  * 0x2: divider by 3
1021  * ...
1022  * 0xFF: divider by 256
1023  */
1024 #define SEI_CTRL_TRG_IN_DIV_IN0_DIV_MASK (0xFFU)
1025 #define SEI_CTRL_TRG_IN_DIV_IN0_DIV_SHIFT (0U)
1026 #define SEI_CTRL_TRG_IN_DIV_IN0_DIV_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_DIV_IN0_DIV_SHIFT) & SEI_CTRL_TRG_IN_DIV_IN0_DIV_MASK)
1027 #define SEI_CTRL_TRG_IN_DIV_IN0_DIV_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_DIV_IN0_DIV_MASK) >> SEI_CTRL_TRG_IN_DIV_IN0_DIV_SHIFT)
1028 
1029 /* Bitfield definition for register of struct array CTRL: PRD_STS */
1030 /*
1031  * TRIGERED (RO)
1032  *
1033  * Period has been triggered
1034  * 0: Not triggered
1035  * 1: Triggered
1036  */
1037 #define SEI_CTRL_TRG_PRD_STS_TRIGERED_MASK (0x100000UL)
1038 #define SEI_CTRL_TRG_PRD_STS_TRIGERED_SHIFT (20U)
1039 #define SEI_CTRL_TRG_PRD_STS_TRIGERED_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_STS_TRIGERED_MASK) >> SEI_CTRL_TRG_PRD_STS_TRIGERED_SHIFT)
1040 
1041 /*
1042  * ARMED (RO)
1043  *
1044  * Waiting for trigger
1045  * 0: Not in waiting status
1046  * 1: In waiting status
1047  */
1048 #define SEI_CTRL_TRG_PRD_STS_ARMED_MASK (0x10000UL)
1049 #define SEI_CTRL_TRG_PRD_STS_ARMED_SHIFT (16U)
1050 #define SEI_CTRL_TRG_PRD_STS_ARMED_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_STS_ARMED_MASK) >> SEI_CTRL_TRG_PRD_STS_ARMED_SHIFT)
1051 
1052 /* Bitfield definition for register of struct array CTRL: PRD_CNT */
1053 /*
1054  * PERIOD_CNT (RO)
1055  *
1056  * Trigger period counter
1057  */
1058 #define SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_MASK (0xFFFFFFFFUL)
1059 #define SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_SHIFT (0U)
1060 #define SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_MASK) >> SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_SHIFT)
1061 
1062 /* Bitfield definition for register of struct array CTRL: DIV_STS */
1063 /*
1064  * IN1_CNT (RO)
1065  *
1066  * The divider counter for trigger in 1, trigger valid when counter is 0.
1067  */
1068 #define SEI_CTRL_TRG_DIV_STS_IN1_CNT_MASK (0xFF00U)
1069 #define SEI_CTRL_TRG_DIV_STS_IN1_CNT_SHIFT (8U)
1070 #define SEI_CTRL_TRG_DIV_STS_IN1_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_DIV_STS_IN1_CNT_MASK) >> SEI_CTRL_TRG_DIV_STS_IN1_CNT_SHIFT)
1071 
1072 /*
1073  * IN0_CNT (RO)
1074  *
1075  * The divider counter for trigger in 0, trigger valid when counter is 0.
1076  */
1077 #define SEI_CTRL_TRG_DIV_STS_IN0_CNT_MASK (0xFFU)
1078 #define SEI_CTRL_TRG_DIV_STS_IN0_CNT_SHIFT (0U)
1079 #define SEI_CTRL_TRG_DIV_STS_IN0_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_DIV_STS_IN0_CNT_MASK) >> SEI_CTRL_TRG_DIV_STS_IN0_CNT_SHIFT)
1080 
1081 /* Bitfield definition for register of struct array CTRL: 0 */
1082 /*
1083  * CMD_TRIGGER0 (RW)
1084  *
1085  * Trigger command
1086  */
1087 #define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_MASK (0xFFFFFFFFUL)
1088 #define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SHIFT (0U)
1089 #define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SHIFT) & SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_MASK)
1090 #define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_MASK) >> SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SHIFT)
1091 
1092 /* Bitfield definition for register of struct array CTRL: 0 */
1093 /*
1094  * TRIGGER0_TIME (RO)
1095  *
1096  * Trigger time
1097  */
1098 #define SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_MASK (0xFFFFFFFFUL)
1099 #define SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_SHIFT (0U)
1100 #define SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_MASK) >> SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_SHIFT)
1101 
1102 /* Bitfield definition for register of struct array CTRL: MODE */
1103 /*
1104  * WLEN (RW)
1105  *
1106  * word length
1107  * 0: 1 bit
1108  * 1: 2 bit
1109  * ...
1110  * 31: 32 bit
1111  */
1112 #define SEI_CTRL_CMD_MODE_WLEN_MASK (0x1F0000UL)
1113 #define SEI_CTRL_CMD_MODE_WLEN_SHIFT (16U)
1114 #define SEI_CTRL_CMD_MODE_WLEN_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_WLEN_SHIFT) & SEI_CTRL_CMD_MODE_WLEN_MASK)
1115 #define SEI_CTRL_CMD_MODE_WLEN_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_WLEN_MASK) >> SEI_CTRL_CMD_MODE_WLEN_SHIFT)
1116 
1117 /*
1118  * WORDER (RW)
1119  *
1120  * word order
1121  * 0: sample as bit order
1122  * 1: different from bit order
1123  */
1124 #define SEI_CTRL_CMD_MODE_WORDER_MASK (0x800U)
1125 #define SEI_CTRL_CMD_MODE_WORDER_SHIFT (11U)
1126 #define SEI_CTRL_CMD_MODE_WORDER_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_WORDER_SHIFT) & SEI_CTRL_CMD_MODE_WORDER_MASK)
1127 #define SEI_CTRL_CMD_MODE_WORDER_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_WORDER_MASK) >> SEI_CTRL_CMD_MODE_WORDER_SHIFT)
1128 
1129 /*
1130  * BORDER (RW)
1131  *
1132  * bit order
1133  * 0: LSB first
1134  * 1: MSB first
1135  */
1136 #define SEI_CTRL_CMD_MODE_BORDER_MASK (0x400U)
1137 #define SEI_CTRL_CMD_MODE_BORDER_SHIFT (10U)
1138 #define SEI_CTRL_CMD_MODE_BORDER_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_BORDER_SHIFT) & SEI_CTRL_CMD_MODE_BORDER_MASK)
1139 #define SEI_CTRL_CMD_MODE_BORDER_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_BORDER_MASK) >> SEI_CTRL_CMD_MODE_BORDER_SHIFT)
1140 
1141 /*
1142  * SIGNED (RW)
1143  *
1144  * Signed
1145  * 0: unsigned value
1146  * 1: signed value
1147  */
1148 #define SEI_CTRL_CMD_MODE_SIGNED_MASK (0x200U)
1149 #define SEI_CTRL_CMD_MODE_SIGNED_SHIFT (9U)
1150 #define SEI_CTRL_CMD_MODE_SIGNED_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_SIGNED_SHIFT) & SEI_CTRL_CMD_MODE_SIGNED_MASK)
1151 #define SEI_CTRL_CMD_MODE_SIGNED_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_SIGNED_MASK) >> SEI_CTRL_CMD_MODE_SIGNED_SHIFT)
1152 
1153 /*
1154  * REWIND (WC)
1155  *
1156  * Write 1 to rewind read/write pointer, this is a self clear bit
1157  */
1158 #define SEI_CTRL_CMD_MODE_REWIND_MASK (0x100U)
1159 #define SEI_CTRL_CMD_MODE_REWIND_SHIFT (8U)
1160 #define SEI_CTRL_CMD_MODE_REWIND_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_REWIND_SHIFT) & SEI_CTRL_CMD_MODE_REWIND_MASK)
1161 #define SEI_CTRL_CMD_MODE_REWIND_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_REWIND_MASK) >> SEI_CTRL_CMD_MODE_REWIND_SHIFT)
1162 
1163 /*
1164  * MODE (RW)
1165  *
1166  * Data mode(CMD register only support data mode)
1167  * 0: data mode
1168  * 1: check mode
1169  * 2: CRC mode
1170  */
1171 #define SEI_CTRL_CMD_MODE_MODE_MASK (0x3U)
1172 #define SEI_CTRL_CMD_MODE_MODE_SHIFT (0U)
1173 #define SEI_CTRL_CMD_MODE_MODE_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_MODE_SHIFT) & SEI_CTRL_CMD_MODE_MODE_MASK)
1174 #define SEI_CTRL_CMD_MODE_MODE_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_MODE_MASK) >> SEI_CTRL_CMD_MODE_MODE_SHIFT)
1175 
1176 /* Bitfield definition for register of struct array CTRL: IDX */
1177 /*
1178  * LAST_BIT (RW)
1179  *
1180  * Last bit index for tranceive
1181  */
1182 #define SEI_CTRL_CMD_IDX_LAST_BIT_MASK (0x1F000000UL)
1183 #define SEI_CTRL_CMD_IDX_LAST_BIT_SHIFT (24U)
1184 #define SEI_CTRL_CMD_IDX_LAST_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_LAST_BIT_SHIFT) & SEI_CTRL_CMD_IDX_LAST_BIT_MASK)
1185 #define SEI_CTRL_CMD_IDX_LAST_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_LAST_BIT_MASK) >> SEI_CTRL_CMD_IDX_LAST_BIT_SHIFT)
1186 
1187 /*
1188  * FIRST_BIT (RW)
1189  *
1190  * First bit index for tranceive
1191  */
1192 #define SEI_CTRL_CMD_IDX_FIRST_BIT_MASK (0x1F0000UL)
1193 #define SEI_CTRL_CMD_IDX_FIRST_BIT_SHIFT (16U)
1194 #define SEI_CTRL_CMD_IDX_FIRST_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_FIRST_BIT_SHIFT) & SEI_CTRL_CMD_IDX_FIRST_BIT_MASK)
1195 #define SEI_CTRL_CMD_IDX_FIRST_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_FIRST_BIT_MASK) >> SEI_CTRL_CMD_IDX_FIRST_BIT_SHIFT)
1196 
1197 /*
1198  * MAX_BIT (RW)
1199  *
1200  * Highest bit index
1201  */
1202 #define SEI_CTRL_CMD_IDX_MAX_BIT_MASK (0x1F00U)
1203 #define SEI_CTRL_CMD_IDX_MAX_BIT_SHIFT (8U)
1204 #define SEI_CTRL_CMD_IDX_MAX_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_MAX_BIT_SHIFT) & SEI_CTRL_CMD_IDX_MAX_BIT_MASK)
1205 #define SEI_CTRL_CMD_IDX_MAX_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_MAX_BIT_MASK) >> SEI_CTRL_CMD_IDX_MAX_BIT_SHIFT)
1206 
1207 /*
1208  * MIN_BIT (RW)
1209  *
1210  * Lowest bit index
1211  */
1212 #define SEI_CTRL_CMD_IDX_MIN_BIT_MASK (0x1FU)
1213 #define SEI_CTRL_CMD_IDX_MIN_BIT_SHIFT (0U)
1214 #define SEI_CTRL_CMD_IDX_MIN_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_MIN_BIT_SHIFT) & SEI_CTRL_CMD_IDX_MIN_BIT_MASK)
1215 #define SEI_CTRL_CMD_IDX_MIN_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_MIN_BIT_MASK) >> SEI_CTRL_CMD_IDX_MIN_BIT_SHIFT)
1216 
1217 /* Bitfield definition for register of struct array CTRL: CMD */
1218 /*
1219  * DATA (RW)
1220  *
1221  * DATA
1222  */
1223 #define SEI_CTRL_CMD_CMD_DATA_MASK (0xFFFFFFFFUL)
1224 #define SEI_CTRL_CMD_CMD_DATA_SHIFT (0U)
1225 #define SEI_CTRL_CMD_CMD_DATA_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_CMD_DATA_SHIFT) & SEI_CTRL_CMD_CMD_DATA_MASK)
1226 #define SEI_CTRL_CMD_CMD_DATA_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_CMD_DATA_MASK) >> SEI_CTRL_CMD_CMD_DATA_SHIFT)
1227 
1228 /* Bitfield definition for register of struct array CTRL: SET */
1229 /*
1230  * DATA_SET (RW)
1231  *
1232  * DATA bit set
1233  */
1234 #define SEI_CTRL_CMD_SET_DATA_SET_MASK (0xFFFFFFFFUL)
1235 #define SEI_CTRL_CMD_SET_DATA_SET_SHIFT (0U)
1236 #define SEI_CTRL_CMD_SET_DATA_SET_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_SET_DATA_SET_SHIFT) & SEI_CTRL_CMD_SET_DATA_SET_MASK)
1237 #define SEI_CTRL_CMD_SET_DATA_SET_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_SET_DATA_SET_MASK) >> SEI_CTRL_CMD_SET_DATA_SET_SHIFT)
1238 
1239 /* Bitfield definition for register of struct array CTRL: CLR */
1240 /*
1241  * DATA_CLR (RW)
1242  *
1243  * DATA bit clear
1244  */
1245 #define SEI_CTRL_CMD_CLR_DATA_CLR_MASK (0xFFFFFFFFUL)
1246 #define SEI_CTRL_CMD_CLR_DATA_CLR_SHIFT (0U)
1247 #define SEI_CTRL_CMD_CLR_DATA_CLR_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_CLR_DATA_CLR_SHIFT) & SEI_CTRL_CMD_CLR_DATA_CLR_MASK)
1248 #define SEI_CTRL_CMD_CLR_DATA_CLR_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_CLR_DATA_CLR_MASK) >> SEI_CTRL_CMD_CLR_DATA_CLR_SHIFT)
1249 
1250 /* Bitfield definition for register of struct array CTRL: INV */
1251 /*
1252  * DATA_TGL (RW)
1253  *
1254  * DATA bit toggle
1255  */
1256 #define SEI_CTRL_CMD_INV_DATA_TGL_MASK (0xFFFFFFFFUL)
1257 #define SEI_CTRL_CMD_INV_DATA_TGL_SHIFT (0U)
1258 #define SEI_CTRL_CMD_INV_DATA_TGL_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_INV_DATA_TGL_SHIFT) & SEI_CTRL_CMD_INV_DATA_TGL_MASK)
1259 #define SEI_CTRL_CMD_INV_DATA_TGL_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_INV_DATA_TGL_MASK) >> SEI_CTRL_CMD_INV_DATA_TGL_SHIFT)
1260 
1261 /* Bitfield definition for register of struct array CTRL: IN */
1262 /*
1263  * DATA_IN (RO)
1264  *
1265  * Commad input
1266  */
1267 #define SEI_CTRL_CMD_IN_DATA_IN_MASK (0xFFFFFFFFUL)
1268 #define SEI_CTRL_CMD_IN_DATA_IN_SHIFT (0U)
1269 #define SEI_CTRL_CMD_IN_DATA_IN_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IN_DATA_IN_MASK) >> SEI_CTRL_CMD_IN_DATA_IN_SHIFT)
1270 
1271 /* Bitfield definition for register of struct array CTRL: OUT */
1272 /*
1273  * DATA_OUT (RO)
1274  *
1275  * Command output
1276  */
1277 #define SEI_CTRL_CMD_OUT_DATA_OUT_MASK (0xFFFFFFFFUL)
1278 #define SEI_CTRL_CMD_OUT_DATA_OUT_SHIFT (0U)
1279 #define SEI_CTRL_CMD_OUT_DATA_OUT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_OUT_DATA_OUT_MASK) >> SEI_CTRL_CMD_OUT_DATA_OUT_SHIFT)
1280 
1281 /* Bitfield definition for register of struct array CTRL: STS */
1282 /*
1283  * WORD_IDX (RO)
1284  *
1285  * Word index
1286  */
1287 #define SEI_CTRL_CMD_STS_WORD_IDX_MASK (0x1F0000UL)
1288 #define SEI_CTRL_CMD_STS_WORD_IDX_SHIFT (16U)
1289 #define SEI_CTRL_CMD_STS_WORD_IDX_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_STS_WORD_IDX_MASK) >> SEI_CTRL_CMD_STS_WORD_IDX_SHIFT)
1290 
1291 /*
1292  * WORD_CNT (RO)
1293  *
1294  * Word counter
1295  */
1296 #define SEI_CTRL_CMD_STS_WORD_CNT_MASK (0x1F00U)
1297 #define SEI_CTRL_CMD_STS_WORD_CNT_SHIFT (8U)
1298 #define SEI_CTRL_CMD_STS_WORD_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_STS_WORD_CNT_MASK) >> SEI_CTRL_CMD_STS_WORD_CNT_SHIFT)
1299 
1300 /*
1301  * BIT_IDX (RO)
1302  *
1303  * Bit index
1304  */
1305 #define SEI_CTRL_CMD_STS_BIT_IDX_MASK (0x1FU)
1306 #define SEI_CTRL_CMD_STS_BIT_IDX_SHIFT (0U)
1307 #define SEI_CTRL_CMD_STS_BIT_IDX_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_STS_BIT_IDX_MASK) >> SEI_CTRL_CMD_STS_BIT_IDX_SHIFT)
1308 
1309 /* Bitfield definition for register of struct array CTRL: MIN */
1310 /*
1311  * CMD_MIN (RW)
1312  *
1313  * minimum command value
1314  */
1315 #define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_MASK (0xFFFFFFFFUL)
1316 #define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SHIFT (0U)
1317 #define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SHIFT) & SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_MASK)
1318 #define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_MASK) >> SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SHIFT)
1319 
1320 /* Bitfield definition for register of struct array CTRL: MAX */
1321 /*
1322  * CMD_MAX (RW)
1323  *
1324  * maximum command value
1325  */
1326 #define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_MASK (0xFFFFFFFFUL)
1327 #define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SHIFT (0U)
1328 #define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SHIFT) & SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_MASK)
1329 #define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_MASK) >> SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SHIFT)
1330 
1331 /* Bitfield definition for register of struct array CTRL: MSK */
1332 /*
1333  * CMD_MASK (RW)
1334  *
1335  * compare mask
1336  */
1337 #define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_MASK (0xFFFFFFFFUL)
1338 #define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SHIFT (0U)
1339 #define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SHIFT) & SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_MASK)
1340 #define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_MASK) >> SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SHIFT)
1341 
1342 /* Bitfield definition for register of struct array CTRL: PTA */
1343 /*
1344  * PTR3 (RW)
1345  *
1346  * pointer3
1347  */
1348 #define SEI_CTRL_CMD_TABLE_PTA_PTR3_MASK (0xFF000000UL)
1349 #define SEI_CTRL_CMD_TABLE_PTA_PTR3_SHIFT (24U)
1350 #define SEI_CTRL_CMD_TABLE_PTA_PTR3_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR3_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR3_MASK)
1351 #define SEI_CTRL_CMD_TABLE_PTA_PTR3_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR3_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR3_SHIFT)
1352 
1353 /*
1354  * PTR2 (RW)
1355  *
1356  * pointer2
1357  */
1358 #define SEI_CTRL_CMD_TABLE_PTA_PTR2_MASK (0xFF0000UL)
1359 #define SEI_CTRL_CMD_TABLE_PTA_PTR2_SHIFT (16U)
1360 #define SEI_CTRL_CMD_TABLE_PTA_PTR2_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR2_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR2_MASK)
1361 #define SEI_CTRL_CMD_TABLE_PTA_PTR2_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR2_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR2_SHIFT)
1362 
1363 /*
1364  * PTR1 (RW)
1365  *
1366  * pointer1
1367  */
1368 #define SEI_CTRL_CMD_TABLE_PTA_PTR1_MASK (0xFF00U)
1369 #define SEI_CTRL_CMD_TABLE_PTA_PTR1_SHIFT (8U)
1370 #define SEI_CTRL_CMD_TABLE_PTA_PTR1_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR1_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR1_MASK)
1371 #define SEI_CTRL_CMD_TABLE_PTA_PTR1_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR1_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR1_SHIFT)
1372 
1373 /*
1374  * PTR0 (RW)
1375  *
1376  * pointer0
1377  */
1378 #define SEI_CTRL_CMD_TABLE_PTA_PTR0_MASK (0xFFU)
1379 #define SEI_CTRL_CMD_TABLE_PTA_PTR0_SHIFT (0U)
1380 #define SEI_CTRL_CMD_TABLE_PTA_PTR0_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR0_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR0_MASK)
1381 #define SEI_CTRL_CMD_TABLE_PTA_PTR0_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR0_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR0_SHIFT)
1382 
1383 /* Bitfield definition for register of struct array CTRL: PTB */
1384 /*
1385  * PTR7 (RW)
1386  *
1387  * pointer7
1388  */
1389 #define SEI_CTRL_CMD_TABLE_PTB_PTR7_MASK (0xFF000000UL)
1390 #define SEI_CTRL_CMD_TABLE_PTB_PTR7_SHIFT (24U)
1391 #define SEI_CTRL_CMD_TABLE_PTB_PTR7_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR7_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR7_MASK)
1392 #define SEI_CTRL_CMD_TABLE_PTB_PTR7_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR7_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR7_SHIFT)
1393 
1394 /*
1395  * PTR6 (RW)
1396  *
1397  * pointer6
1398  */
1399 #define SEI_CTRL_CMD_TABLE_PTB_PTR6_MASK (0xFF0000UL)
1400 #define SEI_CTRL_CMD_TABLE_PTB_PTR6_SHIFT (16U)
1401 #define SEI_CTRL_CMD_TABLE_PTB_PTR6_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR6_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR6_MASK)
1402 #define SEI_CTRL_CMD_TABLE_PTB_PTR6_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR6_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR6_SHIFT)
1403 
1404 /*
1405  * PTR5 (RW)
1406  *
1407  * pointer5
1408  */
1409 #define SEI_CTRL_CMD_TABLE_PTB_PTR5_MASK (0xFF00U)
1410 #define SEI_CTRL_CMD_TABLE_PTB_PTR5_SHIFT (8U)
1411 #define SEI_CTRL_CMD_TABLE_PTB_PTR5_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR5_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR5_MASK)
1412 #define SEI_CTRL_CMD_TABLE_PTB_PTR5_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR5_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR5_SHIFT)
1413 
1414 /*
1415  * PTR4 (RW)
1416  *
1417  * pointer4
1418  */
1419 #define SEI_CTRL_CMD_TABLE_PTB_PTR4_MASK (0xFFU)
1420 #define SEI_CTRL_CMD_TABLE_PTB_PTR4_SHIFT (0U)
1421 #define SEI_CTRL_CMD_TABLE_PTB_PTR4_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR4_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR4_MASK)
1422 #define SEI_CTRL_CMD_TABLE_PTB_PTR4_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR4_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR4_SHIFT)
1423 
1424 /* Bitfield definition for register of struct array CTRL: 0_1 */
1425 /*
1426  * POINTER (RW)
1427  *
1428  * pointer
1429  */
1430 #define SEI_CTRL_LATCH_TRAN_POINTER_MASK (0xFF000000UL)
1431 #define SEI_CTRL_LATCH_TRAN_POINTER_SHIFT (24U)
1432 #define SEI_CTRL_LATCH_TRAN_POINTER_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_POINTER_SHIFT) & SEI_CTRL_LATCH_TRAN_POINTER_MASK)
1433 #define SEI_CTRL_LATCH_TRAN_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_POINTER_MASK) >> SEI_CTRL_LATCH_TRAN_POINTER_SHIFT)
1434 
1435 /*
1436  * CFG_TM (RW)
1437  *
1438  * timeout
1439  * 0: high
1440  * 1: low
1441  * 2: rise
1442  * 3: fall
1443  */
1444 #define SEI_CTRL_LATCH_TRAN_CFG_TM_MASK (0x30000UL)
1445 #define SEI_CTRL_LATCH_TRAN_CFG_TM_SHIFT (16U)
1446 #define SEI_CTRL_LATCH_TRAN_CFG_TM_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_TM_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_TM_MASK)
1447 #define SEI_CTRL_LATCH_TRAN_CFG_TM_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_TM_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_TM_SHIFT)
1448 
1449 /*
1450  * CFG_RXD (RW)
1451  *
1452  * data received
1453  * 0: high
1454  * 1: low
1455  * 2: rise
1456  * 3: fall
1457  */
1458 #define SEI_CTRL_LATCH_TRAN_CFG_RXD_MASK (0xC000U)
1459 #define SEI_CTRL_LATCH_TRAN_CFG_RXD_SHIFT (14U)
1460 #define SEI_CTRL_LATCH_TRAN_CFG_RXD_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_RXD_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_RXD_MASK)
1461 #define SEI_CTRL_LATCH_TRAN_CFG_RXD_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_RXD_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_RXD_SHIFT)
1462 
1463 /*
1464  * CFG_TXD (RW)
1465  *
1466  * data send
1467  * 0: high
1468  * 1: low
1469  * 2: rise
1470  * 3: fall
1471  */
1472 #define SEI_CTRL_LATCH_TRAN_CFG_TXD_MASK (0x3000U)
1473 #define SEI_CTRL_LATCH_TRAN_CFG_TXD_SHIFT (12U)
1474 #define SEI_CTRL_LATCH_TRAN_CFG_TXD_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_TXD_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_TXD_MASK)
1475 #define SEI_CTRL_LATCH_TRAN_CFG_TXD_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_TXD_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_TXD_SHIFT)
1476 
1477 /*
1478  * CFG_CLK (RW)
1479  *
1480  * clock
1481  * 0: high
1482  * 1: low
1483  * 2: rise
1484  * 3: fall
1485  */
1486 #define SEI_CTRL_LATCH_TRAN_CFG_CLK_MASK (0xC00U)
1487 #define SEI_CTRL_LATCH_TRAN_CFG_CLK_SHIFT (10U)
1488 #define SEI_CTRL_LATCH_TRAN_CFG_CLK_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_CLK_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_CLK_MASK)
1489 #define SEI_CTRL_LATCH_TRAN_CFG_CLK_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_CLK_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_CLK_SHIFT)
1490 
1491 /*
1492  * CFG_PTR (RW)
1493  *
1494  * pointer
1495  * 0: match
1496  * 1: not match
1497  * 2:entry
1498  * 3:leave
1499  */
1500 #define SEI_CTRL_LATCH_TRAN_CFG_PTR_MASK (0x300U)
1501 #define SEI_CTRL_LATCH_TRAN_CFG_PTR_SHIFT (8U)
1502 #define SEI_CTRL_LATCH_TRAN_CFG_PTR_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_PTR_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_PTR_MASK)
1503 #define SEI_CTRL_LATCH_TRAN_CFG_PTR_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_PTR_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_PTR_SHIFT)
1504 
1505 /*
1506  * OV_TM (RW)
1507  *
1508  * override timeout check
1509  */
1510 #define SEI_CTRL_LATCH_TRAN_OV_TM_MASK (0x10U)
1511 #define SEI_CTRL_LATCH_TRAN_OV_TM_SHIFT (4U)
1512 #define SEI_CTRL_LATCH_TRAN_OV_TM_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_TM_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_TM_MASK)
1513 #define SEI_CTRL_LATCH_TRAN_OV_TM_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_TM_MASK) >> SEI_CTRL_LATCH_TRAN_OV_TM_SHIFT)
1514 
1515 /*
1516  * OV_RXD (RW)
1517  *
1518  * override RX data check
1519  */
1520 #define SEI_CTRL_LATCH_TRAN_OV_RXD_MASK (0x8U)
1521 #define SEI_CTRL_LATCH_TRAN_OV_RXD_SHIFT (3U)
1522 #define SEI_CTRL_LATCH_TRAN_OV_RXD_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_RXD_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_RXD_MASK)
1523 #define SEI_CTRL_LATCH_TRAN_OV_RXD_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_RXD_MASK) >> SEI_CTRL_LATCH_TRAN_OV_RXD_SHIFT)
1524 
1525 /*
1526  * OV_TXD (RW)
1527  *
1528  * override TX data check
1529  */
1530 #define SEI_CTRL_LATCH_TRAN_OV_TXD_MASK (0x4U)
1531 #define SEI_CTRL_LATCH_TRAN_OV_TXD_SHIFT (2U)
1532 #define SEI_CTRL_LATCH_TRAN_OV_TXD_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_TXD_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_TXD_MASK)
1533 #define SEI_CTRL_LATCH_TRAN_OV_TXD_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_TXD_MASK) >> SEI_CTRL_LATCH_TRAN_OV_TXD_SHIFT)
1534 
1535 /*
1536  * OV_CLK (RW)
1537  *
1538  * override clock check
1539  */
1540 #define SEI_CTRL_LATCH_TRAN_OV_CLK_MASK (0x2U)
1541 #define SEI_CTRL_LATCH_TRAN_OV_CLK_SHIFT (1U)
1542 #define SEI_CTRL_LATCH_TRAN_OV_CLK_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_CLK_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_CLK_MASK)
1543 #define SEI_CTRL_LATCH_TRAN_OV_CLK_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_CLK_MASK) >> SEI_CTRL_LATCH_TRAN_OV_CLK_SHIFT)
1544 
1545 /*
1546  * OV_PTR (RW)
1547  *
1548  * override pointer check
1549  */
1550 #define SEI_CTRL_LATCH_TRAN_OV_PTR_MASK (0x1U)
1551 #define SEI_CTRL_LATCH_TRAN_OV_PTR_SHIFT (0U)
1552 #define SEI_CTRL_LATCH_TRAN_OV_PTR_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_PTR_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_PTR_MASK)
1553 #define SEI_CTRL_LATCH_TRAN_OV_PTR_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_PTR_MASK) >> SEI_CTRL_LATCH_TRAN_OV_PTR_SHIFT)
1554 
1555 /* Bitfield definition for register of struct array CTRL: CFG */
1556 /*
1557  * EN (RW)
1558  *
1559  * Enable latch
1560  * 0: disable
1561  * 1: enable
1562  */
1563 #define SEI_CTRL_LATCH_CFG_EN_MASK (0x80000000UL)
1564 #define SEI_CTRL_LATCH_CFG_EN_SHIFT (31U)
1565 #define SEI_CTRL_LATCH_CFG_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_CFG_EN_SHIFT) & SEI_CTRL_LATCH_CFG_EN_MASK)
1566 #define SEI_CTRL_LATCH_CFG_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_CFG_EN_MASK) >> SEI_CTRL_LATCH_CFG_EN_SHIFT)
1567 
1568 /*
1569  * SELECT (RW)
1570  *
1571  * Output select
1572  * 0: state0-state1
1573  * 1: state1-state2
1574  * 2: state2-state3
1575  * 3: state3-state0
1576  */
1577 #define SEI_CTRL_LATCH_CFG_SELECT_MASK (0x7000000UL)
1578 #define SEI_CTRL_LATCH_CFG_SELECT_SHIFT (24U)
1579 #define SEI_CTRL_LATCH_CFG_SELECT_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_CFG_SELECT_SHIFT) & SEI_CTRL_LATCH_CFG_SELECT_MASK)
1580 #define SEI_CTRL_LATCH_CFG_SELECT_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_CFG_SELECT_MASK) >> SEI_CTRL_LATCH_CFG_SELECT_SHIFT)
1581 
1582 /*
1583  * DELAY (RW)
1584  *
1585  * Delay in system clock cycle, for state transition
1586  */
1587 #define SEI_CTRL_LATCH_CFG_DELAY_MASK (0xFFFFU)
1588 #define SEI_CTRL_LATCH_CFG_DELAY_SHIFT (0U)
1589 #define SEI_CTRL_LATCH_CFG_DELAY_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_CFG_DELAY_SHIFT) & SEI_CTRL_LATCH_CFG_DELAY_MASK)
1590 #define SEI_CTRL_LATCH_CFG_DELAY_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_CFG_DELAY_MASK) >> SEI_CTRL_LATCH_CFG_DELAY_SHIFT)
1591 
1592 /* Bitfield definition for register of struct array CTRL: TIME */
1593 /*
1594  * LAT_TIME (RO)
1595  *
1596  * Latch time
1597  */
1598 #define SEI_CTRL_LATCH_TIME_LAT_TIME_MASK (0xFFFFFFFFUL)
1599 #define SEI_CTRL_LATCH_TIME_LAT_TIME_SHIFT (0U)
1600 #define SEI_CTRL_LATCH_TIME_LAT_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TIME_LAT_TIME_MASK) >> SEI_CTRL_LATCH_TIME_LAT_TIME_SHIFT)
1601 
1602 /* Bitfield definition for register of struct array CTRL: STS */
1603 /*
1604  * STATE (RO)
1605  *
1606  * State
1607  */
1608 #define SEI_CTRL_LATCH_STS_STATE_MASK (0x7000000UL)
1609 #define SEI_CTRL_LATCH_STS_STATE_SHIFT (24U)
1610 #define SEI_CTRL_LATCH_STS_STATE_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_STS_STATE_MASK) >> SEI_CTRL_LATCH_STS_STATE_SHIFT)
1611 
1612 /*
1613  * LAT_CNT (RO)
1614  *
1615  * Latch counter
1616  */
1617 #define SEI_CTRL_LATCH_STS_LAT_CNT_MASK (0xFFFFU)
1618 #define SEI_CTRL_LATCH_STS_LAT_CNT_SHIFT (0U)
1619 #define SEI_CTRL_LATCH_STS_LAT_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_STS_LAT_CNT_MASK) >> SEI_CTRL_LATCH_STS_LAT_CNT_SHIFT)
1620 
1621 /* Bitfield definition for register of struct array CTRL: SMP_EN */
1622 /*
1623  * ACC_EN (RW)
1624  *
1625  * Position include acceleration
1626  * 0: use acceleration from sample override acceleration register
1627  * 1: use acceleration from motor group
1628  */
1629 #define SEI_CTRL_POS_SMP_EN_ACC_EN_MASK (0x80000000UL)
1630 #define SEI_CTRL_POS_SMP_EN_ACC_EN_SHIFT (31U)
1631 #define SEI_CTRL_POS_SMP_EN_ACC_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_ACC_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_ACC_EN_MASK)
1632 #define SEI_CTRL_POS_SMP_EN_ACC_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_ACC_EN_MASK) >> SEI_CTRL_POS_SMP_EN_ACC_EN_SHIFT)
1633 
1634 /*
1635  * ACC_SEL (RW)
1636  *
1637  * Data register for acceleration transfer
1638  */
1639 #define SEI_CTRL_POS_SMP_EN_ACC_SEL_MASK (0x1F000000UL)
1640 #define SEI_CTRL_POS_SMP_EN_ACC_SEL_SHIFT (24U)
1641 #define SEI_CTRL_POS_SMP_EN_ACC_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_ACC_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_ACC_SEL_MASK)
1642 #define SEI_CTRL_POS_SMP_EN_ACC_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_ACC_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_ACC_SEL_SHIFT)
1643 
1644 /*
1645  * SPD_EN (RW)
1646  *
1647  * Position include speed
1648  * 0: use speed from sample override speed register
1649  * 1: use speed from motor group
1650  */
1651 #define SEI_CTRL_POS_SMP_EN_SPD_EN_MASK (0x800000UL)
1652 #define SEI_CTRL_POS_SMP_EN_SPD_EN_SHIFT (23U)
1653 #define SEI_CTRL_POS_SMP_EN_SPD_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_SPD_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_SPD_EN_MASK)
1654 #define SEI_CTRL_POS_SMP_EN_SPD_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_SPD_EN_MASK) >> SEI_CTRL_POS_SMP_EN_SPD_EN_SHIFT)
1655 
1656 /*
1657  * SPD_SEL (RW)
1658  *
1659  * Data register for speed transfer
1660  */
1661 #define SEI_CTRL_POS_SMP_EN_SPD_SEL_MASK (0x1F0000UL)
1662 #define SEI_CTRL_POS_SMP_EN_SPD_SEL_SHIFT (16U)
1663 #define SEI_CTRL_POS_SMP_EN_SPD_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_SPD_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_SPD_SEL_MASK)
1664 #define SEI_CTRL_POS_SMP_EN_SPD_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_SPD_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_SPD_SEL_SHIFT)
1665 
1666 /*
1667  * REV_EN (RW)
1668  *
1669  * Position include revolution
1670  * 0: use revolution from sample override revolution register
1671  * 1: use revolution from motor group
1672  */
1673 #define SEI_CTRL_POS_SMP_EN_REV_EN_MASK (0x8000U)
1674 #define SEI_CTRL_POS_SMP_EN_REV_EN_SHIFT (15U)
1675 #define SEI_CTRL_POS_SMP_EN_REV_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_REV_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_REV_EN_MASK)
1676 #define SEI_CTRL_POS_SMP_EN_REV_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_REV_EN_MASK) >> SEI_CTRL_POS_SMP_EN_REV_EN_SHIFT)
1677 
1678 /*
1679  * REV_SEL (RW)
1680  *
1681  * Data register for revolution transfer
1682  */
1683 #define SEI_CTRL_POS_SMP_EN_REV_SEL_MASK (0x1F00U)
1684 #define SEI_CTRL_POS_SMP_EN_REV_SEL_SHIFT (8U)
1685 #define SEI_CTRL_POS_SMP_EN_REV_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_REV_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_REV_SEL_MASK)
1686 #define SEI_CTRL_POS_SMP_EN_REV_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_REV_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_REV_SEL_SHIFT)
1687 
1688 /*
1689  * POS_EN (RW)
1690  *
1691  * Position include position
1692  * 0: use position from sample override position register
1693  * 1: use position from motor group
1694  */
1695 #define SEI_CTRL_POS_SMP_EN_POS_EN_MASK (0x80U)
1696 #define SEI_CTRL_POS_SMP_EN_POS_EN_SHIFT (7U)
1697 #define SEI_CTRL_POS_SMP_EN_POS_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_POS_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_POS_EN_MASK)
1698 #define SEI_CTRL_POS_SMP_EN_POS_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_POS_EN_MASK) >> SEI_CTRL_POS_SMP_EN_POS_EN_SHIFT)
1699 
1700 /*
1701  * POS_SEL (RW)
1702  *
1703  * Data register for position transfer
1704  */
1705 #define SEI_CTRL_POS_SMP_EN_POS_SEL_MASK (0x1FU)
1706 #define SEI_CTRL_POS_SMP_EN_POS_SEL_SHIFT (0U)
1707 #define SEI_CTRL_POS_SMP_EN_POS_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_POS_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_POS_SEL_MASK)
1708 #define SEI_CTRL_POS_SMP_EN_POS_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_POS_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_POS_SEL_SHIFT)
1709 
1710 /* Bitfield definition for register of struct array CTRL: SMP_CFG */
1711 /*
1712  * ONCE (RW)
1713  *
1714  * Sample one time
1715  * 0: Sample during windows time
1716  * 1: Close sample window after first sample
1717  */
1718 #define SEI_CTRL_POS_SMP_CFG_ONCE_MASK (0x1000000UL)
1719 #define SEI_CTRL_POS_SMP_CFG_ONCE_SHIFT (24U)
1720 #define SEI_CTRL_POS_SMP_CFG_ONCE_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_CFG_ONCE_SHIFT) & SEI_CTRL_POS_SMP_CFG_ONCE_MASK)
1721 #define SEI_CTRL_POS_SMP_CFG_ONCE_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_CFG_ONCE_MASK) >> SEI_CTRL_POS_SMP_CFG_ONCE_SHIFT)
1722 
1723 /*
1724  * LAT_SEL (RW)
1725  *
1726  * Latch selection
1727  * 0: latch 0
1728  * 1: latch 1
1729  * 2: latch 2
1730  * 3: latch 3
1731  */
1732 #define SEI_CTRL_POS_SMP_CFG_LAT_SEL_MASK (0x30000UL)
1733 #define SEI_CTRL_POS_SMP_CFG_LAT_SEL_SHIFT (16U)
1734 #define SEI_CTRL_POS_SMP_CFG_LAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_CFG_LAT_SEL_SHIFT) & SEI_CTRL_POS_SMP_CFG_LAT_SEL_MASK)
1735 #define SEI_CTRL_POS_SMP_CFG_LAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_CFG_LAT_SEL_MASK) >> SEI_CTRL_POS_SMP_CFG_LAT_SEL_SHIFT)
1736 
1737 /*
1738  * WINDOW (RW)
1739  *
1740  * Sample window, in clock cycle
1741  */
1742 #define SEI_CTRL_POS_SMP_CFG_WINDOW_MASK (0xFFFFU)
1743 #define SEI_CTRL_POS_SMP_CFG_WINDOW_SHIFT (0U)
1744 #define SEI_CTRL_POS_SMP_CFG_WINDOW_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_CFG_WINDOW_SHIFT) & SEI_CTRL_POS_SMP_CFG_WINDOW_MASK)
1745 #define SEI_CTRL_POS_SMP_CFG_WINDOW_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_CFG_WINDOW_MASK) >> SEI_CTRL_POS_SMP_CFG_WINDOW_SHIFT)
1746 
1747 /* Bitfield definition for register of struct array CTRL: SMP_DAT */
1748 /*
1749  * DAT_SEL (RW)
1750  *
1751  * Data register sampled, each bit represent a data register, select the DATA registers need to be updated when SAMPLE happens.
1752  * Note: CRC register will be cleared automatically by SAMPLE if select the DATA register used for CRC.
1753  */
1754 #define SEI_CTRL_POS_SMP_DAT_DAT_SEL_MASK (0xFFFFFFFFUL)
1755 #define SEI_CTRL_POS_SMP_DAT_DAT_SEL_SHIFT (0U)
1756 #define SEI_CTRL_POS_SMP_DAT_DAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_DAT_DAT_SEL_SHIFT) & SEI_CTRL_POS_SMP_DAT_DAT_SEL_MASK)
1757 #define SEI_CTRL_POS_SMP_DAT_DAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_DAT_DAT_SEL_MASK) >> SEI_CTRL_POS_SMP_DAT_DAT_SEL_SHIFT)
1758 
1759 /* Bitfield definition for register of struct array CTRL: SMP_POS */
1760 /*
1761  * POS (RW)
1762  *
1763  * Sample override position
1764  */
1765 #define SEI_CTRL_POS_SMP_POS_POS_MASK (0xFFFFFFFFUL)
1766 #define SEI_CTRL_POS_SMP_POS_POS_SHIFT (0U)
1767 #define SEI_CTRL_POS_SMP_POS_POS_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_POS_POS_SHIFT) & SEI_CTRL_POS_SMP_POS_POS_MASK)
1768 #define SEI_CTRL_POS_SMP_POS_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_POS_POS_MASK) >> SEI_CTRL_POS_SMP_POS_POS_SHIFT)
1769 
1770 /* Bitfield definition for register of struct array CTRL: SMP_REV */
1771 /*
1772  * REV (RW)
1773  *
1774  * Sample override revolution
1775  */
1776 #define SEI_CTRL_POS_SMP_REV_REV_MASK (0xFFFFFFFFUL)
1777 #define SEI_CTRL_POS_SMP_REV_REV_SHIFT (0U)
1778 #define SEI_CTRL_POS_SMP_REV_REV_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_REV_REV_SHIFT) & SEI_CTRL_POS_SMP_REV_REV_MASK)
1779 #define SEI_CTRL_POS_SMP_REV_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_REV_REV_MASK) >> SEI_CTRL_POS_SMP_REV_REV_SHIFT)
1780 
1781 /* Bitfield definition for register of struct array CTRL: SMP_SPD */
1782 /*
1783  * SPD (RW)
1784  *
1785  * Sample override speed
1786  */
1787 #define SEI_CTRL_POS_SMP_SPD_SPD_MASK (0xFFFFFFFFUL)
1788 #define SEI_CTRL_POS_SMP_SPD_SPD_SHIFT (0U)
1789 #define SEI_CTRL_POS_SMP_SPD_SPD_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_SPD_SPD_SHIFT) & SEI_CTRL_POS_SMP_SPD_SPD_MASK)
1790 #define SEI_CTRL_POS_SMP_SPD_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_SPD_SPD_MASK) >> SEI_CTRL_POS_SMP_SPD_SPD_SHIFT)
1791 
1792 /* Bitfield definition for register of struct array CTRL: SMP_ACC */
1793 /*
1794  * ACC (RW)
1795  *
1796  * Sample override accelerate
1797  */
1798 #define SEI_CTRL_POS_SMP_ACC_ACC_MASK (0xFFFFFFFFUL)
1799 #define SEI_CTRL_POS_SMP_ACC_ACC_SHIFT (0U)
1800 #define SEI_CTRL_POS_SMP_ACC_ACC_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_ACC_ACC_SHIFT) & SEI_CTRL_POS_SMP_ACC_ACC_MASK)
1801 #define SEI_CTRL_POS_SMP_ACC_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_ACC_ACC_MASK) >> SEI_CTRL_POS_SMP_ACC_ACC_SHIFT)
1802 
1803 /* Bitfield definition for register of struct array CTRL: UPD_EN */
1804 /*
1805  * ACC_EN (RW)
1806  *
1807  * Position include acceleration
1808  * 0: use acceleration from update override acceleration register
1809  * 1: use acceleration from data register
1810  */
1811 #define SEI_CTRL_POS_UPD_EN_ACC_EN_MASK (0x80000000UL)
1812 #define SEI_CTRL_POS_UPD_EN_ACC_EN_SHIFT (31U)
1813 #define SEI_CTRL_POS_UPD_EN_ACC_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_ACC_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_ACC_EN_MASK)
1814 #define SEI_CTRL_POS_UPD_EN_ACC_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_ACC_EN_MASK) >> SEI_CTRL_POS_UPD_EN_ACC_EN_SHIFT)
1815 
1816 /*
1817  * ACC_SEL (RW)
1818  *
1819  * Data register for acceleration transfer
1820  */
1821 #define SEI_CTRL_POS_UPD_EN_ACC_SEL_MASK (0x1F000000UL)
1822 #define SEI_CTRL_POS_UPD_EN_ACC_SEL_SHIFT (24U)
1823 #define SEI_CTRL_POS_UPD_EN_ACC_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_ACC_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_ACC_SEL_MASK)
1824 #define SEI_CTRL_POS_UPD_EN_ACC_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_ACC_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_ACC_SEL_SHIFT)
1825 
1826 /*
1827  * SPD_EN (RW)
1828  *
1829  * Position include speed
1830  * 0: use speed from update override speed register
1831  * 1: use speed from data register
1832  */
1833 #define SEI_CTRL_POS_UPD_EN_SPD_EN_MASK (0x800000UL)
1834 #define SEI_CTRL_POS_UPD_EN_SPD_EN_SHIFT (23U)
1835 #define SEI_CTRL_POS_UPD_EN_SPD_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_SPD_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_SPD_EN_MASK)
1836 #define SEI_CTRL_POS_UPD_EN_SPD_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_SPD_EN_MASK) >> SEI_CTRL_POS_UPD_EN_SPD_EN_SHIFT)
1837 
1838 /*
1839  * SPD_SEL (RW)
1840  *
1841  * Data register for speed transfer
1842  */
1843 #define SEI_CTRL_POS_UPD_EN_SPD_SEL_MASK (0x1F0000UL)
1844 #define SEI_CTRL_POS_UPD_EN_SPD_SEL_SHIFT (16U)
1845 #define SEI_CTRL_POS_UPD_EN_SPD_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_SPD_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_SPD_SEL_MASK)
1846 #define SEI_CTRL_POS_UPD_EN_SPD_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_SPD_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_SPD_SEL_SHIFT)
1847 
1848 /*
1849  * REV_EN (RW)
1850  *
1851  * Position include revolution
1852  * 0: use revolution from update override revolution register
1853  * 1: use revolution from data register
1854  */
1855 #define SEI_CTRL_POS_UPD_EN_REV_EN_MASK (0x8000U)
1856 #define SEI_CTRL_POS_UPD_EN_REV_EN_SHIFT (15U)
1857 #define SEI_CTRL_POS_UPD_EN_REV_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_REV_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_REV_EN_MASK)
1858 #define SEI_CTRL_POS_UPD_EN_REV_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_REV_EN_MASK) >> SEI_CTRL_POS_UPD_EN_REV_EN_SHIFT)
1859 
1860 /*
1861  * REV_SEL (RW)
1862  *
1863  * Data register for revolution transfer
1864  */
1865 #define SEI_CTRL_POS_UPD_EN_REV_SEL_MASK (0x1F00U)
1866 #define SEI_CTRL_POS_UPD_EN_REV_SEL_SHIFT (8U)
1867 #define SEI_CTRL_POS_UPD_EN_REV_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_REV_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_REV_SEL_MASK)
1868 #define SEI_CTRL_POS_UPD_EN_REV_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_REV_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_REV_SEL_SHIFT)
1869 
1870 /*
1871  * POS_EN (RW)
1872  *
1873  * Position include position
1874  * 0: use position from update override position register
1875  * 1: use position from data register
1876  */
1877 #define SEI_CTRL_POS_UPD_EN_POS_EN_MASK (0x80U)
1878 #define SEI_CTRL_POS_UPD_EN_POS_EN_SHIFT (7U)
1879 #define SEI_CTRL_POS_UPD_EN_POS_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_POS_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_POS_EN_MASK)
1880 #define SEI_CTRL_POS_UPD_EN_POS_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_POS_EN_MASK) >> SEI_CTRL_POS_UPD_EN_POS_EN_SHIFT)
1881 
1882 /*
1883  * POS_SEL (RW)
1884  *
1885  * Data register for position transfer
1886  */
1887 #define SEI_CTRL_POS_UPD_EN_POS_SEL_MASK (0x1FU)
1888 #define SEI_CTRL_POS_UPD_EN_POS_SEL_SHIFT (0U)
1889 #define SEI_CTRL_POS_UPD_EN_POS_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_POS_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_POS_SEL_MASK)
1890 #define SEI_CTRL_POS_UPD_EN_POS_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_POS_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_POS_SEL_SHIFT)
1891 
1892 /* Bitfield definition for register of struct array CTRL: UPD_CFG */
1893 /*
1894  * TIME_OVRD (RW)
1895  *
1896  * Use override time
1897  * 0: use time sample from motor group
1898  * 1: use override time
1899  */
1900 #define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_MASK (0x80000000UL)
1901 #define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SHIFT (31U)
1902 #define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SHIFT) & SEI_CTRL_POS_UPD_CFG_TIME_OVRD_MASK)
1903 #define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_CFG_TIME_OVRD_MASK) >> SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SHIFT)
1904 
1905 /*
1906  * ONERR (RW)
1907  *
1908  * Sample one time
1909  * 0: Sample during windows time
1910  * 1: Close sample window after first sample
1911  */
1912 #define SEI_CTRL_POS_UPD_CFG_ONERR_MASK (0x1000000UL)
1913 #define SEI_CTRL_POS_UPD_CFG_ONERR_SHIFT (24U)
1914 #define SEI_CTRL_POS_UPD_CFG_ONERR_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_CFG_ONERR_SHIFT) & SEI_CTRL_POS_UPD_CFG_ONERR_MASK)
1915 #define SEI_CTRL_POS_UPD_CFG_ONERR_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_CFG_ONERR_MASK) >> SEI_CTRL_POS_UPD_CFG_ONERR_SHIFT)
1916 
1917 /*
1918  * LAT_SEL (RW)
1919  *
1920  * Latch selection
1921  * 0: latch 0
1922  * 1: latch 1
1923  * 2: latch 2
1924  * 3: latch 3
1925  */
1926 #define SEI_CTRL_POS_UPD_CFG_LAT_SEL_MASK (0x30000UL)
1927 #define SEI_CTRL_POS_UPD_CFG_LAT_SEL_SHIFT (16U)
1928 #define SEI_CTRL_POS_UPD_CFG_LAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_CFG_LAT_SEL_SHIFT) & SEI_CTRL_POS_UPD_CFG_LAT_SEL_MASK)
1929 #define SEI_CTRL_POS_UPD_CFG_LAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_CFG_LAT_SEL_MASK) >> SEI_CTRL_POS_UPD_CFG_LAT_SEL_SHIFT)
1930 
1931 /* Bitfield definition for register of struct array CTRL: UPD_DAT */
1932 /*
1933  * DAT_SEL (RW)
1934  *
1935  * Data register sampled, each bit represent a data register, select the DATA registers need to be updated when UPDATE happen.
1936  * Note: CRC register will be cleared automatically by UPDATE if select the DATA register used for CRC.
1937  */
1938 #define SEI_CTRL_POS_UPD_DAT_DAT_SEL_MASK (0xFFFFFFFFUL)
1939 #define SEI_CTRL_POS_UPD_DAT_DAT_SEL_SHIFT (0U)
1940 #define SEI_CTRL_POS_UPD_DAT_DAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_DAT_DAT_SEL_SHIFT) & SEI_CTRL_POS_UPD_DAT_DAT_SEL_MASK)
1941 #define SEI_CTRL_POS_UPD_DAT_DAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_DAT_DAT_SEL_MASK) >> SEI_CTRL_POS_UPD_DAT_DAT_SEL_SHIFT)
1942 
1943 /* Bitfield definition for register of struct array CTRL: UPD_TIME */
1944 /*
1945  * TIME (RW)
1946  *
1947  * Update override time
1948  */
1949 #define SEI_CTRL_POS_UPD_TIME_TIME_MASK (0xFFFFFFFFUL)
1950 #define SEI_CTRL_POS_UPD_TIME_TIME_SHIFT (0U)
1951 #define SEI_CTRL_POS_UPD_TIME_TIME_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_TIME_TIME_SHIFT) & SEI_CTRL_POS_UPD_TIME_TIME_MASK)
1952 #define SEI_CTRL_POS_UPD_TIME_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_TIME_TIME_MASK) >> SEI_CTRL_POS_UPD_TIME_TIME_SHIFT)
1953 
1954 /* Bitfield definition for register of struct array CTRL: UPD_POS */
1955 /*
1956  * POS (RW)
1957  *
1958  * Update override position
1959  */
1960 #define SEI_CTRL_POS_UPD_POS_POS_MASK (0xFFFFFFFFUL)
1961 #define SEI_CTRL_POS_UPD_POS_POS_SHIFT (0U)
1962 #define SEI_CTRL_POS_UPD_POS_POS_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_POS_POS_SHIFT) & SEI_CTRL_POS_UPD_POS_POS_MASK)
1963 #define SEI_CTRL_POS_UPD_POS_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_POS_POS_MASK) >> SEI_CTRL_POS_UPD_POS_POS_SHIFT)
1964 
1965 /* Bitfield definition for register of struct array CTRL: UPD_REV */
1966 /*
1967  * REV (RW)
1968  *
1969  * Update override revolution
1970  */
1971 #define SEI_CTRL_POS_UPD_REV_REV_MASK (0xFFFFFFFFUL)
1972 #define SEI_CTRL_POS_UPD_REV_REV_SHIFT (0U)
1973 #define SEI_CTRL_POS_UPD_REV_REV_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_REV_REV_SHIFT) & SEI_CTRL_POS_UPD_REV_REV_MASK)
1974 #define SEI_CTRL_POS_UPD_REV_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_REV_REV_MASK) >> SEI_CTRL_POS_UPD_REV_REV_SHIFT)
1975 
1976 /* Bitfield definition for register of struct array CTRL: UPD_SPD */
1977 /*
1978  * SPD (RW)
1979  *
1980  * Update override speed
1981  */
1982 #define SEI_CTRL_POS_UPD_SPD_SPD_MASK (0xFFFFFFFFUL)
1983 #define SEI_CTRL_POS_UPD_SPD_SPD_SHIFT (0U)
1984 #define SEI_CTRL_POS_UPD_SPD_SPD_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_SPD_SPD_SHIFT) & SEI_CTRL_POS_UPD_SPD_SPD_MASK)
1985 #define SEI_CTRL_POS_UPD_SPD_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_SPD_SPD_MASK) >> SEI_CTRL_POS_UPD_SPD_SPD_SHIFT)
1986 
1987 /* Bitfield definition for register of struct array CTRL: UPD_ACC */
1988 /*
1989  * ACC (RW)
1990  *
1991  * Update override accelerate
1992  */
1993 #define SEI_CTRL_POS_UPD_ACC_ACC_MASK (0xFFFFFFFFUL)
1994 #define SEI_CTRL_POS_UPD_ACC_ACC_SHIFT (0U)
1995 #define SEI_CTRL_POS_UPD_ACC_ACC_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_ACC_ACC_SHIFT) & SEI_CTRL_POS_UPD_ACC_ACC_MASK)
1996 #define SEI_CTRL_POS_UPD_ACC_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_ACC_ACC_MASK) >> SEI_CTRL_POS_UPD_ACC_ACC_SHIFT)
1997 
1998 /* Bitfield definition for register of struct array CTRL: SMP_VAL */
1999 /*
2000  * ACC (RO)
2001  *
2002  * Position include acceleration
2003  */
2004 #define SEI_CTRL_POS_SMP_VAL_ACC_MASK (0x80000000UL)
2005 #define SEI_CTRL_POS_SMP_VAL_ACC_SHIFT (31U)
2006 #define SEI_CTRL_POS_SMP_VAL_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_ACC_MASK) >> SEI_CTRL_POS_SMP_VAL_ACC_SHIFT)
2007 
2008 /*
2009  * SPD (RO)
2010  *
2011  * Position include speed
2012  */
2013 #define SEI_CTRL_POS_SMP_VAL_SPD_MASK (0x800000UL)
2014 #define SEI_CTRL_POS_SMP_VAL_SPD_SHIFT (23U)
2015 #define SEI_CTRL_POS_SMP_VAL_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_SPD_MASK) >> SEI_CTRL_POS_SMP_VAL_SPD_SHIFT)
2016 
2017 /*
2018  * REV (RO)
2019  *
2020  * Position include revolution
2021  */
2022 #define SEI_CTRL_POS_SMP_VAL_REV_MASK (0x8000U)
2023 #define SEI_CTRL_POS_SMP_VAL_REV_SHIFT (15U)
2024 #define SEI_CTRL_POS_SMP_VAL_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_REV_MASK) >> SEI_CTRL_POS_SMP_VAL_REV_SHIFT)
2025 
2026 /*
2027  * POS (RO)
2028  *
2029  * Position include position
2030  */
2031 #define SEI_CTRL_POS_SMP_VAL_POS_MASK (0x80U)
2032 #define SEI_CTRL_POS_SMP_VAL_POS_SHIFT (7U)
2033 #define SEI_CTRL_POS_SMP_VAL_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_POS_MASK) >> SEI_CTRL_POS_SMP_VAL_POS_SHIFT)
2034 
2035 /* Bitfield definition for register of struct array CTRL: SMP_STS */
2036 /*
2037  * OCCUR (RO)
2038  *
2039  * Sample occured
2040  * 0: Sample not happened
2041  * 1: Sample occured
2042  */
2043 #define SEI_CTRL_POS_SMP_STS_OCCUR_MASK (0x1000000UL)
2044 #define SEI_CTRL_POS_SMP_STS_OCCUR_SHIFT (24U)
2045 #define SEI_CTRL_POS_SMP_STS_OCCUR_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_STS_OCCUR_MASK) >> SEI_CTRL_POS_SMP_STS_OCCUR_SHIFT)
2046 
2047 /*
2048  * WIN_CNT (RO)
2049  *
2050  * Sample window counter
2051  */
2052 #define SEI_CTRL_POS_SMP_STS_WIN_CNT_MASK (0xFFFFU)
2053 #define SEI_CTRL_POS_SMP_STS_WIN_CNT_SHIFT (0U)
2054 #define SEI_CTRL_POS_SMP_STS_WIN_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_STS_WIN_CNT_MASK) >> SEI_CTRL_POS_SMP_STS_WIN_CNT_SHIFT)
2055 
2056 /* Bitfield definition for register of struct array CTRL: TIME_IN */
2057 /*
2058  * TIME (RO)
2059  *
2060  * input time
2061  */
2062 #define SEI_CTRL_POS_TIME_IN_TIME_MASK (0xFFFFFFFFUL)
2063 #define SEI_CTRL_POS_TIME_IN_TIME_SHIFT (0U)
2064 #define SEI_CTRL_POS_TIME_IN_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_TIME_IN_TIME_MASK) >> SEI_CTRL_POS_TIME_IN_TIME_SHIFT)
2065 
2066 /* Bitfield definition for register of struct array CTRL: POS_IN */
2067 /*
2068  * POS (RO)
2069  *
2070  * Input position
2071  */
2072 #define SEI_CTRL_POS_POS_IN_POS_MASK (0xFFFFFFFFUL)
2073 #define SEI_CTRL_POS_POS_IN_POS_SHIFT (0U)
2074 #define SEI_CTRL_POS_POS_IN_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_POS_IN_POS_MASK) >> SEI_CTRL_POS_POS_IN_POS_SHIFT)
2075 
2076 /* Bitfield definition for register of struct array CTRL: REV_IN */
2077 /*
2078  * REV (RO)
2079  *
2080  * Input revolution
2081  */
2082 #define SEI_CTRL_POS_REV_IN_REV_MASK (0xFFFFFFFFUL)
2083 #define SEI_CTRL_POS_REV_IN_REV_SHIFT (0U)
2084 #define SEI_CTRL_POS_REV_IN_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_REV_IN_REV_MASK) >> SEI_CTRL_POS_REV_IN_REV_SHIFT)
2085 
2086 /* Bitfield definition for register of struct array CTRL: SPD_IN */
2087 /*
2088  * SPD (RO)
2089  *
2090  * Input speed
2091  */
2092 #define SEI_CTRL_POS_SPD_IN_SPD_MASK (0xFFFFFFFFUL)
2093 #define SEI_CTRL_POS_SPD_IN_SPD_SHIFT (0U)
2094 #define SEI_CTRL_POS_SPD_IN_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SPD_IN_SPD_MASK) >> SEI_CTRL_POS_SPD_IN_SPD_SHIFT)
2095 
2096 /* Bitfield definition for register of struct array CTRL: ACC_IN */
2097 /*
2098  * ACC (RO)
2099  *
2100  * Input accelerate
2101  */
2102 #define SEI_CTRL_POS_ACC_IN_ACC_MASK (0xFFFFFFFFUL)
2103 #define SEI_CTRL_POS_ACC_IN_ACC_SHIFT (0U)
2104 #define SEI_CTRL_POS_ACC_IN_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_ACC_IN_ACC_MASK) >> SEI_CTRL_POS_ACC_IN_ACC_SHIFT)
2105 
2106 /* Bitfield definition for register of struct array CTRL: UPD_STS */
2107 /*
2108  * UPD_ERR (RO)
2109  *
2110  * Update error
2111  * 0: data receive normally
2112  * 1: data receive error
2113  */
2114 #define SEI_CTRL_POS_UPD_STS_UPD_ERR_MASK (0x1000000UL)
2115 #define SEI_CTRL_POS_UPD_STS_UPD_ERR_SHIFT (24U)
2116 #define SEI_CTRL_POS_UPD_STS_UPD_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_STS_UPD_ERR_MASK) >> SEI_CTRL_POS_UPD_STS_UPD_ERR_SHIFT)
2117 
2118 /* Bitfield definition for register of struct array CTRL: INT_EN */
2119 /*
2120  * TRG_ERR3 (RW)
2121  *
2122  * Trigger3 failed
2123  */
2124 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_MASK (0x80000000UL)
2125 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SHIFT (31U)
2126 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR3_MASK)
2127 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR3_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SHIFT)
2128 
2129 /*
2130  * TRG_ERR2 (RW)
2131  *
2132  * Trigger2 failed
2133  */
2134 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_MASK (0x40000000UL)
2135 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SHIFT (30U)
2136 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR2_MASK)
2137 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR2_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SHIFT)
2138 
2139 /*
2140  * TRG_ERR1 (RW)
2141  *
2142  * Trigger1 failed
2143  */
2144 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_MASK (0x20000000UL)
2145 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SHIFT (29U)
2146 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR1_MASK)
2147 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR1_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SHIFT)
2148 
2149 /*
2150  * TRG_ERR0 (RW)
2151  *
2152  * Trigger0 failed
2153  */
2154 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_MASK (0x10000000UL)
2155 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SHIFT (28U)
2156 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR0_MASK)
2157 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR0_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SHIFT)
2158 
2159 /*
2160  * TRIGER3 (RW)
2161  *
2162  * Trigger3
2163  */
2164 #define SEI_CTRL_IRQ_INT_EN_TRIGER3_MASK (0x8000000UL)
2165 #define SEI_CTRL_IRQ_INT_EN_TRIGER3_SHIFT (27U)
2166 #define SEI_CTRL_IRQ_INT_EN_TRIGER3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER3_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER3_MASK)
2167 #define SEI_CTRL_IRQ_INT_EN_TRIGER3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER3_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER3_SHIFT)
2168 
2169 /*
2170  * TRIGER2 (RW)
2171  *
2172  * Trigger2
2173  */
2174 #define SEI_CTRL_IRQ_INT_EN_TRIGER2_MASK (0x4000000UL)
2175 #define SEI_CTRL_IRQ_INT_EN_TRIGER2_SHIFT (26U)
2176 #define SEI_CTRL_IRQ_INT_EN_TRIGER2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER2_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER2_MASK)
2177 #define SEI_CTRL_IRQ_INT_EN_TRIGER2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER2_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER2_SHIFT)
2178 
2179 /*
2180  * TRIGER1 (RW)
2181  *
2182  * Trigger1
2183  */
2184 #define SEI_CTRL_IRQ_INT_EN_TRIGER1_MASK (0x2000000UL)
2185 #define SEI_CTRL_IRQ_INT_EN_TRIGER1_SHIFT (25U)
2186 #define SEI_CTRL_IRQ_INT_EN_TRIGER1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER1_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER1_MASK)
2187 #define SEI_CTRL_IRQ_INT_EN_TRIGER1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER1_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER1_SHIFT)
2188 
2189 /*
2190  * TRIGER0 (RW)
2191  *
2192  * Trigger0
2193  */
2194 #define SEI_CTRL_IRQ_INT_EN_TRIGER0_MASK (0x1000000UL)
2195 #define SEI_CTRL_IRQ_INT_EN_TRIGER0_SHIFT (24U)
2196 #define SEI_CTRL_IRQ_INT_EN_TRIGER0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER0_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER0_MASK)
2197 #define SEI_CTRL_IRQ_INT_EN_TRIGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER0_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER0_SHIFT)
2198 
2199 /*
2200  * SMP_ERR (RW)
2201  *
2202  * Sample error
2203  */
2204 #define SEI_CTRL_IRQ_INT_EN_SMP_ERR_MASK (0x100000UL)
2205 #define SEI_CTRL_IRQ_INT_EN_SMP_ERR_SHIFT (20U)
2206 #define SEI_CTRL_IRQ_INT_EN_SMP_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_SMP_ERR_SHIFT) & SEI_CTRL_IRQ_INT_EN_SMP_ERR_MASK)
2207 #define SEI_CTRL_IRQ_INT_EN_SMP_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_SMP_ERR_MASK) >> SEI_CTRL_IRQ_INT_EN_SMP_ERR_SHIFT)
2208 
2209 /*
2210  * LATCH3 (RW)
2211  *
2212  * Latch3
2213  */
2214 #define SEI_CTRL_IRQ_INT_EN_LATCH3_MASK (0x80000UL)
2215 #define SEI_CTRL_IRQ_INT_EN_LATCH3_SHIFT (19U)
2216 #define SEI_CTRL_IRQ_INT_EN_LATCH3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH3_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH3_MASK)
2217 #define SEI_CTRL_IRQ_INT_EN_LATCH3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH3_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH3_SHIFT)
2218 
2219 /*
2220  * LATCH2 (RW)
2221  *
2222  * Latch2
2223  */
2224 #define SEI_CTRL_IRQ_INT_EN_LATCH2_MASK (0x40000UL)
2225 #define SEI_CTRL_IRQ_INT_EN_LATCH2_SHIFT (18U)
2226 #define SEI_CTRL_IRQ_INT_EN_LATCH2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH2_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH2_MASK)
2227 #define SEI_CTRL_IRQ_INT_EN_LATCH2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH2_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH2_SHIFT)
2228 
2229 /*
2230  * LATCH1 (RW)
2231  *
2232  * Latch1
2233  */
2234 #define SEI_CTRL_IRQ_INT_EN_LATCH1_MASK (0x20000UL)
2235 #define SEI_CTRL_IRQ_INT_EN_LATCH1_SHIFT (17U)
2236 #define SEI_CTRL_IRQ_INT_EN_LATCH1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH1_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH1_MASK)
2237 #define SEI_CTRL_IRQ_INT_EN_LATCH1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH1_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH1_SHIFT)
2238 
2239 /*
2240  * LATCH0 (RW)
2241  *
2242  * Latch0
2243  */
2244 #define SEI_CTRL_IRQ_INT_EN_LATCH0_MASK (0x10000UL)
2245 #define SEI_CTRL_IRQ_INT_EN_LATCH0_SHIFT (16U)
2246 #define SEI_CTRL_IRQ_INT_EN_LATCH0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH0_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH0_MASK)
2247 #define SEI_CTRL_IRQ_INT_EN_LATCH0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH0_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH0_SHIFT)
2248 
2249 /*
2250  * TIMEOUT (RW)
2251  *
2252  * Timeout
2253  */
2254 #define SEI_CTRL_IRQ_INT_EN_TIMEOUT_MASK (0x2000U)
2255 #define SEI_CTRL_IRQ_INT_EN_TIMEOUT_SHIFT (13U)
2256 #define SEI_CTRL_IRQ_INT_EN_TIMEOUT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TIMEOUT_SHIFT) & SEI_CTRL_IRQ_INT_EN_TIMEOUT_MASK)
2257 #define SEI_CTRL_IRQ_INT_EN_TIMEOUT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TIMEOUT_MASK) >> SEI_CTRL_IRQ_INT_EN_TIMEOUT_SHIFT)
2258 
2259 /*
2260  * TRX_ERR (RW)
2261  *
2262  * Transfer error
2263  */
2264 #define SEI_CTRL_IRQ_INT_EN_TRX_ERR_MASK (0x1000U)
2265 #define SEI_CTRL_IRQ_INT_EN_TRX_ERR_SHIFT (12U)
2266 #define SEI_CTRL_IRQ_INT_EN_TRX_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRX_ERR_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRX_ERR_MASK)
2267 #define SEI_CTRL_IRQ_INT_EN_TRX_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRX_ERR_MASK) >> SEI_CTRL_IRQ_INT_EN_TRX_ERR_SHIFT)
2268 
2269 /*
2270  * INSTR1_END (RW)
2271  *
2272  * Instruction 1 end
2273  */
2274 #define SEI_CTRL_IRQ_INT_EN_INSTR1_END_MASK (0x800U)
2275 #define SEI_CTRL_IRQ_INT_EN_INSTR1_END_SHIFT (11U)
2276 #define SEI_CTRL_IRQ_INT_EN_INSTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR1_END_MASK)
2277 #define SEI_CTRL_IRQ_INT_EN_INSTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR1_END_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR1_END_SHIFT)
2278 
2279 /*
2280  * INSTR0_END (RW)
2281  *
2282  * Instruction 0 end
2283  */
2284 #define SEI_CTRL_IRQ_INT_EN_INSTR0_END_MASK (0x400U)
2285 #define SEI_CTRL_IRQ_INT_EN_INSTR0_END_SHIFT (10U)
2286 #define SEI_CTRL_IRQ_INT_EN_INSTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR0_END_MASK)
2287 #define SEI_CTRL_IRQ_INT_EN_INSTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR0_END_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR0_END_SHIFT)
2288 
2289 /*
2290  * PTR1_END (RW)
2291  *
2292  * Pointer 1 end
2293  */
2294 #define SEI_CTRL_IRQ_INT_EN_PTR1_END_MASK (0x200U)
2295 #define SEI_CTRL_IRQ_INT_EN_PTR1_END_SHIFT (9U)
2296 #define SEI_CTRL_IRQ_INT_EN_PTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR1_END_MASK)
2297 #define SEI_CTRL_IRQ_INT_EN_PTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR1_END_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR1_END_SHIFT)
2298 
2299 /*
2300  * PTR0_END (RW)
2301  *
2302  * Pointer 0 end
2303  */
2304 #define SEI_CTRL_IRQ_INT_EN_PTR0_END_MASK (0x100U)
2305 #define SEI_CTRL_IRQ_INT_EN_PTR0_END_SHIFT (8U)
2306 #define SEI_CTRL_IRQ_INT_EN_PTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR0_END_MASK)
2307 #define SEI_CTRL_IRQ_INT_EN_PTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR0_END_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR0_END_SHIFT)
2308 
2309 /*
2310  * INSTR1_ST (RW)
2311  *
2312  * Instruction 1 start
2313  */
2314 #define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_MASK (0x80U)
2315 #define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SHIFT (7U)
2316 #define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR1_ST_MASK)
2317 #define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SHIFT)
2318 
2319 /*
2320  * INSTR0_ST (RW)
2321  *
2322  * Instruction 0 start
2323  */
2324 #define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_MASK (0x40U)
2325 #define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SHIFT (6U)
2326 #define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR0_ST_MASK)
2327 #define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SHIFT)
2328 
2329 /*
2330  * PTR1_ST (RW)
2331  *
2332  * Pointer 1 start
2333  */
2334 #define SEI_CTRL_IRQ_INT_EN_PTR1_ST_MASK (0x20U)
2335 #define SEI_CTRL_IRQ_INT_EN_PTR1_ST_SHIFT (5U)
2336 #define SEI_CTRL_IRQ_INT_EN_PTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR1_ST_MASK)
2337 #define SEI_CTRL_IRQ_INT_EN_PTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR1_ST_SHIFT)
2338 
2339 /*
2340  * PTR0_ST (RW)
2341  *
2342  * Pointer 0 start
2343  */
2344 #define SEI_CTRL_IRQ_INT_EN_PTR0_ST_MASK (0x10U)
2345 #define SEI_CTRL_IRQ_INT_EN_PTR0_ST_SHIFT (4U)
2346 #define SEI_CTRL_IRQ_INT_EN_PTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR0_ST_MASK)
2347 #define SEI_CTRL_IRQ_INT_EN_PTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR0_ST_SHIFT)
2348 
2349 /*
2350  * WDOG (RW)
2351  *
2352  * Watch dog
2353  */
2354 #define SEI_CTRL_IRQ_INT_EN_WDOG_MASK (0x4U)
2355 #define SEI_CTRL_IRQ_INT_EN_WDOG_SHIFT (2U)
2356 #define SEI_CTRL_IRQ_INT_EN_WDOG_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_WDOG_SHIFT) & SEI_CTRL_IRQ_INT_EN_WDOG_MASK)
2357 #define SEI_CTRL_IRQ_INT_EN_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_WDOG_MASK) >> SEI_CTRL_IRQ_INT_EN_WDOG_SHIFT)
2358 
2359 /*
2360  * EXCEPT (RW)
2361  *
2362  * Exception
2363  */
2364 #define SEI_CTRL_IRQ_INT_EN_EXCEPT_MASK (0x2U)
2365 #define SEI_CTRL_IRQ_INT_EN_EXCEPT_SHIFT (1U)
2366 #define SEI_CTRL_IRQ_INT_EN_EXCEPT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_EXCEPT_SHIFT) & SEI_CTRL_IRQ_INT_EN_EXCEPT_MASK)
2367 #define SEI_CTRL_IRQ_INT_EN_EXCEPT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_EXCEPT_MASK) >> SEI_CTRL_IRQ_INT_EN_EXCEPT_SHIFT)
2368 
2369 /*
2370  * STALL (RW)
2371  *
2372  * Stall
2373  */
2374 #define SEI_CTRL_IRQ_INT_EN_STALL_MASK (0x1U)
2375 #define SEI_CTRL_IRQ_INT_EN_STALL_SHIFT (0U)
2376 #define SEI_CTRL_IRQ_INT_EN_STALL_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_STALL_SHIFT) & SEI_CTRL_IRQ_INT_EN_STALL_MASK)
2377 #define SEI_CTRL_IRQ_INT_EN_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_STALL_MASK) >> SEI_CTRL_IRQ_INT_EN_STALL_SHIFT)
2378 
2379 /* Bitfield definition for register of struct array CTRL: INT_FLAG */
2380 /*
2381  * TRG_ERR3 (W1C)
2382  *
2383  * Trigger3 failed
2384  */
2385 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_MASK (0x80000000UL)
2386 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SHIFT (31U)
2387 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_MASK)
2388 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SHIFT)
2389 
2390 /*
2391  * TRG_ERR2 (W1C)
2392  *
2393  * Trigger2 failed
2394  */
2395 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_MASK (0x40000000UL)
2396 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SHIFT (30U)
2397 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_MASK)
2398 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SHIFT)
2399 
2400 /*
2401  * TRG_ERR1 (W1C)
2402  *
2403  * Trigger1 failed
2404  */
2405 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_MASK (0x20000000UL)
2406 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SHIFT (29U)
2407 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_MASK)
2408 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SHIFT)
2409 
2410 /*
2411  * TRG_ERR0 (W1C)
2412  *
2413  * Trigger0 failed
2414  */
2415 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_MASK (0x10000000UL)
2416 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SHIFT (28U)
2417 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_MASK)
2418 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SHIFT)
2419 
2420 /*
2421  * TRIGER3 (W1C)
2422  *
2423  * Trigger3
2424  */
2425 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_MASK (0x8000000UL)
2426 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SHIFT (27U)
2427 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER3_MASK)
2428 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER3_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SHIFT)
2429 
2430 /*
2431  * TRIGER2 (W1C)
2432  *
2433  * Trigger2
2434  */
2435 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_MASK (0x4000000UL)
2436 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SHIFT (26U)
2437 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER2_MASK)
2438 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER2_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SHIFT)
2439 
2440 /*
2441  * TRIGER1 (W1C)
2442  *
2443  * Trigger1
2444  */
2445 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_MASK (0x2000000UL)
2446 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SHIFT (25U)
2447 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER1_MASK)
2448 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER1_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SHIFT)
2449 
2450 /*
2451  * TRIGER0 (W1C)
2452  *
2453  * Trigger0
2454  */
2455 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_MASK (0x1000000UL)
2456 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SHIFT (24U)
2457 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER0_MASK)
2458 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER0_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SHIFT)
2459 
2460 /*
2461  * SMP_ERR (W1C)
2462  *
2463  * Sample error
2464  */
2465 #define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_MASK (0x100000UL)
2466 #define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SHIFT (20U)
2467 #define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_MASK)
2468 #define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_MASK) >> SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SHIFT)
2469 
2470 /*
2471  * LATCH3 (W1C)
2472  *
2473  * Latch3
2474  */
2475 #define SEI_CTRL_IRQ_INT_FLAG_LATCH3_MASK (0x80000UL)
2476 #define SEI_CTRL_IRQ_INT_FLAG_LATCH3_SHIFT (19U)
2477 #define SEI_CTRL_IRQ_INT_FLAG_LATCH3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH3_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH3_MASK)
2478 #define SEI_CTRL_IRQ_INT_FLAG_LATCH3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH3_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH3_SHIFT)
2479 
2480 /*
2481  * LATCH2 (W1C)
2482  *
2483  * Latch2
2484  */
2485 #define SEI_CTRL_IRQ_INT_FLAG_LATCH2_MASK (0x40000UL)
2486 #define SEI_CTRL_IRQ_INT_FLAG_LATCH2_SHIFT (18U)
2487 #define SEI_CTRL_IRQ_INT_FLAG_LATCH2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH2_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH2_MASK)
2488 #define SEI_CTRL_IRQ_INT_FLAG_LATCH2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH2_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH2_SHIFT)
2489 
2490 /*
2491  * LATCH1 (W1C)
2492  *
2493  * Latch1
2494  */
2495 #define SEI_CTRL_IRQ_INT_FLAG_LATCH1_MASK (0x20000UL)
2496 #define SEI_CTRL_IRQ_INT_FLAG_LATCH1_SHIFT (17U)
2497 #define SEI_CTRL_IRQ_INT_FLAG_LATCH1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH1_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH1_MASK)
2498 #define SEI_CTRL_IRQ_INT_FLAG_LATCH1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH1_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH1_SHIFT)
2499 
2500 /*
2501  * LATCH0 (W1C)
2502  *
2503  * Latch0
2504  */
2505 #define SEI_CTRL_IRQ_INT_FLAG_LATCH0_MASK (0x10000UL)
2506 #define SEI_CTRL_IRQ_INT_FLAG_LATCH0_SHIFT (16U)
2507 #define SEI_CTRL_IRQ_INT_FLAG_LATCH0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH0_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH0_MASK)
2508 #define SEI_CTRL_IRQ_INT_FLAG_LATCH0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH0_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH0_SHIFT)
2509 
2510 /*
2511  * TIMEOUT (W1C)
2512  *
2513  * Timeout
2514  */
2515 #define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_MASK (0x2000U)
2516 #define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SHIFT (13U)
2517 #define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_MASK)
2518 #define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SHIFT)
2519 
2520 /*
2521  * TRX_ERR (W1C)
2522  *
2523  * Transfer error
2524  */
2525 #define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_MASK (0x1000U)
2526 #define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SHIFT (12U)
2527 #define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_MASK)
2528 #define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SHIFT)
2529 
2530 /*
2531  * INSTR1_END (W1C)
2532  *
2533  * Instruction 1 end
2534  */
2535 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_MASK (0x800U)
2536 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SHIFT (11U)
2537 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_MASK)
2538 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SHIFT)
2539 
2540 /*
2541  * INSTR0_END (W1C)
2542  *
2543  * Instruction 0 end
2544  */
2545 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_MASK (0x400U)
2546 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SHIFT (10U)
2547 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_MASK)
2548 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SHIFT)
2549 
2550 /*
2551  * PTR1_END (W1C)
2552  *
2553  * Pointer 1 end
2554  */
2555 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_MASK (0x200U)
2556 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SHIFT (9U)
2557 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR1_END_MASK)
2558 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR1_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SHIFT)
2559 
2560 /*
2561  * PTR0_END (W1C)
2562  *
2563  * Pointer 0 end
2564  */
2565 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_MASK (0x100U)
2566 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SHIFT (8U)
2567 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR0_END_MASK)
2568 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR0_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SHIFT)
2569 
2570 /*
2571  * INSTR1_ST (W1C)
2572  *
2573  * Instruction 1 start
2574  */
2575 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_MASK (0x80U)
2576 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SHIFT (7U)
2577 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_MASK)
2578 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SHIFT)
2579 
2580 /*
2581  * INSTR0_ST (W1C)
2582  *
2583  * Instruction 0 start
2584  */
2585 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_MASK (0x40U)
2586 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SHIFT (6U)
2587 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_MASK)
2588 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SHIFT)
2589 
2590 /*
2591  * PTR1_ST (W1C)
2592  *
2593  * Pointer 1 start
2594  */
2595 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_MASK (0x20U)
2596 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SHIFT (5U)
2597 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_MASK)
2598 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SHIFT)
2599 
2600 /*
2601  * PTR0_ST (W1C)
2602  *
2603  * Pointer 0 start
2604  */
2605 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_MASK (0x10U)
2606 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SHIFT (4U)
2607 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_MASK)
2608 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SHIFT)
2609 
2610 /*
2611  * WDOG (W1C)
2612  *
2613  * Watch dog
2614  */
2615 #define SEI_CTRL_IRQ_INT_FLAG_WDOG_MASK (0x4U)
2616 #define SEI_CTRL_IRQ_INT_FLAG_WDOG_SHIFT (2U)
2617 #define SEI_CTRL_IRQ_INT_FLAG_WDOG_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_WDOG_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_WDOG_MASK)
2618 #define SEI_CTRL_IRQ_INT_FLAG_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_WDOG_MASK) >> SEI_CTRL_IRQ_INT_FLAG_WDOG_SHIFT)
2619 
2620 /*
2621  * EXCEPT (W1C)
2622  *
2623  * Exception
2624  */
2625 #define SEI_CTRL_IRQ_INT_FLAG_EXCEPT_MASK (0x2U)
2626 #define SEI_CTRL_IRQ_INT_FLAG_EXCEPT_SHIFT (1U)
2627 #define SEI_CTRL_IRQ_INT_FLAG_EXCEPT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_EXCEPT_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_EXCEPT_MASK)
2628 #define SEI_CTRL_IRQ_INT_FLAG_EXCEPT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_EXCEPT_MASK) >> SEI_CTRL_IRQ_INT_FLAG_EXCEPT_SHIFT)
2629 
2630 /*
2631  * STALL (W1C)
2632  *
2633  * Stall
2634  */
2635 #define SEI_CTRL_IRQ_INT_FLAG_STALL_MASK (0x1U)
2636 #define SEI_CTRL_IRQ_INT_FLAG_STALL_SHIFT (0U)
2637 #define SEI_CTRL_IRQ_INT_FLAG_STALL_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_STALL_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_STALL_MASK)
2638 #define SEI_CTRL_IRQ_INT_FLAG_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_STALL_MASK) >> SEI_CTRL_IRQ_INT_FLAG_STALL_SHIFT)
2639 
2640 /* Bitfield definition for register of struct array CTRL: INT_STS */
2641 /*
2642  * TRG_ERR3 (RO)
2643  *
2644  * Trigger3 failed
2645  */
2646 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR3_MASK (0x80000000UL)
2647 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR3_SHIFT (31U)
2648 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR3_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR3_SHIFT)
2649 
2650 /*
2651  * TRG_ERR2 (RO)
2652  *
2653  * Trigger2 failed
2654  */
2655 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR2_MASK (0x40000000UL)
2656 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR2_SHIFT (30U)
2657 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR2_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR2_SHIFT)
2658 
2659 /*
2660  * TRG_ERR1 (RO)
2661  *
2662  * Trigger1 failed
2663  */
2664 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR1_MASK (0x20000000UL)
2665 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR1_SHIFT (29U)
2666 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR1_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR1_SHIFT)
2667 
2668 /*
2669  * TRG_ERR0 (RO)
2670  *
2671  * Trigger0 failed
2672  */
2673 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR0_MASK (0x10000000UL)
2674 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR0_SHIFT (28U)
2675 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR0_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR0_SHIFT)
2676 
2677 /*
2678  * TRIGER3 (RO)
2679  *
2680  * Trigger3
2681  */
2682 #define SEI_CTRL_IRQ_INT_STS_TRIGER3_MASK (0x8000000UL)
2683 #define SEI_CTRL_IRQ_INT_STS_TRIGER3_SHIFT (27U)
2684 #define SEI_CTRL_IRQ_INT_STS_TRIGER3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER3_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER3_SHIFT)
2685 
2686 /*
2687  * TRIGER2 (RO)
2688  *
2689  * Trigger2
2690  */
2691 #define SEI_CTRL_IRQ_INT_STS_TRIGER2_MASK (0x4000000UL)
2692 #define SEI_CTRL_IRQ_INT_STS_TRIGER2_SHIFT (26U)
2693 #define SEI_CTRL_IRQ_INT_STS_TRIGER2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER2_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER2_SHIFT)
2694 
2695 /*
2696  * TRIGER1 (RO)
2697  *
2698  * Trigger1
2699  */
2700 #define SEI_CTRL_IRQ_INT_STS_TRIGER1_MASK (0x2000000UL)
2701 #define SEI_CTRL_IRQ_INT_STS_TRIGER1_SHIFT (25U)
2702 #define SEI_CTRL_IRQ_INT_STS_TRIGER1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER1_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER1_SHIFT)
2703 
2704 /*
2705  * TRIGER0 (RO)
2706  *
2707  * Trigger0
2708  */
2709 #define SEI_CTRL_IRQ_INT_STS_TRIGER0_MASK (0x1000000UL)
2710 #define SEI_CTRL_IRQ_INT_STS_TRIGER0_SHIFT (24U)
2711 #define SEI_CTRL_IRQ_INT_STS_TRIGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER0_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER0_SHIFT)
2712 
2713 /*
2714  * SMP_ERR (RO)
2715  *
2716  * Sample error
2717  */
2718 #define SEI_CTRL_IRQ_INT_STS_SMP_ERR_MASK (0x100000UL)
2719 #define SEI_CTRL_IRQ_INT_STS_SMP_ERR_SHIFT (20U)
2720 #define SEI_CTRL_IRQ_INT_STS_SMP_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_SMP_ERR_MASK) >> SEI_CTRL_IRQ_INT_STS_SMP_ERR_SHIFT)
2721 
2722 /*
2723  * LATCH3 (RO)
2724  *
2725  * Latch3
2726  */
2727 #define SEI_CTRL_IRQ_INT_STS_LATCH3_MASK (0x80000UL)
2728 #define SEI_CTRL_IRQ_INT_STS_LATCH3_SHIFT (19U)
2729 #define SEI_CTRL_IRQ_INT_STS_LATCH3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH3_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH3_SHIFT)
2730 
2731 /*
2732  * LATCH2 (RO)
2733  *
2734  * Latch2
2735  */
2736 #define SEI_CTRL_IRQ_INT_STS_LATCH2_MASK (0x40000UL)
2737 #define SEI_CTRL_IRQ_INT_STS_LATCH2_SHIFT (18U)
2738 #define SEI_CTRL_IRQ_INT_STS_LATCH2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH2_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH2_SHIFT)
2739 
2740 /*
2741  * LATCH1 (RO)
2742  *
2743  * Latch1
2744  */
2745 #define SEI_CTRL_IRQ_INT_STS_LATCH1_MASK (0x20000UL)
2746 #define SEI_CTRL_IRQ_INT_STS_LATCH1_SHIFT (17U)
2747 #define SEI_CTRL_IRQ_INT_STS_LATCH1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH1_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH1_SHIFT)
2748 
2749 /*
2750  * LATCH0 (RO)
2751  *
2752  * Latch0
2753  */
2754 #define SEI_CTRL_IRQ_INT_STS_LATCH0_MASK (0x10000UL)
2755 #define SEI_CTRL_IRQ_INT_STS_LATCH0_SHIFT (16U)
2756 #define SEI_CTRL_IRQ_INT_STS_LATCH0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH0_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH0_SHIFT)
2757 
2758 /*
2759  * TIMEOUT (RO)
2760  *
2761  * Timeout
2762  */
2763 #define SEI_CTRL_IRQ_INT_STS_TIMEOUT_MASK (0x2000U)
2764 #define SEI_CTRL_IRQ_INT_STS_TIMEOUT_SHIFT (13U)
2765 #define SEI_CTRL_IRQ_INT_STS_TIMEOUT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TIMEOUT_MASK) >> SEI_CTRL_IRQ_INT_STS_TIMEOUT_SHIFT)
2766 
2767 /*
2768  * TRX_ERR (RO)
2769  *
2770  * Transfer error
2771  */
2772 #define SEI_CTRL_IRQ_INT_STS_TRX_ERR_MASK (0x1000U)
2773 #define SEI_CTRL_IRQ_INT_STS_TRX_ERR_SHIFT (12U)
2774 #define SEI_CTRL_IRQ_INT_STS_TRX_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRX_ERR_MASK) >> SEI_CTRL_IRQ_INT_STS_TRX_ERR_SHIFT)
2775 
2776 /*
2777  * INSTR1_END (RO)
2778  *
2779  * Instruction 1 end
2780  */
2781 #define SEI_CTRL_IRQ_INT_STS_INSTR1_END_MASK (0x800U)
2782 #define SEI_CTRL_IRQ_INT_STS_INSTR1_END_SHIFT (11U)
2783 #define SEI_CTRL_IRQ_INT_STS_INSTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR1_END_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR1_END_SHIFT)
2784 
2785 /*
2786  * INSTR0_END (RO)
2787  *
2788  * Instruction 0 end
2789  */
2790 #define SEI_CTRL_IRQ_INT_STS_INSTR0_END_MASK (0x400U)
2791 #define SEI_CTRL_IRQ_INT_STS_INSTR0_END_SHIFT (10U)
2792 #define SEI_CTRL_IRQ_INT_STS_INSTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR0_END_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR0_END_SHIFT)
2793 
2794 /*
2795  * PTR1_END (RO)
2796  *
2797  * Pointer 1 end
2798  */
2799 #define SEI_CTRL_IRQ_INT_STS_PTR1_END_MASK (0x200U)
2800 #define SEI_CTRL_IRQ_INT_STS_PTR1_END_SHIFT (9U)
2801 #define SEI_CTRL_IRQ_INT_STS_PTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR1_END_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR1_END_SHIFT)
2802 
2803 /*
2804  * PTR0_END (RO)
2805  *
2806  * Pointer 0 end
2807  */
2808 #define SEI_CTRL_IRQ_INT_STS_PTR0_END_MASK (0x100U)
2809 #define SEI_CTRL_IRQ_INT_STS_PTR0_END_SHIFT (8U)
2810 #define SEI_CTRL_IRQ_INT_STS_PTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR0_END_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR0_END_SHIFT)
2811 
2812 /*
2813  * INSTR1_ST (RO)
2814  *
2815  * Instruction 1 start
2816  */
2817 #define SEI_CTRL_IRQ_INT_STS_INSTR1_ST_MASK (0x80U)
2818 #define SEI_CTRL_IRQ_INT_STS_INSTR1_ST_SHIFT (7U)
2819 #define SEI_CTRL_IRQ_INT_STS_INSTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR1_ST_SHIFT)
2820 
2821 /*
2822  * INSTR0_ST (RO)
2823  *
2824  * Instruction 0 start
2825  */
2826 #define SEI_CTRL_IRQ_INT_STS_INSTR0_ST_MASK (0x40U)
2827 #define SEI_CTRL_IRQ_INT_STS_INSTR0_ST_SHIFT (6U)
2828 #define SEI_CTRL_IRQ_INT_STS_INSTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR0_ST_SHIFT)
2829 
2830 /*
2831  * PTR1_ST (RO)
2832  *
2833  * Pointer 1 start
2834  */
2835 #define SEI_CTRL_IRQ_INT_STS_PTR1_ST_MASK (0x20U)
2836 #define SEI_CTRL_IRQ_INT_STS_PTR1_ST_SHIFT (5U)
2837 #define SEI_CTRL_IRQ_INT_STS_PTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR1_ST_SHIFT)
2838 
2839 /*
2840  * PTR0_ST (RO)
2841  *
2842  * Pointer 0 start
2843  */
2844 #define SEI_CTRL_IRQ_INT_STS_PTR0_ST_MASK (0x10U)
2845 #define SEI_CTRL_IRQ_INT_STS_PTR0_ST_SHIFT (4U)
2846 #define SEI_CTRL_IRQ_INT_STS_PTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR0_ST_SHIFT)
2847 
2848 /*
2849  * WDOG (RO)
2850  *
2851  * Watch dog
2852  */
2853 #define SEI_CTRL_IRQ_INT_STS_WDOG_MASK (0x4U)
2854 #define SEI_CTRL_IRQ_INT_STS_WDOG_SHIFT (2U)
2855 #define SEI_CTRL_IRQ_INT_STS_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_WDOG_MASK) >> SEI_CTRL_IRQ_INT_STS_WDOG_SHIFT)
2856 
2857 /*
2858  * EXCEPT (RO)
2859  *
2860  * Exception
2861  */
2862 #define SEI_CTRL_IRQ_INT_STS_EXCEPT_MASK (0x2U)
2863 #define SEI_CTRL_IRQ_INT_STS_EXCEPT_SHIFT (1U)
2864 #define SEI_CTRL_IRQ_INT_STS_EXCEPT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_EXCEPT_MASK) >> SEI_CTRL_IRQ_INT_STS_EXCEPT_SHIFT)
2865 
2866 /*
2867  * STALL (RO)
2868  *
2869  * Stall
2870  */
2871 #define SEI_CTRL_IRQ_INT_STS_STALL_MASK (0x1U)
2872 #define SEI_CTRL_IRQ_INT_STS_STALL_SHIFT (0U)
2873 #define SEI_CTRL_IRQ_INT_STS_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_STALL_MASK) >> SEI_CTRL_IRQ_INT_STS_STALL_SHIFT)
2874 
2875 /* Bitfield definition for register of struct array CTRL: POINTER0 */
2876 /*
2877  * POINTER (RW)
2878  *
2879  * Match pointer 0
2880  */
2881 #define SEI_CTRL_IRQ_POINTER0_POINTER_MASK (0xFFU)
2882 #define SEI_CTRL_IRQ_POINTER0_POINTER_SHIFT (0U)
2883 #define SEI_CTRL_IRQ_POINTER0_POINTER_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_POINTER0_POINTER_SHIFT) & SEI_CTRL_IRQ_POINTER0_POINTER_MASK)
2884 #define SEI_CTRL_IRQ_POINTER0_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_POINTER0_POINTER_MASK) >> SEI_CTRL_IRQ_POINTER0_POINTER_SHIFT)
2885 
2886 /* Bitfield definition for register of struct array CTRL: POINTER1 */
2887 /*
2888  * POINTER (RW)
2889  *
2890  * Match pointer 1
2891  */
2892 #define SEI_CTRL_IRQ_POINTER1_POINTER_MASK (0xFFU)
2893 #define SEI_CTRL_IRQ_POINTER1_POINTER_SHIFT (0U)
2894 #define SEI_CTRL_IRQ_POINTER1_POINTER_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_POINTER1_POINTER_SHIFT) & SEI_CTRL_IRQ_POINTER1_POINTER_MASK)
2895 #define SEI_CTRL_IRQ_POINTER1_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_POINTER1_POINTER_MASK) >> SEI_CTRL_IRQ_POINTER1_POINTER_SHIFT)
2896 
2897 /* Bitfield definition for register of struct array CTRL: INSTR0 */
2898 /*
2899  * INSTR (RW)
2900  *
2901  * Match instruction 0
2902  */
2903 #define SEI_CTRL_IRQ_INSTR0_INSTR_MASK (0xFFFFFFFFUL)
2904 #define SEI_CTRL_IRQ_INSTR0_INSTR_SHIFT (0U)
2905 #define SEI_CTRL_IRQ_INSTR0_INSTR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INSTR0_INSTR_SHIFT) & SEI_CTRL_IRQ_INSTR0_INSTR_MASK)
2906 #define SEI_CTRL_IRQ_INSTR0_INSTR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INSTR0_INSTR_MASK) >> SEI_CTRL_IRQ_INSTR0_INSTR_SHIFT)
2907 
2908 /* Bitfield definition for register of struct array CTRL: INSTR1 */
2909 /*
2910  * INSTR (RW)
2911  *
2912  * Match instruction 1
2913  */
2914 #define SEI_CTRL_IRQ_INSTR1_INSTR_MASK (0xFFFFFFFFUL)
2915 #define SEI_CTRL_IRQ_INSTR1_INSTR_SHIFT (0U)
2916 #define SEI_CTRL_IRQ_INSTR1_INSTR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INSTR1_INSTR_SHIFT) & SEI_CTRL_IRQ_INSTR1_INSTR_MASK)
2917 #define SEI_CTRL_IRQ_INSTR1_INSTR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INSTR1_INSTR_MASK) >> SEI_CTRL_IRQ_INSTR1_INSTR_SHIFT)
2918 
2919 /* Bitfield definition for register of struct array CTRL: DMA_EN */
2920 /*
2921  * TRG_ERR3 (RW)
2922  *
2923  * Trigger3 failed
2924  */
2925 #define SEI_CTRL_DMA_EN_TRG_ERR3_MASK (0x80000000UL)
2926 #define SEI_CTRL_DMA_EN_TRG_ERR3_SHIFT (31U)
2927 #define SEI_CTRL_DMA_EN_TRG_ERR3_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRG_ERR3_SHIFT) & SEI_CTRL_DMA_EN_TRG_ERR3_MASK)
2928 #define SEI_CTRL_DMA_EN_TRG_ERR3_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRG_ERR3_MASK) >> SEI_CTRL_DMA_EN_TRG_ERR3_SHIFT)
2929 
2930 /*
2931  * TRG_ERR2 (RW)
2932  *
2933  * Trigger2 failed
2934  */
2935 #define SEI_CTRL_DMA_EN_TRG_ERR2_MASK (0x40000000UL)
2936 #define SEI_CTRL_DMA_EN_TRG_ERR2_SHIFT (30U)
2937 #define SEI_CTRL_DMA_EN_TRG_ERR2_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRG_ERR2_SHIFT) & SEI_CTRL_DMA_EN_TRG_ERR2_MASK)
2938 #define SEI_CTRL_DMA_EN_TRG_ERR2_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRG_ERR2_MASK) >> SEI_CTRL_DMA_EN_TRG_ERR2_SHIFT)
2939 
2940 /*
2941  * TRG_ERR1 (RW)
2942  *
2943  * Trigger1 failed
2944  */
2945 #define SEI_CTRL_DMA_EN_TRG_ERR1_MASK (0x20000000UL)
2946 #define SEI_CTRL_DMA_EN_TRG_ERR1_SHIFT (29U)
2947 #define SEI_CTRL_DMA_EN_TRG_ERR1_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRG_ERR1_SHIFT) & SEI_CTRL_DMA_EN_TRG_ERR1_MASK)
2948 #define SEI_CTRL_DMA_EN_TRG_ERR1_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRG_ERR1_MASK) >> SEI_CTRL_DMA_EN_TRG_ERR1_SHIFT)
2949 
2950 /*
2951  * TRG_ERR0 (RW)
2952  *
2953  * Trigger0 failed
2954  */
2955 #define SEI_CTRL_DMA_EN_TRG_ERR0_MASK (0x10000000UL)
2956 #define SEI_CTRL_DMA_EN_TRG_ERR0_SHIFT (28U)
2957 #define SEI_CTRL_DMA_EN_TRG_ERR0_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRG_ERR0_SHIFT) & SEI_CTRL_DMA_EN_TRG_ERR0_MASK)
2958 #define SEI_CTRL_DMA_EN_TRG_ERR0_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRG_ERR0_MASK) >> SEI_CTRL_DMA_EN_TRG_ERR0_SHIFT)
2959 
2960 /*
2961  * TRIGER3 (RW)
2962  *
2963  * Trigger3
2964  */
2965 #define SEI_CTRL_DMA_EN_TRIGER3_MASK (0x8000000UL)
2966 #define SEI_CTRL_DMA_EN_TRIGER3_SHIFT (27U)
2967 #define SEI_CTRL_DMA_EN_TRIGER3_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRIGER3_SHIFT) & SEI_CTRL_DMA_EN_TRIGER3_MASK)
2968 #define SEI_CTRL_DMA_EN_TRIGER3_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRIGER3_MASK) >> SEI_CTRL_DMA_EN_TRIGER3_SHIFT)
2969 
2970 /*
2971  * TRIGER2 (RW)
2972  *
2973  * Trigger2
2974  */
2975 #define SEI_CTRL_DMA_EN_TRIGER2_MASK (0x4000000UL)
2976 #define SEI_CTRL_DMA_EN_TRIGER2_SHIFT (26U)
2977 #define SEI_CTRL_DMA_EN_TRIGER2_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRIGER2_SHIFT) & SEI_CTRL_DMA_EN_TRIGER2_MASK)
2978 #define SEI_CTRL_DMA_EN_TRIGER2_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRIGER2_MASK) >> SEI_CTRL_DMA_EN_TRIGER2_SHIFT)
2979 
2980 /*
2981  * TRIGER1 (RW)
2982  *
2983  * Trigger1
2984  */
2985 #define SEI_CTRL_DMA_EN_TRIGER1_MASK (0x2000000UL)
2986 #define SEI_CTRL_DMA_EN_TRIGER1_SHIFT (25U)
2987 #define SEI_CTRL_DMA_EN_TRIGER1_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRIGER1_SHIFT) & SEI_CTRL_DMA_EN_TRIGER1_MASK)
2988 #define SEI_CTRL_DMA_EN_TRIGER1_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRIGER1_MASK) >> SEI_CTRL_DMA_EN_TRIGER1_SHIFT)
2989 
2990 /*
2991  * TRIGER0 (RW)
2992  *
2993  * Trigger0
2994  */
2995 #define SEI_CTRL_DMA_EN_TRIGER0_MASK (0x1000000UL)
2996 #define SEI_CTRL_DMA_EN_TRIGER0_SHIFT (24U)
2997 #define SEI_CTRL_DMA_EN_TRIGER0_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRIGER0_SHIFT) & SEI_CTRL_DMA_EN_TRIGER0_MASK)
2998 #define SEI_CTRL_DMA_EN_TRIGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRIGER0_MASK) >> SEI_CTRL_DMA_EN_TRIGER0_SHIFT)
2999 
3000 /*
3001  * SMP_ERR (RW)
3002  *
3003  * Sample error
3004  */
3005 #define SEI_CTRL_DMA_EN_SMP_ERR_MASK (0x100000UL)
3006 #define SEI_CTRL_DMA_EN_SMP_ERR_SHIFT (20U)
3007 #define SEI_CTRL_DMA_EN_SMP_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_SMP_ERR_SHIFT) & SEI_CTRL_DMA_EN_SMP_ERR_MASK)
3008 #define SEI_CTRL_DMA_EN_SMP_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_SMP_ERR_MASK) >> SEI_CTRL_DMA_EN_SMP_ERR_SHIFT)
3009 
3010 /*
3011  * LATCH3 (RW)
3012  *
3013  * Latch3
3014  */
3015 #define SEI_CTRL_DMA_EN_LATCH3_MASK (0x80000UL)
3016 #define SEI_CTRL_DMA_EN_LATCH3_SHIFT (19U)
3017 #define SEI_CTRL_DMA_EN_LATCH3_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_LATCH3_SHIFT) & SEI_CTRL_DMA_EN_LATCH3_MASK)
3018 #define SEI_CTRL_DMA_EN_LATCH3_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_LATCH3_MASK) >> SEI_CTRL_DMA_EN_LATCH3_SHIFT)
3019 
3020 /*
3021  * LATCH2 (RW)
3022  *
3023  * Latch2
3024  */
3025 #define SEI_CTRL_DMA_EN_LATCH2_MASK (0x40000UL)
3026 #define SEI_CTRL_DMA_EN_LATCH2_SHIFT (18U)
3027 #define SEI_CTRL_DMA_EN_LATCH2_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_LATCH2_SHIFT) & SEI_CTRL_DMA_EN_LATCH2_MASK)
3028 #define SEI_CTRL_DMA_EN_LATCH2_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_LATCH2_MASK) >> SEI_CTRL_DMA_EN_LATCH2_SHIFT)
3029 
3030 /*
3031  * LATCH1 (RW)
3032  *
3033  * Latch1
3034  */
3035 #define SEI_CTRL_DMA_EN_LATCH1_MASK (0x20000UL)
3036 #define SEI_CTRL_DMA_EN_LATCH1_SHIFT (17U)
3037 #define SEI_CTRL_DMA_EN_LATCH1_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_LATCH1_SHIFT) & SEI_CTRL_DMA_EN_LATCH1_MASK)
3038 #define SEI_CTRL_DMA_EN_LATCH1_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_LATCH1_MASK) >> SEI_CTRL_DMA_EN_LATCH1_SHIFT)
3039 
3040 /*
3041  * LATCH0 (RW)
3042  *
3043  * Latch0
3044  */
3045 #define SEI_CTRL_DMA_EN_LATCH0_MASK (0x10000UL)
3046 #define SEI_CTRL_DMA_EN_LATCH0_SHIFT (16U)
3047 #define SEI_CTRL_DMA_EN_LATCH0_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_LATCH0_SHIFT) & SEI_CTRL_DMA_EN_LATCH0_MASK)
3048 #define SEI_CTRL_DMA_EN_LATCH0_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_LATCH0_MASK) >> SEI_CTRL_DMA_EN_LATCH0_SHIFT)
3049 
3050 /*
3051  * TIMEOUT (RW)
3052  *
3053  * Timeout
3054  */
3055 #define SEI_CTRL_DMA_EN_TIMEOUT_MASK (0x2000U)
3056 #define SEI_CTRL_DMA_EN_TIMEOUT_SHIFT (13U)
3057 #define SEI_CTRL_DMA_EN_TIMEOUT_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TIMEOUT_SHIFT) & SEI_CTRL_DMA_EN_TIMEOUT_MASK)
3058 #define SEI_CTRL_DMA_EN_TIMEOUT_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TIMEOUT_MASK) >> SEI_CTRL_DMA_EN_TIMEOUT_SHIFT)
3059 
3060 /*
3061  * TRX_ERR (RW)
3062  *
3063  * Transfer error
3064  */
3065 #define SEI_CTRL_DMA_EN_TRX_ERR_MASK (0x1000U)
3066 #define SEI_CTRL_DMA_EN_TRX_ERR_SHIFT (12U)
3067 #define SEI_CTRL_DMA_EN_TRX_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRX_ERR_SHIFT) & SEI_CTRL_DMA_EN_TRX_ERR_MASK)
3068 #define SEI_CTRL_DMA_EN_TRX_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRX_ERR_MASK) >> SEI_CTRL_DMA_EN_TRX_ERR_SHIFT)
3069 
3070 /*
3071  * INSTR1_END (RW)
3072  *
3073  * Instruction 1 end
3074  */
3075 #define SEI_CTRL_DMA_EN_INSTR1_END_MASK (0x800U)
3076 #define SEI_CTRL_DMA_EN_INSTR1_END_SHIFT (11U)
3077 #define SEI_CTRL_DMA_EN_INSTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_INSTR1_END_SHIFT) & SEI_CTRL_DMA_EN_INSTR1_END_MASK)
3078 #define SEI_CTRL_DMA_EN_INSTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_INSTR1_END_MASK) >> SEI_CTRL_DMA_EN_INSTR1_END_SHIFT)
3079 
3080 /*
3081  * INSTR0_END (RW)
3082  *
3083  * Instruction 0 end
3084  */
3085 #define SEI_CTRL_DMA_EN_INSTR0_END_MASK (0x400U)
3086 #define SEI_CTRL_DMA_EN_INSTR0_END_SHIFT (10U)
3087 #define SEI_CTRL_DMA_EN_INSTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_INSTR0_END_SHIFT) & SEI_CTRL_DMA_EN_INSTR0_END_MASK)
3088 #define SEI_CTRL_DMA_EN_INSTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_INSTR0_END_MASK) >> SEI_CTRL_DMA_EN_INSTR0_END_SHIFT)
3089 
3090 /*
3091  * PTR1_END (RW)
3092  *
3093  * Pointer 1 end
3094  */
3095 #define SEI_CTRL_DMA_EN_PTR1_END_MASK (0x200U)
3096 #define SEI_CTRL_DMA_EN_PTR1_END_SHIFT (9U)
3097 #define SEI_CTRL_DMA_EN_PTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_PTR1_END_SHIFT) & SEI_CTRL_DMA_EN_PTR1_END_MASK)
3098 #define SEI_CTRL_DMA_EN_PTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_PTR1_END_MASK) >> SEI_CTRL_DMA_EN_PTR1_END_SHIFT)
3099 
3100 /*
3101  * PTR0_END (RW)
3102  *
3103  * Pointer 0 end
3104  */
3105 #define SEI_CTRL_DMA_EN_PTR0_END_MASK (0x100U)
3106 #define SEI_CTRL_DMA_EN_PTR0_END_SHIFT (8U)
3107 #define SEI_CTRL_DMA_EN_PTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_PTR0_END_SHIFT) & SEI_CTRL_DMA_EN_PTR0_END_MASK)
3108 #define SEI_CTRL_DMA_EN_PTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_PTR0_END_MASK) >> SEI_CTRL_DMA_EN_PTR0_END_SHIFT)
3109 
3110 /*
3111  * INSTR1_ST (RW)
3112  *
3113  * Instruction 1 start
3114  */
3115 #define SEI_CTRL_DMA_EN_INSTR1_ST_MASK (0x80U)
3116 #define SEI_CTRL_DMA_EN_INSTR1_ST_SHIFT (7U)
3117 #define SEI_CTRL_DMA_EN_INSTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_INSTR1_ST_SHIFT) & SEI_CTRL_DMA_EN_INSTR1_ST_MASK)
3118 #define SEI_CTRL_DMA_EN_INSTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_INSTR1_ST_MASK) >> SEI_CTRL_DMA_EN_INSTR1_ST_SHIFT)
3119 
3120 /*
3121  * INSTR0_ST (RW)
3122  *
3123  * Instruction 0 start
3124  */
3125 #define SEI_CTRL_DMA_EN_INSTR0_ST_MASK (0x40U)
3126 #define SEI_CTRL_DMA_EN_INSTR0_ST_SHIFT (6U)
3127 #define SEI_CTRL_DMA_EN_INSTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_INSTR0_ST_SHIFT) & SEI_CTRL_DMA_EN_INSTR0_ST_MASK)
3128 #define SEI_CTRL_DMA_EN_INSTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_INSTR0_ST_MASK) >> SEI_CTRL_DMA_EN_INSTR0_ST_SHIFT)
3129 
3130 /*
3131  * PTR1_ST (RW)
3132  *
3133  * Pointer 1 start
3134  */
3135 #define SEI_CTRL_DMA_EN_PTR1_ST_MASK (0x20U)
3136 #define SEI_CTRL_DMA_EN_PTR1_ST_SHIFT (5U)
3137 #define SEI_CTRL_DMA_EN_PTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_PTR1_ST_SHIFT) & SEI_CTRL_DMA_EN_PTR1_ST_MASK)
3138 #define SEI_CTRL_DMA_EN_PTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_PTR1_ST_MASK) >> SEI_CTRL_DMA_EN_PTR1_ST_SHIFT)
3139 
3140 /*
3141  * PTR0_ST (RW)
3142  *
3143  * Pointer 0 start
3144  */
3145 #define SEI_CTRL_DMA_EN_PTR0_ST_MASK (0x10U)
3146 #define SEI_CTRL_DMA_EN_PTR0_ST_SHIFT (4U)
3147 #define SEI_CTRL_DMA_EN_PTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_PTR0_ST_SHIFT) & SEI_CTRL_DMA_EN_PTR0_ST_MASK)
3148 #define SEI_CTRL_DMA_EN_PTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_PTR0_ST_MASK) >> SEI_CTRL_DMA_EN_PTR0_ST_SHIFT)
3149 
3150 /*
3151  * WDOG (RW)
3152  *
3153  * Watch dog
3154  */
3155 #define SEI_CTRL_DMA_EN_WDOG_MASK (0x4U)
3156 #define SEI_CTRL_DMA_EN_WDOG_SHIFT (2U)
3157 #define SEI_CTRL_DMA_EN_WDOG_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_WDOG_SHIFT) & SEI_CTRL_DMA_EN_WDOG_MASK)
3158 #define SEI_CTRL_DMA_EN_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_WDOG_MASK) >> SEI_CTRL_DMA_EN_WDOG_SHIFT)
3159 
3160 /*
3161  * EXCEPT (RW)
3162  *
3163  * Exception
3164  */
3165 #define SEI_CTRL_DMA_EN_EXCEPT_MASK (0x2U)
3166 #define SEI_CTRL_DMA_EN_EXCEPT_SHIFT (1U)
3167 #define SEI_CTRL_DMA_EN_EXCEPT_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_EXCEPT_SHIFT) & SEI_CTRL_DMA_EN_EXCEPT_MASK)
3168 #define SEI_CTRL_DMA_EN_EXCEPT_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_EXCEPT_MASK) >> SEI_CTRL_DMA_EN_EXCEPT_SHIFT)
3169 
3170 /*
3171  * STALL (RW)
3172  *
3173  * Stall
3174  */
3175 #define SEI_CTRL_DMA_EN_STALL_MASK (0x1U)
3176 #define SEI_CTRL_DMA_EN_STALL_SHIFT (0U)
3177 #define SEI_CTRL_DMA_EN_STALL_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_STALL_SHIFT) & SEI_CTRL_DMA_EN_STALL_MASK)
3178 #define SEI_CTRL_DMA_EN_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_STALL_MASK) >> SEI_CTRL_DMA_EN_STALL_SHIFT)
3179 
3180 /* Bitfield definition for register array: INSTR */
3181 /*
3182  * OP (RW)
3183  *
3184  * operation
3185  * 0: halt
3186  * 1: jump
3187  * 2: send with timeout check
3188  * 3: send without timout check
3189  * 4: wait with timeout check
3190  * 5: wait without timout check
3191  * 6: receive with timeout check
3192  * 7: receive without timout check
3193  */
3194 #define SEI_INSTR_OP_MASK (0x1C000000UL)
3195 #define SEI_INSTR_OP_SHIFT (26U)
3196 #define SEI_INSTR_OP_SET(x) (((uint32_t)(x) << SEI_INSTR_OP_SHIFT) & SEI_INSTR_OP_MASK)
3197 #define SEI_INSTR_OP_GET(x) (((uint32_t)(x) & SEI_INSTR_OP_MASK) >> SEI_INSTR_OP_SHIFT)
3198 
3199 /*
3200  * CK (RW)
3201  *
3202  * clock state configure
3203  * a. In synchronous master mode:
3204  * 0: low
3205  * 1: rise-fall
3206  * 2: fall-rise
3207  * 3: high
3208  * b. In synchronous slave mode:
3209  * 0：Use TX_POINT and RX_POINT as the timing for data transmission and reception. Disable the TIMEOUT function in the communication protocol( this is not WDG).
3210  * 1：Switch the timing for data transmission and reception (e.g., switching edges for receive/transmit in an EnDat Encoder communication cycle). Disable the TIMEOUT function in the communication protocol.
3211  * 2：Use TX_POINT and RX_POINT as the timing for data transmission and receptionï¼›Enable the TIMEOUT function in the communication protocol.
3212  * 3：Switch the timing for data transmission and reception. Enable the TIMEOUT function in the communication protocol.
3213  * c. In asynchronous mode: please keep 0.
3214  */
3215 #define SEI_INSTR_CK_MASK (0x3000000UL)
3216 #define SEI_INSTR_CK_SHIFT (24U)
3217 #define SEI_INSTR_CK_SET(x) (((uint32_t)(x) << SEI_INSTR_CK_SHIFT) & SEI_INSTR_CK_MASK)
3218 #define SEI_INSTR_CK_GET(x) (((uint32_t)(x) & SEI_INSTR_CK_MASK) >> SEI_INSTR_CK_SHIFT)
3219 
3220 /*
3221  * CRC (RW)
3222  *
3223  * CRC register
3224  * 0: don't calculate CRC
3225  * 1: do not set this value
3226  * 2: data register 2
3227  * 3: data register 3
3228  * ...
3229  * 29: data register 29
3230  * 30: do not set this value
3231  * 31: do not set this value
3232  */
3233 #define SEI_INSTR_CRC_MASK (0x1F0000UL)
3234 #define SEI_INSTR_CRC_SHIFT (16U)
3235 #define SEI_INSTR_CRC_SET(x) (((uint32_t)(x) << SEI_INSTR_CRC_SHIFT) & SEI_INSTR_CRC_MASK)
3236 #define SEI_INSTR_CRC_GET(x) (((uint32_t)(x) & SEI_INSTR_CRC_MASK) >> SEI_INSTR_CRC_SHIFT)
3237 
3238 /*
3239  * DAT (RW)
3240  *
3241  * DATA register
3242  * 0: ignore data
3243  * 1: command
3244  * 2: data register 2
3245  * 3: data register 3
3246  * ...
3247  * 29: data register 29
3248  * 30: value 0 when send, wait 0 in receive
3249  * 31: value1 when send, wait 1 in receive
3250  */
3251 #define SEI_INSTR_DAT_MASK (0x1F00U)
3252 #define SEI_INSTR_DAT_SHIFT (8U)
3253 #define SEI_INSTR_DAT_SET(x) (((uint32_t)(x) << SEI_INSTR_DAT_SHIFT) & SEI_INSTR_DAT_MASK)
3254 #define SEI_INSTR_DAT_GET(x) (((uint32_t)(x) & SEI_INSTR_DAT_MASK) >> SEI_INSTR_DAT_SHIFT)
3255 
3256 /*
3257  * OPR (RW)
3258  *
3259  * a. When OP is 0, this area is the halt time in baudrate, 0 represents infinite time.
3260  * b. When OP is 1, this area is the the pointer to the command table.
3261  * OPR[4]=1, OPR[3:0] value is CMD_TABLE instruct pointer;
3262  * OPR[4]=0, OPR[3:0]=0 is INIT_POINTER;
3263  * OPR[4]=0, OPR[3:0]=1 is WDG_POINTER.
3264  * c. When OP is 2-7, this area is the data length as fellow:
3265  * 0: 1 bit
3266  * 1: 2 bit
3267  * ...
3268  * 31: 32 bit
3269  */
3270 #define SEI_INSTR_OPR_MASK (0x1FU)
3271 #define SEI_INSTR_OPR_SHIFT (0U)
3272 #define SEI_INSTR_OPR_SET(x) (((uint32_t)(x) << SEI_INSTR_OPR_SHIFT) & SEI_INSTR_OPR_MASK)
3273 #define SEI_INSTR_OPR_GET(x) (((uint32_t)(x) & SEI_INSTR_OPR_MASK) >> SEI_INSTR_OPR_SHIFT)
3274 
3275 /* Bitfield definition for register of struct array DAT: MODE */
3276 /*
3277  * CRC_LEN (RW)
3278  *
3279  * CRC length
3280  * 0: 1 bit
3281  * 1: 2 bit
3282  * ...
3283  * 31: 32 bit
3284  */
3285 #define SEI_DAT_MODE_CRC_LEN_MASK (0x1F000000UL)
3286 #define SEI_DAT_MODE_CRC_LEN_SHIFT (24U)
3287 #define SEI_DAT_MODE_CRC_LEN_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_CRC_LEN_SHIFT) & SEI_DAT_MODE_CRC_LEN_MASK)
3288 #define SEI_DAT_MODE_CRC_LEN_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_CRC_LEN_MASK) >> SEI_DAT_MODE_CRC_LEN_SHIFT)
3289 
3290 /*
3291  * WLEN (RW)
3292  *
3293  * word length
3294  * 0: 1 bit
3295  * 1: 2 bit
3296  * ...
3297  * 31: 32 bit
3298  */
3299 #define SEI_DAT_MODE_WLEN_MASK (0x1F0000UL)
3300 #define SEI_DAT_MODE_WLEN_SHIFT (16U)
3301 #define SEI_DAT_MODE_WLEN_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_WLEN_SHIFT) & SEI_DAT_MODE_WLEN_MASK)
3302 #define SEI_DAT_MODE_WLEN_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_WLEN_MASK) >> SEI_DAT_MODE_WLEN_SHIFT)
3303 
3304 /*
3305  * CRC_SHIFT (RW)
3306  *
3307  * CRC shift mode, this mode is used to perform repeat code check
3308  * 0: CRC
3309  * 1: shift mode
3310  */
3311 #define SEI_DAT_MODE_CRC_SHIFT_MASK (0x2000U)
3312 #define SEI_DAT_MODE_CRC_SHIFT_SHIFT (13U)
3313 #define SEI_DAT_MODE_CRC_SHIFT_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_CRC_SHIFT_SHIFT) & SEI_DAT_MODE_CRC_SHIFT_MASK)
3314 #define SEI_DAT_MODE_CRC_SHIFT_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_CRC_SHIFT_MASK) >> SEI_DAT_MODE_CRC_SHIFT_SHIFT)
3315 
3316 /*
3317  * CRC_INV (RW)
3318  *
3319  * CRC invert
3320  * 0: use CRC
3321  * 1: use inverted CRC
3322  */
3323 #define SEI_DAT_MODE_CRC_INV_MASK (0x1000U)
3324 #define SEI_DAT_MODE_CRC_INV_SHIFT (12U)
3325 #define SEI_DAT_MODE_CRC_INV_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_CRC_INV_SHIFT) & SEI_DAT_MODE_CRC_INV_MASK)
3326 #define SEI_DAT_MODE_CRC_INV_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_CRC_INV_MASK) >> SEI_DAT_MODE_CRC_INV_SHIFT)
3327 
3328 /*
3329  * WORDER (RW)
3330  *
3331  * word order
3332  * 0: sample as bit order
3333  * 1: different from bit order
3334  */
3335 #define SEI_DAT_MODE_WORDER_MASK (0x800U)
3336 #define SEI_DAT_MODE_WORDER_SHIFT (11U)
3337 #define SEI_DAT_MODE_WORDER_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_WORDER_SHIFT) & SEI_DAT_MODE_WORDER_MASK)
3338 #define SEI_DAT_MODE_WORDER_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_WORDER_MASK) >> SEI_DAT_MODE_WORDER_SHIFT)
3339 
3340 /*
3341  * BORDER (RW)
3342  *
3343  * bit order
3344  * 0: LSB first
3345  * 1: MSB first
3346  */
3347 #define SEI_DAT_MODE_BORDER_MASK (0x400U)
3348 #define SEI_DAT_MODE_BORDER_SHIFT (10U)
3349 #define SEI_DAT_MODE_BORDER_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_BORDER_SHIFT) & SEI_DAT_MODE_BORDER_MASK)
3350 #define SEI_DAT_MODE_BORDER_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_BORDER_MASK) >> SEI_DAT_MODE_BORDER_SHIFT)
3351 
3352 /*
3353  * SIGNED (RW)
3354  *
3355  * Signed
3356  * 0: unsigned value
3357  * 1: signed value
3358  */
3359 #define SEI_DAT_MODE_SIGNED_MASK (0x200U)
3360 #define SEI_DAT_MODE_SIGNED_SHIFT (9U)
3361 #define SEI_DAT_MODE_SIGNED_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_SIGNED_SHIFT) & SEI_DAT_MODE_SIGNED_MASK)
3362 #define SEI_DAT_MODE_SIGNED_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_SIGNED_MASK) >> SEI_DAT_MODE_SIGNED_SHIFT)
3363 
3364 /*
3365  * REWIND (RW)
3366  *
3367  * Write 1 to rewind read/write pointer, this is a self clear bit
3368  */
3369 #define SEI_DAT_MODE_REWIND_MASK (0x100U)
3370 #define SEI_DAT_MODE_REWIND_SHIFT (8U)
3371 #define SEI_DAT_MODE_REWIND_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_REWIND_SHIFT) & SEI_DAT_MODE_REWIND_MASK)
3372 #define SEI_DAT_MODE_REWIND_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_REWIND_MASK) >> SEI_DAT_MODE_REWIND_SHIFT)
3373 
3374 /*
3375  * MODE (RW)
3376  *
3377  * Data mode
3378  * 0: data mode
3379  * 1: check mode
3380  * 2: CRC mode
3381  */
3382 #define SEI_DAT_MODE_MODE_MASK (0x3U)
3383 #define SEI_DAT_MODE_MODE_SHIFT (0U)
3384 #define SEI_DAT_MODE_MODE_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_MODE_SHIFT) & SEI_DAT_MODE_MODE_MASK)
3385 #define SEI_DAT_MODE_MODE_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_MODE_MASK) >> SEI_DAT_MODE_MODE_SHIFT)
3386 
3387 /* Bitfield definition for register of struct array DAT: IDX */
3388 /*
3389  * LAST_BIT (RW)
3390  *
3391  * Last bit index for tranceive
3392  */
3393 #define SEI_DAT_IDX_LAST_BIT_MASK (0x1F000000UL)
3394 #define SEI_DAT_IDX_LAST_BIT_SHIFT (24U)
3395 #define SEI_DAT_IDX_LAST_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_LAST_BIT_SHIFT) & SEI_DAT_IDX_LAST_BIT_MASK)
3396 #define SEI_DAT_IDX_LAST_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_LAST_BIT_MASK) >> SEI_DAT_IDX_LAST_BIT_SHIFT)
3397 
3398 /*
3399  * FIRST_BIT (RW)
3400  *
3401  * First bit index for tranceive
3402  */
3403 #define SEI_DAT_IDX_FIRST_BIT_MASK (0x1F0000UL)
3404 #define SEI_DAT_IDX_FIRST_BIT_SHIFT (16U)
3405 #define SEI_DAT_IDX_FIRST_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_FIRST_BIT_SHIFT) & SEI_DAT_IDX_FIRST_BIT_MASK)
3406 #define SEI_DAT_IDX_FIRST_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_FIRST_BIT_MASK) >> SEI_DAT_IDX_FIRST_BIT_SHIFT)
3407 
3408 /*
3409  * MAX_BIT (RW)
3410  *
3411  * Highest bit index
3412  */
3413 #define SEI_DAT_IDX_MAX_BIT_MASK (0x1F00U)
3414 #define SEI_DAT_IDX_MAX_BIT_SHIFT (8U)
3415 #define SEI_DAT_IDX_MAX_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_MAX_BIT_SHIFT) & SEI_DAT_IDX_MAX_BIT_MASK)
3416 #define SEI_DAT_IDX_MAX_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_MAX_BIT_MASK) >> SEI_DAT_IDX_MAX_BIT_SHIFT)
3417 
3418 /*
3419  * MIN_BIT (RW)
3420  *
3421  * Lowest bit index
3422  */
3423 #define SEI_DAT_IDX_MIN_BIT_MASK (0x1FU)
3424 #define SEI_DAT_IDX_MIN_BIT_SHIFT (0U)
3425 #define SEI_DAT_IDX_MIN_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_MIN_BIT_SHIFT) & SEI_DAT_IDX_MIN_BIT_MASK)
3426 #define SEI_DAT_IDX_MIN_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_MIN_BIT_MASK) >> SEI_DAT_IDX_MIN_BIT_SHIFT)
3427 
3428 /* Bitfield definition for register of struct array DAT: GOLD */
3429 /*
3430  * GOLD_VALUE (RW)
3431  *
3432  * Gold value for check mode
3433  */
3434 #define SEI_DAT_GOLD_GOLD_VALUE_MASK (0xFFFFFFFFUL)
3435 #define SEI_DAT_GOLD_GOLD_VALUE_SHIFT (0U)
3436 #define SEI_DAT_GOLD_GOLD_VALUE_SET(x) (((uint32_t)(x) << SEI_DAT_GOLD_GOLD_VALUE_SHIFT) & SEI_DAT_GOLD_GOLD_VALUE_MASK)
3437 #define SEI_DAT_GOLD_GOLD_VALUE_GET(x) (((uint32_t)(x) & SEI_DAT_GOLD_GOLD_VALUE_MASK) >> SEI_DAT_GOLD_GOLD_VALUE_SHIFT)
3438 
3439 /* Bitfield definition for register of struct array DAT: CRCINIT */
3440 /*
3441  * CRC_INIT (RW)
3442  *
3443  * CRC initial value
3444  */
3445 #define SEI_DAT_CRCINIT_CRC_INIT_MASK (0xFFFFFFFFUL)
3446 #define SEI_DAT_CRCINIT_CRC_INIT_SHIFT (0U)
3447 #define SEI_DAT_CRCINIT_CRC_INIT_SET(x) (((uint32_t)(x) << SEI_DAT_CRCINIT_CRC_INIT_SHIFT) & SEI_DAT_CRCINIT_CRC_INIT_MASK)
3448 #define SEI_DAT_CRCINIT_CRC_INIT_GET(x) (((uint32_t)(x) & SEI_DAT_CRCINIT_CRC_INIT_MASK) >> SEI_DAT_CRCINIT_CRC_INIT_SHIFT)
3449 
3450 /* Bitfield definition for register of struct array DAT: CRCPOLY */
3451 /*
3452  * CRC_POLY (RW)
3453  *
3454  * CRC polymonial
3455  */
3456 #define SEI_DAT_CRCPOLY_CRC_POLY_MASK (0xFFFFFFFFUL)
3457 #define SEI_DAT_CRCPOLY_CRC_POLY_SHIFT (0U)
3458 #define SEI_DAT_CRCPOLY_CRC_POLY_SET(x) (((uint32_t)(x) << SEI_DAT_CRCPOLY_CRC_POLY_SHIFT) & SEI_DAT_CRCPOLY_CRC_POLY_MASK)
3459 #define SEI_DAT_CRCPOLY_CRC_POLY_GET(x) (((uint32_t)(x) & SEI_DAT_CRCPOLY_CRC_POLY_MASK) >> SEI_DAT_CRCPOLY_CRC_POLY_SHIFT)
3460 
3461 /* Bitfield definition for register of struct array DAT: DATA */
3462 /*
3463  * DATA (RW)
3464  *
3465  * DATA
3466  */
3467 #define SEI_DAT_DATA_DATA_MASK (0xFFFFFFFFUL)
3468 #define SEI_DAT_DATA_DATA_SHIFT (0U)
3469 #define SEI_DAT_DATA_DATA_SET(x) (((uint32_t)(x) << SEI_DAT_DATA_DATA_SHIFT) & SEI_DAT_DATA_DATA_MASK)
3470 #define SEI_DAT_DATA_DATA_GET(x) (((uint32_t)(x) & SEI_DAT_DATA_DATA_MASK) >> SEI_DAT_DATA_DATA_SHIFT)
3471 
3472 /* Bitfield definition for register of struct array DAT: SET */
3473 /*
3474  * DATA_SET (RW)
3475  *
3476  * DATA bit set
3477  */
3478 #define SEI_DAT_SET_DATA_SET_MASK (0xFFFFFFFFUL)
3479 #define SEI_DAT_SET_DATA_SET_SHIFT (0U)
3480 #define SEI_DAT_SET_DATA_SET_SET(x) (((uint32_t)(x) << SEI_DAT_SET_DATA_SET_SHIFT) & SEI_DAT_SET_DATA_SET_MASK)
3481 #define SEI_DAT_SET_DATA_SET_GET(x) (((uint32_t)(x) & SEI_DAT_SET_DATA_SET_MASK) >> SEI_DAT_SET_DATA_SET_SHIFT)
3482 
3483 /* Bitfield definition for register of struct array DAT: CLR */
3484 /*
3485  * DATA_CLR (RW)
3486  *
3487  * DATA bit clear
3488  */
3489 #define SEI_DAT_CLR_DATA_CLR_MASK (0xFFFFFFFFUL)
3490 #define SEI_DAT_CLR_DATA_CLR_SHIFT (0U)
3491 #define SEI_DAT_CLR_DATA_CLR_SET(x) (((uint32_t)(x) << SEI_DAT_CLR_DATA_CLR_SHIFT) & SEI_DAT_CLR_DATA_CLR_MASK)
3492 #define SEI_DAT_CLR_DATA_CLR_GET(x) (((uint32_t)(x) & SEI_DAT_CLR_DATA_CLR_MASK) >> SEI_DAT_CLR_DATA_CLR_SHIFT)
3493 
3494 /* Bitfield definition for register of struct array DAT: INV */
3495 /*
3496  * DATA_INV (RW)
3497  *
3498  * DATA bit toggle
3499  */
3500 #define SEI_DAT_INV_DATA_INV_MASK (0xFFFFFFFFUL)
3501 #define SEI_DAT_INV_DATA_INV_SHIFT (0U)
3502 #define SEI_DAT_INV_DATA_INV_SET(x) (((uint32_t)(x) << SEI_DAT_INV_DATA_INV_SHIFT) & SEI_DAT_INV_DATA_INV_MASK)
3503 #define SEI_DAT_INV_DATA_INV_GET(x) (((uint32_t)(x) & SEI_DAT_INV_DATA_INV_MASK) >> SEI_DAT_INV_DATA_INV_SHIFT)
3504 
3505 /* Bitfield definition for register of struct array DAT: IN */
3506 /*
3507  * DATA_IN (RO)
3508  *
3509  * Data input
3510  */
3511 #define SEI_DAT_IN_DATA_IN_MASK (0xFFFFFFFFUL)
3512 #define SEI_DAT_IN_DATA_IN_SHIFT (0U)
3513 #define SEI_DAT_IN_DATA_IN_GET(x) (((uint32_t)(x) & SEI_DAT_IN_DATA_IN_MASK) >> SEI_DAT_IN_DATA_IN_SHIFT)
3514 
3515 /* Bitfield definition for register of struct array DAT: OUT */
3516 /*
3517  * DATA_OUT (RO)
3518  *
3519  * Data output
3520  */
3521 #define SEI_DAT_OUT_DATA_OUT_MASK (0xFFFFFFFFUL)
3522 #define SEI_DAT_OUT_DATA_OUT_SHIFT (0U)
3523 #define SEI_DAT_OUT_DATA_OUT_GET(x) (((uint32_t)(x) & SEI_DAT_OUT_DATA_OUT_MASK) >> SEI_DAT_OUT_DATA_OUT_SHIFT)
3524 
3525 /* Bitfield definition for register of struct array DAT: STS */
3526 /*
3527  * CRC_IDX (RO)
3528  *
3529  * CRC index
3530  */
3531 #define SEI_DAT_STS_CRC_IDX_MASK (0x1F000000UL)
3532 #define SEI_DAT_STS_CRC_IDX_SHIFT (24U)
3533 #define SEI_DAT_STS_CRC_IDX_GET(x) (((uint32_t)(x) & SEI_DAT_STS_CRC_IDX_MASK) >> SEI_DAT_STS_CRC_IDX_SHIFT)
3534 
3535 /*
3536  * WORD_IDX (RO)
3537  *
3538  * Word index
3539  */
3540 #define SEI_DAT_STS_WORD_IDX_MASK (0x1F0000UL)
3541 #define SEI_DAT_STS_WORD_IDX_SHIFT (16U)
3542 #define SEI_DAT_STS_WORD_IDX_GET(x) (((uint32_t)(x) & SEI_DAT_STS_WORD_IDX_MASK) >> SEI_DAT_STS_WORD_IDX_SHIFT)
3543 
3544 /*
3545  * WORD_CNT (RO)
3546  *
3547  * Word counter
3548  */
3549 #define SEI_DAT_STS_WORD_CNT_MASK (0x1F00U)
3550 #define SEI_DAT_STS_WORD_CNT_SHIFT (8U)
3551 #define SEI_DAT_STS_WORD_CNT_GET(x) (((uint32_t)(x) & SEI_DAT_STS_WORD_CNT_MASK) >> SEI_DAT_STS_WORD_CNT_SHIFT)
3552 
3553 /*
3554  * BIT_IDX (RO)
3555  *
3556  * Bit index
3557  */
3558 #define SEI_DAT_STS_BIT_IDX_MASK (0x1FU)
3559 #define SEI_DAT_STS_BIT_IDX_SHIFT (0U)
3560 #define SEI_DAT_STS_BIT_IDX_GET(x) (((uint32_t)(x) & SEI_DAT_STS_BIT_IDX_MASK) >> SEI_DAT_STS_BIT_IDX_SHIFT)
3561 
3562 
3563 
3564 /* CMD register group index macro definition */
3565 #define SEI_CTRL_TRG_TABLE_CMD_0 (0UL)
3566 #define SEI_CTRL_TRG_TABLE_CMD_1 (1UL)
3567 #define SEI_CTRL_TRG_TABLE_CMD_2 (2UL)
3568 #define SEI_CTRL_TRG_TABLE_CMD_3 (3UL)
3569 
3570 /* TIME register group index macro definition */
3571 #define SEI_CTRL_TRG_TABLE_TIME_0 (0UL)
3572 #define SEI_CTRL_TRG_TABLE_TIME_1 (1UL)
3573 #define SEI_CTRL_TRG_TABLE_TIME_2 (2UL)
3574 #define SEI_CTRL_TRG_TABLE_TIME_3 (3UL)
3575 
3576 /* CMD_TABLE register group index macro definition */
3577 #define SEI_CMD_TABLE_0 (0UL)
3578 #define SEI_CMD_TABLE_1 (1UL)
3579 #define SEI_CMD_TABLE_2 (2UL)
3580 #define SEI_CMD_TABLE_3 (3UL)
3581 #define SEI_CMD_TABLE_4 (4UL)
3582 #define SEI_CMD_TABLE_5 (5UL)
3583 #define SEI_CMD_TABLE_6 (6UL)
3584 #define SEI_CMD_TABLE_7 (7UL)
3585 
3586 /* TRAN register group index macro definition */
3587 #define SEI_CTRL_LATCH_TRAN_0_1 (0UL)
3588 #define SEI_CTRL_LATCH_TRAN_1_2 (1UL)
3589 #define SEI_CTRL_LATCH_TRAN_2_3 (2UL)
3590 #define SEI_CTRL_LATCH_TRAN_3_0 (3UL)
3591 
3592 /* LATCH register group index macro definition */
3593 #define SEI_LATCH_0 (0UL)
3594 #define SEI_LATCH_1 (1UL)
3595 #define SEI_LATCH_2 (2UL)
3596 #define SEI_LATCH_3 (3UL)
3597 
3598 /* CTRL register group index macro definition */
3599 #define SEI_CTRL_0 (0UL)
3600 #define SEI_CTRL_1 (1UL)
3601 
3602 /* INSTR register group index macro definition */
3603 #define SEI_INSTR_0 (0UL)
3604 #define SEI_INSTR_1 (1UL)
3605 #define SEI_INSTR_2 (2UL)
3606 #define SEI_INSTR_3 (3UL)
3607 #define SEI_INSTR_4 (4UL)
3608 #define SEI_INSTR_5 (5UL)
3609 #define SEI_INSTR_6 (6UL)
3610 #define SEI_INSTR_7 (7UL)
3611 #define SEI_INSTR_8 (8UL)
3612 #define SEI_INSTR_9 (9UL)
3613 #define SEI_INSTR_10 (10UL)
3614 #define SEI_INSTR_11 (11UL)
3615 #define SEI_INSTR_12 (12UL)
3616 #define SEI_INSTR_13 (13UL)
3617 #define SEI_INSTR_14 (14UL)
3618 #define SEI_INSTR_15 (15UL)
3619 #define SEI_INSTR_16 (16UL)
3620 #define SEI_INSTR_17 (17UL)
3621 #define SEI_INSTR_18 (18UL)
3622 #define SEI_INSTR_19 (19UL)
3623 #define SEI_INSTR_20 (20UL)
3624 #define SEI_INSTR_21 (21UL)
3625 #define SEI_INSTR_22 (22UL)
3626 #define SEI_INSTR_23 (23UL)
3627 #define SEI_INSTR_24 (24UL)
3628 #define SEI_INSTR_25 (25UL)
3629 #define SEI_INSTR_26 (26UL)
3630 #define SEI_INSTR_27 (27UL)
3631 #define SEI_INSTR_28 (28UL)
3632 #define SEI_INSTR_29 (29UL)
3633 #define SEI_INSTR_30 (30UL)
3634 #define SEI_INSTR_31 (31UL)
3635 #define SEI_INSTR_32 (32UL)
3636 #define SEI_INSTR_33 (33UL)
3637 #define SEI_INSTR_34 (34UL)
3638 #define SEI_INSTR_35 (35UL)
3639 #define SEI_INSTR_36 (36UL)
3640 #define SEI_INSTR_37 (37UL)
3641 #define SEI_INSTR_38 (38UL)
3642 #define SEI_INSTR_39 (39UL)
3643 #define SEI_INSTR_40 (40UL)
3644 #define SEI_INSTR_41 (41UL)
3645 #define SEI_INSTR_42 (42UL)
3646 #define SEI_INSTR_43 (43UL)
3647 #define SEI_INSTR_44 (44UL)
3648 #define SEI_INSTR_45 (45UL)
3649 #define SEI_INSTR_46 (46UL)
3650 #define SEI_INSTR_47 (47UL)
3651 #define SEI_INSTR_48 (48UL)
3652 #define SEI_INSTR_49 (49UL)
3653 #define SEI_INSTR_50 (50UL)
3654 #define SEI_INSTR_51 (51UL)
3655 #define SEI_INSTR_52 (52UL)
3656 #define SEI_INSTR_53 (53UL)
3657 #define SEI_INSTR_54 (54UL)
3658 #define SEI_INSTR_55 (55UL)
3659 #define SEI_INSTR_56 (56UL)
3660 #define SEI_INSTR_57 (57UL)
3661 #define SEI_INSTR_58 (58UL)
3662 #define SEI_INSTR_59 (59UL)
3663 #define SEI_INSTR_60 (60UL)
3664 #define SEI_INSTR_61 (61UL)
3665 #define SEI_INSTR_62 (62UL)
3666 #define SEI_INSTR_63 (63UL)
3667 #define SEI_INSTR_64 (64UL)
3668 #define SEI_INSTR_65 (65UL)
3669 #define SEI_INSTR_66 (66UL)
3670 #define SEI_INSTR_67 (67UL)
3671 #define SEI_INSTR_68 (68UL)
3672 #define SEI_INSTR_69 (69UL)
3673 #define SEI_INSTR_70 (70UL)
3674 #define SEI_INSTR_71 (71UL)
3675 #define SEI_INSTR_72 (72UL)
3676 #define SEI_INSTR_73 (73UL)
3677 #define SEI_INSTR_74 (74UL)
3678 #define SEI_INSTR_75 (75UL)
3679 #define SEI_INSTR_76 (76UL)
3680 #define SEI_INSTR_77 (77UL)
3681 #define SEI_INSTR_78 (78UL)
3682 #define SEI_INSTR_79 (79UL)
3683 #define SEI_INSTR_80 (80UL)
3684 #define SEI_INSTR_81 (81UL)
3685 #define SEI_INSTR_82 (82UL)
3686 #define SEI_INSTR_83 (83UL)
3687 #define SEI_INSTR_84 (84UL)
3688 #define SEI_INSTR_85 (85UL)
3689 #define SEI_INSTR_86 (86UL)
3690 #define SEI_INSTR_87 (87UL)
3691 #define SEI_INSTR_88 (88UL)
3692 #define SEI_INSTR_89 (89UL)
3693 #define SEI_INSTR_90 (90UL)
3694 #define SEI_INSTR_91 (91UL)
3695 #define SEI_INSTR_92 (92UL)
3696 #define SEI_INSTR_93 (93UL)
3697 #define SEI_INSTR_94 (94UL)
3698 #define SEI_INSTR_95 (95UL)
3699 #define SEI_INSTR_96 (96UL)
3700 #define SEI_INSTR_97 (97UL)
3701 #define SEI_INSTR_98 (98UL)
3702 #define SEI_INSTR_99 (99UL)
3703 #define SEI_INSTR_100 (100UL)
3704 #define SEI_INSTR_101 (101UL)
3705 #define SEI_INSTR_102 (102UL)
3706 #define SEI_INSTR_103 (103UL)
3707 #define SEI_INSTR_104 (104UL)
3708 #define SEI_INSTR_105 (105UL)
3709 #define SEI_INSTR_106 (106UL)
3710 #define SEI_INSTR_107 (107UL)
3711 #define SEI_INSTR_108 (108UL)
3712 #define SEI_INSTR_109 (109UL)
3713 #define SEI_INSTR_110 (110UL)
3714 #define SEI_INSTR_111 (111UL)
3715 #define SEI_INSTR_112 (112UL)
3716 #define SEI_INSTR_113 (113UL)
3717 #define SEI_INSTR_114 (114UL)
3718 #define SEI_INSTR_115 (115UL)
3719 #define SEI_INSTR_116 (116UL)
3720 #define SEI_INSTR_117 (117UL)
3721 #define SEI_INSTR_118 (118UL)
3722 #define SEI_INSTR_119 (119UL)
3723 #define SEI_INSTR_120 (120UL)
3724 #define SEI_INSTR_121 (121UL)
3725 #define SEI_INSTR_122 (122UL)
3726 #define SEI_INSTR_123 (123UL)
3727 #define SEI_INSTR_124 (124UL)
3728 #define SEI_INSTR_125 (125UL)
3729 #define SEI_INSTR_126 (126UL)
3730 #define SEI_INSTR_127 (127UL)
3731 
3732 /* DAT register group index macro definition */
3733 #define SEI_DAT_0 (0UL)
3734 #define SEI_DAT_1 (1UL)
3735 #define SEI_DAT_2 (2UL)
3736 #define SEI_DAT_3 (3UL)
3737 #define SEI_DAT_4 (4UL)
3738 #define SEI_DAT_5 (5UL)
3739 #define SEI_DAT_6 (6UL)
3740 #define SEI_DAT_7 (7UL)
3741 #define SEI_DAT_8 (8UL)
3742 #define SEI_DAT_9 (9UL)
3743 #define SEI_DAT_10 (10UL)
3744 #define SEI_DAT_11 (11UL)
3745 #define SEI_DAT_12 (12UL)
3746 #define SEI_DAT_13 (13UL)
3747 #define SEI_DAT_14 (14UL)
3748 #define SEI_DAT_15 (15UL)
3749 #define SEI_DAT_16 (16UL)
3750 #define SEI_DAT_17 (17UL)
3751 
3752 
3753 #endif /* HPM_SEI_H */
MIN
#define MIN(a, b)
Definition: hpm_common.h:49
MAX
#define MAX(a, b)
Definition: hpm_common.h:46
SEI_Type
Definition: hpm_sei_regs.h:12