hpm_esc_drv.h

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/*
 * Copyright (c) 2024 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
 */
 
 
#ifndef HPM_ESC_DRV_H
#define HPM_ESC_DRV_H
 
#include "hpm_common.h"
#include "hpm_esc_regs.h"
 
enum {
    status_esc_eeprom_ack_error      = MAKE_STATUS(status_group_esc, 0),           
    status_esc_eeprom_checksum_error = MAKE_STATUS(status_group_esc, 1),           
};
 
 
typedef enum {
    latch_source_from_ntm = 0,
    latch_source_from_trigger_mux = 1,
} esc_latch_source_t;
 
typedef enum {
    esc_eeprom_idle_cmd = 0, /* clear error bits */
    esc_eeprom_read_cmd = 1,
    esc_eeprom_write_cmd = 2,
    esc_eeprom_reload_cmd = 4,
} esc_eeprom_cmd_t;
 
typedef enum  {
    esc_ctrl_signal_func_alt_nmii_link0 = 0,
    esc_ctrl_signal_func_alt_nmii_link1 = 1,
    esc_ctrl_signal_func_alt_nmii_link2 = 2,
    esc_ctrl_signal_func_alt_link_act0  = 3,
    esc_ctrl_signal_func_alt_link_act1  = 4,
    esc_ctrl_signal_func_alt_link_act2  = 5,
    esc_ctrl_signal_func_alt_led_run    = 6,
    esc_ctrl_signal_func_alt_led_err    = 7,
    esc_ctrl_signal_func_alt_reset_out  = 8,
} esc_ctrl_signal_function_t;
 
/*
 * @brief ESC IRQ mask
 *
 * @note The ESC(PDI) IRQ is always enabled, and this enum is only used to control sync0/sync1 and reset irq.
 */
typedef enum {
    esc_irq_mask_none = 0,
    esc_sync0_irq_mask = ESC_GPR_CFG1_SYNC0_IRQ_EN_MASK,
    esc_sync1_irq_mask = ESC_GPR_CFG1_SYNC1_IRQ_EN_MASK,
    esc_reset_irq_mask = ESC_GPR_CFG1_RSTO_IRQ_EN_MASK,
    esc_irq_mask_all = ESC_GPR_CFG1_SYNC0_IRQ_EN_MASK | ESC_GPR_CFG1_SYNC1_IRQ_EN_MASK | ESC_GPR_CFG1_RSTO_IRQ_EN_MASK,
} esc_irq_mask_t;
 
 
typedef struct {
    bool eeprom_emulation;
    bool eeprom_size_over_16kbit;
    bool core_clock_en;
    bool phy_refclk_en;
} esc_eeprom_clock_config_t;
 
 
#ifdef __cplusplus
extern "C" {
#endif
 
static inline void esc_core_enable_clock(ESC_Type *ptr, bool enable)
{
    if (enable) {
        ptr->GPR_CFG0 |= ESC_GPR_CFG0_CLK100_EN_MASK;
    } else {
        ptr->GPR_CFG0 &= ~ESC_GPR_CFG0_CLK100_EN_MASK;
    }
}
 
static inline void esc_phy_enable_clock(ESC_Type *ptr, bool enable)
{
    if (enable) {
        ptr->PHY_CFG1 |= ESC_PHY_CFG1_REFCK_25M_OE_MASK;   
    } else {
        ptr->PHY_CFG1 &= ~ESC_PHY_CFG1_REFCK_25M_OE_MASK;   
    }
}
 
static inline void esc_config_eeprom_and_clock(ESC_Type *ptr, esc_eeprom_clock_config_t *config)
{
    uint32_t gpr_cfg0 = ptr->GPR_CFG0;
 
    if (config->eeprom_emulation) {
        gpr_cfg0 |= ESC_GPR_CFG0_EEPROM_EMU_MASK;
        gpr_cfg0 &= ~(ESC_GPR_CFG0_PROM_SIZE_MASK | ESC_GPR_CFG0_I2C_SCLK_EN_MASK);
    } else {
        gpr_cfg0 &= ~ESC_GPR_CFG0_EEPROM_EMU_MASK;
        gpr_cfg0 |= ESC_GPR_CFG0_I2C_SCLK_EN_MASK;
        if (config->eeprom_size_over_16kbit) {
            gpr_cfg0 |= ESC_GPR_CFG0_PROM_SIZE_MASK;
        } else {
            gpr_cfg0 &= ~ESC_GPR_CFG0_PROM_SIZE_MASK;
        }
    }
    ptr->GPR_CFG0 = gpr_cfg0;
    esc_core_enable_clock(ptr, config->core_clock_en);
    esc_phy_enable_clock(ptr, config->phy_refclk_en);
}
 
static inline void esc_config_ctrl_signal_function(ESC_Type *ptr, uint8_t index, esc_ctrl_signal_function_t func, bool invert)
{
    ptr->IO_CFG[index] = ESC_IO_CFG_FUNC_ALT_SET(func) | ESC_IO_CFG_INVERT_SET(invert);
}
 
static inline void esc_config_nmii_link_source(ESC_Type *ptr, bool link0_from_io, bool link1_from_io, bool link2_from_io)
{
    if (link0_from_io) {
        ptr->GPR_CFG2 |= ESC_GPR_CFG2_NMII_LINK0_FROM_IO_MASK;
    } else {
        ptr->GPR_CFG2 &= ~ESC_GPR_CFG2_NMII_LINK0_FROM_IO_MASK;
        ptr->GPR_CFG2 |= ESC_GPR_CFG2_NMII_LINK0_GPR_MASK; /* config GRP to indicate LINK0 is invalid by default */
    }
 
    if (link1_from_io) {
        ptr->GPR_CFG2 |= ESC_GPR_CFG2_NMII_LINK1_FROM_IO_MASK;
    } else {
        ptr->GPR_CFG2 &= ~ESC_GPR_CFG2_NMII_LINK1_FROM_IO_MASK;
        ptr->GPR_CFG2 |= ESC_GPR_CFG2_NMII_LINK1_GPR_MASK; /* config GRP to indicate LINK1 is invalid by default */
    }
 
    if (link2_from_io) {
        ptr->GPR_CFG2 |= ESC_GPR_CFG2_NMII_LINK2_FROM_IO_MASK;
    } else {
        ptr->GPR_CFG2 &= ~ESC_GPR_CFG2_NMII_LINK2_FROM_IO_MASK;
        ptr->GPR_CFG2 |= ESC_GPR_CFG2_NMII_LINK2_GPR_MASK; /* config GRP to indicate LINK2 is invalid by default */
    }
}
 
/* config ESC reset request source: ESC core or GRP_REG value */
static inline void esc_config_reset_source(ESC_Type *ptr, bool reset_from_ecat_core)
{
    if (reset_from_ecat_core) {
        ptr->GPR_CFG1 |= ESC_GPR_CFG1_RSTO_OVRD_ENJ_MASK;
    } else {
        ptr->GPR_CFG1 &= ~ESC_GPR_CFG1_RSTO_OVRD_ENJ_MASK;
    }
}
 
static inline void esc_pdi_reset(ESC_Type *ptr)
{
    ptr->ESC_RST_PDI = 0x52; /* R */
    ptr->ESC_RST_PDI = 0x45; /* E */
    ptr->ESC_RST_PDI = 0x53; /* S */
}
 
static inline void esc_set_phy_offset(ESC_Type *ptr, uint8_t offset)
{
    ptr->PHY_CFG0 = (ptr->PHY_CFG0 & ~ESC_PHY_CFG0_PHY_OFFSET_VAL_MASK) | (offset << ESC_PHY_CFG0_PHY_OFFSET_VAL_SHIFT);
}
 
static inline void esc_enable_pdi_access_mii_management(ESC_Type *ptr)
{
    ptr->MIIM_PDI_ACC_STAT |= ESC_MIIM_PDI_ACC_STAT_ACC_MASK;
}
 
static inline void esc_disable_pdi_access_mii_management(ESC_Type *ptr)
{
    ptr->MIIM_PDI_ACC_STAT &= ~ESC_MIIM_PDI_ACC_STAT_ACC_MASK;
}
 
hpm_stat_t esc_mdio_read(ESC_Type *ptr, uint8_t phy_addr, uint8_t reg_addr, uint16_t *data);
 
hpm_stat_t esc_mdio_write(ESC_Type *ptr, uint8_t phy_addr, uint8_t reg_addr, uint16_t data);
 
hpm_stat_t esc_check_eeprom_loading(ESC_Type *ptr);
 
static inline uint8_t esc_get_eeprom_cmd(ESC_Type *ptr)
{
    return ESC_EEPROM_CTRL_STAT_CMD_GET(ptr->EEPROM_CTRL_STAT);
}
 
static inline void esc_eeprom_emulation_ack(ESC_Type *ptr, esc_eeprom_cmd_t cmd, bool ack_err, bool crc_err)
{
    uint16_t temp = ESC_EEPROM_CTRL_STAT_CMD_SET(cmd);
    if (ack_err) {
        temp |= ESC_EEPROM_CTRL_STAT_ERR_ACK_CMD_MASK;
    }
    if (crc_err) {
        temp |= ESC_EEPROM_CTRL_STAT_CKSM_ERR_MASK;
    }
 
    ptr->EEPROM_CTRL_STAT = temp;
}
 
static inline uint32_t esc_get_eeprom_byte_address(ESC_Type *ptr)
{
    return (ptr->EEPROM_ADDR) << 1U;
}
 
static inline uint32_t esc_get_eeprom_word_address(ESC_Type *ptr)
{
    return ptr->EEPROM_ADDR;
}
 
static inline uint64_t esc_read_eeprom_data(ESC_Type *ptr)
{
    return ptr->EEPROM_DATA;
}
 
static inline void esc_write_eeprom_data(ESC_Type *ptr, uint64_t data)
{
    ptr->EEPROM_DATA = data;
}
 
static inline void esc_config_latch0_source(ESC_Type *ptr, bool latch0_from_ntm)
{
    if (latch0_from_ntm) {
        ptr->GPR_CFG1 &= ~ESC_GPR_CFG1_LATCH0_FROM_IO_MASK;
    } else {
        ptr->GPR_CFG1 |= ESC_GPR_CFG1_LATCH0_FROM_IO_MASK;
    }
}
 
static inline void esc_config_latch1_source(ESC_Type *ptr, bool latch0_from_trigmux)
{
    if (latch0_from_trigmux) {
        ptr->GPR_CFG1 &= ~ESC_GPR_CFG1_LATCH1_FROM_IO_MASK;
    } else {
        ptr->GPR_CFG1 |= ESC_GPR_CFG1_LATCH1_FROM_IO_MASK;
    }
}
 
static inline void esc_enable_irq(ESC_Type *ptr, esc_irq_mask_t irq_mask)
{
    ptr->GPR_CFG1 |= (irq_mask & esc_irq_mask_all);
}
 
static inline void esc_disable_irq(ESC_Type *ptr, esc_irq_mask_t irq_mask)
{
    ptr->GPR_CFG1 &= ~(irq_mask & esc_irq_mask_all);
}
 
#if defined(HPM_IP_FEATURE_ESC_SYNC_IRQ_MASK) && HPM_IP_FEATURE_ESC_SYNC_IRQ_MASK
static inline void esc_enable_sync_irq_to_pdi_irq(ESC_Type *ptr, bool sync0_irq, bool sync1_irq)
{
    ptr->GPR_CFG0 = (ptr->GPR_CFG0 & ~(ESC_GPR_CFG0_SYNC0_PDI_IRQEN_MASK | ESC_GPR_CFG0_SYNC1_PDI_IRQEN_MASK))
                     | (ESC_GPR_CFG0_SYNC0_PDI_IRQEN_SET(sync0_irq))
                     | (ESC_GPR_CFG0_SYNC1_PDI_IRQEN_SET(sync1_irq));
}
#endif
 
#if defined(HPM_IP_FEATURE_ESC_PORT_DIS) && HPM_IP_FEATURE_ESC_PORT_DIS
static inline void esc_change_port_description(ESC_Type *ptr, bool port0, bool port1, bool port2)
{
    ptr->GPR_CFG0 = (ptr->GPR_CFG0 & ~(ESC_GPR_CFG0_PORT0_DIS_MASK | ESC_GPR_CFG0_PORT1_DIS_MASK | ESC_GPR_CFG0_PORT2_DIS_MASK))
                     | (ESC_GPR_CFG0_PORT0_DIS_SET(port0))
                     | (ESC_GPR_CFG0_PORT1_DIS_SET(port1))
                     | (ESC_GPR_CFG0_PORT2_DIS_SET(port2));
}
#endif
 
#ifdef __cplusplus
}
#endif
#endif /* HPM_ESC_DRV_H */