HPM SDK
HPMicro Software Development Kit
hpm_eui_regs.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_EUI_H
10 #define HPM_EUI_H
11 
12 typedef struct {
13  __RW uint32_t CTRL; /* 0x0: Control Register */
14  __RW uint32_t DIV_CFG; /* 0x4: */
15  __RW uint32_t PAD_CFG; /* 0x8: */
16  __RW uint32_t POL_CFG; /* 0xC: */
17  __RW uint32_t OUT_CFG; /* 0x10: */
18  __RW uint32_t IN_CFG; /* 0x14: */
19  __R uint8_t RESERVED0[8]; /* 0x18 - 0x1F: Reserved */
20  __W uint32_t IRQ_STS; /* 0x20: */
21  __RW uint32_t IRQ_EN; /* 0x24: */
22  __R uint8_t RESERVED1[24]; /* 0x28 - 0x3F: Reserved */
23  __R uint32_t DATA_IN0; /* 0x40: */
24  __R uint32_t DATA_IN1; /* 0x44: */
25  __R uint32_t DATA_IN2; /* 0x48: */
26  __R uint32_t DATA_IN3; /* 0x4C: */
27  __R uint32_t DATA_IN4; /* 0x50: */
28  __R uint32_t DATA_IN5; /* 0x54: */
29  __R uint32_t DATA_IN6; /* 0x58: */
30  __R uint32_t DATA_IN7; /* 0x5C: */
31  __R uint8_t RESERVED2[32]; /* 0x60 - 0x7F: Reserved */
32  __RW uint32_t DAB_CTRL; /* 0x80: */
33  __R uint8_t RESERVED3[12]; /* 0x84 - 0x8F: Reserved */
34  __RW uint32_t DCD_CTRL; /* 0x90: */
35  __R uint8_t RESERVED4[12]; /* 0x94 - 0x9F: Reserved */
36  __RW uint32_t DEF_CTRL; /* 0xA0: */
37  __R uint8_t RESERVED5[12]; /* 0xA4 - 0xAF: Reserved */
38  __RW uint32_t DGH_CTRL; /* 0xB0: */
39  __R uint8_t RESERVED6[76]; /* 0xB4 - 0xFF: Reserved */
40  __RW uint32_t DA_00; /* 0x100: */
41  __RW uint32_t DA_01; /* 0x104: */
42  __R uint8_t RESERVED7[56]; /* 0x108 - 0x13F: Reserved */
43  __RW uint32_t DB_00; /* 0x140: */
44  __RW uint32_t DB_01; /* 0x144: */
45  __R uint8_t RESERVED8[56]; /* 0x148 - 0x17F: Reserved */
46  __RW uint32_t DC_00; /* 0x180: */
47  __RW uint32_t DC_01; /* 0x184: */
48  __R uint8_t RESERVED9[56]; /* 0x188 - 0x1BF: Reserved */
49  __RW uint32_t DD_00; /* 0x1C0: */
50  __RW uint32_t DD_01; /* 0x1C4: */
51  __R uint8_t RESERVED10[56]; /* 0x1C8 - 0x1FF: Reserved */
52  __RW uint32_t DE_00; /* 0x200: */
53  __RW uint32_t DE_01; /* 0x204: */
54  __R uint8_t RESERVED11[56]; /* 0x208 - 0x23F: Reserved */
55  __RW uint32_t DF_00; /* 0x240: */
56  __RW uint32_t DF_01; /* 0x244: */
57  __R uint8_t RESERVED12[56]; /* 0x248 - 0x27F: Reserved */
58  __RW uint32_t DG_00; /* 0x280: */
59  __RW uint32_t DG_01; /* 0x284: */
60  __R uint8_t RESERVED13[56]; /* 0x288 - 0x2BF: Reserved */
61  __RW uint32_t DH_00; /* 0x2C0: */
62  __RW uint32_t DH_01; /* 0x2C4: */
63 } EUI_Type;
64 
65 
66 /* Bitfield definition for register: CTRL */
67 /*
68  * CLR_OUTPUT (RW)
69  *
70  * write 1 to send 24bit 0 to data output, Auto clear after clear finishd;
71  * only can be set when clock_enable(in eut_state) is 0
72  */
73 #define EUI_CTRL_CLR_OUTPUT_MASK (0x80000000UL)
74 #define EUI_CTRL_CLR_OUTPUT_SHIFT (31U)
75 #define EUI_CTRL_CLR_OUTPUT_SET(x) (((uint32_t)(x) << EUI_CTRL_CLR_OUTPUT_SHIFT) & EUI_CTRL_CLR_OUTPUT_MASK)
76 #define EUI_CTRL_CLR_OUTPUT_GET(x) (((uint32_t)(x) & EUI_CTRL_CLR_OUTPUT_MASK) >> EUI_CTRL_CLR_OUTPUT_SHIFT)
77 
78 /*
79  * CLR_DATA_IN (WO)
80  *
81  * write 1 to clear data_in register to all 0.
82  * only can be set when clock_enable(in eut_state) is 0
83  */
84 #define EUI_CTRL_CLR_DATA_IN_MASK (0x40000000UL)
85 #define EUI_CTRL_CLR_DATA_IN_SHIFT (30U)
86 #define EUI_CTRL_CLR_DATA_IN_SET(x) (((uint32_t)(x) << EUI_CTRL_CLR_DATA_IN_SHIFT) & EUI_CTRL_CLR_DATA_IN_MASK)
87 #define EUI_CTRL_CLR_DATA_IN_GET(x) (((uint32_t)(x) & EUI_CTRL_CLR_DATA_IN_MASK) >> EUI_CTRL_CLR_DATA_IN_SHIFT)
88 
89 /*
90  * COL_LOOP_MODE (RW)
91  *
92  * 0: all configured LED on at same time in one column;
93  * 1: only one LED on in one column, need
94  */
95 #define EUI_CTRL_COL_LOOP_MODE_MASK (0x4U)
96 #define EUI_CTRL_COL_LOOP_MODE_SHIFT (2U)
97 #define EUI_CTRL_COL_LOOP_MODE_SET(x) (((uint32_t)(x) << EUI_CTRL_COL_LOOP_MODE_SHIFT) & EUI_CTRL_COL_LOOP_MODE_MASK)
98 #define EUI_CTRL_COL_LOOP_MODE_GET(x) (((uint32_t)(x) & EUI_CTRL_COL_LOOP_MODE_MASK) >> EUI_CTRL_COL_LOOP_MODE_SHIFT)
99 
100 /*
101  * DISP_MODE (RW)
102  *
103  * 0 for 8x8(8bit data,8bit select, need 2 external 595 chip, 1 for data, 1 for select)
104  * 1 for 16x4(16bit data, 4bit select, need 3 external 595 chip, 2 for data, 4bit for select,
105  * the other 4bit can be used as dedicate led control)
106  */
107 #define EUI_CTRL_DISP_MODE_MASK (0x2U)
108 #define EUI_CTRL_DISP_MODE_SHIFT (1U)
109 #define EUI_CTRL_DISP_MODE_SET(x) (((uint32_t)(x) << EUI_CTRL_DISP_MODE_SHIFT) & EUI_CTRL_DISP_MODE_MASK)
110 #define EUI_CTRL_DISP_MODE_GET(x) (((uint32_t)(x) & EUI_CTRL_DISP_MODE_MASK) >> EUI_CTRL_DISP_MODE_SHIFT)
111 
112 /*
113  * ENABLE (RW)
114  *
115  * set to start block; clr to stop(hw will finish current loop)
116  */
117 #define EUI_CTRL_ENABLE_MASK (0x1U)
118 #define EUI_CTRL_ENABLE_SHIFT (0U)
119 #define EUI_CTRL_ENABLE_SET(x) (((uint32_t)(x) << EUI_CTRL_ENABLE_SHIFT) & EUI_CTRL_ENABLE_MASK)
120 #define EUI_CTRL_ENABLE_GET(x) (((uint32_t)(x) & EUI_CTRL_ENABLE_MASK) >> EUI_CTRL_ENABLE_SHIFT)
121 
122 /* Bitfield definition for register: DIV_CFG */
123 /*
124  * CLKO_ADJ (RW)
125  *
126  * used to generate pulse signal for internal slow clock base, such as data change time.
127  * default 2 for data change 3 system clock cycles after negedge of coutput clock
128  */
129 #define EUI_DIV_CFG_CLKO_ADJ_MASK (0xF00000UL)
130 #define EUI_DIV_CFG_CLKO_ADJ_SHIFT (20U)
131 #define EUI_DIV_CFG_CLKO_ADJ_SET(x) (((uint32_t)(x) << EUI_DIV_CFG_CLKO_ADJ_SHIFT) & EUI_DIV_CFG_CLKO_ADJ_MASK)
132 #define EUI_DIV_CFG_CLKO_ADJ_GET(x) (((uint32_t)(x) & EUI_DIV_CFG_CLKO_ADJ_MASK) >> EUI_DIV_CFG_CLKO_ADJ_SHIFT)
133 
134 /*
135  * HOLD_TIME (RW)
136  *
137  * for display hold time, in unit of slot time(32 output clock cycles)
138  * shift 16 or 24 cycles in one slot time, then hold output for hold_time slots
139  * it need N*(hold_time+1) slot to display all LEDs, N is LED column select signal bits,
140  * valid value is 1 to 8 (default is 1024us in 8x8 mode, 512 us in 16x4 mode)
141  */
142 #define EUI_DIV_CFG_HOLD_TIME_MASK (0xF0000UL)
143 #define EUI_DIV_CFG_HOLD_TIME_SHIFT (16U)
144 #define EUI_DIV_CFG_HOLD_TIME_SET(x) (((uint32_t)(x) << EUI_DIV_CFG_HOLD_TIME_SHIFT) & EUI_DIV_CFG_HOLD_TIME_MASK)
145 #define EUI_DIV_CFG_HOLD_TIME_GET(x) (((uint32_t)(x) & EUI_DIV_CFG_HOLD_TIME_MASK) >> EUI_DIV_CFG_HOLD_TIME_SHIFT)
146 
147 /*
148  * CLK_DIV (RW)
149  *
150  * output clock divider of system clock.
151  * 0 for div2, 1 for div4; default 0x63 for 1MHz output clock at 200MHz system clock
152  */
153 #define EUI_DIV_CFG_CLK_DIV_MASK (0xFFFFU)
154 #define EUI_DIV_CFG_CLK_DIV_SHIFT (0U)
155 #define EUI_DIV_CFG_CLK_DIV_SET(x) (((uint32_t)(x) << EUI_DIV_CFG_CLK_DIV_SHIFT) & EUI_DIV_CFG_CLK_DIV_MASK)
156 #define EUI_DIV_CFG_CLK_DIV_GET(x) (((uint32_t)(x) & EUI_DIV_CFG_CLK_DIV_MASK) >> EUI_DIV_CFG_CLK_DIV_SHIFT)
157 
158 /* Bitfield definition for register: PAD_CFG */
159 /*
160  * FILT_LEN (RW)
161  *
162  * switch filter length, use to remove jitter. In unit of disp_time.
163  * will assert interrupt if scan input data stable for more than this time.
164  * Default 5ms in 8x8 mode
165  */
166 #define EUI_PAD_CFG_FILT_LEN_MASK (0xFFFU)
167 #define EUI_PAD_CFG_FILT_LEN_SHIFT (0U)
168 #define EUI_PAD_CFG_FILT_LEN_SET(x) (((uint32_t)(x) << EUI_PAD_CFG_FILT_LEN_SHIFT) & EUI_PAD_CFG_FILT_LEN_MASK)
169 #define EUI_PAD_CFG_FILT_LEN_GET(x) (((uint32_t)(x) & EUI_PAD_CFG_FILT_LEN_MASK) >> EUI_PAD_CFG_FILT_LEN_SHIFT)
170 
171 /* Bitfield definition for register: POL_CFG */
172 /*
173  * DI_POL (RW)
174  *
175  * polarity at pad_do_eut_in
176  */
177 #define EUI_POL_CFG_DI_POL_MASK (0x8000000UL)
178 #define EUI_POL_CFG_DI_POL_SHIFT (27U)
179 #define EUI_POL_CFG_DI_POL_SET(x) (((uint32_t)(x) << EUI_POL_CFG_DI_POL_SHIFT) & EUI_POL_CFG_DI_POL_MASK)
180 #define EUI_POL_CFG_DI_POL_GET(x) (((uint32_t)(x) & EUI_POL_CFG_DI_POL_MASK) >> EUI_POL_CFG_DI_POL_SHIFT)
181 
182 /*
183  * DO_POL (RW)
184  *
185  * polarity at pad_do_eut_out
186  */
187 #define EUI_POL_CFG_DO_POL_MASK (0x4000000UL)
188 #define EUI_POL_CFG_DO_POL_SHIFT (26U)
189 #define EUI_POL_CFG_DO_POL_SET(x) (((uint32_t)(x) << EUI_POL_CFG_DO_POL_SHIFT) & EUI_POL_CFG_DO_POL_MASK)
190 #define EUI_POL_CFG_DO_POL_GET(x) (((uint32_t)(x) & EUI_POL_CFG_DO_POL_MASK) >> EUI_POL_CFG_DO_POL_SHIFT)
191 
192 /*
193  * CK_POL (RW)
194  *
195  * polarity at pad_do_eut_ck
196  */
197 #define EUI_POL_CFG_CK_POL_MASK (0x2000000UL)
198 #define EUI_POL_CFG_CK_POL_SHIFT (25U)
199 #define EUI_POL_CFG_CK_POL_SET(x) (((uint32_t)(x) << EUI_POL_CFG_CK_POL_SHIFT) & EUI_POL_CFG_CK_POL_MASK)
200 #define EUI_POL_CFG_CK_POL_GET(x) (((uint32_t)(x) & EUI_POL_CFG_CK_POL_MASK) >> EUI_POL_CFG_CK_POL_SHIFT)
201 
202 /*
203  * SH_POL (RW)
204  *
205  * polarity at pad_do_eut_sh
206  */
207 #define EUI_POL_CFG_SH_POL_MASK (0x1000000UL)
208 #define EUI_POL_CFG_SH_POL_SHIFT (24U)
209 #define EUI_POL_CFG_SH_POL_SET(x) (((uint32_t)(x) << EUI_POL_CFG_SH_POL_SHIFT) & EUI_POL_CFG_SH_POL_MASK)
210 #define EUI_POL_CFG_SH_POL_GET(x) (((uint32_t)(x) & EUI_POL_CFG_SH_POL_MASK) >> EUI_POL_CFG_SH_POL_SHIFT)
211 
212 /*
213  * DATA_POL (RW)
214  *
215  * output polarity, set to invert output data at output shift register.
216  * NOTE: high 16bits are used in 8x8 mode since shift is always 24 cycles
217  */
218 #define EUI_POL_CFG_DATA_POL_MASK (0xFFFFFFUL)
219 #define EUI_POL_CFG_DATA_POL_SHIFT (0U)
220 #define EUI_POL_CFG_DATA_POL_SET(x) (((uint32_t)(x) << EUI_POL_CFG_DATA_POL_SHIFT) & EUI_POL_CFG_DATA_POL_MASK)
221 #define EUI_POL_CFG_DATA_POL_GET(x) (((uint32_t)(x) & EUI_POL_CFG_DATA_POL_MASK) >> EUI_POL_CFG_DATA_POL_SHIFT)
222 
223 /* Bitfield definition for register: OUT_CFG */
224 /*
225  * DO_CFG (RW)
226  *
227  * define how many dedicate led controls
228  * in 8x8 mode:
229  * 0: no dedicate led control, use 8bits(A~H) for led line select
230  * 1: do_val[7]/H is use as dedicate led control, 7bits(A~G) for led line select
231  * 2: do_val[7:6]/GH are use as dedicate led control, 6bits(A~F) for led line select
232  * …...
233  * 6: do_val[7:2]/C~H are use as dedicate led control, 2bit/AB for led line select
234  * 7: 24 bits are used as dedicate led control(do_val[23:0] is used)
235  * in 16x4 mode, if set to 0~4, 4bit(A~D)for led line select
236  * others are same as 8x8 mode
237  */
238 #define EUI_OUT_CFG_DO_CFG_MASK (0x7000000UL)
239 #define EUI_OUT_CFG_DO_CFG_SHIFT (24U)
240 #define EUI_OUT_CFG_DO_CFG_SET(x) (((uint32_t)(x) << EUI_OUT_CFG_DO_CFG_SHIFT) & EUI_OUT_CFG_DO_CFG_MASK)
241 #define EUI_OUT_CFG_DO_CFG_GET(x) (((uint32_t)(x) & EUI_OUT_CFG_DO_CFG_MASK) >> EUI_OUT_CFG_DO_CFG_SHIFT)
242 
243 /*
244  * DO_VAL (RW)
245  *
246  * dedicate led control values, this value will override output data(after do_pol)
247  */
248 #define EUI_OUT_CFG_DO_VAL_MASK (0xFFFFFFUL)
249 #define EUI_OUT_CFG_DO_VAL_SHIFT (0U)
250 #define EUI_OUT_CFG_DO_VAL_SET(x) (((uint32_t)(x) << EUI_OUT_CFG_DO_VAL_SHIFT) & EUI_OUT_CFG_DO_VAL_MASK)
251 #define EUI_OUT_CFG_DO_VAL_GET(x) (((uint32_t)(x) & EUI_OUT_CFG_DO_VAL_MASK) >> EUI_OUT_CFG_DO_VAL_SHIFT)
252 
253 /* Bitfield definition for register: IN_CFG */
254 /*
255  * DI_CFG (RW)
256  *
257  * set for input used as dedicate switch, will use dedicate filter logic and interrupt logic
258  */
259 #define EUI_IN_CFG_DI_CFG_MASK (0xFFFF0000UL)
260 #define EUI_IN_CFG_DI_CFG_SHIFT (16U)
261 #define EUI_IN_CFG_DI_CFG_SET(x) (((uint32_t)(x) << EUI_IN_CFG_DI_CFG_SHIFT) & EUI_IN_CFG_DI_CFG_MASK)
262 #define EUI_IN_CFG_DI_CFG_GET(x) (((uint32_t)(x) & EUI_IN_CFG_DI_CFG_MASK) >> EUI_IN_CFG_DI_CFG_SHIFT)
263 
264 /*
265  * DI_VAL (RO)
266  *
267  * 16bit input data
268  */
269 #define EUI_IN_CFG_DI_VAL_MASK (0xFFFFU)
270 #define EUI_IN_CFG_DI_VAL_SHIFT (0U)
271 #define EUI_IN_CFG_DI_VAL_GET(x) (((uint32_t)(x) & EUI_IN_CFG_DI_VAL_MASK) >> EUI_IN_CFG_DI_VAL_SHIFT)
272 
273 /* Bitfield definition for register: IRQ_STS */
274 /*
275  * IRQ_SINGLE_STS (W1C)
276  *
277  */
278 #define EUI_IRQ_STS_IRQ_SINGLE_STS_MASK (0x2U)
279 #define EUI_IRQ_STS_IRQ_SINGLE_STS_SHIFT (1U)
280 #define EUI_IRQ_STS_IRQ_SINGLE_STS_SET(x) (((uint32_t)(x) << EUI_IRQ_STS_IRQ_SINGLE_STS_SHIFT) & EUI_IRQ_STS_IRQ_SINGLE_STS_MASK)
281 #define EUI_IRQ_STS_IRQ_SINGLE_STS_GET(x) (((uint32_t)(x) & EUI_IRQ_STS_IRQ_SINGLE_STS_MASK) >> EUI_IRQ_STS_IRQ_SINGLE_STS_SHIFT)
282 
283 /*
284  * IRQ_AREA_STS (W1C)
285  *
286  */
287 #define EUI_IRQ_STS_IRQ_AREA_STS_MASK (0x1U)
288 #define EUI_IRQ_STS_IRQ_AREA_STS_SHIFT (0U)
289 #define EUI_IRQ_STS_IRQ_AREA_STS_SET(x) (((uint32_t)(x) << EUI_IRQ_STS_IRQ_AREA_STS_SHIFT) & EUI_IRQ_STS_IRQ_AREA_STS_MASK)
290 #define EUI_IRQ_STS_IRQ_AREA_STS_GET(x) (((uint32_t)(x) & EUI_IRQ_STS_IRQ_AREA_STS_MASK) >> EUI_IRQ_STS_IRQ_AREA_STS_SHIFT)
291 
292 /* Bitfield definition for register: IRQ_EN */
293 /*
294  * IRQ_SINGLE_EN (RW)
295  *
296  */
297 #define EUI_IRQ_EN_IRQ_SINGLE_EN_MASK (0x2U)
298 #define EUI_IRQ_EN_IRQ_SINGLE_EN_SHIFT (1U)
299 #define EUI_IRQ_EN_IRQ_SINGLE_EN_SET(x) (((uint32_t)(x) << EUI_IRQ_EN_IRQ_SINGLE_EN_SHIFT) & EUI_IRQ_EN_IRQ_SINGLE_EN_MASK)
300 #define EUI_IRQ_EN_IRQ_SINGLE_EN_GET(x) (((uint32_t)(x) & EUI_IRQ_EN_IRQ_SINGLE_EN_MASK) >> EUI_IRQ_EN_IRQ_SINGLE_EN_SHIFT)
301 
302 /*
303  * IRQ_AREA_EN (RW)
304  *
305  */
306 #define EUI_IRQ_EN_IRQ_AREA_EN_MASK (0x1U)
307 #define EUI_IRQ_EN_IRQ_AREA_EN_SHIFT (0U)
308 #define EUI_IRQ_EN_IRQ_AREA_EN_SET(x) (((uint32_t)(x) << EUI_IRQ_EN_IRQ_AREA_EN_SHIFT) & EUI_IRQ_EN_IRQ_AREA_EN_MASK)
309 #define EUI_IRQ_EN_IRQ_AREA_EN_GET(x) (((uint32_t)(x) & EUI_IRQ_EN_IRQ_AREA_EN_MASK) >> EUI_IRQ_EN_IRQ_AREA_EN_SHIFT)
310 
311 /* Bitfield definition for register: DATA_IN0 */
312 /*
313  * DATA (RO)
314  *
315  * read value when select bit 0(0x01 for output value in 8x8 mode)
316  */
317 #define EUI_DATA_IN0_DATA_MASK (0xFFFFU)
318 #define EUI_DATA_IN0_DATA_SHIFT (0U)
319 #define EUI_DATA_IN0_DATA_GET(x) (((uint32_t)(x) & EUI_DATA_IN0_DATA_MASK) >> EUI_DATA_IN0_DATA_SHIFT)
320 
321 /* Bitfield definition for register: DATA_IN1 */
322 /*
323  * DATA (RO)
324  *
325  */
326 #define EUI_DATA_IN1_DATA_MASK (0xFFFFU)
327 #define EUI_DATA_IN1_DATA_SHIFT (0U)
328 #define EUI_DATA_IN1_DATA_GET(x) (((uint32_t)(x) & EUI_DATA_IN1_DATA_MASK) >> EUI_DATA_IN1_DATA_SHIFT)
329 
330 /* Bitfield definition for register: DATA_IN2 */
331 /*
332  * DATA (RO)
333  *
334  */
335 #define EUI_DATA_IN2_DATA_MASK (0xFFFFU)
336 #define EUI_DATA_IN2_DATA_SHIFT (0U)
337 #define EUI_DATA_IN2_DATA_GET(x) (((uint32_t)(x) & EUI_DATA_IN2_DATA_MASK) >> EUI_DATA_IN2_DATA_SHIFT)
338 
339 /* Bitfield definition for register: DATA_IN3 */
340 /*
341  * DATA (RO)
342  *
343  */
344 #define EUI_DATA_IN3_DATA_MASK (0xFFFFU)
345 #define EUI_DATA_IN3_DATA_SHIFT (0U)
346 #define EUI_DATA_IN3_DATA_GET(x) (((uint32_t)(x) & EUI_DATA_IN3_DATA_MASK) >> EUI_DATA_IN3_DATA_SHIFT)
347 
348 /* Bitfield definition for register: DATA_IN4 */
349 /*
350  * DATA (RO)
351  *
352  */
353 #define EUI_DATA_IN4_DATA_MASK (0xFFFFU)
354 #define EUI_DATA_IN4_DATA_SHIFT (0U)
355 #define EUI_DATA_IN4_DATA_GET(x) (((uint32_t)(x) & EUI_DATA_IN4_DATA_MASK) >> EUI_DATA_IN4_DATA_SHIFT)
356 
357 /* Bitfield definition for register: DATA_IN5 */
358 /*
359  * DATA (RO)
360  *
361  */
362 #define EUI_DATA_IN5_DATA_MASK (0xFFFFU)
363 #define EUI_DATA_IN5_DATA_SHIFT (0U)
364 #define EUI_DATA_IN5_DATA_GET(x) (((uint32_t)(x) & EUI_DATA_IN5_DATA_MASK) >> EUI_DATA_IN5_DATA_SHIFT)
365 
366 /* Bitfield definition for register: DATA_IN6 */
367 /*
368  * DATA (RO)
369  *
370  */
371 #define EUI_DATA_IN6_DATA_MASK (0xFFFFU)
372 #define EUI_DATA_IN6_DATA_SHIFT (0U)
373 #define EUI_DATA_IN6_DATA_GET(x) (((uint32_t)(x) & EUI_DATA_IN6_DATA_MASK) >> EUI_DATA_IN6_DATA_SHIFT)
374 
375 /* Bitfield definition for register: DATA_IN7 */
376 /*
377  * DATA (RO)
378  *
379  */
380 #define EUI_DATA_IN7_DATA_MASK (0xFFFFU)
381 #define EUI_DATA_IN7_DATA_SHIFT (0U)
382 #define EUI_DATA_IN7_DATA_GET(x) (((uint32_t)(x) & EUI_DATA_IN7_DATA_MASK) >> EUI_DATA_IN7_DATA_SHIFT)
383 
384 /* Bitfield definition for register: DAB_CTRL */
385 /*
386  * DB_CTRL (RW)
387  *
388  * 00: output data B directly;
389  * 01: A&B; 10: A|B; 11: A^B
390  */
391 #define EUI_DAB_CTRL_DB_CTRL_MASK (0xC0000000UL)
392 #define EUI_DAB_CTRL_DB_CTRL_SHIFT (30U)
393 #define EUI_DAB_CTRL_DB_CTRL_SET(x) (((uint32_t)(x) << EUI_DAB_CTRL_DB_CTRL_SHIFT) & EUI_DAB_CTRL_DB_CTRL_MASK)
394 #define EUI_DAB_CTRL_DB_CTRL_GET(x) (((uint32_t)(x) & EUI_DAB_CTRL_DB_CTRL_MASK) >> EUI_DAB_CTRL_DB_CTRL_SHIFT)
395 
396 /*
397  * LOOPAB (RW)
398  *
399  * display AB loop
400  * display data A for prda, then B for prdB, then lopp AB;
401  * then display C, D(loop CD), EF, GH, then back to AB
402  * 0 for no loop, just display once
403  */
404 #define EUI_DAB_CTRL_LOOPAB_MASK (0xFF0000UL)
405 #define EUI_DAB_CTRL_LOOPAB_SHIFT (16U)
406 #define EUI_DAB_CTRL_LOOPAB_SET(x) (((uint32_t)(x) << EUI_DAB_CTRL_LOOPAB_SHIFT) & EUI_DAB_CTRL_LOOPAB_MASK)
407 #define EUI_DAB_CTRL_LOOPAB_GET(x) (((uint32_t)(x) & EUI_DAB_CTRL_LOOPAB_MASK) >> EUI_DAB_CTRL_LOOPAB_SHIFT)
408 
409 /*
410  * PRDB (RW)
411  *
412  * display data B time(in unit of 16*disp_time), default 65ms(65536us)
413  */
414 #define EUI_DAB_CTRL_PRDB_MASK (0xFF00U)
415 #define EUI_DAB_CTRL_PRDB_SHIFT (8U)
416 #define EUI_DAB_CTRL_PRDB_SET(x) (((uint32_t)(x) << EUI_DAB_CTRL_PRDB_SHIFT) & EUI_DAB_CTRL_PRDB_MASK)
417 #define EUI_DAB_CTRL_PRDB_GET(x) (((uint32_t)(x) & EUI_DAB_CTRL_PRDB_MASK) >> EUI_DAB_CTRL_PRDB_SHIFT)
418 
419 /*
420  * PRDA (RW)
421  *
422  * display data A time(in unit of 16*disp_time)
423  * dab_ctrl.prda must be none-zero value, others can be set to 0 if no data
424  */
425 #define EUI_DAB_CTRL_PRDA_MASK (0xFFU)
426 #define EUI_DAB_CTRL_PRDA_SHIFT (0U)
427 #define EUI_DAB_CTRL_PRDA_SET(x) (((uint32_t)(x) << EUI_DAB_CTRL_PRDA_SHIFT) & EUI_DAB_CTRL_PRDA_MASK)
428 #define EUI_DAB_CTRL_PRDA_GET(x) (((uint32_t)(x) & EUI_DAB_CTRL_PRDA_MASK) >> EUI_DAB_CTRL_PRDA_SHIFT)
429 
430 /* Bitfield definition for register: DCD_CTRL */
431 /*
432  * DD_CTRL (RW)
433  *
434  */
435 #define EUI_DCD_CTRL_DD_CTRL_MASK (0xC0000000UL)
436 #define EUI_DCD_CTRL_DD_CTRL_SHIFT (30U)
437 #define EUI_DCD_CTRL_DD_CTRL_SET(x) (((uint32_t)(x) << EUI_DCD_CTRL_DD_CTRL_SHIFT) & EUI_DCD_CTRL_DD_CTRL_MASK)
438 #define EUI_DCD_CTRL_DD_CTRL_GET(x) (((uint32_t)(x) & EUI_DCD_CTRL_DD_CTRL_MASK) >> EUI_DCD_CTRL_DD_CTRL_SHIFT)
439 
440 /*
441  * LOOPCD (RW)
442  *
443  */
444 #define EUI_DCD_CTRL_LOOPCD_MASK (0xFF0000UL)
445 #define EUI_DCD_CTRL_LOOPCD_SHIFT (16U)
446 #define EUI_DCD_CTRL_LOOPCD_SET(x) (((uint32_t)(x) << EUI_DCD_CTRL_LOOPCD_SHIFT) & EUI_DCD_CTRL_LOOPCD_MASK)
447 #define EUI_DCD_CTRL_LOOPCD_GET(x) (((uint32_t)(x) & EUI_DCD_CTRL_LOOPCD_MASK) >> EUI_DCD_CTRL_LOOPCD_SHIFT)
448 
449 /*
450  * PRDD (RW)
451  *
452  */
453 #define EUI_DCD_CTRL_PRDD_MASK (0xFF00U)
454 #define EUI_DCD_CTRL_PRDD_SHIFT (8U)
455 #define EUI_DCD_CTRL_PRDD_SET(x) (((uint32_t)(x) << EUI_DCD_CTRL_PRDD_SHIFT) & EUI_DCD_CTRL_PRDD_MASK)
456 #define EUI_DCD_CTRL_PRDD_GET(x) (((uint32_t)(x) & EUI_DCD_CTRL_PRDD_MASK) >> EUI_DCD_CTRL_PRDD_SHIFT)
457 
458 /*
459  * PRDC (RW)
460  *
461  */
462 #define EUI_DCD_CTRL_PRDC_MASK (0xFFU)
463 #define EUI_DCD_CTRL_PRDC_SHIFT (0U)
464 #define EUI_DCD_CTRL_PRDC_SET(x) (((uint32_t)(x) << EUI_DCD_CTRL_PRDC_SHIFT) & EUI_DCD_CTRL_PRDC_MASK)
465 #define EUI_DCD_CTRL_PRDC_GET(x) (((uint32_t)(x) & EUI_DCD_CTRL_PRDC_MASK) >> EUI_DCD_CTRL_PRDC_SHIFT)
466 
467 /* Bitfield definition for register: DEF_CTRL */
468 /*
469  * DF_CTRL (RW)
470  *
471  */
472 #define EUI_DEF_CTRL_DF_CTRL_MASK (0xC0000000UL)
473 #define EUI_DEF_CTRL_DF_CTRL_SHIFT (30U)
474 #define EUI_DEF_CTRL_DF_CTRL_SET(x) (((uint32_t)(x) << EUI_DEF_CTRL_DF_CTRL_SHIFT) & EUI_DEF_CTRL_DF_CTRL_MASK)
475 #define EUI_DEF_CTRL_DF_CTRL_GET(x) (((uint32_t)(x) & EUI_DEF_CTRL_DF_CTRL_MASK) >> EUI_DEF_CTRL_DF_CTRL_SHIFT)
476 
477 /*
478  * LOOPEF (RW)
479  *
480  */
481 #define EUI_DEF_CTRL_LOOPEF_MASK (0xFF0000UL)
482 #define EUI_DEF_CTRL_LOOPEF_SHIFT (16U)
483 #define EUI_DEF_CTRL_LOOPEF_SET(x) (((uint32_t)(x) << EUI_DEF_CTRL_LOOPEF_SHIFT) & EUI_DEF_CTRL_LOOPEF_MASK)
484 #define EUI_DEF_CTRL_LOOPEF_GET(x) (((uint32_t)(x) & EUI_DEF_CTRL_LOOPEF_MASK) >> EUI_DEF_CTRL_LOOPEF_SHIFT)
485 
486 /*
487  * PRDF (RW)
488  *
489  */
490 #define EUI_DEF_CTRL_PRDF_MASK (0xFF00U)
491 #define EUI_DEF_CTRL_PRDF_SHIFT (8U)
492 #define EUI_DEF_CTRL_PRDF_SET(x) (((uint32_t)(x) << EUI_DEF_CTRL_PRDF_SHIFT) & EUI_DEF_CTRL_PRDF_MASK)
493 #define EUI_DEF_CTRL_PRDF_GET(x) (((uint32_t)(x) & EUI_DEF_CTRL_PRDF_MASK) >> EUI_DEF_CTRL_PRDF_SHIFT)
494 
495 /*
496  * PRDE (RW)
497  *
498  */
499 #define EUI_DEF_CTRL_PRDE_MASK (0xFFU)
500 #define EUI_DEF_CTRL_PRDE_SHIFT (0U)
501 #define EUI_DEF_CTRL_PRDE_SET(x) (((uint32_t)(x) << EUI_DEF_CTRL_PRDE_SHIFT) & EUI_DEF_CTRL_PRDE_MASK)
502 #define EUI_DEF_CTRL_PRDE_GET(x) (((uint32_t)(x) & EUI_DEF_CTRL_PRDE_MASK) >> EUI_DEF_CTRL_PRDE_SHIFT)
503 
504 /* Bitfield definition for register: DGH_CTRL */
505 /*
506  * DH_CTRL (RW)
507  *
508  */
509 #define EUI_DGH_CTRL_DH_CTRL_MASK (0xC0000000UL)
510 #define EUI_DGH_CTRL_DH_CTRL_SHIFT (30U)
511 #define EUI_DGH_CTRL_DH_CTRL_SET(x) (((uint32_t)(x) << EUI_DGH_CTRL_DH_CTRL_SHIFT) & EUI_DGH_CTRL_DH_CTRL_MASK)
512 #define EUI_DGH_CTRL_DH_CTRL_GET(x) (((uint32_t)(x) & EUI_DGH_CTRL_DH_CTRL_MASK) >> EUI_DGH_CTRL_DH_CTRL_SHIFT)
513 
514 /*
515  * LOOPGH (RW)
516  *
517  */
518 #define EUI_DGH_CTRL_LOOPGH_MASK (0xFF0000UL)
519 #define EUI_DGH_CTRL_LOOPGH_SHIFT (16U)
520 #define EUI_DGH_CTRL_LOOPGH_SET(x) (((uint32_t)(x) << EUI_DGH_CTRL_LOOPGH_SHIFT) & EUI_DGH_CTRL_LOOPGH_MASK)
521 #define EUI_DGH_CTRL_LOOPGH_GET(x) (((uint32_t)(x) & EUI_DGH_CTRL_LOOPGH_MASK) >> EUI_DGH_CTRL_LOOPGH_SHIFT)
522 
523 /*
524  * PRDH (RW)
525  *
526  */
527 #define EUI_DGH_CTRL_PRDH_MASK (0xFF00U)
528 #define EUI_DGH_CTRL_PRDH_SHIFT (8U)
529 #define EUI_DGH_CTRL_PRDH_SET(x) (((uint32_t)(x) << EUI_DGH_CTRL_PRDH_SHIFT) & EUI_DGH_CTRL_PRDH_MASK)
530 #define EUI_DGH_CTRL_PRDH_GET(x) (((uint32_t)(x) & EUI_DGH_CTRL_PRDH_MASK) >> EUI_DGH_CTRL_PRDH_SHIFT)
531 
532 /*
533  * PRDG (RW)
534  *
535  */
536 #define EUI_DGH_CTRL_PRDG_MASK (0xFFU)
537 #define EUI_DGH_CTRL_PRDG_SHIFT (0U)
538 #define EUI_DGH_CTRL_PRDG_SET(x) (((uint32_t)(x) << EUI_DGH_CTRL_PRDG_SHIFT) & EUI_DGH_CTRL_PRDG_MASK)
539 #define EUI_DGH_CTRL_PRDG_GET(x) (((uint32_t)(x) & EUI_DGH_CTRL_PRDG_MASK) >> EUI_DGH_CTRL_PRDG_SHIFT)
540 
541 /* Bitfield definition for register: DA_00 */
542 /*
543  * DATA (RW)
544  *
545  */
546 #define EUI_DA_00_DATA_MASK (0xFFFFFFFFUL)
547 #define EUI_DA_00_DATA_SHIFT (0U)
548 #define EUI_DA_00_DATA_SET(x) (((uint32_t)(x) << EUI_DA_00_DATA_SHIFT) & EUI_DA_00_DATA_MASK)
549 #define EUI_DA_00_DATA_GET(x) (((uint32_t)(x) & EUI_DA_00_DATA_MASK) >> EUI_DA_00_DATA_SHIFT)
550 
551 /* Bitfield definition for register: DA_01 */
552 /*
553  * DATA (RW)
554  *
555  */
556 #define EUI_DA_01_DATA_MASK (0xFFFFFFFFUL)
557 #define EUI_DA_01_DATA_SHIFT (0U)
558 #define EUI_DA_01_DATA_SET(x) (((uint32_t)(x) << EUI_DA_01_DATA_SHIFT) & EUI_DA_01_DATA_MASK)
559 #define EUI_DA_01_DATA_GET(x) (((uint32_t)(x) & EUI_DA_01_DATA_MASK) >> EUI_DA_01_DATA_SHIFT)
560 
561 /* Bitfield definition for register: DB_00 */
562 /*
563  * DATA (RW)
564  *
565  */
566 #define EUI_DB_00_DATA_MASK (0xFFFFFFFFUL)
567 #define EUI_DB_00_DATA_SHIFT (0U)
568 #define EUI_DB_00_DATA_SET(x) (((uint32_t)(x) << EUI_DB_00_DATA_SHIFT) & EUI_DB_00_DATA_MASK)
569 #define EUI_DB_00_DATA_GET(x) (((uint32_t)(x) & EUI_DB_00_DATA_MASK) >> EUI_DB_00_DATA_SHIFT)
570 
571 /* Bitfield definition for register: DB_01 */
572 /*
573  * DATA (RW)
574  *
575  */
576 #define EUI_DB_01_DATA_MASK (0xFFFFFFFFUL)
577 #define EUI_DB_01_DATA_SHIFT (0U)
578 #define EUI_DB_01_DATA_SET(x) (((uint32_t)(x) << EUI_DB_01_DATA_SHIFT) & EUI_DB_01_DATA_MASK)
579 #define EUI_DB_01_DATA_GET(x) (((uint32_t)(x) & EUI_DB_01_DATA_MASK) >> EUI_DB_01_DATA_SHIFT)
580 
581 /* Bitfield definition for register: DC_00 */
582 /*
583  * DATA (RW)
584  *
585  */
586 #define EUI_DC_00_DATA_MASK (0xFFFFFFFFUL)
587 #define EUI_DC_00_DATA_SHIFT (0U)
588 #define EUI_DC_00_DATA_SET(x) (((uint32_t)(x) << EUI_DC_00_DATA_SHIFT) & EUI_DC_00_DATA_MASK)
589 #define EUI_DC_00_DATA_GET(x) (((uint32_t)(x) & EUI_DC_00_DATA_MASK) >> EUI_DC_00_DATA_SHIFT)
590 
591 /* Bitfield definition for register: DC_01 */
592 /*
593  * DATA (RW)
594  *
595  */
596 #define EUI_DC_01_DATA_MASK (0xFFFFFFFFUL)
597 #define EUI_DC_01_DATA_SHIFT (0U)
598 #define EUI_DC_01_DATA_SET(x) (((uint32_t)(x) << EUI_DC_01_DATA_SHIFT) & EUI_DC_01_DATA_MASK)
599 #define EUI_DC_01_DATA_GET(x) (((uint32_t)(x) & EUI_DC_01_DATA_MASK) >> EUI_DC_01_DATA_SHIFT)
600 
601 /* Bitfield definition for register: DD_00 */
602 /*
603  * DATA (RW)
604  *
605  */
606 #define EUI_DD_00_DATA_MASK (0xFFFFFFFFUL)
607 #define EUI_DD_00_DATA_SHIFT (0U)
608 #define EUI_DD_00_DATA_SET(x) (((uint32_t)(x) << EUI_DD_00_DATA_SHIFT) & EUI_DD_00_DATA_MASK)
609 #define EUI_DD_00_DATA_GET(x) (((uint32_t)(x) & EUI_DD_00_DATA_MASK) >> EUI_DD_00_DATA_SHIFT)
610 
611 /* Bitfield definition for register: DD_01 */
612 /*
613  * DATA (RW)
614  *
615  */
616 #define EUI_DD_01_DATA_MASK (0xFFFFFFFFUL)
617 #define EUI_DD_01_DATA_SHIFT (0U)
618 #define EUI_DD_01_DATA_SET(x) (((uint32_t)(x) << EUI_DD_01_DATA_SHIFT) & EUI_DD_01_DATA_MASK)
619 #define EUI_DD_01_DATA_GET(x) (((uint32_t)(x) & EUI_DD_01_DATA_MASK) >> EUI_DD_01_DATA_SHIFT)
620 
621 /* Bitfield definition for register: DE_00 */
622 /*
623  * DATA (RW)
624  *
625  */
626 #define EUI_DE_00_DATA_MASK (0xFFFFFFFFUL)
627 #define EUI_DE_00_DATA_SHIFT (0U)
628 #define EUI_DE_00_DATA_SET(x) (((uint32_t)(x) << EUI_DE_00_DATA_SHIFT) & EUI_DE_00_DATA_MASK)
629 #define EUI_DE_00_DATA_GET(x) (((uint32_t)(x) & EUI_DE_00_DATA_MASK) >> EUI_DE_00_DATA_SHIFT)
630 
631 /* Bitfield definition for register: DE_01 */
632 /*
633  * DATA (RW)
634  *
635  */
636 #define EUI_DE_01_DATA_MASK (0xFFFFFFFFUL)
637 #define EUI_DE_01_DATA_SHIFT (0U)
638 #define EUI_DE_01_DATA_SET(x) (((uint32_t)(x) << EUI_DE_01_DATA_SHIFT) & EUI_DE_01_DATA_MASK)
639 #define EUI_DE_01_DATA_GET(x) (((uint32_t)(x) & EUI_DE_01_DATA_MASK) >> EUI_DE_01_DATA_SHIFT)
640 
641 /* Bitfield definition for register: DF_00 */
642 /*
643  * DATA (RW)
644  *
645  */
646 #define EUI_DF_00_DATA_MASK (0xFFFFFFFFUL)
647 #define EUI_DF_00_DATA_SHIFT (0U)
648 #define EUI_DF_00_DATA_SET(x) (((uint32_t)(x) << EUI_DF_00_DATA_SHIFT) & EUI_DF_00_DATA_MASK)
649 #define EUI_DF_00_DATA_GET(x) (((uint32_t)(x) & EUI_DF_00_DATA_MASK) >> EUI_DF_00_DATA_SHIFT)
650 
651 /* Bitfield definition for register: DF_01 */
652 /*
653  * DATA (RW)
654  *
655  */
656 #define EUI_DF_01_DATA_MASK (0xFFFFFFFFUL)
657 #define EUI_DF_01_DATA_SHIFT (0U)
658 #define EUI_DF_01_DATA_SET(x) (((uint32_t)(x) << EUI_DF_01_DATA_SHIFT) & EUI_DF_01_DATA_MASK)
659 #define EUI_DF_01_DATA_GET(x) (((uint32_t)(x) & EUI_DF_01_DATA_MASK) >> EUI_DF_01_DATA_SHIFT)
660 
661 /* Bitfield definition for register: DG_00 */
662 /*
663  * DATA (RW)
664  *
665  */
666 #define EUI_DG_00_DATA_MASK (0xFFFFFFFFUL)
667 #define EUI_DG_00_DATA_SHIFT (0U)
668 #define EUI_DG_00_DATA_SET(x) (((uint32_t)(x) << EUI_DG_00_DATA_SHIFT) & EUI_DG_00_DATA_MASK)
669 #define EUI_DG_00_DATA_GET(x) (((uint32_t)(x) & EUI_DG_00_DATA_MASK) >> EUI_DG_00_DATA_SHIFT)
670 
671 /* Bitfield definition for register: DG_01 */
672 /*
673  * DATA (RW)
674  *
675  */
676 #define EUI_DG_01_DATA_MASK (0xFFFFFFFFUL)
677 #define EUI_DG_01_DATA_SHIFT (0U)
678 #define EUI_DG_01_DATA_SET(x) (((uint32_t)(x) << EUI_DG_01_DATA_SHIFT) & EUI_DG_01_DATA_MASK)
679 #define EUI_DG_01_DATA_GET(x) (((uint32_t)(x) & EUI_DG_01_DATA_MASK) >> EUI_DG_01_DATA_SHIFT)
680 
681 /* Bitfield definition for register: DH_00 */
682 /*
683  * DATA (RW)
684  *
685  */
686 #define EUI_DH_00_DATA_MASK (0xFFFFFFFFUL)
687 #define EUI_DH_00_DATA_SHIFT (0U)
688 #define EUI_DH_00_DATA_SET(x) (((uint32_t)(x) << EUI_DH_00_DATA_SHIFT) & EUI_DH_00_DATA_MASK)
689 #define EUI_DH_00_DATA_GET(x) (((uint32_t)(x) & EUI_DH_00_DATA_MASK) >> EUI_DH_00_DATA_SHIFT)
690 
691 /* Bitfield definition for register: DH_01 */
692 /*
693  * DATA (RW)
694  *
695  */
696 #define EUI_DH_01_DATA_MASK (0xFFFFFFFFUL)
697 #define EUI_DH_01_DATA_SHIFT (0U)
698 #define EUI_DH_01_DATA_SET(x) (((uint32_t)(x) << EUI_DH_01_DATA_SHIFT) & EUI_DH_01_DATA_MASK)
699 #define EUI_DH_01_DATA_GET(x) (((uint32_t)(x) & EUI_DH_01_DATA_MASK) >> EUI_DH_01_DATA_SHIFT)
700 
701 
702 
703 
704 #endif /* HPM_EUI_H */
EUI_Type
Definition: hpm_eui_regs.h:12