hpm_pwm_drv.h

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/*
 * Copyright (c) 2021-2025 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
 */
 
#ifndef HPM_PWM_DRV_H
#define HPM_PWM_DRV_H
 
#include "hpm_common.h"
#include "hpm_pwm_regs.h"
#include "hpm_soc_feature.h"
#define PWM_UNLOCK_KEY (0xB0382607UL)
 
/* IRQ enable bit mask */
#define PWM_IRQ_FAULT PWM_IRQEN_FAULTIRQE_MASK
#define PWM_IRQ_EX_RELOAD PWM_IRQEN_XRLDIRQE_MASK
#define PWM_IRQ_HALF_RELOAD PWM_IRQEN_HALFRLDIRQE_MASK
#define PWM_IRQ_RELOAD PWM_IRQEN_RLDIRQE_MASK
#define PWM_IRQ_CMP(x) PWM_IRQEN_CMPIRQEX_SET((1 << x))
 
/* PWM force output mask */
#define PWM_FORCE_OUTPUT(pwm_index, force_output) \
    (force_output << (pwm_index << 1))
 
#define PWM_DUTY_CYCLE_FP_MAX ((1U << 24) - 1)
 
typedef enum pwm_counter_type {
    pwm_counter_type_capture_rising_edge,   
    pwm_counter_type_capture_falling_edge,  
} pwm_counter_type_t;
 
typedef enum pwm_cmp_mode {
    pwm_cmp_mode_output_compare = 0,    
    pwm_cmp_mode_input_capture = 1,     
} pwm_cmp_mode_t;
 
typedef enum pwm_register_update {
    pwm_shadow_register_update_on_shlk = 0,     
    pwm_shadow_register_update_on_modify = 1,   
    pwm_shadow_register_update_on_hw_event = 2, 
    pwm_shadow_register_update_on_sh_synci = 3, 
} pwm_shadow_register_update_trigger_t;
 
typedef enum pwm_fault_mode {
    pwm_fault_mode_force_output_0 = 0, 
    pwm_fault_mode_force_output_1 = 1,  
    pwm_fault_mode_force_output_highz = 2,  
} pwm_fault_mode_t;
 
typedef enum pwm_fault_recovery_trigger {
    pwm_fault_recovery_immediately = 0, 
    pwm_fault_recovery_on_reload = 1,   
    pwm_fault_recovery_on_hw_event = 2, 
    pwm_fault_recovery_on_fault_clear = 3,  
} pwm_fault_recovery_trigger_t;
 
typedef enum pwm_fault_source {
    pwm_fault_source_internal_0 = PWM_GCR_FAULTI0EN_MASK, 
    pwm_fault_source_internal_1 = PWM_GCR_FAULTI1EN_MASK, 
    pwm_fault_source_internal_2 = PWM_GCR_FAULTI2EN_MASK, 
    pwm_fault_source_internal_3 = PWM_GCR_FAULTI3EN_MASK, 
    pwm_fault_source_external_0 = PWM_GCR_FAULTE0EN_MASK, 
    pwm_fault_source_external_1 = PWM_GCR_FAULTE1EN_MASK, 
    pwm_fault_source_debug = PWM_GCR_DEBUGFAULT_MASK,   
} pwm_fault_source_t;
 
typedef enum pwm_force_source {
    pwm_force_source_force_input = 0, 
    pwm_force_source_software = 1,  
} pwm_force_source_t;
typedef enum pwm_force_cmd_timing {
    pwm_force_immediately = 0,  
    pwm_force_at_reload = 1,    
    pwm_force_at_synci = 2,     
    pwm_force_none = 3,         
} pwm_force_cmd_timing_t;
 
typedef enum pwm_output_type {
    pwm_output_0 = 0, 
    pwm_output_1 = 1, 
    pwm_output_high_z = 2, 
    pwm_output_no_force = 3,
} pwm_output_type_t;
 
typedef struct pwm_cmp_config {
    uint32_t cmp;         
    bool enable_ex_cmp;   
#if defined(PWM_SOC_HRPWM_SUPPORT) && PWM_SOC_HRPWM_SUPPORT
    bool enable_hrcmp;     
#endif
    uint8_t mode;         
    uint8_t update_trigger;  
    uint8_t ex_cmp;       
    uint8_t half_clock_cmp; 
    uint8_t jitter_cmp;     
#if defined(PWM_SOC_HRPWM_SUPPORT) && PWM_SOC_HRPWM_SUPPORT
    uint8_t hrcmp;         
#endif
} pwm_cmp_config_t;
 
typedef struct pwm_output_channel {
    uint8_t cmp_start_index; 
    uint8_t cmp_end_index;   
    bool invert_output;      
} pwm_output_channel_t;
typedef struct pwm_fault_source_config {
    uint32_t source_mask;                   
    bool fault_recover_at_rising_edge;      
    bool fault_external_0_active_low;       
    bool fault_external_1_active_low;       
    uint8_t fault_output_recovery_trigger;  
} pwm_fault_source_config_t;
 
typedef struct pwm_config {
#if defined(PWM_SOC_HRPWM_SUPPORT) && PWM_SOC_HRPWM_SUPPORT
    bool hrpwm_update_mode;             
#endif
    bool enable_output;                 
    bool invert_output;                 
    uint8_t force_cmd_shadow_update_trigger;  
    uint8_t fault_mode;                 
    uint8_t fault_recovery_trigger;     
    uint8_t force_source;               
    uint32_t dead_zone_in_half_cycle;   
} pwm_config_t;
 
typedef struct pwm_pair_config {
    pwm_config_t pwm[2];    
} pwm_pair_config_t;
 
#ifdef __cplusplus
extern "C" {
#endif
 
static inline void pwm_deinit(PWM_Type *pwm_x)
{
    pwm_x->IRQEN = 0;
    pwm_x->DMAEN = 0;
    pwm_x->SR = pwm_x->SR;
    pwm_x->STA = 0;
    pwm_x->RLD = PWM_RLD_RLD_MASK;
    for (uint8_t i = 0; i < PWM_SOC_CMP_MAX_COUNT; i++) {
        pwm_x->CMP[i] = PWM_CMP_CMP_MASK;
        pwm_x->CMPCFG[i] = 0;
        pwm_x->CHCFG[i] = PWM_CHCFG_CMPSELEND_SET(PWM_SOC_CMP_MAX_COUNT - 1) | PWM_CHCFG_CMPSELBEG_SET(PWM_SOC_CMP_MAX_COUNT - 1);
    }
    pwm_x->FRCMD = 0;
    pwm_x->GCR = 0;
    pwm_x->SHCR = 0;
#if defined(PWM_SOC_HRPWM_SUPPORT) && PWM_SOC_HRPWM_SUPPORT
    pwm_x->HRPWM_CFG = 0;
#endif
    for (uint8_t i = 0; i < PWM_SOC_OUTPUT_TO_PWM_MAX_COUNT; i++) {
        pwm_x->PWMCFG[i] = 0;
    }
}
 
static inline void pwm_issue_shadow_register_lock_event(PWM_Type *pwm_x)
{
    if (pwm_x->SHCR & PWM_SHCR_SHLKEN_MASK) {
        /*
         * if lock shadow register has been enabled in SHCR, it has to set
         * the lock bit twice to issue shadow register lock event.
         */
        pwm_x->SHLK = PWM_SHLK_SHLK_MASK;
    }
    pwm_x->SHLK = PWM_SHLK_SHLK_MASK;
}
 
static inline void pwm_shadow_register_lock(PWM_Type *pwm_x)
{
    pwm_x->SHCR |= PWM_SHCR_SHLKEN_MASK;
    pwm_x->SHLK = PWM_SHLK_SHLK_MASK;
}
 
static inline void pwm_shadow_register_unlock(PWM_Type *pwm_x)
{
    pwm_x->UNLK = PWM_UNLOCK_KEY;
}
 
static inline void pwm_set_start_count(PWM_Type *pwm_x,
                                        uint8_t ex_start,
                                        uint32_t start)
{
    pwm_x->STA = PWM_STA_XSTA_SET(ex_start)
        | PWM_STA_STA_SET(start);
}
 
#if defined(PWM_SOC_HRPWM_SUPPORT) && PWM_SOC_HRPWM_SUPPORT
 
static inline void pwm_set_hrpwm_start_count(PWM_Type *pwm_x,
                                        uint32_t start)
{
    pwm_x->STA_HRPWM = PWM_STA_HRPWM_STA_SET(start);
}
 
#endif
 
static inline void pwm_set_reload(PWM_Type *pwm_x,
                                   uint8_t ex_reload,
                                   uint32_t reload)
{
    pwm_shadow_register_unlock(pwm_x);
    pwm_x->RLD = PWM_RLD_XRLD_SET(ex_reload)
        | PWM_RLD_RLD_SET(reload);
}
 
#if defined(PWM_SOC_HRPWM_SUPPORT) && PWM_SOC_HRPWM_SUPPORT
 
static inline void pwm_set_hrpwm_reload(PWM_Type *pwm_x,
                                   uint16_t hrpwm_reload,
                                   uint32_t reload)
{
    pwm_shadow_register_unlock(pwm_x);
    pwm_x->RLD_HRPWM = PWM_RLD_HRPWM_RLD_HR_SET(hrpwm_reload)
        | PWM_RLD_HRPWM_RLD_SET(reload);
}
 
#endif
 
static inline void pwm_clear_status(PWM_Type *pwm_x, uint32_t mask)
{
    pwm_x->SR = mask;
}
 
#if defined(PWM_SOC_TIMER_RESET_SUPPORT) && PWM_SOC_TIMER_RESET_SUPPORT
 
static inline void pwm_timer_reset(PWM_Type *pwm_x)
{
     pwm_x->GCR = ((pwm_x->GCR & ~(PWM_GCR_TIMERRESET_MASK)) | PWM_GCR_TIMERRESET_SET(1));
}
 
#endif
 
static inline uint32_t pwm_get_status(PWM_Type *pwm_x)
{
    return pwm_x->SR;
}
 
static inline uint32_t pwm_get_irq_en(PWM_Type *pwm_x)
{
    return pwm_x->IRQEN;
}
 
static inline void pwm_disable_irq(PWM_Type *pwm_x, uint32_t mask)
{
    pwm_x->IRQEN &= ~mask;
}
 
static inline void pwm_enable_irq(PWM_Type *pwm_x, uint32_t mask)
{
    pwm_x->IRQEN |= mask;
}
 
static inline void pwm_set_capture_irq_falling_edge(PWM_Type *pwm_x, uint32_t mask)
{
    pwm_x->CAP_EN_NEG |= mask;
}
 
static inline void pwm_set_capture_irq_rising_edge(PWM_Type *pwm_x, uint32_t mask)
{
    pwm_x->CAP_EN_NEG &= ~mask;
}
 
static inline void pwm_disable_dma_request(PWM_Type *pwm_x, uint32_t mask)
{
    pwm_x->DMAEN &= ~mask;
}
 
static inline void pwm_enable_dma_request(PWM_Type *pwm_x, uint32_t mask)
{
    pwm_x->DMAEN |= mask;
}
 
static inline void pwm_set_force_cmd_shadow_register_hwevent(PWM_Type *pwm_x,
                                                    uint8_t target_cmp_index)
{
    pwm_x->SHCR = ((pwm_x->SHCR & ~(PWM_SHCR_FRCSHDWSEL_MASK))
                    | PWM_SHCR_FRCSHDWSEL_SET(target_cmp_index));
}
static inline void pwm_set_load_counter_shadow_register_trigger(PWM_Type *pwm_x,
                                pwm_shadow_register_update_trigger_t trigger,
                                uint8_t target_cmp_index)
{
    if (trigger == pwm_shadow_register_update_on_hw_event) {
        pwm_x->SHCR = ((pwm_x->SHCR & ~(PWM_SHCR_CNTSHDWSEL_MASK
                        | PWM_SHCR_CNTSHDWUPT_MASK))
                | PWM_SHCR_CNTSHDWSEL_SET(target_cmp_index)
                | PWM_SHCR_CNTSHDWUPT_SET(trigger));
    } else {
        pwm_x->SHCR = ((pwm_x->SHCR & ~(PWM_SHCR_CNTSHDWUPT_MASK))
                | PWM_SHCR_CNTSHDWUPT_SET(trigger));
    }
}
 
static inline void pwm_load_cmp_shadow_on_capture(PWM_Type *pwm_x,
                                                   uint8_t index,
                                                   bool is_falling_edge)
{
    pwm_x->CMPCFG[index] |= PWM_CMPCFG_CMPMODE_MASK;
    pwm_x->GCR = ((pwm_x->GCR & ~(PWM_GCR_CMPSHDWSEL_MASK | PWM_GCR_HWSHDWEDG_MASK))
            | PWM_GCR_CMPSHDWSEL_SET(index)
            | PWM_GCR_HWSHDWEDG_SET(is_falling_edge));
}
 
#if defined(PWM_SOC_SHADOW_TRIG_SUPPORT) && PWM_SOC_SHADOW_TRIG_SUPPORT
 
static inline void pwm_set_cnt_shadow_trig_reload(PWM_Type *pwm_x, bool is_enable)
{
        pwm_x->SHCR = ((pwm_x->SHCR & ~PWM_SHCR_CNT_UPDATE_RELOAD_MASK)
            | PWM_SHCR_CNT_UPDATE_RELOAD_SET(is_enable));
}
 
static inline void pwm_set_cnt_shadow_trig_edge(PWM_Type *pwm_x,
                                                   bool is_falling_edge)
{
    pwm_x->SHCR = ((pwm_x->SHCR & ~PWM_SHCR_CNT_UPDATE_EDGE_MASK)
            | PWM_SHCR_CNT_UPDATE_EDGE_SET(is_falling_edge));
}
 
static inline void pwm_set_force_shadow_trig_edge(PWM_Type *pwm_x,
                                                   bool is_falling_edge)
{
    pwm_x->SHCR = ((pwm_x->SHCR & ~PWM_SHCR_FORCE_UPDATE_EDGE_MASK)
            | PWM_SHCR_FORCE_UPDATE_EDGE_SET(is_falling_edge));
}
 
#endif
static inline void pwm_cmp_disable_half_clock(PWM_Type *pwm_x, uint8_t index)
{
    pwm_x->CMP[index] &= ~PWM_CMP_CMPHLF_MASK;
}
 
static inline void pwm_cmp_enable_half_clock(PWM_Type *pwm_x, uint8_t index)
{
    pwm_x->CMP[index] |= PWM_CMP_CMPHLF_MASK;
}
 
static inline void pwm_cmp_update_jitter_value(PWM_Type *pwm_x, uint8_t index, uint8_t jitter)
{
    pwm_x->CMP[index] = (pwm_x->CMP[index] & ~PWM_CMP_CMPJIT_MASK) | PWM_CMP_CMPJIT_SET(jitter);
}
 
static inline void pwm_cmp_update_cmp_value(PWM_Type *pwm_x, uint8_t index,
                                            uint32_t cmp, uint16_t ex_cmp)
{
    pwm_x->CMP[index] = (pwm_x->CMP[index] & ~(PWM_CMP_CMP_MASK | PWM_CMP_XCMP_MASK))
        | PWM_CMP_CMP_SET(cmp) | PWM_CMP_XCMP_SET(ex_cmp);
}
 
static inline uint32_t pwm_cmp_get_cmp_value(PWM_Type *pwm_x, uint8_t index)
{
    return PWM_CMP_CMP_GET(pwm_x->CMP[index]);
}
 
static inline uint32_t pwm_cmp_get_excmp_value(PWM_Type *pwm_x, uint8_t index)
{
    return PWM_CMP_XCMP_GET(pwm_x->CMP[index]);
}
 
static inline void pwm_fault_recovery_update_cmp_value(PWM_Type *pwm_x, uint8_t index,
                                            uint32_t cmp)
{
    pwm_cmp_update_cmp_value(pwm_x, index, cmp, 0);
}
 
#if defined(PWM_SOC_HRPWM_SUPPORT) && PWM_SOC_HRPWM_SUPPORT
static inline void pwm_cmp_update_hrcmp_value(PWM_Type *pwm_x, uint8_t index,
                                            uint32_t cmp, uint16_t hrcmp)
{
    pwm_x->CMP_HRPWM[index] = (pwm_x->CMP_HRPWM[index] & ~(PWM_CMP_HRPWM_CMP_MASK | PWM_CMP_HRPWM_CMP_HR_MASK))
        | PWM_CMP_HRPWM_CMP_SET(cmp) | PWM_CMP_HRPWM_CMP_HR_SET(hrcmp);
}
#endif
 
static inline void pwm_cmp_force_value(PWM_Type *pwm_x, uint8_t index, uint32_t cmp)
{
    pwm_x->CMP[index] = cmp;
}
 
static inline void pwm_config_cmp(PWM_Type *pwm_x, uint8_t index, pwm_cmp_config_t *config)
{
    pwm_shadow_register_unlock(pwm_x);
    if (config->mode == pwm_cmp_mode_output_compare) {
#if defined(PWM_SOC_HRPWM_SUPPORT) && PWM_SOC_HRPWM_SUPPORT
        if (config->enable_hrcmp) {
            pwm_x->CMPCFG[index] = PWM_CMPCFG_CMPSHDWUPT_SET(config->update_trigger);
            pwm_x->CMP[index] = PWM_CMP_HRPWM_CMP_SET(config->cmp)
                        | PWM_CMP_HRPWM_CMP_HR_SET(config->hrcmp);
        } else {
#endif
            pwm_x->CMPCFG[index] = (config->enable_ex_cmp ? PWM_CMPCFG_XCNTCMPEN_MASK : 0)
                        | PWM_CMPCFG_CMPSHDWUPT_SET(config->update_trigger);
            pwm_x->CMP[index] = PWM_CMP_CMP_SET(config->cmp)
                        | PWM_CMP_XCMP_SET(config->ex_cmp)
                        | PWM_CMP_CMPHLF_SET(config->half_clock_cmp)
                        | PWM_CMP_CMPJIT_SET(config->jitter_cmp);
#if defined(PWM_SOC_HRPWM_SUPPORT) && PWM_SOC_HRPWM_SUPPORT
        }
#endif
    } else {
        pwm_x->CMPCFG[index] |= PWM_CMPCFG_CMPMODE_MASK;
    }
}
 
static inline void pwm_config_output_channel(PWM_Type *pwm_x, uint8_t index, pwm_output_channel_t *config)
{
    pwm_x->CHCFG[index] = PWM_CHCFG_CMPSELBEG_SET(config->cmp_start_index)
                            | PWM_CHCFG_CMPSELEND_SET(config->cmp_end_index)
                            | PWM_CHCFG_OUTPOL_SET(config->invert_output);
}
 
static inline void pwm_config_fault_source(PWM_Type *pwm_x, pwm_fault_source_config_t *config)
{
    pwm_x->GCR = (pwm_x->GCR & ~(PWM_GCR_FAULTI0EN_MASK | PWM_GCR_FAULTI1EN_MASK
                | PWM_GCR_FAULTI2EN_MASK | PWM_GCR_FAULTI3EN_MASK
                | PWM_GCR_FAULTE0EN_MASK | PWM_GCR_FAULTE1EN_MASK
                | PWM_GCR_FAULTRECEDG_MASK | PWM_GCR_FAULTEXPOL_MASK
                | PWM_GCR_FAULTRECHWSEL_MASK))
        | config->source_mask
        | PWM_GCR_FAULTEXPOL_SET((config->fault_external_0_active_low ? 0x1 : 0) | (config->fault_external_1_active_low ? 0x2 : 0))
        | PWM_GCR_FAULTRECEDG_SET(config->fault_recover_at_rising_edge ? 0 : 1)
        | PWM_GCR_FAULTRECHWSEL_SET(config->fault_output_recovery_trigger);
}
 
static inline void pwm_clear_fault(PWM_Type *pwm_x)
{
    pwm_x->GCR |= PWM_GCR_FAULTCLR_MASK;
    pwm_x->GCR &= ~PWM_GCR_FAULTCLR_MASK;
}
 
static inline void pwm_stop_counter(PWM_Type *pwm_x)
{
    pwm_x->GCR &= ~PWM_GCR_CEN_MASK;
}
 
static inline void pwm_start_counter(PWM_Type *pwm_x)
{
    pwm_x->GCR |= PWM_GCR_CEN_MASK;
}
 
static inline void pwm_enable_sw_force(PWM_Type *pwm_x)
{
    pwm_x->GCR |= PWM_GCR_SWFRC_MASK;
}
 
static inline void pwm_disable_sw_force(PWM_Type *pwm_x)
{
    pwm_x->GCR &= ~PWM_GCR_SWFRC_MASK;
}
 
static inline void pwm_enable_reload_at_synci(PWM_Type *pwm_x)
{
    pwm_x->GCR |= PWM_GCR_XRLDSYNCEN_MASK | PWM_GCR_RLDSYNCEN_MASK;
}
 
static inline void pwm_disable_output(PWM_Type *pwm_x, uint8_t index)
{
    pwm_x->PWMCFG[index] &= ~PWM_PWMCFG_OEN_MASK;
}
 
static inline void pwm_enable_output(PWM_Type *pwm_x, uint8_t index)
{
    pwm_x->PWMCFG[index] |= PWM_PWMCFG_OEN_MASK;
}
 
static inline void pwm_set_force_output(PWM_Type *pwm_x, uint32_t output_mask)
{
    pwm_x->FRCMD = PWM_FRCMD_FRCMD_SET(output_mask);
}
 
static inline void pwm_config_force_polarity(PWM_Type *pwm_x, bool polarity)
{
    pwm_x->GCR = (pwm_x->GCR & ~(PWM_GCR_FRCPOL_MASK)) | PWM_GCR_FRCPOL_SET(polarity);
}
 
static inline void pwm_config_force_cmd_timing(PWM_Type *pwm_x, pwm_force_cmd_timing_t timing)
{
    pwm_x->GCR = (pwm_x->GCR & ~(PWM_GCR_FRCTIME_MASK)) | PWM_GCR_FRCTIME_SET(timing);
}
 
static inline void pwm_enable_pwm_sw_force_output(PWM_Type *pwm_x, uint8_t index)
{
    pwm_x->PWMCFG[index] |= PWM_PWMCFG_OEN_MASK | PWM_PWMCFG_FRCSRCSEL_MASK
        | PWM_PWMCFG_FRCSHDWUPT_SET(pwm_shadow_register_update_on_modify);
}
 
static inline void pwm_disable_pwm_sw_force_output(PWM_Type *pwm_x, uint8_t index)
{
    pwm_x->PWMCFG[index] &= ~PWM_PWMCFG_FRCSRCSEL_MASK;
}
 
static inline void pwm_config_pwm(PWM_Type *pwm_x, uint8_t index,
                                  pwm_config_t *config, bool enable_pair_mode)
{
    pwm_x->PWMCFG[index] = PWM_PWMCFG_OEN_SET(config->enable_output)
        | PWM_PWMCFG_FRCSHDWUPT_SET(config->force_cmd_shadow_update_trigger)
        | PWM_PWMCFG_FAULTMODE_SET(config->fault_mode)
        | PWM_PWMCFG_FAULTRECTIME_SET(config->fault_recovery_trigger)
        | PWM_PWMCFG_FRCSRCSEL_SET(config->force_source)
        | PWM_PWMCFG_PAIR_SET(enable_pair_mode)
#if defined(PWM_SOC_HRPWM_SUPPORT) && PWM_SOC_HRPWM_SUPPORT
        | PWM_PWMCFG_HR_UPDATE_MODE_SET(config->hrpwm_update_mode)
#endif
        | PWM_PWMCFG_DEADAREA_SET(config->dead_zone_in_half_cycle);
}
 
static inline uint32_t pwm_get_reload_val(PWM_Type *pwm_x)
{
    return PWM_RLD_RLD_GET(pwm_x->RLD);
}
 
static inline uint32_t pwm_get_ex_reload_val(PWM_Type *pwm_x)
{
    return PWM_RLD_XRLD_GET(pwm_x->RLD);
}
 
static inline uint32_t pwm_get_counter_val(PWM_Type *pwm_x)
{
    return PWM_CNT_CNT_GET(pwm_x->CNT);
}
 
static inline uint32_t pwm_get_ex_counter_val(PWM_Type *pwm_x)
{
    return PWM_CNT_XCNT_GET(pwm_x->CNT);
}
 
hpm_stat_t pwm_load_cmp_shadow_on_match(PWM_Type *pwm_x,
                                         uint8_t index,
                                         pwm_cmp_config_t *config);
 
void pwm_get_captured_count(PWM_Type *pwm_x, uint32_t *buf, pwm_counter_type_t counter, uint8_t start_index, uint8_t num);
 
void pwm_get_default_cmp_config(PWM_Type *pwm_x, pwm_cmp_config_t *config);
 
void pwm_get_default_output_channel_config(PWM_Type *pwm_x, pwm_output_channel_t *config);
 
void pwm_get_default_pwm_config(PWM_Type *pwm_x, pwm_config_t *config);
 
void pwm_get_default_pwm_pair_config(PWM_Type *pwm_x, pwm_pair_config_t *config);
 
hpm_stat_t pwm_setup_waveform(PWM_Type *pwm_x,
                        uint8_t pwm_index, pwm_config_t *pwm_config,
                        uint8_t cmp_start_index, pwm_cmp_config_t *cmp, uint8_t cmp_num);
hpm_stat_t pwm_setup_waveform_in_pair(PWM_Type *pwm_x,
                        uint8_t pwm_index, pwm_pair_config_t *pwm_pair_config,
                        uint8_t cmp_start_index, pwm_cmp_config_t *cmp, uint8_t cmp_num);
 
hpm_stat_t pwm_update_raw_cmp_edge_aligned(PWM_Type *pwm_x, uint8_t cmp_index,
                                uint32_t target_cmp);
 
hpm_stat_t pwm_update_raw_cmp_central_aligned(PWM_Type *pwm_x, uint8_t cmp1_index,
                                       uint8_t cmp2_index, uint32_t target_cmp1, uint32_t target_cmp2);
 
 
hpm_stat_t pwm_update_duty_edge_aligned(PWM_Type *pwm_x, uint8_t cmp_index, float duty);
 
hpm_stat_t pwm_update_duty_central_aligned(PWM_Type *pwm_x, uint8_t cmp1_index,
                                       uint8_t cmp2_index, float duty);
 
#if defined(PWM_SOC_HRPWM_SUPPORT) && PWM_SOC_HRPWM_SUPPORT
 
static inline void pwm_recovery_hrpwm_output(PWM_Type *pwm_x)
{
    pwm_x->HRPWM_CFG |= PWM_HRPWM_CFG_CAL_SW_EN_MASK;
    pwm_x->ANA_CFG0 |= PWM_ANA_CFG0_CAL_SW_TRIG_H_MASK;
    pwm_x->ANA_CFG0 &= ~PWM_ANA_CFG0_CAL_SW_TRIG_H_MASK;
    pwm_x->ANA_CFG0 |= PWM_ANA_CFG0_CAL_SW_TRIG_H_MASK;
    pwm_x->ANA_CFG0 &= ~PWM_ANA_CFG0_CAL_SW_TRIG_H_MASK;
    pwm_x->HRPWM_CFG &= ~PWM_HRPWM_CFG_CAL_SW_EN_MASK;
}
 
static inline void pwm_enable_hrpwm(PWM_Type *pwm_x)
{
    pwm_x->GCR = (pwm_x->GCR & ~(PWM_GCR_HR_PWM_EN_MASK)) | PWM_GCR_HR_PWM_EN_SET(1);
}
 
static inline void pwm_disable_hrpwm(PWM_Type *pwm_x)
{
    pwm_x->GCR = pwm_x->GCR & ~(PWM_GCR_HR_PWM_EN_MASK);
}
 
static inline void pwm_start_hrpwm_counter(PWM_Type *pwm_x)
{
    pwm_start_counter(pwm_x);
    pwm_enable_hrpwm(pwm_x);
}
 
static inline void pwm_cal_hrpwm_start(PWM_Type *pwm_x)
{
    pwm_x->HRPWM_CFG |= PWM_HRPWM_CFG_CAL_START_MASK;
}
 
static inline void pwm_cal_hrpwm_chn_start(PWM_Type *pwm_x, uint8_t chn)
{
    pwm_x->HRPWM_CFG |= PWM_HRPWM_CFG_CAL_START_SET((1 << chn));
}
 
static inline void pwm_cal_hrpwm_chn_wait(PWM_Type *pwm_x, uint8_t chn)
{
    while (PWM_ANASTS_CALON_GET(pwm_x->ANASTS[chn])) {
    };
}
 
static inline uint32_t pwm_get_cal_hrpwm_status(PWM_Type *pwm_x, uint8_t chn)
{
    return PWM_ANASTS_CALON_GET(pwm_x->ANASTS[chn]);
}
 
static inline uint32_t pwm_get_hrpwm_reload_val(PWM_Type *pwm_x)
{
    return PWM_RLD_HRPWM_RLD_GET(pwm_x->RLD_HRPWM);
}
 
static inline uint32_t pwm_get_hrpwm_hr_reload_val(PWM_Type *pwm_x)
{
    return PWM_RLD_HRPWM_RLD_HR_GET(pwm_x->RLD_HRPWM);
}
 
 
hpm_stat_t pwm_update_raw_hrcmp_edge_aligned(PWM_Type *pwm_x, uint8_t cmp_index, uint32_t target_cmp,
            uint16_t target_hrcmp);
 
hpm_stat_t pwm_update_raw_hrcmp_central_aligned(PWM_Type *pwm_x, uint8_t cmp1_index,
                                       uint8_t cmp2_index, uint32_t target_cmp1, uint32_t target_cmp2,
                                        uint16_t target_hrcmp1, uint16_t target_hrcmp2);
#endif
 
#ifdef __cplusplus
}
#endif
#endif /* HPM_PWM_DRV_H */