hpm_qei_drv.h

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/*
 * Copyright (c) 2021-2025 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
 */
 
#ifndef HPM_QEI_DRV_H
#define HPM_QEI_DRV_H
 
#include "hpm_common.h"
#include "hpm_qei_regs.h"
#define QEI_EVENT_WDOG_FLAG_MASK (1U << 31) 
#define QEI_EVENT_HOME_FLAG_MASK (1U << 30) 
#define QEI_EVENT_POSITION_COMPARE_FLAG_MASK (1U << 29) 
#define QEI_EVENT_Z_PHASE_FLAG_MASK (1U << 28) 
#define QEI_EVENT_POSITIVE_COMPARE_FLAG_MASK QEI_EVENT_POSITION_COMPARE_FLAG_MASK  /* Legacy macro, kept for backwards compatibility */
 
typedef enum qei_z_count_inc_mode {
    qei_z_count_inc_on_z_input_assert = 0, 
    qei_z_count_inc_on_phase_count_max = 1, 
} qei_z_count_inc_mode_t;
 
typedef enum qei_rotation_dir_cmp {
    qei_rotation_dir_cmp_positive = 0,  
    qei_rotation_dir_cmp_negative = 1,   
    qei_rotation_dir_cmp_ignore = 2,    
} qei_rotation_dir_cmp_t;
 
typedef enum qei_counter_type {
    qei_counter_type_z = 0, 
    qei_counter_type_phase = 1, 
    qei_counter_type_speed = 2, 
    qei_counter_type_timer = 3, 
} qei_counter_type_t;
 
typedef enum qei_work_mode {
    qei_work_mode_abz = 0,  
    qei_work_mode_pd = 1,   
    qei_work_mode_ud = 2,   
} qei_work_mode_t;
 
typedef enum qei_speed_his_type {
    qei_speed_his0 = QEI_SPDHIS_SPDHIS0, 
    qei_speed_his1 = QEI_SPDHIS_SPDHIS1, 
    qei_speed_his2 = QEI_SPDHIS_SPDHIS2, 
    qei_speed_his3 = QEI_SPDHIS_SPDHIS3, 
} qei_speed_his_type_t;
 
typedef struct {
    qei_work_mode_t work_mode;
    qei_z_count_inc_mode_t z_count_inc_mode;
    uint32_t phcnt_max;
    bool z_cali_enable;
    uint32_t phcnt_idx;
} qei_mode_config_t;      
typedef struct {
    bool h_fall_dir_forward;
    bool h_fall_dir_reverse;
    bool h_rise_dir_forward;
    bool h_rise_dir_reverse;
    bool h_valid_reset_spdcnt;
    bool h_valid_reset_phcnt;
    bool h_valid_reset_zcnt;
} qei_h_phase_config_t;      
typedef struct {
    bool pause_valid_pause_spdcnt;
    bool pause_valid_pause_phcnt;
    bool pause_valid_pause_zcnt;
} qei_pause_config_t;      
#ifdef __cplusplus
extern "C" {
#endif
 
static inline void qei_wdog_enable(QEI_Type *qei_x)
{
    qei_x->WDGCFG |= QEI_WDGCFG_WDGEN_MASK;
}
 
static inline void qei_wdog_disable(QEI_Type *qei_x)
{
    qei_x->WDGCFG &= ~QEI_WDGCFG_WDGEN_MASK;
}
 
static inline void qei_wdog_config(QEI_Type *qei_x, uint32_t timeout, bool enable)
{
    qei_x->WDGCFG = QEI_WDGCFG_WDGTO_SET(timeout) | QEI_WDGCFG_WDGEN_SET(enable);
}
 
static inline void qei_phase_config(QEI_Type *qei_x, uint32_t phase_count,
                              qei_z_count_inc_mode_t mode, bool z_calibrate)
{
    qei_x->PHCFG = QEI_PHCFG_ZCNTCFG_SET(mode) | QEI_PHCFG_PHCALIZ_SET(z_calibrate)
                | QEI_PHCFG_PHMAX_SET(phase_count - 1);
}
 
static inline void qei_phase_set_index(QEI_Type *qei_x, uint32_t phase_index)
{
    qei_x->PHIDX = QEI_PHIDX_PHIDX_SET(phase_index);
}
 
static inline void qei_output_trigger_event_enable(QEI_Type *qei_x, uint32_t event_mask)
{
    qei_x->TRGOEN |= event_mask;
}
 
static inline void qei_output_trigger_event_disable(QEI_Type *qei_x, uint32_t event_mask)
{
    qei_x->TRGOEN &= ~event_mask;
}
 
static inline void qei_load_read_trigger_event_enable(QEI_Type *qei_x, uint32_t event_mask)
{
    qei_x->READEN |= event_mask;
}
 
static inline void qei_load_read_trigger_event_disable(QEI_Type *qei_x, uint32_t event_mask)
{
    qei_x->READEN &= ~event_mask;
}
 
static inline void qei_z_cmp_set(QEI_Type *qei_x, uint32_t cmp)
{
    qei_x->ZCMP = QEI_ZCMP_ZCMP_SET(cmp);
}
 
static inline void qei_speed_cmp_set(QEI_Type *qei_x, uint32_t cmp)
{
    qei_x->SPDCMP = QEI_SPDCMP_SPDCMP_SET(cmp);
}
 
static inline void qei_phase_cmp_set(QEI_Type *qei_x, uint32_t cmp,
                            bool cmp_z, qei_rotation_dir_cmp_t rotation_dir)
{
    qei_x->PHCMP = QEI_PHCMP_PHCMP_SET(cmp)
        | QEI_PHCMP_ZCMPDIS_SET(!cmp_z)
        | ((rotation_dir == qei_rotation_dir_cmp_ignore)
                ? QEI_PHCMP_DIRCMPDIS_MASK : (QEI_PHCMP_DIRCMP_SET(rotation_dir)));
}
 
static inline void qei_clear_status(QEI_Type *qei_x, uint32_t mask)
{
    qei_x->SR = mask;
}
 
static inline uint32_t qei_get_status(QEI_Type *qei_x)
{
    return qei_x->SR;
}
 
static inline bool qei_get_bit_status(QEI_Type *qei_x, uint32_t mask)
{
    if ((qei_x->SR & mask) == mask) {
        return true;
    } else {
        return false;
    }
}
 
static inline void qei_irq_enable(QEI_Type *qei_x, uint32_t mask)
{
    qei_x->IRQEN |= mask;
}
 
static inline void qei_irq_disable(QEI_Type *qei_x, uint32_t mask)
{
    qei_x->IRQEN &= ~mask;
}
 
static inline void qei_dma_request_enable(QEI_Type *qei_x, uint32_t mask)
{
    qei_x->DMAEN |= mask;
}
 
static inline void qei_dma_request_disable(QEI_Type *qei_x, uint32_t mask)
{
    qei_x->DMAEN &= ~mask;
}
 
static inline uint32_t qei_get_current_count(QEI_Type *qei_x,
                                            qei_counter_type_t type)
{
    return *(&qei_x->COUNT[QEI_COUNT_CURRENT].Z + type);
}
 
static inline uint32_t qei_get_current_phase_phcnt(QEI_Type *qei_x)
{
    return QEI_COUNT_PH_PHCNT_GET(qei_get_current_count(qei_x, qei_counter_type_phase));
}
 
static inline bool qei_get_current_phase_astat(QEI_Type *qei_x)
{
    return QEI_COUNT_PH_ASTAT_GET(qei_get_current_count(qei_x, qei_counter_type_phase));
}
 
static inline bool qei_get_current_phase_bstat(QEI_Type *qei_x)
{
    return QEI_COUNT_PH_BSTAT_GET(qei_get_current_count(qei_x, qei_counter_type_phase));
}
 
static inline bool qei_get_current_phase_dir(QEI_Type *qei_x)
{
    return QEI_COUNT_PH_DIR_GET(qei_get_current_count(qei_x, qei_counter_type_phase));
}
 
static inline uint32_t qei_get_count_on_read_event(QEI_Type *qei_x,
                                            qei_counter_type_t type)
{
    return *(&(qei_x->COUNT[QEI_COUNT_READ].Z) + type);
}
 
static inline uint32_t qei_get_count_on_snap0_event(QEI_Type *qei_x,
                                            qei_counter_type_t type)
{
    return *(&qei_x->COUNT[QEI_COUNT_SNAP0].Z + type);
}
 
static inline uint32_t qei_get_count_on_snap1_event(QEI_Type *qei_x,
                                            qei_counter_type_t type)
{
    return *(&qei_x->COUNT[QEI_COUNT_SNAP1].Z + type);
}
 
static inline uint32_t qei_get_speed_history(QEI_Type *qei_x, qei_speed_his_type_t hist_index)
{
    return QEI_SPDHIS_SPDHIS0_GET(qei_x->SPDHIS[hist_index]);
}
 
static inline void qei_load_counter_to_read_registers(QEI_Type *qei_x)
{
    qei_x->CR |= QEI_CR_READ_MASK;
}
 
static inline void qei_reset_counter_on_h_assert(QEI_Type *qei_x,
                                               uint32_t counter_mask)
{
    qei_x->CR |= counter_mask << 16;
}
 
static inline void qei_pause_counter_on_pause(QEI_Type *qei_x,
                                               uint32_t counter_mask)
{
    qei_x->CR |= counter_mask << 12;
}
 
static inline void qei_snap_enable(QEI_Type *qei_x)
{
    qei_x->CR |= QEI_CR_SNAPEN_MASK;
}
 
static inline void qei_snap_disable(QEI_Type *qei_x)
{
    qei_x->CR &= ~QEI_CR_SNAPEN_MASK;
}
 
static inline void qei_counter_reset_assert(QEI_Type *qei_x)
{
    qei_x->CR |= QEI_CR_RSTCNT_MASK;
}
 
static inline void qei_counter_reset_release(QEI_Type *qei_x)
{
    qei_x->CR &= ~QEI_CR_RSTCNT_MASK;
}
 
static inline void qei_set_work_mode(QEI_Type *qei_x, qei_work_mode_t mode)
{
    qei_x->CR = (qei_x->CR & ~QEI_CR_ENCTYP_MASK) | QEI_CR_ENCTYP_SET(mode);
}
 
void qei_config_mode(QEI_Type *qei_x, qei_mode_config_t *config);
 
void qei_config_h_phase(QEI_Type *qei_x, qei_h_phase_config_t *config);
 
void qei_config_pause(QEI_Type *qei_x, qei_pause_config_t *config);
 
#ifdef __cplusplus
}
#endif
#endif /* HPM_QEI_DRV_H */