hpm_sei_drv.h

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/*
 * Copyright (c) 2023-2025 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
 */
 
#ifndef HPM_SEI_DRV_H
#define HPM_SEI_DRV_H
 
#include "hpm_common.h"
#include "hpm_soc_feature.h"
#include "hpm_sei_regs.h"
 
typedef enum {
    sei_arming_direct_exec = 0,
    sei_arming_wait_trigger
} sei_arming_mode_t;
 
typedef enum {
    sei_wdg_exec_next_instr = 0,
    sei_wdg_exec_exception_instr
} sei_wdg_action_t;
 
typedef enum {
    sei_synchronous_master_mode = 0,
    sei_synchronous_slave_mode,
    sei_asynchronous_mode
} sei_transceiver_mode_t;
 
typedef enum {
    sei_asynchronous_parity_even = 0,
    sei_asynchronous_parity_odd
} sei_asynchronous_parity_t;
 
typedef enum {
    sei_idle_low_state = 0,
    sei_idle_high_state,
} sei_idle_state_t;
 
typedef enum {
    sei_data_mode = 0,
    sei_check_mode,
    sei_crc_mode
} sei_data_mode_t;
 
typedef enum {
    sei_bit_lsb_first = 0,
    sei_bit_msb_first
} sei_data_bit_order_t;
 
typedef enum {
    sei_word_nonreverse = 0,
    sei_word_reverse
} sei_data_word_order_t;
 
typedef enum {
    sei_state_tran_condition_high_match = 0,
    sei_state_tran_condition_low_dismatch,
    sei_state_tran_condition_rise_entry,
    sei_state_tran_condition_fall_leave
} sei_state_tran_condition_t;
 
typedef enum {
    sei_trig_in0 = 0,
    sei_trig_in1,
    sei_trig_in_period,
    sei_trig_in_soft
} sei_trig_in_type_t;      
typedef enum {
    sei_irq_stall_event = SEI_CTRL_IRQ_INT_FLAG_STALL_MASK,
    sei_irq_execpt_event = SEI_CTRL_IRQ_INT_FLAG_EXCEPT_MASK,
    sei_irq_wdog_event = SEI_CTRL_IRQ_INT_FLAG_WDOG_MASK,
    sei_irq_instr_ptr0_start_event = SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_MASK,
    sei_irq_instr_ptr1_start_event = SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_MASK,
    sei_irq_instr_value0_start_event = SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_MASK,
    sei_irq_instr_value1_start_event = SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_MASK,
    sei_irq_instr_ptr0_end_event = SEI_CTRL_IRQ_INT_FLAG_PTR0_END_MASK,
    sei_irq_instr_ptr1_end_event = SEI_CTRL_IRQ_INT_FLAG_PTR1_END_MASK,
    sei_irq_instr_value0_end_event = SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_MASK,
    sei_irq_instr_value1_end_event = SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_MASK,
    sei_irq_trx_err_event = SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_MASK,
    sei_irq_timeout_event = SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_MASK,
    sei_irq_latch0_event = SEI_CTRL_IRQ_INT_FLAG_LATCH0_MASK,
    sei_irq_latch1_event = SEI_CTRL_IRQ_INT_FLAG_LATCH1_MASK,
    sei_irq_latch2_event = SEI_CTRL_IRQ_INT_FLAG_LATCH2_MASK,
    sei_irq_latch3_event = SEI_CTRL_IRQ_INT_FLAG_LATCH3_MASK,
    sei_irq_sample_err_event = SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_MASK,
    sei_irq_trig0_event = SEI_CTRL_IRQ_INT_FLAG_TRIGER0_MASK,
    sei_irq_trig1_event = SEI_CTRL_IRQ_INT_FLAG_TRIGER1_MASK,
    sei_irq_trig2_event = SEI_CTRL_IRQ_INT_FLAG_TRIGER2_MASK,
    sei_irq_trig3_event = SEI_CTRL_IRQ_INT_FLAG_TRIGER3_MASK,
    sei_irq_trig0_err_event = SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_MASK,
    sei_irq_trig1_err_event = SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_MASK,
    sei_irq_trig2_err_event = SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_MASK,
    sei_irq_trig3_err_event = SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_MASK,
} sei_irq_event_t;      
typedef enum {
    sei_dma_en_stall_event = SEI_CTRL_DMA_EN_STALL_MASK,
    sei_dma_en_execpt_event = SEI_CTRL_DMA_EN_EXCEPT_MASK,
    sei_dma_en_wdog_event = SEI_CTRL_DMA_EN_WDOG_MASK,
    sei_dma_en_instr_ptr0_start_event = SEI_CTRL_DMA_EN_PTR0_ST_MASK,
    sei_dma_en_instr_ptr1_start_event = SEI_CTRL_DMA_EN_PTR1_ST_MASK,
    sei_dma_en_instr_value0_start_event = SEI_CTRL_DMA_EN_INSTR0_ST_MASK,
    sei_dma_en_instr_value1_start_event = SEI_CTRL_DMA_EN_INSTR1_ST_MASK,
    sei_dma_en_instr_ptr0_end_event = SEI_CTRL_DMA_EN_PTR0_END_MASK,
    sei_dma_en_instr_ptr1_end_event = SEI_CTRL_DMA_EN_PTR1_END_MASK,
    sei_dma_en_instr_value0_end_event = SEI_CTRL_DMA_EN_INSTR0_END_MASK,
    sei_dma_en_instr_value1_end_event = SEI_CTRL_DMA_EN_INSTR1_END_MASK,
    sei_dma_en_trx_err_event = SEI_CTRL_DMA_EN_TRX_ERR_MASK,
    sei_dma_en_timeout_event = SEI_CTRL_DMA_EN_TIMEOUT_MASK,
    sei_dma_en_latch0_event = SEI_CTRL_DMA_EN_LATCH0_MASK,
    sei_dma_en_latch1_event = SEI_CTRL_DMA_EN_LATCH1_MASK,
    sei_dma_en_latch2_event = SEI_CTRL_DMA_EN_LATCH2_MASK,
    sei_dma_en_latch3_event = SEI_CTRL_DMA_EN_LATCH3_MASK,
    sei_dma_en_sample_err_event = SEI_CTRL_DMA_EN_SMP_ERR_MASK,
    sei_dma_en_trig0_event = SEI_CTRL_DMA_EN_TRIGER0_MASK,
    sei_dma_en_trig1_event = SEI_CTRL_DMA_EN_TRIGER1_MASK,
    sei_dma_en_trig2_event = SEI_CTRL_DMA_EN_TRIGER2_MASK,
    sei_dma_en_trig3_event = SEI_CTRL_DMA_EN_TRIGER3_MASK,
    sei_dma_en_trig0_err_event = SEI_CTRL_DMA_EN_TRG_ERR0_MASK,
    sei_dma_en_trig1_err_event = SEI_CTRL_DMA_EN_TRG_ERR1_MASK,
    sei_dma_en_trig2_err_event = SEI_CTRL_DMA_EN_TRG_ERR2_MASK,
    sei_dma_en_trig3_err_event = SEI_CTRL_DMA_EN_TRG_ERR3_MASK,
} sei_dma_en_t;      
#define SEI_SELECT_CMD true      
#define SEI_SELECT_DATA false    
#define SEI_DAT_CMD           (1UL)
#define SEI_DATA_CONST_0      (30UL)
#define SEI_DATA_CONST_1      (31UL)
 
#define SEI_INSTR_OP_HALT 0u      
#define SEI_INSTR_OP_JUMP 1u      
#define SEI_INSTR_OP_SEND_WDG 2u  
#define SEI_INSTR_OP_SEND 3u      
#define SEI_INSTR_OP_WAIT_WDG 4u  
#define SEI_INSTR_OP_WAIT 5u      
#define SEI_INSTR_OP_RECV_WDG 6u  
#define SEI_INSTR_OP_RECV 7u      
#define SEI_INSTR_M_CK_LOW 0u            
#define SEI_INSTR_M_CK_RISE_FALL 1u      
#define SEI_INSTR_M_CK_FALL_RISE 2u      
#define SEI_INSTR_M_CK_HIGH 3u           
#define SEI_INSTR_S_CK_DEFAULT 0u                
#define SEI_INSTR_S_CK_TRX_EXCH 1u               
#define SEI_INSTR_S_CK_TIMEOUT_EN 2u             
#define SEI_INSTR_S_CK_TRX_EXCH_TIMEOUT_EN 3u    
#define SEI_SYNC_SLAVE_RX_TX_POINT_ON_RISE_EDGE 0x8002
#define SEI_SYNC_SLAVE_RX_TX_POINT_ON_FALL_EDGE 0x0002
 
#define SEI_JUMP_INIT_INSTR_IDX 0x00u             
#define SEI_JUMP_WDG_INSTR_IDX 0x01u              
#define SEI_JUMP_CMD_TABLE_INSTR_IDX0 0x10u       
#define SEI_JUMP_CMD_TABLE_INSTR_IDX1 0x11u       
#define SEI_JUMP_CMD_TABLE_INSTR_IDX2 0x12u       
#define SEI_JUMP_CMD_TABLE_INSTR_IDX3 0x13u       
#define SEI_JUMP_CMD_TABLE_INSTR_IDX4 0x14u       
#define SEI_JUMP_CMD_TABLE_INSTR_IDX5 0x15u       
#define SEI_JUMP_CMD_TABLE_INSTR_IDX6 0x16u       
#define SEI_JUMP_CMD_TABLE_INSTR_IDX7 0x17u       
#define SEI_JUMP_CMD_TABLE_INSTR_IDX8 0x18u       
#define SEI_JUMP_CMD_TABLE_INSTR_IDX9 0x19u       
#define SEI_JUMP_CMD_TABLE_INSTR_IDX10 0x1Au      
#define SEI_JUMP_CMD_TABLE_INSTR_IDX11 0x1Bu      
#define SEI_JUMP_CMD_TABLE_INSTR_IDX12 0x1Cu      
#define SEI_JUMP_CMD_TABLE_INSTR_IDX13 0x1Du      
#define SEI_JUMP_CMD_TABLE_INSTR_IDX14 0x1Eu      
#define SEI_JUMP_CMD_TABLE_INSTR_IDX15 0x1Fu      
typedef struct {
    sei_arming_mode_t arming_mode;
    uint8_t data_cdm_idx;
    uint8_t data_base_idx;
    uint8_t init_instr_idx;
    bool wdg_enable;
    sei_wdg_action_t wdg_action;
    uint8_t wdg_instr_idx;
    uint16_t wdg_time;
} sei_engine_config_t;      
typedef struct {
    bool data_idle_high_z;
    sei_idle_state_t data_idle_state;
    bool clock_idle_high_z;
    sei_idle_state_t clock_idle_state;
    uint32_t baudrate;
} sei_transceiver_synchronous_master_config_t;      
typedef struct {
    bool data_idle_high_z;
    sei_idle_state_t data_idle_state;
    bool clock_idle_high_z;
    sei_idle_state_t clock_idle_state;
    uint32_t max_baudrate;
    uint16_t ck0_timeout_us;
    uint16_t ck1_timeout_us;
} sei_transceiver_synchronous_slave_config_t;      
typedef struct {
    uint8_t wait_len;
    uint8_t data_len;
    bool parity_enable;
    sei_asynchronous_parity_t parity;
    bool data_idle_high_z;
    sei_idle_state_t data_idle_state;
    uint32_t baudrate;
} sei_transceiver_asynchronous_config_t;      
typedef struct {
    sei_transceiver_mode_t mode;
    bool tri_sample;
    uint32_t src_clk_freq;
    sei_transceiver_synchronous_master_config_t synchronous_master_config;
    sei_transceiver_synchronous_slave_config_t synchronous_slave_config;
    sei_transceiver_asynchronous_config_t asynchronous_config;
} sei_transceiver_config_t;             
typedef struct {
    bool trig_in0_enable;
    uint8_t trig_in0_select;
    bool trig_in1_enable;
    uint8_t trig_in1_select;
    bool trig_period_enable;
    sei_arming_mode_t trig_period_arming_mode;
    bool trig_period_sync_enable;
    uint8_t trig_period_sync_select;
    uint32_t trig_period_time;
#if defined(HPM_IP_FEATURE_SEI_TRIG_IN_DIV) && HPM_IP_FEATURE_SEI_TRIG_IN_DIV
    uint8_t trig_in0_div;
    uint8_t trig_in1_div;
#endif
} sei_trigger_input_config_t;      
typedef struct {
    uint8_t src_latch_select;
    bool trig_out_enable;
    uint8_t trig_out_select;
} sei_trigger_output_config_t;      
typedef struct {
    sei_data_mode_t mode;
    bool signed_flag;
    sei_data_bit_order_t bit_order;
    sei_data_word_order_t word_order;
    uint8_t word_len;
    bool crc_invert;
    bool crc_shift_mode;
    uint8_t crc_len;
    uint8_t last_bit;
    uint8_t first_bit;
    uint8_t max_bit;
    uint8_t min_bit;
    uint32_t gold_value;
    uint32_t crc_init_value;
    uint32_t crc_poly;
} sei_data_format_config_t;      
typedef struct {
    uint32_t cmd_min_value;
    uint32_t cmd_max_value;
    uint32_t cmd_mask_value;
    uint8_t instr_idx[8];
} sei_command_table_config_t;      
typedef struct {
    bool disable_instr_ptr_check;
    sei_state_tran_condition_t instr_ptr_cfg;
    uint8_t instr_ptr_value;
    bool disable_clk_check;
    sei_state_tran_condition_t clk_cfg;
    bool disable_txd_check;
    sei_state_tran_condition_t txd_cfg;
    bool disable_rxd_check;
    sei_state_tran_condition_t rxd_cfg;
    bool disable_timeout_check;
    sei_state_tran_condition_t timeout_cfg;
} sei_state_transition_config_t;      
typedef struct {
    bool enable;
    uint8_t output_select;
    uint16_t delay;
} sei_state_transition_latch_config_t;      
typedef struct {
    uint8_t acc_data_idx;
    uint8_t spd_data_idx;
    uint8_t rev_data_idx;
    uint8_t pos_data_idx;
    bool acc_data_use_rx;      
    bool spd_data_use_rx;      
    bool rev_data_use_rx;      
    bool pos_data_use_rx;      
    uint8_t latch_select;
    bool sample_once;
    uint16_t sample_window;
    uint32_t data_register_select;
} sei_sample_config_t;      
typedef struct {
    uint8_t acc_data_idx;
    uint8_t spd_data_idx;
    uint8_t rev_data_idx;
    uint8_t pos_data_idx;
    bool acc_data_use_rx;      
    bool spd_data_use_rx;      
    bool rev_data_use_rx;      
    bool pos_data_use_rx;      
    bool time_use_override;    
    bool update_on_err;
    uint8_t latch_select;
    uint32_t data_register_select;
} sei_update_config_t;      
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
 
static inline void sei_set_engine_enable(SEI_Type *ptr, uint8_t idx, bool enable)
{
    if (enable) {
        ptr->CTRL[idx].ENGINE.CTRL |= SEI_CTRL_ENGINE_CTRL_ENABLE_MASK;
    } else {
        ptr->CTRL[idx].ENGINE.CTRL &= ~SEI_CTRL_ENGINE_CTRL_ENABLE_MASK;
    }
}
 
static inline void sei_set_engine_rewind(SEI_Type *ptr, uint8_t idx)
{
    ptr->CTRL[idx].ENGINE.CTRL |= SEI_CTRL_ENGINE_CTRL_REWIND_MASK;
}
 
static inline void sei_set_engine_init_instr_idx(SEI_Type *ptr, uint8_t idx, uint8_t init_instr_idx)
{
    ptr->CTRL[idx].ENGINE.PTR_CFG = (ptr->CTRL[idx].ENGINE.PTR_CFG & ~SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_MASK)
                                    | SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SET(init_instr_idx);
}
 
static inline void sei_set_engine_wdg_instr_idx(SEI_Type *ptr, uint8_t idx, uint8_t wdg_instr_idx)
{
    ptr->CTRL[idx].ENGINE.PTR_CFG = (ptr->CTRL[idx].ENGINE.PTR_CFG & ~SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_MASK)
                                    | SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SET(wdg_instr_idx);
}
 
static inline void sei_set_engine_data_base_idx(SEI_Type *ptr, uint8_t idx, uint8_t data_base_idx)
{
    ptr->CTRL[idx].ENGINE.PTR_CFG = (ptr->CTRL[idx].ENGINE.PTR_CFG & ~SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_MASK)
                                    | SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SET(data_base_idx);
}
 
static inline void sei_set_trig_input_in0_enable(SEI_Type *ptr, uint8_t idx, bool enable)
{
    if (enable) {
        ptr->CTRL[idx].TRG.IN_CFG |= SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK;
    } else {
        ptr->CTRL[idx].TRG.IN_CFG &= ~SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK;
    }
}
 
static inline void sei_set_trig_input_in1_enable(SEI_Type *ptr, uint8_t idx, bool enable)
{
    if (enable) {
        ptr->CTRL[idx].TRG.IN_CFG |= SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK;
    } else {
        ptr->CTRL[idx].TRG.IN_CFG &= ~SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK;
    }
}
 
static inline void sei_set_trig_input_period_enable(SEI_Type *ptr, uint8_t idx, bool enable)
{
    if (enable) {
        ptr->CTRL[idx].TRG.IN_CFG |= SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK;
    } else {
        ptr->CTRL[idx].TRG.IN_CFG &= ~SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK;
    }
}
 
static inline void sei_set_trig_input_soft_enable(SEI_Type *ptr, uint8_t idx)
{
    ptr->CTRL[idx].TRG.SW |= SEI_CTRL_TRG_SW_SOFT_MASK;
}
 
static inline void sei_set_trig_input_command_value(SEI_Type *ptr, uint8_t idx, sei_trig_in_type_t type, uint32_t data)
{
    ptr->CTRL[idx].TRG_TABLE.CMD[type] = data;
}
 
static inline uint32_t sei_get_trig_input_time(SEI_Type *ptr, uint8_t idx, sei_trig_in_type_t type)
{
    return ptr->CTRL[idx].TRG_TABLE.TIME[type];
}
 
static inline uint32_t sei_get_latch_time(SEI_Type *ptr, uint8_t idx, uint8_t latch_idx)
{
    return ptr->CTRL[idx].LATCH[latch_idx].TIME;
}
 
 static inline uint16_t sei_get_xcvr_baud_div(SEI_Type *ptr, uint8_t idx)
 {
     return SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_GET(ptr->CTRL[idx].XCVR.BAUD_CFG);
 }
 
static inline void sei_set_xcvr_rx_point(SEI_Type *ptr, uint8_t idx, uint16_t point)
{
    uint32_t tmp;
 
    assert(point > 0);
    tmp = ptr->CTRL[idx].XCVR.DATA_CFG;
    tmp &= ~SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_MASK;
    tmp |= SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SET(point);
    ptr->CTRL[idx].XCVR.DATA_CFG = tmp;
}
 
static inline void sei_set_xcvr_tx_point(SEI_Type *ptr, uint8_t idx, uint16_t point)
{
    uint32_t tmp;
 
    assert(point > 0);
    tmp = ptr->CTRL[idx].XCVR.DATA_CFG;
    tmp &= ~SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_MASK;
    tmp |= SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SET(point);
    ptr->CTRL[idx].XCVR.DATA_CFG = tmp;
}
 
static inline void sei_set_xcvr_ck0_point(SEI_Type *ptr, uint8_t idx, uint16_t point)
{
    uint32_t tmp;
 
    assert(point > 0);
    tmp = ptr->CTRL[idx].XCVR.CLK_CFG;
    tmp &= ~SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_MASK;
    tmp |= SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SET(point);
    ptr->CTRL[idx].XCVR.CLK_CFG = tmp;
}
 
static inline void sei_set_xcvr_ck1_point(SEI_Type *ptr, uint8_t idx, uint16_t point)
{
    uint32_t tmp;
 
    assert(point > 0);
    tmp = ptr->CTRL[idx].XCVR.CLK_CFG;
    tmp &= ~SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_MASK;
    tmp |= SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SET(point);
    ptr->CTRL[idx].XCVR.CLK_CFG = tmp;
}
 
static inline uint16_t sei_get_xcvr_ck0_point(SEI_Type *ptr, uint8_t idx)
{
    return SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_GET(ptr->CTRL[idx].XCVR.CLK_CFG);
}
 
static inline uint16_t sei_get_xcvr_ck1_point(SEI_Type *ptr, uint8_t idx)
{
    return SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_GET(ptr->CTRL[idx].XCVR.CLK_CFG);
}
 
static inline uint32_t sei_get_command_value(SEI_Type *ptr, uint8_t idx)
{
    return ptr->CTRL[idx].CMD.CMD;
}
 
static inline void sei_set_command_rewind(SEI_Type *ptr, uint8_t idx)
{
    ptr->CTRL[idx].CMD.MODE |= SEI_CTRL_CMD_MODE_REWIND_MASK;
}
 
#if defined(HPM_IP_FEATURE_SEI_LATCH_REWIND_CMD) && HPM_IP_FEATURE_SEI_LATCH_REWIND_CMD
static inline void sei_config_command_rewind_by_latch(SEI_Type *ptr, uint8_t idx, uint8_t latch_select, bool enable)
{
   ptr->CTRL[idx].TRG.IN_CFG = (ptr->CTRL[idx].TRG.IN_CFG & ~(SEI_CTRL_TRG_IN_CFG_REWIND_EN_MASK | SEI_CTRL_TRG_IN_CFG_REWIND_SEL_MASK))
                             | (SEI_CTRL_TRG_IN_CFG_REWIND_EN_SET(enable) | SEI_CTRL_TRG_IN_CFG_REWIND_SEL_SET(latch_select));
}
#endif
 
static inline void sei_set_data_value(SEI_Type *ptr, uint8_t idx, uint32_t data)
{
    ptr->DAT[idx].DATA = data;
}
 
static inline uint32_t sei_get_data_value(SEI_Type *ptr, uint8_t idx)
{
    return ptr->DAT[idx].DATA;
}
 
static inline void sei_set_data_rewind(SEI_Type *ptr, uint8_t idx)
{
    ptr->DAT[idx].MODE |= SEI_DAT_MODE_REWIND_MASK;
}
 
static inline void sei_set_sample_pos_override_value(SEI_Type *ptr, uint8_t idx, uint32_t data)
{
    ptr->CTRL[idx].POS.SMP_POS = data;
}
 
static inline void sei_set_sample_rev_override_value(SEI_Type *ptr, uint8_t idx, uint32_t data)
{
    ptr->CTRL[idx].POS.SMP_REV = data;
}
 
static inline void sei_set_sample_spd_override_value(SEI_Type *ptr, uint8_t idx, uint32_t data)
{
    ptr->CTRL[idx].POS.SMP_SPD = data;
}
 
static inline void sei_set_sample_acc_override_value(SEI_Type *ptr, uint8_t idx, uint32_t data)
{
    ptr->CTRL[idx].POS.SMP_ACC = data;
}
 
static inline void sei_set_update_pos_override_value(SEI_Type *ptr, uint8_t idx, uint32_t data)
{
    ptr->CTRL[idx].POS.UPD_POS = data;
}
 
static inline void sei_set_update_rev_override_value(SEI_Type *ptr, uint8_t idx, uint32_t data)
{
    ptr->CTRL[idx].POS.UPD_REV = data;
}
 
static inline void sei_set_update_spd_override_value(SEI_Type *ptr, uint8_t idx, uint32_t data)
{
    ptr->CTRL[idx].POS.UPD_SPD = data;
}
 
static inline void sei_set_update_acc_override_value(SEI_Type *ptr, uint8_t idx, uint32_t data)
{
    ptr->CTRL[idx].POS.UPD_ACC = data;
}
 
static inline void sei_set_update_time_override_value(SEI_Type *ptr, uint8_t idx, uint32_t data)
{
    ptr->CTRL[idx].POS.UPD_TIME = data;
}
 
static inline void sei_set_irq_match_instr0_ptr(SEI_Type *ptr, uint8_t idx, uint8_t instr_idx)
{
    ptr->CTRL[idx].IRQ.POINTER0 = SEI_CTRL_IRQ_POINTER0_POINTER_SET(instr_idx);
}
 
static inline void sei_set_irq_match_instr1_ptr(SEI_Type *ptr, uint8_t idx, uint8_t instr_idx)
{
    ptr->CTRL[idx].IRQ.POINTER1 = SEI_CTRL_IRQ_POINTER1_POINTER_SET(instr_idx);
}
 
static inline void sei_set_irq_match_instr0_value(SEI_Type *ptr, uint8_t idx, uint32_t instr_value)
{
    ptr->CTRL[idx].IRQ.INSTR0 = SEI_CTRL_IRQ_INSTR0_INSTR_SET(instr_value);
}
 
static inline void sei_set_irq_match_instr1_value(SEI_Type *ptr, uint8_t idx, uint32_t instr_value)
{
    ptr->CTRL[idx].IRQ.INSTR1 = SEI_CTRL_IRQ_INSTR1_INSTR_SET(instr_value);
}
 
static inline void sei_set_irq_enable(SEI_Type *ptr, uint8_t idx, uint32_t irq_mask, bool enable)
{
    if (enable) {
        ptr->CTRL[idx].IRQ.INT_EN |= irq_mask;
    } else {
        ptr->CTRL[idx].IRQ.INT_EN &= ~irq_mask;
    }
}
 
static inline uint32_t sei_get_irq_enable_status(SEI_Type *ptr, uint8_t idx)
{
     return ptr->CTRL[idx].IRQ.INT_EN;
}
 
static inline bool sei_get_irq_status(SEI_Type *ptr, uint8_t idx, uint32_t irq_mask)
{
    return ((ptr->CTRL[idx].IRQ.INT_FLAG & irq_mask) == irq_mask) ? true : false;
}
 
 static inline uint32_t sei_get_irq_flag(SEI_Type *ptr, uint8_t idx)
 {
     return ptr->CTRL[idx].IRQ.INT_FLAG;
 }
 
static inline void sei_clear_irq_flag(SEI_Type *ptr, uint8_t idx, uint32_t irq_mask)
{
    ptr->CTRL[idx].IRQ.INT_FLAG = irq_mask;
}
 
static inline void sei_set_dma_req_enable(SEI_Type *ptr, uint8_t idx, uint32_t dma_en_mask, bool enable)
{
    if (enable) {
        ptr->CTRL[idx].DMA_EN |= dma_en_mask;
    } else {
        ptr->CTRL[idx].DMA_EN &= ~dma_en_mask;
    }
}
 
hpm_stat_t sei_transceiver_config_init(SEI_Type *ptr, uint8_t idx, sei_transceiver_config_t *config);
 
hpm_stat_t sei_cmd_data_format_config_init(SEI_Type *ptr, bool cmd_data_select, uint8_t idx, sei_data_format_config_t *config);
 
hpm_stat_t sei_cmd_table_config_init(SEI_Type *ptr, uint8_t idx, uint8_t table_idx, sei_command_table_config_t *config);
 
hpm_stat_t sei_state_transition_config_init(SEI_Type *ptr, uint8_t idx, uint8_t latch_idx, uint8_t state, sei_state_transition_config_t *config);
 
hpm_stat_t sei_state_transition_latch_config_init(SEI_Type *ptr, uint8_t idx, uint8_t latch_idx, sei_state_transition_latch_config_t *config);
 
hpm_stat_t sei_sample_config_init(SEI_Type *ptr, uint8_t idx, sei_sample_config_t *config);
 
hpm_stat_t sei_update_config_init(SEI_Type *ptr, uint8_t idx, sei_update_config_t *config);
 
hpm_stat_t sei_trigger_input_config_init(SEI_Type *ptr, uint8_t idx, sei_trigger_input_config_t *config);
 
hpm_stat_t sei_trigger_output_config_init(SEI_Type *ptr, uint8_t idx, sei_trigger_output_config_t *config);
 
hpm_stat_t sei_engine_config_init(SEI_Type *ptr, uint8_t idx, sei_engine_config_t *config);
 
void sei_set_instr(SEI_Type *ptr, uint8_t idx, uint8_t op, uint8_t ck, uint8_t crc, uint8_t data, uint8_t opr);
 
uint32_t sei_get_crc_value(SEI_Type *ptr, uint8_t idx);
 
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif