HPM SDK
HPMicro Software Development Kit
hpm_tsw_regs.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_TSW_H
10 #define HPM_TSW_H
11 
12 typedef struct {
13  __R uint8_t RESERVED0[4]; /* 0x0 - 0x3: Reserved */
14  __RW uint32_t LU_MAIN_CTRL; /* 0x4: LU_MAIN control */
15  __RW uint32_t LU_MAIN_HITMEM; /* 0x8: LU_MAIN hit */
16  __R uint32_t LU_MAIN_PARAM; /* 0xC: LU_MAIN parameter */
17  __RW uint32_t LU_MAIN_BYPASS; /* 0x10: LU_MAIN bypass */
18  __RW uint32_t LU_MAIN_PCP_REMAP; /* 0x14: LU_MAIN PCP remap */
19  __R uint32_t LU_MAIN_VERSION; /* 0x18: LU_MAIN version */
20  __R uint8_t RESERVED1[4]; /* 0x1C - 0x1F: Reserved */
21  __RW uint32_t LU_MAIN_INTF_ACTION; /* 0x20: LU_MAIN low word of action data for internal frames */
22  __R uint8_t RESERVED2[4]; /* 0x24 - 0x27: Reserved */
23  __RW uint32_t LU_MAIN_BC_ACTION; /* 0x28: LU_MAIN low word of action data for broadcast frames */
24  __R uint8_t RESERVED3[4]; /* 0x2C - 0x2F: Reserved */
25  __RW uint32_t LU_MAIN_NN_ACTION; /* 0x30: LU_MAIN low word of action data for unknown frames */
26  __R uint8_t RESERVED4[204]; /* 0x34 - 0xFF: Reserved */
27  __R uint32_t APB2AXIS_CAM_STS; /* 0x100: status register */
28  __R uint8_t RESERVED5[12]; /* 0x104 - 0x10F: Reserved */
29  __R uint32_t APB2AXIS_CAM_REQ_CNT; /* 0x110: request count */
30  __R uint32_t APB2AXIS_CAM_FILLSTS; /* 0x114: fill status */
31  __W uint32_t APB2AXIS_CAM_RESET; /* 0x118: reset */
32  __R uint32_t APB2AXIS_CAM_PARAM; /* 0x11C: parameter */
33  __RW uint32_t APB2AXIS_CAM_REQDATA_0; /* 0x120: data0 */
34  __RW uint32_t APB2AXIS_CAM_REQDATA_1; /* 0x124: data1 */
35  __RW uint32_t APB2AXIS_CAM_REQDATA_2; /* 0x128: data2 */
36  __R uint8_t RESERVED6[212]; /* 0x12C - 0x1FF: Reserved */
37  __R uint32_t APB2AXIS_ALMEM_STS; /* 0x200: status register */
38  __R uint8_t RESERVED7[12]; /* 0x204 - 0x20F: Reserved */
39  __R uint32_t APB2AXIS_ALMEM_REQ_CNT; /* 0x210: request count */
40  __R uint32_t APB2AXIS_ALMEM_FILLSTS; /* 0x214: fill status */
41  __W uint32_t APB2AXIS_ALMEM_RESET; /* 0x218: reset */
42  __R uint32_t APB2AXIS_ALMEM_PARAM; /* 0x21C: parameter */
43  __RW uint32_t APB2AXIS_ALMEM_REQDATA_0; /* 0x220: data0 */
44  __RW uint32_t APB2AXIS_ALMEM_REQDATA_1; /* 0x224: data1 */
45  __R uint8_t RESERVED8[88]; /* 0x228 - 0x27F: Reserved */
46  __R uint32_t AXIS2APB_ALMEM_STS; /* 0x280: status register */
47  __R uint8_t RESERVED9[12]; /* 0x284 - 0x28F: Reserved */
48  __R uint32_t AXIS2APB_ALMEM_RESP_CNT; /* 0x290: response count */
49  __R uint32_t AXIS2APB_ALMEM_FILLSTS; /* 0x294: fill status */
50  __RW uint32_t AXIS2APB_ALMEM_RESET; /* 0x298: reset */
51  __R uint32_t AXIS2APB_ALMEM_PARAM; /* 0x29C: parameter */
52  __RW uint32_t AXIS2APB_ALMEM_RESPDATA_0; /* 0x2A0: data0 */
53  __RW uint32_t AXIS2APB_ALMEM_RESPDATA_1; /* 0x2A4: data1 */
54  __R uint8_t RESERVED10[344]; /* 0x2A8 - 0x3FF: Reserved */
55  __RW uint32_t HITMEM[4]; /* 0x400 - 0x40C: hitmem */
56  __R uint8_t RESERVED11[3056]; /* 0x410 - 0xFFF: Reserved */
57  __R uint32_t APB2AXIS_LOOKUP_STS; /* 0x1000: status register */
58  __R uint8_t RESERVED12[12]; /* 0x1004 - 0x100F: Reserved */
59  __R uint32_t APB2AXIS_LOOKUP_REQ_CNT; /* 0x1010: response count */
60  __R uint32_t APB2AXIS_LOOKUP_FILLSTS; /* 0x1014: fill status */
61  __RW uint32_t APB2AXIS_LOOKUP_RESET; /* 0x1018: reset */
62  __R uint32_t APB2AXIS_LOOKUP_PARAM; /* 0x101C: parameter */
63  __RW uint32_t APB2AXIS_LOOKUP_REQDATA_0; /* 0x1020: LOOKUP REQUEST Register REQ_DATA_0 */
64  __RW uint32_t APB2AXIS_LOOKUP_REQDATA_1; /* 0x1024: LOOKUP REQUEST Register REQ_DATA_1 */
65  __R uint8_t RESERVED13[4]; /* 0x1028 - 0x102B: Reserved */
66  __RW uint32_t APB2AXIS_LOOKUP_REQDATA_3; /* 0x102C: LOOKUP REQUEST Register REQ_DATA_2 */
67  __R uint8_t RESERVED14[80]; /* 0x1030 - 0x107F: Reserved */
68  __R uint32_t AXIS2APB_LOOKUP_STS; /* 0x1080: status register */
69  __R uint8_t RESERVED15[12]; /* 0x1084 - 0x108F: Reserved */
70  __R uint32_t AXIS2APB_LOOKUP_RESP_CNT; /* 0x1090: response count */
71  __R uint32_t AXIS2APB_LOOKUP_FILLSTS; /* 0x1094: fill status */
72  __RW uint32_t AXIS2APB_LOOKUP_RESET; /* 0x1098: reset */
73  __R uint32_t AXIS2APB_LOOKUP_PARAM; /* 0x109C: parameter */
74  __RW uint32_t AXIS2APB_LOOKUP_RESPDATA_0; /* 0x10A0: LOOKUP RESPONSE Data Register */
75  __R uint8_t RESERVED16[4]; /* 0x10A4 - 0x10A7: Reserved */
76  __RW uint32_t AXIS2APB_LOOKUP_RESPDATA_1; /* 0x10A8: LOOKUP RESPONSE Data Register */
77  __R uint8_t RESERVED17[3924]; /* 0x10AC - 0x1FFF: Reserved */
78  __R uint32_t CENTRAL_CSR_VERSION; /* 0x2000: version register */
79  __R uint32_t CENTRAL_CSR_PARAM; /* 0x2004: Parameter Register */
80  __RW uint32_t CENTRAL_CSR_CONFIG; /* 0x2008: Configuration Register */
81  __R uint32_t CENTRAL_CSR_CB_PARAM; /* 0x200C: CB Parameter Register */
82  __R uint32_t CENTRAL_CSR_QCI_CTRL_PARAM; /* 0x2010: QCI Control Parameter Register */
83  __R uint8_t RESERVED18[240]; /* 0x2014 - 0x2103: Reserved */
84  __R uint32_t CENTRAL_QCI_HWCFG; /* 0x2104: PSPF General CTRAL */
85  __R uint8_t RESERVED19[8]; /* 0x2108 - 0x210F: Reserved */
86  __RW uint32_t CENTRAL_QCI_FILTERSEL; /* 0x2110: Filter select index */
87  __RW uint32_t CENTRAL_QCI_METERSEL; /* 0x2114: Flowmeter select index */
88  __RW uint32_t CENTRAL_QCI_GATESEL; /* 0x2118: Gate select index */
89  __R uint8_t RESERVED20[4]; /* 0x211C - 0x211F: Reserved */
90  __RW uint32_t CENTRAL_QCI_FCTRL; /* 0x2120: FILTER SETTING */
91  __RW uint32_t CENTRAL_QCI_FSIZE; /* 0x2124: */
92  __R uint8_t RESERVED21[24]; /* 0x2128 - 0x213F: Reserved */
93  __R uint32_t QCI_CNT[6]; /* 0x2140 - 0x2154: FILTER COUNTER */
94  __R uint8_t RESERVED22[8]; /* 0x2158 - 0x215F: Reserved */
95  __RW uint32_t CENTRAL_QCI_MCTRL; /* 0x2160: Flow meter settings */
96  __R uint8_t RESERVED23[12]; /* 0x2164 - 0x216F: Reserved */
97  __RW uint32_t CENTRAL_QCI_CIR; /* 0x2170: */
98  __RW uint32_t CENTRAL_QCI_CBS; /* 0x2174: */
99  __RW uint32_t CENTRAL_QCI_EIR; /* 0x2178: */
100  __RW uint32_t CENTRAL_QCI_EBS; /* 0x217C: */
101  __RW uint32_t CENTRAL_QCI_GCTRL; /* 0x2180: Gate settings */
102  __RW uint32_t CENTRAL_QCI_GSTATUS; /* 0x2184: */
103  __RW uint32_t CENTRAL_QCI_GLISTINDEX; /* 0x2188: */
104  __RW uint32_t CENTRAL_QCI_LISTLEN; /* 0x218C: */
105  __RW uint32_t CENTRAL_QCI_ACYCLETM; /* 0x2190: */
106  __RW uint32_t CENTRAL_QCI_ABASETM_L; /* 0x2194: */
107  __RW uint32_t CENTRAL_QCI_ABASETM_H; /* 0x2198: */
108  __R uint8_t RESERVED24[4]; /* 0x219C - 0x219F: Reserved */
109  __RW uint32_t CENTRAL_QCI_AENTRY_CTRL; /* 0x21A0: */
110  __RW uint32_t CENTRAL_QCI_AENTRY_AENTRY_IVAL; /* 0x21A4: */
111  __R uint32_t CENTRAL_QCI_AENTRY_OCYCLETM; /* 0x21A8: */
112  __R uint32_t CENTRAL_QCI_AENTRY_OBASETM_L;/* 0x21AC: */
113  __R uint32_t CENTRAL_QCI_AENTRY_OBASETM_H;/* 0x21B0: */
114  __R uint8_t RESERVED25[7756]; /* 0x21B4 - 0x3FFF: Reserved */
115  __RW uint32_t MM2S_DMA_CR; /* 0x4000: mm2s control register */
116  __RW uint32_t MM2S_DMA_SR; /* 0x4004: mm2s status */
117  __R uint32_t MM2S_DMA_FILL; /* 0x4008: mm2s dma fill status */
118  __R uint8_t RESERVED26[16]; /* 0x400C - 0x401B: Reserved */
119  __R uint32_t MM2S_DMA_CFG; /* 0x401C: mm2s dma configure */
120  __RW uint32_t MM2S_ADDRLO; /* 0x4020: mm2s axi address */
121  __R uint8_t RESERVED27[4]; /* 0x4024 - 0x4027: Reserved */
122  __RW uint32_t MM2S_LENGTH; /* 0x4028: mm2s axi length */
123  __RW uint32_t MM2S_CTRL; /* 0x402C: mm2s command control */
124  __R uint32_t MM2S_RESP; /* 0x4030: mm2s response buffer */
125  __R uint8_t RESERVED28[76]; /* 0x4034 - 0x407F: Reserved */
126  __RW uint32_t S2MM_DMA_CR; /* 0x4080: s2mm dma control */
127  __RW uint32_t S2MM_DMA_SR; /* 0x4084: s2mm state */
128  __R uint32_t S2MM_DMA_FILL; /* 0x4088: s2mm buffer fill status */
129  __R uint8_t RESERVED29[16]; /* 0x408C - 0x409B: Reserved */
130  __R uint32_t S2MM_DMA_CFG; /* 0x409C: s2mm dma config status */
131  __RW uint32_t S2MM_ADDRLO; /* 0x40A0: s2mm axi address */
132  __R uint8_t RESERVED30[4]; /* 0x40A4 - 0x40A7: Reserved */
133  __RW uint32_t S2MM_LENGTH; /* 0x40A8: s2mm axi length */
134  __RW uint32_t S2MM_CTRL; /* 0x40AC: s2mm command control */
135  __R uint32_t S2MM_RESP; /* 0x40B0: s2mm response buffer */
136  __R uint8_t RESERVED31[8012]; /* 0x40B4 - 0x5FFF: Reserved */
137  __RW uint32_t PTP_EVT_TS_CTL; /* 0x6000: timestamp control */
138  __R uint8_t RESERVED32[4]; /* 0x6004 - 0x6007: Reserved */
139  __R uint32_t PTP_EVT_PPS_TOD_SEC; /* 0x6008: pps tod seconds */
140  __R uint32_t PTP_EVT_PPS_TOD_NS; /* 0x600C: pps tod sun seconds */
141  __R uint8_t RESERVED33[12]; /* 0x6010 - 0x601B: Reserved */
142  __RW uint32_t PTP_EVT_SCP_SEC0; /* 0x601C: target time seconds */
143  __RW uint32_t PTP_EVT_SCP_NS0; /* 0x6020: target time sub seconds */
144  __R uint8_t RESERVED34[4]; /* 0x6024 - 0x6027: Reserved */
145  __R uint32_t PTP_EVT_TMR_STS; /* 0x6028: timer status */
146  __RW uint32_t PTP_EVT_PPS_CMD; /* 0x602C: pps command control */
147  __R uint32_t PTP_EVT_ATSLO; /* 0x6030: auxiliary read data sub seconds */
148  __R uint32_t PTP_EVT_ATSHI; /* 0x6034: auxiliary read data seconds */
149  __R uint8_t RESERVED35[40]; /* 0x6038 - 0x605F: Reserved */
150  __RW uint32_t PTP_EVT_PPS0_INTERVAL; /* 0x6060: pps0 interval configure */
151  __RW uint32_t PTP_EVT_PPS0_WIDTH; /* 0x6064: pps0 width configure */
152  __R uint8_t RESERVED36[24]; /* 0x6068 - 0x607F: Reserved */
153  __RW uint32_t PTP_EVT_SCP_SEC1; /* 0x6080: target time seconds */
154  __RW uint32_t PTP_EVT_SCP_NS1; /* 0x6084: target time sub seconds */
155  __RW uint32_t PTP_EVT_PPS1_INTERVAL; /* 0x6088: pps1 interval configure */
156  __RW uint32_t PTP_EVT_PPS1_WIDTH; /* 0x608C: pps1 width configure */
157  __R uint8_t RESERVED37[16]; /* 0x6090 - 0x609F: Reserved */
158  __RW uint32_t PTP_EVT_SCP_SEC2; /* 0x60A0: target time seconds */
159  __RW uint32_t PTP_EVT_SCP_NS2; /* 0x60A4: target time sub seconds */
160  __RW uint32_t PTP_EVT_PPS2_INTERVAL; /* 0x60A8: pps2 interval configure */
161  __RW uint32_t PTP_EVT_PPS2_WIDTH; /* 0x60AC: pps2 width configure */
162  __R uint8_t RESERVED38[16]; /* 0x60B0 - 0x60BF: Reserved */
163  __RW uint32_t PTP_EVT_SCP_SEC3; /* 0x60C0: target time seconds */
164  __RW uint32_t PTP_EVT_SCP_NS3; /* 0x60C4: target time sub seconds */
165  __RW uint32_t PTP_EVT_PPS3_INTERVAL; /* 0x60C8: pps3 interval configure */
166  __RW uint32_t PTP_EVT_PPS3_WIDTH; /* 0x60CC: pps3 width configure */
167  __R uint8_t RESERVED39[16]; /* 0x60D0 - 0x60DF: Reserved */
168  __RW uint32_t PTP_EVT_PPS_CTRL0; /* 0x60E0: pps control 0 register */
169  __RW uint32_t PTP_EVT_PPS_SEL; /* 0x60E4: */
170  __R uint8_t RESERVED40[8]; /* 0x60E8 - 0x60EF: Reserved */
171  __RW uint32_t SOFT_RST_CTRL; /* 0x60F0: softer reset control */
172  __R uint8_t RESERVED41[40716]; /* 0x60F4 - 0xFFFF: Reserved */
173  __RW uint32_t CPU_PORT_PORT_MAIN_TAGGING; /* 0x10000: PVID Tagging Register */
174  __RW uint32_t CPU_PORT_PORT_MAIN_ENNABLE; /* 0x10004: Port Module Enable Register */
175  __R uint8_t RESERVED42[10232]; /* 0x10008 - 0x127FF: Reserved */
176  __RW uint32_t CPU_PORT_EGRESS_STMID_ESELECT; /* 0x12800: Stream Identification */
177  __R uint8_t RESERVED43[60]; /* 0x12804 - 0x1283F: Reserved */
178  __RW uint32_t CPU_PORT_EGRESS_STMID_CONTROL; /* 0x12840: */
179  __RW uint32_t CPU_PORT_EGRESS_STMID_SEQNO; /* 0x12844: */
180  __RW uint32_t CPU_PORT_EGRESS_STMID_MATCHCNT; /* 0x12848: */
181  __R uint8_t RESERVED44[4]; /* 0x1284C - 0x1284F: Reserved */
182  __RW uint32_t CPU_PORT_EGRESS_STMID_MACLO; /* 0x12850: */
183  __RW uint32_t CPU_PORT_EGRESS_STMID_MACHI; /* 0x12854: */
184  __RW uint32_t CPU_PORT_EGRESS_STMID_AMACLO;/* 0x12858: */
185  __RW uint32_t CPU_PORT_EGRESS_STMID_AMACHI;/* 0x1285C: */
186  __R uint8_t RESERVED45[160]; /* 0x12860 - 0x128FF: Reserved */
187  __RW uint32_t CPU_PORT_EGRESS_FRER_CONTROL;/* 0x12900: Frame Replication and Elimination */
188  __RW uint32_t CPU_PORT_EGRESS_FRER_SIDSEL; /* 0x12904: */
189  __RW uint32_t CPU_PORT_EGRESS_FRER_IRFUNC; /* 0x12908: */
190  __RW uint32_t CPU_PORT_EGRESS_FRER_SRFUNC; /* 0x1290C: */
191  __RW uint32_t CPU_PORT_EGRESS_FRER_FSELECT;/* 0x12910: */
192  __R uint8_t RESERVED46[44]; /* 0x12914 - 0x1293F: Reserved */
193  __RW uint32_t CPU_PORT_EGRESS_FRER_FCTRL; /* 0x12940: */
194  __RW uint32_t CPU_PORT_EGRESS_FRER_RESETMSEC; /* 0x12944: */
195  __RW uint32_t CPU_PORT_EGRESS_FRER_LATRSPERIOD; /* 0x12948: */
196  __RW uint32_t CPU_PORT_EGRESS_FRER_LATTESTPERIOD; /* 0x1294C: */
197  __RW uint32_t CPU_PORT_EGRESS_FRER_LATERRDIFFALW; /* 0x12950: */
198  __RW uint32_t CPU_PORT_EGRESS_FRER_LATERRCNT; /* 0x12954: */
199  __R uint8_t RESERVED47[8]; /* 0x12958 - 0x1295F: Reserved */
200  __R uint32_t EGFRCNT[8]; /* 0x12960 - 0x1297C: */
201  __R uint8_t RESERVED48[5760]; /* 0x12980 - 0x13FFF: Reserved */
202  __R uint32_t CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_CNT_BYTE; /* 0x14000: */
203  __R uint32_t CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS; /* 0x14004: */
204  __RW uint32_t CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG; /* 0x14008: */
205  __RW uint32_t CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG; /* 0x1400C: */
206  __RW uint32_t CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG; /* 0x14010: */
207  __RW uint32_t CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG; /* 0x14014: */
208  __W uint32_t CPU_PORT_IGRESS_RX_FDFIFO_RESET; /* 0x14018: */
209  __R uint32_t CPU_PORT_IGRESS_RX_FDFIFO_PARAM; /* 0x1401C: */
210  __RW uint32_t CPU_PORT_IGRESS_RX_FDFIFO_STRFWD; /* 0x14020: */
211  __RW uint32_t CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK; /* 0x14024: */
212  __RW uint32_t CPU_PORT_IGRESS_RX_FDFIFO_MIRROR; /* 0x14028: */
213  __RW uint32_t CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX; /* 0x1402C: */
214  __R uint8_t RESERVED49[2000]; /* 0x14030 - 0x147FF: Reserved */
215  __RW uint32_t CPU_PORT_IGRESS_STMID_ESELECT; /* 0x14800: Stream Identification */
216  __R uint8_t RESERVED50[60]; /* 0x14804 - 0x1483F: Reserved */
217  __RW uint32_t CPU_PORT_IGRESS_STMID_CONTROL; /* 0x14840: */
218  __RW uint32_t CPU_PORT_IGRESS_STMID_SEQNO; /* 0x14844: */
219  __RW uint32_t CPU_PORT_IGRESS_STMID_MATCHCNT; /* 0x14848: */
220  __R uint8_t RESERVED51[4]; /* 0x1484C - 0x1484F: Reserved */
221  __RW uint32_t CPU_PORT_IGRESS_STMID_MACLO; /* 0x14850: */
222  __RW uint32_t CPU_PORT_IGRESS_STMID_MACHI; /* 0x14854: */
223  __RW uint32_t CPU_PORT_IGRESS_STMID_AMACLO;/* 0x14858: */
224  __RW uint32_t CPU_PORT_IGRESS_STMID_AMACHI;/* 0x1485C: */
225  __R uint8_t RESERVED52[160]; /* 0x14860 - 0x148FF: Reserved */
226  __RW uint32_t CPU_PORT_IGRESS_FRER_CONTROL;/* 0x14900: Frame Replication and Elimination */
227  __RW uint32_t CPU_PORT_IGRESS_FRER_SIDSEL; /* 0x14904: */
228  __RW uint32_t CPU_PORT_IGRESS_FRER_IRFUNC; /* 0x14908: */
229  __RW uint32_t CPU_PORT_IGRESS_FRER_SRFUNC; /* 0x1490C: */
230  __RW uint32_t CPU_PORT_IGRESS_FRER_FSELECT;/* 0x14910: */
231  __R uint8_t RESERVED53[44]; /* 0x14914 - 0x1493F: Reserved */
232  __RW uint32_t CPU_PORT_IGRESS_FRER_FCTRL; /* 0x14940: */
233  __RW uint32_t CPU_PORT_IGRESS_FRER_RESETMSEC; /* 0x14944: */
234  __RW uint32_t CPU_PORT_IGRESS_FRER_LATRSPERIOD; /* 0x14948: */
235  __RW uint32_t CPU_PORT_IGRESS_FRER_LATTESTPERIOD; /* 0x1494C: */
236  __RW uint32_t CPU_PORT_IGRESS_FRER_LATERRDIFFALW; /* 0x14950: */
237  __RW uint32_t CPU_PORT_IGRESS_FRER_LATERRCNT; /* 0x14954: */
238  __R uint8_t RESERVED54[8]; /* 0x14958 - 0x1495F: Reserved */
239  __R uint32_t IGFRCNT[8]; /* 0x14960 - 0x1497C: */
240  __R uint8_t RESERVED55[13956]; /* 0x14980 - 0x18003: Reserved */
241  __RW uint32_t CPU_PORT_MONITOR_CTRL; /* 0x18004: */
242  __W uint32_t CPU_PORT_MONITOR_RESET; /* 0x18008: */
243  __R uint32_t CPU_PORT_MONITOR_PARAM; /* 0x1800C: */
244  __R uint32_t CPU_PORT_MONITOR_TX_COUNTER_TX_FGOOD; /* 0x18010: */
245  __R uint8_t RESERVED56[4]; /* 0x18014 - 0x18017: Reserved */
246  __R uint32_t CPU_PORT_MONITOR_TX_COUNTER_TX_FERROR; /* 0x18018: */
247  __R uint8_t RESERVED57[4]; /* 0x1801C - 0x1801F: Reserved */
248  __R uint32_t CPU_PORT_MONITOR_TX_COUNTER_TX_DROP_OVFL; /* 0x18020: */
249  __R uint8_t RESERVED58[28]; /* 0x18024 - 0x1803F: Reserved */
250  __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_FGOOD; /* 0x18040: */
251  __R uint8_t RESERVED59[4]; /* 0x18044 - 0x18047: Reserved */
252  __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_FERROR; /* 0x18048: */
253  __R uint8_t RESERVED60[4]; /* 0x1804C - 0x1804F: Reserved */
254  __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_KNOWN; /* 0x18050: */
255  __R uint8_t RESERVED61[4]; /* 0x18054 - 0x18057: Reserved */
256  __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_UNKNOWN; /* 0x18058: */
257  __R uint8_t RESERVED62[4]; /* 0x1805C - 0x1805F: Reserved */
258  __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_UC; /* 0x18060: */
259  __R uint8_t RESERVED63[4]; /* 0x18064 - 0x18067: Reserved */
260  __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_INTERN; /* 0x18068: */
261  __R uint8_t RESERVED64[4]; /* 0x1806C - 0x1806F: Reserved */
262  __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_BC; /* 0x18070: */
263  __R uint8_t RESERVED65[4]; /* 0x18074 - 0x18077: Reserved */
264  __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_MULTI; /* 0x18078: */
265  __R uint8_t RESERVED66[4]; /* 0x1807C - 0x1807F: Reserved */
266  __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_VLAN; /* 0x18080: */
267  __R uint8_t RESERVED67[4]; /* 0x18084 - 0x18087: Reserved */
268  __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_OVFL; /* 0x18088: */
269  __R uint8_t RESERVED68[4]; /* 0x1808C - 0x1808F: Reserved */
270  __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_LU; /* 0x18090: */
271  __R uint8_t RESERVED69[4]; /* 0x18094 - 0x18097: Reserved */
272  __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_ERR; /* 0x18098: */
273  __R uint8_t RESERVED70[4]; /* 0x1809C - 0x1809F: Reserved */
274  __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_VLAN; /* 0x180A0: */
275  __R uint8_t RESERVED71[4]; /* 0x180A4 - 0x180A7: Reserved */
276  __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD; /* 0x180A8: */
277  __R uint8_t RESERVED72[32596]; /* 0x180AC - 0x1FFFF: Reserved */
278  struct {
279  struct {
280  __R uint32_t MAC_VER; /* 0x20000: */
281  __RW uint32_t MAC_MACADDR_L; /* 0x20004: */
282  __RW uint32_t MAC_MACADDR_H; /* 0x20008: */
283  __RW uint32_t MAC_MAC_CTRL; /* 0x2000C: */
284  __R uint32_t MAC_TX_FRAMES; /* 0x20010: */
285  __R uint32_t MAC_RX_FRAMES; /* 0x20014: */
286  __R uint32_t MAC_TX_OCTETS; /* 0x20018: */
287  __R uint32_t MAC_RX_OCTETS; /* 0x2001C: */
288  __RW uint32_t MAC_MDIO_CFG; /* 0x20020: */
289  __RW uint32_t MAC_MDIO_CTRL; /* 0x20024: */
290  __R uint32_t MAC_MDIO_RD_DATA; /* 0x20028: */
291  __RW uint32_t MAC_MDIO_WR_DATA; /* 0x2002C: */
292  __RW uint32_t MAC_IRQ_CTRL; /* 0x20030: */
293  __R uint8_t RESERVED0[460]; /* 0x20034 - 0x201FF: Reserved */
294  } MAC[2];
295  __R uint8_t RESERVED0[1024]; /* 0x20400 - 0x207FF: Reserved */
296  __RW uint32_t RTC_CR; /* 0x20800: ONLY IN PORT1 */
297  __RW uint32_t RTC_SR; /* 0x20804: ONLY IN PORT1 */
298  __R uint8_t RESERVED1[8]; /* 0x20808 - 0x2080F: Reserved */
299  __RW uint32_t RTC_CT_CURTIME_NS; /* 0x20810: ONLY IN PORT1 */
300  __R uint32_t RTC_CT_CURTIME_SEC; /* 0x20814: ONLY IN PORT1 */
301  __R uint8_t RESERVED2[4]; /* 0x20818 - 0x2081B: Reserved */
302  __RW uint32_t RTC_CT_TIMER_INCR; /* 0x2081C: ONLY IN PORT1 */
303  __RW uint32_t RTC_OFS_NS; /* 0x20820: ONLY IN PORT1 */
304  __RW uint32_t RTC_OFS_SL; /* 0x20824: ONLY IN PORT1 */
305  __RW uint32_t RTC_OFS_SH; /* 0x20828: ONLY IN PORT1 */
306  __RW uint32_t RTC_OFS_CH; /* 0x2082C: ONLY IN PORT1 */
307  __RW uint32_t RTC_ALARM_NS; /* 0x20830: ONLY IN PORT1 */
308  __RW uint32_t RTC_ALARM_SL; /* 0x20834: ONLY IN PORT1 */
309  __RW uint32_t RTC_ALARM_SH; /* 0x20838: ONLY IN PORT1 */
310  __R uint8_t RESERVED3[4]; /* 0x2083C - 0x2083F: Reserved */
311  __RW uint32_t RTC_TIMER_A_PERIOD; /* 0x20840: ONLY IN PORT1 */
312  __R uint8_t RESERVED4[1984]; /* 0x20844 - 0x21003: Reserved */
313  __RW uint32_t TSYN_CR; /* 0x21004: */
314  __RW uint32_t TSYN_SR; /* 0x21008: */
315  __R uint8_t RESERVED5[4]; /* 0x2100C - 0x2100F: Reserved */
316  __R uint32_t TSYN_PTP_TX_STS; /* 0x21010: */
317  __RW uint32_t TSYN_PTP_TX_DONE; /* 0x21014: */
318  __W uint32_t TSYN_PTP_TX_TRIG; /* 0x21018: */
319  __RW uint32_t TSYN_PTP_RX_STS; /* 0x2101C: */
320  __RW uint32_t TSYNTMR[5]; /* 0x21020 - 0x21030: */
321  __R uint8_t RESERVED6[8]; /* 0x21034 - 0x2103B: Reserved */
322  __RW uint32_t TSYN_HCLKDIV; /* 0x2103C: */
323  __R uint8_t RESERVED7[1472]; /* 0x21040 - 0x215FF: Reserved */
324  __R uint32_t TSYN_RXBUF_RX_FRAME_LENGTH_BYTES; /* 0x21600: */
325  __R uint8_t RESERVED8[4]; /* 0x21604 - 0x21607: Reserved */
326  __R uint32_t TSYN_RXBUF_RX_TIME_STAMP_L; /* 0x21608: */
327  __R uint32_t TSYN_RXBUF_RX_TIME_STAMP_H; /* 0x2160C: */
328  __R uint32_t RXDATA[60]; /* 0x21610 - 0x216FC: */
329  __R uint8_t RESERVED9[256]; /* 0x21700 - 0x217FF: Reserved */
330  struct {
331  __W uint32_t TXDATA[60]; /* 0x21800 - 0x218EC: */
332  __W uint32_t TSYN_TXBUF_TQUE_AND_TX_LEN; /* 0x218F0: */
333  __R uint8_t RESERVED0[4]; /* 0x218F4 - 0x218F7: Reserved */
334  __R uint32_t TSYN_TXBUF_TX_TIMESTAMP_L; /* 0x218F8: */
335  __R uint32_t TSYN_TXBUF_TX_TIMESTAMP_H; /* 0x218FC: */
336  } BIN[8];
337  __R uint8_t RESERVED10[4]; /* 0x22000 - 0x22003: Reserved */
338  __R uint32_t TSN_SHAPER_HWCFG1; /* 0x22004: */
339  __R uint8_t RESERVED11[4]; /* 0x22008 - 0x2200B: Reserved */
340  __RW uint32_t TSN_SHAPER_TQAV; /* 0x2200C: */
341  __R uint32_t TSN_SHAPER_TQEM; /* 0x22010: */
342  __RW uint32_t TSN_SHAPER_FPST; /* 0x22014: */
343  __RW uint32_t TSN_SHAPER_MMCT; /* 0x22018: */
344  __RW uint32_t TSN_SHAPER_HOLDADV; /* 0x2201C: */
345  __R uint8_t RESERVED12[224]; /* 0x22020 - 0x220FF: Reserved */
346  __RW uint32_t MXSDU[8]; /* 0x22100 - 0x2211C: */
347  __RW uint32_t TXSEL[8]; /* 0x22120 - 0x2213C: */
348  __RW uint32_t IDSEL[8]; /* 0x22140 - 0x2215C: */
349  __R uint8_t RESERVED13[1696]; /* 0x22160 - 0x227FF: Reserved */
350  __RW uint32_t PORT1_QCH0_CFG; /* 0x22800: qch channel0 control */
351  __RW uint32_t PORT1_QCH1_CFG; /* 0x22804: qch channel1 control */
352  __RW uint32_t PORT1_QCH2_CFG; /* 0x22808: qch channel2 control */
353  __RW uint32_t PORT1_QCH3_CFG; /* 0x2280C: qch channel3 control */
354  __RW uint32_t PORT1_QCH_ERR_CFG; /* 0x22810: qch clear */
355  __R uint8_t RESERVED14[2028]; /* 0x22814 - 0x22FFF: Reserved */
356  __RW uint32_t TSN_SHAPER_TAS_CRSR; /* 0x23000: */
357  __RW uint32_t TSN_SHAPER_TAS_ACYCLETM; /* 0x23004: */
358  __RW uint32_t TSN_SHAPER_TAS_ABASETM_L;/* 0x23008: */
359  __RW uint32_t TSN_SHAPER_TAS_ABASETM_H;/* 0x2300C: */
360  __RW uint32_t TSN_SHAPER_TAS_LISTLEN; /* 0x23010: */
361  __R uint32_t TSN_SHAPER_TAS_OCYCLETM; /* 0x23014: */
362  __R uint32_t TSN_SHAPER_TAS_OBASETM_L;/* 0x23018: */
363  __R uint32_t TSN_SHAPER_TAS_OBASETM_H;/* 0x2301C: */
364  __RW uint32_t MXTK[8]; /* 0x23020 - 0x2303C: */
365  __RW uint32_t TXOV[8]; /* 0x23040 - 0x2305C: */
366  __R uint8_t RESERVED15[1952]; /* 0x23060 - 0x237FF: Reserved */
367  struct {
368  __RW uint32_t TSN_SHAPER_ACLIST_ENTRY_L; /* 0x23800: */
369  __RW uint32_t TSN_SHAPER_ACLIST_ENTRY_H; /* 0x23804: */
370  } SHACL[256];
371  __R uint8_t RESERVED16[45056]; /* 0x24000 - 0x2EFFF: Reserved */
372  __R uint32_t TSN_EP_VER; /* 0x2F000: */
373  __RW uint32_t TSN_EP_CTRL; /* 0x2F004: */
374  __R uint8_t RESERVED17[8]; /* 0x2F008 - 0x2F00F: Reserved */
375  __RW uint32_t TSN_EP_TXUF; /* 0x2F010: */
376  __R uint32_t TSN_EP_IPCFG; /* 0x2F014: */
377  __R uint8_t RESERVED18[8]; /* 0x2F018 - 0x2F01F: Reserved */
378  __R uint32_t TSN_EP_TSF_D0; /* 0x2F020: */
379  __R uint32_t TSN_EP_TSF_D1; /* 0x2F024: */
380  __R uint32_t TSN_EP_TSF_D2; /* 0x2F028: */
381  __RW uint32_t TSN_EP_TSF_SR; /* 0x2F02C: */
382  __RW uint32_t TSN_EP_MMS_CTRL; /* 0x2F030: */
383  __R uint32_t TSN_EP_MMS_STS; /* 0x2F034: */
384  __RW uint32_t TSN_EP_MMS_VTIME; /* 0x2F038: */
385  __RW uint32_t TSN_EP_MMS_STAT; /* 0x2F03C: */
386  __W uint32_t TSN_EP_PTP_UPTM_NS; /* 0x2F040: */
387  __W uint32_t TSN_EP_PTP_UPTM_S; /* 0x2F044: */
388  __R uint32_t TSN_EP_PTP_SR; /* 0x2F048: */
389  __R uint8_t RESERVED19[4020]; /* 0x2F04C - 0x2FFFF: Reserved */
390  __RW uint32_t SW_CTRL_PORT_MAIN_TAGGING; /* 0x30000: PVID Tagging Register */
391  __R uint8_t RESERVED20[8188]; /* 0x30004 - 0x31FFF: Reserved */
392  __RW uint32_t SW_CTRL_EGRESS_ECSR_QDROP; /* 0x32000: */
393  __R uint8_t RESERVED21[8188]; /* 0x32004 - 0x33FFF: Reserved */
394  struct {
395  __R uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_CNT_BYTE; /* 0x34000: */
396  __R uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS; /* 0x34004: */
397  __RW uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG; /* 0x34008: */
398  __RW uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG; /* 0x3400C: */
399  __RW uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG; /* 0x34010: */
400  __RW uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG; /* 0x34014: */
401  __W uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_RESET; /* 0x34018: */
402  __R uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM; /* 0x3401C: */
403  __RW uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD; /* 0x34020: */
404  __RW uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK; /* 0x34024: */
405  __RW uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR; /* 0x34028: */
406  __RW uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX; /* 0x3402C: */
407  __R uint8_t RESERVED0[208]; /* 0x34030 - 0x340FF: Reserved */
408  } RXFIFO[2];
409  __R uint8_t RESERVED22[15876]; /* 0x34200 - 0x38003: Reserved */
410  __RW uint32_t SW_CTRL_MONITOR_CTRL; /* 0x38004: */
411  __W uint32_t SW_CTRL_MONITOR_RESET; /* 0x38008: */
412  __R uint32_t SW_CTRL_MONITOR_PARAM; /* 0x3800C: */
413  __R uint32_t MONITOR_TX_COUNTER_TX_FGOOD; /* 0x38010: */
414  __R uint8_t RESERVED23[4]; /* 0x38014 - 0x38017: Reserved */
415  __R uint32_t MONITOR_TX_COUNTER_TX_FERROR; /* 0x38018: */
416  __R uint8_t RESERVED24[4]; /* 0x3801C - 0x3801F: Reserved */
417  __R uint32_t MONITOR_TX_COUNTER_TX_DROP_OVFL; /* 0x38020: */
418  __R uint8_t RESERVED25[28]; /* 0x38024 - 0x3803F: Reserved */
419  __R uint32_t MONITOR_RX_COUNTER_RX_FGOOD; /* 0x38040: */
420  __R uint8_t RESERVED26[4]; /* 0x38044 - 0x38047: Reserved */
421  __R uint32_t MONITOR_RX_COUNTER_RX_FERROR; /* 0x38048: */
422  __R uint8_t RESERVED27[4]; /* 0x3804C - 0x3804F: Reserved */
423  __R uint32_t MONITOR_RX_COUNTER_RX_KNOWN; /* 0x38050: */
424  __R uint8_t RESERVED28[4]; /* 0x38054 - 0x38057: Reserved */
425  __R uint32_t MONITOR_RX_COUNTER_RX_UNKNOWN; /* 0x38058: */
426  __R uint8_t RESERVED29[4]; /* 0x3805C - 0x3805F: Reserved */
427  __R uint32_t MONITOR_RX_COUNTER_RX_UC;/* 0x38060: */
428  __R uint8_t RESERVED30[4]; /* 0x38064 - 0x38067: Reserved */
429  __R uint32_t MONITOR_RX_COUNTER_RX_INTERN; /* 0x38068: */
430  __R uint8_t RESERVED31[4]; /* 0x3806C - 0x3806F: Reserved */
431  __R uint32_t MONITOR_RX_COUNTER_RX_BC;/* 0x38070: */
432  __R uint8_t RESERVED32[4]; /* 0x38074 - 0x38077: Reserved */
433  __R uint32_t MONITOR_RX_COUNTER_RX_MULTI; /* 0x38078: */
434  __R uint8_t RESERVED33[4]; /* 0x3807C - 0x3807F: Reserved */
435  __R uint32_t MONITOR_RX_COUNTER_RX_VLAN; /* 0x38080: */
436  __R uint8_t RESERVED34[4]; /* 0x38084 - 0x38087: Reserved */
437  __R uint32_t MONITOR_RX_COUNTER_RX_DROP_OVFL; /* 0x38088: */
438  __R uint8_t RESERVED35[4]; /* 0x3808C - 0x3808F: Reserved */
439  __R uint32_t MONITOR_RX_COUNTER_RX_DROP_LU; /* 0x38090: */
440  __R uint8_t RESERVED36[4]; /* 0x38094 - 0x38097: Reserved */
441  __R uint32_t MONITOR_RX_COUNTER_RX_DROP_ERR; /* 0x38098: */
442  __R uint8_t RESERVED37[4]; /* 0x3809C - 0x3809F: Reserved */
443  __R uint32_t MONITOR_RX_COUNTER_RX_DROP_VLAN; /* 0x380A0: */
444  __R uint8_t RESERVED38[4]; /* 0x380A4 - 0x380A7: Reserved */
445  __R uint32_t MONITOR_RX_COUNTER_RX_FPE_FGOOD; /* 0x380A8: */
446  __R uint8_t RESERVED39[16212]; /* 0x380AC - 0x3BFFF: Reserved */
447  __RW uint32_t GPR_CTRL0; /* 0x3C000: control register0 */
448  __R uint8_t RESERVED40[4]; /* 0x3C004 - 0x3C007: Reserved */
449  __RW uint32_t GPR_CTRL2; /* 0x3C008: control register2 */
450  __R uint8_t RESERVED41[16372]; /* 0x3C00C - 0x3FFFF: Reserved */
451  } TSNPORT[3];
452 } TSW_Type;
453 
454 
455 /* Bitfield definition for register: LU_MAIN_CTRL */
456 /*
457  * BYP_EN (R/W)
458  *
459  * MAC lookup bypass
460  */
461 #define TSW_LU_MAIN_CTRL_BYP_EN_MASK (0x1U)
462 #define TSW_LU_MAIN_CTRL_BYP_EN_SHIFT (0U)
463 #define TSW_LU_MAIN_CTRL_BYP_EN_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_CTRL_BYP_EN_SHIFT) & TSW_LU_MAIN_CTRL_BYP_EN_MASK)
464 #define TSW_LU_MAIN_CTRL_BYP_EN_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_CTRL_BYP_EN_MASK) >> TSW_LU_MAIN_CTRL_BYP_EN_SHIFT)
465 
466 /* Bitfield definition for register: LU_MAIN_HITMEM */
467 /*
468  * CAMMEMCLR (R/W)
469  *
470  * clear the cam memory
471  */
472 #define TSW_LU_MAIN_HITMEM_CAMMEMCLR_MASK (0x2U)
473 #define TSW_LU_MAIN_HITMEM_CAMMEMCLR_SHIFT (1U)
474 #define TSW_LU_MAIN_HITMEM_CAMMEMCLR_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_HITMEM_CAMMEMCLR_SHIFT) & TSW_LU_MAIN_HITMEM_CAMMEMCLR_MASK)
475 #define TSW_LU_MAIN_HITMEM_CAMMEMCLR_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_HITMEM_CAMMEMCLR_MASK) >> TSW_LU_MAIN_HITMEM_CAMMEMCLR_SHIFT)
476 
477 /*
478  * HITMEMCLR (R/W)
479  *
480  * clears the hit memory
481  */
482 #define TSW_LU_MAIN_HITMEM_HITMEMCLR_MASK (0x1U)
483 #define TSW_LU_MAIN_HITMEM_HITMEMCLR_SHIFT (0U)
484 #define TSW_LU_MAIN_HITMEM_HITMEMCLR_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_HITMEM_HITMEMCLR_SHIFT) & TSW_LU_MAIN_HITMEM_HITMEMCLR_MASK)
485 #define TSW_LU_MAIN_HITMEM_HITMEMCLR_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_HITMEM_HITMEMCLR_MASK) >> TSW_LU_MAIN_HITMEM_HITMEMCLR_SHIFT)
486 
487 /* Bitfield definition for register: LU_MAIN_PARAM */
488 /*
489  * NSTR (RO)
490  *
491  * number of supported streams
492  */
493 #define TSW_LU_MAIN_PARAM_NSTR_MASK (0xFF00U)
494 #define TSW_LU_MAIN_PARAM_NSTR_SHIFT (8U)
495 #define TSW_LU_MAIN_PARAM_NSTR_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_PARAM_NSTR_MASK) >> TSW_LU_MAIN_PARAM_NSTR_SHIFT)
496 
497 /*
498  * ADDRW_ENTRY (RO)
499  *
500  * bit width of entry address vector
501  */
502 #define TSW_LU_MAIN_PARAM_ADDRW_ENTRY_MASK (0xFFU)
503 #define TSW_LU_MAIN_PARAM_ADDRW_ENTRY_SHIFT (0U)
504 #define TSW_LU_MAIN_PARAM_ADDRW_ENTRY_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_PARAM_ADDRW_ENTRY_MASK) >> TSW_LU_MAIN_PARAM_ADDRW_ENTRY_SHIFT)
505 
506 /* Bitfield definition for register: LU_MAIN_BYPASS */
507 /*
508  * HIT (R/W)
509  *
510  * set hit bit to frame, only for debugging
511  */
512 #define TSW_LU_MAIN_BYPASS_HIT_MASK (0x1000000UL)
513 #define TSW_LU_MAIN_BYPASS_HIT_SHIFT (24U)
514 #define TSW_LU_MAIN_BYPASS_HIT_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_BYPASS_HIT_SHIFT) & TSW_LU_MAIN_BYPASS_HIT_MASK)
515 #define TSW_LU_MAIN_BYPASS_HIT_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_BYPASS_HIT_MASK) >> TSW_LU_MAIN_BYPASS_HIT_SHIFT)
516 
517 /*
518  * UTAG (R/W)
519  *
520  * set internal user tag field
521  */
522 #define TSW_LU_MAIN_BYPASS_UTAG_MASK (0xE00000UL)
523 #define TSW_LU_MAIN_BYPASS_UTAG_SHIFT (21U)
524 #define TSW_LU_MAIN_BYPASS_UTAG_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_BYPASS_UTAG_SHIFT) & TSW_LU_MAIN_BYPASS_UTAG_MASK)
525 #define TSW_LU_MAIN_BYPASS_UTAG_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_BYPASS_UTAG_MASK) >> TSW_LU_MAIN_BYPASS_UTAG_SHIFT)
526 
527 /*
528  * HIT_VLAN (R/W)
529  *
530  * mark frame to be vlan-tagged
531  */
532 #define TSW_LU_MAIN_BYPASS_HIT_VLAN_MASK (0x100000UL)
533 #define TSW_LU_MAIN_BYPASS_HIT_VLAN_SHIFT (20U)
534 #define TSW_LU_MAIN_BYPASS_HIT_VLAN_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_BYPASS_HIT_VLAN_SHIFT) & TSW_LU_MAIN_BYPASS_HIT_VLAN_MASK)
535 #define TSW_LU_MAIN_BYPASS_HIT_VLAN_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_BYPASS_HIT_VLAN_MASK) >> TSW_LU_MAIN_BYPASS_HIT_VLAN_SHIFT)
536 
537 /*
538  * DROP (R/W)
539  *
540  * mark frame to be dropped
541  */
542 #define TSW_LU_MAIN_BYPASS_DROP_MASK (0x80000UL)
543 #define TSW_LU_MAIN_BYPASS_DROP_SHIFT (19U)
544 #define TSW_LU_MAIN_BYPASS_DROP_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_BYPASS_DROP_SHIFT) & TSW_LU_MAIN_BYPASS_DROP_MASK)
545 #define TSW_LU_MAIN_BYPASS_DROP_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_BYPASS_DROP_MASK) >> TSW_LU_MAIN_BYPASS_DROP_SHIFT)
546 
547 /*
548  * QUEUE (R/W)
549  *
550  * number of configured buffer depth
551  */
552 #define TSW_LU_MAIN_BYPASS_QUEUE_MASK (0x70000UL)
553 #define TSW_LU_MAIN_BYPASS_QUEUE_SHIFT (16U)
554 #define TSW_LU_MAIN_BYPASS_QUEUE_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_BYPASS_QUEUE_SHIFT) & TSW_LU_MAIN_BYPASS_QUEUE_MASK)
555 #define TSW_LU_MAIN_BYPASS_QUEUE_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_BYPASS_QUEUE_MASK) >> TSW_LU_MAIN_BYPASS_QUEUE_SHIFT)
556 
557 /*
558  * DEST (R/W)
559  *
560  * target destination ports of frame
561  */
562 #define TSW_LU_MAIN_BYPASS_DEST_MASK (0xFFFFU)
563 #define TSW_LU_MAIN_BYPASS_DEST_SHIFT (0U)
564 #define TSW_LU_MAIN_BYPASS_DEST_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_BYPASS_DEST_SHIFT) & TSW_LU_MAIN_BYPASS_DEST_MASK)
565 #define TSW_LU_MAIN_BYPASS_DEST_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_BYPASS_DEST_MASK) >> TSW_LU_MAIN_BYPASS_DEST_SHIFT)
566 
567 /* Bitfield definition for register: LU_MAIN_PCP_REMAP */
568 /*
569  * PCP7 (R/W)
570  *
571  * queue value for PCP=7
572  */
573 #define TSW_LU_MAIN_PCP_REMAP_PCP7_MASK (0xE00000UL)
574 #define TSW_LU_MAIN_PCP_REMAP_PCP7_SHIFT (21U)
575 #define TSW_LU_MAIN_PCP_REMAP_PCP7_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP7_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP7_MASK)
576 #define TSW_LU_MAIN_PCP_REMAP_PCP7_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP7_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP7_SHIFT)
577 
578 /*
579  * PCP6 (R/W)
580  *
581  * queue value for PCP=6
582  */
583 #define TSW_LU_MAIN_PCP_REMAP_PCP6_MASK (0x1C0000UL)
584 #define TSW_LU_MAIN_PCP_REMAP_PCP6_SHIFT (18U)
585 #define TSW_LU_MAIN_PCP_REMAP_PCP6_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP6_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP6_MASK)
586 #define TSW_LU_MAIN_PCP_REMAP_PCP6_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP6_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP6_SHIFT)
587 
588 /*
589  * PCP5 (R/W)
590  *
591  * queue value for PCP=5
592  */
593 #define TSW_LU_MAIN_PCP_REMAP_PCP5_MASK (0x38000UL)
594 #define TSW_LU_MAIN_PCP_REMAP_PCP5_SHIFT (15U)
595 #define TSW_LU_MAIN_PCP_REMAP_PCP5_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP5_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP5_MASK)
596 #define TSW_LU_MAIN_PCP_REMAP_PCP5_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP5_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP5_SHIFT)
597 
598 /*
599  * PCP4 (R/W)
600  *
601  * queue value for PCP=4
602  */
603 #define TSW_LU_MAIN_PCP_REMAP_PCP4_MASK (0x7000U)
604 #define TSW_LU_MAIN_PCP_REMAP_PCP4_SHIFT (12U)
605 #define TSW_LU_MAIN_PCP_REMAP_PCP4_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP4_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP4_MASK)
606 #define TSW_LU_MAIN_PCP_REMAP_PCP4_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP4_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP4_SHIFT)
607 
608 /*
609  * PCP3 (R/W)
610  *
611  * queue value for PCP=3
612  */
613 #define TSW_LU_MAIN_PCP_REMAP_PCP3_MASK (0xE00U)
614 #define TSW_LU_MAIN_PCP_REMAP_PCP3_SHIFT (9U)
615 #define TSW_LU_MAIN_PCP_REMAP_PCP3_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP3_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP3_MASK)
616 #define TSW_LU_MAIN_PCP_REMAP_PCP3_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP3_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP3_SHIFT)
617 
618 /*
619  * PCP2 (R/W)
620  *
621  * queue value for PCP=2
622  */
623 #define TSW_LU_MAIN_PCP_REMAP_PCP2_MASK (0x1C0U)
624 #define TSW_LU_MAIN_PCP_REMAP_PCP2_SHIFT (6U)
625 #define TSW_LU_MAIN_PCP_REMAP_PCP2_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP2_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP2_MASK)
626 #define TSW_LU_MAIN_PCP_REMAP_PCP2_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP2_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP2_SHIFT)
627 
628 /*
629  * PCP1 (R/W)
630  *
631  * queue value for PCP=1
632  */
633 #define TSW_LU_MAIN_PCP_REMAP_PCP1_MASK (0x38U)
634 #define TSW_LU_MAIN_PCP_REMAP_PCP1_SHIFT (3U)
635 #define TSW_LU_MAIN_PCP_REMAP_PCP1_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP1_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP1_MASK)
636 #define TSW_LU_MAIN_PCP_REMAP_PCP1_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP1_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP1_SHIFT)
637 
638 /*
639  * PCP0 (R/W)
640  *
641  * queue value for PCP=0
642  */
643 #define TSW_LU_MAIN_PCP_REMAP_PCP0_MASK (0x7U)
644 #define TSW_LU_MAIN_PCP_REMAP_PCP0_SHIFT (0U)
645 #define TSW_LU_MAIN_PCP_REMAP_PCP0_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP0_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP0_MASK)
646 #define TSW_LU_MAIN_PCP_REMAP_PCP0_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP0_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP0_SHIFT)
647 
648 /* Bitfield definition for register: LU_MAIN_VERSION */
649 /*
650  * VER_HI (RO)
651  *
652  * major version
653  */
654 #define TSW_LU_MAIN_VERSION_VER_HI_MASK (0xFF000000UL)
655 #define TSW_LU_MAIN_VERSION_VER_HI_SHIFT (24U)
656 #define TSW_LU_MAIN_VERSION_VER_HI_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_VERSION_VER_HI_MASK) >> TSW_LU_MAIN_VERSION_VER_HI_SHIFT)
657 
658 /*
659  * VER_LO (RO)
660  *
661  * minor version
662  */
663 #define TSW_LU_MAIN_VERSION_VER_LO_MASK (0xFF0000UL)
664 #define TSW_LU_MAIN_VERSION_VER_LO_SHIFT (16U)
665 #define TSW_LU_MAIN_VERSION_VER_LO_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_VERSION_VER_LO_MASK) >> TSW_LU_MAIN_VERSION_VER_LO_SHIFT)
666 
667 /*
668  * VER_REV (RO)
669  *
670  * revision number
671  */
672 #define TSW_LU_MAIN_VERSION_VER_REV_MASK (0xFFU)
673 #define TSW_LU_MAIN_VERSION_VER_REV_SHIFT (0U)
674 #define TSW_LU_MAIN_VERSION_VER_REV_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_VERSION_VER_REV_MASK) >> TSW_LU_MAIN_VERSION_VER_REV_SHIFT)
675 
676 /* Bitfield definition for register: LU_MAIN_INTF_ACTION */
677 /*
678  * UTAG (R/W)
679  *
680  * TSN user sideband information from ALMEM
681  */
682 #define TSW_LU_MAIN_INTF_ACTION_UTAG_MASK (0x1C00000UL)
683 #define TSW_LU_MAIN_INTF_ACTION_UTAG_SHIFT (22U)
684 #define TSW_LU_MAIN_INTF_ACTION_UTAG_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_INTF_ACTION_UTAG_SHIFT) & TSW_LU_MAIN_INTF_ACTION_UTAG_MASK)
685 #define TSW_LU_MAIN_INTF_ACTION_UTAG_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_INTF_ACTION_UTAG_MASK) >> TSW_LU_MAIN_INTF_ACTION_UTAG_SHIFT)
686 
687 /*
688  * QSEL (R/W)
689  *
690  * Define the traffic queue selection:
691  * 00 – use PCP field of VLAN, untagged frames use PCP of PVID
692  * 01 – use PCP field with global remapping list
693  * 10 – reserved
694  * 11 – use value QUEUE of Action List
695  */
696 #define TSW_LU_MAIN_INTF_ACTION_QSEL_MASK (0x300000UL)
697 #define TSW_LU_MAIN_INTF_ACTION_QSEL_SHIFT (20U)
698 #define TSW_LU_MAIN_INTF_ACTION_QSEL_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_INTF_ACTION_QSEL_SHIFT) & TSW_LU_MAIN_INTF_ACTION_QSEL_MASK)
699 #define TSW_LU_MAIN_INTF_ACTION_QSEL_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_INTF_ACTION_QSEL_MASK) >> TSW_LU_MAIN_INTF_ACTION_QSEL_SHIFT)
700 
701 /*
702  * DROP (R/W)
703  *
704  * 1 if frame should be dropped.
705  */
706 #define TSW_LU_MAIN_INTF_ACTION_DROP_MASK (0x80000UL)
707 #define TSW_LU_MAIN_INTF_ACTION_DROP_SHIFT (19U)
708 #define TSW_LU_MAIN_INTF_ACTION_DROP_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_INTF_ACTION_DROP_SHIFT) & TSW_LU_MAIN_INTF_ACTION_DROP_MASK)
709 #define TSW_LU_MAIN_INTF_ACTION_DROP_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_INTF_ACTION_DROP_MASK) >> TSW_LU_MAIN_INTF_ACTION_DROP_SHIFT)
710 
711 /*
712  * QUEUE (R/W)
713  *
714  * Select the Priority Queue for TSN TX, only used if QSEL=11
715  */
716 #define TSW_LU_MAIN_INTF_ACTION_QUEUE_MASK (0x70000UL)
717 #define TSW_LU_MAIN_INTF_ACTION_QUEUE_SHIFT (16U)
718 #define TSW_LU_MAIN_INTF_ACTION_QUEUE_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_INTF_ACTION_QUEUE_SHIFT) & TSW_LU_MAIN_INTF_ACTION_QUEUE_MASK)
719 #define TSW_LU_MAIN_INTF_ACTION_QUEUE_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_INTF_ACTION_QUEUE_MASK) >> TSW_LU_MAIN_INTF_ACTION_QUEUE_SHIFT)
720 
721 /*
722  * DEST (R/W)
723  *
724  * Select the destination ports of forwarded frame. It is coded in onehot/select way,
725  * where 0 is always route to null. Every bit is mapped to a port.
726  * 00000 – to null (frame to clear)
727  * 00001 – to port 0 (CPU Port)
728  * 00010 – to port 1
729  * 00100 – to port 2
730  * 01000 – to port 3
731  */
732 #define TSW_LU_MAIN_INTF_ACTION_DEST_MASK (0xFFFFU)
733 #define TSW_LU_MAIN_INTF_ACTION_DEST_SHIFT (0U)
734 #define TSW_LU_MAIN_INTF_ACTION_DEST_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_INTF_ACTION_DEST_SHIFT) & TSW_LU_MAIN_INTF_ACTION_DEST_MASK)
735 #define TSW_LU_MAIN_INTF_ACTION_DEST_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_INTF_ACTION_DEST_MASK) >> TSW_LU_MAIN_INTF_ACTION_DEST_SHIFT)
736 
737 /* Bitfield definition for register: LU_MAIN_BC_ACTION */
738 /*
739  * UTAG (R/W)
740  *
741  * TSN user sideband information from ALMEM
742  */
743 #define TSW_LU_MAIN_BC_ACTION_UTAG_MASK (0x1C00000UL)
744 #define TSW_LU_MAIN_BC_ACTION_UTAG_SHIFT (22U)
745 #define TSW_LU_MAIN_BC_ACTION_UTAG_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_BC_ACTION_UTAG_SHIFT) & TSW_LU_MAIN_BC_ACTION_UTAG_MASK)
746 #define TSW_LU_MAIN_BC_ACTION_UTAG_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_BC_ACTION_UTAG_MASK) >> TSW_LU_MAIN_BC_ACTION_UTAG_SHIFT)
747 
748 /*
749  * QSEL (R/W)
750  *
751  * Define the traffic queue selection:
752  * 00 – use PCP field of VLAN, untagged frames use PCP of PVID
753  * 01 – use PCP field with global remapping list
754  * 10 – reserved
755  * 11 – use value QUEUE of Action List
756  */
757 #define TSW_LU_MAIN_BC_ACTION_QSEL_MASK (0x300000UL)
758 #define TSW_LU_MAIN_BC_ACTION_QSEL_SHIFT (20U)
759 #define TSW_LU_MAIN_BC_ACTION_QSEL_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_BC_ACTION_QSEL_SHIFT) & TSW_LU_MAIN_BC_ACTION_QSEL_MASK)
760 #define TSW_LU_MAIN_BC_ACTION_QSEL_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_BC_ACTION_QSEL_MASK) >> TSW_LU_MAIN_BC_ACTION_QSEL_SHIFT)
761 
762 /*
763  * DROP (R/W)
764  *
765  * 1 if frame should be dropped.
766  */
767 #define TSW_LU_MAIN_BC_ACTION_DROP_MASK (0x80000UL)
768 #define TSW_LU_MAIN_BC_ACTION_DROP_SHIFT (19U)
769 #define TSW_LU_MAIN_BC_ACTION_DROP_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_BC_ACTION_DROP_SHIFT) & TSW_LU_MAIN_BC_ACTION_DROP_MASK)
770 #define TSW_LU_MAIN_BC_ACTION_DROP_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_BC_ACTION_DROP_MASK) >> TSW_LU_MAIN_BC_ACTION_DROP_SHIFT)
771 
772 /*
773  * QUEUE (R/W)
774  *
775  * Select the Priority Queue for TSN TX, only used if QSEL=11
776  */
777 #define TSW_LU_MAIN_BC_ACTION_QUEUE_MASK (0x70000UL)
778 #define TSW_LU_MAIN_BC_ACTION_QUEUE_SHIFT (16U)
779 #define TSW_LU_MAIN_BC_ACTION_QUEUE_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_BC_ACTION_QUEUE_SHIFT) & TSW_LU_MAIN_BC_ACTION_QUEUE_MASK)
780 #define TSW_LU_MAIN_BC_ACTION_QUEUE_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_BC_ACTION_QUEUE_MASK) >> TSW_LU_MAIN_BC_ACTION_QUEUE_SHIFT)
781 
782 /*
783  * DEST (R/W)
784  *
785  * Select the destination ports of forwarded frame. It is coded in onehot/select way,
786  * where 0 is always route to null. Every bit is mapped to a port.
787  * 00000 – to null (frame to clear)
788  * 00001 – to port 0 (CPU Port)
789  * 00010 – to port 1
790  * 00100 – to port 2
791  * 01000 – to port 3
792  */
793 #define TSW_LU_MAIN_BC_ACTION_DEST_MASK (0xFFFFU)
794 #define TSW_LU_MAIN_BC_ACTION_DEST_SHIFT (0U)
795 #define TSW_LU_MAIN_BC_ACTION_DEST_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_BC_ACTION_DEST_SHIFT) & TSW_LU_MAIN_BC_ACTION_DEST_MASK)
796 #define TSW_LU_MAIN_BC_ACTION_DEST_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_BC_ACTION_DEST_MASK) >> TSW_LU_MAIN_BC_ACTION_DEST_SHIFT)
797 
798 /* Bitfield definition for register: LU_MAIN_NN_ACTION */
799 /*
800  * UTAG (R/W)
801  *
802  * TSN user sideband information from ALMEM
803  */
804 #define TSW_LU_MAIN_NN_ACTION_UTAG_MASK (0x1C00000UL)
805 #define TSW_LU_MAIN_NN_ACTION_UTAG_SHIFT (22U)
806 #define TSW_LU_MAIN_NN_ACTION_UTAG_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_NN_ACTION_UTAG_SHIFT) & TSW_LU_MAIN_NN_ACTION_UTAG_MASK)
807 #define TSW_LU_MAIN_NN_ACTION_UTAG_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_NN_ACTION_UTAG_MASK) >> TSW_LU_MAIN_NN_ACTION_UTAG_SHIFT)
808 
809 /*
810  * QSEL (R/W)
811  *
812  * Define the traffic queue selection:
813  * 00 – use PCP field of VLAN, untagged frames use PCP of PVID
814  * 01 – use PCP field with global remapping list
815  * 10 – reserved
816  * 11 – use value QUEUE of Action List
817  */
818 #define TSW_LU_MAIN_NN_ACTION_QSEL_MASK (0x300000UL)
819 #define TSW_LU_MAIN_NN_ACTION_QSEL_SHIFT (20U)
820 #define TSW_LU_MAIN_NN_ACTION_QSEL_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_NN_ACTION_QSEL_SHIFT) & TSW_LU_MAIN_NN_ACTION_QSEL_MASK)
821 #define TSW_LU_MAIN_NN_ACTION_QSEL_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_NN_ACTION_QSEL_MASK) >> TSW_LU_MAIN_NN_ACTION_QSEL_SHIFT)
822 
823 /*
824  * DROP (R/W)
825  *
826  * 1 if frame should be dropped.
827  */
828 #define TSW_LU_MAIN_NN_ACTION_DROP_MASK (0x80000UL)
829 #define TSW_LU_MAIN_NN_ACTION_DROP_SHIFT (19U)
830 #define TSW_LU_MAIN_NN_ACTION_DROP_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_NN_ACTION_DROP_SHIFT) & TSW_LU_MAIN_NN_ACTION_DROP_MASK)
831 #define TSW_LU_MAIN_NN_ACTION_DROP_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_NN_ACTION_DROP_MASK) >> TSW_LU_MAIN_NN_ACTION_DROP_SHIFT)
832 
833 /*
834  * QUEUE (R/W)
835  *
836  * Select the Priority Queue for TSN TX, only used if QSEL=11
837  */
838 #define TSW_LU_MAIN_NN_ACTION_QUEUE_MASK (0x70000UL)
839 #define TSW_LU_MAIN_NN_ACTION_QUEUE_SHIFT (16U)
840 #define TSW_LU_MAIN_NN_ACTION_QUEUE_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_NN_ACTION_QUEUE_SHIFT) & TSW_LU_MAIN_NN_ACTION_QUEUE_MASK)
841 #define TSW_LU_MAIN_NN_ACTION_QUEUE_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_NN_ACTION_QUEUE_MASK) >> TSW_LU_MAIN_NN_ACTION_QUEUE_SHIFT)
842 
843 /*
844  * DEST (R/W)
845  *
846  * Select the destination ports of forwarded frame. It is coded in onehot/select way,
847  * where 0 is always route to null. Every bit is mapped to a port.
848  * 00000 – to null (frame to clear)
849  * 00001 – to port 0 (CPU Port)
850  * 00010 – to port 1
851  * 00100 – to port 2
852  * 01000 – to port 3
853  */
854 #define TSW_LU_MAIN_NN_ACTION_DEST_MASK (0xFFFFU)
855 #define TSW_LU_MAIN_NN_ACTION_DEST_SHIFT (0U)
856 #define TSW_LU_MAIN_NN_ACTION_DEST_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_NN_ACTION_DEST_SHIFT) & TSW_LU_MAIN_NN_ACTION_DEST_MASK)
857 #define TSW_LU_MAIN_NN_ACTION_DEST_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_NN_ACTION_DEST_MASK) >> TSW_LU_MAIN_NN_ACTION_DEST_SHIFT)
858 
859 /* Bitfield definition for register: APB2AXIS_CAM_STS */
860 /*
861  * BUSY (RO)
862  *
863  * the controller is writing data and/or data is pending
864  */
865 #define TSW_APB2AXIS_CAM_STS_BUSY_MASK (0x2U)
866 #define TSW_APB2AXIS_CAM_STS_BUSY_SHIFT (1U)
867 #define TSW_APB2AXIS_CAM_STS_BUSY_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_CAM_STS_BUSY_MASK) >> TSW_APB2AXIS_CAM_STS_BUSY_SHIFT)
868 
869 /*
870  * RDY (RO)
871  *
872  * the new data is written to data register
873  */
874 #define TSW_APB2AXIS_CAM_STS_RDY_MASK (0x1U)
875 #define TSW_APB2AXIS_CAM_STS_RDY_SHIFT (0U)
876 #define TSW_APB2AXIS_CAM_STS_RDY_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_CAM_STS_RDY_MASK) >> TSW_APB2AXIS_CAM_STS_RDY_SHIFT)
877 
878 /* Bitfield definition for register: APB2AXIS_CAM_REQ_CNT */
879 /*
880  * WRCNT (RO)
881  *
882  * number of streams in queue
883  */
884 #define TSW_APB2AXIS_CAM_REQ_CNT_WRCNT_MASK (0xFFU)
885 #define TSW_APB2AXIS_CAM_REQ_CNT_WRCNT_SHIFT (0U)
886 #define TSW_APB2AXIS_CAM_REQ_CNT_WRCNT_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_CAM_REQ_CNT_WRCNT_MASK) >> TSW_APB2AXIS_CAM_REQ_CNT_WRCNT_SHIFT)
887 
888 /* Bitfield definition for register: APB2AXIS_CAM_FILLSTS */
889 /*
890  * FULL (RO)
891  *
892  * frame was dropped because the internal descriptor FIFO is full
893  */
894 #define TSW_APB2AXIS_CAM_FILLSTS_FULL_MASK (0x10U)
895 #define TSW_APB2AXIS_CAM_FILLSTS_FULL_SHIFT (4U)
896 #define TSW_APB2AXIS_CAM_FILLSTS_FULL_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_CAM_FILLSTS_FULL_MASK) >> TSW_APB2AXIS_CAM_FILLSTS_FULL_SHIFT)
897 
898 /*
899  * EMPTY (RO)
900  *
901  * FD FIFO failure, internal controller lost synchronization
902  */
903 #define TSW_APB2AXIS_CAM_FILLSTS_EMPTY_MASK (0x1U)
904 #define TSW_APB2AXIS_CAM_FILLSTS_EMPTY_SHIFT (0U)
905 #define TSW_APB2AXIS_CAM_FILLSTS_EMPTY_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_CAM_FILLSTS_EMPTY_MASK) >> TSW_APB2AXIS_CAM_FILLSTS_EMPTY_SHIFT)
906 
907 /* Bitfield definition for register: APB2AXIS_CAM_RESET */
908 /*
909  * RESET (W1C)
910  *
911  * resets controller and clears all pending stream data
912  */
913 #define TSW_APB2AXIS_CAM_RESET_RESET_MASK (0x1U)
914 #define TSW_APB2AXIS_CAM_RESET_RESET_SHIFT (0U)
915 #define TSW_APB2AXIS_CAM_RESET_RESET_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_CAM_RESET_RESET_SHIFT) & TSW_APB2AXIS_CAM_RESET_RESET_MASK)
916 #define TSW_APB2AXIS_CAM_RESET_RESET_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_CAM_RESET_RESET_MASK) >> TSW_APB2AXIS_CAM_RESET_RESET_SHIFT)
917 
918 /* Bitfield definition for register: APB2AXIS_CAM_PARAM */
919 /*
920  * DEPTH (RO)
921  *
922  * number of configured buffer depth
923  */
924 #define TSW_APB2AXIS_CAM_PARAM_DEPTH_MASK (0xFF00U)
925 #define TSW_APB2AXIS_CAM_PARAM_DEPTH_SHIFT (8U)
926 #define TSW_APB2AXIS_CAM_PARAM_DEPTH_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_CAM_PARAM_DEPTH_MASK) >> TSW_APB2AXIS_CAM_PARAM_DEPTH_SHIFT)
927 
928 /*
929  * WORDLEN_BYTE (RO)
930  *
931  * number of configured 32bit words for this controller
932  */
933 #define TSW_APB2AXIS_CAM_PARAM_WORDLEN_BYTE_MASK (0xFFU)
934 #define TSW_APB2AXIS_CAM_PARAM_WORDLEN_BYTE_SHIFT (0U)
935 #define TSW_APB2AXIS_CAM_PARAM_WORDLEN_BYTE_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_CAM_PARAM_WORDLEN_BYTE_MASK) >> TSW_APB2AXIS_CAM_PARAM_WORDLEN_BYTE_SHIFT)
936 
937 /* Bitfield definition for register: APB2AXIS_CAM_REQDATA_0 */
938 /*
939  * ENTRY_NUM (R/W)
940  *
941  * entry number
942  */
943 #define TSW_APB2AXIS_CAM_REQDATA_0_ENTRY_NUM_MASK (0xFFFF0000UL)
944 #define TSW_APB2AXIS_CAM_REQDATA_0_ENTRY_NUM_SHIFT (16U)
945 #define TSW_APB2AXIS_CAM_REQDATA_0_ENTRY_NUM_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_CAM_REQDATA_0_ENTRY_NUM_SHIFT) & TSW_APB2AXIS_CAM_REQDATA_0_ENTRY_NUM_MASK)
946 #define TSW_APB2AXIS_CAM_REQDATA_0_ENTRY_NUM_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_CAM_REQDATA_0_ENTRY_NUM_MASK) >> TSW_APB2AXIS_CAM_REQDATA_0_ENTRY_NUM_SHIFT)
947 
948 /*
949  * TYPE (R/W)
950  *
951  * select between set, clear or clear all
952  */
953 #define TSW_APB2AXIS_CAM_REQDATA_0_TYPE_MASK (0x300U)
954 #define TSW_APB2AXIS_CAM_REQDATA_0_TYPE_SHIFT (8U)
955 #define TSW_APB2AXIS_CAM_REQDATA_0_TYPE_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_CAM_REQDATA_0_TYPE_SHIFT) & TSW_APB2AXIS_CAM_REQDATA_0_TYPE_MASK)
956 #define TSW_APB2AXIS_CAM_REQDATA_0_TYPE_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_CAM_REQDATA_0_TYPE_MASK) >> TSW_APB2AXIS_CAM_REQDATA_0_TYPE_SHIFT)
957 
958 /*
959  * CH (R/W)
960  *
961  * CAM APB2AXIS channel selection
962  */
963 #define TSW_APB2AXIS_CAM_REQDATA_0_CH_MASK (0x1U)
964 #define TSW_APB2AXIS_CAM_REQDATA_0_CH_SHIFT (0U)
965 #define TSW_APB2AXIS_CAM_REQDATA_0_CH_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_CAM_REQDATA_0_CH_SHIFT) & TSW_APB2AXIS_CAM_REQDATA_0_CH_MASK)
966 #define TSW_APB2AXIS_CAM_REQDATA_0_CH_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_CAM_REQDATA_0_CH_MASK) >> TSW_APB2AXIS_CAM_REQDATA_0_CH_SHIFT)
967 
968 /* Bitfield definition for register: APB2AXIS_CAM_REQDATA_1 */
969 /*
970  * DESTMAC_LO_PORT_VEC (R/W)
971  *
972  * dest-mac[31:0] when CH=0；PORT_VEC when CH=1
973  */
974 #define TSW_APB2AXIS_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_MASK (0xFFFFFFFFUL)
975 #define TSW_APB2AXIS_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_SHIFT (0U)
976 #define TSW_APB2AXIS_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_SHIFT) & TSW_APB2AXIS_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_MASK)
977 #define TSW_APB2AXIS_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_MASK) >> TSW_APB2AXIS_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_SHIFT)
978 
979 /* Bitfield definition for register: APB2AXIS_CAM_REQDATA_2 */
980 /*
981  * VID (R/W)
982  *
983  * VLAN-ID value (12 bit) for the VLAN_ID table. Use the fefault VLAN-ID(VID=1), if setup an entry for non-VLAN traffic.
984  */
985 #define TSW_APB2AXIS_CAM_REQDATA_2_VID_MASK (0xFFF0000UL)
986 #define TSW_APB2AXIS_CAM_REQDATA_2_VID_SHIFT (16U)
987 #define TSW_APB2AXIS_CAM_REQDATA_2_VID_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_CAM_REQDATA_2_VID_SHIFT) & TSW_APB2AXIS_CAM_REQDATA_2_VID_MASK)
988 #define TSW_APB2AXIS_CAM_REQDATA_2_VID_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_CAM_REQDATA_2_VID_MASK) >> TSW_APB2AXIS_CAM_REQDATA_2_VID_SHIFT)
989 
990 /*
991  * DESTMAC_HI (R/W)
992  *
993  * dest-mac[47:32] when CH=0
994  */
995 #define TSW_APB2AXIS_CAM_REQDATA_2_DESTMAC_HI_MASK (0xFFFFU)
996 #define TSW_APB2AXIS_CAM_REQDATA_2_DESTMAC_HI_SHIFT (0U)
997 #define TSW_APB2AXIS_CAM_REQDATA_2_DESTMAC_HI_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_CAM_REQDATA_2_DESTMAC_HI_SHIFT) & TSW_APB2AXIS_CAM_REQDATA_2_DESTMAC_HI_MASK)
998 #define TSW_APB2AXIS_CAM_REQDATA_2_DESTMAC_HI_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_CAM_REQDATA_2_DESTMAC_HI_MASK) >> TSW_APB2AXIS_CAM_REQDATA_2_DESTMAC_HI_SHIFT)
999 
1000 /* Bitfield definition for register: APB2AXIS_ALMEM_STS */
1001 /*
1002  * BUSY (RO)
1003  *
1004  * the controller is writing data and/or data is pending
1005  */
1006 #define TSW_APB2AXIS_ALMEM_STS_BUSY_MASK (0x2U)
1007 #define TSW_APB2AXIS_ALMEM_STS_BUSY_SHIFT (1U)
1008 #define TSW_APB2AXIS_ALMEM_STS_BUSY_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_STS_BUSY_MASK) >> TSW_APB2AXIS_ALMEM_STS_BUSY_SHIFT)
1009 
1010 /*
1011  * RDY (RO)
1012  *
1013  * the new data is written to data register
1014  */
1015 #define TSW_APB2AXIS_ALMEM_STS_RDY_MASK (0x1U)
1016 #define TSW_APB2AXIS_ALMEM_STS_RDY_SHIFT (0U)
1017 #define TSW_APB2AXIS_ALMEM_STS_RDY_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_STS_RDY_MASK) >> TSW_APB2AXIS_ALMEM_STS_RDY_SHIFT)
1018 
1019 /* Bitfield definition for register: APB2AXIS_ALMEM_REQ_CNT */
1020 /*
1021  * WRCNT (RO)
1022  *
1023  * number of streams in queue
1024  */
1025 #define TSW_APB2AXIS_ALMEM_REQ_CNT_WRCNT_MASK (0xFFU)
1026 #define TSW_APB2AXIS_ALMEM_REQ_CNT_WRCNT_SHIFT (0U)
1027 #define TSW_APB2AXIS_ALMEM_REQ_CNT_WRCNT_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQ_CNT_WRCNT_MASK) >> TSW_APB2AXIS_ALMEM_REQ_CNT_WRCNT_SHIFT)
1028 
1029 /* Bitfield definition for register: APB2AXIS_ALMEM_FILLSTS */
1030 /*
1031  * FULL (RO)
1032  *
1033  * frame was dropped because the internal descriptor FIFO is full
1034  */
1035 #define TSW_APB2AXIS_ALMEM_FILLSTS_FULL_MASK (0x10U)
1036 #define TSW_APB2AXIS_ALMEM_FILLSTS_FULL_SHIFT (4U)
1037 #define TSW_APB2AXIS_ALMEM_FILLSTS_FULL_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_FILLSTS_FULL_MASK) >> TSW_APB2AXIS_ALMEM_FILLSTS_FULL_SHIFT)
1038 
1039 /*
1040  * EMPTY (RO)
1041  *
1042  * FD FIFO failure, internal controller lost synchronization
1043  */
1044 #define TSW_APB2AXIS_ALMEM_FILLSTS_EMPTY_MASK (0x1U)
1045 #define TSW_APB2AXIS_ALMEM_FILLSTS_EMPTY_SHIFT (0U)
1046 #define TSW_APB2AXIS_ALMEM_FILLSTS_EMPTY_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_FILLSTS_EMPTY_MASK) >> TSW_APB2AXIS_ALMEM_FILLSTS_EMPTY_SHIFT)
1047 
1048 /* Bitfield definition for register: APB2AXIS_ALMEM_RESET */
1049 /*
1050  * RESET (W1C)
1051  *
1052  * resets controller and clears all pending stream data
1053  */
1054 #define TSW_APB2AXIS_ALMEM_RESET_RESET_MASK (0x1U)
1055 #define TSW_APB2AXIS_ALMEM_RESET_RESET_SHIFT (0U)
1056 #define TSW_APB2AXIS_ALMEM_RESET_RESET_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_RESET_RESET_SHIFT) & TSW_APB2AXIS_ALMEM_RESET_RESET_MASK)
1057 #define TSW_APB2AXIS_ALMEM_RESET_RESET_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_RESET_RESET_MASK) >> TSW_APB2AXIS_ALMEM_RESET_RESET_SHIFT)
1058 
1059 /* Bitfield definition for register: APB2AXIS_ALMEM_PARAM */
1060 /*
1061  * DEPTH (RO)
1062  *
1063  * number of configured buffer depth
1064  */
1065 #define TSW_APB2AXIS_ALMEM_PARAM_DEPTH_MASK (0xFF00U)
1066 #define TSW_APB2AXIS_ALMEM_PARAM_DEPTH_SHIFT (8U)
1067 #define TSW_APB2AXIS_ALMEM_PARAM_DEPTH_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_PARAM_DEPTH_MASK) >> TSW_APB2AXIS_ALMEM_PARAM_DEPTH_SHIFT)
1068 
1069 /*
1070  * WORDLEN_BYTE (RO)
1071  *
1072  * number of configured 32bit words for this controller
1073  */
1074 #define TSW_APB2AXIS_ALMEM_PARAM_WORDLEN_BYTE_MASK (0xFFU)
1075 #define TSW_APB2AXIS_ALMEM_PARAM_WORDLEN_BYTE_SHIFT (0U)
1076 #define TSW_APB2AXIS_ALMEM_PARAM_WORDLEN_BYTE_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_PARAM_WORDLEN_BYTE_MASK) >> TSW_APB2AXIS_ALMEM_PARAM_WORDLEN_BYTE_SHIFT)
1077 
1078 /* Bitfield definition for register: APB2AXIS_ALMEM_REQDATA_0 */
1079 /*
1080  * UTAG (R/W)
1081  *
1082  * user sideband information
1083  */
1084 #define TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_MASK (0x1C00000UL)
1085 #define TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_SHIFT (22U)
1086 #define TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_MASK)
1087 #define TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_SHIFT)
1088 
1089 /*
1090  * QSEL (R/W)
1091  *
1092  * define the traffic queue selection
1093  */
1094 #define TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_MASK (0x300000UL)
1095 #define TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_SHIFT (20U)
1096 #define TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_MASK)
1097 #define TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_SHIFT)
1098 
1099 /*
1100  * DROP (R/W)
1101  *
1102  * frame should dropped
1103  */
1104 #define TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_MASK (0x80000UL)
1105 #define TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_SHIFT (19U)
1106 #define TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_MASK)
1107 #define TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_SHIFT)
1108 
1109 /*
1110  * QUEUE (R/W)
1111  *
1112  * select the priority queue if qsel=11
1113  */
1114 #define TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_MASK (0x70000UL)
1115 #define TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_SHIFT (16U)
1116 #define TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_MASK)
1117 #define TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_SHIFT)
1118 
1119 /*
1120  * DEST (R/W)
1121  *
1122  * destination ports
1123  */
1124 #define TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_MASK (0xFFFFU)
1125 #define TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_SHIFT (0U)
1126 #define TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_MASK)
1127 #define TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_SHIFT)
1128 
1129 /* Bitfield definition for register: APB2AXIS_ALMEM_REQDATA_1 */
1130 /*
1131  * WR_NRD (R/W)
1132  *
1133  * 1 for write and 0 for read
1134  */
1135 #define TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_MASK (0x80000000UL)
1136 #define TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_SHIFT (31U)
1137 #define TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_MASK)
1138 #define TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_SHIFT)
1139 
1140 /*
1141  * RESP (R/W)
1142  *
1143  * write response enable
1144  */
1145 #define TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_MASK (0x40000000UL)
1146 #define TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_SHIFT (30U)
1147 #define TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_MASK)
1148 #define TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_SHIFT)
1149 
1150 /*
1151  * ENTRY_NUM (R/W)
1152  *
1153  * define the entry number for reading and writing
1154  */
1155 #define TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_MASK (0xFFFFU)
1156 #define TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_SHIFT (0U)
1157 #define TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_MASK)
1158 #define TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_SHIFT)
1159 
1160 /* Bitfield definition for register: AXIS2APB_ALMEM_STS */
1161 /*
1162  * BUSY (RO)
1163  *
1164  * the controller is writing data and/or data is pending
1165  */
1166 #define TSW_AXIS2APB_ALMEM_STS_BUSY_MASK (0x2U)
1167 #define TSW_AXIS2APB_ALMEM_STS_BUSY_SHIFT (1U)
1168 #define TSW_AXIS2APB_ALMEM_STS_BUSY_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_STS_BUSY_MASK) >> TSW_AXIS2APB_ALMEM_STS_BUSY_SHIFT)
1169 
1170 /*
1171  * RDY (RO)
1172  *
1173  * the new data is written to data register
1174  */
1175 #define TSW_AXIS2APB_ALMEM_STS_RDY_MASK (0x1U)
1176 #define TSW_AXIS2APB_ALMEM_STS_RDY_SHIFT (0U)
1177 #define TSW_AXIS2APB_ALMEM_STS_RDY_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_STS_RDY_MASK) >> TSW_AXIS2APB_ALMEM_STS_RDY_SHIFT)
1178 
1179 /* Bitfield definition for register: AXIS2APB_ALMEM_RESP_CNT */
1180 /*
1181  * RDCNT (RO)
1182  *
1183  * number of streams in queue
1184  */
1185 #define TSW_AXIS2APB_ALMEM_RESP_CNT_RDCNT_MASK (0xFFU)
1186 #define TSW_AXIS2APB_ALMEM_RESP_CNT_RDCNT_SHIFT (0U)
1187 #define TSW_AXIS2APB_ALMEM_RESP_CNT_RDCNT_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESP_CNT_RDCNT_MASK) >> TSW_AXIS2APB_ALMEM_RESP_CNT_RDCNT_SHIFT)
1188 
1189 /* Bitfield definition for register: AXIS2APB_ALMEM_FILLSTS */
1190 /*
1191  * FULL (RO)
1192  *
1193  * FD FIFO full
1194  */
1195 #define TSW_AXIS2APB_ALMEM_FILLSTS_FULL_MASK (0x10U)
1196 #define TSW_AXIS2APB_ALMEM_FILLSTS_FULL_SHIFT (4U)
1197 #define TSW_AXIS2APB_ALMEM_FILLSTS_FULL_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_FILLSTS_FULL_MASK) >> TSW_AXIS2APB_ALMEM_FILLSTS_FULL_SHIFT)
1198 
1199 /*
1200  * EMPTY (RO)
1201  *
1202  * FD FIFO failure
1203  */
1204 #define TSW_AXIS2APB_ALMEM_FILLSTS_EMPTY_MASK (0x1U)
1205 #define TSW_AXIS2APB_ALMEM_FILLSTS_EMPTY_SHIFT (0U)
1206 #define TSW_AXIS2APB_ALMEM_FILLSTS_EMPTY_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_FILLSTS_EMPTY_MASK) >> TSW_AXIS2APB_ALMEM_FILLSTS_EMPTY_SHIFT)
1207 
1208 /* Bitfield definition for register: AXIS2APB_ALMEM_RESET */
1209 /*
1210  * RESET (R/W)
1211  *
1212  * Resets controller and clears all pending stream data
1213  */
1214 #define TSW_AXIS2APB_ALMEM_RESET_RESET_MASK (0x1U)
1215 #define TSW_AXIS2APB_ALMEM_RESET_RESET_SHIFT (0U)
1216 #define TSW_AXIS2APB_ALMEM_RESET_RESET_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESET_RESET_SHIFT) & TSW_AXIS2APB_ALMEM_RESET_RESET_MASK)
1217 #define TSW_AXIS2APB_ALMEM_RESET_RESET_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESET_RESET_MASK) >> TSW_AXIS2APB_ALMEM_RESET_RESET_SHIFT)
1218 
1219 /* Bitfield definition for register: AXIS2APB_ALMEM_PARAM */
1220 /*
1221  * DEPTH (RO)
1222  *
1223  * number of configured buffer depth
1224  */
1225 #define TSW_AXIS2APB_ALMEM_PARAM_DEPTH_MASK (0xFF00U)
1226 #define TSW_AXIS2APB_ALMEM_PARAM_DEPTH_SHIFT (8U)
1227 #define TSW_AXIS2APB_ALMEM_PARAM_DEPTH_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_PARAM_DEPTH_MASK) >> TSW_AXIS2APB_ALMEM_PARAM_DEPTH_SHIFT)
1228 
1229 /*
1230  * WORDLEN_BYTE (RO)
1231  *
1232  * number of configured 32bit for this controller
1233  */
1234 #define TSW_AXIS2APB_ALMEM_PARAM_WORDLEN_BYTE_MASK (0xFFU)
1235 #define TSW_AXIS2APB_ALMEM_PARAM_WORDLEN_BYTE_SHIFT (0U)
1236 #define TSW_AXIS2APB_ALMEM_PARAM_WORDLEN_BYTE_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_PARAM_WORDLEN_BYTE_MASK) >> TSW_AXIS2APB_ALMEM_PARAM_WORDLEN_BYTE_SHIFT)
1237 
1238 /* Bitfield definition for register: AXIS2APB_ALMEM_RESPDATA_0 */
1239 /*
1240  * UTAG (R/W)
1241  *
1242  * user sideband information
1243  */
1244 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_MASK (0x1C00000UL)
1245 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_SHIFT (22U)
1246 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_MASK)
1247 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_SHIFT)
1248 
1249 /*
1250  * QSEL (R/W)
1251  *
1252  * define the traffic queue selection
1253  */
1254 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_MASK (0x300000UL)
1255 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_SHIFT (20U)
1256 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_MASK)
1257 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_SHIFT)
1258 
1259 /*
1260  * DROP (R/W)
1261  *
1262  * frame should dropped
1263  */
1264 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_MASK (0x80000UL)
1265 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_SHIFT (19U)
1266 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_MASK)
1267 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_SHIFT)
1268 
1269 /*
1270  * QUEUE (R/W)
1271  *
1272  * select the priority queue if qsel=11
1273  */
1274 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_MASK (0x70000UL)
1275 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_SHIFT (16U)
1276 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_MASK)
1277 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_SHIFT)
1278 
1279 /*
1280  * DEST (R/W)
1281  *
1282  * destination ports
1283  */
1284 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_MASK (0xFFFFU)
1285 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_SHIFT (0U)
1286 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_MASK)
1287 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_SHIFT)
1288 
1289 /* Bitfield definition for register: AXIS2APB_ALMEM_RESPDATA_1 */
1290 /*
1291  * WR_NRD (R/W)
1292  *
1293  * 1 for write and 0 for read
1294  */
1295 #define TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_MASK (0x80000000UL)
1296 #define TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_SHIFT (31U)
1297 #define TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_MASK)
1298 #define TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_SHIFT)
1299 
1300 /*
1301  * RESP (R/W)
1302  *
1303  * write response enable
1304  */
1305 #define TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_MASK (0x40000000UL)
1306 #define TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_SHIFT (30U)
1307 #define TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_MASK)
1308 #define TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_SHIFT)
1309 
1310 /*
1311  * ENTRY_NUM (R/W)
1312  *
1313  * define the entry number for reading and writing
1314  */
1315 #define TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_MASK (0xFFFFU)
1316 #define TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_SHIFT (0U)
1317 #define TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_MASK)
1318 #define TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_SHIFT)
1319 
1320 /* Bitfield definition for register array: HITMEM */
1321 /*
1322  * HITMEM_REG (RW)
1323  *
1324  * Every bit represents a lookup entry starting with bit 0
1325  * as entry 0. The memory can be written and cleared by the host system via common memory-mapped
1326  * bus access.
1327  */
1328 #define TSW_HITMEM_HITMEM_REG_MASK (0xFFFFFFFFUL)
1329 #define TSW_HITMEM_HITMEM_REG_SHIFT (0U)
1330 #define TSW_HITMEM_HITMEM_REG_SET(x) (((uint32_t)(x) << TSW_HITMEM_HITMEM_REG_SHIFT) & TSW_HITMEM_HITMEM_REG_MASK)
1331 #define TSW_HITMEM_HITMEM_REG_GET(x) (((uint32_t)(x) & TSW_HITMEM_HITMEM_REG_MASK) >> TSW_HITMEM_HITMEM_REG_SHIFT)
1332 
1333 /* Bitfield definition for register: APB2AXIS_LOOKUP_STS */
1334 /*
1335  * BUSY (RO)
1336  *
1337  * the controller is writing data and/or data is pending
1338  */
1339 #define TSW_APB2AXIS_LOOKUP_STS_BUSY_MASK (0x2U)
1340 #define TSW_APB2AXIS_LOOKUP_STS_BUSY_SHIFT (1U)
1341 #define TSW_APB2AXIS_LOOKUP_STS_BUSY_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_STS_BUSY_MASK) >> TSW_APB2AXIS_LOOKUP_STS_BUSY_SHIFT)
1342 
1343 /*
1344  * RDY (RO)
1345  *
1346  * the new data is written to data register
1347  */
1348 #define TSW_APB2AXIS_LOOKUP_STS_RDY_MASK (0x1U)
1349 #define TSW_APB2AXIS_LOOKUP_STS_RDY_SHIFT (0U)
1350 #define TSW_APB2AXIS_LOOKUP_STS_RDY_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_STS_RDY_MASK) >> TSW_APB2AXIS_LOOKUP_STS_RDY_SHIFT)
1351 
1352 /* Bitfield definition for register: APB2AXIS_LOOKUP_REQ_CNT */
1353 /*
1354  * WRCNT (RO)
1355  *
1356  * number of streams in queue
1357  */
1358 #define TSW_APB2AXIS_LOOKUP_REQ_CNT_WRCNT_MASK (0xFFU)
1359 #define TSW_APB2AXIS_LOOKUP_REQ_CNT_WRCNT_SHIFT (0U)
1360 #define TSW_APB2AXIS_LOOKUP_REQ_CNT_WRCNT_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_REQ_CNT_WRCNT_MASK) >> TSW_APB2AXIS_LOOKUP_REQ_CNT_WRCNT_SHIFT)
1361 
1362 /* Bitfield definition for register: APB2AXIS_LOOKUP_FILLSTS */
1363 /*
1364  * FULL (RO)
1365  *
1366  * FD FIFO full
1367  */
1368 #define TSW_APB2AXIS_LOOKUP_FILLSTS_FULL_MASK (0x10U)
1369 #define TSW_APB2AXIS_LOOKUP_FILLSTS_FULL_SHIFT (4U)
1370 #define TSW_APB2AXIS_LOOKUP_FILLSTS_FULL_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_FILLSTS_FULL_MASK) >> TSW_APB2AXIS_LOOKUP_FILLSTS_FULL_SHIFT)
1371 
1372 /*
1373  * EMPTY (RO)
1374  *
1375  * FD FIFO failure
1376  */
1377 #define TSW_APB2AXIS_LOOKUP_FILLSTS_EMPTY_MASK (0x1U)
1378 #define TSW_APB2AXIS_LOOKUP_FILLSTS_EMPTY_SHIFT (0U)
1379 #define TSW_APB2AXIS_LOOKUP_FILLSTS_EMPTY_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_FILLSTS_EMPTY_MASK) >> TSW_APB2AXIS_LOOKUP_FILLSTS_EMPTY_SHIFT)
1380 
1381 /* Bitfield definition for register: APB2AXIS_LOOKUP_RESET */
1382 /*
1383  * RESET (R/W)
1384  *
1385  * Resets controller and clears all pending stream data
1386  */
1387 #define TSW_APB2AXIS_LOOKUP_RESET_RESET_MASK (0x1U)
1388 #define TSW_APB2AXIS_LOOKUP_RESET_RESET_SHIFT (0U)
1389 #define TSW_APB2AXIS_LOOKUP_RESET_RESET_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_LOOKUP_RESET_RESET_SHIFT) & TSW_APB2AXIS_LOOKUP_RESET_RESET_MASK)
1390 #define TSW_APB2AXIS_LOOKUP_RESET_RESET_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_RESET_RESET_MASK) >> TSW_APB2AXIS_LOOKUP_RESET_RESET_SHIFT)
1391 
1392 /* Bitfield definition for register: APB2AXIS_LOOKUP_PARAM */
1393 /*
1394  * DEPTH (RO)
1395  *
1396  * number of configured buffer depth
1397  */
1398 #define TSW_APB2AXIS_LOOKUP_PARAM_DEPTH_MASK (0xFF00U)
1399 #define TSW_APB2AXIS_LOOKUP_PARAM_DEPTH_SHIFT (8U)
1400 #define TSW_APB2AXIS_LOOKUP_PARAM_DEPTH_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_PARAM_DEPTH_MASK) >> TSW_APB2AXIS_LOOKUP_PARAM_DEPTH_SHIFT)
1401 
1402 /*
1403  * WORDLEN_BYTE (RO)
1404  *
1405  * number of configured 32bit for this controller
1406  */
1407 #define TSW_APB2AXIS_LOOKUP_PARAM_WORDLEN_BYTE_MASK (0xFFU)
1408 #define TSW_APB2AXIS_LOOKUP_PARAM_WORDLEN_BYTE_SHIFT (0U)
1409 #define TSW_APB2AXIS_LOOKUP_PARAM_WORDLEN_BYTE_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_PARAM_WORDLEN_BYTE_MASK) >> TSW_APB2AXIS_LOOKUP_PARAM_WORDLEN_BYTE_SHIFT)
1410 
1411 /* Bitfield definition for register: APB2AXIS_LOOKUP_REQDATA_0 */
1412 /*
1413  * DESTMAC (RW)
1414  *
1415  * Holding the first four bytes of requested MAC address.
1416  */
1417 #define TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_MASK (0xFFFFFFFFUL)
1418 #define TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_SHIFT (0U)
1419 #define TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_SHIFT) & TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_MASK)
1420 #define TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_MASK) >> TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_SHIFT)
1421 
1422 /* Bitfield definition for register: APB2AXIS_LOOKUP_REQDATA_1 */
1423 /*
1424  * DESTMAC (RW)
1425  *
1426  * Holding the last two bytes of requested MAC address.
1427  */
1428 #define TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_MASK (0xFFFFU)
1429 #define TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_SHIFT (0U)
1430 #define TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_SHIFT) & TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_MASK)
1431 #define TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_MASK) >> TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_SHIFT)
1432 
1433 /* Bitfield definition for register: APB2AXIS_LOOKUP_REQDATA_3 */
1434 /*
1435  * IS_VLAN (RW)
1436  *
1437  * Tell the LOOKUP module the requested traffic is VLAN tagged.
1438  */
1439 #define TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_MASK (0x10000UL)
1440 #define TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_SHIFT (16U)
1441 #define TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_SHIFT) & TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_MASK)
1442 #define TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_MASK) >> TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_SHIFT)
1443 
1444 /*
1445  * VLAN_TCI (RW)
1446  *
1447  * Set the requested traffic VLAN_TCI, if IS_VLAN=1.
1448  */
1449 #define TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_MASK (0xFFFFU)
1450 #define TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_SHIFT (0U)
1451 #define TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_SHIFT) & TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_MASK)
1452 #define TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_MASK) >> TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_SHIFT)
1453 
1454 /* Bitfield definition for register: AXIS2APB_LOOKUP_STS */
1455 /*
1456  * BUSY (RO)
1457  *
1458  * the controller is writing data and/or data is pending
1459  */
1460 #define TSW_AXIS2APB_LOOKUP_STS_BUSY_MASK (0x2U)
1461 #define TSW_AXIS2APB_LOOKUP_STS_BUSY_SHIFT (1U)
1462 #define TSW_AXIS2APB_LOOKUP_STS_BUSY_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_STS_BUSY_MASK) >> TSW_AXIS2APB_LOOKUP_STS_BUSY_SHIFT)
1463 
1464 /*
1465  * RDY (RO)
1466  *
1467  * the new data is written to data register
1468  */
1469 #define TSW_AXIS2APB_LOOKUP_STS_RDY_MASK (0x1U)
1470 #define TSW_AXIS2APB_LOOKUP_STS_RDY_SHIFT (0U)
1471 #define TSW_AXIS2APB_LOOKUP_STS_RDY_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_STS_RDY_MASK) >> TSW_AXIS2APB_LOOKUP_STS_RDY_SHIFT)
1472 
1473 /* Bitfield definition for register: AXIS2APB_LOOKUP_RESP_CNT */
1474 /*
1475  * RDCNT (RO)
1476  *
1477  * number of streams in queue
1478  */
1479 #define TSW_AXIS2APB_LOOKUP_RESP_CNT_RDCNT_MASK (0xFFU)
1480 #define TSW_AXIS2APB_LOOKUP_RESP_CNT_RDCNT_SHIFT (0U)
1481 #define TSW_AXIS2APB_LOOKUP_RESP_CNT_RDCNT_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESP_CNT_RDCNT_MASK) >> TSW_AXIS2APB_LOOKUP_RESP_CNT_RDCNT_SHIFT)
1482 
1483 /* Bitfield definition for register: AXIS2APB_LOOKUP_FILLSTS */
1484 /*
1485  * FULL (RO)
1486  *
1487  * FD FIFO full
1488  */
1489 #define TSW_AXIS2APB_LOOKUP_FILLSTS_FULL_MASK (0x10U)
1490 #define TSW_AXIS2APB_LOOKUP_FILLSTS_FULL_SHIFT (4U)
1491 #define TSW_AXIS2APB_LOOKUP_FILLSTS_FULL_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_FILLSTS_FULL_MASK) >> TSW_AXIS2APB_LOOKUP_FILLSTS_FULL_SHIFT)
1492 
1493 /*
1494  * EMPTY (RO)
1495  *
1496  * FD FIFO failure
1497  */
1498 #define TSW_AXIS2APB_LOOKUP_FILLSTS_EMPTY_MASK (0x1U)
1499 #define TSW_AXIS2APB_LOOKUP_FILLSTS_EMPTY_SHIFT (0U)
1500 #define TSW_AXIS2APB_LOOKUP_FILLSTS_EMPTY_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_FILLSTS_EMPTY_MASK) >> TSW_AXIS2APB_LOOKUP_FILLSTS_EMPTY_SHIFT)
1501 
1502 /* Bitfield definition for register: AXIS2APB_LOOKUP_RESET */
1503 /*
1504  * RESET (R/W)
1505  *
1506  * Resets controller and clears all pending stream data
1507  */
1508 #define TSW_AXIS2APB_LOOKUP_RESET_RESET_MASK (0x1U)
1509 #define TSW_AXIS2APB_LOOKUP_RESET_RESET_SHIFT (0U)
1510 #define TSW_AXIS2APB_LOOKUP_RESET_RESET_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESET_RESET_SHIFT) & TSW_AXIS2APB_LOOKUP_RESET_RESET_MASK)
1511 #define TSW_AXIS2APB_LOOKUP_RESET_RESET_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESET_RESET_MASK) >> TSW_AXIS2APB_LOOKUP_RESET_RESET_SHIFT)
1512 
1513 /* Bitfield definition for register: AXIS2APB_LOOKUP_PARAM */
1514 /*
1515  * DEPTH (RO)
1516  *
1517  * number of configured buffer depth
1518  */
1519 #define TSW_AXIS2APB_LOOKUP_PARAM_DEPTH_MASK (0xFF00U)
1520 #define TSW_AXIS2APB_LOOKUP_PARAM_DEPTH_SHIFT (8U)
1521 #define TSW_AXIS2APB_LOOKUP_PARAM_DEPTH_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_PARAM_DEPTH_MASK) >> TSW_AXIS2APB_LOOKUP_PARAM_DEPTH_SHIFT)
1522 
1523 /*
1524  * WORDLEN_BYTE (RO)
1525  *
1526  * number of configured 32bit for this controller
1527  */
1528 #define TSW_AXIS2APB_LOOKUP_PARAM_WORDLEN_BYTE_MASK (0xFFU)
1529 #define TSW_AXIS2APB_LOOKUP_PARAM_WORDLEN_BYTE_SHIFT (0U)
1530 #define TSW_AXIS2APB_LOOKUP_PARAM_WORDLEN_BYTE_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_PARAM_WORDLEN_BYTE_MASK) >> TSW_AXIS2APB_LOOKUP_PARAM_WORDLEN_BYTE_SHIFT)
1531 
1532 /* Bitfield definition for register: AXIS2APB_LOOKUP_RESPDATA_0 */
1533 /*
1534  * DROP_VLAN (RW)
1535  *
1536  * Used for statistics. Shows that drop occurs by VLAN-ID
1537  */
1538 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_MASK (0x2000000UL)
1539 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_SHIFT (25U)
1540 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_MASK)
1541 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_SHIFT)
1542 
1543 /*
1544  * HIT (RW)
1545  *
1546  * Is 1, if DESTMAC and VID hit an entry.
1547  */
1548 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_MASK (0x1000000UL)
1549 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_SHIFT (24U)
1550 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_MASK)
1551 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_SHIFT)
1552 
1553 /*
1554  * UTAG (RW)
1555  *
1556  * TSN user sideband information from ALMEM.
1557  */
1558 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_MASK (0xE00000UL)
1559 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_SHIFT (21U)
1560 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_MASK)
1561 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_SHIFT)
1562 
1563 /*
1564  * HIT_VLAN (RW)
1565  *
1566  * Is 1, if VID hit entry in VLAN_PORT table.
1567  */
1568 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_MASK (0x100000UL)
1569 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_SHIFT (20U)
1570 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_MASK)
1571 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_SHIFT)
1572 
1573 /*
1574  * DROP (RW)
1575  *
1576  * Indicate that the frame should be dropped.
1577  */
1578 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_MASK (0x80000UL)
1579 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_SHIFT (19U)
1580 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_MASK)
1581 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_SHIFT)
1582 
1583 /*
1584  * QUEUE (RW)
1585  *
1586  * TX traffic queue selection.
1587  */
1588 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_MASK (0x70000UL)
1589 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_SHIFT (16U)
1590 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_MASK)
1591 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_SHIFT)
1592 
1593 /*
1594  * DEST (RW)
1595  *
1596  * Forwarding ports from 0 to 15, Bit 0 is CPU port.
1597  */
1598 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_MASK (0xFFFFU)
1599 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_SHIFT (0U)
1600 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_MASK)
1601 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_SHIFT)
1602 
1603 /* Bitfield definition for register: AXIS2APB_LOOKUP_RESPDATA_1 */
1604 /*
1605  * ENTRY_NUM (RW)
1606  *
1607  * Entry number of ALMEM.
1608  */
1609 #define TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_MASK (0xFFFFU)
1610 #define TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_SHIFT (0U)
1611 #define TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_MASK)
1612 #define TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_SHIFT)
1613 
1614 /* Bitfield definition for register: CENTRAL_CSR_VERSION */
1615 /*
1616  * VER_HI (RO)
1617  *
1618  * Major Version number of TSN-SW core.
1619  */
1620 #define TSW_CENTRAL_CSR_VERSION_VER_HI_MASK (0xFF000000UL)
1621 #define TSW_CENTRAL_CSR_VERSION_VER_HI_SHIFT (24U)
1622 #define TSW_CENTRAL_CSR_VERSION_VER_HI_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_VERSION_VER_HI_MASK) >> TSW_CENTRAL_CSR_VERSION_VER_HI_SHIFT)
1623 
1624 /*
1625  * VER_LO (RO)
1626  *
1627  * Minor Version number of TSN-SW core.
1628  */
1629 #define TSW_CENTRAL_CSR_VERSION_VER_LO_MASK (0xFF0000UL)
1630 #define TSW_CENTRAL_CSR_VERSION_VER_LO_SHIFT (16U)
1631 #define TSW_CENTRAL_CSR_VERSION_VER_LO_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_VERSION_VER_LO_MASK) >> TSW_CENTRAL_CSR_VERSION_VER_LO_SHIFT)
1632 
1633 /*
1634  * VER_REV (RO)
1635  *
1636  * Reversion number of TSN-SW core.
1637  */
1638 #define TSW_CENTRAL_CSR_VERSION_VER_REV_MASK (0xFFU)
1639 #define TSW_CENTRAL_CSR_VERSION_VER_REV_SHIFT (0U)
1640 #define TSW_CENTRAL_CSR_VERSION_VER_REV_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_VERSION_VER_REV_MASK) >> TSW_CENTRAL_CSR_VERSION_VER_REV_SHIFT)
1641 
1642 /* Bitfield definition for register: CENTRAL_CSR_PARAM */
1643 /*
1644  * INCL_QCI (RO)
1645  *
1646  * Shows if QCI module is present.
1647  */
1648 #define TSW_CENTRAL_CSR_PARAM_INCL_QCI_MASK (0x40000UL)
1649 #define TSW_CENTRAL_CSR_PARAM_INCL_QCI_SHIFT (18U)
1650 #define TSW_CENTRAL_CSR_PARAM_INCL_QCI_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_PARAM_INCL_QCI_MASK) >> TSW_CENTRAL_CSR_PARAM_INCL_QCI_SHIFT)
1651 
1652 /*
1653  * INCL_CB0 (RO)
1654  *
1655  * Shows if IP is configured with “lightweight” 802.1CB at CPU-Port.
1656  */
1657 #define TSW_CENTRAL_CSR_PARAM_INCL_CB0_MASK (0x20000UL)
1658 #define TSW_CENTRAL_CSR_PARAM_INCL_CB0_SHIFT (17U)
1659 #define TSW_CENTRAL_CSR_PARAM_INCL_CB0_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_PARAM_INCL_CB0_MASK) >> TSW_CENTRAL_CSR_PARAM_INCL_CB0_SHIFT)
1660 
1661 /*
1662  * TESTMODE (RO)
1663  *
1664  * Shows if IP is configured in TESTMODE.
1665  */
1666 #define TSW_CENTRAL_CSR_PARAM_TESTMODE_MASK (0x10000UL)
1667 #define TSW_CENTRAL_CSR_PARAM_TESTMODE_SHIFT (16U)
1668 #define TSW_CENTRAL_CSR_PARAM_TESTMODE_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_PARAM_TESTMODE_MASK) >> TSW_CENTRAL_CSR_PARAM_TESTMODE_SHIFT)
1669 
1670 /*
1671  * TYPE (RO)
1672  *
1673  * Specify type of switch core
1674  */
1675 #define TSW_CENTRAL_CSR_PARAM_TYPE_MASK (0xFF00U)
1676 #define TSW_CENTRAL_CSR_PARAM_TYPE_SHIFT (8U)
1677 #define TSW_CENTRAL_CSR_PARAM_TYPE_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_PARAM_TYPE_MASK) >> TSW_CENTRAL_CSR_PARAM_TYPE_SHIFT)
1678 
1679 /*
1680  * NPORTS (RO)
1681  *
1682  * Number of TSN ports without counting internal CPU port. For TSN-SE, it returns always 2
1683  */
1684 #define TSW_CENTRAL_CSR_PARAM_NPORTS_MASK (0xFFU)
1685 #define TSW_CENTRAL_CSR_PARAM_NPORTS_SHIFT (0U)
1686 #define TSW_CENTRAL_CSR_PARAM_NPORTS_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_PARAM_NPORTS_MASK) >> TSW_CENTRAL_CSR_PARAM_NPORTS_SHIFT)
1687 
1688 /* Bitfield definition for register: CENTRAL_CSR_CONFIG */
1689 /*
1690  * MSEC_CYCLES (R/W)
1691  *
1692  * Number of SYS_CLK cycles during 1 ms. It is required to calculate a correct time
1693  */
1694 #define TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_MASK (0xFFFFFFUL)
1695 #define TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_SHIFT (0U)
1696 #define TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_SET(x) (((uint32_t)(x) << TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_SHIFT) & TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_MASK)
1697 #define TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_MASK) >> TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_SHIFT)
1698 
1699 /* Bitfield definition for register: CENTRAL_CSR_CB_PARAM */
1700 /*
1701  * SID_D (RO)
1702  *
1703  * Number of 802.1CB Stream Identification entries. 2^SID_D entries
1704  */
1705 #define TSW_CENTRAL_CSR_CB_PARAM_SID_D_MASK (0xFF00U)
1706 #define TSW_CENTRAL_CSR_CB_PARAM_SID_D_SHIFT (8U)
1707 #define TSW_CENTRAL_CSR_CB_PARAM_SID_D_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_CB_PARAM_SID_D_MASK) >> TSW_CENTRAL_CSR_CB_PARAM_SID_D_SHIFT)
1708 
1709 /*
1710  * FRER_D (RO)
1711  *
1712  * Number of 802.1CB Recovery Function entries. 2^FRER_D entries.
1713  */
1714 #define TSW_CENTRAL_CSR_CB_PARAM_FRER_D_MASK (0xFFU)
1715 #define TSW_CENTRAL_CSR_CB_PARAM_FRER_D_SHIFT (0U)
1716 #define TSW_CENTRAL_CSR_CB_PARAM_FRER_D_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_CB_PARAM_FRER_D_MASK) >> TSW_CENTRAL_CSR_CB_PARAM_FRER_D_SHIFT)
1717 
1718 /* Bitfield definition for register: CENTRAL_CSR_QCI_CTRL_PARAM */
1719 /*
1720  * QCI_GTD (RO)
1721  *
1722  * (Log) gate table depth. 2**GTD entries.
1723  */
1724 #define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_GTD_MASK (0xFF0000UL)
1725 #define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_GTD_SHIFT (16U)
1726 #define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_GTD_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_GTD_MASK) >> TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_GTD_SHIFT)
1727 
1728 /*
1729  * QCI_FMD (RO)
1730  *
1731  * (Log) flow meter depth. 2**FMD entries.
1732  */
1733 #define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FMD_MASK (0xFF00U)
1734 #define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FMD_SHIFT (8U)
1735 #define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FMD_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FMD_MASK) >> TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FMD_SHIFT)
1736 
1737 /*
1738  * QCI_FTD (RO)
1739  *
1740  * (Log) filter table depth. 2**FTD entries.
1741  */
1742 #define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FTD_MASK (0xFFU)
1743 #define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FTD_SHIFT (0U)
1744 #define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FTD_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FTD_MASK) >> TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FTD_SHIFT)
1745 
1746 /* Bitfield definition for register: CENTRAL_QCI_HWCFG */
1747 /*
1748  * FMD (RO)
1749  *
1750  * FMD – parameter
1751  */
1752 #define TSW_CENTRAL_QCI_HWCFG_FMD_MASK (0xFF0000UL)
1753 #define TSW_CENTRAL_QCI_HWCFG_FMD_SHIFT (16U)
1754 #define TSW_CENTRAL_QCI_HWCFG_FMD_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_HWCFG_FMD_MASK) >> TSW_CENTRAL_QCI_HWCFG_FMD_SHIFT)
1755 
1756 /*
1757  * GTD (RO)
1758  *
1759  * GTD – parameter
1760  */
1761 #define TSW_CENTRAL_QCI_HWCFG_GTD_MASK (0xFF00U)
1762 #define TSW_CENTRAL_QCI_HWCFG_GTD_SHIFT (8U)
1763 #define TSW_CENTRAL_QCI_HWCFG_GTD_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_HWCFG_GTD_MASK) >> TSW_CENTRAL_QCI_HWCFG_GTD_SHIFT)
1764 
1765 /*
1766  * FTD (RO)
1767  *
1768  * FTD – parameter
1769  */
1770 #define TSW_CENTRAL_QCI_HWCFG_FTD_MASK (0xFFU)
1771 #define TSW_CENTRAL_QCI_HWCFG_FTD_SHIFT (0U)
1772 #define TSW_CENTRAL_QCI_HWCFG_FTD_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_HWCFG_FTD_MASK) >> TSW_CENTRAL_QCI_HWCFG_FTD_SHIFT)
1773 
1774 /* Bitfield definition for register: CENTRAL_QCI_FILTERSEL */
1775 /*
1776  * INDEX (R/W)
1777  *
1778  * Filter select index
1779  * Any written value larger than the maximum index
1780  * (2**FTD-1) will result in a read-back value of <0>.
1781  */
1782 #define TSW_CENTRAL_QCI_FILTERSEL_INDEX_MASK (0xFFU)
1783 #define TSW_CENTRAL_QCI_FILTERSEL_INDEX_SHIFT (0U)
1784 #define TSW_CENTRAL_QCI_FILTERSEL_INDEX_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_FILTERSEL_INDEX_SHIFT) & TSW_CENTRAL_QCI_FILTERSEL_INDEX_MASK)
1785 #define TSW_CENTRAL_QCI_FILTERSEL_INDEX_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_FILTERSEL_INDEX_MASK) >> TSW_CENTRAL_QCI_FILTERSEL_INDEX_SHIFT)
1786 
1787 /* Bitfield definition for register: CENTRAL_QCI_METERSEL */
1788 /*
1789  * INDEX (R/W)
1790  *
1791  * Flowmeter select index
1792  * Any written value larger than the maximum index
1793  * (2**FMD-1) will result in a read-back value of <0>.
1794  */
1795 #define TSW_CENTRAL_QCI_METERSEL_INDEX_MASK (0xFFU)
1796 #define TSW_CENTRAL_QCI_METERSEL_INDEX_SHIFT (0U)
1797 #define TSW_CENTRAL_QCI_METERSEL_INDEX_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_METERSEL_INDEX_SHIFT) & TSW_CENTRAL_QCI_METERSEL_INDEX_MASK)
1798 #define TSW_CENTRAL_QCI_METERSEL_INDEX_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_METERSEL_INDEX_MASK) >> TSW_CENTRAL_QCI_METERSEL_INDEX_SHIFT)
1799 
1800 /* Bitfield definition for register: CENTRAL_QCI_GATESEL */
1801 /*
1802  * INDEX (R/W)
1803  *
1804  * Gate select index
1805  * Any written value larger than the maximum index
1806  * (2**GTD-1) will result in a read-back value of <0>.
1807  */
1808 #define TSW_CENTRAL_QCI_GATESEL_INDEX_MASK (0xFFU)
1809 #define TSW_CENTRAL_QCI_GATESEL_INDEX_SHIFT (0U)
1810 #define TSW_CENTRAL_QCI_GATESEL_INDEX_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_GATESEL_INDEX_SHIFT) & TSW_CENTRAL_QCI_GATESEL_INDEX_MASK)
1811 #define TSW_CENTRAL_QCI_GATESEL_INDEX_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GATESEL_INDEX_MASK) >> TSW_CENTRAL_QCI_GATESEL_INDEX_SHIFT)
1812 
1813 /* Bitfield definition for register: CENTRAL_QCI_FCTRL */
1814 /*
1815  * ENBLK (R/W)
1816  *
1817  * Enable blocking of oversized frames
1818  * (802.1Qci – 8.6.5.1.1 (g))
1819  */
1820 #define TSW_CENTRAL_QCI_FCTRL_ENBLK_MASK (0x80000000UL)
1821 #define TSW_CENTRAL_QCI_FCTRL_ENBLK_SHIFT (31U)
1822 #define TSW_CENTRAL_QCI_FCTRL_ENBLK_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_ENBLK_SHIFT) & TSW_CENTRAL_QCI_FCTRL_ENBLK_MASK)
1823 #define TSW_CENTRAL_QCI_FCTRL_ENBLK_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_ENBLK_MASK) >> TSW_CENTRAL_QCI_FCTRL_ENBLK_SHIFT)
1824 
1825 /*
1826  * ENFSZ (R/W)
1827  *
1828  * 0: No frame size check
1829  * 1: Frame size checking, size defined by FSIZE.MXSZ
1830  * (802.1Qci – 8.6.5.1.1 (e.1))
1831  */
1832 #define TSW_CENTRAL_QCI_FCTRL_ENFSZ_MASK (0x40000000UL)
1833 #define TSW_CENTRAL_QCI_FCTRL_ENFSZ_SHIFT (30U)
1834 #define TSW_CENTRAL_QCI_FCTRL_ENFSZ_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_ENFSZ_SHIFT) & TSW_CENTRAL_QCI_FCTRL_ENFSZ_MASK)
1835 #define TSW_CENTRAL_QCI_FCTRL_ENFSZ_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_ENFSZ_MASK) >> TSW_CENTRAL_QCI_FCTRL_ENFSZ_SHIFT)
1836 
1837 /*
1838  * ENFID (R/W)
1839  *
1840  * 0: No Flow Meter
1841  * 1: Enable Flow Metering
1842  * (802.1Qci – 8.6.5.1.1 (e.2))
1843  */
1844 #define TSW_CENTRAL_QCI_FCTRL_ENFID_MASK (0x20000000UL)
1845 #define TSW_CENTRAL_QCI_FCTRL_ENFID_SHIFT (29U)
1846 #define TSW_CENTRAL_QCI_FCTRL_ENFID_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_ENFID_SHIFT) & TSW_CENTRAL_QCI_FCTRL_ENFID_MASK)
1847 #define TSW_CENTRAL_QCI_FCTRL_ENFID_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_ENFID_MASK) >> TSW_CENTRAL_QCI_FCTRL_ENFID_SHIFT)
1848 
1849 /*
1850  * ENSID (R/W)
1851  *
1852  * 0: Filter match any SID value
1853  * 1: Filter match SID value
1854  * (802.1Qci – 8.6.5.1.1 (b))
1855  */
1856 #define TSW_CENTRAL_QCI_FCTRL_ENSID_MASK (0x10000000UL)
1857 #define TSW_CENTRAL_QCI_FCTRL_ENSID_SHIFT (28U)
1858 #define TSW_CENTRAL_QCI_FCTRL_ENSID_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_ENSID_SHIFT) & TSW_CENTRAL_QCI_FCTRL_ENSID_MASK)
1859 #define TSW_CENTRAL_QCI_FCTRL_ENSID_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_ENSID_MASK) >> TSW_CENTRAL_QCI_FCTRL_ENSID_SHIFT)
1860 
1861 /*
1862  * ENPCP (R/W)
1863  *
1864  * 0: Filter match any PCP value
1865  * 1: Filter match PCP value
1866  * (802.1Qci – 8.6.5.1.1 (c))
1867  */
1868 #define TSW_CENTRAL_QCI_FCTRL_ENPCP_MASK (0x8000000UL)
1869 #define TSW_CENTRAL_QCI_FCTRL_ENPCP_SHIFT (27U)
1870 #define TSW_CENTRAL_QCI_FCTRL_ENPCP_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_ENPCP_SHIFT) & TSW_CENTRAL_QCI_FCTRL_ENPCP_MASK)
1871 #define TSW_CENTRAL_QCI_FCTRL_ENPCP_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_ENPCP_MASK) >> TSW_CENTRAL_QCI_FCTRL_ENPCP_SHIFT)
1872 
1873 /*
1874  * PCP (R/W)
1875  *
1876  * Filter priority code point, if enabled by ENPCP
1877  */
1878 #define TSW_CENTRAL_QCI_FCTRL_PCP_MASK (0x7000000UL)
1879 #define TSW_CENTRAL_QCI_FCTRL_PCP_SHIFT (24U)
1880 #define TSW_CENTRAL_QCI_FCTRL_PCP_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_PCP_SHIFT) & TSW_CENTRAL_QCI_FCTRL_PCP_MASK)
1881 #define TSW_CENTRAL_QCI_FCTRL_PCP_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_PCP_MASK) >> TSW_CENTRAL_QCI_FCTRL_PCP_SHIFT)
1882 
1883 /*
1884  * FMD (R/W)
1885  *
1886  * Associated Flow Meter – if enabled by ENFID
1887  */
1888 #define TSW_CENTRAL_QCI_FCTRL_FMD_MASK (0xFF0000UL)
1889 #define TSW_CENTRAL_QCI_FCTRL_FMD_SHIFT (16U)
1890 #define TSW_CENTRAL_QCI_FCTRL_FMD_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_FMD_SHIFT) & TSW_CENTRAL_QCI_FCTRL_FMD_MASK)
1891 #define TSW_CENTRAL_QCI_FCTRL_FMD_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_FMD_MASK) >> TSW_CENTRAL_QCI_FCTRL_FMD_SHIFT)
1892 
1893 /*
1894  * GID (R/W)
1895  *
1896  * Associated Gate
1897  */
1898 #define TSW_CENTRAL_QCI_FCTRL_GID_MASK (0xFF00U)
1899 #define TSW_CENTRAL_QCI_FCTRL_GID_SHIFT (8U)
1900 #define TSW_CENTRAL_QCI_FCTRL_GID_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_GID_SHIFT) & TSW_CENTRAL_QCI_FCTRL_GID_MASK)
1901 #define TSW_CENTRAL_QCI_FCTRL_GID_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_GID_MASK) >> TSW_CENTRAL_QCI_FCTRL_GID_SHIFT)
1902 
1903 /*
1904  * SID (R/W)
1905  *
1906  * Filter Stream ID – if enabled by ENSID
1907  */
1908 #define TSW_CENTRAL_QCI_FCTRL_SID_MASK (0xFFU)
1909 #define TSW_CENTRAL_QCI_FCTRL_SID_SHIFT (0U)
1910 #define TSW_CENTRAL_QCI_FCTRL_SID_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_SID_SHIFT) & TSW_CENTRAL_QCI_FCTRL_SID_MASK)
1911 #define TSW_CENTRAL_QCI_FCTRL_SID_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_SID_MASK) >> TSW_CENTRAL_QCI_FCTRL_SID_SHIFT)
1912 
1913 /* Bitfield definition for register: CENTRAL_QCI_FSIZE */
1914 /*
1915  * BLK (R/WC)
1916  *
1917  * Stream blocked due to oversize frame.
1918  * Write <1> to clear.
1919  * (802.1Qci – 8.6.5.1.1 (h))
1920  */
1921 #define TSW_CENTRAL_QCI_FSIZE_BLK_MASK (0x80000000UL)
1922 #define TSW_CENTRAL_QCI_FSIZE_BLK_SHIFT (31U)
1923 #define TSW_CENTRAL_QCI_FSIZE_BLK_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_FSIZE_BLK_SHIFT) & TSW_CENTRAL_QCI_FSIZE_BLK_MASK)
1924 #define TSW_CENTRAL_QCI_FSIZE_BLK_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_FSIZE_BLK_MASK) >> TSW_CENTRAL_QCI_FSIZE_BLK_SHIFT)
1925 
1926 /*
1927  * MXSZ (R/W)
1928  *
1929  * Maximum-SDU size in octets
1930  */
1931 #define TSW_CENTRAL_QCI_FSIZE_MXSZ_MASK (0xFFFFU)
1932 #define TSW_CENTRAL_QCI_FSIZE_MXSZ_SHIFT (0U)
1933 #define TSW_CENTRAL_QCI_FSIZE_MXSZ_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_FSIZE_MXSZ_SHIFT) & TSW_CENTRAL_QCI_FSIZE_MXSZ_MASK)
1934 #define TSW_CENTRAL_QCI_FSIZE_MXSZ_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_FSIZE_MXSZ_MASK) >> TSW_CENTRAL_QCI_FSIZE_MXSZ_SHIFT)
1935 
1936 /* Bitfield definition for register array: QCI_CNT */
1937 /*
1938  * VALUE (RO)
1939  *
1940  * Filter counter (see 802.1Qci 8.6.5.1.1 f)
1941  * CNT0: Frames that matched filter
1942  * CNT1: Frames that passed gate
1943  * CNT2: Frames that did not pass gate
1944  * CNT3: Frames that passed Maximum-SDU size check
1945  * CNT4: Frames that did not pass size check
1946  * CNT5: Frames discarded by Flow Meter operation
1947  * Counters starting at value <0> after reset.
1948  */
1949 #define TSW_QCI_CNT_VALUE_MASK (0xFFFFFFFFUL)
1950 #define TSW_QCI_CNT_VALUE_SHIFT (0U)
1951 #define TSW_QCI_CNT_VALUE_GET(x) (((uint32_t)(x) & TSW_QCI_CNT_VALUE_MASK) >> TSW_QCI_CNT_VALUE_SHIFT)
1952 
1953 /* Bitfield definition for register: CENTRAL_QCI_MCTRL */
1954 /*
1955  * RESET (WO)
1956  *
1957  * Flow Meter reset – self-resetting to <0>
1958  */
1959 #define TSW_CENTRAL_QCI_MCTRL_RESET_MASK (0x80000000UL)
1960 #define TSW_CENTRAL_QCI_MCTRL_RESET_SHIFT (31U)
1961 #define TSW_CENTRAL_QCI_MCTRL_RESET_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_MCTRL_RESET_SHIFT) & TSW_CENTRAL_QCI_MCTRL_RESET_MASK)
1962 #define TSW_CENTRAL_QCI_MCTRL_RESET_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_MCTRL_RESET_MASK) >> TSW_CENTRAL_QCI_MCTRL_RESET_SHIFT)
1963 
1964 /*
1965  * MAFR (RO)
1966  *
1967  * MarkAllFramesRed – cleared by RESET
1968  * (802.1Qci – 8.6.5.1.3 (j))
1969  */
1970 #define TSW_CENTRAL_QCI_MCTRL_MAFR_MASK (0x10U)
1971 #define TSW_CENTRAL_QCI_MCTRL_MAFR_SHIFT (4U)
1972 #define TSW_CENTRAL_QCI_MCTRL_MAFR_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_MCTRL_MAFR_MASK) >> TSW_CENTRAL_QCI_MCTRL_MAFR_SHIFT)
1973 
1974 /*
1975  * MAFREN (R/W)
1976  *
1977  * MarkAllFramesRedEnable
1978  * (802.1Qci – 8.6.5.1.3 (i))
1979  */
1980 #define TSW_CENTRAL_QCI_MCTRL_MAFREN_MASK (0x8U)
1981 #define TSW_CENTRAL_QCI_MCTRL_MAFREN_SHIFT (3U)
1982 #define TSW_CENTRAL_QCI_MCTRL_MAFREN_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_MCTRL_MAFREN_SHIFT) & TSW_CENTRAL_QCI_MCTRL_MAFREN_MASK)
1983 #define TSW_CENTRAL_QCI_MCTRL_MAFREN_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_MCTRL_MAFREN_MASK) >> TSW_CENTRAL_QCI_MCTRL_MAFREN_SHIFT)
1984 
1985 /*
1986  * DOY (R/W)
1987  *
1988  * DropOnYellow
1989  * (802.1Qci – 8.6.5.1.3 (h))
1990  */
1991 #define TSW_CENTRAL_QCI_MCTRL_DOY_MASK (0x4U)
1992 #define TSW_CENTRAL_QCI_MCTRL_DOY_SHIFT (2U)
1993 #define TSW_CENTRAL_QCI_MCTRL_DOY_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_MCTRL_DOY_SHIFT) & TSW_CENTRAL_QCI_MCTRL_DOY_MASK)
1994 #define TSW_CENTRAL_QCI_MCTRL_DOY_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_MCTRL_DOY_MASK) >> TSW_CENTRAL_QCI_MCTRL_DOY_SHIFT)
1995 
1996 /*
1997  * CM (R/W)
1998  *
1999  * Color mode – functionally unused
2000  * (802.1Qci – 8.6.5.1.3 (g))
2001  */
2002 #define TSW_CENTRAL_QCI_MCTRL_CM_MASK (0x2U)
2003 #define TSW_CENTRAL_QCI_MCTRL_CM_SHIFT (1U)
2004 #define TSW_CENTRAL_QCI_MCTRL_CM_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_MCTRL_CM_SHIFT) & TSW_CENTRAL_QCI_MCTRL_CM_MASK)
2005 #define TSW_CENTRAL_QCI_MCTRL_CM_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_MCTRL_CM_MASK) >> TSW_CENTRAL_QCI_MCTRL_CM_SHIFT)
2006 
2007 /*
2008  * CF (R/W)
2009  *
2010  * Coupling flag
2011  * (802.1Qci – 8.6.5.1.3 (f))
2012  */
2013 #define TSW_CENTRAL_QCI_MCTRL_CF_MASK (0x1U)
2014 #define TSW_CENTRAL_QCI_MCTRL_CF_SHIFT (0U)
2015 #define TSW_CENTRAL_QCI_MCTRL_CF_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_MCTRL_CF_SHIFT) & TSW_CENTRAL_QCI_MCTRL_CF_MASK)
2016 #define TSW_CENTRAL_QCI_MCTRL_CF_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_MCTRL_CF_MASK) >> TSW_CENTRAL_QCI_MCTRL_CF_SHIFT)
2017 
2018 /* Bitfield definition for register: CENTRAL_QCI_CIR */
2019 /*
2020  * CIR (R/W)
2021  *
2022  * Committed information rate – see Chapter 7.5.2.4.
2023  * (802.1Qci – 8.6.5.1.3 (b))
2024  */
2025 #define TSW_CENTRAL_QCI_CIR_CIR_MASK (0xFFFFFFUL)
2026 #define TSW_CENTRAL_QCI_CIR_CIR_SHIFT (0U)
2027 #define TSW_CENTRAL_QCI_CIR_CIR_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_CIR_CIR_SHIFT) & TSW_CENTRAL_QCI_CIR_CIR_MASK)
2028 #define TSW_CENTRAL_QCI_CIR_CIR_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_CIR_CIR_MASK) >> TSW_CENTRAL_QCI_CIR_CIR_SHIFT)
2029 
2030 /* Bitfield definition for register: CENTRAL_QCI_CBS */
2031 /*
2032  * CBS (R/W)
2033  *
2034  * Committed burst size, in bits (not octets!)
2035  * (802.1Qci – 8.6.5.1.3 (c))
2036  */
2037 #define TSW_CENTRAL_QCI_CBS_CBS_MASK (0xFFFFFFFFUL)
2038 #define TSW_CENTRAL_QCI_CBS_CBS_SHIFT (0U)
2039 #define TSW_CENTRAL_QCI_CBS_CBS_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_CBS_CBS_SHIFT) & TSW_CENTRAL_QCI_CBS_CBS_MASK)
2040 #define TSW_CENTRAL_QCI_CBS_CBS_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_CBS_CBS_MASK) >> TSW_CENTRAL_QCI_CBS_CBS_SHIFT)
2041 
2042 /* Bitfield definition for register: CENTRAL_QCI_EIR */
2043 /*
2044  * EIR (R/W)
2045  *
2046  * Excess information rate – see Chapter 7.5.2.4.
2047  * (802.1Qci – 8.6.5.1.3 (d))
2048  */
2049 #define TSW_CENTRAL_QCI_EIR_EIR_MASK (0xFFFFFFUL)
2050 #define TSW_CENTRAL_QCI_EIR_EIR_SHIFT (0U)
2051 #define TSW_CENTRAL_QCI_EIR_EIR_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_EIR_EIR_SHIFT) & TSW_CENTRAL_QCI_EIR_EIR_MASK)
2052 #define TSW_CENTRAL_QCI_EIR_EIR_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_EIR_EIR_MASK) >> TSW_CENTRAL_QCI_EIR_EIR_SHIFT)
2053 
2054 /* Bitfield definition for register: CENTRAL_QCI_EBS */
2055 /*
2056  * EBS (R/W)
2057  *
2058  * Excess burst size, in bits (not octets)
2059  * (802.1Qci – 8.6.5.1.3 (e))
2060  */
2061 #define TSW_CENTRAL_QCI_EBS_EBS_MASK (0xFFFFFFFFUL)
2062 #define TSW_CENTRAL_QCI_EBS_EBS_SHIFT (0U)
2063 #define TSW_CENTRAL_QCI_EBS_EBS_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_EBS_EBS_SHIFT) & TSW_CENTRAL_QCI_EBS_EBS_MASK)
2064 #define TSW_CENTRAL_QCI_EBS_EBS_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_EBS_EBS_MASK) >> TSW_CENTRAL_QCI_EBS_EBS_SHIFT)
2065 
2066 /* Bitfield definition for register: CENTRAL_QCI_GCTRL */
2067 /*
2068  * IPV (R/W)
2069  *
2070  * Administrative internal priority value specification
2071  * (802.1Qci – 8.6.5.1.2 (c))
2072  */
2073 #define TSW_CENTRAL_QCI_GCTRL_IPV_MASK (0xE0U)
2074 #define TSW_CENTRAL_QCI_GCTRL_IPV_SHIFT (5U)
2075 #define TSW_CENTRAL_QCI_GCTRL_IPV_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_GCTRL_IPV_SHIFT) & TSW_CENTRAL_QCI_GCTRL_IPV_MASK)
2076 #define TSW_CENTRAL_QCI_GCTRL_IPV_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GCTRL_IPV_MASK) >> TSW_CENTRAL_QCI_GCTRL_IPV_SHIFT)
2077 
2078 /*
2079  * STATE (R/W)
2080  *
2081  * Administrative stream gate state
2082  * (802.1Qci – 8.6.5.1.2 (b))
2083  */
2084 #define TSW_CENTRAL_QCI_GCTRL_STATE_MASK (0x10U)
2085 #define TSW_CENTRAL_QCI_GCTRL_STATE_SHIFT (4U)
2086 #define TSW_CENTRAL_QCI_GCTRL_STATE_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_GCTRL_STATE_SHIFT) & TSW_CENTRAL_QCI_GCTRL_STATE_MASK)
2087 #define TSW_CENTRAL_QCI_GCTRL_STATE_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GCTRL_STATE_MASK) >> TSW_CENTRAL_QCI_GCTRL_STATE_SHIFT)
2088 
2089 /*
2090  * CDOEE (R/W)
2091  *
2092  * Gate – ClosedDueToOctetsExceededEnable
2093  * (802.1Qci – 8.6.5.1.2 (f))
2094  */
2095 #define TSW_CENTRAL_QCI_GCTRL_CDOEE_MASK (0x8U)
2096 #define TSW_CENTRAL_QCI_GCTRL_CDOEE_SHIFT (3U)
2097 #define TSW_CENTRAL_QCI_GCTRL_CDOEE_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_GCTRL_CDOEE_SHIFT) & TSW_CENTRAL_QCI_GCTRL_CDOEE_MASK)
2098 #define TSW_CENTRAL_QCI_GCTRL_CDOEE_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GCTRL_CDOEE_MASK) >> TSW_CENTRAL_QCI_GCTRL_CDOEE_SHIFT)
2099 
2100 /*
2101  * CDIRE (R/W)
2102  *
2103  * Gate – ClosedDueToInvalidRxEnable
2104  * (802.1Qci – 8.6.5.1.2 (d))
2105  */
2106 #define TSW_CENTRAL_QCI_GCTRL_CDIRE_MASK (0x4U)
2107 #define TSW_CENTRAL_QCI_GCTRL_CDIRE_SHIFT (2U)
2108 #define TSW_CENTRAL_QCI_GCTRL_CDIRE_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_GCTRL_CDIRE_SHIFT) & TSW_CENTRAL_QCI_GCTRL_CDIRE_MASK)
2109 #define TSW_CENTRAL_QCI_GCTRL_CDIRE_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GCTRL_CDIRE_MASK) >> TSW_CENTRAL_QCI_GCTRL_CDIRE_SHIFT)
2110 
2111 /*
2112  * CFGCH (R/W)
2113  *
2114  * Gate – change config (self-resetting to <0>)
2115  */
2116 #define TSW_CENTRAL_QCI_GCTRL_CFGCH_MASK (0x2U)
2117 #define TSW_CENTRAL_QCI_GCTRL_CFGCH_SHIFT (1U)
2118 #define TSW_CENTRAL_QCI_GCTRL_CFGCH_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_GCTRL_CFGCH_SHIFT) & TSW_CENTRAL_QCI_GCTRL_CFGCH_MASK)
2119 #define TSW_CENTRAL_QCI_GCTRL_CFGCH_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GCTRL_CFGCH_MASK) >> TSW_CENTRAL_QCI_GCTRL_CFGCH_SHIFT)
2120 
2121 /*
2122  * EN (R/W)
2123  *
2124  * Gate control – enable
2125  */
2126 #define TSW_CENTRAL_QCI_GCTRL_EN_MASK (0x1U)
2127 #define TSW_CENTRAL_QCI_GCTRL_EN_SHIFT (0U)
2128 #define TSW_CENTRAL_QCI_GCTRL_EN_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_GCTRL_EN_SHIFT) & TSW_CENTRAL_QCI_GCTRL_EN_MASK)
2129 #define TSW_CENTRAL_QCI_GCTRL_EN_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GCTRL_EN_MASK) >> TSW_CENTRAL_QCI_GCTRL_EN_SHIFT)
2130 
2131 /* Bitfield definition for register: CENTRAL_QCI_GSTATUS */
2132 /*
2133  * IPV (RO)
2134  *
2135  * Operational internal priority value specification
2136  * (802.1Qci – 8.6.5.1.2 (c))
2137  */
2138 #define TSW_CENTRAL_QCI_GSTATUS_IPV_MASK (0xE0U)
2139 #define TSW_CENTRAL_QCI_GSTATUS_IPV_SHIFT (5U)
2140 #define TSW_CENTRAL_QCI_GSTATUS_IPV_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GSTATUS_IPV_MASK) >> TSW_CENTRAL_QCI_GSTATUS_IPV_SHIFT)
2141 
2142 /*
2143  * STATE (RO)
2144  *
2145  * Operational stream gate state
2146  * (802.1Qci – 8.6.5.1.2 (b))
2147  */
2148 #define TSW_CENTRAL_QCI_GSTATUS_STATE_MASK (0x10U)
2149 #define TSW_CENTRAL_QCI_GSTATUS_STATE_SHIFT (4U)
2150 #define TSW_CENTRAL_QCI_GSTATUS_STATE_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GSTATUS_STATE_MASK) >> TSW_CENTRAL_QCI_GSTATUS_STATE_SHIFT)
2151 
2152 /*
2153  * CDOE (WC)
2154  *
2155  * Gate – ClosedDueToOctetsExceeded. Write <1> to
2156  * clear.
2157  * (802.1Qci – 8.6.5.1.2 (g))
2158  */
2159 #define TSW_CENTRAL_QCI_GSTATUS_CDOE_MASK (0x8U)
2160 #define TSW_CENTRAL_QCI_GSTATUS_CDOE_SHIFT (3U)
2161 #define TSW_CENTRAL_QCI_GSTATUS_CDOE_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_GSTATUS_CDOE_SHIFT) & TSW_CENTRAL_QCI_GSTATUS_CDOE_MASK)
2162 #define TSW_CENTRAL_QCI_GSTATUS_CDOE_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GSTATUS_CDOE_MASK) >> TSW_CENTRAL_QCI_GSTATUS_CDOE_SHIFT)
2163 
2164 /*
2165  * CDIR (WC)
2166  *
2167  * Gate – ClosedDueToInvalidRx. Write <1> to clear.
2168  * (802.1Qci – 8.6.5.1.2 (e))
2169  */
2170 #define TSW_CENTRAL_QCI_GSTATUS_CDIR_MASK (0x4U)
2171 #define TSW_CENTRAL_QCI_GSTATUS_CDIR_SHIFT (2U)
2172 #define TSW_CENTRAL_QCI_GSTATUS_CDIR_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_GSTATUS_CDIR_SHIFT) & TSW_CENTRAL_QCI_GSTATUS_CDIR_MASK)
2173 #define TSW_CENTRAL_QCI_GSTATUS_CDIR_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GSTATUS_CDIR_MASK) >> TSW_CENTRAL_QCI_GSTATUS_CDIR_SHIFT)
2174 
2175 /*
2176  * CFGP (RO)
2177  *
2178  * Configuration change pending
2179  */
2180 #define TSW_CENTRAL_QCI_GSTATUS_CFGP_MASK (0x2U)
2181 #define TSW_CENTRAL_QCI_GSTATUS_CFGP_SHIFT (1U)
2182 #define TSW_CENTRAL_QCI_GSTATUS_CFGP_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GSTATUS_CFGP_MASK) >> TSW_CENTRAL_QCI_GSTATUS_CFGP_SHIFT)
2183 
2184 /*
2185  * CFGERR (WC)
2186  *
2187  * Configuration change error. Write <1> to clear.
2188  */
2189 #define TSW_CENTRAL_QCI_GSTATUS_CFGERR_MASK (0x1U)
2190 #define TSW_CENTRAL_QCI_GSTATUS_CFGERR_SHIFT (0U)
2191 #define TSW_CENTRAL_QCI_GSTATUS_CFGERR_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_GSTATUS_CFGERR_SHIFT) & TSW_CENTRAL_QCI_GSTATUS_CFGERR_MASK)
2192 #define TSW_CENTRAL_QCI_GSTATUS_CFGERR_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GSTATUS_CFGERR_MASK) >> TSW_CENTRAL_QCI_GSTATUS_CFGERR_SHIFT)
2193 
2194 /* Bitfield definition for register: CENTRAL_QCI_GLISTINDEX */
2195 /*
2196  * IDX (R/W)
2197  *
2198  * Admin list pointer, select entry 0 – 15.
2199  */
2200 #define TSW_CENTRAL_QCI_GLISTINDEX_IDX_MASK (0xFU)
2201 #define TSW_CENTRAL_QCI_GLISTINDEX_IDX_SHIFT (0U)
2202 #define TSW_CENTRAL_QCI_GLISTINDEX_IDX_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_GLISTINDEX_IDX_SHIFT) & TSW_CENTRAL_QCI_GLISTINDEX_IDX_MASK)
2203 #define TSW_CENTRAL_QCI_GLISTINDEX_IDX_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GLISTINDEX_IDX_MASK) >> TSW_CENTRAL_QCI_GLISTINDEX_IDX_SHIFT)
2204 
2205 /* Bitfield definition for register: CENTRAL_QCI_LISTLEN */
2206 /*
2207  * OLEN (RO)
2208  *
2209  * Operational list length
2210  */
2211 #define TSW_CENTRAL_QCI_LISTLEN_OLEN_MASK (0xF0000UL)
2212 #define TSW_CENTRAL_QCI_LISTLEN_OLEN_SHIFT (16U)
2213 #define TSW_CENTRAL_QCI_LISTLEN_OLEN_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_LISTLEN_OLEN_MASK) >> TSW_CENTRAL_QCI_LISTLEN_OLEN_SHIFT)
2214 
2215 /*
2216  * ALEN (R/W)
2217  *
2218  * Administrative list length
2219  */
2220 #define TSW_CENTRAL_QCI_LISTLEN_ALEN_MASK (0xFU)
2221 #define TSW_CENTRAL_QCI_LISTLEN_ALEN_SHIFT (0U)
2222 #define TSW_CENTRAL_QCI_LISTLEN_ALEN_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_LISTLEN_ALEN_SHIFT) & TSW_CENTRAL_QCI_LISTLEN_ALEN_MASK)
2223 #define TSW_CENTRAL_QCI_LISTLEN_ALEN_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_LISTLEN_ALEN_MASK) >> TSW_CENTRAL_QCI_LISTLEN_ALEN_SHIFT)
2224 
2225 /* Bitfield definition for register: CENTRAL_QCI_ACYCLETM */
2226 /*
2227  * ACT (R/W)
2228  *
2229  * Administrative cycle time length, nanoseconds.
2230  */
2231 #define TSW_CENTRAL_QCI_ACYCLETM_ACT_MASK (0x3FFFFFFFUL)
2232 #define TSW_CENTRAL_QCI_ACYCLETM_ACT_SHIFT (0U)
2233 #define TSW_CENTRAL_QCI_ACYCLETM_ACT_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_ACYCLETM_ACT_SHIFT) & TSW_CENTRAL_QCI_ACYCLETM_ACT_MASK)
2234 #define TSW_CENTRAL_QCI_ACYCLETM_ACT_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_ACYCLETM_ACT_MASK) >> TSW_CENTRAL_QCI_ACYCLETM_ACT_SHIFT)
2235 
2236 /* Bitfield definition for register: CENTRAL_QCI_ABASETM_L */
2237 /*
2238  * ABTL (R/W)
2239  *
2240  * Administrative base time. Nanoseconds and seconds part. Cycle starts after becoming operational when time is reached by inputs <rtc_sec> and <rtc_ns>.
2241  */
2242 #define TSW_CENTRAL_QCI_ABASETM_L_ABTL_MASK (0x3FFFFFFFUL)
2243 #define TSW_CENTRAL_QCI_ABASETM_L_ABTL_SHIFT (0U)
2244 #define TSW_CENTRAL_QCI_ABASETM_L_ABTL_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_ABASETM_L_ABTL_SHIFT) & TSW_CENTRAL_QCI_ABASETM_L_ABTL_MASK)
2245 #define TSW_CENTRAL_QCI_ABASETM_L_ABTL_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_ABASETM_L_ABTL_MASK) >> TSW_CENTRAL_QCI_ABASETM_L_ABTL_SHIFT)
2246 
2247 /* Bitfield definition for register: CENTRAL_QCI_ABASETM_H */
2248 /*
2249  * ABTH (R/W)
2250  *
2251  */
2252 #define TSW_CENTRAL_QCI_ABASETM_H_ABTH_MASK (0xFFFFFFFFUL)
2253 #define TSW_CENTRAL_QCI_ABASETM_H_ABTH_SHIFT (0U)
2254 #define TSW_CENTRAL_QCI_ABASETM_H_ABTH_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_ABASETM_H_ABTH_SHIFT) & TSW_CENTRAL_QCI_ABASETM_H_ABTH_MASK)
2255 #define TSW_CENTRAL_QCI_ABASETM_H_ABTH_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_ABASETM_H_ABTH_MASK) >> TSW_CENTRAL_QCI_ABASETM_H_ABTH_SHIFT)
2256 
2257 /* Bitfield definition for register: CENTRAL_QCI_AENTRY_CTRL */
2258 /*
2259  * STATE (R/W)
2260  *
2261  * AdminList – gate state (1: open)
2262  */
2263 #define TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_MASK (0x80000000UL)
2264 #define TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_SHIFT (31U)
2265 #define TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_SHIFT) & TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_MASK)
2266 #define TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_MASK) >> TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_SHIFT)
2267 
2268 /*
2269  * IPV (R/W)
2270  *
2271  * AdminList – IPV
2272  */
2273 #define TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_MASK (0x70000000UL)
2274 #define TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_SHIFT (28U)
2275 #define TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_SHIFT) & TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_MASK)
2276 #define TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_MASK) >> TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_SHIFT)
2277 
2278 /*
2279  * OCT (R/W)
2280  *
2281  * AdminList – maximum octets (0 – disabled)
2282  */
2283 #define TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_MASK (0xFFFFFFFUL)
2284 #define TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_SHIFT (0U)
2285 #define TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_SHIFT) & TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_MASK)
2286 #define TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_MASK) >> TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_SHIFT)
2287 
2288 /* Bitfield definition for register: CENTRAL_QCI_AENTRY_AENTRY_IVAL */
2289 /*
2290  * IVAL (R/W)
2291  *
2292  * AdminList – time interval in clock ticks
2293  */
2294 #define TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_MASK (0xFFFFFFFFUL)
2295 #define TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_SHIFT (0U)
2296 #define TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_SHIFT) & TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_MASK)
2297 #define TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_MASK) >> TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_SHIFT)
2298 
2299 /* Bitfield definition for register: CENTRAL_QCI_AENTRY_OCYCLETM */
2300 /*
2301  * OCT (RO)
2302  *
2303  * OperCycleTime in nanoseconds
2304  */
2305 #define TSW_CENTRAL_QCI_AENTRY_OCYCLETM_OCT_MASK (0xFFFFFFFFUL)
2306 #define TSW_CENTRAL_QCI_AENTRY_OCYCLETM_OCT_SHIFT (0U)
2307 #define TSW_CENTRAL_QCI_AENTRY_OCYCLETM_OCT_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_AENTRY_OCYCLETM_OCT_MASK) >> TSW_CENTRAL_QCI_AENTRY_OCYCLETM_OCT_SHIFT)
2308 
2309 /* Bitfield definition for register: CENTRAL_QCI_AENTRY_OBASETM_L */
2310 /*
2311  * OBTL (RO)
2312  *
2313  * OperBaseTime – nanoseconds and seconds. Constantly
2314  * updated – OperBaseTime + N * OperCycleTimt. Might
2315  * be non-normalized.
2316  */
2317 #define TSW_CENTRAL_QCI_AENTRY_OBASETM_L_OBTL_MASK (0xFFFFFFFFUL)
2318 #define TSW_CENTRAL_QCI_AENTRY_OBASETM_L_OBTL_SHIFT (0U)
2319 #define TSW_CENTRAL_QCI_AENTRY_OBASETM_L_OBTL_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_AENTRY_OBASETM_L_OBTL_MASK) >> TSW_CENTRAL_QCI_AENTRY_OBASETM_L_OBTL_SHIFT)
2320 
2321 /* Bitfield definition for register: CENTRAL_QCI_AENTRY_OBASETM_H */
2322 /*
2323  * OBTH (RO)
2324  *
2325  */
2326 #define TSW_CENTRAL_QCI_AENTRY_OBASETM_H_OBTH_MASK (0xFFFFFFFFUL)
2327 #define TSW_CENTRAL_QCI_AENTRY_OBASETM_H_OBTH_SHIFT (0U)
2328 #define TSW_CENTRAL_QCI_AENTRY_OBASETM_H_OBTH_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_AENTRY_OBASETM_H_OBTH_MASK) >> TSW_CENTRAL_QCI_AENTRY_OBASETM_H_OBTH_SHIFT)
2329 
2330 /* Bitfield definition for register: MM2S_DMA_CR */
2331 /*
2332  * MXLEN (RW)
2333  *
2334  * max axi burst size
2335  */
2336 #define TSW_MM2S_DMA_CR_MXLEN_MASK (0xFF000000UL)
2337 #define TSW_MM2S_DMA_CR_MXLEN_SHIFT (24U)
2338 #define TSW_MM2S_DMA_CR_MXLEN_SET(x) (((uint32_t)(x) << TSW_MM2S_DMA_CR_MXLEN_SHIFT) & TSW_MM2S_DMA_CR_MXLEN_MASK)
2339 #define TSW_MM2S_DMA_CR_MXLEN_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_CR_MXLEN_MASK) >> TSW_MM2S_DMA_CR_MXLEN_SHIFT)
2340 
2341 /*
2342  * IRQEN (RW)
2343  *
2344  * interrupt request enable
2345  */
2346 #define TSW_MM2S_DMA_CR_IRQEN_MASK (0x8U)
2347 #define TSW_MM2S_DMA_CR_IRQEN_SHIFT (3U)
2348 #define TSW_MM2S_DMA_CR_IRQEN_SET(x) (((uint32_t)(x) << TSW_MM2S_DMA_CR_IRQEN_SHIFT) & TSW_MM2S_DMA_CR_IRQEN_MASK)
2349 #define TSW_MM2S_DMA_CR_IRQEN_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_CR_IRQEN_MASK) >> TSW_MM2S_DMA_CR_IRQEN_SHIFT)
2350 
2351 /*
2352  * RESET (WO)
2353  *
2354  * do reset when active
2355  */
2356 #define TSW_MM2S_DMA_CR_RESET_MASK (0x4U)
2357 #define TSW_MM2S_DMA_CR_RESET_SHIFT (2U)
2358 #define TSW_MM2S_DMA_CR_RESET_SET(x) (((uint32_t)(x) << TSW_MM2S_DMA_CR_RESET_SHIFT) & TSW_MM2S_DMA_CR_RESET_MASK)
2359 #define TSW_MM2S_DMA_CR_RESET_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_CR_RESET_MASK) >> TSW_MM2S_DMA_CR_RESET_SHIFT)
2360 
2361 /*
2362  * SOE (RW)
2363  *
2364  * stop on error flag
2365  */
2366 #define TSW_MM2S_DMA_CR_SOE_MASK (0x2U)
2367 #define TSW_MM2S_DMA_CR_SOE_SHIFT (1U)
2368 #define TSW_MM2S_DMA_CR_SOE_SET(x) (((uint32_t)(x) << TSW_MM2S_DMA_CR_SOE_SHIFT) & TSW_MM2S_DMA_CR_SOE_MASK)
2369 #define TSW_MM2S_DMA_CR_SOE_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_CR_SOE_MASK) >> TSW_MM2S_DMA_CR_SOE_SHIFT)
2370 
2371 /*
2372  * RUN (RW)
2373  *
2374  * run command from queue to data mover
2375  */
2376 #define TSW_MM2S_DMA_CR_RUN_MASK (0x1U)
2377 #define TSW_MM2S_DMA_CR_RUN_SHIFT (0U)
2378 #define TSW_MM2S_DMA_CR_RUN_SET(x) (((uint32_t)(x) << TSW_MM2S_DMA_CR_RUN_SHIFT) & TSW_MM2S_DMA_CR_RUN_MASK)
2379 #define TSW_MM2S_DMA_CR_RUN_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_CR_RUN_MASK) >> TSW_MM2S_DMA_CR_RUN_SHIFT)
2380 
2381 /* Bitfield definition for register: MM2S_DMA_SR */
2382 /*
2383  * RBUFF (RO)
2384  *
2385  * response buffer full
2386  */
2387 #define TSW_MM2S_DMA_SR_RBUFF_MASK (0x80U)
2388 #define TSW_MM2S_DMA_SR_RBUFF_SHIFT (7U)
2389 #define TSW_MM2S_DMA_SR_RBUFF_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_SR_RBUFF_MASK) >> TSW_MM2S_DMA_SR_RBUFF_SHIFT)
2390 
2391 /*
2392  * RBUFE (RO)
2393  *
2394  * response buffer empty
2395  */
2396 #define TSW_MM2S_DMA_SR_RBUFE_MASK (0x40U)
2397 #define TSW_MM2S_DMA_SR_RBUFE_SHIFT (6U)
2398 #define TSW_MM2S_DMA_SR_RBUFE_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_SR_RBUFE_MASK) >> TSW_MM2S_DMA_SR_RBUFE_SHIFT)
2399 
2400 /*
2401  * CBUFF (RO)
2402  *
2403  * command buffer full
2404  */
2405 #define TSW_MM2S_DMA_SR_CBUFF_MASK (0x20U)
2406 #define TSW_MM2S_DMA_SR_CBUFF_SHIFT (5U)
2407 #define TSW_MM2S_DMA_SR_CBUFF_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_SR_CBUFF_MASK) >> TSW_MM2S_DMA_SR_CBUFF_SHIFT)
2408 
2409 /*
2410  * CBUFE (RO)
2411  *
2412  * command buffer empty
2413  */
2414 #define TSW_MM2S_DMA_SR_CBUFE_MASK (0x10U)
2415 #define TSW_MM2S_DMA_SR_CBUFE_SHIFT (4U)
2416 #define TSW_MM2S_DMA_SR_CBUFE_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_SR_CBUFE_MASK) >> TSW_MM2S_DMA_SR_CBUFE_SHIFT)
2417 
2418 /*
2419  * IRQ (RWC)
2420  *
2421  * interrupt request pending
2422  */
2423 #define TSW_MM2S_DMA_SR_IRQ_MASK (0x8U)
2424 #define TSW_MM2S_DMA_SR_IRQ_SHIFT (3U)
2425 #define TSW_MM2S_DMA_SR_IRQ_SET(x) (((uint32_t)(x) << TSW_MM2S_DMA_SR_IRQ_SHIFT) & TSW_MM2S_DMA_SR_IRQ_MASK)
2426 #define TSW_MM2S_DMA_SR_IRQ_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_SR_IRQ_MASK) >> TSW_MM2S_DMA_SR_IRQ_SHIFT)
2427 
2428 /*
2429  * RSET (RO)
2430  *
2431  * resetting status
2432  */
2433 #define TSW_MM2S_DMA_SR_RSET_MASK (0x4U)
2434 #define TSW_MM2S_DMA_SR_RSET_SHIFT (2U)
2435 #define TSW_MM2S_DMA_SR_RSET_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_SR_RSET_MASK) >> TSW_MM2S_DMA_SR_RSET_SHIFT)
2436 
2437 /*
2438  * BUSY (RO)
2439  *
2440  * busy
2441  */
2442 #define TSW_MM2S_DMA_SR_BUSY_MASK (0x2U)
2443 #define TSW_MM2S_DMA_SR_BUSY_SHIFT (1U)
2444 #define TSW_MM2S_DMA_SR_BUSY_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_SR_BUSY_MASK) >> TSW_MM2S_DMA_SR_BUSY_SHIFT)
2445 
2446 /*
2447  * STOP (RO)
2448  *
2449  * mm2s is stopped
2450  */
2451 #define TSW_MM2S_DMA_SR_STOP_MASK (0x1U)
2452 #define TSW_MM2S_DMA_SR_STOP_SHIFT (0U)
2453 #define TSW_MM2S_DMA_SR_STOP_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_SR_STOP_MASK) >> TSW_MM2S_DMA_SR_STOP_SHIFT)
2454 
2455 /* Bitfield definition for register: MM2S_DMA_FILL */
2456 /*
2457  * RFILL (RO)
2458  *
2459  * response buffer fill level
2460  */
2461 #define TSW_MM2S_DMA_FILL_RFILL_MASK (0xFFFF0000UL)
2462 #define TSW_MM2S_DMA_FILL_RFILL_SHIFT (16U)
2463 #define TSW_MM2S_DMA_FILL_RFILL_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_FILL_RFILL_MASK) >> TSW_MM2S_DMA_FILL_RFILL_SHIFT)
2464 
2465 /*
2466  * CFILL (RO)
2467  *
2468  * command buffer fill level
2469  */
2470 #define TSW_MM2S_DMA_FILL_CFILL_MASK (0xFFFFU)
2471 #define TSW_MM2S_DMA_FILL_CFILL_SHIFT (0U)
2472 #define TSW_MM2S_DMA_FILL_CFILL_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_FILL_CFILL_MASK) >> TSW_MM2S_DMA_FILL_CFILL_SHIFT)
2473 
2474 /* Bitfield definition for register: MM2S_DMA_CFG */
2475 /*
2476  * DBUFD (RO)
2477  *
2478  * data buffer depth
2479  */
2480 #define TSW_MM2S_DMA_CFG_DBUFD_MASK (0xF000000UL)
2481 #define TSW_MM2S_DMA_CFG_DBUFD_SHIFT (24U)
2482 #define TSW_MM2S_DMA_CFG_DBUFD_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_CFG_DBUFD_MASK) >> TSW_MM2S_DMA_CFG_DBUFD_SHIFT)
2483 
2484 /*
2485  * CBUFD (RO)
2486  *
2487  * command buffer depth
2488  */
2489 #define TSW_MM2S_DMA_CFG_CBUFD_MASK (0xF00000UL)
2490 #define TSW_MM2S_DMA_CFG_CBUFD_SHIFT (20U)
2491 #define TSW_MM2S_DMA_CFG_CBUFD_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_CFG_CBUFD_MASK) >> TSW_MM2S_DMA_CFG_CBUFD_SHIFT)
2492 
2493 /*
2494  * ENA64 (RO)
2495  *
2496  * enable support for 64 bit addressing
2497  */
2498 #define TSW_MM2S_DMA_CFG_ENA64_MASK (0x80000UL)
2499 #define TSW_MM2S_DMA_CFG_ENA64_SHIFT (19U)
2500 #define TSW_MM2S_DMA_CFG_ENA64_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_CFG_ENA64_MASK) >> TSW_MM2S_DMA_CFG_ENA64_SHIFT)
2501 
2502 /*
2503  * ASIZE (RO)
2504  *
2505  * axi data bus width
2506  */
2507 #define TSW_MM2S_DMA_CFG_ASIZE_MASK (0x70000UL)
2508 #define TSW_MM2S_DMA_CFG_ASIZE_SHIFT (16U)
2509 #define TSW_MM2S_DMA_CFG_ASIZE_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_CFG_ASIZE_MASK) >> TSW_MM2S_DMA_CFG_ASIZE_SHIFT)
2510 
2511 /*
2512  * VER (RO)
2513  *
2514  * ip version
2515  */
2516 #define TSW_MM2S_DMA_CFG_VER_MASK (0xFFFFU)
2517 #define TSW_MM2S_DMA_CFG_VER_SHIFT (0U)
2518 #define TSW_MM2S_DMA_CFG_VER_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_CFG_VER_MASK) >> TSW_MM2S_DMA_CFG_VER_SHIFT)
2519 
2520 /* Bitfield definition for register: MM2S_ADDRLO */
2521 /*
2522  * ADDRLO (RW)
2523  *
2524  * axi address
2525  */
2526 #define TSW_MM2S_ADDRLO_ADDRLO_MASK (0xFFFFFFFFUL)
2527 #define TSW_MM2S_ADDRLO_ADDRLO_SHIFT (0U)
2528 #define TSW_MM2S_ADDRLO_ADDRLO_SET(x) (((uint32_t)(x) << TSW_MM2S_ADDRLO_ADDRLO_SHIFT) & TSW_MM2S_ADDRLO_ADDRLO_MASK)
2529 #define TSW_MM2S_ADDRLO_ADDRLO_GET(x) (((uint32_t)(x) & TSW_MM2S_ADDRLO_ADDRLO_MASK) >> TSW_MM2S_ADDRLO_ADDRLO_SHIFT)
2530 
2531 /* Bitfield definition for register: MM2S_LENGTH */
2532 /*
2533  * LENGTH (RW)
2534  *
2535  * transfer request length in bytes
2536  */
2537 #define TSW_MM2S_LENGTH_LENGTH_MASK (0xFFFFU)
2538 #define TSW_MM2S_LENGTH_LENGTH_SHIFT (0U)
2539 #define TSW_MM2S_LENGTH_LENGTH_SET(x) (((uint32_t)(x) << TSW_MM2S_LENGTH_LENGTH_SHIFT) & TSW_MM2S_LENGTH_LENGTH_MASK)
2540 #define TSW_MM2S_LENGTH_LENGTH_GET(x) (((uint32_t)(x) & TSW_MM2S_LENGTH_LENGTH_MASK) >> TSW_MM2S_LENGTH_LENGTH_SHIFT)
2541 
2542 /* Bitfield definition for register: MM2S_CTRL */
2543 /*
2544  * GO (WO)
2545  *
2546  * commit buffered descriptor to command queue
2547  */
2548 #define TSW_MM2S_CTRL_GO_MASK (0x80000000UL)
2549 #define TSW_MM2S_CTRL_GO_SHIFT (31U)
2550 #define TSW_MM2S_CTRL_GO_SET(x) (((uint32_t)(x) << TSW_MM2S_CTRL_GO_SHIFT) & TSW_MM2S_CTRL_GO_MASK)
2551 #define TSW_MM2S_CTRL_GO_GET(x) (((uint32_t)(x) & TSW_MM2S_CTRL_GO_MASK) >> TSW_MM2S_CTRL_GO_SHIFT)
2552 
2553 /*
2554  * NGENLAST (RW)
2555  *
2556  * no generation of TLAST
2557  */
2558 #define TSW_MM2S_CTRL_NGENLAST_MASK (0x10U)
2559 #define TSW_MM2S_CTRL_NGENLAST_SHIFT (4U)
2560 #define TSW_MM2S_CTRL_NGENLAST_SET(x) (((uint32_t)(x) << TSW_MM2S_CTRL_NGENLAST_SHIFT) & TSW_MM2S_CTRL_NGENLAST_MASK)
2561 #define TSW_MM2S_CTRL_NGENLAST_GET(x) (((uint32_t)(x) & TSW_MM2S_CTRL_NGENLAST_MASK) >> TSW_MM2S_CTRL_NGENLAST_SHIFT)
2562 
2563 /*
2564  * ID (RW)
2565  *
2566  * command id
2567  */
2568 #define TSW_MM2S_CTRL_ID_MASK (0xFU)
2569 #define TSW_MM2S_CTRL_ID_SHIFT (0U)
2570 #define TSW_MM2S_CTRL_ID_SET(x) (((uint32_t)(x) << TSW_MM2S_CTRL_ID_SHIFT) & TSW_MM2S_CTRL_ID_MASK)
2571 #define TSW_MM2S_CTRL_ID_GET(x) (((uint32_t)(x) & TSW_MM2S_CTRL_ID_MASK) >> TSW_MM2S_CTRL_ID_SHIFT)
2572 
2573 /* Bitfield definition for register: MM2S_RESP */
2574 /*
2575  * LAST (RO)
2576  *
2577  * axi-stream with TLAST
2578  */
2579 #define TSW_MM2S_RESP_LAST_MASK (0x40000000UL)
2580 #define TSW_MM2S_RESP_LAST_SHIFT (30U)
2581 #define TSW_MM2S_RESP_LAST_GET(x) (((uint32_t)(x) & TSW_MM2S_RESP_LAST_MASK) >> TSW_MM2S_RESP_LAST_SHIFT)
2582 
2583 /*
2584  * DECERR (RO)
2585  *
2586  * decode error
2587  */
2588 #define TSW_MM2S_RESP_DECERR_MASK (0x20000000UL)
2589 #define TSW_MM2S_RESP_DECERR_SHIFT (29U)
2590 #define TSW_MM2S_RESP_DECERR_GET(x) (((uint32_t)(x) & TSW_MM2S_RESP_DECERR_MASK) >> TSW_MM2S_RESP_DECERR_SHIFT)
2591 
2592 /*
2593  * SLVERR (RO)
2594  *
2595  * slave error
2596  */
2597 #define TSW_MM2S_RESP_SLVERR_MASK (0x10000000UL)
2598 #define TSW_MM2S_RESP_SLVERR_SHIFT (28U)
2599 #define TSW_MM2S_RESP_SLVERR_GET(x) (((uint32_t)(x) & TSW_MM2S_RESP_SLVERR_MASK) >> TSW_MM2S_RESP_SLVERR_SHIFT)
2600 
2601 /*
2602  * ID (RO)
2603  *
2604  * command ID feedback
2605  */
2606 #define TSW_MM2S_RESP_ID_MASK (0xF000000UL)
2607 #define TSW_MM2S_RESP_ID_SHIFT (24U)
2608 #define TSW_MM2S_RESP_ID_GET(x) (((uint32_t)(x) & TSW_MM2S_RESP_ID_MASK) >> TSW_MM2S_RESP_ID_SHIFT)
2609 
2610 /*
2611  * LENGTH (RO)
2612  *
2613  * requested length of tansfer in bytes from command
2614  */
2615 #define TSW_MM2S_RESP_LENGTH_MASK (0xFFFFU)
2616 #define TSW_MM2S_RESP_LENGTH_SHIFT (0U)
2617 #define TSW_MM2S_RESP_LENGTH_GET(x) (((uint32_t)(x) & TSW_MM2S_RESP_LENGTH_MASK) >> TSW_MM2S_RESP_LENGTH_SHIFT)
2618 
2619 /* Bitfield definition for register: S2MM_DMA_CR */
2620 /*
2621  * MXLEN (RW)
2622  *
2623  * max axi burst size
2624  */
2625 #define TSW_S2MM_DMA_CR_MXLEN_MASK (0xFF000000UL)
2626 #define TSW_S2MM_DMA_CR_MXLEN_SHIFT (24U)
2627 #define TSW_S2MM_DMA_CR_MXLEN_SET(x) (((uint32_t)(x) << TSW_S2MM_DMA_CR_MXLEN_SHIFT) & TSW_S2MM_DMA_CR_MXLEN_MASK)
2628 #define TSW_S2MM_DMA_CR_MXLEN_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_CR_MXLEN_MASK) >> TSW_S2MM_DMA_CR_MXLEN_SHIFT)
2629 
2630 /*
2631  * IRQEN (RW)
2632  *
2633  * interrupt request enable
2634  */
2635 #define TSW_S2MM_DMA_CR_IRQEN_MASK (0x8U)
2636 #define TSW_S2MM_DMA_CR_IRQEN_SHIFT (3U)
2637 #define TSW_S2MM_DMA_CR_IRQEN_SET(x) (((uint32_t)(x) << TSW_S2MM_DMA_CR_IRQEN_SHIFT) & TSW_S2MM_DMA_CR_IRQEN_MASK)
2638 #define TSW_S2MM_DMA_CR_IRQEN_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_CR_IRQEN_MASK) >> TSW_S2MM_DMA_CR_IRQEN_SHIFT)
2639 
2640 /*
2641  * RESET (WO)
2642  *
2643  * do reset when writing 1
2644  */
2645 #define TSW_S2MM_DMA_CR_RESET_MASK (0x4U)
2646 #define TSW_S2MM_DMA_CR_RESET_SHIFT (2U)
2647 #define TSW_S2MM_DMA_CR_RESET_SET(x) (((uint32_t)(x) << TSW_S2MM_DMA_CR_RESET_SHIFT) & TSW_S2MM_DMA_CR_RESET_MASK)
2648 #define TSW_S2MM_DMA_CR_RESET_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_CR_RESET_MASK) >> TSW_S2MM_DMA_CR_RESET_SHIFT)
2649 
2650 /*
2651  * SOE (RW)
2652  *
2653  * stop on error flag
2654  */
2655 #define TSW_S2MM_DMA_CR_SOE_MASK (0x2U)
2656 #define TSW_S2MM_DMA_CR_SOE_SHIFT (1U)
2657 #define TSW_S2MM_DMA_CR_SOE_SET(x) (((uint32_t)(x) << TSW_S2MM_DMA_CR_SOE_SHIFT) & TSW_S2MM_DMA_CR_SOE_MASK)
2658 #define TSW_S2MM_DMA_CR_SOE_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_CR_SOE_MASK) >> TSW_S2MM_DMA_CR_SOE_SHIFT)
2659 
2660 /*
2661  * RUN (RW)
2662  *
2663  * run commands from queue to data mover
2664  */
2665 #define TSW_S2MM_DMA_CR_RUN_MASK (0x1U)
2666 #define TSW_S2MM_DMA_CR_RUN_SHIFT (0U)
2667 #define TSW_S2MM_DMA_CR_RUN_SET(x) (((uint32_t)(x) << TSW_S2MM_DMA_CR_RUN_SHIFT) & TSW_S2MM_DMA_CR_RUN_MASK)
2668 #define TSW_S2MM_DMA_CR_RUN_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_CR_RUN_MASK) >> TSW_S2MM_DMA_CR_RUN_SHIFT)
2669 
2670 /* Bitfield definition for register: S2MM_DMA_SR */
2671 /*
2672  * RBUFF (RO)
2673  *
2674  * response buffer full
2675  */
2676 #define TSW_S2MM_DMA_SR_RBUFF_MASK (0x80U)
2677 #define TSW_S2MM_DMA_SR_RBUFF_SHIFT (7U)
2678 #define TSW_S2MM_DMA_SR_RBUFF_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_SR_RBUFF_MASK) >> TSW_S2MM_DMA_SR_RBUFF_SHIFT)
2679 
2680 /*
2681  * RBUFE (RO)
2682  *
2683  * response buffer empty
2684  */
2685 #define TSW_S2MM_DMA_SR_RBUFE_MASK (0x40U)
2686 #define TSW_S2MM_DMA_SR_RBUFE_SHIFT (6U)
2687 #define TSW_S2MM_DMA_SR_RBUFE_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_SR_RBUFE_MASK) >> TSW_S2MM_DMA_SR_RBUFE_SHIFT)
2688 
2689 /*
2690  * CBUFF (RO)
2691  *
2692  * command buffer full
2693  */
2694 #define TSW_S2MM_DMA_SR_CBUFF_MASK (0x20U)
2695 #define TSW_S2MM_DMA_SR_CBUFF_SHIFT (5U)
2696 #define TSW_S2MM_DMA_SR_CBUFF_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_SR_CBUFF_MASK) >> TSW_S2MM_DMA_SR_CBUFF_SHIFT)
2697 
2698 /*
2699  * CBUFE (RO)
2700  *
2701  * command buffer empty
2702  */
2703 #define TSW_S2MM_DMA_SR_CBUFE_MASK (0x10U)
2704 #define TSW_S2MM_DMA_SR_CBUFE_SHIFT (4U)
2705 #define TSW_S2MM_DMA_SR_CBUFE_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_SR_CBUFE_MASK) >> TSW_S2MM_DMA_SR_CBUFE_SHIFT)
2706 
2707 /*
2708  * IRQ (RWC)
2709  *
2710  * interrupt request pending
2711  */
2712 #define TSW_S2MM_DMA_SR_IRQ_MASK (0x8U)
2713 #define TSW_S2MM_DMA_SR_IRQ_SHIFT (3U)
2714 #define TSW_S2MM_DMA_SR_IRQ_SET(x) (((uint32_t)(x) << TSW_S2MM_DMA_SR_IRQ_SHIFT) & TSW_S2MM_DMA_SR_IRQ_MASK)
2715 #define TSW_S2MM_DMA_SR_IRQ_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_SR_IRQ_MASK) >> TSW_S2MM_DMA_SR_IRQ_SHIFT)
2716 
2717 /*
2718  * RSET (RO)
2719  *
2720  * resetting status
2721  */
2722 #define TSW_S2MM_DMA_SR_RSET_MASK (0x4U)
2723 #define TSW_S2MM_DMA_SR_RSET_SHIFT (2U)
2724 #define TSW_S2MM_DMA_SR_RSET_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_SR_RSET_MASK) >> TSW_S2MM_DMA_SR_RSET_SHIFT)
2725 
2726 /*
2727  * BUSY (RO)
2728  *
2729  * busy, issued command and outstanding response
2730  */
2731 #define TSW_S2MM_DMA_SR_BUSY_MASK (0x2U)
2732 #define TSW_S2MM_DMA_SR_BUSY_SHIFT (1U)
2733 #define TSW_S2MM_DMA_SR_BUSY_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_SR_BUSY_MASK) >> TSW_S2MM_DMA_SR_BUSY_SHIFT)
2734 
2735 /*
2736  * STOP (RO)
2737  *
2738  * s2mm is stopped
2739  */
2740 #define TSW_S2MM_DMA_SR_STOP_MASK (0x1U)
2741 #define TSW_S2MM_DMA_SR_STOP_SHIFT (0U)
2742 #define TSW_S2MM_DMA_SR_STOP_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_SR_STOP_MASK) >> TSW_S2MM_DMA_SR_STOP_SHIFT)
2743 
2744 /* Bitfield definition for register: S2MM_DMA_FILL */
2745 /*
2746  * RFILL (RO)
2747  *
2748  * response buffer fill level
2749  */
2750 #define TSW_S2MM_DMA_FILL_RFILL_MASK (0xFFFF0000UL)
2751 #define TSW_S2MM_DMA_FILL_RFILL_SHIFT (16U)
2752 #define TSW_S2MM_DMA_FILL_RFILL_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_FILL_RFILL_MASK) >> TSW_S2MM_DMA_FILL_RFILL_SHIFT)
2753 
2754 /*
2755  * CFILL (RO)
2756  *
2757  * command buffer fill level
2758  */
2759 #define TSW_S2MM_DMA_FILL_CFILL_MASK (0xFFFFU)
2760 #define TSW_S2MM_DMA_FILL_CFILL_SHIFT (0U)
2761 #define TSW_S2MM_DMA_FILL_CFILL_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_FILL_CFILL_MASK) >> TSW_S2MM_DMA_FILL_CFILL_SHIFT)
2762 
2763 /* Bitfield definition for register: S2MM_DMA_CFG */
2764 /*
2765  * DBUFD (RO)
2766  *
2767  * data buffer depth
2768  */
2769 #define TSW_S2MM_DMA_CFG_DBUFD_MASK (0xF000000UL)
2770 #define TSW_S2MM_DMA_CFG_DBUFD_SHIFT (24U)
2771 #define TSW_S2MM_DMA_CFG_DBUFD_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_CFG_DBUFD_MASK) >> TSW_S2MM_DMA_CFG_DBUFD_SHIFT)
2772 
2773 /*
2774  * CBUFD (RO)
2775  *
2776  * command buffer depth
2777  */
2778 #define TSW_S2MM_DMA_CFG_CBUFD_MASK (0xF00000UL)
2779 #define TSW_S2MM_DMA_CFG_CBUFD_SHIFT (20U)
2780 #define TSW_S2MM_DMA_CFG_CBUFD_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_CFG_CBUFD_MASK) >> TSW_S2MM_DMA_CFG_CBUFD_SHIFT)
2781 
2782 /*
2783  * ENA64 (RO)
2784  *
2785  * enabled support for 64 bit
2786  */
2787 #define TSW_S2MM_DMA_CFG_ENA64_MASK (0x80000UL)
2788 #define TSW_S2MM_DMA_CFG_ENA64_SHIFT (19U)
2789 #define TSW_S2MM_DMA_CFG_ENA64_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_CFG_ENA64_MASK) >> TSW_S2MM_DMA_CFG_ENA64_SHIFT)
2790 
2791 /*
2792  * ASIZE (RO)
2793  *
2794  * axi data bus width
2795  */
2796 #define TSW_S2MM_DMA_CFG_ASIZE_MASK (0x70000UL)
2797 #define TSW_S2MM_DMA_CFG_ASIZE_SHIFT (16U)
2798 #define TSW_S2MM_DMA_CFG_ASIZE_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_CFG_ASIZE_MASK) >> TSW_S2MM_DMA_CFG_ASIZE_SHIFT)
2799 
2800 /*
2801  * VER (RO)
2802  *
2803  * IP version
2804  */
2805 #define TSW_S2MM_DMA_CFG_VER_MASK (0xFFFFU)
2806 #define TSW_S2MM_DMA_CFG_VER_SHIFT (0U)
2807 #define TSW_S2MM_DMA_CFG_VER_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_CFG_VER_MASK) >> TSW_S2MM_DMA_CFG_VER_SHIFT)
2808 
2809 /* Bitfield definition for register: S2MM_ADDRLO */
2810 /*
2811  * ADDRLO (RW)
2812  *
2813  * axi address
2814  */
2815 #define TSW_S2MM_ADDRLO_ADDRLO_MASK (0xFFFFFFFFUL)
2816 #define TSW_S2MM_ADDRLO_ADDRLO_SHIFT (0U)
2817 #define TSW_S2MM_ADDRLO_ADDRLO_SET(x) (((uint32_t)(x) << TSW_S2MM_ADDRLO_ADDRLO_SHIFT) & TSW_S2MM_ADDRLO_ADDRLO_MASK)
2818 #define TSW_S2MM_ADDRLO_ADDRLO_GET(x) (((uint32_t)(x) & TSW_S2MM_ADDRLO_ADDRLO_MASK) >> TSW_S2MM_ADDRLO_ADDRLO_SHIFT)
2819 
2820 /* Bitfield definition for register: S2MM_LENGTH */
2821 /*
2822  * LENGTH (RW)
2823  *
2824  * transfer request length in bytes
2825  */
2826 #define TSW_S2MM_LENGTH_LENGTH_MASK (0xFFFFU)
2827 #define TSW_S2MM_LENGTH_LENGTH_SHIFT (0U)
2828 #define TSW_S2MM_LENGTH_LENGTH_SET(x) (((uint32_t)(x) << TSW_S2MM_LENGTH_LENGTH_SHIFT) & TSW_S2MM_LENGTH_LENGTH_MASK)
2829 #define TSW_S2MM_LENGTH_LENGTH_GET(x) (((uint32_t)(x) & TSW_S2MM_LENGTH_LENGTH_MASK) >> TSW_S2MM_LENGTH_LENGTH_SHIFT)
2830 
2831 /* Bitfield definition for register: S2MM_CTRL */
2832 /*
2833  * GO (WO)
2834  *
2835  * commit buffered descriptor to command queue
2836  */
2837 #define TSW_S2MM_CTRL_GO_MASK (0x80000000UL)
2838 #define TSW_S2MM_CTRL_GO_SHIFT (31U)
2839 #define TSW_S2MM_CTRL_GO_SET(x) (((uint32_t)(x) << TSW_S2MM_CTRL_GO_SHIFT) & TSW_S2MM_CTRL_GO_MASK)
2840 #define TSW_S2MM_CTRL_GO_GET(x) (((uint32_t)(x) & TSW_S2MM_CTRL_GO_MASK) >> TSW_S2MM_CTRL_GO_SHIFT)
2841 
2842 /*
2843  * ID (RW)
2844  *
2845  * command id
2846  */
2847 #define TSW_S2MM_CTRL_ID_MASK (0xFU)
2848 #define TSW_S2MM_CTRL_ID_SHIFT (0U)
2849 #define TSW_S2MM_CTRL_ID_SET(x) (((uint32_t)(x) << TSW_S2MM_CTRL_ID_SHIFT) & TSW_S2MM_CTRL_ID_MASK)
2850 #define TSW_S2MM_CTRL_ID_GET(x) (((uint32_t)(x) & TSW_S2MM_CTRL_ID_MASK) >> TSW_S2MM_CTRL_ID_SHIFT)
2851 
2852 /* Bitfield definition for register: S2MM_RESP */
2853 /*
2854  * LAST (RO)
2855  *
2856  * axi-stream with last
2857  */
2858 #define TSW_S2MM_RESP_LAST_MASK (0x40000000UL)
2859 #define TSW_S2MM_RESP_LAST_SHIFT (30U)
2860 #define TSW_S2MM_RESP_LAST_GET(x) (((uint32_t)(x) & TSW_S2MM_RESP_LAST_MASK) >> TSW_S2MM_RESP_LAST_SHIFT)
2861 
2862 /*
2863  * DECERR (RO)
2864  *
2865  * decode error
2866  */
2867 #define TSW_S2MM_RESP_DECERR_MASK (0x20000000UL)
2868 #define TSW_S2MM_RESP_DECERR_SHIFT (29U)
2869 #define TSW_S2MM_RESP_DECERR_GET(x) (((uint32_t)(x) & TSW_S2MM_RESP_DECERR_MASK) >> TSW_S2MM_RESP_DECERR_SHIFT)
2870 
2871 /*
2872  * SLVERR (RO)
2873  *
2874  * slave error
2875  */
2876 #define TSW_S2MM_RESP_SLVERR_MASK (0x10000000UL)
2877 #define TSW_S2MM_RESP_SLVERR_SHIFT (28U)
2878 #define TSW_S2MM_RESP_SLVERR_GET(x) (((uint32_t)(x) & TSW_S2MM_RESP_SLVERR_MASK) >> TSW_S2MM_RESP_SLVERR_SHIFT)
2879 
2880 /*
2881  * ID (RO)
2882  *
2883  * command ID feedback
2884  */
2885 #define TSW_S2MM_RESP_ID_MASK (0xF000000UL)
2886 #define TSW_S2MM_RESP_ID_SHIFT (24U)
2887 #define TSW_S2MM_RESP_ID_GET(x) (((uint32_t)(x) & TSW_S2MM_RESP_ID_MASK) >> TSW_S2MM_RESP_ID_SHIFT)
2888 
2889 /*
2890  * LENGTH (RO)
2891  *
2892  * received packet size when terminated by TLAST
2893  */
2894 #define TSW_S2MM_RESP_LENGTH_MASK (0xFFFFU)
2895 #define TSW_S2MM_RESP_LENGTH_SHIFT (0U)
2896 #define TSW_S2MM_RESP_LENGTH_GET(x) (((uint32_t)(x) & TSW_S2MM_RESP_LENGTH_MASK) >> TSW_S2MM_RESP_LENGTH_SHIFT)
2897 
2898 /* Bitfield definition for register: PTP_EVT_TS_CTL */
2899 /*
2900  * ATSEN (RW)
2901  *
2902  * auxiliay snapshot enable
2903  */
2904 #define TSW_PTP_EVT_TS_CTL_ATSEN_MASK (0x1E000000UL)
2905 #define TSW_PTP_EVT_TS_CTL_ATSEN_SHIFT (25U)
2906 #define TSW_PTP_EVT_TS_CTL_ATSEN_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_TS_CTL_ATSEN_SHIFT) & TSW_PTP_EVT_TS_CTL_ATSEN_MASK)
2907 #define TSW_PTP_EVT_TS_CTL_ATSEN_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TS_CTL_ATSEN_MASK) >> TSW_PTP_EVT_TS_CTL_ATSEN_SHIFT)
2908 
2909 /*
2910  * ATSFC (W1C)
2911  *
2912  * auxiliary snapshot fifo clear
2913  */
2914 #define TSW_PTP_EVT_TS_CTL_ATSFC_MASK (0x1000000UL)
2915 #define TSW_PTP_EVT_TS_CTL_ATSFC_SHIFT (24U)
2916 #define TSW_PTP_EVT_TS_CTL_ATSFC_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_TS_CTL_ATSFC_SHIFT) & TSW_PTP_EVT_TS_CTL_ATSFC_MASK)
2917 #define TSW_PTP_EVT_TS_CTL_ATSFC_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TS_CTL_ATSFC_MASK) >> TSW_PTP_EVT_TS_CTL_ATSFC_SHIFT)
2918 
2919 /*
2920  * TSTIG (RW)
2921  *
2922  * timestamp interrupt trigger enable
2923  */
2924 #define TSW_PTP_EVT_TS_CTL_TSTIG_MASK (0x10U)
2925 #define TSW_PTP_EVT_TS_CTL_TSTIG_SHIFT (4U)
2926 #define TSW_PTP_EVT_TS_CTL_TSTIG_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_TS_CTL_TSTIG_SHIFT) & TSW_PTP_EVT_TS_CTL_TSTIG_MASK)
2927 #define TSW_PTP_EVT_TS_CTL_TSTIG_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TS_CTL_TSTIG_MASK) >> TSW_PTP_EVT_TS_CTL_TSTIG_SHIFT)
2928 
2929 /* Bitfield definition for register: PTP_EVT_PPS_TOD_SEC */
2930 /*
2931  * PPS_TOD_SEC (RO)
2932  *
2933  * pps tod seconds
2934  */
2935 #define TSW_PTP_EVT_PPS_TOD_SEC_PPS_TOD_SEC_MASK (0xFFFFFFFFUL)
2936 #define TSW_PTP_EVT_PPS_TOD_SEC_PPS_TOD_SEC_SHIFT (0U)
2937 #define TSW_PTP_EVT_PPS_TOD_SEC_PPS_TOD_SEC_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_TOD_SEC_PPS_TOD_SEC_MASK) >> TSW_PTP_EVT_PPS_TOD_SEC_PPS_TOD_SEC_SHIFT)
2938 
2939 /* Bitfield definition for register: PTP_EVT_PPS_TOD_NS */
2940 /*
2941  * PPS_TOD_NS (RO)
2942  *
2943  * pps tod sub seconds
2944  */
2945 #define TSW_PTP_EVT_PPS_TOD_NS_PPS_TOD_NS_MASK (0x3FFFFFFFUL)
2946 #define TSW_PTP_EVT_PPS_TOD_NS_PPS_TOD_NS_SHIFT (0U)
2947 #define TSW_PTP_EVT_PPS_TOD_NS_PPS_TOD_NS_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_TOD_NS_PPS_TOD_NS_MASK) >> TSW_PTP_EVT_PPS_TOD_NS_PPS_TOD_NS_SHIFT)
2948 
2949 /* Bitfield definition for register: PTP_EVT_SCP_SEC0 */
2950 /*
2951  * SCP_SEC (RW)
2952  *
2953  * target time seconds
2954  */
2955 #define TSW_PTP_EVT_SCP_SEC0_SCP_SEC_MASK (0xFFFFFFFFUL)
2956 #define TSW_PTP_EVT_SCP_SEC0_SCP_SEC_SHIFT (0U)
2957 #define TSW_PTP_EVT_SCP_SEC0_SCP_SEC_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_SCP_SEC0_SCP_SEC_SHIFT) & TSW_PTP_EVT_SCP_SEC0_SCP_SEC_MASK)
2958 #define TSW_PTP_EVT_SCP_SEC0_SCP_SEC_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_SCP_SEC0_SCP_SEC_MASK) >> TSW_PTP_EVT_SCP_SEC0_SCP_SEC_SHIFT)
2959 
2960 /* Bitfield definition for register: PTP_EVT_SCP_NS0 */
2961 /*
2962  * SCP_NS (RW)
2963  *
2964  * target time sub seconds
2965  */
2966 #define TSW_PTP_EVT_SCP_NS0_SCP_NS_MASK (0x3FFFFFFFUL)
2967 #define TSW_PTP_EVT_SCP_NS0_SCP_NS_SHIFT (0U)
2968 #define TSW_PTP_EVT_SCP_NS0_SCP_NS_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_SCP_NS0_SCP_NS_SHIFT) & TSW_PTP_EVT_SCP_NS0_SCP_NS_MASK)
2969 #define TSW_PTP_EVT_SCP_NS0_SCP_NS_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_SCP_NS0_SCP_NS_MASK) >> TSW_PTP_EVT_SCP_NS0_SCP_NS_SHIFT)
2970 
2971 /* Bitfield definition for register: PTP_EVT_TMR_STS */
2972 /*
2973  * RD_CNT (RO)
2974  *
2975  * fifo valid count
2976  */
2977 #define TSW_PTP_EVT_TMR_STS_RD_CNT_MASK (0x3E000000UL)
2978 #define TSW_PTP_EVT_TMR_STS_RD_CNT_SHIFT (25U)
2979 #define TSW_PTP_EVT_TMR_STS_RD_CNT_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_RD_CNT_MASK) >> TSW_PTP_EVT_TMR_STS_RD_CNT_SHIFT)
2980 
2981 /*
2982  * ATSSTM (RO)
2983  *
2984  * auxiliary fifo full error
2985  */
2986 #define TSW_PTP_EVT_TMR_STS_ATSSTM_MASK (0x1000000UL)
2987 #define TSW_PTP_EVT_TMR_STS_ATSSTM_SHIFT (24U)
2988 #define TSW_PTP_EVT_TMR_STS_ATSSTM_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_ATSSTM_MASK) >> TSW_PTP_EVT_TMR_STS_ATSSTM_SHIFT)
2989 
2990 /*
2991  * ATPORT (RO)
2992  *
2993  * auxiliary port
2994  */
2995 #define TSW_PTP_EVT_TMR_STS_ATPORT_MASK (0xF0000UL)
2996 #define TSW_PTP_EVT_TMR_STS_ATPORT_SHIFT (16U)
2997 #define TSW_PTP_EVT_TMR_STS_ATPORT_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_ATPORT_MASK) >> TSW_PTP_EVT_TMR_STS_ATPORT_SHIFT)
2998 
2999 /*
3000  * PPS_TOD_INTR (RC)
3001  *
3002  * pps tod intrrupt
3003  */
3004 #define TSW_PTP_EVT_TMR_STS_PPS_TOD_INTR_MASK (0x400U)
3005 #define TSW_PTP_EVT_TMR_STS_PPS_TOD_INTR_SHIFT (10U)
3006 #define TSW_PTP_EVT_TMR_STS_PPS_TOD_INTR_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_PPS_TOD_INTR_MASK) >> TSW_PTP_EVT_TMR_STS_PPS_TOD_INTR_SHIFT)
3007 
3008 /*
3009  * TARGET_TIME3_CFG_ERR (RO)
3010  *
3011  * target time3 configure error
3012  */
3013 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME3_CFG_ERR_MASK (0x200U)
3014 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME3_CFG_ERR_SHIFT (9U)
3015 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME3_CFG_ERR_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME3_CFG_ERR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME3_CFG_ERR_SHIFT)
3016 
3017 /*
3018  * TARGET_TIME3_REACH_INTR (RC)
3019  *
3020  * target time3 reached
3021  */
3022 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME3_REACH_INTR_MASK (0x100U)
3023 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME3_REACH_INTR_SHIFT (8U)
3024 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME3_REACH_INTR_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME3_REACH_INTR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME3_REACH_INTR_SHIFT)
3025 
3026 /*
3027  * TARGET_TIME2_CFG_ERR (RO)
3028  *
3029  * target time2 configure error
3030  */
3031 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME2_CFG_ERR_MASK (0x80U)
3032 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME2_CFG_ERR_SHIFT (7U)
3033 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME2_CFG_ERR_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME2_CFG_ERR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME2_CFG_ERR_SHIFT)
3034 
3035 /*
3036  * TARGET_TIME2_REACH_INTR (RC)
3037  *
3038  * target time2 reached
3039  */
3040 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME2_REACH_INTR_MASK (0x40U)
3041 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME2_REACH_INTR_SHIFT (6U)
3042 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME2_REACH_INTR_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME2_REACH_INTR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME2_REACH_INTR_SHIFT)
3043 
3044 /*
3045  * TARGET_TIME1_CFG_ERR (RO)
3046  *
3047  * target time1 configure error
3048  */
3049 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME1_CFG_ERR_MASK (0x20U)
3050 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME1_CFG_ERR_SHIFT (5U)
3051 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME1_CFG_ERR_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME1_CFG_ERR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME1_CFG_ERR_SHIFT)
3052 
3053 /*
3054  * TARGET_TIME1_REACH_INTR (RC)
3055  *
3056  * target time1 reached
3057  */
3058 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME1_REACH_INTR_MASK (0x10U)
3059 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME1_REACH_INTR_SHIFT (4U)
3060 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME1_REACH_INTR_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME1_REACH_INTR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME1_REACH_INTR_SHIFT)
3061 
3062 /*
3063  * TARGET_TIME0_CFG_ERR (RO)
3064  *
3065  * target time0 configure error
3066  */
3067 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME0_CFG_ERR_MASK (0x8U)
3068 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME0_CFG_ERR_SHIFT (3U)
3069 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME0_CFG_ERR_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME0_CFG_ERR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME0_CFG_ERR_SHIFT)
3070 
3071 /*
3072  * PTP_FIFO_WR_INTR (RC)
3073  *
3074  * auxiliary timestamp trigger snapshot
3075  */
3076 #define TSW_PTP_EVT_TMR_STS_PTP_FIFO_WR_INTR_MASK (0x4U)
3077 #define TSW_PTP_EVT_TMR_STS_PTP_FIFO_WR_INTR_SHIFT (2U)
3078 #define TSW_PTP_EVT_TMR_STS_PTP_FIFO_WR_INTR_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_PTP_FIFO_WR_INTR_MASK) >> TSW_PTP_EVT_TMR_STS_PTP_FIFO_WR_INTR_SHIFT)
3079 
3080 /*
3081  * TARGET_TIME0_REACH_INTR (RC)
3082  *
3083  * target time0 reached
3084  */
3085 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME0_REACH_INTR_MASK (0x2U)
3086 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME0_REACH_INTR_SHIFT (1U)
3087 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME0_REACH_INTR_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME0_REACH_INTR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME0_REACH_INTR_SHIFT)
3088 
3089 /* Bitfield definition for register: PTP_EVT_PPS_CMD */
3090 /*
3091  * PPS_MODE3 (RW)
3092  *
3093  * Target Time Register Mode for PPS3 Output
3094  */
3095 #define TSW_PTP_EVT_PPS_CMD_PPS_MODE3_MASK (0x60000000UL)
3096 #define TSW_PTP_EVT_PPS_CMD_PPS_MODE3_SHIFT (29U)
3097 #define TSW_PTP_EVT_PPS_CMD_PPS_MODE3_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_MODE3_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_MODE3_MASK)
3098 #define TSW_PTP_EVT_PPS_CMD_PPS_MODE3_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_MODE3_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_MODE3_SHIFT)
3099 
3100 /*
3101  * PPS_CMD3 (RW)
3102  *
3103  * pps3 command
3104  */
3105 #define TSW_PTP_EVT_PPS_CMD_PPS_CMD3_MASK (0x7000000UL)
3106 #define TSW_PTP_EVT_PPS_CMD_PPS_CMD3_SHIFT (24U)
3107 #define TSW_PTP_EVT_PPS_CMD_PPS_CMD3_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_CMD3_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_CMD3_MASK)
3108 #define TSW_PTP_EVT_PPS_CMD_PPS_CMD3_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_CMD3_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_CMD3_SHIFT)
3109 
3110 /*
3111  * PPS_MODE2 (RW)
3112  *
3113  * Target Time Register Mode for PPS2 Output
3114  */
3115 #define TSW_PTP_EVT_PPS_CMD_PPS_MODE2_MASK (0x600000UL)
3116 #define TSW_PTP_EVT_PPS_CMD_PPS_MODE2_SHIFT (21U)
3117 #define TSW_PTP_EVT_PPS_CMD_PPS_MODE2_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_MODE2_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_MODE2_MASK)
3118 #define TSW_PTP_EVT_PPS_CMD_PPS_MODE2_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_MODE2_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_MODE2_SHIFT)
3119 
3120 /*
3121  * PPS_CMD2 (RW)
3122  *
3123  * pps2 command
3124  */
3125 #define TSW_PTP_EVT_PPS_CMD_PPS_CMD2_MASK (0x70000UL)
3126 #define TSW_PTP_EVT_PPS_CMD_PPS_CMD2_SHIFT (16U)
3127 #define TSW_PTP_EVT_PPS_CMD_PPS_CMD2_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_CMD2_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_CMD2_MASK)
3128 #define TSW_PTP_EVT_PPS_CMD_PPS_CMD2_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_CMD2_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_CMD2_SHIFT)
3129 
3130 /*
3131  * PPS_MODE1 (RW)
3132  *
3133  * Target Time Register Mode for PPS1 Output
3134  */
3135 #define TSW_PTP_EVT_PPS_CMD_PPS_MODE1_MASK (0x6000U)
3136 #define TSW_PTP_EVT_PPS_CMD_PPS_MODE1_SHIFT (13U)
3137 #define TSW_PTP_EVT_PPS_CMD_PPS_MODE1_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_MODE1_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_MODE1_MASK)
3138 #define TSW_PTP_EVT_PPS_CMD_PPS_MODE1_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_MODE1_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_MODE1_SHIFT)
3139 
3140 /*
3141  * PPS_CMD1 (RW)
3142  *
3143  * pps1 command
3144  */
3145 #define TSW_PTP_EVT_PPS_CMD_PPS_CMD1_MASK (0x700U)
3146 #define TSW_PTP_EVT_PPS_CMD_PPS_CMD1_SHIFT (8U)
3147 #define TSW_PTP_EVT_PPS_CMD_PPS_CMD1_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_CMD1_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_CMD1_MASK)
3148 #define TSW_PTP_EVT_PPS_CMD_PPS_CMD1_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_CMD1_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_CMD1_SHIFT)
3149 
3150 /*
3151  * PPS_MODE0 (RW)
3152  *
3153  * Target Time Register Mode for PPS0 Output
3154  */
3155 #define TSW_PTP_EVT_PPS_CMD_PPS_MODE0_MASK (0x60U)
3156 #define TSW_PTP_EVT_PPS_CMD_PPS_MODE0_SHIFT (5U)
3157 #define TSW_PTP_EVT_PPS_CMD_PPS_MODE0_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_MODE0_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_MODE0_MASK)
3158 #define TSW_PTP_EVT_PPS_CMD_PPS_MODE0_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_MODE0_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_MODE0_SHIFT)
3159 
3160 /*
3161  * PPS_EN0 (RW)
3162  *
3163  * flexible PPS0 output mode enable
3164  */
3165 #define TSW_PTP_EVT_PPS_CMD_PPS_EN0_MASK (0x10U)
3166 #define TSW_PTP_EVT_PPS_CMD_PPS_EN0_SHIFT (4U)
3167 #define TSW_PTP_EVT_PPS_CMD_PPS_EN0_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_EN0_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_EN0_MASK)
3168 #define TSW_PTP_EVT_PPS_CMD_PPS_EN0_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_EN0_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_EN0_SHIFT)
3169 
3170 /*
3171  * PPS_CMD0 (RW)
3172  *
3173  * pps0 command
3174  */
3175 #define TSW_PTP_EVT_PPS_CMD_PPS_CMD0_MASK (0xFU)
3176 #define TSW_PTP_EVT_PPS_CMD_PPS_CMD0_SHIFT (0U)
3177 #define TSW_PTP_EVT_PPS_CMD_PPS_CMD0_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_CMD0_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_CMD0_MASK)
3178 #define TSW_PTP_EVT_PPS_CMD_PPS_CMD0_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_CMD0_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_CMD0_SHIFT)
3179 
3180 /* Bitfield definition for register: PTP_EVT_ATSLO */
3181 /*
3182  * STSLO (RO)
3183  *
3184  * auxiliary fifo read sub seconds info
3185  */
3186 #define TSW_PTP_EVT_ATSLO_STSLO_MASK (0x7FFFFFFFUL)
3187 #define TSW_PTP_EVT_ATSLO_STSLO_SHIFT (0U)
3188 #define TSW_PTP_EVT_ATSLO_STSLO_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_ATSLO_STSLO_MASK) >> TSW_PTP_EVT_ATSLO_STSLO_SHIFT)
3189 
3190 /* Bitfield definition for register: PTP_EVT_ATSHI */
3191 /*
3192  * STSHI (RO)
3193  *
3194  * auxiliary fifo read seconds info
3195  */
3196 #define TSW_PTP_EVT_ATSHI_STSHI_MASK (0xFFFFFFFFUL)
3197 #define TSW_PTP_EVT_ATSHI_STSHI_SHIFT (0U)
3198 #define TSW_PTP_EVT_ATSHI_STSHI_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_ATSHI_STSHI_MASK) >> TSW_PTP_EVT_ATSHI_STSHI_SHIFT)
3199 
3200 /* Bitfield definition for register: PTP_EVT_PPS0_INTERVAL */
3201 /*
3202  * PPSINT (RW)
3203  *
3204  * PPS0 output signal interval
3205  */
3206 #define TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_MASK (0xFFFFFFFFUL)
3207 #define TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_SHIFT (0U)
3208 #define TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_SHIFT) & TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_MASK)
3209 #define TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_MASK) >> TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_SHIFT)
3210 
3211 /* Bitfield definition for register: PTP_EVT_PPS0_WIDTH */
3212 /*
3213  * PPS_WIDTH (RW)
3214  *
3215  * pps0 output signal width
3216  */
3217 #define TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_MASK (0xFFFFFFFFUL)
3218 #define TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_SHIFT (0U)
3219 #define TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_SHIFT) & TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_MASK)
3220 #define TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_MASK) >> TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_SHIFT)
3221 
3222 /* Bitfield definition for register: PTP_EVT_SCP_SEC1 */
3223 /*
3224  * SCP_SEC (RW)
3225  *
3226  * target time seconds
3227  */
3228 #define TSW_PTP_EVT_SCP_SEC1_SCP_SEC_MASK (0xFFFFFFFFUL)
3229 #define TSW_PTP_EVT_SCP_SEC1_SCP_SEC_SHIFT (0U)
3230 #define TSW_PTP_EVT_SCP_SEC1_SCP_SEC_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_SCP_SEC1_SCP_SEC_SHIFT) & TSW_PTP_EVT_SCP_SEC1_SCP_SEC_MASK)
3231 #define TSW_PTP_EVT_SCP_SEC1_SCP_SEC_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_SCP_SEC1_SCP_SEC_MASK) >> TSW_PTP_EVT_SCP_SEC1_SCP_SEC_SHIFT)
3232 
3233 /* Bitfield definition for register: PTP_EVT_SCP_NS1 */
3234 /*
3235  * SCP_NS (RW)
3236  *
3237  * target time sub seconds
3238  */
3239 #define TSW_PTP_EVT_SCP_NS1_SCP_NS_MASK (0x3FFFFFFFUL)
3240 #define TSW_PTP_EVT_SCP_NS1_SCP_NS_SHIFT (0U)
3241 #define TSW_PTP_EVT_SCP_NS1_SCP_NS_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_SCP_NS1_SCP_NS_SHIFT) & TSW_PTP_EVT_SCP_NS1_SCP_NS_MASK)
3242 #define TSW_PTP_EVT_SCP_NS1_SCP_NS_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_SCP_NS1_SCP_NS_MASK) >> TSW_PTP_EVT_SCP_NS1_SCP_NS_SHIFT)
3243 
3244 /* Bitfield definition for register: PTP_EVT_PPS1_INTERVAL */
3245 /*
3246  * PPSINT (RW)
3247  *
3248  * PPS1 output signal interval
3249  */
3250 #define TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_MASK (0xFFFFFFFFUL)
3251 #define TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_SHIFT (0U)
3252 #define TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_SHIFT) & TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_MASK)
3253 #define TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_MASK) >> TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_SHIFT)
3254 
3255 /* Bitfield definition for register: PTP_EVT_PPS1_WIDTH */
3256 /*
3257  * PPS_WIDTH (RW)
3258  *
3259  * pps1 output signal width
3260  */
3261 #define TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_MASK (0xFFFFFFFFUL)
3262 #define TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_SHIFT (0U)
3263 #define TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_SHIFT) & TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_MASK)
3264 #define TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_MASK) >> TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_SHIFT)
3265 
3266 /* Bitfield definition for register: PTP_EVT_SCP_SEC2 */
3267 /*
3268  * SCP_SEC (RW)
3269  *
3270  * target time seconds
3271  */
3272 #define TSW_PTP_EVT_SCP_SEC2_SCP_SEC_MASK (0xFFFFFFFFUL)
3273 #define TSW_PTP_EVT_SCP_SEC2_SCP_SEC_SHIFT (0U)
3274 #define TSW_PTP_EVT_SCP_SEC2_SCP_SEC_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_SCP_SEC2_SCP_SEC_SHIFT) & TSW_PTP_EVT_SCP_SEC2_SCP_SEC_MASK)
3275 #define TSW_PTP_EVT_SCP_SEC2_SCP_SEC_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_SCP_SEC2_SCP_SEC_MASK) >> TSW_PTP_EVT_SCP_SEC2_SCP_SEC_SHIFT)
3276 
3277 /* Bitfield definition for register: PTP_EVT_SCP_NS2 */
3278 /*
3279  * SCP_NS (RW)
3280  *
3281  * target time sub seconds
3282  */
3283 #define TSW_PTP_EVT_SCP_NS2_SCP_NS_MASK (0x3FFFFFFFUL)
3284 #define TSW_PTP_EVT_SCP_NS2_SCP_NS_SHIFT (0U)
3285 #define TSW_PTP_EVT_SCP_NS2_SCP_NS_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_SCP_NS2_SCP_NS_SHIFT) & TSW_PTP_EVT_SCP_NS2_SCP_NS_MASK)
3286 #define TSW_PTP_EVT_SCP_NS2_SCP_NS_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_SCP_NS2_SCP_NS_MASK) >> TSW_PTP_EVT_SCP_NS2_SCP_NS_SHIFT)
3287 
3288 /* Bitfield definition for register: PTP_EVT_PPS2_INTERVAL */
3289 /*
3290  * PPSINT (RW)
3291  *
3292  * PPS2 output signal interval
3293  */
3294 #define TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_MASK (0xFFFFFFFFUL)
3295 #define TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_SHIFT (0U)
3296 #define TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_SHIFT) & TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_MASK)
3297 #define TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_MASK) >> TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_SHIFT)
3298 
3299 /* Bitfield definition for register: PTP_EVT_PPS2_WIDTH */
3300 /*
3301  * PPS_WIDTH (RW)
3302  *
3303  * pps2 output signal width
3304  */
3305 #define TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_MASK (0xFFFFFFFFUL)
3306 #define TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_SHIFT (0U)
3307 #define TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_SHIFT) & TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_MASK)
3308 #define TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_MASK) >> TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_SHIFT)
3309 
3310 /* Bitfield definition for register: PTP_EVT_SCP_SEC3 */
3311 /*
3312  * SCP_SEC (RW)
3313  *
3314  * target time seconds
3315  */
3316 #define TSW_PTP_EVT_SCP_SEC3_SCP_SEC_MASK (0xFFFFFFFFUL)
3317 #define TSW_PTP_EVT_SCP_SEC3_SCP_SEC_SHIFT (0U)
3318 #define TSW_PTP_EVT_SCP_SEC3_SCP_SEC_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_SCP_SEC3_SCP_SEC_SHIFT) & TSW_PTP_EVT_SCP_SEC3_SCP_SEC_MASK)
3319 #define TSW_PTP_EVT_SCP_SEC3_SCP_SEC_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_SCP_SEC3_SCP_SEC_MASK) >> TSW_PTP_EVT_SCP_SEC3_SCP_SEC_SHIFT)
3320 
3321 /* Bitfield definition for register: PTP_EVT_SCP_NS3 */
3322 /*
3323  * SCP_NS (RW)
3324  *
3325  * target time sub seconds
3326  */
3327 #define TSW_PTP_EVT_SCP_NS3_SCP_NS_MASK (0x3FFFFFFFUL)
3328 #define TSW_PTP_EVT_SCP_NS3_SCP_NS_SHIFT (0U)
3329 #define TSW_PTP_EVT_SCP_NS3_SCP_NS_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_SCP_NS3_SCP_NS_SHIFT) & TSW_PTP_EVT_SCP_NS3_SCP_NS_MASK)
3330 #define TSW_PTP_EVT_SCP_NS3_SCP_NS_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_SCP_NS3_SCP_NS_MASK) >> TSW_PTP_EVT_SCP_NS3_SCP_NS_SHIFT)
3331 
3332 /* Bitfield definition for register: PTP_EVT_PPS3_INTERVAL */
3333 /*
3334  * PPSINT (RW)
3335  *
3336  * PPS3 output signal interval
3337  */
3338 #define TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_MASK (0xFFFFFFFFUL)
3339 #define TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_SHIFT (0U)
3340 #define TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_SHIFT) & TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_MASK)
3341 #define TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_MASK) >> TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_SHIFT)
3342 
3343 /* Bitfield definition for register: PTP_EVT_PPS3_WIDTH */
3344 /*
3345  * PPS_WIDTH (RW)
3346  *
3347  * pps3 output signal width
3348  */
3349 #define TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_MASK (0xFFFFFFFFUL)
3350 #define TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_SHIFT (0U)
3351 #define TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_SHIFT) & TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_MASK)
3352 #define TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_MASK) >> TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_SHIFT)
3353 
3354 /* Bitfield definition for register: PTP_EVT_PPS_CTRL0 */
3355 /*
3356  * PPS_TOD_INTR_MSK (RW)
3357  *
3358  * pps tod interrupt enable
3359  */
3360 #define TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_MASK (0x8U)
3361 #define TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_SHIFT (3U)
3362 #define TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_SHIFT) & TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_MASK)
3363 #define TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_MASK) >> TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_SHIFT)
3364 
3365 /*
3366  * TARGET_RAC_INTR_MSK (RW)
3367  *
3368  * target timmer interrupt mask
3369  */
3370 #define TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_MASK (0x4U)
3371 #define TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_SHIFT (2U)
3372 #define TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_SHIFT) & TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_MASK)
3373 #define TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_MASK) >> TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_SHIFT)
3374 
3375 /*
3376  * FIFO_WR_INTR_MSK (RW)
3377  *
3378  * auxiliary snapshot fifo write interrupt enable
3379  */
3380 #define TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_MASK (0x2U)
3381 #define TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_SHIFT (1U)
3382 #define TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_SHIFT) & TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_MASK)
3383 #define TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_MASK) >> TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_SHIFT)
3384 
3385 /*
3386  * TIME_SEL (RW)
3387  *
3388  * timer selection
3389  */
3390 #define TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_MASK (0x1U)
3391 #define TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_SHIFT (0U)
3392 #define TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_SHIFT) & TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_MASK)
3393 #define TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_MASK) >> TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_SHIFT)
3394 
3395 /* Bitfield definition for register: PTP_EVT_PPS_SEL */
3396 /*
3397  * PPS3_SEL (RW)
3398  *
3399  * pps selection for pps3
3400  */
3401 #define TSW_PTP_EVT_PPS_SEL_PPS3_SEL_MASK (0x1F000000UL)
3402 #define TSW_PTP_EVT_PPS_SEL_PPS3_SEL_SHIFT (24U)
3403 #define TSW_PTP_EVT_PPS_SEL_PPS3_SEL_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_SEL_PPS3_SEL_SHIFT) & TSW_PTP_EVT_PPS_SEL_PPS3_SEL_MASK)
3404 #define TSW_PTP_EVT_PPS_SEL_PPS3_SEL_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_SEL_PPS3_SEL_MASK) >> TSW_PTP_EVT_PPS_SEL_PPS3_SEL_SHIFT)
3405 
3406 /*
3407  * PPS2_SEL (RW)
3408  *
3409  * pps selection for pps2
3410  */
3411 #define TSW_PTP_EVT_PPS_SEL_PPS2_SEL_MASK (0x1F0000UL)
3412 #define TSW_PTP_EVT_PPS_SEL_PPS2_SEL_SHIFT (16U)
3413 #define TSW_PTP_EVT_PPS_SEL_PPS2_SEL_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_SEL_PPS2_SEL_SHIFT) & TSW_PTP_EVT_PPS_SEL_PPS2_SEL_MASK)
3414 #define TSW_PTP_EVT_PPS_SEL_PPS2_SEL_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_SEL_PPS2_SEL_MASK) >> TSW_PTP_EVT_PPS_SEL_PPS2_SEL_SHIFT)
3415 
3416 /*
3417  * PPS1_SEL (RW)
3418  *
3419  * pps selection for pps1
3420  */
3421 #define TSW_PTP_EVT_PPS_SEL_PPS1_SEL_MASK (0x1F00U)
3422 #define TSW_PTP_EVT_PPS_SEL_PPS1_SEL_SHIFT (8U)
3423 #define TSW_PTP_EVT_PPS_SEL_PPS1_SEL_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_SEL_PPS1_SEL_SHIFT) & TSW_PTP_EVT_PPS_SEL_PPS1_SEL_MASK)
3424 #define TSW_PTP_EVT_PPS_SEL_PPS1_SEL_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_SEL_PPS1_SEL_MASK) >> TSW_PTP_EVT_PPS_SEL_PPS1_SEL_SHIFT)
3425 
3426 /*
3427  * PPS0_SEL (RW)
3428  *
3429  * pps selection for pps0
3430  */
3431 #define TSW_PTP_EVT_PPS_SEL_PPS0_SEL_MASK (0x1FU)
3432 #define TSW_PTP_EVT_PPS_SEL_PPS0_SEL_SHIFT (0U)
3433 #define TSW_PTP_EVT_PPS_SEL_PPS0_SEL_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_SEL_PPS0_SEL_SHIFT) & TSW_PTP_EVT_PPS_SEL_PPS0_SEL_MASK)
3434 #define TSW_PTP_EVT_PPS_SEL_PPS0_SEL_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_SEL_PPS0_SEL_MASK) >> TSW_PTP_EVT_PPS_SEL_PPS0_SEL_SHIFT)
3435 
3436 /* Bitfield definition for register: SOFT_RST_CTRL */
3437 /*
3438  * TSN_CORE_RST (RW)
3439  *
3440  * tsn core reset control
3441  */
3442 #define TSW_SOFT_RST_CTRL_TSN_CORE_RST_MASK (0x800U)
3443 #define TSW_SOFT_RST_CTRL_TSN_CORE_RST_SHIFT (11U)
3444 #define TSW_SOFT_RST_CTRL_TSN_CORE_RST_SET(x) (((uint32_t)(x) << TSW_SOFT_RST_CTRL_TSN_CORE_RST_SHIFT) & TSW_SOFT_RST_CTRL_TSN_CORE_RST_MASK)
3445 #define TSW_SOFT_RST_CTRL_TSN_CORE_RST_GET(x) (((uint32_t)(x) & TSW_SOFT_RST_CTRL_TSN_CORE_RST_MASK) >> TSW_SOFT_RST_CTRL_TSN_CORE_RST_SHIFT)
3446 
3447 /*
3448  * PTP_EVT_RST (RW)
3449  *
3450  * ptp event module reset control
3451  */
3452 #define TSW_SOFT_RST_CTRL_PTP_EVT_RST_MASK (0x400U)
3453 #define TSW_SOFT_RST_CTRL_PTP_EVT_RST_SHIFT (10U)
3454 #define TSW_SOFT_RST_CTRL_PTP_EVT_RST_SET(x) (((uint32_t)(x) << TSW_SOFT_RST_CTRL_PTP_EVT_RST_SHIFT) & TSW_SOFT_RST_CTRL_PTP_EVT_RST_MASK)
3455 #define TSW_SOFT_RST_CTRL_PTP_EVT_RST_GET(x) (((uint32_t)(x) & TSW_SOFT_RST_CTRL_PTP_EVT_RST_MASK) >> TSW_SOFT_RST_CTRL_PTP_EVT_RST_SHIFT)
3456 
3457 /*
3458  * DMA0_RST (RW)
3459  *
3460  * dma0 reset control
3461  */
3462 #define TSW_SOFT_RST_CTRL_DMA0_RST_MASK (0x100U)
3463 #define TSW_SOFT_RST_CTRL_DMA0_RST_SHIFT (8U)
3464 #define TSW_SOFT_RST_CTRL_DMA0_RST_SET(x) (((uint32_t)(x) << TSW_SOFT_RST_CTRL_DMA0_RST_SHIFT) & TSW_SOFT_RST_CTRL_DMA0_RST_MASK)
3465 #define TSW_SOFT_RST_CTRL_DMA0_RST_GET(x) (((uint32_t)(x) & TSW_SOFT_RST_CTRL_DMA0_RST_MASK) >> TSW_SOFT_RST_CTRL_DMA0_RST_SHIFT)
3466 
3467 /*
3468  * PORT3_RX_RST (RW)
3469  *
3470  * port3 rx reset control
3471  */
3472 #define TSW_SOFT_RST_CTRL_PORT3_RX_RST_MASK (0x20U)
3473 #define TSW_SOFT_RST_CTRL_PORT3_RX_RST_SHIFT (5U)
3474 #define TSW_SOFT_RST_CTRL_PORT3_RX_RST_SET(x) (((uint32_t)(x) << TSW_SOFT_RST_CTRL_PORT3_RX_RST_SHIFT) & TSW_SOFT_RST_CTRL_PORT3_RX_RST_MASK)
3475 #define TSW_SOFT_RST_CTRL_PORT3_RX_RST_GET(x) (((uint32_t)(x) & TSW_SOFT_RST_CTRL_PORT3_RX_RST_MASK) >> TSW_SOFT_RST_CTRL_PORT3_RX_RST_SHIFT)
3476 
3477 /*
3478  * PORT3_TX_RST (RW)
3479  *
3480  * port3 tx reset control
3481  */
3482 #define TSW_SOFT_RST_CTRL_PORT3_TX_RST_MASK (0x10U)
3483 #define TSW_SOFT_RST_CTRL_PORT3_TX_RST_SHIFT (4U)
3484 #define TSW_SOFT_RST_CTRL_PORT3_TX_RST_SET(x) (((uint32_t)(x) << TSW_SOFT_RST_CTRL_PORT3_TX_RST_SHIFT) & TSW_SOFT_RST_CTRL_PORT3_TX_RST_MASK)
3485 #define TSW_SOFT_RST_CTRL_PORT3_TX_RST_GET(x) (((uint32_t)(x) & TSW_SOFT_RST_CTRL_PORT3_TX_RST_MASK) >> TSW_SOFT_RST_CTRL_PORT3_TX_RST_SHIFT)
3486 
3487 /*
3488  * PORT2_RX_RST (RW)
3489  *
3490  * port2 rx reset control
3491  */
3492 #define TSW_SOFT_RST_CTRL_PORT2_RX_RST_MASK (0x8U)
3493 #define TSW_SOFT_RST_CTRL_PORT2_RX_RST_SHIFT (3U)
3494 #define TSW_SOFT_RST_CTRL_PORT2_RX_RST_SET(x) (((uint32_t)(x) << TSW_SOFT_RST_CTRL_PORT2_RX_RST_SHIFT) & TSW_SOFT_RST_CTRL_PORT2_RX_RST_MASK)
3495 #define TSW_SOFT_RST_CTRL_PORT2_RX_RST_GET(x) (((uint32_t)(x) & TSW_SOFT_RST_CTRL_PORT2_RX_RST_MASK) >> TSW_SOFT_RST_CTRL_PORT2_RX_RST_SHIFT)
3496 
3497 /*
3498  * PORT2_TX_RST (RW)
3499  *
3500  * port2 tx reset control
3501  */
3502 #define TSW_SOFT_RST_CTRL_PORT2_TX_RST_MASK (0x4U)
3503 #define TSW_SOFT_RST_CTRL_PORT2_TX_RST_SHIFT (2U)
3504 #define TSW_SOFT_RST_CTRL_PORT2_TX_RST_SET(x) (((uint32_t)(x) << TSW_SOFT_RST_CTRL_PORT2_TX_RST_SHIFT) & TSW_SOFT_RST_CTRL_PORT2_TX_RST_MASK)
3505 #define TSW_SOFT_RST_CTRL_PORT2_TX_RST_GET(x) (((uint32_t)(x) & TSW_SOFT_RST_CTRL_PORT2_TX_RST_MASK) >> TSW_SOFT_RST_CTRL_PORT2_TX_RST_SHIFT)
3506 
3507 /*
3508  * PORT1_RX_RST (RW)
3509  *
3510  * port1 rx reset control
3511  */
3512 #define TSW_SOFT_RST_CTRL_PORT1_RX_RST_MASK (0x2U)
3513 #define TSW_SOFT_RST_CTRL_PORT1_RX_RST_SHIFT (1U)
3514 #define TSW_SOFT_RST_CTRL_PORT1_RX_RST_SET(x) (((uint32_t)(x) << TSW_SOFT_RST_CTRL_PORT1_RX_RST_SHIFT) & TSW_SOFT_RST_CTRL_PORT1_RX_RST_MASK)
3515 #define TSW_SOFT_RST_CTRL_PORT1_RX_RST_GET(x) (((uint32_t)(x) & TSW_SOFT_RST_CTRL_PORT1_RX_RST_MASK) >> TSW_SOFT_RST_CTRL_PORT1_RX_RST_SHIFT)
3516 
3517 /*
3518  * PORT1_TX_RST (RW)
3519  *
3520  * port1 tx reset control
3521  */
3522 #define TSW_SOFT_RST_CTRL_PORT1_TX_RST_MASK (0x1U)
3523 #define TSW_SOFT_RST_CTRL_PORT1_TX_RST_SHIFT (0U)
3524 #define TSW_SOFT_RST_CTRL_PORT1_TX_RST_SET(x) (((uint32_t)(x) << TSW_SOFT_RST_CTRL_PORT1_TX_RST_SHIFT) & TSW_SOFT_RST_CTRL_PORT1_TX_RST_MASK)
3525 #define TSW_SOFT_RST_CTRL_PORT1_TX_RST_GET(x) (((uint32_t)(x) & TSW_SOFT_RST_CTRL_PORT1_TX_RST_MASK) >> TSW_SOFT_RST_CTRL_PORT1_TX_RST_SHIFT)
3526 
3527 /* Bitfield definition for register: CPU_PORT_PORT_MAIN_TAGGING */
3528 /*
3529  * FORCE (R/W)
3530  *
3531  * The VLAN-TAG with PVID will be inserted in every frame from Host as their first VLAN-TAG. This can be used for double tagging of tagged/trunk ports
3532  */
3533 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_MASK (0x20000UL)
3534 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_SHIFT (17U)
3535 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_SHIFT) & TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_MASK)
3536 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_MASK) >> TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_SHIFT)
3537 
3538 /*
3539  * ACCESS (R/W)
3540  *
3541  * Every tagged frame not matching PVID is filtered out. Every untagged ingress frame will be tagged with PVID. Every egress frame with PVID will be untagged
3542  */
3543 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_MASK (0x10000UL)
3544 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_SHIFT (16U)
3545 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_SHIFT) & TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_MASK)
3546 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_MASK) >> TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_SHIFT)
3547 
3548 /*
3549  * PCP (R/W)
3550  *
3551  * VLAN-TCI: Priority Code Point, used when tagged.
3552  */
3553 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_MASK (0xE000U)
3554 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_SHIFT (13U)
3555 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_SHIFT) & TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_MASK)
3556 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_MASK) >> TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_SHIFT)
3557 
3558 /*
3559  * DEI (R/W)
3560  *
3561  * VLAN-TCI: Drop Eligible Indicator, used when tagged.
3562  */
3563 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_MASK (0x1000U)
3564 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_SHIFT (12U)
3565 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_SHIFT) & TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_MASK)
3566 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_MASK) >> TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_SHIFT)
3567 
3568 /*
3569  * PVID (R/W)
3570  *
3571  * Native VLAN of Port. Untagged traffic will be tagged with the native VLAN-ID By default the Port uses VLAN 1.
3572  */
3573 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_MASK (0xFFFU)
3574 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_SHIFT (0U)
3575 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_SHIFT) & TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_MASK)
3576 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_MASK) >> TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_SHIFT)
3577 
3578 /* Bitfield definition for register: CPU_PORT_PORT_MAIN_ENNABLE */
3579 /*
3580  * EN_SF (R/W)
3581  *
3582  * only applicable for CPU-Port at egress: '1' to use S&F FIFO and '0' disable S&F FIFO. Changing during frame operation can lead to frame corruption
3583  */
3584 #define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_MASK (0x2U)
3585 #define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_SHIFT (1U)
3586 #define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_SHIFT) & TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_MASK)
3587 #define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_MASK) >> TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_SHIFT)
3588 
3589 /*
3590  * EN_QCI (R/W)
3591  *
3592  * if QCI is present at selected egress port, '1' to use QCI and '0' disable QCI. Changing during frame operation can lead to frame corruption.
3593  */
3594 #define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_MASK (0x1U)
3595 #define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_SHIFT (0U)
3596 #define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_SHIFT) & TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_MASK)
3597 #define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_MASK) >> TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_SHIFT)
3598 
3599 /* Bitfield definition for register: CPU_PORT_EGRESS_STMID_ESELECT */
3600 /*
3601  * ESEL (RW)
3602  *
3603  * Select entry. Selected entry mapped to 0x40 – 0x5C.
3604  */
3605 #define TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_MASK (0xFFU)
3606 #define TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_SHIFT (0U)
3607 #define TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_MASK)
3608 #define TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_MASK) >> TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_SHIFT)
3609 
3610 /* Bitfield definition for register: CPU_PORT_EGRESS_STMID_CONTROL */
3611 /*
3612  * SID (R/W)
3613  *
3614  * Stream ID – inserted to header on match
3615  */
3616 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_MASK (0xFF00U)
3617 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_SHIFT (8U)
3618 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_MASK)
3619 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_MASK) >> TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_SHIFT)
3620 
3621 /*
3622  * SEQGEN (R/W)
3623  *
3624  * Sequence number generation enable
3625  */
3626 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_MASK (0x80U)
3627 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_SHIFT (7U)
3628 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_MASK)
3629 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_MASK) >> TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_SHIFT)
3630 
3631 /*
3632  * ACTCTL (R/W)
3633  *
3634  * Active Destination MAC – control. See Table 6-6.
3635  */
3636 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_MASK (0x30U)
3637 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_SHIFT (4U)
3638 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_MASK)
3639 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_MASK) >> TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_SHIFT)
3640 
3641 /*
3642  * SMAC (R/W)
3643  *
3644  * 0: Lookup by Destination MAC 1: Lookup by Source MAC
3645  */
3646 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_MASK (0x8U)
3647 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_SHIFT (3U)
3648 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_MASK)
3649 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_MASK) >> TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_SHIFT)
3650 
3651 /*
3652  * MODE (R/W)
3653  *
3654  * Lookup mode. 1:Priority – a frame must be untagged or priority tagged ; 2:Tagged – a frame must have a VLAN tag ; 3:All – a frame can be tagged or untagged
3655  */
3656 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_MASK (0x6U)
3657 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_SHIFT (1U)
3658 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_MASK)
3659 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_MASK) >> TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_SHIFT)
3660 
3661 /*
3662  * EN (R/W)
3663  *
3664  * Enable entry
3665  */
3666 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_MASK (0x1U)
3667 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_SHIFT (0U)
3668 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_MASK)
3669 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_MASK) >> TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_SHIFT)
3670 
3671 /* Bitfield definition for register: CPU_PORT_EGRESS_STMID_SEQNO */
3672 /*
3673  * SEQNO (R/WC)
3674  *
3675  * Sequence number – next number when generating,any write access to clear.
3676  */
3677 #define TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_MASK (0xFFFFU)
3678 #define TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_SHIFT (0U)
3679 #define TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_MASK)
3680 #define TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_MASK) >> TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_SHIFT)
3681 
3682 /* Bitfield definition for register: CPU_PORT_EGRESS_STMID_MATCHCNT */
3683 /*
3684  * MATCH (R/WC)
3685  *
3686  * Entry match counter – any write access to clear.
3687  */
3688 #define TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_MASK (0xFFFFFFFFUL)
3689 #define TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_SHIFT (0U)
3690 #define TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_MASK)
3691 #define TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_MASK) >> TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_SHIFT)
3692 
3693 /* Bitfield definition for register: CPU_PORT_EGRESS_STMID_MACLO */
3694 /*
3695  * MACL (R/WC)
3696  *
3697  * MAC-Address [31:0] used by lookup.
3698  */
3699 #define TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_MASK (0xFFFFFFFFUL)
3700 #define TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_SHIFT (0U)
3701 #define TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_MASK)
3702 #define TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_MASK) >> TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_SHIFT)
3703 
3704 /* Bitfield definition for register: CPU_PORT_EGRESS_STMID_MACHI */
3705 /*
3706  * VID (R/W)
3707  *
3708  * VLAN ID used by lookup.
3709  */
3710 #define TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_MASK (0xFFF0000UL)
3711 #define TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_SHIFT (16U)
3712 #define TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_MASK)
3713 #define TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_MASK) >> TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_SHIFT)
3714 
3715 /*
3716  * MATCH (R/W)
3717  *
3718  * MAC-Address [47:31] used by lookup.
3719  */
3720 #define TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_MASK (0xFFFFU)
3721 #define TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_SHIFT (0U)
3722 #define TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_MASK)
3723 #define TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_MASK) >> TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_SHIFT)
3724 
3725 /* Bitfield definition for register: CPU_PORT_EGRESS_STMID_AMACLO */
3726 /*
3727  * AMACL (R/W)
3728  *
3729  * Active Destination MAC, MAC-Address [31:0]
3730  */
3731 #define TSW_CPU_PORT_EGRESS_STMID_AMACLO_AMACL_MASK (0xFFFFFFFFUL)
3732 #define TSW_CPU_PORT_EGRESS_STMID_AMACLO_AMACL_SHIFT (0U)
3733 #define TSW_CPU_PORT_EGRESS_STMID_AMACLO_AMACL_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_AMACLO_AMACL_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_AMACLO_AMACL_MASK)
3734 #define TSW_CPU_PORT_EGRESS_STMID_AMACLO_AMACL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_AMACLO_AMACL_MASK) >> TSW_CPU_PORT_EGRESS_STMID_AMACLO_AMACL_SHIFT)
3735 
3736 /* Bitfield definition for register: CPU_PORT_EGRESS_STMID_AMACHI */
3737 /*
3738  * APCP (R/W)
3739  *
3740  * Active Destination MAC, PCP
3741  */
3742 #define TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_MASK (0xF0000000UL)
3743 #define TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_SHIFT (28U)
3744 #define TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_MASK)
3745 #define TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_MASK) >> TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_SHIFT)
3746 
3747 /*
3748  * AVID (R/W)
3749  *
3750  * Active Destination MAC, VLAN ID
3751  */
3752 #define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_MASK (0xFFF0000UL)
3753 #define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_SHIFT (16U)
3754 #define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_MASK)
3755 #define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_MASK) >> TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_SHIFT)
3756 
3757 /*
3758  * AMACH (R/W)
3759  *
3760  * Active Destination MAC, MAC-Address [47:32]
3761  */
3762 #define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_MASK (0xFFFFU)
3763 #define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_SHIFT (0U)
3764 #define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_MASK)
3765 #define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_MASK) >> TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_SHIFT)
3766 
3767 /* Bitfield definition for register: CPU_PORT_EGRESS_FRER_CONTROL */
3768 /*
3769  * LATER (R/WC)
3770  *
3771  * Latent error flag – write 1 to clear
3772  */
3773 #define TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_MASK (0x2U)
3774 #define TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_SHIFT (1U)
3775 #define TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_MASK)
3776 #define TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_MASK) >> TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_SHIFT)
3777 
3778 /*
3779  * RTENC (R/W)
3780  *
3781  * R-TAG encoding enable.
3782  */
3783 #define TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_MASK (0x1U)
3784 #define TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_SHIFT (0U)
3785 #define TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_MASK)
3786 #define TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_MASK) >> TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_SHIFT)
3787 
3788 /* Bitfield definition for register: CPU_PORT_EGRESS_FRER_SIDSEL */
3789 /*
3790  * SID (R/W)
3791  *
3792  * Stream ID selection for host access to IRFUNC and SRFUNC.
3793  */
3794 #define TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_MASK (0xFFU)
3795 #define TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_SHIFT (0U)
3796 #define TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_MASK)
3797 #define TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_MASK) >> TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_SHIFT)
3798 
3799 /* Bitfield definition for register: CPU_PORT_EGRESS_FRER_IRFUNC */
3800 /*
3801  * FEN (R/W)
3802  *
3803  * Individual recovery function: FEN – enable function for stream SIDSEL.SID. FIDX – function index for stream SIDSEL.SID If function does not exists (FIDX >= 2**FD), FEN will be set to 0.
3804  */
3805 #define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_MASK (0x80000000UL)
3806 #define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_SHIFT (31U)
3807 #define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_MASK)
3808 #define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_MASK) >> TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_SHIFT)
3809 
3810 /*
3811  * FIDX (R/W)
3812  *
3813  */
3814 #define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_MASK (0xFFU)
3815 #define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_SHIFT (0U)
3816 #define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_MASK)
3817 #define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_MASK) >> TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_SHIFT)
3818 
3819 /* Bitfield definition for register: CPU_PORT_EGRESS_FRER_SRFUNC */
3820 /*
3821  * FEN (R/W)
3822  *
3823  * Sequence recovery function: FEN – enable function for stream SIDSEL.SID. FIDX – function index for stream SIDSEL.SID If function does not exists (FIDX >= 2**FD), FEN will be set to 0.
3824  */
3825 #define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_MASK (0x80000000UL)
3826 #define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_SHIFT (31U)
3827 #define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_MASK)
3828 #define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_MASK) >> TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_SHIFT)
3829 
3830 /*
3831  * FIDX (R/W)
3832  *
3833  */
3834 #define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_MASK (0xFFU)
3835 #define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_SHIFT (0U)
3836 #define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_MASK)
3837 #define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_MASK) >> TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_SHIFT)
3838 
3839 /* Bitfield definition for register: CPU_PORT_EGRESS_FRER_FSELECT */
3840 /*
3841  * FIDX (R/W)
3842  *
3843  * Recovery function selection for host access at offset 0x140+
3844  */
3845 #define TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_MASK (0xFFU)
3846 #define TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_SHIFT (0U)
3847 #define TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_MASK)
3848 #define TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_SHIFT)
3849 
3850 /* Bitfield definition for register: CPU_PORT_EGRESS_FRER_FCTRL */
3851 /*
3852  * FRSET (WO)
3853  *
3854  * Reset recovery function – self-resetting to 0
3855  */
3856 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_MASK (0x80000000UL)
3857 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_SHIFT (31U)
3858 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_MASK)
3859 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_SHIFT)
3860 
3861 /*
3862  * PATHS (R/W)
3863  *
3864  * Number of paths (used by latent error detection)
3865  */
3866 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_MASK (0xFF0000UL)
3867 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_SHIFT (16U)
3868 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_MASK)
3869 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_SHIFT)
3870 
3871 /*
3872  * HLEN (R/W)
3873  *
3874  * History length (used by Vector recovery algorithm)
3875  */
3876 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_MASK (0x1F00U)
3877 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_SHIFT (8U)
3878 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_MASK)
3879 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_SHIFT)
3880 
3881 /*
3882  * ALGO (R/W)
3883  *
3884  * Recovery function algorithm: 0 – Vector recovery algorithm 1 – Match recovery algorithm
3885  */
3886 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_MASK (0x10U)
3887 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_SHIFT (4U)
3888 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_MASK)
3889 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_SHIFT)
3890 
3891 /*
3892  * LATEN (R/W)
3893  *
3894  * Latent error detection enable
3895  */
3896 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_MASK (0x8U)
3897 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_SHIFT (3U)
3898 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_MASK)
3899 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_SHIFT)
3900 
3901 /*
3902  * IND (R/W)
3903  *
3904  * Individual function (802.1CB 10.4.1.10)
3905  */
3906 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_MASK (0x4U)
3907 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_SHIFT (2U)
3908 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_MASK)
3909 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_SHIFT)
3910 
3911 /*
3912  * TNS (R/W)
3913  *
3914  * TakeNoSequence (802.1CB 10.4.1.9)
3915  */
3916 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_MASK (0x2U)
3917 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_SHIFT (1U)
3918 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_MASK)
3919 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_SHIFT)
3920 
3921 /* Bitfield definition for register: CPU_PORT_EGRESS_FRER_RESETMSEC */
3922 /*
3923  * FSRMS (R/W)
3924  *
3925  * frerSeqRcvyResetMSec (802.1CB 10.4.1.7)
3926  */
3927 #define TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_MASK (0xFFFFFFUL)
3928 #define TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_SHIFT (0U)
3929 #define TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_MASK)
3930 #define TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_MASK) >> TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_SHIFT)
3931 
3932 /* Bitfield definition for register: CPU_PORT_EGRESS_FRER_LATRSPERIOD */
3933 /*
3934  * FLATR (R/W)
3935  *
3936  * frerSeqRcvyLatentResetPeriod (802.1CB 10.4.1.12.4)
3937  */
3938 #define TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_MASK (0xFFFFFFUL)
3939 #define TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_SHIFT (0U)
3940 #define TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_MASK)
3941 #define TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_MASK) >> TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_SHIFT)
3942 
3943 /* Bitfield definition for register: CPU_PORT_EGRESS_FRER_LATTESTPERIOD */
3944 /*
3945  * FLATT (R/W)
3946  *
3947  * frerSeqRcvyLatentErrorPeriod (802.1CB 10.4.1.12.2)
3948  */
3949 #define TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_MASK (0xFFFFFFUL)
3950 #define TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_SHIFT (0U)
3951 #define TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_MASK)
3952 #define TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_MASK) >> TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_SHIFT)
3953 
3954 /* Bitfield definition for register: CPU_PORT_EGRESS_FRER_LATERRDIFFALW */
3955 /*
3956  * FDIFF (R/W)
3957  *
3958  * frerSeqRcvyLatentErrorDifference (802.1CB 10.4.1.12.1)
3959  */
3960 #define TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_MASK (0xFFFFFFFFUL)
3961 #define TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_SHIFT (0U)
3962 #define TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_MASK)
3963 #define TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_MASK) >> TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_SHIFT)
3964 
3965 /* Bitfield definition for register: CPU_PORT_EGRESS_FRER_LATERRCNT */
3966 /*
3967  * LATERR (R/WC)
3968  *
3969  * Counter – latent error detect. Write any value to clear
3970  */
3971 #define TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_MASK (0xFFFFFFFFUL)
3972 #define TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_SHIFT (0U)
3973 #define TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_MASK)
3974 #define TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_MASK) >> TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_SHIFT)
3975 
3976 /* Bitfield definition for register array: EGFRCNT */
3977 /*
3978  * VALUE (RO)
3979  *
3980  * Frame counters
3981  */
3982 #define TSW_EGFRCNT_VALUE_MASK (0xFFFFFFFFUL)
3983 #define TSW_EGFRCNT_VALUE_SHIFT (0U)
3984 #define TSW_EGFRCNT_VALUE_GET(x) (((uint32_t)(x) & TSW_EGFRCNT_VALUE_MASK) >> TSW_EGFRCNT_VALUE_SHIFT)
3985 
3986 /* Bitfield definition for register: CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_CNT_BYTE */
3987 /*
3988  * FDMEM_CNT_BYTE (RO)
3989  *
3990  * Number of bytes stored in frame drop FIFO
3991  */
3992 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_MASK (0xFFFFFFFFUL)
3993 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_SHIFT (0U)
3994 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_SHIFT)
3995 
3996 /* Bitfield definition for register: CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS */
3997 /*
3998  * WAIT_FOR_LU (RO)
3999  *
4000  * FD FIFO waits for LookUp information.
4001  */
4002 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_LU_MASK (0x800U)
4003 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_LU_SHIFT (11U)
4004 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_LU_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_LU_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_LU_SHIFT)
4005 
4006 /*
4007  * WAIT_FOR_FRAME (RO)
4008  *
4009  * FD FIFO waits for more frame data.
4010  */
4011 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_FRAME_MASK (0x400U)
4012 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_FRAME_SHIFT (10U)
4013 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_FRAME_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_FRAME_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_FRAME_SHIFT)
4014 
4015 /*
4016  * BUSY (RO)
4017  *
4018  * FD FIFO processes data.
4019  */
4020 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_BUSY_MASK (0x200U)
4021 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_BUSY_SHIFT (9U)
4022 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_BUSY_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_BUSY_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_BUSY_SHIFT)
4023 
4024 /*
4025  * READY (RO)
4026  *
4027  * FD FIFO ready to work or working.
4028  */
4029 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_READY_MASK (0x100U)
4030 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_READY_SHIFT (8U)
4031 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_READY_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_READY_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_READY_SHIFT)
4032 
4033 /*
4034  * FULL (RO)
4035  *
4036  * FD FIFO full
4037  */
4038 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_FULL_MASK (0x8U)
4039 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_FULL_SHIFT (3U)
4040 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_FULL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_FULL_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_FULL_SHIFT)
4041 
4042 /*
4043  * AMST_FULL (RO)
4044  *
4045  * FD FIFO almost full. Less than 1600 Byte left.
4046  */
4047 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_FULL_MASK (0x4U)
4048 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_FULL_SHIFT (2U)
4049 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_FULL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_FULL_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_FULL_SHIFT)
4050 
4051 /*
4052  * AMST_EMPTY (RO)
4053  *
4054  * FD FIFO almost empty. Few bytes in FIFO.
4055  */
4056 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_EMPTY_MASK (0x2U)
4057 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_EMPTY_SHIFT (1U)
4058 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_EMPTY_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_EMPTY_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_EMPTY_SHIFT)
4059 
4060 /*
4061  * EMPTY (RO)
4062  *
4063  * FD FIFO empty
4064  */
4065 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_EMPTY_MASK (0x1U)
4066 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_EMPTY_SHIFT (0U)
4067 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_EMPTY_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_EMPTY_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_EMPTY_SHIFT)
4068 
4069 /* Bitfield definition for register: CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG */
4070 /*
4071  * LU_DESC_ERR (R/W1C)
4072  *
4073  * LookUp Descriptor lost, because of unknown frame burst by MAC. If there is no MAC mailfunction then this flag will never be raised. FDFIFO requires reset.
4074  */
4075 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_MASK (0x40U)
4076 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_SHIFT (6U)
4077 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_MASK)
4078 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_SHIFT)
4079 
4080 /*
4081  * WRFAIL_FULL (R/W1C)
4082  *
4083  * Set if a frame is partially written into FIFO which had insufficient space. The frame is cut and frame error is set.
4084  */
4085 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_MASK (0x20U)
4086 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_SHIFT (5U)
4087 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_MASK)
4088 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_SHIFT)
4089 
4090 /*
4091  * DROP_NRDY (R/W1C)
4092  *
4093  * Frame was dropped because the FIFO was not ready. That can typically happen after a reset of the FIFO
4094  */
4095 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_MASK (0x10U)
4096 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_SHIFT (4U)
4097 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_MASK)
4098 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_SHIFT)
4099 
4100 /*
4101  * DROP_FULL_DESC (R/W1C)
4102  *
4103  * Frame was dropped because the internal descriptor FIFO is full. Full by too many frames.
4104  */
4105 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_MASK (0x8U)
4106 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_SHIFT (3U)
4107 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_MASK)
4108 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_SHIFT)
4109 
4110 /*
4111  * DROP_FULL_MEM (R/W1C)
4112  *
4113  * Frame was dropped because the FIFO is full. Full by too much data.
4114  */
4115 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_MASK (0x4U)
4116 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_SHIFT (2U)
4117 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_MASK)
4118 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_SHIFT)
4119 
4120 /*
4121  * DESC_NRDY_ERR (R/W1C)
4122  *
4123  * FD FIFO failure. Descriptor not received correctly.
4124  */
4125 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_MASK (0x2U)
4126 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_SHIFT (1U)
4127 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_MASK)
4128 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_SHIFT)
4129 
4130 /*
4131  * DESC_SEQ_ERR (R/W1C)
4132  *
4133  * FD FIFO failure. Internal controller lost synchronization.
4134  */
4135 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_MASK (0x1U)
4136 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_SHIFT (0U)
4137 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_MASK)
4138 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_SHIFT)
4139 
4140 /* Bitfield definition for register: CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG */
4141 /*
4142  * IE (R/W)
4143  *
4144  * Interrupt enable of ERROR_FLAG.
4145  */
4146 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_MASK (0x7FU)
4147 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_SHIFT (0U)
4148 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_MASK)
4149 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_SHIFT)
4150 
4151 /* Bitfield definition for register: CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG */
4152 /*
4153  * NOCUT_ERROR (R/W)
4154  *
4155  * FD_FIFO does not shorten frames which contain an error.
4156  */
4157 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_MASK (0x1U)
4158 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_SHIFT (0U)
4159 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_MASK)
4160 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_SHIFT)
4161 
4162 /* Bitfield definition for register: CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG */
4163 /*
4164  * DROP_DEST (R/W)
4165  *
4166  * Bit mapped Destination for dropped frames. Typically, frames are cleared at destination 0. Use another value to stream frames for analysis. Supports only max range of port[15:0].
4167  */
4168 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_MASK (0xFFFF0000UL)
4169 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_SHIFT (16U)
4170 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_MASK)
4171 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_SHIFT)
4172 
4173 /*
4174  * MIRROR_TX_EN (R/W)
4175  *
4176  * Incoming frames of this port will be mirrored to the given destination in MIRROR if their destination match with MIRROR_TX.
4177  */
4178 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_MASK (0x200U)
4179 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_SHIFT (9U)
4180 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_MASK)
4181 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_SHIFT)
4182 
4183 /*
4184  * MIRROR_RX_EN (R/W)
4185  *
4186  * Incoming frames of this port will be mirrored to the given destination in MIRROR_RX.
4187  */
4188 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_MASK (0x100U)
4189 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_SHIFT (8U)
4190 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_MASK)
4191 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_SHIFT)
4192 
4193 /*
4194  * CT_FPE_OVRD (R/W)
4195  *
4196  * If any Store&Forward option in RX_FDFIFO is set then this flag will still force preemptable traffic to be forwarded in Cut-Through mode. This is a useful option to save latency by double buffering if the used MAC/TSN-EP already does S&F.
4197  */
4198 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_MASK (0x40U)
4199 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_SHIFT (6U)
4200 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_MASK)
4201 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_SHIFT)
4202 
4203 /*
4204  * DISABLE (R/W)
4205  *
4206  * Disable input of FD FIFO. Take care that also descriptor generation of LookUp is disabled. Remaining frames should be cleared with DROP_ALL.
4207  */
4208 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_MASK (0x20U)
4209 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_SHIFT (5U)
4210 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_MASK)
4211 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_SHIFT)
4212 
4213 /*
4214  * DROP_ALL (R/W)
4215  *
4216  * Route all frames to DROP_DEST.
4217  */
4218 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_MASK (0x10U)
4219 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_SHIFT (4U)
4220 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_MASK)
4221 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_SHIFT)
4222 
4223 /*
4224  * ERROR_TO_CPU (R/W)
4225  *
4226  * Send error frames to CPU.
4227  */
4228 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_MASK (0x8U)
4229 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_SHIFT (3U)
4230 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_MASK)
4231 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_SHIFT)
4232 
4233 /*
4234  * MIRROR_TO_CPU (R/W)
4235  *
4236  * Duplicate frames to CPU.
4237  */
4238 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_MASK (0x4U)
4239 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_SHIFT (2U)
4240 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_MASK)
4241 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_SHIFT)
4242 
4243 /*
4244  * NODROP_ERROR (R/W)
4245  *
4246  * Do not drop frame errors.
4247  */
4248 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_MASK (0x2U)
4249 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_SHIFT (1U)
4250 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_MASK)
4251 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_SHIFT)
4252 
4253 /*
4254  * MODE_STORE_FW (R/W)
4255  *
4256  * Switch between Cut-Through and Store&Forward mode. 0 - Cut-Through 1 - Store&Forward
4257  */
4258 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_MASK (0x1U)
4259 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_SHIFT (0U)
4260 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_MASK)
4261 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_SHIFT)
4262 
4263 /* Bitfield definition for register: CPU_PORT_IGRESS_RX_FDFIFO_RESET */
4264 /*
4265  * SOFTRS (W)
4266  *
4267  * Write 1 to reset FD controller and memory pointers. Register Map content remains untouched
4268  */
4269 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_MASK (0x1U)
4270 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_SHIFT (0U)
4271 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_MASK)
4272 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_SHIFT)
4273 
4274 /* Bitfield definition for register: CPU_PORT_IGRESS_RX_FDFIFO_PARAM */
4275 /*
4276  * LU_FIFO_DEPTH (RO)
4277  *
4278  * Number of MAC lookup descriptors the FIFO can store.
4279  */
4280 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_LU_FIFO_DEPTH_MASK (0xFF000000UL)
4281 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_LU_FIFO_DEPTH_SHIFT (24U)
4282 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_LU_FIFO_DEPTH_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_LU_FIFO_DEPTH_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_LU_FIFO_DEPTH_SHIFT)
4283 
4284 /*
4285  * FD_DESC_FIFO_DESC (RO)
4286  *
4287  * Number of FD descriptors the FIFO can store. Two descriptors need to be stored per frame.
4288  */
4289 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_DESC_FIFO_DESC_MASK (0xFF0000UL)
4290 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_DESC_FIFO_DESC_SHIFT (16U)
4291 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_DESC_FIFO_DESC_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_DESC_FIFO_DESC_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_DESC_FIFO_DESC_SHIFT)
4292 
4293 /*
4294  * FD_FIFO_DESC (RO)
4295  *
4296  * Number of words (4byte) the Frame Drop FIFO can store.
4297  */
4298 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_FIFO_DESC_MASK (0xFFFFU)
4299 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_FIFO_DESC_SHIFT (0U)
4300 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_FIFO_DESC_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_FIFO_DESC_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_FIFO_DESC_SHIFT)
4301 
4302 /* Bitfield definition for register: CPU_PORT_IGRESS_RX_FDFIFO_STRFWD */
4303 /*
4304  * PORT (R/W)
4305  *
4306  * If selected port is set then the frame is transmitted in Store & Forward mode. This is necessary when the ingress rate of this port is slower than the egress rate of the transmitting port. In S&F, the ingress module is able to drop frames with bad CRC.bit 0 - CPU-Port,
4307  * bit 1 - Port 1, …
4308  */
4309 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_MASK (0x1FFFFFFUL)
4310 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_SHIFT (0U)
4311 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_MASK)
4312 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_SHIFT)
4313 
4314 /* Bitfield definition for register: CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK */
4315 /*
4316  * PORT (R/W)
4317  *
4318  * Port grouping via port mask. If the selected port is not set then the destination will be filtered out. This register allows the realization of port-based-VLAN (no VLAN tags required, only set it by ports).
4319  * bit 0 - CPU-Port,
4320  * bit 1 - Port 1, …
4321  */
4322 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_MASK (0x1FFFFFFUL)
4323 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_SHIFT (0U)
4324 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_MASK)
4325 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_SHIFT)
4326 
4327 /* Bitfield definition for register: CPU_PORT_IGRESS_RX_FDFIFO_MIRROR */
4328 /*
4329  * PORT (R/W)
4330  *
4331  * Mirror Port. If port mirroring is enabled TX/RX traffic will also be forwarded to this port.
4332  * bit 0 - CPU-Port,
4333  * bit 1 - Port 1, …
4334  */
4335 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_MASK (0x1FFFFFFUL)
4336 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_SHIFT (0U)
4337 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_MASK)
4338 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_SHIFT)
4339 
4340 /* Bitfield definition for register: CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX */
4341 /*
4342  * PORT (R/W)
4343  *
4344  * Mirror Selection TX. The destination of the frame is compared with this vector. All matching TX probe ports will be mirrored to MIRROR. It is necessary to configure all ingress ports to mirror the complete TX traffic.
4345  * bit 0 - CPU-Port,
4346  * bit 1 - Port 1, …
4347  */
4348 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_MASK (0x1FFFFFFUL)
4349 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_SHIFT (0U)
4350 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_MASK)
4351 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_SHIFT)
4352 
4353 /* Bitfield definition for register: CPU_PORT_IGRESS_STMID_ESELECT */
4354 /*
4355  * ESEL (RW)
4356  *
4357  * Select entry. Selected entry mapped to 0x40 – 0x5C.
4358  */
4359 #define TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_MASK (0xFFU)
4360 #define TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_SHIFT (0U)
4361 #define TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_MASK)
4362 #define TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_MASK) >> TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_SHIFT)
4363 
4364 /* Bitfield definition for register: CPU_PORT_IGRESS_STMID_CONTROL */
4365 /*
4366  * SID (RW)
4367  *
4368  * Stream ID – inserted to header on match
4369  */
4370 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_MASK (0xFF00U)
4371 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_SHIFT (8U)
4372 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_MASK)
4373 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_MASK) >> TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_SHIFT)
4374 
4375 /*
4376  * SEQGEN (RW)
4377  *
4378  * Sequence number generation enable
4379  */
4380 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_MASK (0x80U)
4381 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_SHIFT (7U)
4382 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_MASK)
4383 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_MASK) >> TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_SHIFT)
4384 
4385 /*
4386  * ACTCTL (RW)
4387  *
4388  * Active Destination MAC – control. See Table 6-6.
4389  */
4390 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_MASK (0x30U)
4391 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_SHIFT (4U)
4392 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_MASK)
4393 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_MASK) >> TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_SHIFT)
4394 
4395 /*
4396  * SMAC (RW)
4397  *
4398  * 0: Lookup by Destination MAC 1: Lookup by Source MAC
4399  */
4400 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_MASK (0x8U)
4401 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_SHIFT (3U)
4402 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_MASK)
4403 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_MASK) >> TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_SHIFT)
4404 
4405 /*
4406  * MODE (RW)
4407  *
4408  * Lookup mode. 1:Priority – a frame must be untagged or priority tagged ; 2:Tagged – a frame must have a VLAN tag ; 3:All – a frame can be tagged or untagged
4409  */
4410 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_MASK (0x6U)
4411 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_SHIFT (1U)
4412 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_MASK)
4413 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_MASK) >> TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_SHIFT)
4414 
4415 /*
4416  * EN (RW)
4417  *
4418  * Enable entry
4419  */
4420 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_MASK (0x1U)
4421 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_SHIFT (0U)
4422 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_MASK)
4423 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_MASK) >> TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_SHIFT)
4424 
4425 /* Bitfield definition for register: CPU_PORT_IGRESS_STMID_SEQNO */
4426 /*
4427  * SEQNO (RWC)
4428  *
4429  * Sequence number – next number when generating,any write access to clear.
4430  */
4431 #define TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_MASK (0xFFFFU)
4432 #define TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_SHIFT (0U)
4433 #define TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_MASK)
4434 #define TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_MASK) >> TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_SHIFT)
4435 
4436 /* Bitfield definition for register: CPU_PORT_IGRESS_STMID_MATCHCNT */
4437 /*
4438  * MATCH (RWC)
4439  *
4440  * Entry match counter – any write access to clear.
4441  */
4442 #define TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_MASK (0xFFFFFFFFUL)
4443 #define TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_SHIFT (0U)
4444 #define TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_MASK)
4445 #define TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_MASK) >> TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_SHIFT)
4446 
4447 /* Bitfield definition for register: CPU_PORT_IGRESS_STMID_MACLO */
4448 /*
4449  * MACL (RWC)
4450  *
4451  * MAC-Address [31:0] used by lookup.
4452  */
4453 #define TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_MASK (0xFFFFFFFFUL)
4454 #define TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_SHIFT (0U)
4455 #define TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_MASK)
4456 #define TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_MASK) >> TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_SHIFT)
4457 
4458 /* Bitfield definition for register: CPU_PORT_IGRESS_STMID_MACHI */
4459 /*
4460  * VID (RW)
4461  *
4462  * VLAN ID used by lookup.
4463  */
4464 #define TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_MASK (0xFFF0000UL)
4465 #define TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_SHIFT (16U)
4466 #define TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_MASK)
4467 #define TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_MASK) >> TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_SHIFT)
4468 
4469 /*
4470  * MATCH (RW)
4471  *
4472  * MAC-Address [47:31] used by lookup.
4473  */
4474 #define TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_MASK (0xFFFFU)
4475 #define TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_SHIFT (0U)
4476 #define TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_MASK)
4477 #define TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_MASK) >> TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_SHIFT)
4478 
4479 /* Bitfield definition for register: CPU_PORT_IGRESS_STMID_AMACLO */
4480 /*
4481  * AMACL (RW)
4482  *
4483  * Active Destination MAC, MAC-Address [31:0]
4484  */
4485 #define TSW_CPU_PORT_IGRESS_STMID_AMACLO_AMACL_MASK (0xFFFFFFFFUL)
4486 #define TSW_CPU_PORT_IGRESS_STMID_AMACLO_AMACL_SHIFT (0U)
4487 #define TSW_CPU_PORT_IGRESS_STMID_AMACLO_AMACL_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_AMACLO_AMACL_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_AMACLO_AMACL_MASK)
4488 #define TSW_CPU_PORT_IGRESS_STMID_AMACLO_AMACL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_AMACLO_AMACL_MASK) >> TSW_CPU_PORT_IGRESS_STMID_AMACLO_AMACL_SHIFT)
4489 
4490 /* Bitfield definition for register: CPU_PORT_IGRESS_STMID_AMACHI */
4491 /*
4492  * APCP (RW)
4493  *
4494  * Active Destination MAC, PCP
4495  */
4496 #define TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_MASK (0xF0000000UL)
4497 #define TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_SHIFT (28U)
4498 #define TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_MASK)
4499 #define TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_MASK) >> TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_SHIFT)
4500 
4501 /*
4502  * AVID (RW)
4503  *
4504  * Active Destination MAC, VLAN ID
4505  */
4506 #define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_MASK (0xFFF0000UL)
4507 #define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_SHIFT (16U)
4508 #define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_MASK)
4509 #define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_MASK) >> TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_SHIFT)
4510 
4511 /*
4512  * AMACH (RW)
4513  *
4514  * Active Destination MAC, MAC-Address [47:32]
4515  */
4516 #define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_MASK (0xFFFFU)
4517 #define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_SHIFT (0U)
4518 #define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_MASK)
4519 #define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_MASK) >> TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_SHIFT)
4520 
4521 /* Bitfield definition for register: CPU_PORT_IGRESS_FRER_CONTROL */
4522 /*
4523  * LATER (RWC)
4524  *
4525  * Latent error flag – write 1 to clear
4526  */
4527 #define TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_MASK (0x2U)
4528 #define TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_SHIFT (1U)
4529 #define TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_MASK)
4530 #define TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_MASK) >> TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_SHIFT)
4531 
4532 /*
4533  * RTENC (RW)
4534  *
4535  * R-TAG encoding enable.
4536  */
4537 #define TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_MASK (0x1U)
4538 #define TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_SHIFT (0U)
4539 #define TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_MASK)
4540 #define TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_MASK) >> TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_SHIFT)
4541 
4542 /* Bitfield definition for register: CPU_PORT_IGRESS_FRER_SIDSEL */
4543 /*
4544  * SID (RW)
4545  *
4546  * Stream ID selection for host access to IRFUNC and SRFUNC.
4547  */
4548 #define TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_MASK (0xFFU)
4549 #define TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_SHIFT (0U)
4550 #define TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_MASK)
4551 #define TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_MASK) >> TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_SHIFT)
4552 
4553 /* Bitfield definition for register: CPU_PORT_IGRESS_FRER_IRFUNC */
4554 /*
4555  * FEN (RW)
4556  *
4557  * Individual recovery function: FEN – enable function for stream SIDSEL.SID. FIDX – function index for stream SIDSEL.SID If function does not exists (FIDX >= 2**FD), FEN will be set to 0.
4558  */
4559 #define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_MASK (0x80000000UL)
4560 #define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_SHIFT (31U)
4561 #define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_MASK)
4562 #define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_MASK) >> TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_SHIFT)
4563 
4564 /*
4565  * FIDX (RW)
4566  *
4567  */
4568 #define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_MASK (0xFFU)
4569 #define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_SHIFT (0U)
4570 #define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_MASK)
4571 #define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_MASK) >> TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_SHIFT)
4572 
4573 /* Bitfield definition for register: CPU_PORT_IGRESS_FRER_SRFUNC */
4574 /*
4575  * FEN (RW)
4576  *
4577  * Sequence recovery function: FEN – enable function for stream SIDSEL.SID. FIDX – function index for stream SIDSEL.SID If function does not exists (FIDX >= 2**FD), FEN will be set to 0.
4578  */
4579 #define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_MASK (0x80000000UL)
4580 #define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_SHIFT (31U)
4581 #define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_MASK)
4582 #define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_MASK) >> TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_SHIFT)
4583 
4584 /*
4585  * FIDX (RW)
4586  *
4587  */
4588 #define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_MASK (0xFFU)
4589 #define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_SHIFT (0U)
4590 #define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_MASK)
4591 #define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_MASK) >> TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_SHIFT)
4592 
4593 /* Bitfield definition for register: CPU_PORT_IGRESS_FRER_FSELECT */
4594 /*
4595  * FIDX (RW)
4596  *
4597  * Recovery function selection for host access at offset 0x140+
4598  */
4599 #define TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_MASK (0xFFU)
4600 #define TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_SHIFT (0U)
4601 #define TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_MASK)
4602 #define TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_SHIFT)
4603 
4604 /* Bitfield definition for register: CPU_PORT_IGRESS_FRER_FCTRL */
4605 /*
4606  * FRSET (WO)
4607  *
4608  * Reset recovery function – self-resetting to 0
4609  */
4610 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_MASK (0x80000000UL)
4611 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_SHIFT (31U)
4612 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_MASK)
4613 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_SHIFT)
4614 
4615 /*
4616  * PATHS (RW)
4617  *
4618  * Number of paths (used by latent error detection)
4619  */
4620 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_MASK (0xFF0000UL)
4621 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_SHIFT (16U)
4622 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_MASK)
4623 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_SHIFT)
4624 
4625 /*
4626  * HLEN (RW)
4627  *
4628  * History length (used by Vector recovery algorithm)
4629  */
4630 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_MASK (0x1F00U)
4631 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_SHIFT (8U)
4632 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_MASK)
4633 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_SHIFT)
4634 
4635 /*
4636  * ALGO (RW)
4637  *
4638  * Recovery function algorithm: 0 – Vector recovery algorithm 1 – Match recovery algorithm
4639  */
4640 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_MASK (0x10U)
4641 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_SHIFT (4U)
4642 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_MASK)
4643 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_SHIFT)
4644 
4645 /*
4646  * LATEN (RW)
4647  *
4648  * Latent error detection enable
4649  */
4650 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_MASK (0x8U)
4651 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_SHIFT (3U)
4652 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_MASK)
4653 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_SHIFT)
4654 
4655 /*
4656  * IND (RW)
4657  *
4658  * Individual function (802.1CB 10.4.1.10)
4659  */
4660 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_MASK (0x4U)
4661 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_SHIFT (2U)
4662 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_MASK)
4663 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_SHIFT)
4664 
4665 /*
4666  * TNS (RW)
4667  *
4668  * TakeNoSequence (802.1CB 10.4.1.9)
4669  */
4670 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_MASK (0x2U)
4671 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_SHIFT (1U)
4672 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_MASK)
4673 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_SHIFT)
4674 
4675 /* Bitfield definition for register: CPU_PORT_IGRESS_FRER_RESETMSEC */
4676 /*
4677  * FSRMS (RW)
4678  *
4679  * frerSeqRcvyResetMSec (802.1CB 10.4.1.7)
4680  */
4681 #define TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_MASK (0xFFFFFFUL)
4682 #define TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_SHIFT (0U)
4683 #define TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_MASK)
4684 #define TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_MASK) >> TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_SHIFT)
4685 
4686 /* Bitfield definition for register: CPU_PORT_IGRESS_FRER_LATRSPERIOD */
4687 /*
4688  * FLATR (RW)
4689  *
4690  * frerSeqRcvyLatentResetPeriod (802.1CB 10.4.1.12.4)
4691  */
4692 #define TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_MASK (0xFFFFFFUL)
4693 #define TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_SHIFT (0U)
4694 #define TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_MASK)
4695 #define TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_MASK) >> TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_SHIFT)
4696 
4697 /* Bitfield definition for register: CPU_PORT_IGRESS_FRER_LATTESTPERIOD */
4698 /*
4699  * FLATT (RW)
4700  *
4701  * frerSeqRcvyLatentErrorPeriod (802.1CB 10.4.1.12.2)
4702  */
4703 #define TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_MASK (0xFFFFFFUL)
4704 #define TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_SHIFT (0U)
4705 #define TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_MASK)
4706 #define TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_MASK) >> TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_SHIFT)
4707 
4708 /* Bitfield definition for register: CPU_PORT_IGRESS_FRER_LATERRDIFFALW */
4709 /*
4710  * FDIFF (RW)
4711  *
4712  * frerSeqRcvyLatentErrorDifference (802.1CB 10.4.1.12.1)
4713  */
4714 #define TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_MASK (0xFFFFFFFFUL)
4715 #define TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_SHIFT (0U)
4716 #define TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_MASK)
4717 #define TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_MASK) >> TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_SHIFT)
4718 
4719 /* Bitfield definition for register: CPU_PORT_IGRESS_FRER_LATERRCNT */
4720 /*
4721  * LATERR (RWC)
4722  *
4723  * Counter – latent error detect. Write any value to clear
4724  */
4725 #define TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_MASK (0xFFFFFFFFUL)
4726 #define TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_SHIFT (0U)
4727 #define TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_MASK)
4728 #define TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_MASK) >> TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_SHIFT)
4729 
4730 /* Bitfield definition for register array: IGFRCNT */
4731 /*
4732  * VALUE (RO)
4733  *
4734  * Frame counters
4735  */
4736 #define TSW_IGFRCNT_VALUE_MASK (0xFFFFFFFFUL)
4737 #define TSW_IGFRCNT_VALUE_SHIFT (0U)
4738 #define TSW_IGFRCNT_VALUE_GET(x) (((uint32_t)(x) & TSW_IGFRCNT_VALUE_MASK) >> TSW_IGFRCNT_VALUE_SHIFT)
4739 
4740 /* Bitfield definition for register: CPU_PORT_MONITOR_CTRL */
4741 /*
4742  * EN (R/W)
4743  *
4744  * Enables counter. If deasserted the counter process stops and the counters hold their value.
4745  */
4746 #define TSW_CPU_PORT_MONITOR_CTRL_EN_MASK (0x1U)
4747 #define TSW_CPU_PORT_MONITOR_CTRL_EN_SHIFT (0U)
4748 #define TSW_CPU_PORT_MONITOR_CTRL_EN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_MONITOR_CTRL_EN_SHIFT) & TSW_CPU_PORT_MONITOR_CTRL_EN_MASK)
4749 #define TSW_CPU_PORT_MONITOR_CTRL_EN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_CTRL_EN_MASK) >> TSW_CPU_PORT_MONITOR_CTRL_EN_SHIFT)
4750 
4751 /* Bitfield definition for register: CPU_PORT_MONITOR_RESET */
4752 /*
4753  * RSRX (WO)
4754  *
4755  * Write '1' to reset all RX counters.
4756  */
4757 #define TSW_CPU_PORT_MONITOR_RESET_RSRX_MASK (0x4U)
4758 #define TSW_CPU_PORT_MONITOR_RESET_RSRX_SHIFT (2U)
4759 #define TSW_CPU_PORT_MONITOR_RESET_RSRX_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_MONITOR_RESET_RSRX_SHIFT) & TSW_CPU_PORT_MONITOR_RESET_RSRX_MASK)
4760 #define TSW_CPU_PORT_MONITOR_RESET_RSRX_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RESET_RSRX_MASK) >> TSW_CPU_PORT_MONITOR_RESET_RSRX_SHIFT)
4761 
4762 /*
4763  * RSTX (WO)
4764  *
4765  * Write '1' to reset all TX counters
4766  */
4767 #define TSW_CPU_PORT_MONITOR_RESET_RSTX_MASK (0x2U)
4768 #define TSW_CPU_PORT_MONITOR_RESET_RSTX_SHIFT (1U)
4769 #define TSW_CPU_PORT_MONITOR_RESET_RSTX_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_MONITOR_RESET_RSTX_SHIFT) & TSW_CPU_PORT_MONITOR_RESET_RSTX_MASK)
4770 #define TSW_CPU_PORT_MONITOR_RESET_RSTX_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RESET_RSTX_MASK) >> TSW_CPU_PORT_MONITOR_RESET_RSTX_SHIFT)
4771 
4772 /*
4773  * RSALL (WO)
4774  *
4775  * Write '1' to reset all TX&RX counters.
4776  */
4777 #define TSW_CPU_PORT_MONITOR_RESET_RSALL_MASK (0x1U)
4778 #define TSW_CPU_PORT_MONITOR_RESET_RSALL_SHIFT (0U)
4779 #define TSW_CPU_PORT_MONITOR_RESET_RSALL_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_MONITOR_RESET_RSALL_SHIFT) & TSW_CPU_PORT_MONITOR_RESET_RSALL_MASK)
4780 #define TSW_CPU_PORT_MONITOR_RESET_RSALL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RESET_RSALL_MASK) >> TSW_CPU_PORT_MONITOR_RESET_RSALL_SHIFT)
4781 
4782 /* Bitfield definition for register: CPU_PORT_MONITOR_PARAM */
4783 /*
4784  * RX_CNT_EN_VEC (RO)
4785  *
4786  * Vector of implemented RX counters. E.g. 0x000F means only the first 4 RX counter are available.
4787  */
4788 #define TSW_CPU_PORT_MONITOR_PARAM_RX_CNT_EN_VEC_MASK (0xFFFF0000UL)
4789 #define TSW_CPU_PORT_MONITOR_PARAM_RX_CNT_EN_VEC_SHIFT (16U)
4790 #define TSW_CPU_PORT_MONITOR_PARAM_RX_CNT_EN_VEC_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_PARAM_RX_CNT_EN_VEC_MASK) >> TSW_CPU_PORT_MONITOR_PARAM_RX_CNT_EN_VEC_SHIFT)
4791 
4792 /*
4793  * TX_CNT_EN_VEC (RO)
4794  *
4795  * Vector of implemented RX counters. E.g. 0x000F means only the first 4 RX counter are available.
4796  */
4797 #define TSW_CPU_PORT_MONITOR_PARAM_TX_CNT_EN_VEC_MASK (0xFF00U)
4798 #define TSW_CPU_PORT_MONITOR_PARAM_TX_CNT_EN_VEC_SHIFT (8U)
4799 #define TSW_CPU_PORT_MONITOR_PARAM_TX_CNT_EN_VEC_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_PARAM_TX_CNT_EN_VEC_MASK) >> TSW_CPU_PORT_MONITOR_PARAM_TX_CNT_EN_VEC_SHIFT)
4800 
4801 /*
4802  * CNTW (RO)
4803  *
4804  * Vector of implemented RX counters. E.g. 0x000F means only the first 4 RX counter
4805  * are available.
4806  */
4807 #define TSW_CPU_PORT_MONITOR_PARAM_CNTW_MASK (0x7FU)
4808 #define TSW_CPU_PORT_MONITOR_PARAM_CNTW_SHIFT (0U)
4809 #define TSW_CPU_PORT_MONITOR_PARAM_CNTW_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_PARAM_CNTW_MASK) >> TSW_CPU_PORT_MONITOR_PARAM_CNTW_SHIFT)
4810 
4811 /* Bitfield definition for register: CPU_PORT_MONITOR_TX_COUNTER_TX_FGOOD */
4812 /*
4813  * TX_FGOOD (RO)
4814  *
4815  * Good transmitted Frames to TX TSN-EP.
4816  */
4817 #define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_MASK (0xFFFFFFFFUL)
4818 #define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_SHIFT (0U)
4819 #define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_MASK) >> TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_SHIFT)
4820 
4821 /* Bitfield definition for register: CPU_PORT_MONITOR_TX_COUNTER_TX_FERROR */
4822 /*
4823  * TX_FERROR (RO)
4824  *
4825  * Transmitted Frames with Error to TX TSN-EP.
4826  */
4827 #define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_MASK (0xFFFFFFFFUL)
4828 #define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_SHIFT (0U)
4829 #define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_MASK) >> TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_SHIFT)
4830 
4831 /* Bitfield definition for register: CPU_PORT_MONITOR_TX_COUNTER_TX_DROP_OVFL */
4832 /*
4833  * TX_DROP_OVFL (RO)
4834  *
4835  * Dropped frames by full queue of TSN-EP.
4836  */
4837 #define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_MASK (0xFFFFFFFFUL)
4838 #define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_SHIFT (0U)
4839 #define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_MASK) >> TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_SHIFT)
4840 
4841 /* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_FGOOD */
4842 /*
4843  * RX_FGOOD (RO)
4844  *
4845  * Good received frame by ingress buffer.
4846  */
4847 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_MASK (0xFFFFFFFFUL)
4848 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_SHIFT (0U)
4849 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_SHIFT)
4850 
4851 /* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_FERROR */
4852 /*
4853  * RX_FERROR (RO)
4854  *
4855  * Bad received frame by ingress buffer.
4856  */
4857 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_MASK (0xFFFFFFFFUL)
4858 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_SHIFT (0U)
4859 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_SHIFT)
4860 
4861 /* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_KNOWN */
4862 /*
4863  * RX_KNOWN (RO)
4864  *
4865  * Number of frames passed ingress with hit by MAC Table. This includes Broadcast and non-relayed frames.
4866  */
4867 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_MASK (0xFFFFFFFFUL)
4868 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_SHIFT (0U)
4869 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_SHIFT)
4870 
4871 /* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_UNKNOWN */
4872 /*
4873  * RX_UNKNOWN (RO)
4874  *
4875  * Number of frames passed ingress without hit by MAC table.
4876  */
4877 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_MASK (0xFFFFFFFFUL)
4878 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_SHIFT (0U)
4879 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_SHIFT)
4880 
4881 /* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_UC */
4882 /*
4883  * RX_UC (RO)
4884  *
4885  * Number of unicast frames
4886  */
4887 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_MASK (0xFFFFFFFFUL)
4888 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_SHIFT (0U)
4889 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_SHIFT)
4890 
4891 /* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_INTERN */
4892 /*
4893  * RX_INTERN (RO)
4894  *
4895  * Number of non-relay frames
4896  */
4897 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_MASK (0xFFFFFFFFUL)
4898 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_SHIFT (0U)
4899 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_SHIFT)
4900 
4901 /* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_BC */
4902 /*
4903  * RX_BC (RO)
4904  *
4905  * Number of Broadcast frames
4906  */
4907 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_MASK (0xFFFFFFFFUL)
4908 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_SHIFT (0U)
4909 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_SHIFT)
4910 
4911 /* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_MULTI */
4912 /*
4913  * RX_MULTI (RO)
4914  *
4915  * Number of Multicast frames
4916  */
4917 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_MASK (0xFFFFFFFFUL)
4918 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_SHIFT (0U)
4919 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_SHIFT)
4920 
4921 /* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_VLAN */
4922 /*
4923  * RX_VLAN (RO)
4924  *
4925  * Number of VLAN tagged frames
4926  */
4927 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_MASK (0xFFFFFFFFUL)
4928 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_SHIFT (0U)
4929 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_SHIFT)
4930 
4931 /* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_OVFL */
4932 /*
4933  * RX_DROP_OVFL (RO)
4934  *
4935  * Dropped frames by ingress overflow.
4936  */
4937 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_MASK (0xFFFFFFFFUL)
4938 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_SHIFT (0U)
4939 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_SHIFT)
4940 
4941 /* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_LU */
4942 /*
4943  * RX_DROP_LU (RO)
4944  *
4945  * Dropped frames by LookUp decision.
4946  */
4947 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_MASK (0xFFFFFFFFUL)
4948 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_SHIFT (0U)
4949 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_SHIFT)
4950 
4951 /* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_ERR */
4952 /*
4953  * RX_DROP_ERR (RO)
4954  *
4955  * Dropped frames with error by ingress. Possible in S&F mode or when frame is queued in ingress.
4956  */
4957 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_MASK (0xFFFFFFFFUL)
4958 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_SHIFT (0U)
4959 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_SHIFT)
4960 
4961 /* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_VLAN */
4962 /*
4963  * RX_DROP_VLAN (RO)
4964  *
4965  * Dropped frames by incompatible VLAN.
4966  */
4967 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_MASK (0xFFFFFFFFUL)
4968 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_SHIFT (0U)
4969 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_SHIFT)
4970 
4971 /* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD */
4972 /*
4973  * RX_FPE_FGOOD (RO)
4974  *
4975  * Number of preemptable frames. Subset of RX_FGOOD
4976  */
4977 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_MASK (0xFFFFFFFFUL)
4978 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_SHIFT (0U)
4979 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_SHIFT)
4980 
4981 /* Bitfield definition for register of struct array TSNPORT: MAC_VER */
4982 /*
4983  * VER_H (R)
4984  *
4985  * Major version number (higher part of the version)
4986  */
4987 #define TSW_TSNPORT_MAC_MAC_VER_VER_H_MASK (0xFFFF0000UL)
4988 #define TSW_TSNPORT_MAC_MAC_VER_VER_H_SHIFT (16U)
4989 #define TSW_TSNPORT_MAC_MAC_VER_VER_H_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_VER_VER_H_MASK) >> TSW_TSNPORT_MAC_MAC_VER_VER_H_SHIFT)
4990 
4991 /*
4992  * VER_L (R)
4993  *
4994  * Minor version number (lower part of the version)
4995  */
4996 #define TSW_TSNPORT_MAC_MAC_VER_VER_L_MASK (0xFFFFU)
4997 #define TSW_TSNPORT_MAC_MAC_VER_VER_L_SHIFT (0U)
4998 #define TSW_TSNPORT_MAC_MAC_VER_VER_L_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_VER_VER_L_MASK) >> TSW_TSNPORT_MAC_MAC_VER_VER_L_SHIFT)
4999 
5000 /* Bitfield definition for register of struct array TSNPORT: MAC_MACADDR_L */
5001 /*
5002  * MACADDR (R/W)
5003  *
5004  * MAC address
5005  * Lower bits of MAC address (31:0).
5006  * MACADDR only be modified if TX_EN=0 and RX_EN=0.
5007  */
5008 #define TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_MASK (0xFFFFFFFFUL)
5009 #define TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_SHIFT (0U)
5010 #define TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_SHIFT) & TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_MASK)
5011 #define TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_MASK) >> TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_SHIFT)
5012 
5013 /* Bitfield definition for register of struct array TSNPORT: MAC_MACADDR_H */
5014 /*
5015  * PROMISC (R/W)
5016  *
5017  * 0 – disabled
5018  * 1 – enabled
5019  * If promiscuous mode is enabled, then reception of all frames independent from the
5020  * Ethernet destination address is enabled.
5021  * PROMISC can be changed at any time.
5022  */
5023 #define TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_MASK (0x10000UL)
5024 #define TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_SHIFT (16U)
5025 #define TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_SHIFT) & TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_MASK)
5026 #define TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_MASK) >> TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_SHIFT)
5027 
5028 /*
5029  * MACADDR (R/W)
5030  *
5031  * MAC address (see Chapter 4.1)
5032  * Upper bits of MAC address (47:32).
5033  * MACADDR can only be modified if TX_EN=0 and RX_EN=0.
5034  */
5035 #define TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_MASK (0xFFFFU)
5036 #define TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_SHIFT (0U)
5037 #define TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_SHIFT) & TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_MASK)
5038 #define TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_MASK) >> TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_SHIFT)
5039 
5040 /* Bitfield definition for register of struct array TSNPORT: MAC_MAC_CTRL */
5041 /*
5042  * FSTIM (R/W)
5043  *
5044  * Fault Stimulation
5045  * See Chapter 11.3, Table 11-1 for details.
5046  * FSTIM is write-locked if CSA=1.
5047  */
5048 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_MASK (0x1F000000UL)
5049 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_SHIFT (24U)
5050 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_MASK)
5051 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_SHIFT)
5052 
5053 /*
5054  * RCA (R)
5055  *
5056  * <ref_clk> active
5057  * 0 – not active
5058  * 1 – active
5059  * See chapter 11.2.3 for details.
5060  */
5061 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCA_MASK (0x100000UL)
5062 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCA_SHIFT (20U)
5063 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCA_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCA_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCA_SHIFT)
5064 
5065 /*
5066  * MCA (R)
5067  *
5068  * <mii_clk> active
5069  * 0 – not active
5070  * 1 – active
5071  * See chapter 11.2.3 for details.
5072  */
5073 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCA_MASK (0x80000UL)
5074 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCA_SHIFT (19U)
5075 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCA_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCA_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCA_SHIFT)
5076 
5077 /*
5078  * SEN (R/W)
5079  *
5080  * Safety Enable
5081  * 0 – disabled
5082  * 1 – enabled
5083  * If enabled, then two instances of the logic core of LLEMAC-1G are compared at
5084  * runtime to each other.
5085  * SEN can only be changed if RX_EN and TX_EN can be read as 0. Deactivation delays
5086  * of RX_EN and TX_EN have to be considered. It is possible to change SEN together
5087  * with the activation of RX_EN and TX_EN.
5088  */
5089 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_MASK (0x10000UL)
5090 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_SHIFT (16U)
5091 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_MASK)
5092 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_SHIFT)
5093 
5094 /*
5095  * CSA (R)
5096  *
5097  * Clock switching active (<tx_clk>)
5098  * 0 – not active
5099  * 1 – active
5100  * Switching of <tx_clk> is commanded if CLKSEL or FSTIM (see Table 11-1) are
5101  * written. Clock switching takes a few clock cycles and this is signaled with CSA=1.
5102  * When CSA=1 then CLKSEL and FSTIM are write-locked and cannot be changed.
5103  */
5104 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_CSA_MASK (0x2000U)
5105 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_CSA_SHIFT (13U)
5106 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_CSA_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_CSA_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_CSA_SHIFT)
5107 
5108 /*
5109  * RCE (R/W)
5110  *
5111  * <ref_clk> enable
5112  * 0 – disabled
5113  * 1 – enabled
5114  * RCE can only be modified if CLKSEL=111. See Chapter 7.3.3 for further details.
5115  */
5116 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_MASK (0x1000U)
5117 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_SHIFT (12U)
5118 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_MASK)
5119 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_SHIFT)
5120 
5121 /*
5122  * MCE (R/W)
5123  *
5124  * <mii_clk> enable
5125  * 0 – disabled
5126  * 1 – enabled
5127  * MCE can only be modified if CLKSEL=111. See Chapter 7.3.3 for further details.
5128  */
5129 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_MASK (0x800U)
5130 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_SHIFT (11U)
5131 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_MASK)
5132 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_SHIFT)
5133 
5134 /*
5135  * CLKSEL (R/W)
5136  *
5137  * TX path clock selector
5138  * 000 – <mii_clk>
5139  * 001 – <ref_clk> (recommended setting for this selection)
5140  * 010 – <ref_clk> divided by 5
5141  * 011 – <ref_clk> divided by 10
5142  * 100 – <ref_clk> divided by 50
5143  * 111 – <ref_clk> and enables modification of RCE and MCE
5144  * others – <ref_clk>
5145  * See Chapter 7 for further details.
5146  * CLKSEL is write-locked if CSA=1.
5147  */
5148 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_MASK (0x700U)
5149 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_SHIFT (8U)
5150 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_MASK)
5151 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_SHIFT)
5152 
5153 /*
5154  * PHYSEL (R/W)
5155  *
5156  * Selection of the PHY
5157  * 01 – GMII, fixed to 1
5158  */
5159 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_MASK (0x60U)
5160 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_SHIFT (5U)
5161 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_MASK)
5162 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_SHIFT)
5163 
5164 /*
5165  * GMIIMODE (R/W)
5166  *
5167  * GMII mode / Ethernet speed selection (See Chapter 4.5.)
5168  * 0 – MII: 10Mbit/s or 100Mbit/s
5169  * 1 – GMII: 1GBit/s
5170  * GMIIMODE can only be changed if RX_EN=0 and TX_EN=0. Deactivation delays of
5171  * RX_EN and TX_EN have to be considered. GMIIMODE can only be changed, if these
5172  * register bits can be read as 0. It is possible to change GMIIMODE together with the
5173  * activation of RX_EN and TX_EN.
5174  * GMIIMODE drives the outputs <tx_gmiimode> and <rx_gmiimode>.
5175  */
5176 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_MASK (0x10U)
5177 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_SHIFT (4U)
5178 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_MASK)
5179 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_SHIFT)
5180 
5181 /*
5182  * JUMBO (R/W)
5183  *
5184  * Jumbo frame support
5185  * 0 – jumbo frames not supported
5186  * 1 – jumbo frame supported (not recommended)
5187  * Jumbo frames are non-standard Ethernet frames with a size bigger than envelope
5188  * frames (which contain 1982 payload bytes). If jumbo frames are not supported, then
5189  * LLEMAC-1G generates the appropriate error signals (<tx_gmii_er> for the TX path
5190  * and <rx_avst_err> for the RX path).
5191  * Although jumbo frames typically contain up to 9000 bytes, the LLEMAC-1G can handle
5192  * an infinite frame size. The problem of jumbo frames is the necessary storage space in
5193  * transmission and reception buffers. LLEMAC-1G does not include storage buffers.
5194  * JUMBO can be activated or deactivated at any time. The new setting becomes valid
5195  * immediately after clock domain crossing.
5196  */
5197 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_MASK (0x8U)
5198 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_SHIFT (3U)
5199 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_MASK)
5200 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_SHIFT)
5201 
5202 /*
5203  * TX_EN (R/W)
5204  *
5205  * TX path enable
5206  * 0 – transmission disabled - Avalon-ST READY for the TX path will be set to 0.
5207  * 1 – transmission enabled
5208  * TX_EN can be activated or deactivated at any time. Deactivation may take some time.
5209  * If during deactivation there is a frame in transmission, then this frame will be
5210  * completed fist. Afterwards bit TX_EN can be read as 0.
5211  * After the transmission is disabled there may be pending frames left, waiting at the TX
5212  * stream interface.
5213  */
5214 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_MASK (0x4U)
5215 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_SHIFT (2U)
5216 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_MASK)
5217 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_SHIFT)
5218 
5219 /*
5220  * RX_EN (R/W)
5221  *
5222  * RX path enable
5223  * 0 – reception disabled – no frames fed to Avalon-ST RX path
5224  * 1 – reception enabled
5225  * RX_EN can be activated or deactivated at any time. Deactivation may take some time.
5226  * If during deactivation there is a frame in reception, then this frame will be completed
5227  * first. Afterwards bit RX_EN can be read as 0.
5228  */
5229 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_MASK (0x2U)
5230 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_SHIFT (1U)
5231 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_MASK)
5232 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_SHIFT)
5233 
5234 /*
5235  * RESSTAT (R/W)
5236  *
5237  * Software reset of the statistic counters (see Table 3-8)
5238  * 0 – no reset
5239  * 1 – reset active
5240  * RESSTAT will be automatically set to 0 after the counters have been reset
5241  */
5242 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_MASK (0x1U)
5243 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_SHIFT (0U)
5244 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_MASK)
5245 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_SHIFT)
5246 
5247 /* Bitfield definition for register of struct array TSNPORT: MAC_TX_FRAMES */
5248 /*
5249  * TX_FRAMES (R)
5250  *
5251  * Number of successfully transmitted frames.
5252  */
5253 #define TSW_TSNPORT_MAC_MAC_TX_FRAMES_TX_FRAMES_MASK (0xFFFFFFFFUL)
5254 #define TSW_TSNPORT_MAC_MAC_TX_FRAMES_TX_FRAMES_SHIFT (0U)
5255 #define TSW_TSNPORT_MAC_MAC_TX_FRAMES_TX_FRAMES_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_TX_FRAMES_TX_FRAMES_MASK) >> TSW_TSNPORT_MAC_MAC_TX_FRAMES_TX_FRAMES_SHIFT)
5256 
5257 /* Bitfield definition for register of struct array TSNPORT: MAC_RX_FRAMES */
5258 /*
5259  * RX_FRAMES (R)
5260  *
5261  * Number of successfully received frames.
5262  */
5263 #define TSW_TSNPORT_MAC_MAC_RX_FRAMES_RX_FRAMES_MASK (0xFFFFFFFFUL)
5264 #define TSW_TSNPORT_MAC_MAC_RX_FRAMES_RX_FRAMES_SHIFT (0U)
5265 #define TSW_TSNPORT_MAC_MAC_RX_FRAMES_RX_FRAMES_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_RX_FRAMES_RX_FRAMES_MASK) >> TSW_TSNPORT_MAC_MAC_RX_FRAMES_RX_FRAMES_SHIFT)
5266 
5267 /* Bitfield definition for register of struct array TSNPORT: MAC_TX_OCTETS */
5268 /*
5269  * TX_OCTETS (R)
5270  *
5271  * Number of successfully transmitted payload and padding octets.
5272  */
5273 #define TSW_TSNPORT_MAC_MAC_TX_OCTETS_TX_OCTETS_MASK (0xFFFFFFFFUL)
5274 #define TSW_TSNPORT_MAC_MAC_TX_OCTETS_TX_OCTETS_SHIFT (0U)
5275 #define TSW_TSNPORT_MAC_MAC_TX_OCTETS_TX_OCTETS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_TX_OCTETS_TX_OCTETS_MASK) >> TSW_TSNPORT_MAC_MAC_TX_OCTETS_TX_OCTETS_SHIFT)
5276 
5277 /* Bitfield definition for register of struct array TSNPORT: MAC_RX_OCTETS */
5278 /*
5279  * RX_OCTETS (R)
5280  *
5281  * Number of successfully received payload and padding octets.
5282  */
5283 #define TSW_TSNPORT_MAC_MAC_RX_OCTETS_RX_OCTETS_MASK (0xFFFFFFFFUL)
5284 #define TSW_TSNPORT_MAC_MAC_RX_OCTETS_RX_OCTETS_SHIFT (0U)
5285 #define TSW_TSNPORT_MAC_MAC_RX_OCTETS_RX_OCTETS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_RX_OCTETS_RX_OCTETS_MASK) >> TSW_TSNPORT_MAC_MAC_RX_OCTETS_RX_OCTETS_SHIFT)
5286 
5287 /* Bitfield definition for register of struct array TSNPORT: MAC_MDIO_CFG */
5288 /*
5289  * NPRE (R/W)
5290  *
5291  * No Preamble
5292  * With NPRE=1 the preamble generation is suppressed and frames are initiated with
5293  * Start of Frame pattern directly. Suitable in case that all connected PHYs accept
5294  * management frames without a preamble pattern. Recommended to be used if only
5295  * one PHY is connected.
5296  */
5297 #define TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_MASK (0x8000U)
5298 #define TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_SHIFT (15U)
5299 #define TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_MASK)
5300 #define TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_SHIFT)
5301 
5302 /*
5303  * ENABLE (R/W)
5304  *
5305  * Enable the MDIO controller. If the controller is enabled then MDC will be toggled.
5306  * ENABLE can only be read as 1 if a valid MDC_CLKDIV value is set.
5307  */
5308 #define TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_MASK (0x100U)
5309 #define TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_SHIFT (8U)
5310 #define TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_MASK)
5311 #define TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_SHIFT)
5312 
5313 /*
5314  * MDC_CLKDIV (R/W)
5315  *
5316  * Clock Divider to configure MDC clock frequency. Refer to 10.1 Clock Divider for more
5317  * details.
5318  */
5319 #define TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_MASK (0xFFU)
5320 #define TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_SHIFT (0U)
5321 #define TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_MASK)
5322 #define TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_SHIFT)
5323 
5324 /* Bitfield definition for register of struct array TSNPORT: MAC_MDIO_CTRL */
5325 /*
5326  * OP (R/W)
5327  *
5328  * Opcode to determine transfer type
5329  * 01 – Write Access
5330  * 10 – Read Access
5331  */
5332 #define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_MASK (0xC0000000UL)
5333 #define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_SHIFT (30U)
5334 #define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_MASK)
5335 #define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_SHIFT)
5336 
5337 /*
5338  * PHYAD (R/W)
5339  *
5340  * Management Frame PHY Address.
5341  */
5342 #define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_MASK (0x1F000000UL)
5343 #define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_SHIFT (24U)
5344 #define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_MASK)
5345 #define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_SHIFT)
5346 
5347 /*
5348  * REGAD (R/W)
5349  *
5350  * Management Frame Register Address.
5351  */
5352 #define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_MASK (0x1F0000UL)
5353 #define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_SHIFT (16U)
5354 #define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_MASK)
5355 #define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_SHIFT)
5356 
5357 /*
5358  * INIT (R/W)
5359  *
5360  * INIT=1 results in a MDIO write/read transfer if READY=1. If READY=0 while a
5361  * transfer is already pending or if ENABLE=0 then settings INIT=1 has no effect and
5362  * the current transaction is withdrawn.
5363  */
5364 #define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_MASK (0x100U)
5365 #define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_SHIFT (8U)
5366 #define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_MASK)
5367 #define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_SHIFT)
5368 
5369 /*
5370  * READY (R)
5371  *
5372  * READY=1 indicates a finished transfer and also shows that the controller is ready for a
5373  * new transfer. READY=1 is only possible if ENABLE=1.
5374  * If READY=1 is signaled after a read transfer, then RD_DATA is valid until a new
5375  * transfer is started.
5376  */
5377 #define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_READY_MASK (0x1U)
5378 #define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_READY_SHIFT (0U)
5379 #define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_READY_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_READY_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CTRL_READY_SHIFT)
5380 
5381 /* Bitfield definition for register of struct array TSNPORT: MAC_MDIO_RD_DATA */
5382 /*
5383  * RD_DATA (R)
5384  *
5385  * Read Data is available if READY=1 after a transfer has been started. RD_DATA represents the content of the management data field of the read transfer.
5386  */
5387 #define TSW_TSNPORT_MAC_MAC_MDIO_RD_DATA_RD_DATA_MASK (0xFFFFU)
5388 #define TSW_TSNPORT_MAC_MAC_MDIO_RD_DATA_RD_DATA_SHIFT (0U)
5389 #define TSW_TSNPORT_MAC_MAC_MDIO_RD_DATA_RD_DATA_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_RD_DATA_RD_DATA_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_RD_DATA_RD_DATA_SHIFT)
5390 
5391 /* Bitfield definition for register of struct array TSNPORT: MAC_MDIO_WR_DATA */
5392 /*
5393  * WR_DATA (R/W)
5394  *
5395  * Data is used for the management data field after a write transfer has been started
5396  */
5397 #define TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_MASK (0xFFFFU)
5398 #define TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_SHIFT (0U)
5399 #define TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_MASK)
5400 #define TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_SHIFT)
5401 
5402 /* Bitfield definition for register of struct array TSNPORT: MAC_IRQ_CTRL */
5403 /*
5404  * CAIF (R/W)
5405  *
5406  * Clock activity interrupt flag
5407  * 0 – no interrupt
5408  * 1 – interrupt pending
5409  * See Chapter 11.2.3 for details.
5410  */
5411 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_MASK (0x800U)
5412 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_SHIFT (11U)
5413 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_SHIFT) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_MASK)
5414 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_MASK) >> TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_SHIFT)
5415 
5416 /*
5417  * SWIF (R/W)
5418  *
5419  * Safety warning interrupt flag
5420  * 0 – no interrupt
5421  * 1 – interrupt pending
5422  * See Chapter 11.2.2 for details
5423  */
5424 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_MASK (0x400U)
5425 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_SHIFT (10U)
5426 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_SHIFT) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_MASK)
5427 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_MASK) >> TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_SHIFT)
5428 
5429 /*
5430  * SEIF (R/W)
5431  *
5432  * Safety Error Interrupt Flag
5433  * 0 – no interrupt
5434  * 1 – interrupt pending
5435  * If SEN=1 and if there is a mismatch between both instances of the logic core of
5436  * LLEMAC-1G then this results in SEIF=1, TX_EN=0 and RX_EN=0.
5437  */
5438 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_MASK (0x200U)
5439 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_SHIFT (9U)
5440 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_SHIFT) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_MASK)
5441 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_MASK) >> TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_SHIFT)
5442 
5443 /*
5444  * MDIF (R/W)
5445  *
5446  * MDIO Interrupt Flag
5447  * 1 – A transfer has been finished
5448  * 0 – No transfer done
5449  */
5450 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_MASK (0x100U)
5451 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_SHIFT (8U)
5452 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_SHIFT) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_MASK)
5453 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_MASK) >> TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_SHIFT)
5454 
5455 /*
5456  * CAIE (R/W)
5457  *
5458  * Clock activity interrupt enable
5459  * 0 – CAIF disabled
5460  * 1 – CAIF enabled
5461  */
5462 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_MASK (0x8U)
5463 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_SHIFT (3U)
5464 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_SHIFT) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_MASK)
5465 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_MASK) >> TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_SHIFT)
5466 
5467 /*
5468  * SWIE (R/W)
5469  *
5470  * Safety warning interrupt enable
5471  * 0 – SWIF disabled
5472  * 1 – SWIF enabled
5473  */
5474 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_MASK (0x4U)
5475 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_SHIFT (2U)
5476 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_SHIFT) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_MASK)
5477 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_MASK) >> TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_SHIFT)
5478 
5479 /*
5480  * MDIE (R/W)
5481  *
5482  * MDIO Interrupt Enable
5483  * 0 – Disabled
5484  * 1 – Enabled
5485  */
5486 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_MASK (0x1U)
5487 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_SHIFT (0U)
5488 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_SHIFT) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_MASK)
5489 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_MASK) >> TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_SHIFT)
5490 
5491 /* Bitfield definition for register of struct array TSNPORT: RTC_CR */
5492 /*
5493  * TAIE (R/W)
5494  *
5495  * Timer A interrupt enable: interrupt enabled when 1
5496  */
5497 #define TSW_TSNPORT_RTC_CR_TAIE_MASK (0x8U)
5498 #define TSW_TSNPORT_RTC_CR_TAIE_SHIFT (3U)
5499 #define TSW_TSNPORT_RTC_CR_TAIE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_CR_TAIE_SHIFT) & TSW_TSNPORT_RTC_CR_TAIE_MASK)
5500 #define TSW_TSNPORT_RTC_CR_TAIE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_CR_TAIE_MASK) >> TSW_TSNPORT_RTC_CR_TAIE_SHIFT)
5501 
5502 /*
5503  * TAEN (R/W)
5504  *
5505  * Timer A enable: timer enabled when 1
5506  */
5507 #define TSW_TSNPORT_RTC_CR_TAEN_MASK (0x4U)
5508 #define TSW_TSNPORT_RTC_CR_TAEN_SHIFT (2U)
5509 #define TSW_TSNPORT_RTC_CR_TAEN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_CR_TAEN_SHIFT) & TSW_TSNPORT_RTC_CR_TAEN_MASK)
5510 #define TSW_TSNPORT_RTC_CR_TAEN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_CR_TAEN_MASK) >> TSW_TSNPORT_RTC_CR_TAEN_SHIFT)
5511 
5512 /*
5513  * ALIE (R/W)
5514  *
5515  * Alarm interrupt enable: alarm interrupt enabled when 1
5516  */
5517 #define TSW_TSNPORT_RTC_CR_ALIE_MASK (0x2U)
5518 #define TSW_TSNPORT_RTC_CR_ALIE_SHIFT (1U)
5519 #define TSW_TSNPORT_RTC_CR_ALIE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_CR_ALIE_SHIFT) & TSW_TSNPORT_RTC_CR_ALIE_MASK)
5520 #define TSW_TSNPORT_RTC_CR_ALIE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_CR_ALIE_MASK) >> TSW_TSNPORT_RTC_CR_ALIE_SHIFT)
5521 
5522 /* Bitfield definition for register of struct array TSNPORT: RTC_SR */
5523 /*
5524  * TAIS (R/WC)
5525  *
5526  * Timer A Interrupt Status: set at rising edge of “timer_clk_a”, write 1 to clear
5527  */
5528 #define TSW_TSNPORT_RTC_SR_TAIS_MASK (0x8U)
5529 #define TSW_TSNPORT_RTC_SR_TAIS_SHIFT (3U)
5530 #define TSW_TSNPORT_RTC_SR_TAIS_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_SR_TAIS_SHIFT) & TSW_TSNPORT_RTC_SR_TAIS_MASK)
5531 #define TSW_TSNPORT_RTC_SR_TAIS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_SR_TAIS_MASK) >> TSW_TSNPORT_RTC_SR_TAIS_SHIFT)
5532 
5533 /*
5534  * ALIS (RO)
5535  *
5536  * ALIS ro Alarm Interrupt Status: Always set while RTC-Time >= Alarm-Time
5537  */
5538 #define TSW_TSNPORT_RTC_SR_ALIS_MASK (0x2U)
5539 #define TSW_TSNPORT_RTC_SR_ALIS_SHIFT (1U)
5540 #define TSW_TSNPORT_RTC_SR_ALIS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_SR_ALIS_MASK) >> TSW_TSNPORT_RTC_SR_ALIS_SHIFT)
5541 
5542 /* Bitfield definition for register of struct array TSNPORT: RTC_CT_CURTIME_NS */
5543 /*
5544  * CT_NS (RO/WU)
5545  *
5546  * Local Time (nanosecond part): Update can be triggered by write access to this register. Value range from 0 – 999999999.
5547  */
5548 #define TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_MASK (0x3FFFFFFFUL)
5549 #define TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_SHIFT (0U)
5550 #define TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_SHIFT) & TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_MASK)
5551 #define TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_MASK) >> TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_SHIFT)
5552 
5553 /* Bitfield definition for register of struct array TSNPORT: RTC_CT_CURTIME_SEC */
5554 /*
5555  * CT_SEC (RO)
5556  *
5557  * Current Time (second part): Update can be triggered by write access to register CURTIME_NS.
5558  */
5559 #define TSW_TSNPORT_RTC_CT_CURTIME_SEC_CT_SEC_MASK (0xFFFFFFFFUL)
5560 #define TSW_TSNPORT_RTC_CT_CURTIME_SEC_CT_SEC_SHIFT (0U)
5561 #define TSW_TSNPORT_RTC_CT_CURTIME_SEC_CT_SEC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_CT_CURTIME_SEC_CT_SEC_MASK) >> TSW_TSNPORT_RTC_CT_CURTIME_SEC_CT_SEC_SHIFT)
5562 
5563 /* Bitfield definition for register of struct array TSNPORT: RTC_CT_TIMER_INCR */
5564 /*
5565  * NS (RW)
5566  *
5567  * Local time increment – nanoseconds (integer)
5568  */
5569 #define TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_MASK (0xFF000000UL)
5570 #define TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_SHIFT (24U)
5571 #define TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_SHIFT) & TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_MASK)
5572 #define TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_MASK) >> TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_SHIFT)
5573 
5574 /*
5575  * FNS (RW)
5576  *
5577  * Local time increment – fractional ns, unsigned, in (1 / 2^24) n
5578  */
5579 #define TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_MASK (0xFFFFFFUL)
5580 #define TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_SHIFT (0U)
5581 #define TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_SHIFT) & TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_MASK)
5582 #define TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_MASK) >> TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_SHIFT)
5583 
5584 /* Bitfield definition for register of struct array TSNPORT: RTC_OFS_NS */
5585 /*
5586  * OFS_NS (R/W)
5587  *
5588  * Real Time Offset (nanoseconds part). Valid value range from 0 – 999999999.
5589  */
5590 #define TSW_TSNPORT_RTC_OFS_NS_OFS_NS_MASK (0x3FFFFFFFUL)
5591 #define TSW_TSNPORT_RTC_OFS_NS_OFS_NS_SHIFT (0U)
5592 #define TSW_TSNPORT_RTC_OFS_NS_OFS_NS_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_OFS_NS_OFS_NS_SHIFT) & TSW_TSNPORT_RTC_OFS_NS_OFS_NS_MASK)
5593 #define TSW_TSNPORT_RTC_OFS_NS_OFS_NS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_OFS_NS_OFS_NS_MASK) >> TSW_TSNPORT_RTC_OFS_NS_OFS_NS_SHIFT)
5594 
5595 /* Bitfield definition for register of struct array TSNPORT: RTC_OFS_SL */
5596 /*
5597  * OFS_SL (R/W)
5598  *
5599  * 48 Bit Real Time Offset (seconds lo part)
5600  */
5601 #define TSW_TSNPORT_RTC_OFS_SL_OFS_SL_MASK (0xFFFFFFFFUL)
5602 #define TSW_TSNPORT_RTC_OFS_SL_OFS_SL_SHIFT (0U)
5603 #define TSW_TSNPORT_RTC_OFS_SL_OFS_SL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_OFS_SL_OFS_SL_SHIFT) & TSW_TSNPORT_RTC_OFS_SL_OFS_SL_MASK)
5604 #define TSW_TSNPORT_RTC_OFS_SL_OFS_SL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_OFS_SL_OFS_SL_MASK) >> TSW_TSNPORT_RTC_OFS_SL_OFS_SL_SHIFT)
5605 
5606 /* Bitfield definition for register of struct array TSNPORT: RTC_OFS_SH */
5607 /*
5608  * OFS_SH (R/W)
5609  *
5610  * 48 Bit Real Time Offset (seconds hi part)
5611  */
5612 #define TSW_TSNPORT_RTC_OFS_SH_OFS_SH_MASK (0xFFFFU)
5613 #define TSW_TSNPORT_RTC_OFS_SH_OFS_SH_SHIFT (0U)
5614 #define TSW_TSNPORT_RTC_OFS_SH_OFS_SH_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_OFS_SH_OFS_SH_SHIFT) & TSW_TSNPORT_RTC_OFS_SH_OFS_SH_MASK)
5615 #define TSW_TSNPORT_RTC_OFS_SH_OFS_SH_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_OFS_SH_OFS_SH_MASK) >> TSW_TSNPORT_RTC_OFS_SH_OFS_SH_SHIFT)
5616 
5617 /* Bitfield definition for register of struct array TSNPORT: RTC_OFS_CH */
5618 /*
5619  * SEXT (RO)
5620  *
5621  * Real Time Offset Change – sign extension of SFNS (Bit 23)
5622  */
5623 #define TSW_TSNPORT_RTC_OFS_CH_SEXT_MASK (0xFF000000UL)
5624 #define TSW_TSNPORT_RTC_OFS_CH_SEXT_SHIFT (24U)
5625 #define TSW_TSNPORT_RTC_OFS_CH_SEXT_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_OFS_CH_SEXT_MASK) >> TSW_TSNPORT_RTC_OFS_CH_SEXT_SHIFT)
5626 
5627 /*
5628  * SFNS (R/W)
5629  *
5630  * Real Time Offset Change in fractional nanoseconds, signed value; value range from -2^23 / 2^24 to (2^23-1) / 2^24 nanoseconds.
5631  */
5632 #define TSW_TSNPORT_RTC_OFS_CH_SFNS_MASK (0xFFFFFFUL)
5633 #define TSW_TSNPORT_RTC_OFS_CH_SFNS_SHIFT (0U)
5634 #define TSW_TSNPORT_RTC_OFS_CH_SFNS_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_OFS_CH_SFNS_SHIFT) & TSW_TSNPORT_RTC_OFS_CH_SFNS_MASK)
5635 #define TSW_TSNPORT_RTC_OFS_CH_SFNS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_OFS_CH_SFNS_MASK) >> TSW_TSNPORT_RTC_OFS_CH_SFNS_SHIFT)
5636 
5637 /* Bitfield definition for register of struct array TSNPORT: RTC_ALARM_NS */
5638 /*
5639  * AL_NS (R/W)
5640  *
5641  * Alarm Time (nanoseconds part). Valid value range from 0 – 999999999.
5642  */
5643 #define TSW_TSNPORT_RTC_ALARM_NS_AL_NS_MASK (0x3FFFFFFFUL)
5644 #define TSW_TSNPORT_RTC_ALARM_NS_AL_NS_SHIFT (0U)
5645 #define TSW_TSNPORT_RTC_ALARM_NS_AL_NS_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_ALARM_NS_AL_NS_SHIFT) & TSW_TSNPORT_RTC_ALARM_NS_AL_NS_MASK)
5646 #define TSW_TSNPORT_RTC_ALARM_NS_AL_NS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_ALARM_NS_AL_NS_MASK) >> TSW_TSNPORT_RTC_ALARM_NS_AL_NS_SHIFT)
5647 
5648 /* Bitfield definition for register of struct array TSNPORT: RTC_ALARM_SL */
5649 /*
5650  * AL_SL (R/W)
5651  *
5652  * Alarm Time (seconds lo part)
5653  */
5654 #define TSW_TSNPORT_RTC_ALARM_SL_AL_SL_MASK (0xFFFFFFFFUL)
5655 #define TSW_TSNPORT_RTC_ALARM_SL_AL_SL_SHIFT (0U)
5656 #define TSW_TSNPORT_RTC_ALARM_SL_AL_SL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_ALARM_SL_AL_SL_SHIFT) & TSW_TSNPORT_RTC_ALARM_SL_AL_SL_MASK)
5657 #define TSW_TSNPORT_RTC_ALARM_SL_AL_SL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_ALARM_SL_AL_SL_MASK) >> TSW_TSNPORT_RTC_ALARM_SL_AL_SL_SHIFT)
5658 
5659 /* Bitfield definition for register of struct array TSNPORT: RTC_ALARM_SH */
5660 /*
5661  * AL_SH (R/W)
5662  *
5663  * Alarm Time (seconds hi part)
5664  */
5665 #define TSW_TSNPORT_RTC_ALARM_SH_AL_SH_MASK (0xFFFFU)
5666 #define TSW_TSNPORT_RTC_ALARM_SH_AL_SH_SHIFT (0U)
5667 #define TSW_TSNPORT_RTC_ALARM_SH_AL_SH_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_ALARM_SH_AL_SH_SHIFT) & TSW_TSNPORT_RTC_ALARM_SH_AL_SH_MASK)
5668 #define TSW_TSNPORT_RTC_ALARM_SH_AL_SH_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_ALARM_SH_AL_SH_MASK) >> TSW_TSNPORT_RTC_ALARM_SH_AL_SH_SHIFT)
5669 
5670 /* Bitfield definition for register of struct array TSNPORT: RTC_TIMER_A_PERIOD */
5671 /*
5672  * PERIOD_NS (R/W)
5673  *
5674  * Timer A Period in ns. This is the period of the timer until the next event, but the half-period of the signal “timer_a_clk”.
5675  */
5676 #define TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_MASK (0x1FFFFFFFUL)
5677 #define TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_SHIFT (0U)
5678 #define TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_SHIFT) & TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_MASK)
5679 #define TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_MASK) >> TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_SHIFT)
5680 
5681 /* Bitfield definition for register of struct array TSNPORT: TSYN_CR */
5682 /*
5683  * TMR_ALD (R/W)
5684  *
5685  * Timer Auto Load: automatic reloading of timer when reaching 0. Done flag stays set after countdown. Used for periodic events, when following event shall not be delayed by host interaction.
5686  */
5687 #define TSW_TSNPORT_TSYN_CR_TMR_ALD_MASK (0x1F0000UL)
5688 #define TSW_TSNPORT_TSYN_CR_TMR_ALD_SHIFT (16U)
5689 #define TSW_TSNPORT_TSYN_CR_TMR_ALD_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSYN_CR_TMR_ALD_SHIFT) & TSW_TSNPORT_TSYN_CR_TMR_ALD_MASK)
5690 #define TSW_TSNPORT_TSYN_CR_TMR_ALD_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_CR_TMR_ALD_MASK) >> TSW_TSNPORT_TSYN_CR_TMR_ALD_SHIFT)
5691 
5692 /*
5693  * TMR_EN (R/W)
5694  *
5695  * Timer Enable: every bit corresponds to Timer 0 – 4
5696  */
5697 #define TSW_TSNPORT_TSYN_CR_TMR_EN_MASK (0x1F00U)
5698 #define TSW_TSNPORT_TSYN_CR_TMR_EN_SHIFT (8U)
5699 #define TSW_TSNPORT_TSYN_CR_TMR_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSYN_CR_TMR_EN_SHIFT) & TSW_TSNPORT_TSYN_CR_TMR_EN_MASK)
5700 #define TSW_TSNPORT_TSYN_CR_TMR_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_CR_TMR_EN_MASK) >> TSW_TSNPORT_TSYN_CR_TMR_EN_SHIFT)
5701 
5702 /*
5703  * TMRIE (R/W)
5704  *
5705  * Timer Interrupt Enable
5706  */
5707 #define TSW_TSNPORT_TSYN_CR_TMRIE_MASK (0x4U)
5708 #define TSW_TSNPORT_TSYN_CR_TMRIE_SHIFT (2U)
5709 #define TSW_TSNPORT_TSYN_CR_TMRIE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSYN_CR_TMRIE_SHIFT) & TSW_TSNPORT_TSYN_CR_TMRIE_MASK)
5710 #define TSW_TSNPORT_TSYN_CR_TMRIE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_CR_TMRIE_MASK) >> TSW_TSNPORT_TSYN_CR_TMRIE_SHIFT)
5711 
5712 /*
5713  * RXIE (R/W)
5714  *
5715  * Rx Interrupt Enable
5716  */
5717 #define TSW_TSNPORT_TSYN_CR_RXIE_MASK (0x2U)
5718 #define TSW_TSNPORT_TSYN_CR_RXIE_SHIFT (1U)
5719 #define TSW_TSNPORT_TSYN_CR_RXIE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSYN_CR_RXIE_SHIFT) & TSW_TSNPORT_TSYN_CR_RXIE_MASK)
5720 #define TSW_TSNPORT_TSYN_CR_RXIE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_CR_RXIE_MASK) >> TSW_TSNPORT_TSYN_CR_RXIE_SHIFT)
5721 
5722 /*
5723  * TXIE (R/W)
5724  *
5725  * Tx Interrupt Enable
5726  */
5727 #define TSW_TSNPORT_TSYN_CR_TXIE_MASK (0x1U)
5728 #define TSW_TSNPORT_TSYN_CR_TXIE_SHIFT (0U)
5729 #define TSW_TSNPORT_TSYN_CR_TXIE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSYN_CR_TXIE_SHIFT) & TSW_TSNPORT_TSYN_CR_TXIE_MASK)
5730 #define TSW_TSNPORT_TSYN_CR_TXIE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_CR_TXIE_MASK) >> TSW_TSNPORT_TSYN_CR_TXIE_SHIFT)
5731 
5732 /* Bitfield definition for register of struct array TSNPORT: TSYN_SR */
5733 /*
5734  * TMR_DN (R/WC)
5735  *
5736  * Timer Done: 1 when timer reached 0
5737  */
5738 #define TSW_TSNPORT_TSYN_SR_TMR_DN_MASK (0x1F00U)
5739 #define TSW_TSNPORT_TSYN_SR_TMR_DN_SHIFT (8U)
5740 #define TSW_TSNPORT_TSYN_SR_TMR_DN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSYN_SR_TMR_DN_SHIFT) & TSW_TSNPORT_TSYN_SR_TMR_DN_MASK)
5741 #define TSW_TSNPORT_TSYN_SR_TMR_DN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_SR_TMR_DN_MASK) >> TSW_TSNPORT_TSYN_SR_TMR_DN_SHIFT)
5742 
5743 /*
5744  * TMRIS (RO)
5745  *
5746  * Timer Interrupt Status: OR’ed (TMR_DN AND TMR_EN) flags. 1 when timer is enabled and countdown is done
5747  */
5748 #define TSW_TSNPORT_TSYN_SR_TMRIS_MASK (0x4U)
5749 #define TSW_TSNPORT_TSYN_SR_TMRIS_SHIFT (2U)
5750 #define TSW_TSNPORT_TSYN_SR_TMRIS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_SR_TMRIS_MASK) >> TSW_TSNPORT_TSYN_SR_TMRIS_SHIFT)
5751 
5752 /*
5753  * RXIS (RO)
5754  *
5755  * Rx Interrupt Status, RX buffer data available equal to PTP_RX_STS.AV)
5756  */
5757 #define TSW_TSNPORT_TSYN_SR_RXIS_MASK (0x2U)
5758 #define TSW_TSNPORT_TSYN_SR_RXIS_SHIFT (1U)
5759 #define TSW_TSNPORT_TSYN_SR_RXIS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_SR_RXIS_MASK) >> TSW_TSNPORT_TSYN_SR_RXIS_SHIFT)
5760 
5761 /*
5762  * TXIS (RO)
5763  *
5764  * Tx Done Interrupt Status: OR’ed PTP_TX_DONE
5765  */
5766 #define TSW_TSNPORT_TSYN_SR_TXIS_MASK (0x1U)
5767 #define TSW_TSNPORT_TSYN_SR_TXIS_SHIFT (0U)
5768 #define TSW_TSNPORT_TSYN_SR_TXIS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_SR_TXIS_MASK) >> TSW_TSNPORT_TSYN_SR_TXIS_SHIFT)
5769 
5770 /* Bitfield definition for register of struct array TSNPORT: TSYN_PTP_TX_STS */
5771 /*
5772  * STS (RO)
5773  *
5774  * Transmission status of PTP TX bin n (bit 0 – 7 correspond to tx bin 0 – 7). 1: transmission pending
5775  */
5776 #define TSW_TSNPORT_TSYN_PTP_TX_STS_STS_MASK (0xFFU)
5777 #define TSW_TSNPORT_TSYN_PTP_TX_STS_STS_SHIFT (0U)
5778 #define TSW_TSNPORT_TSYN_PTP_TX_STS_STS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_PTP_TX_STS_STS_MASK) >> TSW_TSNPORT_TSYN_PTP_TX_STS_STS_SHIFT)
5779 
5780 /* Bitfield definition for register of struct array TSNPORT: TSYN_PTP_TX_DONE */
5781 /*
5782  * DONE (R/WC)
5783  *
5784  * Transmission done status of PTP TX bin n (bit 0 – 7 correspond to tx bin 0 – 7). 1: transmission done.
5785  * Writing a ‘1’ clears corresponding bit..
5786  */
5787 #define TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_MASK (0xFFU)
5788 #define TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_SHIFT (0U)
5789 #define TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_SHIFT) & TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_MASK)
5790 #define TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_MASK) >> TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_SHIFT)
5791 
5792 /* Bitfield definition for register of struct array TSNPORT: TSYN_PTP_TX_TRIG */
5793 /*
5794  * TRIG (WO)
5795  *
5796  * Trigger PTP TX bin n (bit 0 – 7 correspond to tx bin 0 –7). Writing ‘1’ will trigger transmission. Corresponding bit PTP_TX_STS.STS(n) will be set immediately.
5797  */
5798 #define TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_MASK (0xFFU)
5799 #define TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_SHIFT (0U)
5800 #define TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_SHIFT) & TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_MASK)
5801 #define TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_MASK) >> TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_SHIFT)
5802 
5803 /* Bitfield definition for register of struct array TSNPORT: TSYN_PTP_RX_STS */
5804 /*
5805  * OV (R/WC)
5806  *
5807  * FIFO overflow flag. PTP frame has been received and there was no free buffer available. Data has been lost.
5808  */
5809 #define TSW_TSNPORT_TSYN_PTP_RX_STS_OV_MASK (0x80000000UL)
5810 #define TSW_TSNPORT_TSYN_PTP_RX_STS_OV_SHIFT (31U)
5811 #define TSW_TSNPORT_TSYN_PTP_RX_STS_OV_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSYN_PTP_RX_STS_OV_SHIFT) & TSW_TSNPORT_TSYN_PTP_RX_STS_OV_MASK)
5812 #define TSW_TSNPORT_TSYN_PTP_RX_STS_OV_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_PTP_RX_STS_OV_MASK) >> TSW_TSNPORT_TSYN_PTP_RX_STS_OV_SHIFT)
5813 
5814 /*
5815  * AV_NXT (R/W)
5816  *
5817  * Read access: buffer data available – reading data from RX_BUF is valid.
5818  * Write access: switch to next RX buffer – shall only be done when buffer not empty (AV=1). Use field RX_SEL as indication when rx buffer switch has been done.
5819  */
5820 #define TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_MASK (0x40000000UL)
5821 #define TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_SHIFT (30U)
5822 #define TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_SHIFT) & TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_MASK)
5823 #define TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_MASK) >> TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_SHIFT)
5824 
5825 /*
5826  * RX_SEL (RO)
5827  *
5828  * Current selected RX buffer for reading (0-7). Can be used to determine when RX buffer has been switched after setting PTP_RX_STS.NXT
5829  */
5830 #define TSW_TSNPORT_TSYN_PTP_RX_STS_RX_SEL_MASK (0x7U)
5831 #define TSW_TSNPORT_TSYN_PTP_RX_STS_RX_SEL_SHIFT (0U)
5832 #define TSW_TSNPORT_TSYN_PTP_RX_STS_RX_SEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_PTP_RX_STS_RX_SEL_MASK) >> TSW_TSNPORT_TSYN_PTP_RX_STS_RX_SEL_SHIFT)
5833 
5834 /* Bitfield definition for register of struct array TSNPORT: TSYN_TMR0 */
5835 /*
5836  * PERIOD (R/W)
5837  *
5838  * Period in ticks, ticks based on register HCLKDIV and host clock <sys_clk>.
5839  */
5840 #define TSW_TSNPORT_TSYNTMR_PERIOD_MASK (0xFFFFFUL)
5841 #define TSW_TSNPORT_TSYNTMR_PERIOD_SHIFT (0U)
5842 #define TSW_TSNPORT_TSYNTMR_PERIOD_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSYNTMR_PERIOD_SHIFT) & TSW_TSNPORT_TSYNTMR_PERIOD_MASK)
5843 #define TSW_TSNPORT_TSYNTMR_PERIOD_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYNTMR_PERIOD_MASK) >> TSW_TSNPORT_TSYNTMR_PERIOD_SHIFT)
5844 
5845 /* Bitfield definition for register of struct array TSNPORT: TSYN_HCLKDIV */
5846 /*
5847  * PERIOD (R/W)
5848  *
5849  * Period in host clocks <sys_clk>. Host clock shall be scaled to ticks of 1/1024th second. Ticks are used by timer TMR0 – TMR4.
5850  */
5851 #define TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_MASK (0xFFFFFUL)
5852 #define TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_SHIFT (0U)
5853 #define TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_SHIFT) & TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_MASK)
5854 #define TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_MASK) >> TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_SHIFT)
5855 
5856 /* Bitfield definition for register of struct array TSNPORT: TSYN_RXBUF_RX_FRAME_LENGTH_BYTES */
5857 /*
5858  * RX_FRAME_LENGTH_BYTES (RO)
5859  *
5860  * RX frame length bytes [11:0]
5861  */
5862 #define TSW_TSNPORT_TSYN_RXBUF_RX_FRAME_LENGTH_BYTES_RX_FRAME_LENGTH_BYTES_MASK (0xFFFU)
5863 #define TSW_TSNPORT_TSYN_RXBUF_RX_FRAME_LENGTH_BYTES_RX_FRAME_LENGTH_BYTES_SHIFT (0U)
5864 #define TSW_TSNPORT_TSYN_RXBUF_RX_FRAME_LENGTH_BYTES_RX_FRAME_LENGTH_BYTES_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_RXBUF_RX_FRAME_LENGTH_BYTES_RX_FRAME_LENGTH_BYTES_MASK) >> TSW_TSNPORT_TSYN_RXBUF_RX_FRAME_LENGTH_BYTES_RX_FRAME_LENGTH_BYTES_SHIFT)
5865 
5866 /* Bitfield definition for register of struct array TSNPORT: TSYN_RXBUF_RX_TIME_STAMP_L */
5867 /*
5868  * RX_TIMESTAMP_LOW (RO)
5869  *
5870  * RX Timestamp [31:0]
5871  */
5872 #define TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_L_RX_TIMESTAMP_LOW_MASK (0xFFFFFFFFUL)
5873 #define TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_L_RX_TIMESTAMP_LOW_SHIFT (0U)
5874 #define TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_L_RX_TIMESTAMP_LOW_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_L_RX_TIMESTAMP_LOW_MASK) >> TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_L_RX_TIMESTAMP_LOW_SHIFT)
5875 
5876 /* Bitfield definition for register of struct array TSNPORT: TSYN_RXBUF_RX_TIME_STAMP_H */
5877 /*
5878  * RX_TIMESTAMP_HIGH (RO)
5879  *
5880  * RX Timestamp [63:32]
5881  */
5882 #define TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_H_RX_TIMESTAMP_HIGH_MASK (0xFFFFFFFFUL)
5883 #define TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_H_RX_TIMESTAMP_HIGH_SHIFT (0U)
5884 #define TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_H_RX_TIMESTAMP_HIGH_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_H_RX_TIMESTAMP_HIGH_MASK) >> TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_H_RX_TIMESTAMP_HIGH_SHIFT)
5885 
5886 /* Bitfield definition for register of struct array TSNPORT: TSYN_RXBUF_DATA_WORD0 */
5887 /*
5888  * RXBUF_DATA_WORD (RO)
5889  *
5890  * RXBUF_DATA_WORD
5891  */
5892 #define TSW_TSNPORT_RXDATA_RXBUF_DATA_WORD_MASK (0xFFFFFFFFUL)
5893 #define TSW_TSNPORT_RXDATA_RXBUF_DATA_WORD_SHIFT (0U)
5894 #define TSW_TSNPORT_RXDATA_RXBUF_DATA_WORD_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXDATA_RXBUF_DATA_WORD_MASK) >> TSW_TSNPORT_RXDATA_RXBUF_DATA_WORD_SHIFT)
5895 
5896 /* Bitfield definition for register of struct array TSNPORT: TSYN_TXBUF_BIN0_DATA_WORD0 */
5897 /*
5898  * TXBUF_DATA (WO)
5899  *
5900  * TXBUF_DATA
5901  */
5902 #define TSW_TSNPORT_BIN_TXDATA_TXBUF_DATA_MASK (0xFFFFFFFFUL)
5903 #define TSW_TSNPORT_BIN_TXDATA_TXBUF_DATA_SHIFT (0U)
5904 #define TSW_TSNPORT_BIN_TXDATA_TXBUF_DATA_SET(x) (((uint32_t)(x) << TSW_TSNPORT_BIN_TXDATA_TXBUF_DATA_SHIFT) & TSW_TSNPORT_BIN_TXDATA_TXBUF_DATA_MASK)
5905 #define TSW_TSNPORT_BIN_TXDATA_TXBUF_DATA_GET(x) (((uint32_t)(x) & TSW_TSNPORT_BIN_TXDATA_TXBUF_DATA_MASK) >> TSW_TSNPORT_BIN_TXDATA_TXBUF_DATA_SHIFT)
5906 
5907 /* Bitfield definition for register of struct array TSNPORT: TSYN_TXBUF_TQUE_AND_TX_LEN */
5908 /*
5909  * TXBUF_TQUE (WO)
5910  *
5911  * TXBUF_TQUE
5912  */
5913 #define TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TQUE_MASK (0x7000000UL)
5914 #define TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TQUE_SHIFT (24U)
5915 #define TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TQUE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TQUE_SHIFT) & TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TQUE_MASK)
5916 #define TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TQUE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TQUE_MASK) >> TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TQUE_SHIFT)
5917 
5918 /*
5919  * TXBUF_TX_LEN (WO)
5920  *
5921  * TXBUF_TX_LEN
5922  */
5923 #define TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TX_LEN_MASK (0xFFU)
5924 #define TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TX_LEN_SHIFT (0U)
5925 #define TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TX_LEN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TX_LEN_SHIFT) & TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TX_LEN_MASK)
5926 #define TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TX_LEN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TX_LEN_MASK) >> TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TX_LEN_SHIFT)
5927 
5928 /* Bitfield definition for register of struct array TSNPORT: TSYN_TXBUF_TX_TIMESTAMP_L */
5929 /*
5930  * TXBUF_TX_TIMESTAMP_L (RO)
5931  *
5932  * TXBUF_TX_TIMESTAMP_L
5933  */
5934 #define TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_L_TXBUF_TX_TIMESTAMP_L_MASK (0xFFFFFFFFUL)
5935 #define TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_L_TXBUF_TX_TIMESTAMP_L_SHIFT (0U)
5936 #define TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_L_TXBUF_TX_TIMESTAMP_L_GET(x) (((uint32_t)(x) & TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_L_TXBUF_TX_TIMESTAMP_L_MASK) >> TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_L_TXBUF_TX_TIMESTAMP_L_SHIFT)
5937 
5938 /* Bitfield definition for register of struct array TSNPORT: TSYN_TXBUF_TX_TIMESTAMP_H */
5939 /*
5940  * TXBUF_TX_TIMESTAMP_H (RO)
5941  *
5942  * TXBUF_TX_TIMESTAMP_H
5943  */
5944 #define TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_H_TXBUF_TX_TIMESTAMP_H_MASK (0xFFFFFFFFUL)
5945 #define TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_H_TXBUF_TX_TIMESTAMP_H_SHIFT (0U)
5946 #define TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_H_TXBUF_TX_TIMESTAMP_H_GET(x) (((uint32_t)(x) & TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_H_TXBUF_TX_TIMESTAMP_H_MASK) >> TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_H_TXBUF_TX_TIMESTAMP_H_SHIFT)
5947 
5948 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_HWCFG1 */
5949 /*
5950  * LWIDTH (RO)
5951  *
5952  * Scheduler list address width (IP core parameter LWIDTH)
5953  */
5954 #define TSW_TSNPORT_TSN_SHAPER_HWCFG1_LWIDTH_MASK (0xFF000000UL)
5955 #define TSW_TSNPORT_TSN_SHAPER_HWCFG1_LWIDTH_SHIFT (24U)
5956 #define TSW_TSNPORT_TSN_SHAPER_HWCFG1_LWIDTH_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_HWCFG1_LWIDTH_MASK) >> TSW_TSNPORT_TSN_SHAPER_HWCFG1_LWIDTH_SHIFT)
5957 
5958 /*
5959  * TQC (RO)
5960  *
5961  * Traffic queue count (IP core parameter TQC)
5962  */
5963 #define TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQC_MASK (0xFF0000UL)
5964 #define TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQC_SHIFT (16U)
5965 #define TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQC_MASK) >> TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQC_SHIFT)
5966 
5967 /*
5968  * TQD (RO)
5969  *
5970  * Traffic queue depth (IP core parameter TQD)
5971  */
5972 #define TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQD_MASK (0xFF00U)
5973 #define TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQD_SHIFT (8U)
5974 #define TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQD_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQD_MASK) >> TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQD_SHIFT)
5975 
5976 /*
5977  * DW (RO)
5978  *
5979  * Traffic queue data width (Bytes); fixed to value 4 within
5980  * IP core
5981  */
5982 #define TSW_TSNPORT_TSN_SHAPER_HWCFG1_DW_MASK (0xFFU)
5983 #define TSW_TSNPORT_TSN_SHAPER_HWCFG1_DW_SHIFT (0U)
5984 #define TSW_TSNPORT_TSN_SHAPER_HWCFG1_DW_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_HWCFG1_DW_MASK) >> TSW_TSNPORT_TSN_SHAPER_HWCFG1_DW_SHIFT)
5985 
5986 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_TQAV */
5987 /*
5988  * AVIE (R/W)
5989  *
5990  * Traffic queue interrupt enable on buffer space available,
5991  * one bit per traffic queue
5992  * Bit[i] = 0: no interrupt
5993  * Bit[i] = 1: interrupt, when AVAIL[i]=1
5994  */
5995 #define TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_MASK (0xFF00U)
5996 #define TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_SHIFT (8U)
5997 #define TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_MASK)
5998 #define TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_MASK) >> TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_SHIFT)
5999 
6000 /*
6001  * AVAIL (RO)
6002  *
6003  * Traffic queue buffer space available for complete packet of size MaxSDU (register MXSDUi)
6004  * Bit[i] = 1: space available
6005  * Bit[i] = 0: no space available or TQ not implemented (I >= TQC)
6006  */
6007 #define TSW_TSNPORT_TSN_SHAPER_TQAV_AVAIL_MASK (0xFFU)
6008 #define TSW_TSNPORT_TSN_SHAPER_TQAV_AVAIL_SHIFT (0U)
6009 #define TSW_TSNPORT_TSN_SHAPER_TQAV_AVAIL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TQAV_AVAIL_MASK) >> TSW_TSNPORT_TSN_SHAPER_TQAV_AVAIL_SHIFT)
6010 
6011 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_TQEM */
6012 /*
6013  * EMPTY (RO)
6014  *
6015  * Traffic queue empty
6016  * Bit[i] = 1: traffic queue i is empty
6017  */
6018 #define TSW_TSNPORT_TSN_SHAPER_TQEM_EMPTY_MASK (0xFFU)
6019 #define TSW_TSNPORT_TSN_SHAPER_TQEM_EMPTY_SHIFT (0U)
6020 #define TSW_TSNPORT_TSN_SHAPER_TQEM_EMPTY_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TQEM_EMPTY_MASK) >> TSW_TSNPORT_TSN_SHAPER_TQEM_EMPTY_SHIFT)
6021 
6022 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_FPST */
6023 /*
6024  * TABLE (R/W)
6025  *
6026  * Frame Preemption Status Table,
6027  * Bit[i] = 1: Preemptable traffic in TQ[i], otherwise
6028  * Express traffic (default)
6029  */
6030 #define TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_MASK (0xFFU)
6031 #define TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_SHIFT (0U)
6032 #define TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_SHIFT) & TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_MASK)
6033 #define TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_MASK) >> TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_SHIFT)
6034 
6035 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_MMCT */
6036 /*
6037  * RQREL (R/W)
6038  *
6039  * Request HOLD-Signal release operation. Will be automatically set to <0>
6040  */
6041 #define TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_MASK (0x2U)
6042 #define TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_SHIFT (1U)
6043 #define TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_SHIFT) & TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_MASK)
6044 #define TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_MASK) >> TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_SHIFT)
6045 
6046 /*
6047  * RQHLD (R/W)
6048  *
6049  * Request HOLD-Signal hold operation. Will be automatically set to <0>.
6050  */
6051 #define TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_MASK (0x1U)
6052 #define TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_SHIFT (0U)
6053 #define TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_SHIFT) & TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_MASK)
6054 #define TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_MASK) >> TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_SHIFT)
6055 
6056 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_HOLDADV */
6057 /*
6058  * VALUE (R/W)
6059  *
6060  * holdAdvance time for TAS operation Set-And-Hold-MAC in <sys_clk> cycles
6061  */
6062 #define TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_MASK (0xFFFFU)
6063 #define TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_SHIFT (0U)
6064 #define TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_SHIFT) & TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_MASK)
6065 #define TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_MASK) >> TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_SHIFT)
6066 
6067 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_MXSDU0 */
6068 /*
6069  * SDU (R/W)
6070  *
6071  * Maximum SDU size for traffic queue n (n = 0 – 7)Returns 0 when n > TQC. Value is size in words (32 bit word size).
6072  */
6073 #define TSW_TSNPORT_MXSDU_SDU_MASK (0xFFFFU)
6074 #define TSW_TSNPORT_MXSDU_SDU_SHIFT (0U)
6075 #define TSW_TSNPORT_MXSDU_SDU_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MXSDU_SDU_SHIFT) & TSW_TSNPORT_MXSDU_SDU_MASK)
6076 #define TSW_TSNPORT_MXSDU_SDU_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MXSDU_SDU_MASK) >> TSW_TSNPORT_MXSDU_SDU_SHIFT)
6077 
6078 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_TXSEL0 */
6079 /*
6080  * CBS_EN (R/W)
6081  *
6082  * CBS enable traffic queue n (n = 0 – 7). Returns 0 when n > TQC. Must be 0 when changing register IDSLPi.
6083  */
6084 #define TSW_TSNPORT_TXSEL_CBS_EN_MASK (0x1U)
6085 #define TSW_TSNPORT_TXSEL_CBS_EN_SHIFT (0U)
6086 #define TSW_TSNPORT_TXSEL_CBS_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TXSEL_CBS_EN_SHIFT) & TSW_TSNPORT_TXSEL_CBS_EN_MASK)
6087 #define TSW_TSNPORT_TXSEL_CBS_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TXSEL_CBS_EN_MASK) >> TSW_TSNPORT_TXSEL_CBS_EN_SHIFT)
6088 
6089 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_IDSEL0 */
6090 /*
6091  * INT (R/W)
6092  *
6093  * CBS idle slope for traffic queue n (n = 0 – 7). Returns
6094  * 0 when n > TQC. The register must only be written
6095  * when TXSELi.CBE_EN=0.
6096  * The idle slope value is defined as (INT + FRACT /
6097  * 65536). The idle slope is set in bits per tick related to
6098  * <tx_clk>.
6099  */
6100 #define TSW_TSNPORT_IDSEL_INT_MASK (0xF0000UL)
6101 #define TSW_TSNPORT_IDSEL_INT_SHIFT (16U)
6102 #define TSW_TSNPORT_IDSEL_INT_SET(x) (((uint32_t)(x) << TSW_TSNPORT_IDSEL_INT_SHIFT) & TSW_TSNPORT_IDSEL_INT_MASK)
6103 #define TSW_TSNPORT_IDSEL_INT_GET(x) (((uint32_t)(x) & TSW_TSNPORT_IDSEL_INT_MASK) >> TSW_TSNPORT_IDSEL_INT_SHIFT)
6104 
6105 /*
6106  * FRACT (R/W)
6107  *
6108  */
6109 #define TSW_TSNPORT_IDSEL_FRACT_MASK (0xFFFFU)
6110 #define TSW_TSNPORT_IDSEL_FRACT_SHIFT (0U)
6111 #define TSW_TSNPORT_IDSEL_FRACT_SET(x) (((uint32_t)(x) << TSW_TSNPORT_IDSEL_FRACT_SHIFT) & TSW_TSNPORT_IDSEL_FRACT_MASK)
6112 #define TSW_TSNPORT_IDSEL_FRACT_GET(x) (((uint32_t)(x) & TSW_TSNPORT_IDSEL_FRACT_MASK) >> TSW_TSNPORT_IDSEL_FRACT_SHIFT)
6113 
6114 /* Bitfield definition for register of struct array TSNPORT: PORT1_QCH0_CFG */
6115 /*
6116  * CQF_IN_ERR (WC)
6117  *
6118  * qch queue in error
6119  */
6120 #define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_MASK (0x100000UL)
6121 #define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_SHIFT (20U)
6122 #define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_SHIFT) & TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_MASK)
6123 #define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_MASK) >> TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_SHIFT)
6124 
6125 /*
6126  * CQF_NUM (R/W)
6127  *
6128  * qch queue destination buffer select
6129  */
6130 #define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_MASK (0x70000UL)
6131 #define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_SHIFT (16U)
6132 #define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_SHIFT) & TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_MASK)
6133 #define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_MASK) >> TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_SHIFT)
6134 
6135 /*
6136  * TAS_GPIO_SEL (R/W)
6137  *
6138  * tas_gpio select
6139  */
6140 #define TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_MASK (0x7000U)
6141 #define TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_SHIFT (12U)
6142 #define TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_SHIFT) & TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_MASK)
6143 #define TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_MASK) >> TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_SHIFT)
6144 
6145 /*
6146  * AXIS_QCH_EN (R/W)
6147  *
6148  * qch queue in select
6149  */
6150 #define TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_MASK (0xFF0U)
6151 #define TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_SHIFT (4U)
6152 #define TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_MASK)
6153 #define TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_MASK) >> TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_SHIFT)
6154 
6155 /*
6156  * CQF_EN (R/W)
6157  *
6158  * qch enable
6159  */
6160 #define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_MASK (0x1U)
6161 #define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_SHIFT (0U)
6162 #define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_MASK)
6163 #define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_MASK) >> TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_SHIFT)
6164 
6165 /* Bitfield definition for register of struct array TSNPORT: PORT1_QCH1_CFG */
6166 /*
6167  * CQF_IN_ERR (WC)
6168  *
6169  * qch queue in error
6170  */
6171 #define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_MASK (0x100000UL)
6172 #define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_SHIFT (20U)
6173 #define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_SHIFT) & TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_MASK)
6174 #define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_MASK) >> TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_SHIFT)
6175 
6176 /*
6177  * CQF_NUM (R/W)
6178  *
6179  * qch queue destination buffer select
6180  */
6181 #define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_MASK (0x70000UL)
6182 #define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_SHIFT (16U)
6183 #define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_SHIFT) & TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_MASK)
6184 #define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_MASK) >> TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_SHIFT)
6185 
6186 /*
6187  * TAS_GPIO_SEL (R/W)
6188  *
6189  * tas_gpio select
6190  */
6191 #define TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_MASK (0x7000U)
6192 #define TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_SHIFT (12U)
6193 #define TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_SHIFT) & TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_MASK)
6194 #define TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_MASK) >> TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_SHIFT)
6195 
6196 /*
6197  * AXIS_QCH_EN (R/W)
6198  *
6199  * qch queue in select
6200  */
6201 #define TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_MASK (0xFF0U)
6202 #define TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_SHIFT (4U)
6203 #define TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_MASK)
6204 #define TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_MASK) >> TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_SHIFT)
6205 
6206 /*
6207  * CQF_EN (R/W)
6208  *
6209  * qch enable
6210  */
6211 #define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_MASK (0x1U)
6212 #define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_SHIFT (0U)
6213 #define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_MASK)
6214 #define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_MASK) >> TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_SHIFT)
6215 
6216 /* Bitfield definition for register of struct array TSNPORT: PORT1_QCH2_CFG */
6217 /*
6218  * CQF_IN_ERR (WC)
6219  *
6220  * qch queue in error
6221  */
6222 #define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_MASK (0x100000UL)
6223 #define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_SHIFT (20U)
6224 #define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_SHIFT) & TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_MASK)
6225 #define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_MASK) >> TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_SHIFT)
6226 
6227 /*
6228  * CQF_NUM (R/W)
6229  *
6230  * qch queue destination buffer select
6231  */
6232 #define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_MASK (0x70000UL)
6233 #define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_SHIFT (16U)
6234 #define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_SHIFT) & TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_MASK)
6235 #define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_MASK) >> TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_SHIFT)
6236 
6237 /*
6238  * TAS_GPIO_SEL (R/W)
6239  *
6240  * tas_gpio select
6241  */
6242 #define TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_MASK (0x7000U)
6243 #define TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_SHIFT (12U)
6244 #define TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_SHIFT) & TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_MASK)
6245 #define TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_MASK) >> TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_SHIFT)
6246 
6247 /*
6248  * AXIS_QCH_EN (R/W)
6249  *
6250  * qch queue in select
6251  */
6252 #define TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_MASK (0xFF0U)
6253 #define TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_SHIFT (4U)
6254 #define TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_MASK)
6255 #define TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_MASK) >> TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_SHIFT)
6256 
6257 /*
6258  * CQF_EN (R/W)
6259  *
6260  * qch enable
6261  */
6262 #define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_MASK (0x1U)
6263 #define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_SHIFT (0U)
6264 #define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_MASK)
6265 #define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_MASK) >> TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_SHIFT)
6266 
6267 /* Bitfield definition for register of struct array TSNPORT: PORT1_QCH3_CFG */
6268 /*
6269  * CQF_IN_ERR (WC)
6270  *
6271  * qch queue in error
6272  */
6273 #define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_MASK (0x100000UL)
6274 #define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_SHIFT (20U)
6275 #define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_SHIFT) & TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_MASK)
6276 #define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_MASK) >> TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_SHIFT)
6277 
6278 /*
6279  * CQF_NUM (R/W)
6280  *
6281  * qch queue destination buffer select
6282  */
6283 #define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_MASK (0x70000UL)
6284 #define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_SHIFT (16U)
6285 #define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_SHIFT) & TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_MASK)
6286 #define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_MASK) >> TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_SHIFT)
6287 
6288 /*
6289  * TAS_GPIO_SEL (R/W)
6290  *
6291  * tas_gpio select
6292  */
6293 #define TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_MASK (0x7000U)
6294 #define TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_SHIFT (12U)
6295 #define TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_SHIFT) & TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_MASK)
6296 #define TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_MASK) >> TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_SHIFT)
6297 
6298 /*
6299  * AXIS_QCH_EN (R/W)
6300  *
6301  * qch queue in select
6302  */
6303 #define TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_MASK (0xFF0U)
6304 #define TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_SHIFT (4U)
6305 #define TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_MASK)
6306 #define TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_MASK) >> TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_SHIFT)
6307 
6308 /*
6309  * CQF_EN (R/W)
6310  *
6311  * qch enable
6312  */
6313 #define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_MASK (0x1U)
6314 #define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_SHIFT (0U)
6315 #define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_MASK)
6316 #define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_MASK) >> TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_SHIFT)
6317 
6318 /* Bitfield definition for register of struct array TSNPORT: PORT1_QCH_ERR_CFG */
6319 /*
6320  * CQF_QUE_ERR (WC)
6321  *
6322  * que gate error for each cqf
6323  */
6324 #define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_MASK (0xFF00U)
6325 #define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_SHIFT (8U)
6326 #define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_SHIFT) & TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_MASK)
6327 #define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_MASK) >> TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_SHIFT)
6328 
6329 /*
6330  * CQF_NUM_CFG_ERR (RO)
6331  *
6332  * cqf_num config error
6333  */
6334 #define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_NUM_CFG_ERR_MASK (0x4U)
6335 #define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_NUM_CFG_ERR_SHIFT (2U)
6336 #define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_NUM_CFG_ERR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_NUM_CFG_ERR_MASK) >> TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_NUM_CFG_ERR_SHIFT)
6337 
6338 /*
6339  * AXIS_QCH_CFG_ERR (RO)
6340  *
6341  * axis_qch_en config error
6342  */
6343 #define TSW_TSNPORT_PORT1_QCH_ERR_CFG_AXIS_QCH_CFG_ERR_MASK (0x2U)
6344 #define TSW_TSNPORT_PORT1_QCH_ERR_CFG_AXIS_QCH_CFG_ERR_SHIFT (1U)
6345 #define TSW_TSNPORT_PORT1_QCH_ERR_CFG_AXIS_QCH_CFG_ERR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH_ERR_CFG_AXIS_QCH_CFG_ERR_MASK) >> TSW_TSNPORT_PORT1_QCH_ERR_CFG_AXIS_QCH_CFG_ERR_SHIFT)
6346 
6347 /*
6348  * CQF_CLR_CTRL (R/W)
6349  *
6350  * enable cqf buffer auto clear when error
6351  */
6352 #define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_MASK (0x1U)
6353 #define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_SHIFT (0U)
6354 #define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_SHIFT) & TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_MASK)
6355 #define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_MASK) >> TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_SHIFT)
6356 
6357 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_TAS_CRSR */
6358 /*
6359  * ADMINGS (RO)
6360  *
6361  * Admin gate states, fixed 0xFF. Gate states when TAS is disabled.
6362  */
6363 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_ADMINGS_MASK (0xFF000000UL)
6364 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_ADMINGS_SHIFT (24U)
6365 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_ADMINGS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_ADMINGS_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_ADMINGS_SHIFT)
6366 
6367 /*
6368  * OPERGS (RO)
6369  *
6370  * Operational gate states of TQ[i] (i = 0 – TQC-1)
6371  * Bit[i]=0 – Gate is closed; no start of frame TX possible
6372  * Bit[i]=1 – Gate is open
6373  */
6374 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_OPERGS_MASK (0xFF0000UL)
6375 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_OPERGS_SHIFT (16U)
6376 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_OPERGS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_OPERGS_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_OPERGS_SHIFT)
6377 
6378 /*
6379  * TAS_GPIO_STA (RO)
6380  *
6381  * operational tas gpio gate status of TQ[i]
6382  */
6383 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_TAS_GPIO_STA_MASK (0xFF00U)
6384 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_TAS_GPIO_STA_SHIFT (8U)
6385 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_TAS_GPIO_STA_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_TAS_GPIO_STA_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_TAS_GPIO_STA_SHIFT)
6386 
6387 /*
6388  * CFGPEND (RO)
6389  *
6390  * Configuration change is pending – Admin basetime not yet reached.
6391  */
6392 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGPEND_MASK (0x8U)
6393 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGPEND_SHIFT (3U)
6394 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGPEND_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGPEND_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGPEND_SHIFT)
6395 
6396 /*
6397  * CFGERR (R/WC)
6398  *
6399  * Configuration error.
6400  */
6401 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_MASK (0x4U)
6402 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_SHIFT (2U)
6403 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_MASK)
6404 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_SHIFT)
6405 
6406 /*
6407  * CFGCHG (R/W)
6408  *
6409  * Switch configuration; Bit is automatically reset to 0;
6410  * Setting Bit=1 triggers configuration change event.
6411  */
6412 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_MASK (0x2U)
6413 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_SHIFT (1U)
6414 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_MASK)
6415 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_SHIFT)
6416 
6417 /*
6418  * EN (R/W)
6419  *
6420  * Enable time aware scheduling.
6421  */
6422 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_MASK (0x1U)
6423 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_SHIFT (0U)
6424 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_MASK)
6425 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_SHIFT)
6426 
6427 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_TAS_ACYCLETM */
6428 /*
6429  * CTIME (R/W)
6430  *
6431  * Admin cycletime in nanoseconds.
6432  */
6433 #define TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_MASK (0x3FFFFFFFUL)
6434 #define TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_SHIFT (0U)
6435 #define TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_MASK)
6436 #define TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_SHIFT)
6437 
6438 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_TAS_ABASETM_L */
6439 /*
6440  * BASETM_L (R/W)
6441  *
6442  * Admin basetime – nanoseconds and seconds part.
6443  */
6444 #define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_MASK (0x3FFFFFFFUL)
6445 #define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_SHIFT (0U)
6446 #define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_MASK)
6447 #define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_SHIFT)
6448 
6449 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_TAS_ABASETM_H */
6450 /*
6451  * BASETM_H (R/W)
6452  *
6453  */
6454 #define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_MASK (0xFFFFFFFFUL)
6455 #define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_SHIFT (0U)
6456 #define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_MASK)
6457 #define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_SHIFT)
6458 
6459 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_TAS_LISTLEN */
6460 /*
6461  * OLISTLEN (RO)
6462  *
6463  * Oper list length.
6464  */
6465 #define TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_OLISTLEN_MASK (0xFF0000UL)
6466 #define TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_OLISTLEN_SHIFT (16U)
6467 #define TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_OLISTLEN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_OLISTLEN_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_OLISTLEN_SHIFT)
6468 
6469 /*
6470  * ALISTLEN (R/W)
6471  *
6472  * Admin list length.
6473  */
6474 #define TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_MASK (0xFFU)
6475 #define TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_SHIFT (0U)
6476 #define TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_MASK)
6477 #define TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_SHIFT)
6478 
6479 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_TAS_OCYCLETM */
6480 /*
6481  * CTIME (RO)
6482  *
6483  * Operational cycletime in nanoseconds
6484  */
6485 #define TSW_TSNPORT_TSN_SHAPER_TAS_OCYCLETM_CTIME_MASK (0x3FFFFFFFUL)
6486 #define TSW_TSNPORT_TSN_SHAPER_TAS_OCYCLETM_CTIME_SHIFT (0U)
6487 #define TSW_TSNPORT_TSN_SHAPER_TAS_OCYCLETM_CTIME_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_OCYCLETM_CTIME_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_OCYCLETM_CTIME_SHIFT)
6488 
6489 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_TAS_OBASETM_L */
6490 /*
6491  * BASETM_L (RO)
6492  *
6493  * Operational basetime – nanoseconds and seconds part. The operational basetime might occasionally have a non-normalized value (ns >= 10^9) for one clock cycle.
6494  */
6495 #define TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_L_BASETM_L_MASK (0xFFFFFFFFUL)
6496 #define TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_L_BASETM_L_SHIFT (0U)
6497 #define TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_L_BASETM_L_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_L_BASETM_L_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_L_BASETM_L_SHIFT)
6498 
6499 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_TAS_OBASETM_H */
6500 /*
6501  * BASETM_H (RO)
6502  *
6503  */
6504 #define TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_H_BASETM_H_MASK (0xFFFFFFFFUL)
6505 #define TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_H_BASETM_H_SHIFT (0U)
6506 #define TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_H_BASETM_H_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_H_BASETM_H_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_H_BASETM_H_SHIFT)
6507 
6508 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_MXTK0 */
6509 /*
6510  * TICK (R/W)
6511  *
6512  * Maximum SDU size in clock ticks. MXTKi is only supported when TQC > i, otherwise read-only with value 0
6513  */
6514 #define TSW_TSNPORT_MXTK_TICK_MASK (0xFFFFFFUL)
6515 #define TSW_TSNPORT_MXTK_TICK_SHIFT (0U)
6516 #define TSW_TSNPORT_MXTK_TICK_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MXTK_TICK_SHIFT) & TSW_TSNPORT_MXTK_TICK_MASK)
6517 #define TSW_TSNPORT_MXTK_TICK_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MXTK_TICK_MASK) >> TSW_TSNPORT_MXTK_TICK_SHIFT)
6518 
6519 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_TXOV0 */
6520 /*
6521  * VALUE (R/WC)
6522  *
6523  * Transmission overrun counter; increments on transmission when gate is closed; any write access will clear register to 0. TXOVi is only supported when TQC > i.
6524  */
6525 #define TSW_TSNPORT_TXOV_VALUE_MASK (0xFFFFFFFFUL)
6526 #define TSW_TSNPORT_TXOV_VALUE_SHIFT (0U)
6527 #define TSW_TSNPORT_TXOV_VALUE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TXOV_VALUE_SHIFT) & TSW_TSNPORT_TXOV_VALUE_MASK)
6528 #define TSW_TSNPORT_TXOV_VALUE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TXOV_VALUE_MASK) >> TSW_TSNPORT_TXOV_VALUE_SHIFT)
6529 
6530 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_ACLIST_ENTRY_L */
6531 /*
6532  * TAS_GPIO (R/W)
6533  *
6534  * gate states for qch and ptp event source
6535  */
6536 #define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_TAS_GPIO_MASK (0x3FC00UL)
6537 #define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_TAS_GPIO_SHIFT (10U)
6538 #define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_TAS_GPIO_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_TAS_GPIO_SHIFT) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_TAS_GPIO_MASK)
6539 #define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_TAS_GPIO_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_TAS_GPIO_MASK) >> TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_TAS_GPIO_SHIFT)
6540 
6541 /*
6542  * OP (R/W)
6543  *
6544  * gate operation:
6545  * 0 – SetGateStates
6546  * 1 – Set-And-Hold-MAC
6547  * 2 – Set-And-Release-MAC
6548  * 3 – undefined
6549  */
6550 #define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_MASK (0x300U)
6551 #define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_SHIFT (8U)
6552 #define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_SHIFT) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_MASK)
6553 #define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_MASK) >> TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_SHIFT)
6554 
6555 /*
6556  * STATE (R/W)
6557  *
6558  * gate state vector;
6559  * 1 – Gate is open
6560  */
6561 #define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_MASK (0xFFU)
6562 #define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_SHIFT (0U)
6563 #define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_SHIFT) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_MASK)
6564 #define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_MASK) >> TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_SHIFT)
6565 
6566 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_ACLIST_ENTRY_H */
6567 /*
6568  * TIME (R/W)
6569  *
6570  * Time interval, entry execution in in host clock ticks (<sys_clk>)
6571  */
6572 #define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_MASK (0xFFFFFFFFUL)
6573 #define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_SHIFT (0U)
6574 #define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_SHIFT) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_MASK)
6575 #define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_MASK) >> TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_SHIFT)
6576 
6577 /* Bitfield definition for register of struct array TSNPORT: TSN_EP_VER */
6578 /*
6579  * VER_HI (RO)
6580  *
6581  * major version number
6582  */
6583 #define TSW_TSNPORT_TSN_EP_VER_VER_HI_MASK (0xFF000000UL)
6584 #define TSW_TSNPORT_TSN_EP_VER_VER_HI_SHIFT (24U)
6585 #define TSW_TSNPORT_TSN_EP_VER_VER_HI_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_VER_VER_HI_MASK) >> TSW_TSNPORT_TSN_EP_VER_VER_HI_SHIFT)
6586 
6587 /*
6588  * VER_LO (RO)
6589  *
6590  * minor version number
6591  */
6592 #define TSW_TSNPORT_TSN_EP_VER_VER_LO_MASK (0xFF0000UL)
6593 #define TSW_TSNPORT_TSN_EP_VER_VER_LO_SHIFT (16U)
6594 #define TSW_TSNPORT_TSN_EP_VER_VER_LO_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_VER_VER_LO_MASK) >> TSW_TSNPORT_TSN_EP_VER_VER_LO_SHIFT)
6595 
6596 /*
6597  * VER_REV (RO)
6598  *
6599  * revision number
6600  */
6601 #define TSW_TSNPORT_TSN_EP_VER_VER_REV_MASK (0xFFU)
6602 #define TSW_TSNPORT_TSN_EP_VER_VER_REV_SHIFT (0U)
6603 #define TSW_TSNPORT_TSN_EP_VER_VER_REV_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_VER_VER_REV_MASK) >> TSW_TSNPORT_TSN_EP_VER_VER_REV_SHIFT)
6604 
6605 /* Bitfield definition for register of struct array TSNPORT: TSN_EP_CTRL */
6606 /*
6607  * FILTDIS (R/W)
6608  *
6609  * Disable filtering of PTP frames (Ethertype = 0x88F7)
6610  */
6611 #define TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_MASK (0x80000000UL)
6612 #define TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_SHIFT (31U)
6613 #define TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_SHIFT) & TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_MASK)
6614 #define TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_MASK) >> TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_SHIFT)
6615 
6616 /*
6617  * PTP_1S_EN (R/W)
6618  *
6619  * Enable PTPv2 1-step synchronization suppor
6620  */
6621 #define TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_MASK (0x40000000UL)
6622 #define TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_SHIFT (30U)
6623 #define TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_SHIFT) & TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_MASK)
6624 #define TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_MASK) >> TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_SHIFT)
6625 
6626 /*
6627  * IE_TSF (R/W)
6628  *
6629  * TxTimestampFifo interrupt enable; interrupt will be set when IE_TSF=<1> and TSF_SR.USED>0
6630  */
6631 #define TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_MASK (0x1U)
6632 #define TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_SHIFT (0U)
6633 #define TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_SHIFT) & TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_MASK)
6634 #define TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_MASK) >> TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_SHIFT)
6635 
6636 /* Bitfield definition for register of struct array TSNPORT: TSN_EP_TXUF */
6637 /*
6638  * COUNTER (R/WC)
6639  *
6640  * TX buffer underflow counter; incremented when any MAC runs out of data during transmission. The counter is cleared at any write access. The counter is shared by pMAC and eMAC. If underflow event occurs at the same time for pMAC and eMAC, it will be counted as one event.
6641  */
6642 #define TSW_TSNPORT_TSN_EP_TXUF_COUNTER_MASK (0xFFFFFFFFUL)
6643 #define TSW_TSNPORT_TSN_EP_TXUF_COUNTER_SHIFT (0U)
6644 #define TSW_TSNPORT_TSN_EP_TXUF_COUNTER_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_TXUF_COUNTER_SHIFT) & TSW_TSNPORT_TSN_EP_TXUF_COUNTER_MASK)
6645 #define TSW_TSNPORT_TSN_EP_TXUF_COUNTER_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_TXUF_COUNTER_MASK) >> TSW_TSNPORT_TSN_EP_TXUF_COUNTER_SHIFT)
6646 
6647 /* Bitfield definition for register of struct array TSNPORT: TSN_EP_IPCFG */
6648 /*
6649  * INCL_RTC (RO)
6650  *
6651  * IP core parameter “INCL_RTC”
6652  */
6653 #define TSW_TSNPORT_TSN_EP_IPCFG_INCL_RTC_MASK (0x80000000UL)
6654 #define TSW_TSNPORT_TSN_EP_IPCFG_INCL_RTC_SHIFT (31U)
6655 #define TSW_TSNPORT_TSN_EP_IPCFG_INCL_RTC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_IPCFG_INCL_RTC_MASK) >> TSW_TSNPORT_TSN_EP_IPCFG_INCL_RTC_SHIFT)
6656 
6657 /*
6658  * INCL_SHAP (RO)
6659  *
6660  * IP core parameter “INCL_SHAPER”
6661  */
6662 #define TSW_TSNPORT_TSN_EP_IPCFG_INCL_SHAP_MASK (0x40000000UL)
6663 #define TSW_TSNPORT_TSN_EP_IPCFG_INCL_SHAP_SHIFT (30U)
6664 #define TSW_TSNPORT_TSN_EP_IPCFG_INCL_SHAP_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_IPCFG_INCL_SHAP_MASK) >> TSW_TSNPORT_TSN_EP_IPCFG_INCL_SHAP_SHIFT)
6665 
6666 /*
6667  * INCL_FPE (RO)
6668  *
6669  * IP core parameter “INCL_FPE”
6670  */
6671 #define TSW_TSNPORT_TSN_EP_IPCFG_INCL_FPE_MASK (0x20000000UL)
6672 #define TSW_TSNPORT_TSN_EP_IPCFG_INCL_FPE_SHIFT (29U)
6673 #define TSW_TSNPORT_TSN_EP_IPCFG_INCL_FPE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_IPCFG_INCL_FPE_MASK) >> TSW_TSNPORT_TSN_EP_IPCFG_INCL_FPE_SHIFT)
6674 
6675 /*
6676  * INCL_TSF (RO)
6677  *
6678  * IP core parameter “INCL_TSF”
6679  */
6680 #define TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSF_MASK (0x10000000UL)
6681 #define TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSF_SHIFT (28U)
6682 #define TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSF_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSF_MASK) >> TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSF_SHIFT)
6683 
6684 /*
6685  * INCL_TSYNC (RO)
6686  *
6687  * IP core parameter “INCL_TSYNC”
6688  */
6689 #define TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSYNC_MASK (0x8000000UL)
6690 #define TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSYNC_SHIFT (27U)
6691 #define TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSYNC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSYNC_MASK) >> TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSYNC_SHIFT)
6692 
6693 /*
6694  * INCL_1STEP (RO)
6695  *
6696  * IP core parameter “INCL_1STEP”
6697  */
6698 #define TSW_TSNPORT_TSN_EP_IPCFG_INCL_1STEP_MASK (0x4000000UL)
6699 #define TSW_TSNPORT_TSN_EP_IPCFG_INCL_1STEP_SHIFT (26U)
6700 #define TSW_TSNPORT_TSN_EP_IPCFG_INCL_1STEP_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_IPCFG_INCL_1STEP_MASK) >> TSW_TSNPORT_TSN_EP_IPCFG_INCL_1STEP_SHIFT)
6701 
6702 /* Bitfield definition for register of struct array TSNPORT: TSN_EP_TSF_D0 */
6703 /*
6704  * TSF_NS (RO)
6705  *
6706  * Tx-Timestamp-Fifo, lower 32 bit part of local time (<curtime>) at the start of transmission of the packet. Usually nanoseconds part when used with included RTC.
6707  */
6708 #define TSW_TSNPORT_TSN_EP_TSF_D0_TSF_NS_MASK (0xFFFFFFFFUL)
6709 #define TSW_TSNPORT_TSN_EP_TSF_D0_TSF_NS_SHIFT (0U)
6710 #define TSW_TSNPORT_TSN_EP_TSF_D0_TSF_NS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_TSF_D0_TSF_NS_MASK) >> TSW_TSNPORT_TSN_EP_TSF_D0_TSF_NS_SHIFT)
6711 
6712 /* Bitfield definition for register of struct array TSNPORT: TSN_EP_TSF_D1 */
6713 /*
6714  * TSF_SEC (RO)
6715  *
6716  * Tx-Timestamp-Fifo, upper 32 bit part of the local time (<curtime>) at the start of the transmission of the packet. Usually seconds part when used with included RTC.
6717  */
6718 #define TSW_TSNPORT_TSN_EP_TSF_D1_TSF_SEC_MASK (0xFFFFFFFFUL)
6719 #define TSW_TSNPORT_TSN_EP_TSF_D1_TSF_SEC_SHIFT (0U)
6720 #define TSW_TSNPORT_TSN_EP_TSF_D1_TSF_SEC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_TSF_D1_TSF_SEC_MASK) >> TSW_TSNPORT_TSN_EP_TSF_D1_TSF_SEC_SHIFT)
6721 
6722 /* Bitfield definition for register of struct array TSNPORT: TSN_EP_TSF_D2 */
6723 /*
6724  * TSF_TQ (RO)
6725  *
6726  * Tx-Timestamp-Fifo, traffic queue <tx_tqueue> of sent packet
6727  */
6728 #define TSW_TSNPORT_TSN_EP_TSF_D2_TSF_TQ_MASK (0xE0000000UL)
6729 #define TSW_TSNPORT_TSN_EP_TSF_D2_TSF_TQ_SHIFT (29U)
6730 #define TSW_TSNPORT_TSN_EP_TSF_D2_TSF_TQ_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_TSF_D2_TSF_TQ_MASK) >> TSW_TSNPORT_TSN_EP_TSF_D2_TSF_TQ_SHIFT)
6731 
6732 /*
6733  * TSF_USR (RO)
6734  *
6735  * Tx-Timestamp-Fifo, user sideband <tx_tuser> of sent packet; Note: any read to register will remove actual value from FIFO
6736  */
6737 #define TSW_TSNPORT_TSN_EP_TSF_D2_TSF_USR_MASK (0x7U)
6738 #define TSW_TSNPORT_TSN_EP_TSF_D2_TSF_USR_SHIFT (0U)
6739 #define TSW_TSNPORT_TSN_EP_TSF_D2_TSF_USR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_TSF_D2_TSF_USR_MASK) >> TSW_TSNPORT_TSN_EP_TSF_D2_TSF_USR_SHIFT)
6740 
6741 /* Bitfield definition for register of struct array TSNPORT: TSN_EP_TSF_SR */
6742 /*
6743  * TSF_OV (R/WC)
6744  *
6745  * Overflow of Tx-Timestamp-Fifo. At least one transmitted packet has been sent and timestamp was not stored; write bit to clear flag
6746  */
6747 #define TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_MASK (0x80000000UL)
6748 #define TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_SHIFT (31U)
6749 #define TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_SHIFT) & TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_MASK)
6750 #define TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_MASK) >> TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_SHIFT)
6751 
6752 /*
6753  * TSF_USED (RO)
6754  *
6755  * Tx-Timestamp-Fifo currently used entries counter; reading of TSF_Dx is only valid if field value > 0. Any read from TSF_D2 will decrement counter (unless already 0).
6756  */
6757 #define TSW_TSNPORT_TSN_EP_TSF_SR_TSF_USED_MASK (0xFFU)
6758 #define TSW_TSNPORT_TSN_EP_TSF_SR_TSF_USED_SHIFT (0U)
6759 #define TSW_TSNPORT_TSN_EP_TSF_SR_TSF_USED_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_TSF_SR_TSF_USED_MASK) >> TSW_TSNPORT_TSN_EP_TSF_SR_TSF_USED_SHIFT)
6760 
6761 /* Bitfield definition for register of struct array TSNPORT: TSN_EP_MMS_CTRL */
6762 /*
6763  * STATSEL (R/W)
6764  *
6765  * MMS statistic counter selection, value can be read in register
6766  * MMS_STAT
6767  * <000>: Frame reassembly error counter (802.3br, 30.14.1.8)
6768  * <001>: Frames rejected due to wrong SMD (802.3br, 30.14.1.9)
6769  * <010>: Frame assembly ok counter (802.3br, 30.14.1.10)
6770  * <011>: Fragment rx counter (802.3br, 30.14.1.11)
6771  * <100>: Fragment tx counter (802.3br, 30.14.1.12)
6772  * <101>: Hold request counter (802.3br, 30.14.1.13)
6773  * otherwise: <0>
6774  */
6775 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_MASK (0xE0U)
6776 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_SHIFT (5U)
6777 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_SHIFT) & TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_MASK)
6778 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_MASK) >> TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_SHIFT)
6779 
6780 /*
6781  * FRAGSZ (R/W)
6782  *
6783  * Minimum non-final fragment size: 64 x (1 + FRAGSZ) – 4 octets
6784  */
6785 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_MASK (0x18U)
6786 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_SHIFT (3U)
6787 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_SHIFT) & TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_MASK)
6788 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_MASK) >> TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_SHIFT)
6789 
6790 /*
6791  * DISV (R/W)
6792  *
6793  * Disable verification
6794  */
6795 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_MASK (0x4U)
6796 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_SHIFT (2U)
6797 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_SHIFT) & TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_MASK)
6798 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_MASK) >> TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_SHIFT)
6799 
6800 /*
6801  * LINK (R/W)
6802  *
6803  * Link error
6804  */
6805 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_MASK (0x2U)
6806 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_SHIFT (1U)
6807 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_SHIFT) & TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_MASK)
6808 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_MASK) >> TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_SHIFT)
6809 
6810 /*
6811  * EN (R/W)
6812  *
6813  * Enable preemption
6814  */
6815 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_MASK (0x1U)
6816 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_SHIFT (0U)
6817 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_SHIFT) & TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_MASK)
6818 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_MASK) >> TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_SHIFT)
6819 
6820 /* Bitfield definition for register of struct array TSNPORT: TSN_EP_MMS_STS */
6821 /*
6822  * VFAIL (RO)
6823  *
6824  * 802.3br verification state failure; verification is done when any bit VFAIL or VOK is <1>
6825  */
6826 #define TSW_TSNPORT_TSN_EP_MMS_STS_VFAIL_MASK (0x4U)
6827 #define TSW_TSNPORT_TSN_EP_MMS_STS_VFAIL_SHIFT (2U)
6828 #define TSW_TSNPORT_TSN_EP_MMS_STS_VFAIL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_STS_VFAIL_MASK) >> TSW_TSNPORT_TSN_EP_MMS_STS_VFAIL_SHIFT)
6829 
6830 /*
6831  * VOK (RO)
6832  *
6833  * 802.3br verification state ok; verification is done when any bit VFAIL or VOK is <1>
6834  */
6835 #define TSW_TSNPORT_TSN_EP_MMS_STS_VOK_MASK (0x2U)
6836 #define TSW_TSNPORT_TSN_EP_MMS_STS_VOK_SHIFT (1U)
6837 #define TSW_TSNPORT_TSN_EP_MMS_STS_VOK_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_STS_VOK_MASK) >> TSW_TSNPORT_TSN_EP_MMS_STS_VOK_SHIFT)
6838 
6839 /*
6840  * HLD (RO)
6841  *
6842  * HOLD-Signal
6843  */
6844 #define TSW_TSNPORT_TSN_EP_MMS_STS_HLD_MASK (0x1U)
6845 #define TSW_TSNPORT_TSN_EP_MMS_STS_HLD_SHIFT (0U)
6846 #define TSW_TSNPORT_TSN_EP_MMS_STS_HLD_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_STS_HLD_MASK) >> TSW_TSNPORT_TSN_EP_MMS_STS_HLD_SHIFT)
6847 
6848 /* Bitfield definition for register of struct array TSNPORT: TSN_EP_MMS_VTIME */
6849 /*
6850  * VTIME (R/W)
6851  *
6852  * 802.3br verification timeout counter in <sys_clk> cycles. Must be set by software in range of 1ms to 128ms.
6853  */
6854 #define TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_MASK (0xFFFFFFFFUL)
6855 #define TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_SHIFT (0U)
6856 #define TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_SHIFT) & TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_MASK)
6857 #define TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_MASK) >> TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_SHIFT)
6858 
6859 /* Bitfield definition for register of struct array TSNPORT: TSN_EP_MMS_STAT */
6860 /*
6861  * COUNTER (R/WC)
6862  *
6863  * Statistic counter of MMS, selected by MMS_CTRL.STATSEL,any write access will clear selected counter
6864  */
6865 #define TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_MASK (0xFFFFFFFFUL)
6866 #define TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_SHIFT (0U)
6867 #define TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_SHIFT) & TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_MASK)
6868 #define TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_MASK) >> TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_SHIFT)
6869 
6870 /* Bitfield definition for register of struct array TSNPORT: TSN_EP_PTP_UPTM_NS */
6871 /*
6872  * UPTM_NS (WO)
6873  *
6874  * PTP SYNC frame “upstreamTxTime” in format “seconds.nanoseconds” as potentially received by another TSN-EP port. The correction field of a transmitted PTP SYNC frame is modified by (egressTimestamp –upstreamTxTime), relative to the LocalClock. The “rateRatio” to the Grandmaster Clock is not taken into account.
6875  */
6876 #define TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_MASK (0xFFFFFFFFUL)
6877 #define TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_SHIFT (0U)
6878 #define TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_SHIFT) & TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_MASK)
6879 #define TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_MASK) >> TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_SHIFT)
6880 
6881 /* Bitfield definition for register of struct array TSNPORT: TSN_EP_PTP_UPTM_S */
6882 /*
6883  * UPTM_NS (WO)
6884  *
6885  */
6886 #define TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_MASK (0xFFFFFFFFUL)
6887 #define TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_SHIFT (0U)
6888 #define TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_SHIFT) & TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_MASK)
6889 #define TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_MASK) >> TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_SHIFT)
6890 
6891 /* Bitfield definition for register of struct array TSNPORT: TSN_EP_PTP_SR */
6892 /*
6893  * MEAS_NS (RO)
6894  *
6895  * Measured value of the deviation of the early timestamping for PTP frames. This value is informational only. The deviation is already included to the corrected “correctionField”.
6896  */
6897 #define TSW_TSNPORT_TSN_EP_PTP_SR_MEAS_NS_MASK (0xFFFFU)
6898 #define TSW_TSNPORT_TSN_EP_PTP_SR_MEAS_NS_SHIFT (0U)
6899 #define TSW_TSNPORT_TSN_EP_PTP_SR_MEAS_NS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_PTP_SR_MEAS_NS_MASK) >> TSW_TSNPORT_TSN_EP_PTP_SR_MEAS_NS_SHIFT)
6900 
6901 /* Bitfield definition for register of struct array TSNPORT: SW_CTRL_PORT_MAIN_TAGGING */
6902 /*
6903  * FORCE (R/W)
6904  *
6905  * The VLAN-TAG with PVID will be inserted in every frame from Host as their first VLAN-TAG. This can be used for double tagging of tagged/trunk ports
6906  */
6907 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_MASK (0x20000UL)
6908 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_SHIFT (17U)
6909 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_SHIFT) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_MASK)
6910 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_MASK) >> TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_SHIFT)
6911 
6912 /*
6913  * ACCESS (R/W)
6914  *
6915  * Every tagged frame not matching PVID is filtered out. Every untagged ingress frame will be tagged with PVID. Every egress frame with PVID will be untagged
6916  */
6917 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_MASK (0x10000UL)
6918 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_SHIFT (16U)
6919 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_SHIFT) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_MASK)
6920 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_MASK) >> TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_SHIFT)
6921 
6922 /*
6923  * PCP (R/W)
6924  *
6925  * VLAN-TCI: Priority Code Point, used when tagged.
6926  */
6927 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_MASK (0xE000U)
6928 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_SHIFT (13U)
6929 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_SHIFT) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_MASK)
6930 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_MASK) >> TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_SHIFT)
6931 
6932 /*
6933  * DEI (R/W)
6934  *
6935  * VLAN-TCI: Drop Eligible Indicator, used when tagged.
6936  */
6937 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_MASK (0x1000U)
6938 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_SHIFT (12U)
6939 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_SHIFT) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_MASK)
6940 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_MASK) >> TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_SHIFT)
6941 
6942 /*
6943  * PVID (R/W)
6944  *
6945  * Native VLAN of Port. Untagged traffic will be tagged with the native VLAN-ID By default the Port uses VLAN 1.
6946  */
6947 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_MASK (0xFFFU)
6948 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_SHIFT (0U)
6949 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_SHIFT) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_MASK)
6950 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_MASK) >> TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_SHIFT)
6951 
6952 /* Bitfield definition for register of struct array TSNPORT: SW_CTRL_EGRESS_ECSR_QDROP */
6953 /*
6954  * DIS_VEC (R/W)
6955  *
6956  * disable drop for each queue when queue not free
6957  */
6958 #define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_MASK (0xFF000000UL)
6959 #define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_SHIFT (24U)
6960 #define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_SHIFT) & TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_MASK)
6961 #define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_MASK) >> TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_SHIFT)
6962 
6963 /*
6964  * EN_VEC (R/W)
6965  *
6966  * Enable/Disable drop in egress when TSN queue not free.
6967  * 1 - drop enabled
6968  * 0 - drop disabled
6969  * TSN-SW:
6970  * bit[i] - from Port[i]
6971  */
6972 #define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_MASK (0xFFFFFFUL)
6973 #define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_SHIFT (0U)
6974 #define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_SHIFT) & TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_MASK)
6975 #define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_MASK) >> TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_SHIFT)
6976 
6977 /* Bitfield definition for register of struct array TSNPORT: SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_CNT_BYTE */
6978 /*
6979  * FDMEM_CNT_BYTE (RO)
6980  *
6981  * Number of bytes stored in frame drop FIFO
6982  */
6983 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_MASK (0xFFFFFFFFUL)
6984 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_SHIFT (0U)
6985 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_SHIFT)
6986 
6987 /* Bitfield definition for register of struct array TSNPORT: SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS */
6988 /*
6989  * WAIT_FOR_LU (RO)
6990  *
6991  * FD FIFO waits for LookUp information.
6992  */
6993 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_LU_MASK (0x800U)
6994 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_LU_SHIFT (11U)
6995 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_LU_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_LU_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_LU_SHIFT)
6996 
6997 /*
6998  * WAIT_FOR_FRAME (RO)
6999  *
7000  * FD FIFO waits for more frame data.
7001  */
7002 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_FRAME_MASK (0x400U)
7003 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_FRAME_SHIFT (10U)
7004 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_FRAME_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_FRAME_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_FRAME_SHIFT)
7005 
7006 /*
7007  * BUSY (RO)
7008  *
7009  * FD FIFO processes data.
7010  */
7011 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_BUSY_MASK (0x200U)
7012 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_BUSY_SHIFT (9U)
7013 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_BUSY_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_BUSY_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_BUSY_SHIFT)
7014 
7015 /*
7016  * READY (RO)
7017  *
7018  * FD FIFO ready to work or working.
7019  */
7020 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_READY_MASK (0x100U)
7021 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_READY_SHIFT (8U)
7022 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_READY_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_READY_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_READY_SHIFT)
7023 
7024 /*
7025  * FULL (RO)
7026  *
7027  * FD FIFO full
7028  */
7029 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_FULL_MASK (0x8U)
7030 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_FULL_SHIFT (3U)
7031 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_FULL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_FULL_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_FULL_SHIFT)
7032 
7033 /*
7034  * AMST_FULL (RO)
7035  *
7036  * FD FIFO almost full. Less than 1600 Byte left.
7037  */
7038 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_FULL_MASK (0x4U)
7039 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_FULL_SHIFT (2U)
7040 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_FULL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_FULL_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_FULL_SHIFT)
7041 
7042 /*
7043  * AMST_EMPTY (RO)
7044  *
7045  * FD FIFO almost empty. Few bytes in FIFO.
7046  */
7047 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_EMPTY_MASK (0x2U)
7048 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_EMPTY_SHIFT (1U)
7049 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_EMPTY_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_EMPTY_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_EMPTY_SHIFT)
7050 
7051 /*
7052  * EMPTY (RO)
7053  *
7054  * FD FIFO empty
7055  */
7056 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_EMPTY_MASK (0x1U)
7057 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_EMPTY_SHIFT (0U)
7058 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_EMPTY_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_EMPTY_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_EMPTY_SHIFT)
7059 
7060 /* Bitfield definition for register of struct array TSNPORT: SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG */
7061 /*
7062  * LU_DESC_ERR (R/W1C)
7063  *
7064  * LookUp Descriptor lost, because of unknown frame burst by MAC. If there is no MAC mailfunction then this flag will never be raised. FDFIFO requires reset.
7065  */
7066 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_MASK (0x40U)
7067 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_SHIFT (6U)
7068 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_MASK)
7069 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_SHIFT)
7070 
7071 /*
7072  * WRFAIL_FULL (R/W1C)
7073  *
7074  * Set if a frame is partially written into FIFO which had insufficient space. The frame is cut and frame error is set.
7075  */
7076 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_MASK (0x20U)
7077 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_SHIFT (5U)
7078 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_MASK)
7079 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_SHIFT)
7080 
7081 /*
7082  * DROP_NRDY (R/W1C)
7083  *
7084  * Frame was dropped because the FIFO was not ready. That can typically happen after a reset of the FIFO
7085  */
7086 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_MASK (0x10U)
7087 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_SHIFT (4U)
7088 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_MASK)
7089 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_SHIFT)
7090 
7091 /*
7092  * DROP_FULL_DESC (R/W1C)
7093  *
7094  * Frame was dropped because the internal descriptor FIFO is full. Full by too many frames.
7095  */
7096 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_MASK (0x8U)
7097 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_SHIFT (3U)
7098 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_MASK)
7099 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_SHIFT)
7100 
7101 /*
7102  * DROP_FULL_MEM (R/W1C)
7103  *
7104  * Frame was dropped because the FIFO is full. Full by too much data.
7105  */
7106 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_MASK (0x4U)
7107 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_SHIFT (2U)
7108 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_MASK)
7109 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_SHIFT)
7110 
7111 /*
7112  * DESC_NRDY_ERR (R/W1C)
7113  *
7114  * FD FIFO failure. Descriptor not received correctly.
7115  */
7116 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_MASK (0x2U)
7117 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_SHIFT (1U)
7118 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_MASK)
7119 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_SHIFT)
7120 
7121 /*
7122  * DESC_SEQ_ERR (R/W1C)
7123  *
7124  * FD FIFO failure. Internal controller lost synchronization.
7125  */
7126 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_MASK (0x1U)
7127 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_SHIFT (0U)
7128 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_MASK)
7129 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_SHIFT)
7130 
7131 /* Bitfield definition for register of struct array TSNPORT: SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG */
7132 /*
7133  * IE (R/W)
7134  *
7135  * Interrupt enable of ERROR_FLAG.
7136  */
7137 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_MASK (0x7FU)
7138 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_SHIFT (0U)
7139 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_MASK)
7140 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_SHIFT)
7141 
7142 /* Bitfield definition for register of struct array TSNPORT: SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG */
7143 /*
7144  * NOCUT_ERROR (R/W)
7145  *
7146  * FD_FIFO does not shorten frames which contain an error.
7147  */
7148 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_MASK (0x1U)
7149 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_SHIFT (0U)
7150 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_MASK)
7151 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_SHIFT)
7152 
7153 /* Bitfield definition for register of struct array TSNPORT: SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG */
7154 /*
7155  * DROP_DEST (R/W)
7156  *
7157  * Bit mapped Destination for dropped frames. Typically, frames are cleared at destination 0. Use another value to stream frames for analysis. Supports only max range of port[15:0].
7158  */
7159 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_MASK (0xFFFF0000UL)
7160 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_SHIFT (16U)
7161 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_MASK)
7162 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_SHIFT)
7163 
7164 /*
7165  * MIRROR_TX_EN (R/W)
7166  *
7167  * Incoming frames of this port will be mirrored to the given destination in MIRROR if their destination match with MIRROR_TX.
7168  */
7169 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_MASK (0x200U)
7170 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_SHIFT (9U)
7171 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_MASK)
7172 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_SHIFT)
7173 
7174 /*
7175  * MIRROR_RX_EN (R/W)
7176  *
7177  * Incoming frames of this port will be mirrored to the given destination in MIRROR_RX.
7178  */
7179 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_MASK (0x100U)
7180 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_SHIFT (8U)
7181 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_MASK)
7182 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_SHIFT)
7183 
7184 /*
7185  * CT_FPE_OVRD (R/W)
7186  *
7187  * If any Store&Forward option in RX_FDFIFO is set then this flag will still force preemptable traffic to be forwarded in Cut-Through mode. This is a useful option to save latency by double buffering if the used MAC/TSN-EP already does S&F.
7188  */
7189 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_MASK (0x40U)
7190 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_SHIFT (6U)
7191 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_MASK)
7192 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_SHIFT)
7193 
7194 /*
7195  * DISABLE (R/W)
7196  *
7197  * Disable input of FD FIFO. Take care that also descriptor generation of LookUp is disabled. Remaining frames should be cleared with DROP_ALL.
7198  */
7199 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_MASK (0x20U)
7200 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_SHIFT (5U)
7201 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_MASK)
7202 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_SHIFT)
7203 
7204 /*
7205  * DROP_ALL (R/W)
7206  *
7207  * Route all frames to DROP_DEST.
7208  */
7209 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_MASK (0x10U)
7210 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_SHIFT (4U)
7211 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_MASK)
7212 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_SHIFT)
7213 
7214 /*
7215  * ERROR_TO_CPU (R/W)
7216  *
7217  * Send error frames to CPU.
7218  */
7219 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_MASK (0x8U)
7220 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_SHIFT (3U)
7221 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_MASK)
7222 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_SHIFT)
7223 
7224 /*
7225  * MIRROR_TO_CPU (R/W)
7226  *
7227  * Duplicate frames to CPU.
7228  */
7229 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_MASK (0x4U)
7230 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_SHIFT (2U)
7231 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_MASK)
7232 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_SHIFT)
7233 
7234 /*
7235  * NODROP_ERROR (R/W)
7236  *
7237  * Do not drop frame errors.
7238  */
7239 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_MASK (0x2U)
7240 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_SHIFT (1U)
7241 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_MASK)
7242 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_SHIFT)
7243 
7244 /*
7245  * MODE_STORE_FW (R/W)
7246  *
7247  * Switch between Cut-Through and Store&Forward mode. 0 - Cut-Through 1 - Store&Forward
7248  */
7249 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_MASK (0x1U)
7250 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_SHIFT (0U)
7251 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_MASK)
7252 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_SHIFT)
7253 
7254 /* Bitfield definition for register of struct array TSNPORT: SW_CTRL_IGRESS_RX_FDFIFO_E_RESET */
7255 /*
7256  * SOFTRS (W)
7257  *
7258  * Write 1 to reset FD controller and memory pointers. Register Map content remains untouched
7259  */
7260 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_MASK (0x1U)
7261 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_SHIFT (0U)
7262 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_MASK)
7263 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_SHIFT)
7264 
7265 /* Bitfield definition for register of struct array TSNPORT: SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM */
7266 /*
7267  * LU_FIFO_DEPTH (RO)
7268  *
7269  * Number of MAC lookup descriptors the FIFO can store.
7270  */
7271 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_LU_FIFO_DEPTH_MASK (0xFF000000UL)
7272 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_LU_FIFO_DEPTH_SHIFT (24U)
7273 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_LU_FIFO_DEPTH_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_LU_FIFO_DEPTH_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_LU_FIFO_DEPTH_SHIFT)
7274 
7275 /*
7276  * FD_DESC_FIFO_DESC (RO)
7277  *
7278  * Number of FD descriptors the FIFO can store. Two descriptors need to be stored per frame.
7279  */
7280 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_DESC_FIFO_DESC_MASK (0xFF0000UL)
7281 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_DESC_FIFO_DESC_SHIFT (16U)
7282 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_DESC_FIFO_DESC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_DESC_FIFO_DESC_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_DESC_FIFO_DESC_SHIFT)
7283 
7284 /*
7285  * FD_FIFO_DESC (RO)
7286  *
7287  * Number of words (4byte) the Frame Drop FIFO can store.
7288  */
7289 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_FIFO_DESC_MASK (0xFFFFU)
7290 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_FIFO_DESC_SHIFT (0U)
7291 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_FIFO_DESC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_FIFO_DESC_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_FIFO_DESC_SHIFT)
7292 
7293 /* Bitfield definition for register of struct array TSNPORT: SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD */
7294 /*
7295  * PORT (R/W)
7296  *
7297  * If selected port is set then the frame is transmitted in Store & Forward mode. This is necessary when the ingress rate of this port is slower than the egress rate of the transmitting port. In S&F, the ingress module is able to drop frames with bad CRC.bit 0 - CPU-Port,
7298  * bit 1 - Port 1, …
7299  */
7300 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_MASK (0x1FFFFFFUL)
7301 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_SHIFT (0U)
7302 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_MASK)
7303 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_SHIFT)
7304 
7305 /* Bitfield definition for register of struct array TSNPORT: SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK */
7306 /*
7307  * PORT (R/W)
7308  *
7309  * Port grouping via port mask. If the selected port is not set then the destination will be filtered out. This register allows the realization of port-based-VLAN (no VLAN tags required, only set it by ports).
7310  * bit 0 - CPU-Port,
7311  * bit 1 - Port 1, …
7312  */
7313 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_MASK (0x1FFFFFFUL)
7314 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_SHIFT (0U)
7315 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_MASK)
7316 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_SHIFT)
7317 
7318 /* Bitfield definition for register of struct array TSNPORT: SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR */
7319 /*
7320  * PORT (R/W)
7321  *
7322  * Mirror Port. If port mirroring is enabled TX/RX traffic will also be forwarded to this port.
7323  * bit 0 - CPU-Port,
7324  * bit 1 - Port 1, …
7325  */
7326 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_MASK (0x1FFFFFFUL)
7327 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_SHIFT (0U)
7328 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_MASK)
7329 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_SHIFT)
7330 
7331 /* Bitfield definition for register of struct array TSNPORT: SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX */
7332 /*
7333  * PORT (R/W)
7334  *
7335  * Mirror Selection TX. The destination of the frame is compared with this vector. All matching TX probe ports will be mirrored to MIRROR. It is necessary to configure all ingress ports to mirror the complete TX traffic.
7336  * bit 0 - CPU-Port,
7337  * bit 1 - Port 1, …
7338  */
7339 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_MASK (0x1FFFFFFUL)
7340 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_SHIFT (0U)
7341 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_MASK)
7342 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_SHIFT)
7343 
7344 /* Bitfield definition for register of struct array TSNPORT: SW_CTRL_MONITOR_CTRL */
7345 /*
7346  * EN (R/W)
7347  *
7348  * Enables counter. If deasserted the counter process stops and the counters hold their value.
7349  */
7350 #define TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_MASK (0x1U)
7351 #define TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_SHIFT (0U)
7352 #define TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_SHIFT) & TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_MASK)
7353 #define TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_MASK) >> TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_SHIFT)
7354 
7355 /* Bitfield definition for register of struct array TSNPORT: SW_CTRL_MONITOR_RESET */
7356 /*
7357  * RSRX (WO)
7358  *
7359  * Write '1' to reset all RX counters.
7360  */
7361 #define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_MASK (0x4U)
7362 #define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_SHIFT (2U)
7363 #define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_SHIFT) & TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_MASK)
7364 #define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_MASK) >> TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_SHIFT)
7365 
7366 /*
7367  * RSTX (WO)
7368  *
7369  * Write '1' to reset all TX counters
7370  */
7371 #define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_MASK (0x2U)
7372 #define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_SHIFT (1U)
7373 #define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_SHIFT) & TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_MASK)
7374 #define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_MASK) >> TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_SHIFT)
7375 
7376 /*
7377  * RSALL (WO)
7378  *
7379  * Write '1' to reset all TX&RX counters.
7380  */
7381 #define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_MASK (0x1U)
7382 #define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_SHIFT (0U)
7383 #define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_SHIFT) & TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_MASK)
7384 #define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_MASK) >> TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_SHIFT)
7385 
7386 /* Bitfield definition for register of struct array TSNPORT: SW_CTRL_MONITOR_PARAM */
7387 /*
7388  * RX_CNT_EN_VEC (RO)
7389  *
7390  * Vector of implemented RX counters. E.g. 0x000F means only the first 4 RX counter are available.
7391  */
7392 #define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_RX_CNT_EN_VEC_MASK (0xFFFF0000UL)
7393 #define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_RX_CNT_EN_VEC_SHIFT (16U)
7394 #define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_RX_CNT_EN_VEC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_RX_CNT_EN_VEC_MASK) >> TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_RX_CNT_EN_VEC_SHIFT)
7395 
7396 /*
7397  * TX_CNT_EN_VEC (RO)
7398  *
7399  * Vector of implemented RX counters. E.g. 0x000F means only the first 4 RX counter are available.
7400  */
7401 #define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_TX_CNT_EN_VEC_MASK (0xFF00U)
7402 #define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_TX_CNT_EN_VEC_SHIFT (8U)
7403 #define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_TX_CNT_EN_VEC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_TX_CNT_EN_VEC_MASK) >> TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_TX_CNT_EN_VEC_SHIFT)
7404 
7405 /*
7406  * CNTW (RO)
7407  *
7408  * Vector of implemented RX counters. E.g. 0x000F means only the first 4 RX counter
7409  * are available.
7410  */
7411 #define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_CNTW_MASK (0x7FU)
7412 #define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_CNTW_SHIFT (0U)
7413 #define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_CNTW_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_CNTW_MASK) >> TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_CNTW_SHIFT)
7414 
7415 /* Bitfield definition for register of struct array TSNPORT: MONITOR_TX_COUNTER_TX_FGOOD */
7416 /*
7417  * TX_FGOOD (RO)
7418  *
7419  * Good transmitted Frames to TX TSN-EP.
7420  */
7421 #define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_MASK (0xFFFFFFFFUL)
7422 #define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_SHIFT (0U)
7423 #define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_MASK) >> TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_SHIFT)
7424 
7425 /* Bitfield definition for register of struct array TSNPORT: MONITOR_TX_COUNTER_TX_FERROR */
7426 /*
7427  * TX_FERROR (RO)
7428  *
7429  * Transmitted Frames with Error to TX TSN-EP.
7430  */
7431 #define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_MASK (0xFFFFFFFFUL)
7432 #define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_SHIFT (0U)
7433 #define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_MASK) >> TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_SHIFT)
7434 
7435 /* Bitfield definition for register of struct array TSNPORT: MONITOR_TX_COUNTER_TX_DROP_OVFL */
7436 /*
7437  * TX_DROP_OVFL (RO)
7438  *
7439  * Dropped frames by full queue of TSN-EP.
7440  */
7441 #define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_MASK (0xFFFFFFFFUL)
7442 #define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_SHIFT (0U)
7443 #define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_MASK) >> TSW_TSNPORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_SHIFT)
7444 
7445 /* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_FGOOD */
7446 /*
7447  * RX_FGOOD (RO)
7448  *
7449  * Good received frame by ingress buffer.
7450  */
7451 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_MASK (0xFFFFFFFFUL)
7452 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_SHIFT (0U)
7453 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_SHIFT)
7454 
7455 /* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_FERROR */
7456 /*
7457  * RX_FERROR (RO)
7458  *
7459  * Bad received frame by ingress buffer.
7460  */
7461 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_MASK (0xFFFFFFFFUL)
7462 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_SHIFT (0U)
7463 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_SHIFT)
7464 
7465 /* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_KNOWN */
7466 /*
7467  * RX_KNOWN (RO)
7468  *
7469  * Number of frames passed ingress with hit by MAC Table. This includes Broadcast and non-relayed frames.
7470  */
7471 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_MASK (0xFFFFFFFFUL)
7472 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_SHIFT (0U)
7473 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_SHIFT)
7474 
7475 /* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_UNKNOWN */
7476 /*
7477  * RX_UNKNOWN (RO)
7478  *
7479  * Number of frames passed ingress without hit by MAC table.
7480  */
7481 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_MASK (0xFFFFFFFFUL)
7482 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_SHIFT (0U)
7483 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_SHIFT)
7484 
7485 /* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_UC */
7486 /*
7487  * RX_UC (RO)
7488  *
7489  * Number of unicast frames
7490  */
7491 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_MASK (0xFFFFFFFFUL)
7492 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_SHIFT (0U)
7493 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_SHIFT)
7494 
7495 /* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_INTERN */
7496 /*
7497  * RX_INTERN (RO)
7498  *
7499  * Number of non-relay frames
7500  */
7501 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_MASK (0xFFFFFFFFUL)
7502 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_SHIFT (0U)
7503 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_SHIFT)
7504 
7505 /* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_BC */
7506 /*
7507  * RX_BC (RO)
7508  *
7509  * Number of Broadcast frames
7510  */
7511 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_MASK (0xFFFFFFFFUL)
7512 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_SHIFT (0U)
7513 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_SHIFT)
7514 
7515 /* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_MULTI */
7516 /*
7517  * RX_MULTI (RO)
7518  *
7519  * Number of Multicast frames
7520  */
7521 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_MASK (0xFFFFFFFFUL)
7522 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_SHIFT (0U)
7523 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_SHIFT)
7524 
7525 /* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_VLAN */
7526 /*
7527  * RX_VLAN (RO)
7528  *
7529  * Number of VLAN tagged frames
7530  */
7531 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_MASK (0xFFFFFFFFUL)
7532 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_SHIFT (0U)
7533 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_SHIFT)
7534 
7535 /* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_DROP_OVFL */
7536 /*
7537  * RX_DROP_OVFL (RO)
7538  *
7539  * Dropped frames by ingress overflow.
7540  */
7541 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_MASK (0xFFFFFFFFUL)
7542 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_SHIFT (0U)
7543 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_SHIFT)
7544 
7545 /* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_DROP_LU */
7546 /*
7547  * RX_DROP_LU (RO)
7548  *
7549  * Dropped frames by LookUp decision.
7550  */
7551 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_MASK (0xFFFFFFFFUL)
7552 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_SHIFT (0U)
7553 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_SHIFT)
7554 
7555 /* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_DROP_ERR */
7556 /*
7557  * RX_DROP_ERR (RO)
7558  *
7559  * Dropped frames with error by ingress. Possible in S&F mode or when frame is queued in ingress.
7560  */
7561 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_MASK (0xFFFFFFFFUL)
7562 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_SHIFT (0U)
7563 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_SHIFT)
7564 
7565 /* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_DROP_VLAN */
7566 /*
7567  * RX_DROP_VLAN (RO)
7568  *
7569  * Dropped frames by incompatible VLAN.
7570  */
7571 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_MASK (0xFFFFFFFFUL)
7572 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_SHIFT (0U)
7573 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_SHIFT)
7574 
7575 /* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_FPE_FGOOD */
7576 /*
7577  * RX_FPE_FGOOD (RO)
7578  *
7579  * Number of preemptable frames. Subset of RX_FGOOD
7580  */
7581 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_MASK (0xFFFFFFFFUL)
7582 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_SHIFT (0U)
7583 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_SHIFT)
7584 
7585 /* Bitfield definition for register of struct array TSNPORT: GPR_CTRL0 */
7586 /*
7587  * RXCLK_DLY_SEL (RW)
7588  *
7589  * delay value of rxclk_delay_chain
7590  */
7591 #define TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_MASK (0x3F00U)
7592 #define TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_SHIFT (8U)
7593 #define TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_SHIFT) & TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_MASK)
7594 #define TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_MASK) >> TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_SHIFT)
7595 
7596 /*
7597  * TXCLK_DLY_SEL (RW)
7598  *
7599  * delay value of txclk_delay_chain
7600  */
7601 #define TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_MASK (0x3FU)
7602 #define TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_SHIFT (0U)
7603 #define TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_SHIFT) & TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_MASK)
7604 #define TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_MASK) >> TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_SHIFT)
7605 
7606 /* Bitfield definition for register of struct array TSNPORT: GPR_CTRL2 */
7607 /*
7608  * MAC_SPEED (RW)
7609  *
7610  * mac speed
7611  * 00: 1000Mbps
7612  * 10: 10Mbps
7613  * 11: 100Mbps
7614  */
7615 #define TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_MASK (0x300000UL)
7616 #define TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_SHIFT (20U)
7617 #define TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_SET(x) (((uint32_t)(x) << TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_SHIFT) & TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_MASK)
7618 #define TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_GET(x) (((uint32_t)(x) & TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_MASK) >> TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_SHIFT)
7619 
7620 /*
7621  * PAD_OE_ETH_REFCLK (RW)
7622  *
7623  * RMII REFCLK output enable
7624  * 0: Disable REFCLK output
7625  * 1: Enable EFCLK output
7626  */
7627 #define TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_MASK (0x80000UL)
7628 #define TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_SHIFT (19U)
7629 #define TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_SET(x) (((uint32_t)(x) << TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_SHIFT) & TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_MASK)
7630 #define TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_GET(x) (((uint32_t)(x) & TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_MASK) >> TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_SHIFT)
7631 
7632 /*
7633  * PHY_INTF_SEL (RW)
7634  *
7635  * phy interface select
7636  * 000: MII
7637  * 001: RGMII
7638  * 100: RMII
7639  */
7640 #define TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_MASK (0xE000U)
7641 #define TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_SHIFT (13U)
7642 #define TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_SHIFT) & TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_MASK)
7643 #define TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_MASK) >> TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_SHIFT)
7644 
7645 /*
7646  * RMII_TXCLK_SEL (RW)
7647  *
7648  * refclk select for RMII
7649  * 0: Use RXCLK PAD
7650  * 1: Use TXCLK PAD
7651  */
7652 #define TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_MASK (0x400U)
7653 #define TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_SHIFT (10U)
7654 #define TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_SHIFT) & TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_MASK)
7655 #define TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_MASK) >> TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_SHIFT)
7656 
7657 
7658 
7659 /* HITMEM register group index macro definition */
7660 #define TSW_HITMEM_HITMEM_REG_1 (0UL)
7661 #define TSW_HITMEM_HITMEM_REG_2 (1UL)
7662 #define TSW_HITMEM_HITMEM_REG_3 (2UL)
7663 #define TSW_HITMEM_HITMEM_REG_4 (3UL)
7664 
7665 /* QCI_CNT register group index macro definition */
7666 #define TSW_QCI_CNT_CENTRAL_QCI_CNT0 (0UL)
7667 #define TSW_QCI_CNT_CENTRAL_QCI_CNT1 (1UL)
7668 #define TSW_QCI_CNT_CENTRAL_QCI_CNT2 (2UL)
7669 #define TSW_QCI_CNT_CENTRAL_QCI_CNT3 (3UL)
7670 #define TSW_QCI_CNT_CENTRAL_QCI_CNT4 (4UL)
7671 #define TSW_QCI_CNT_CENTRAL_QCI_CNT5 (5UL)
7672 
7673 /* EGFRCNT register group index macro definition */
7674 #define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT0 (0UL)
7675 #define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT1 (1UL)
7676 #define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT2 (2UL)
7677 #define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT3 (3UL)
7678 #define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT4 (4UL)
7679 #define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT5 (5UL)
7680 #define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT6 (6UL)
7681 #define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT7 (7UL)
7682 
7683 /* IGFRCNT register group index macro definition */
7684 #define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT0 (0UL)
7685 #define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT1 (1UL)
7686 #define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT2 (2UL)
7687 #define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT3 (3UL)
7688 #define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT4 (4UL)
7689 #define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT5 (5UL)
7690 #define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT6 (6UL)
7691 #define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT7 (7UL)
7692 
7693 /* MAC register group index macro definition */
7694 #define TSW_MAC_EM1 (0UL)
7695 #define TSW_MAC_PM1 (1UL)
7696 
7697 /* TSYNTMR register group index macro definition */
7698 #define TSW_TSNPORT_TSYNTMR_TSYN_TMR0 (0UL)
7699 #define TSW_TSNPORT_TSYNTMR_TSYN_TMR1 (1UL)
7700 #define TSW_TSNPORT_TSYNTMR_TSYN_TMR2 (2UL)
7701 #define TSW_TSNPORT_TSYNTMR_TSYN_TMR3 (3UL)
7702 #define TSW_TSNPORT_TSYNTMR_TSYN_TMR4 (4UL)
7703 
7704 /* RXDATA register group index macro definition */
7705 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD0 (0UL)
7706 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD1 (1UL)
7707 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD2 (2UL)
7708 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD3 (3UL)
7709 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD4 (4UL)
7710 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD5 (5UL)
7711 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD6 (6UL)
7712 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD7 (7UL)
7713 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD8 (8UL)
7714 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD9 (9UL)
7715 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD10 (10UL)
7716 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD11 (11UL)
7717 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD12 (12UL)
7718 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD13 (13UL)
7719 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD14 (14UL)
7720 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD15 (15UL)
7721 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD16 (16UL)
7722 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD17 (17UL)
7723 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD18 (18UL)
7724 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD19 (19UL)
7725 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD20 (20UL)
7726 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD21 (21UL)
7727 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD22 (22UL)
7728 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD23 (23UL)
7729 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD24 (24UL)
7730 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD25 (25UL)
7731 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD26 (26UL)
7732 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD27 (27UL)
7733 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD28 (28UL)
7734 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD29 (29UL)
7735 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD30 (30UL)
7736 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD31 (31UL)
7737 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD32 (32UL)
7738 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD33 (33UL)
7739 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD34 (34UL)
7740 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD35 (35UL)
7741 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD36 (36UL)
7742 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD37 (37UL)
7743 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD38 (38UL)
7744 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD39 (39UL)
7745 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD40 (40UL)
7746 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD41 (41UL)
7747 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD42 (42UL)
7748 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD43 (43UL)
7749 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD44 (44UL)
7750 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD45 (45UL)
7751 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD46 (46UL)
7752 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD47 (47UL)
7753 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD48 (48UL)
7754 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD49 (49UL)
7755 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD50 (50UL)
7756 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD51 (51UL)
7757 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD52 (52UL)
7758 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD53 (53UL)
7759 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD54 (54UL)
7760 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD55 (55UL)
7761 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD56 (56UL)
7762 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD57 (57UL)
7763 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD58 (58UL)
7764 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD59 (59UL)
7765 
7766 /* TXDATA register group index macro definition */
7767 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD0 (0UL)
7768 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD1 (1UL)
7769 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD2 (2UL)
7770 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD3 (3UL)
7771 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD4 (4UL)
7772 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD5 (5UL)
7773 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD6 (6UL)
7774 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD7 (7UL)
7775 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD8 (8UL)
7776 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD9 (9UL)
7777 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD10 (10UL)
7778 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD11 (11UL)
7779 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD12 (12UL)
7780 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD13 (13UL)
7781 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD14 (14UL)
7782 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD15 (15UL)
7783 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD16 (16UL)
7784 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD17 (17UL)
7785 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD18 (18UL)
7786 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD19 (19UL)
7787 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD20 (20UL)
7788 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD21 (21UL)
7789 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD22 (22UL)
7790 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD23 (23UL)
7791 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD24 (24UL)
7792 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD25 (25UL)
7793 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD26 (26UL)
7794 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD27 (27UL)
7795 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD28 (28UL)
7796 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD29 (29UL)
7797 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD30 (30UL)
7798 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD31 (31UL)
7799 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD32 (32UL)
7800 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD33 (33UL)
7801 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD34 (34UL)
7802 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD35 (35UL)
7803 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD36 (36UL)
7804 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD37 (37UL)
7805 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD38 (38UL)
7806 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD39 (39UL)
7807 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD40 (40UL)
7808 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD41 (41UL)
7809 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD42 (42UL)
7810 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD43 (43UL)
7811 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD44 (44UL)
7812 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD45 (45UL)
7813 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD46 (46UL)
7814 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD47 (47UL)
7815 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD48 (48UL)
7816 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD49 (49UL)
7817 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD50 (50UL)
7818 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD51 (51UL)
7819 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD52 (52UL)
7820 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD53 (53UL)
7821 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD54 (54UL)
7822 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD55 (55UL)
7823 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD56 (56UL)
7824 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD57 (57UL)
7825 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD58 (58UL)
7826 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD59 (59UL)
7827 
7828 /* BIN register group index macro definition */
7829 #define TSW_BIN_TX0 (0UL)
7830 #define TSW_BIN_TX1 (1UL)
7831 #define TSW_BIN_TX2 (2UL)
7832 #define TSW_BIN_TX3 (3UL)
7833 #define TSW_BIN_TX4 (4UL)
7834 #define TSW_BIN_TX5 (5UL)
7835 #define TSW_BIN_TX6 (6UL)
7836 #define TSW_BIN_TX7 (7UL)
7837 
7838 /* MXSDU register group index macro definition */
7839 #define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU0 (0UL)
7840 #define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU1 (1UL)
7841 #define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU2 (2UL)
7842 #define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU3 (3UL)
7843 #define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU4 (4UL)
7844 #define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU5 (5UL)
7845 #define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU6 (6UL)
7846 #define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU7 (7UL)
7847 
7848 /* TXSEL register group index macro definition */
7849 #define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL0 (0UL)
7850 #define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL1 (1UL)
7851 #define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL2 (2UL)
7852 #define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL3 (3UL)
7853 #define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL4 (4UL)
7854 #define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL5 (5UL)
7855 #define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL6 (6UL)
7856 #define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL7 (7UL)
7857 
7858 /* IDSEL register group index macro definition */
7859 #define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL0 (0UL)
7860 #define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL1 (1UL)
7861 #define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL2 (2UL)
7862 #define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL3 (3UL)
7863 #define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL04 (4UL)
7864 #define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL5 (5UL)
7865 #define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL6 (6UL)
7866 #define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL7 (7UL)
7867 
7868 /* MXTK register group index macro definition */
7869 #define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK0 (0UL)
7870 #define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK1 (1UL)
7871 #define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK2 (2UL)
7872 #define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK3 (3UL)
7873 #define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK4 (4UL)
7874 #define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK5 (5UL)
7875 #define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK6 (6UL)
7876 #define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK7 (7UL)
7877 
7878 /* TXOV register group index macro definition */
7879 #define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV0 (0UL)
7880 #define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV1 (1UL)
7881 #define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV2 (2UL)
7882 #define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV3 (3UL)
7883 #define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV4 (4UL)
7884 #define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV5 (5UL)
7885 #define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV6 (6UL)
7886 #define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV7 (7UL)
7887 
7888 /* SHACL register group index macro definition */
7889 #define TSW_SHACL_ENT0 (0UL)
7890 #define TSW_SHACL_ENT1 (1UL)
7891 #define TSW_SHACL_ENT2 (2UL)
7892 #define TSW_SHACL_ENT3 (3UL)
7893 #define TSW_SHACL_ENT4 (4UL)
7894 #define TSW_SHACL_ENT5 (5UL)
7895 #define TSW_SHACL_ENT6 (6UL)
7896 #define TSW_SHACL_ENT7 (7UL)
7897 #define TSW_SHACL_ENT8 (8UL)
7898 #define TSW_SHACL_ENT9 (9UL)
7899 #define TSW_SHACL_ENT10 (10UL)
7900 #define TSW_SHACL_ENT11 (11UL)
7901 #define TSW_SHACL_ENT12 (12UL)
7902 #define TSW_SHACL_ENT13 (13UL)
7903 #define TSW_SHACL_ENT14 (14UL)
7904 #define TSW_SHACL_ENT15 (15UL)
7905 #define TSW_SHACL_ENT16 (16UL)
7906 #define TSW_SHACL_ENT17 (17UL)
7907 #define TSW_SHACL_ENT18 (18UL)
7908 #define TSW_SHACL_ENT19 (19UL)
7909 #define TSW_SHACL_ENT20 (20UL)
7910 #define TSW_SHACL_ENT21 (21UL)
7911 #define TSW_SHACL_ENT22 (22UL)
7912 #define TSW_SHACL_ENT23 (23UL)
7913 #define TSW_SHACL_ENT24 (24UL)
7914 #define TSW_SHACL_ENT25 (25UL)
7915 #define TSW_SHACL_ENT26 (26UL)
7916 #define TSW_SHACL_ENT27 (27UL)
7917 #define TSW_SHACL_ENT28 (28UL)
7918 #define TSW_SHACL_ENT29 (29UL)
7919 #define TSW_SHACL_ENT30 (30UL)
7920 #define TSW_SHACL_ENT31 (31UL)
7921 #define TSW_SHACL_ENT32 (32UL)
7922 #define TSW_SHACL_ENT33 (33UL)
7923 #define TSW_SHACL_ENT34 (34UL)
7924 #define TSW_SHACL_ENT35 (35UL)
7925 #define TSW_SHACL_ENT36 (36UL)
7926 #define TSW_SHACL_ENT37 (37UL)
7927 #define TSW_SHACL_ENT38 (38UL)
7928 #define TSW_SHACL_ENT39 (39UL)
7929 #define TSW_SHACL_ENT40 (40UL)
7930 #define TSW_SHACL_ENT41 (41UL)
7931 #define TSW_SHACL_ENT42 (42UL)
7932 #define TSW_SHACL_ENT43 (43UL)
7933 #define TSW_SHACL_ENT44 (44UL)
7934 #define TSW_SHACL_ENT45 (45UL)
7935 #define TSW_SHACL_ENT46 (46UL)
7936 #define TSW_SHACL_ENT47 (47UL)
7937 #define TSW_SHACL_ENT48 (48UL)
7938 #define TSW_SHACL_ENT49 (49UL)
7939 #define TSW_SHACL_ENT50 (50UL)
7940 #define TSW_SHACL_ENT51 (51UL)
7941 #define TSW_SHACL_ENT52 (52UL)
7942 #define TSW_SHACL_ENT53 (53UL)
7943 #define TSW_SHACL_ENT54 (54UL)
7944 #define TSW_SHACL_ENT55 (55UL)
7945 #define TSW_SHACL_ENT56 (56UL)
7946 #define TSW_SHACL_ENT57 (57UL)
7947 #define TSW_SHACL_ENT58 (58UL)
7948 #define TSW_SHACL_ENT59 (59UL)
7949 #define TSW_SHACL_ENT60 (60UL)
7950 #define TSW_SHACL_ENT61 (61UL)
7951 #define TSW_SHACL_ENT62 (62UL)
7952 #define TSW_SHACL_ENT63 (63UL)
7953 #define TSW_SHACL_ENT64 (64UL)
7954 #define TSW_SHACL_ENT65 (65UL)
7955 #define TSW_SHACL_ENT66 (66UL)
7956 #define TSW_SHACL_ENT67 (67UL)
7957 #define TSW_SHACL_ENT68 (68UL)
7958 #define TSW_SHACL_ENT69 (69UL)
7959 #define TSW_SHACL_ENT70 (70UL)
7960 #define TSW_SHACL_ENT71 (71UL)
7961 #define TSW_SHACL_ENT72 (72UL)
7962 #define TSW_SHACL_ENT73 (73UL)
7963 #define TSW_SHACL_ENT74 (74UL)
7964 #define TSW_SHACL_ENT75 (75UL)
7965 #define TSW_SHACL_ENT76 (76UL)
7966 #define TSW_SHACL_ENT77 (77UL)
7967 #define TSW_SHACL_ENT78 (78UL)
7968 #define TSW_SHACL_ENT79 (79UL)
7969 #define TSW_SHACL_ENT80 (80UL)
7970 #define TSW_SHACL_ENT81 (81UL)
7971 #define TSW_SHACL_ENT82 (82UL)
7972 #define TSW_SHACL_ENT83 (83UL)
7973 #define TSW_SHACL_ENT84 (84UL)
7974 #define TSW_SHACL_ENT85 (85UL)
7975 #define TSW_SHACL_ENT86 (86UL)
7976 #define TSW_SHACL_ENT87 (87UL)
7977 #define TSW_SHACL_ENT88 (88UL)
7978 #define TSW_SHACL_ENT89 (89UL)
7979 #define TSW_SHACL_ENT90 (90UL)
7980 #define TSW_SHACL_ENT91 (91UL)
7981 #define TSW_SHACL_ENT92 (92UL)
7982 #define TSW_SHACL_ENT93 (93UL)
7983 #define TSW_SHACL_ENT94 (94UL)
7984 #define TSW_SHACL_ENT95 (95UL)
7985 #define TSW_SHACL_ENT96 (96UL)
7986 #define TSW_SHACL_ENT97 (97UL)
7987 #define TSW_SHACL_ENT98 (98UL)
7988 #define TSW_SHACL_ENT99 (99UL)
7989 #define TSW_SHACL_ENT100 (100UL)
7990 #define TSW_SHACL_ENT101 (101UL)
7991 #define TSW_SHACL_ENT102 (102UL)
7992 #define TSW_SHACL_ENT103 (103UL)
7993 #define TSW_SHACL_ENT104 (104UL)
7994 #define TSW_SHACL_ENT105 (105UL)
7995 #define TSW_SHACL_ENT106 (106UL)
7996 #define TSW_SHACL_ENT107 (107UL)
7997 #define TSW_SHACL_ENT108 (108UL)
7998 #define TSW_SHACL_ENT109 (109UL)
7999 #define TSW_SHACL_ENT110 (110UL)
8000 #define TSW_SHACL_ENT111 (111UL)
8001 #define TSW_SHACL_ENT112 (112UL)
8002 #define TSW_SHACL_ENT113 (113UL)
8003 #define TSW_SHACL_ENT114 (114UL)
8004 #define TSW_SHACL_ENT115 (115UL)
8005 #define TSW_SHACL_ENT116 (116UL)
8006 #define TSW_SHACL_ENT117 (117UL)
8007 #define TSW_SHACL_ENT118 (118UL)
8008 #define TSW_SHACL_ENT119 (119UL)
8009 #define TSW_SHACL_ENT120 (120UL)
8010 #define TSW_SHACL_ENT121 (121UL)
8011 #define TSW_SHACL_ENT122 (122UL)
8012 #define TSW_SHACL_ENT123 (123UL)
8013 #define TSW_SHACL_ENT124 (124UL)
8014 #define TSW_SHACL_ENT125 (125UL)
8015 #define TSW_SHACL_ENT126 (126UL)
8016 #define TSW_SHACL_ENT127 (127UL)
8017 #define TSW_SHACL_ENT128 (128UL)
8018 #define TSW_SHACL_ENT129 (129UL)
8019 #define TSW_SHACL_ENT130 (130UL)
8020 #define TSW_SHACL_ENT131 (131UL)
8021 #define TSW_SHACL_ENT132 (132UL)
8022 #define TSW_SHACL_ENT133 (133UL)
8023 #define TSW_SHACL_ENT134 (134UL)
8024 #define TSW_SHACL_ENT135 (135UL)
8025 #define TSW_SHACL_ENT136 (136UL)
8026 #define TSW_SHACL_ENT137 (137UL)
8027 #define TSW_SHACL_ENT138 (138UL)
8028 #define TSW_SHACL_ENT139 (139UL)
8029 #define TSW_SHACL_ENT140 (140UL)
8030 #define TSW_SHACL_ENT141 (141UL)
8031 #define TSW_SHACL_ENT142 (142UL)
8032 #define TSW_SHACL_ENT143 (143UL)
8033 #define TSW_SHACL_ENT144 (144UL)
8034 #define TSW_SHACL_ENT145 (145UL)
8035 #define TSW_SHACL_ENT146 (146UL)
8036 #define TSW_SHACL_ENT147 (147UL)
8037 #define TSW_SHACL_ENT148 (148UL)
8038 #define TSW_SHACL_ENT149 (149UL)
8039 #define TSW_SHACL_ENT150 (150UL)
8040 #define TSW_SHACL_ENT151 (151UL)
8041 #define TSW_SHACL_ENT152 (152UL)
8042 #define TSW_SHACL_ENT153 (153UL)
8043 #define TSW_SHACL_ENT154 (154UL)
8044 #define TSW_SHACL_ENT155 (155UL)
8045 #define TSW_SHACL_ENT156 (156UL)
8046 #define TSW_SHACL_ENT157 (157UL)
8047 #define TSW_SHACL_ENT158 (158UL)
8048 #define TSW_SHACL_ENT159 (159UL)
8049 #define TSW_SHACL_ENT160 (160UL)
8050 #define TSW_SHACL_ENT161 (161UL)
8051 #define TSW_SHACL_ENT162 (162UL)
8052 #define TSW_SHACL_ENT163 (163UL)
8053 #define TSW_SHACL_ENT164 (164UL)
8054 #define TSW_SHACL_ENT165 (165UL)
8055 #define TSW_SHACL_ENT166 (166UL)
8056 #define TSW_SHACL_ENT167 (167UL)
8057 #define TSW_SHACL_ENT168 (168UL)
8058 #define TSW_SHACL_ENT169 (169UL)
8059 #define TSW_SHACL_ENT170 (170UL)
8060 #define TSW_SHACL_ENT171 (171UL)
8061 #define TSW_SHACL_ENT172 (172UL)
8062 #define TSW_SHACL_ENT173 (173UL)
8063 #define TSW_SHACL_ENT174 (174UL)
8064 #define TSW_SHACL_ENT175 (175UL)
8065 #define TSW_SHACL_ENT176 (176UL)
8066 #define TSW_SHACL_ENT177 (177UL)
8067 #define TSW_SHACL_ENT178 (178UL)
8068 #define TSW_SHACL_ENT179 (179UL)
8069 #define TSW_SHACL_ENT180 (180UL)
8070 #define TSW_SHACL_ENT181 (181UL)
8071 #define TSW_SHACL_ENT182 (182UL)
8072 #define TSW_SHACL_ENT183 (183UL)
8073 #define TSW_SHACL_ENT184 (184UL)
8074 #define TSW_SHACL_ENT185 (185UL)
8075 #define TSW_SHACL_ENT186 (186UL)
8076 #define TSW_SHACL_ENT187 (187UL)
8077 #define TSW_SHACL_ENT188 (188UL)
8078 #define TSW_SHACL_ENT189 (189UL)
8079 #define TSW_SHACL_ENT190 (190UL)
8080 #define TSW_SHACL_ENT191 (191UL)
8081 #define TSW_SHACL_ENT192 (192UL)
8082 #define TSW_SHACL_ENT193 (193UL)
8083 #define TSW_SHACL_ENT194 (194UL)
8084 #define TSW_SHACL_ENT195 (195UL)
8085 #define TSW_SHACL_ENT196 (196UL)
8086 #define TSW_SHACL_ENT197 (197UL)
8087 #define TSW_SHACL_ENT198 (198UL)
8088 #define TSW_SHACL_ENT199 (199UL)
8089 #define TSW_SHACL_ENT200 (200UL)
8090 #define TSW_SHACL_ENT201 (201UL)
8091 #define TSW_SHACL_ENT202 (202UL)
8092 #define TSW_SHACL_ENT203 (203UL)
8093 #define TSW_SHACL_ENT204 (204UL)
8094 #define TSW_SHACL_ENT205 (205UL)
8095 #define TSW_SHACL_ENT206 (206UL)
8096 #define TSW_SHACL_ENT207 (207UL)
8097 #define TSW_SHACL_ENT208 (208UL)
8098 #define TSW_SHACL_ENT209 (209UL)
8099 #define TSW_SHACL_ENT210 (210UL)
8100 #define TSW_SHACL_ENT211 (211UL)
8101 #define TSW_SHACL_ENT212 (212UL)
8102 #define TSW_SHACL_ENT213 (213UL)
8103 #define TSW_SHACL_ENT214 (214UL)
8104 #define TSW_SHACL_ENT215 (215UL)
8105 #define TSW_SHACL_ENT216 (216UL)
8106 #define TSW_SHACL_ENT217 (217UL)
8107 #define TSW_SHACL_ENT218 (218UL)
8108 #define TSW_SHACL_ENT219 (219UL)
8109 #define TSW_SHACL_ENT220 (220UL)
8110 #define TSW_SHACL_ENT221 (221UL)
8111 #define TSW_SHACL_ENT222 (222UL)
8112 #define TSW_SHACL_ENT223 (223UL)
8113 #define TSW_SHACL_ENT224 (224UL)
8114 #define TSW_SHACL_ENT225 (225UL)
8115 #define TSW_SHACL_ENT226 (226UL)
8116 #define TSW_SHACL_ENT227 (227UL)
8117 #define TSW_SHACL_ENT228 (228UL)
8118 #define TSW_SHACL_ENT229 (229UL)
8119 #define TSW_SHACL_ENT230 (230UL)
8120 #define TSW_SHACL_ENT231 (231UL)
8121 #define TSW_SHACL_ENT232 (232UL)
8122 #define TSW_SHACL_ENT233 (233UL)
8123 #define TSW_SHACL_ENT234 (234UL)
8124 #define TSW_SHACL_ENT235 (235UL)
8125 #define TSW_SHACL_ENT236 (236UL)
8126 #define TSW_SHACL_ENT237 (237UL)
8127 #define TSW_SHACL_ENT238 (238UL)
8128 #define TSW_SHACL_ENT239 (239UL)
8129 #define TSW_SHACL_ENT240 (240UL)
8130 #define TSW_SHACL_ENT241 (241UL)
8131 #define TSW_SHACL_ENT242 (242UL)
8132 #define TSW_SHACL_ENT243 (243UL)
8133 #define TSW_SHACL_ENT244 (244UL)
8134 #define TSW_SHACL_ENT245 (245UL)
8135 #define TSW_SHACL_ENT246 (246UL)
8136 #define TSW_SHACL_ENT247 (247UL)
8137 #define TSW_SHACL_ENT248 (248UL)
8138 #define TSW_SHACL_ENT249 (249UL)
8139 #define TSW_SHACL_ENT250 (250UL)
8140 #define TSW_SHACL_ENT251 (251UL)
8141 #define TSW_SHACL_ENT252 (252UL)
8142 #define TSW_SHACL_ENT253 (253UL)
8143 #define TSW_SHACL_ENT254 (254UL)
8144 #define TSW_SHACL_ENT255 (255UL)
8145 
8146 /* RXFIFO register group index macro definition */
8147 #define TSW_RXFIFO_E1 (0UL)
8148 #define TSW_RXFIFO_P1 (1UL)
8149 
8150 /* TSNPORT register group index macro definition */
8151 #define TSW_TSNPORT_PORT1 (0UL)
8152 #define TSW_TSNPORT_PORT2 (1UL)
8153 #define TSW_TSNPORT_PORT3 (2UL)
8154 
8155 
8156 #endif /* HPM_TSW_H */
TSW_Type
Definition: hpm_tsw_regs.h:12