hpm_wdg_drv.h

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/*
 * Copyright (c) 2021-2023,2025 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
 */
 
#ifndef HPM_WDG_DRV_H
#define HPM_WDG_DRV_H
 
#include "hpm_common.h"
#include "hpm_wdg_regs.h"
 
typedef enum reset_interval_enum {
    reset_interval_clock_period_mult_128    = 0,
    reset_interval_clock_period_mult_256    = 1,
    reset_interval_clock_period_mult_512    = 2,
    reset_interval_clock_period_mult_1k     = 3,
    reset_interval_clock_period_mult_2k     = 4,
    reset_interval_clock_period_mult_4k     = 5,
    reset_interval_clock_period_mult_8k     = 6,
    reset_interval_clock_period_mult_16k    = 7,
    reset_interval_max = reset_interval_clock_period_mult_16k,
    reset_interval_out_of_range,
} reset_interval_t;
 
typedef enum interrupt_interval_enum {
    interrupt_interval_clock_period_multi_64     = 0,
    interrupt_interval_clock_period_multi_256    = 1,
    interrupt_interval_clock_period_multi_1k     = 2,
    interrupt_interval_clock_period_multi_2k     = 3,
    interrupt_interval_clock_period_multi_4k     = 4,
    interrupt_interval_clock_period_multi_8k     = 5,
    interrupt_interval_clock_period_multi_16k    = 6,
    interrupt_interval_clock_period_multi_32k    = 7,
    interrupt_interval_clock_period_multi_128k   = 8,
    interrupt_interval_clock_period_multi_512k   = 9,
    interrupt_interval_clock_period_multi_2m     = 10,
    interrupt_interval_clock_period_multi_8m     = 11,
    interrupt_interval_clock_period_multi_32m     = 12,
    interrupt_interval_clock_period_multi_128m    = 13,
    interrupt_interval_clock_period_multi_512m   = 14,
    interrupt_interval_clock_period_multi_2g   = 15,
    interrupt_interval_max = interrupt_interval_clock_period_multi_2g,
    interrupt_interval_out_of_range,
} interrupt_interval_t;
 
typedef enum wdg_clksrc_enum {
    wdg_clksrc_extclk,                  
    wdg_clksrc_pclk,                    
    wdg_clksrc_max = wdg_clksrc_pclk
} wdg_clksrc_t;
 
typedef struct wdg_control_struct {
    reset_interval_t reset_interval;            
    interrupt_interval_t interrupt_interval;    
    bool reset_enable;                          
    bool interrupt_enable;                      
    wdg_clksrc_t clksrc;                        
    bool wdg_enable;                            
} wdg_control_t;
 
#define WDG_WRITE_ENABLE_MAGIC_NUM (0x5AA5UL)   
#define WDG_RESTART_MAGIC_NUM (0xCAFEUL)        
#define WDG_EXT_CLK_FREQ (32768UL)              
#define PWDG_PERIPH_CLK_FREQ (24000000UL)       
#ifdef __cplusplus
extern "C" {
#endif
 
static inline void wdg_write_enable(WDG_Type *base)
{
    base->WREN = WDG_WRITE_ENABLE_MAGIC_NUM;
}
 
static inline void wdg_enable(WDG_Type *base)
{
    wdg_write_enable(base);
    base->CTRL |= WDG_CTRL_EN_MASK;
}
 
static inline void wdg_disable(WDG_Type *base)
{
    wdg_write_enable(base);
    base->CTRL &= ~WDG_CTRL_EN_MASK;
}
 
static inline void wdg_reset_enable(WDG_Type *base)
{
    wdg_write_enable(base);
    base->CTRL |= WDG_CTRL_RSTEN_MASK;
}
 
static inline void wdg_reset_disable(WDG_Type *base)
{
    wdg_write_enable(base);
    base->CTRL &= ~WDG_CTRL_RSTEN_MASK;
}
 
 
static inline void wdg_interrupt_enable(WDG_Type *base)
{
    wdg_write_enable(base);
    base->CTRL |= WDG_CTRL_INTEN_MASK;
}
 
static inline void wdg_interrupt_disable(WDG_Type *base)
{
    wdg_write_enable(base);
    base->CTRL &= ~WDG_CTRL_INTEN_MASK;
}
 
static inline void wdg_clksrc_select(WDG_Type *base, wdg_clksrc_t clksrc)
{
    if (clksrc == wdg_clksrc_extclk) {
        base->CTRL &= ~WDG_CTRL_CLKSEL_MASK;
    } else {
        base->CTRL |= WDG_CTRL_CLKSEL_MASK;
    }
}
 
static inline void wdg_restart(WDG_Type *base)
{
    wdg_write_enable(base);
    base->RESTART = WDG_RESTART_MAGIC_NUM;
}
 
static inline uint32_t wdg_get_status(WDG_Type *base)
{
    return base->ST;
}
 
static inline void wdg_clear_status(WDG_Type *base, uint32_t status_mask)
{
    base->ST = status_mask;
}
 
hpm_stat_t wdg_init(WDG_Type *base, wdg_control_t *wdg_ctrl);
 
reset_interval_t wdg_convert_reset_interval_from_us(const uint32_t src_freq, const uint32_t reset_us);
 
 uint64_t wdg_convert_interrupt_interval_to_us(const uint32_t src_freq, interrupt_interval_t interval);
 
uint32_t wdg_convert_reset_interval_to_us(const uint32_t src_freq, reset_interval_t interval);
 
interrupt_interval_t wdg_convert_interrupt_interval_from_us(const uint32_t src_freq, uint32_t interval_us);
 
uint64_t wdg_get_interrupt_interval_in_us(WDG_Type *base, const uint32_t src_freq);
 
uint64_t wdg_get_total_reset_interval_in_us(WDG_Type *base, const uint32_t src_freq);
 
#ifdef __cplusplus
}
#endif
 
#endif /* HPM_WDG_DRV_H */