HPM SDK
HPMicro Software Development Kit
hpm_jl1111_regs.h
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1 /*
2  * Copyright (c) 2024 hpmicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_JL1111_REGS_H
10 #define HPM_JL1111_REGS_H
11 
12 typedef enum {
13  JL1111_BMCR = 0, /* 0x0: Basic Mode Control Register */
14  JL1111_BMSR = 1, /* 0x1: Basic Mode Status Register */
15  JL1111_PHYID1 = 2, /* 0x2: PHY Identifier Register 1 */
16  JL1111_PHYID2 = 3, /* 0x3: PHY Identifier Register 2 */
17  JL1111_ANAR = 4, /* 0x4: Auto-Negotiation Advertisement Register */
18  JL1111_ANLPAR = 5, /* 0x5: Auto-Negotiation Link Partner Ability Register */
19  JL1111_MMDAC = 19, /* 0x13: MMD Access Control Register */
20  JL1111_MMDAAD = 20, /* 0x14: MMD Access Address Data Register */
21  JL1111_RMSR_P7 = 22, /* 0x16: RMII Mode Setting Register */
22  JL1111_INTSQI = 48, /* 0x30: Interrupt Indicators and Signal Quality Indicator Register */
23  JL1111_PAGESEL = 49, /* 0x31: Page Select Register */
24 } JL1111_REG_Type;
25 
26 
27 /* Bitfield definition for register: BMCR */
28 /*
29  * RESET (RW/SC)
30  *
31  * 1: PHY reset
32  * 0: normal operation
33  * After software reset, need to delay 10ms de-assert time for chip steady.
34  */
35 #define JL1111_BMCR_RESET_MASK (0x8000U)
36 #define JL1111_BMCR_RESET_SHIFT (15U)
37 #define JL1111_BMCR_RESET_SET(x) (((uint16_t)(x) << JL1111_BMCR_RESET_SHIFT) & JL1111_BMCR_RESET_MASK)
38 #define JL1111_BMCR_RESET_GET(x) (((uint16_t)(x) & JL1111_BMCR_RESET_MASK) >> JL1111_BMCR_RESET_SHIFT)
39 
40 /*
41  * LOOPBACK (RW)
42  *
43  * This bit enables loopback of transmit data nibbles TXD3:0 to the
44  * receive data path.
45  * 1: Enable loopback 0: Normal operation
46  */
47 #define JL1111_BMCR_LOOPBACK_MASK (0x4000U)
48 #define JL1111_BMCR_LOOPBACK_SHIFT (14U)
49 #define JL1111_BMCR_LOOPBACK_SET(x) (((uint16_t)(x) << JL1111_BMCR_LOOPBACK_SHIFT) & JL1111_BMCR_LOOPBACK_MASK)
50 #define JL1111_BMCR_LOOPBACK_GET(x) (((uint16_t)(x) & JL1111_BMCR_LOOPBACK_MASK) >> JL1111_BMCR_LOOPBACK_SHIFT)
51 
52 /*
53  * SPEED0 (RW)
54  *
55  * This bit sets the network speed.
56  * 1: 100Mbps 0: 10Mbps
57  */
58 #define JL1111_BMCR_SPEED0_MASK (0x2000U)
59 #define JL1111_BMCR_SPEED0_SHIFT (13U)
60 #define JL1111_BMCR_SPEED0_SET(x) (((uint16_t)(x) << JL1111_BMCR_SPEED0_SHIFT) & JL1111_BMCR_SPEED0_MASK)
61 #define JL1111_BMCR_SPEED0_GET(x) (((uint16_t)(x) & JL1111_BMCR_SPEED0_MASK) >> JL1111_BMCR_SPEED0_SHIFT)
62 
63 /*
64  * ANE (RW)
65  *
66  * This bit enables/disables the NWay auto-negotiation function.
67  * 1: Enable auto-negotiation; bits 0:13 and 0:8 will be ignored
68  * 0: Disable auto-negotiation; bits 0:13 and 0:8 will determine the
69  * link speed and the data transfer mode
70  */
71 #define JL1111_BMCR_ANE_MASK (0x1000U)
72 #define JL1111_BMCR_ANE_SHIFT (12U)
73 #define JL1111_BMCR_ANE_SET(x) (((uint16_t)(x) << JL1111_BMCR_ANE_SHIFT) & JL1111_BMCR_ANE_MASK)
74 #define JL1111_BMCR_ANE_GET(x) (((uint16_t)(x) & JL1111_BMCR_ANE_MASK) >> JL1111_BMCR_ANE_SHIFT)
75 
76 /*
77  * PWD (RW)
78  *
79  * This bit turns down the power of the PHY chip
80  * The MDC, MDIO is still alive for accessing the MAC.
81  * 1: Power down 0: Normal operation
82  */
83 #define JL1111_BMCR_PWD_MASK (0x800U)
84 #define JL1111_BMCR_PWD_SHIFT (11U)
85 #define JL1111_BMCR_PWD_SET(x) (((uint16_t)(x) << JL1111_BMCR_PWD_SHIFT) & JL1111_BMCR_PWD_MASK)
86 #define JL1111_BMCR_PWD_GET(x) (((uint16_t)(x) & JL1111_BMCR_PWD_MASK) >> JL1111_BMCR_PWD_SHIFT)
87 
88 /*
89  * ISOLATE (RW)
90  *
91  * 1: Electrically isolate the PHY from MII/RMII
92  * PHY is still able to respond to MDC/MDIO.
93  * 0: Normal operation
94  */
95 #define JL1111_BMCR_ISOLATE_MASK (0x400U)
96 #define JL1111_BMCR_ISOLATE_SHIFT (10U)
97 #define JL1111_BMCR_ISOLATE_SET(x) (((uint16_t)(x) << JL1111_BMCR_ISOLATE_SHIFT) & JL1111_BMCR_ISOLATE_MASK)
98 #define JL1111_BMCR_ISOLATE_GET(x) (((uint16_t)(x) & JL1111_BMCR_ISOLATE_MASK) >> JL1111_BMCR_ISOLATE_SHIFT)
99 
100 /*
101  * RESTART_AN (RW/SC)
102  *
103  * This bit allows the NWay auto-negotiation function to be reset.
104  * 1: Re-start auto-negotiation 0: Normal operation
105  */
106 #define JL1111_BMCR_RESTART_AN_MASK (0x200U)
107 #define JL1111_BMCR_RESTART_AN_SHIFT (9U)
108 #define JL1111_BMCR_RESTART_AN_SET(x) (((uint16_t)(x) << JL1111_BMCR_RESTART_AN_SHIFT) & JL1111_BMCR_RESTART_AN_MASK)
109 #define JL1111_BMCR_RESTART_AN_GET(x) (((uint16_t)(x) & JL1111_BMCR_RESTART_AN_MASK) >> JL1111_BMCR_RESTART_AN_SHIFT)
110 
111 /*
112  * DUPLEX (RW)
113  *
114  * This bit sets the duplex mode if auto-negotiation is disabled (bit
115  * 0:12=0).
116  * 1: Full duplex 0: Half duplex
117  */
118 #define JL1111_BMCR_DUPLEX_MASK (0x100U)
119 #define JL1111_BMCR_DUPLEX_SHIFT (8U)
120 #define JL1111_BMCR_DUPLEX_SET(x) (((uint16_t)(x) << JL1111_BMCR_DUPLEX_SHIFT) & JL1111_BMCR_DUPLEX_MASK)
121 #define JL1111_BMCR_DUPLEX_GET(x) (((uint16_t)(x) & JL1111_BMCR_DUPLEX_MASK) >> JL1111_BMCR_DUPLEX_SHIFT)
122 
123 /*
124  * COLLISION_TEST (RW)
125  *
126  * Collision Test.
127  * 1: Collision test enabled
128  * 0: Normal operation
129  * When set, this bit will cause the COL signal to be asserted in
130  * response to the TXEN assertion within 512-bit times. The COL
131  * signal will be de-asserted within 4-bit times in response to the
132  * TXEN de-assertion.
133  */
134 #define JL1111_BMCR_COLLISION_TEST_MASK (0x80U)
135 #define JL1111_BMCR_COLLISION_TEST_SHIFT (7U)
136 #define JL1111_BMCR_COLLISION_TEST_SET(x) (((uint16_t)(x) << JL1111_BMCR_COLLISION_TEST_SHIFT) & JL1111_BMCR_COLLISION_TEST_MASK)
137 #define JL1111_BMCR_COLLISION_TEST_GET(x) (((uint16_t)(x) & JL1111_BMCR_COLLISION_TEST_MASK) >> JL1111_BMCR_COLLISION_TEST_SHIFT)
138 
139 /*
140  * SPEED1 (RW)
141  *
142  * Speed Select Bit 1.
143  * Refer to bit 13.
144  */
145 #define JL1111_BMCR_SPEED1_MASK (0x40U)
146 #define JL1111_BMCR_SPEED1_SHIFT (6U)
147 #define JL1111_BMCR_SPEED1_SET(x) (((uint16_t)(x) << JL1111_BMCR_SPEED1_SHIFT) & JL1111_BMCR_SPEED1_MASK)
148 #define JL1111_BMCR_SPEED1_GET(x) (((uint16_t)(x) & JL1111_BMCR_SPEED1_MASK) >> JL1111_BMCR_SPEED1_SHIFT)
149 
150 /* Bitfield definition for register: BMSR */
151 /*
152  * BASE100_T4_1 (RO)
153  *
154  * 1: Enable 100Base-T4 support
155  * 0: Suppress 100Base-T4 support
156  */
157 #define JL1111_BMSR_BASE100_T4_1_MASK (0x8000U)
158 #define JL1111_BMSR_BASE100_T4_1_SHIFT (15U)
159 #define JL1111_BMSR_BASE100_T4_1_GET(x) (((uint16_t)(x) & JL1111_BMSR_BASE100_T4_1_MASK) >> JL1111_BMSR_BASE100_T4_1_SHIFT)
160 
161 /*
162  * BASE100_TX_FD_1 (RO)
163  *
164  * 1: Enable 100Base-TX full duplex support
165  * 0: Suppress 100Base-TX full duplex support
166  */
167 #define JL1111_BMSR_BASE100_TX_FD_1_MASK (0x4000U)
168 #define JL1111_BMSR_BASE100_TX_FD_1_SHIFT (14U)
169 #define JL1111_BMSR_BASE100_TX_FD_1_GET(x) (((uint16_t)(x) & JL1111_BMSR_BASE100_TX_FD_1_MASK) >> JL1111_BMSR_BASE100_TX_FD_1_SHIFT)
170 
171 /*
172  * BASE100_TX_HD_1 (RO)
173  *
174  * 1: Enable 100Base-TX half duplex support
175  * 0: Suppress 100Base-TX half duplex support
176  */
177 #define JL1111_BMSR_BASE100_TX_HD_1_MASK (0x2000U)
178 #define JL1111_BMSR_BASE100_TX_HD_1_SHIFT (13U)
179 #define JL1111_BMSR_BASE100_TX_HD_1_GET(x) (((uint16_t)(x) & JL1111_BMSR_BASE100_TX_HD_1_MASK) >> JL1111_BMSR_BASE100_TX_HD_1_SHIFT)
180 
181 /*
182  * BASE10_TX_FD (RO)
183  *
184  * 1: Enable 10Base-T full duplex support
185  * 0: Suppress 10Base-T full duplex support
186  */
187 #define JL1111_BMSR_BASE10_TX_FD_MASK (0x1000U)
188 #define JL1111_BMSR_BASE10_TX_FD_SHIFT (12U)
189 #define JL1111_BMSR_BASE10_TX_FD_GET(x) (((uint16_t)(x) & JL1111_BMSR_BASE10_TX_FD_MASK) >> JL1111_BMSR_BASE10_TX_FD_SHIFT)
190 
191 /*
192  * BASE10_TX_HD (RO)
193  *
194  * 1: Enable 10Base-T half duplex support
195  * 0: Suppress 10Base-T half duplex support
196  */
197 #define JL1111_BMSR_BASE10_TX_HD_MASK (0x800U)
198 #define JL1111_BMSR_BASE10_TX_HD_SHIFT (11U)
199 #define JL1111_BMSR_BASE10_TX_HD_GET(x) (((uint16_t)(x) & JL1111_BMSR_BASE10_TX_HD_MASK) >> JL1111_BMSR_BASE10_TX_HD_SHIFT)
200 
201 /*
202  * MDIO_MFPS (RO)
203  *
204  */
205 #define JL1111_BMSR_MDIO_MFPS_MASK (0x40U)
206 #define JL1111_BMSR_MDIO_MFPS_SHIFT (6U)
207 #define JL1111_BMSR_MDIO_MFPS_GET(x) (((uint16_t)(x) & JL1111_BMSR_MDIO_MFPS_MASK) >> JL1111_BMSR_MDIO_MFPS_SHIFT)
208 
209 /*
210  * AUTO_NEGOTIATION_COMPLETE (RO)
211  *
212  * 1: Auto-negotiation process completed
213  * 0: Auto-negotiation process not completed
214  */
215 #define JL1111_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK (0x20U)
216 #define JL1111_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT (5U)
217 #define JL1111_BMSR_AUTO_NEGOTIATION_COMPLETE_GET(x) (((uint16_t)(x) & JL1111_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK) >> JL1111_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT)
218 
219 /*
220  * REMOTE_FAULT (RC)
221  *
222  * 1: Remote fault condition detected (cleared on read)
223  * 0: No remote fault condition detected
224  */
225 #define JL1111_BMSR_REMOTE_FAULT_MASK (0x10U)
226 #define JL1111_BMSR_REMOTE_FAULT_SHIFT (4U)
227 #define JL1111_BMSR_REMOTE_FAULT_GET(x) (((uint16_t)(x) & JL1111_BMSR_REMOTE_FAULT_MASK) >> JL1111_BMSR_REMOTE_FAULT_SHIFT)
228 
229 /*
230  * AUTO_NEGOTIATION_ABILITY (RO)
231  *
232  * 1: PHY is able to perform auto-negotiation
233  * 0: PHY is not able to perform auto-negotiation
234  */
235 #define JL1111_BMSR_AUTO_NEGOTIATION_ABILITY_MASK (0x8U)
236 #define JL1111_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT (3U)
237 #define JL1111_BMSR_AUTO_NEGOTIATION_ABILITY_GET(x) (((uint16_t)(x) & JL1111_BMSR_AUTO_NEGOTIATION_ABILITY_MASK) >> JL1111_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT)
238 
239 /*
240  * LINK_STATUS (RO)
241  *
242  * 1: Valid link established
243  * 0: No valid link established
244  */
245 #define JL1111_BMSR_LINK_STATUS_MASK (0x4U)
246 #define JL1111_BMSR_LINK_STATUS_SHIFT (2U)
247 #define JL1111_BMSR_LINK_STATUS_GET(x) (((uint16_t)(x) & JL1111_BMSR_LINK_STATUS_MASK) >> JL1111_BMSR_LINK_STATUS_SHIFT)
248 
249 /*
250  * JABBER_DETECT (RO)
251  *
252  * 1: Jabber condition detected
253  * 0: No jabber condition detected
254  */
255 #define JL1111_BMSR_JABBER_DETECT_MASK (0x2U)
256 #define JL1111_BMSR_JABBER_DETECT_SHIFT (1U)
257 #define JL1111_BMSR_JABBER_DETECT_GET(x) (((uint16_t)(x) & JL1111_BMSR_JABBER_DETECT_MASK) >> JL1111_BMSR_JABBER_DETECT_SHIFT)
258 
259 /*
260  * EXTENDED_CAPABILITY (RO)
261  *
262  * 1: Extended register capable (permanently=1)
263  * 0: Not extended register capable
264  */
265 #define JL1111_BMSR_EXTENDED_CAPABILITY_MASK (0x1U)
266 #define JL1111_BMSR_EXTENDED_CAPABILITY_SHIFT (0U)
267 #define JL1111_BMSR_EXTENDED_CAPABILITY_GET(x) (((uint16_t)(x) & JL1111_BMSR_EXTENDED_CAPABILITY_MASK) >> JL1111_BMSR_EXTENDED_CAPABILITY_SHIFT)
268 
269 /* Bitfield definition for register: PHYID1 */
270 /*
271  * OUI_MSB (RO)
272  *
273  * JLSemi OUI is 0x24DF10
274  * 0010 0100 1101 1111 0001 0000
275  * BIT1.......................................................BIT24
276  * Register 2.[15:0] show bit3 to 18 of OUI
277  * 1001 0011 0111 1100
278  * BIT3................................BIT18
279  */
280 #define JL1111_PHYID1_OUI_MSB_MASK (0xFFFFU)
281 #define JL1111_PHYID1_OUI_MSB_SHIFT (0U)
282 #define JL1111_PHYID1_OUI_MSB_GET(x) (((uint16_t)(x) & JL1111_PHYID1_OUI_MSB_MASK) >> JL1111_PHYID1_OUI_MSB_SHIFT)
283 
284 /* Bitfield definition for register: PHYID2 */
285 /*
286  * OUI_LSB (RO)
287  *
288  * Organizationally Unique Identifier bits 19:24
289  * 01 0000
290  * bit19....bit24
291  */
292 #define JL1111_PHYID2_OUI_LSB_MASK (0xFC00U)
293 #define JL1111_PHYID2_OUI_LSB_SHIFT (10U)
294 #define JL1111_PHYID2_OUI_LSB_GET(x) (((uint16_t)(x) & JL1111_PHYID2_OUI_LSB_MASK) >> JL1111_PHYID2_OUI_LSB_SHIFT)
295 
296 /*
297  * MODEL_NUMBER (RO)
298  *
299  * Model Number
300  */
301 #define JL1111_PHYID2_MODEL_NUMBER_MASK (0x3F0U)
302 #define JL1111_PHYID2_MODEL_NUMBER_SHIFT (4U)
303 #define JL1111_PHYID2_MODEL_NUMBER_GET(x) (((uint16_t)(x) & JL1111_PHYID2_MODEL_NUMBER_MASK) >> JL1111_PHYID2_MODEL_NUMBER_SHIFT)
304 
305 /*
306  * REVISION_NUMBER (RO)
307  *
308  * Contact JLSemi FAEs for information on the device revision number
309  */
310 #define JL1111_PHYID2_REVISION_NUMBER_MASK (0xFU)
311 #define JL1111_PHYID2_REVISION_NUMBER_SHIFT (0U)
312 #define JL1111_PHYID2_REVISION_NUMBER_GET(x) (((uint16_t)(x) & JL1111_PHYID2_REVISION_NUMBER_MASK) >> JL1111_PHYID2_REVISION_NUMBER_SHIFT)
313 
314 /* Bitfield definition for register: ANAR */
315 /*
316  * NEXT_PAGE (RW)
317  *
318  * Next Page Bit.
319  * 0: Transmitting the primary capability data page
320  * 1: Transmitting the protocol specific data page
321  */
322 #define JL1111_ANAR_NEXT_PAGE_MASK (0x8000U)
323 #define JL1111_ANAR_NEXT_PAGE_SHIFT (15U)
324 #define JL1111_ANAR_NEXT_PAGE_SET(x) (((uint16_t)(x) << JL1111_ANAR_NEXT_PAGE_SHIFT) & JL1111_ANAR_NEXT_PAGE_MASK)
325 #define JL1111_ANAR_NEXT_PAGE_GET(x) (((uint16_t)(x) & JL1111_ANAR_NEXT_PAGE_MASK) >> JL1111_ANAR_NEXT_PAGE_SHIFT)
326 
327 /*
328  * ACKNOWLEDGE (RO)
329  *
330  * 1: Acknowledge reception of link partner capability data world
331  * 0: Do not acknowledge reception
332  */
333 #define JL1111_ANAR_ACKNOWLEDGE_MASK (0x4000U)
334 #define JL1111_ANAR_ACKNOWLEDGE_SHIFT (14U)
335 #define JL1111_ANAR_ACKNOWLEDGE_GET(x) (((uint16_t)(x) & JL1111_ANAR_ACKNOWLEDGE_MASK) >> JL1111_ANAR_ACKNOWLEDGE_SHIFT)
336 
337 /*
338  * REMOTE_FAULT (RO)
339  *
340  * 1: Advertise remote fault detection capability
341  * 0: Do not advertise remote fault detection capability
342  */
343 #define JL1111_ANAR_REMOTE_FAULT_MASK (0x2000U)
344 #define JL1111_ANAR_REMOTE_FAULT_SHIFT (13U)
345 #define JL1111_ANAR_REMOTE_FAULT_GET(x) (((uint16_t)(x) & JL1111_ANAR_REMOTE_FAULT_MASK) >> JL1111_ANAR_REMOTE_FAULT_SHIFT)
346 
347 /*
348  * ASYMMETRIC_PAUSE (RW)
349  *
350  * Asymmetric Pause Support For Full-Duplex Links
351  * 1: Advertise asymmetric pause ability
352  * 0: Do not advertise asymmetric pause ability
353  */
354 #define JL1111_ANAR_ASYMMETRIC_PAUSE_MASK (0x800U)
355 #define JL1111_ANAR_ASYMMETRIC_PAUSE_SHIFT (11U)
356 #define JL1111_ANAR_ASYMMETRIC_PAUSE_SET(x) (((uint16_t)(x) << JL1111_ANAR_ASYMMETRIC_PAUSE_SHIFT) & JL1111_ANAR_ASYMMETRIC_PAUSE_MASK)
357 #define JL1111_ANAR_ASYMMETRIC_PAUSE_GET(x) (((uint16_t)(x) & JL1111_ANAR_ASYMMETRIC_PAUSE_MASK) >> JL1111_ANAR_ASYMMETRIC_PAUSE_SHIFT)
358 
359 /*
360  * PAUSE (RW)
361  *
362  * Pause Support For Full-Duplex Links
363  * 1: Advertise pause ability
364  * 0: Do not advertise pause ability
365  */
366 #define JL1111_ANAR_PAUSE_MASK (0x400U)
367 #define JL1111_ANAR_PAUSE_SHIFT (10U)
368 #define JL1111_ANAR_PAUSE_SET(x) (((uint16_t)(x) << JL1111_ANAR_PAUSE_SHIFT) & JL1111_ANAR_PAUSE_MASK)
369 #define JL1111_ANAR_PAUSE_GET(x) (((uint16_t)(x) & JL1111_ANAR_PAUSE_MASK) >> JL1111_ANAR_PAUSE_SHIFT)
370 
371 /*
372  * 100BASE_T4 (RO)
373  *
374  * 1: 100Base-T4 is supported by local node
375  * 0: 100Base-T4 not supported by local node
376  */
377 #define JL1111_ANAR_100BASE_T4_MASK (0x200U)
378 #define JL1111_ANAR_100BASE_T4_SHIFT (9U)
379 #define JL1111_ANAR_100BASE_T4_GET(x) (((uint16_t)(x) & JL1111_ANAR_100BASE_T4_MASK) >> JL1111_ANAR_100BASE_T4_SHIFT)
380 
381 /*
382  * 100BASE_TX_FD (RW)
383  *
384  * 1: 100Base-TX full duplex is supported by local node
385  * 0: 100Base-TX full duplex not supported by local node
386  */
387 #define JL1111_ANAR_100BASE_TX_FD_MASK (0x100U)
388 #define JL1111_ANAR_100BASE_TX_FD_SHIFT (8U)
389 #define JL1111_ANAR_100BASE_TX_FD_SET(x) (((uint16_t)(x) << JL1111_ANAR_100BASE_TX_FD_SHIFT) & JL1111_ANAR_100BASE_TX_FD_MASK)
390 #define JL1111_ANAR_100BASE_TX_FD_GET(x) (((uint16_t)(x) & JL1111_ANAR_100BASE_TX_FD_MASK) >> JL1111_ANAR_100BASE_TX_FD_SHIFT)
391 
392 /*
393  * 100BASE_TX (RW)
394  *
395  * 1: 100Base-TX is supported by local node
396  * 0: 100Base-TX not supported by local node
397  */
398 #define JL1111_ANAR_100BASE_TX_MASK (0x80U)
399 #define JL1111_ANAR_100BASE_TX_SHIFT (7U)
400 #define JL1111_ANAR_100BASE_TX_SET(x) (((uint16_t)(x) << JL1111_ANAR_100BASE_TX_SHIFT) & JL1111_ANAR_100BASE_TX_MASK)
401 #define JL1111_ANAR_100BASE_TX_GET(x) (((uint16_t)(x) & JL1111_ANAR_100BASE_TX_MASK) >> JL1111_ANAR_100BASE_TX_SHIFT)
402 
403 /*
404  * 10BASE_T_FD (RW)
405  *
406  * 1: 10Base-T full duplex supported by local node
407  * 0: 10Base-T full duplex not supported by local node
408  */
409 #define JL1111_ANAR_10BASE_T_FD_MASK (0x40U)
410 #define JL1111_ANAR_10BASE_T_FD_SHIFT (6U)
411 #define JL1111_ANAR_10BASE_T_FD_SET(x) (((uint16_t)(x) << JL1111_ANAR_10BASE_T_FD_SHIFT) & JL1111_ANAR_10BASE_T_FD_MASK)
412 #define JL1111_ANAR_10BASE_T_FD_GET(x) (((uint16_t)(x) & JL1111_ANAR_10BASE_T_FD_MASK) >> JL1111_ANAR_10BASE_T_FD_SHIFT)
413 
414 /*
415  * 10BASE_T (RW)
416  *
417  * 1: 10Base-T is supported by local node
418  * 0: 10Base-T not supported by local node
419  */
420 #define JL1111_ANAR_10BASE_T_MASK (0x20U)
421 #define JL1111_ANAR_10BASE_T_SHIFT (5U)
422 #define JL1111_ANAR_10BASE_T_SET(x) (((uint16_t)(x) << JL1111_ANAR_10BASE_T_SHIFT) & JL1111_ANAR_10BASE_T_MASK)
423 #define JL1111_ANAR_10BASE_T_GET(x) (((uint16_t)(x) & JL1111_ANAR_10BASE_T_MASK) >> JL1111_ANAR_10BASE_T_SHIFT)
424 
425 /*
426  * SELECTOR_FIELD (RO)
427  *
428  * Binary Encoded Selector Supported by This Node. Currently only CSMA/CD 00001 is specified. No other protocols are supported.
429  */
430 #define JL1111_ANAR_SELECTOR_FIELD_MASK (0x1FU)
431 #define JL1111_ANAR_SELECTOR_FIELD_SHIFT (0U)
432 #define JL1111_ANAR_SELECTOR_FIELD_GET(x) (((uint16_t)(x) & JL1111_ANAR_SELECTOR_FIELD_MASK) >> JL1111_ANAR_SELECTOR_FIELD_SHIFT)
433 
434 /* Bitfield definition for register: ANLPAR */
435 /*
436  * NEXT_PAGE (RO)
437  *
438  * Next Page Bit.
439  * 0: Transmitting the primary capability data page
440  * 1: Transmitting the protocol specific data page
441  */
442 #define JL1111_ANLPAR_NEXT_PAGE_MASK (0x8000U)
443 #define JL1111_ANLPAR_NEXT_PAGE_SHIFT (15U)
444 #define JL1111_ANLPAR_NEXT_PAGE_GET(x) (((uint16_t)(x) & JL1111_ANLPAR_NEXT_PAGE_MASK) >> JL1111_ANLPAR_NEXT_PAGE_SHIFT)
445 
446 /*
447  * ACKNOWLEDGE (RO)
448  *
449  * 1: Link partner acknowledges reception of local node's capability data word
450  * 0: No acknowledgement
451  */
452 #define JL1111_ANLPAR_ACKNOWLEDGE_MASK (0x4000U)
453 #define JL1111_ANLPAR_ACKNOWLEDGE_SHIFT (14U)
454 #define JL1111_ANLPAR_ACKNOWLEDGE_GET(x) (((uint16_t)(x) & JL1111_ANLPAR_ACKNOWLEDGE_MASK) >> JL1111_ANLPAR_ACKNOWLEDGE_SHIFT)
455 
456 /*
457  * REMOTE_FAULT (RO)
458  *
459  * 1: Link partner is indicating a remote fault
460  * 0: Link partner is not indicating a remote fault
461  */
462 #define JL1111_ANLPAR_REMOTE_FAULT_MASK (0x2000U)
463 #define JL1111_ANLPAR_REMOTE_FAULT_SHIFT (13U)
464 #define JL1111_ANLPAR_REMOTE_FAULT_GET(x) (((uint16_t)(x) & JL1111_ANLPAR_REMOTE_FAULT_MASK) >> JL1111_ANLPAR_REMOTE_FAULT_SHIFT)
465 
466 /*
467  * ASYMMETRIC_PAUSE (RO)
468  *
469  * Asymmetric Pause Support For Full-Duplex Links
470  * 1: Advertise asymmetric pause ability
471  * 0: Do not advertise asymmetric puase ability
472  */
473 #define JL1111_ANLPAR_ASYMMETRIC_PAUSE_MASK (0x800U)
474 #define JL1111_ANLPAR_ASYMMETRIC_PAUSE_SHIFT (11U)
475 #define JL1111_ANLPAR_ASYMMETRIC_PAUSE_GET(x) (((uint16_t)(x) & JL1111_ANLPAR_ASYMMETRIC_PAUSE_MASK) >> JL1111_ANLPAR_ASYMMETRIC_PAUSE_SHIFT)
476 
477 /*
478  * PAUSE (RO)
479  *
480  * Pause Support For Full-Duplex Links
481  * 1: Advertise pause ability
482  * 0: Do not advertise pause ability
483  */
484 #define JL1111_ANLPAR_PAUSE_MASK (0x400U)
485 #define JL1111_ANLPAR_PAUSE_SHIFT (10U)
486 #define JL1111_ANLPAR_PAUSE_GET(x) (((uint16_t)(x) & JL1111_ANLPAR_PAUSE_MASK) >> JL1111_ANLPAR_PAUSE_SHIFT)
487 
488 /*
489  * 100BASE_T4 (RO)
490  *
491  * 1: 100Base-T4 is supported by link partner
492  * 0: 100Base-T4 not supported by link partner
493  */
494 #define JL1111_ANLPAR_100BASE_T4_MASK (0x200U)
495 #define JL1111_ANLPAR_100BASE_T4_SHIFT (9U)
496 #define JL1111_ANLPAR_100BASE_T4_GET(x) (((uint16_t)(x) & JL1111_ANLPAR_100BASE_T4_MASK) >> JL1111_ANLPAR_100BASE_T4_SHIFT)
497 
498 /*
499  * 100BASE_TX_FD (RO)
500  *
501  * 1: 100Base-TX full duplex is supported by link partner
502  * 0: 100Base-TX full duplex not supported by link partner
503  */
504 #define JL1111_ANLPAR_100BASE_TX_FD_MASK (0x100U)
505 #define JL1111_ANLPAR_100BASE_TX_FD_SHIFT (8U)
506 #define JL1111_ANLPAR_100BASE_TX_FD_GET(x) (((uint16_t)(x) & JL1111_ANLPAR_100BASE_TX_FD_MASK) >> JL1111_ANLPAR_100BASE_TX_FD_SHIFT)
507 
508 /*
509  * 100BASE_TX (RO)
510  *
511  * 1: 100Base-TX is supported by link partner
512  * 0: 100Base-TX not supported by link partner
513  */
514 #define JL1111_ANLPAR_100BASE_TX_MASK (0x80U)
515 #define JL1111_ANLPAR_100BASE_TX_SHIFT (7U)
516 #define JL1111_ANLPAR_100BASE_TX_GET(x) (((uint16_t)(x) & JL1111_ANLPAR_100BASE_TX_MASK) >> JL1111_ANLPAR_100BASE_TX_SHIFT)
517 
518 /*
519  * 10BASE_T_FD (RO)
520  *
521  * 1: 10Base-T full duplex is supported by link partner
522  * 0: 10Base-T full duplex not supported by link partner
523  */
524 #define JL1111_ANLPAR_10BASE_T_FD_MASK (0x40U)
525 #define JL1111_ANLPAR_10BASE_T_FD_SHIFT (6U)
526 #define JL1111_ANLPAR_10BASE_T_FD_GET(x) (((uint16_t)(x) & JL1111_ANLPAR_10BASE_T_FD_MASK) >> JL1111_ANLPAR_10BASE_T_FD_SHIFT)
527 
528 /*
529  * 10BASE_T (RO)
530  *
531  * 1: 10Base-T is supported by link partner
532  * 0: 10Base-T not supported by link partner
533  */
534 #define JL1111_ANLPAR_10BASE_T_MASK (0x20U)
535 #define JL1111_ANLPAR_10BASE_T_SHIFT (5U)
536 #define JL1111_ANLPAR_10BASE_T_GET(x) (((uint16_t)(x) & JL1111_ANLPAR_10BASE_T_MASK) >> JL1111_ANLPAR_10BASE_T_SHIFT)
537 
538 /*
539  * SELECTOR_FIELD (RO)
540  *
541  * Link Partner's Binary Encoded Node Selector.
542  * Currently only CSMA/CD 00001 is specified.
543  */
544 #define JL1111_ANLPAR_SELECTOR_FIELD_MASK (0x1FU)
545 #define JL1111_ANLPAR_SELECTOR_FIELD_SHIFT (0U)
546 #define JL1111_ANLPAR_SELECTOR_FIELD_GET(x) (((uint16_t)(x) & JL1111_ANLPAR_SELECTOR_FIELD_MASK) >> JL1111_ANLPAR_SELECTOR_FIELD_SHIFT)
547 
548 /* Bitfield definition for register: MMDAC */
549 /*
550  * MMD_FUNCTION (RW)
551  *
552  * 00: address
553  * 01: data, no post increment
554  * 10: data, post increment on reads and writes
555  * 11: data, post increment on writes only
556  */
557 #define JL1111_MMDAC_MMD_FUNCTION_MASK (0xC000U)
558 #define JL1111_MMDAC_MMD_FUNCTION_SHIFT (14U)
559 #define JL1111_MMDAC_MMD_FUNCTION_SET(x) (((uint16_t)(x) << JL1111_MMDAC_MMD_FUNCTION_SHIFT) & JL1111_MMDAC_MMD_FUNCTION_MASK)
560 #define JL1111_MMDAC_MMD_FUNCTION_GET(x) (((uint16_t)(x) & JL1111_MMDAC_MMD_FUNCTION_MASK) >> JL1111_MMDAC_MMD_FUNCTION_SHIFT)
561 
562 /*
563  * RESERVERD (RW)
564  *
565  * Write as 0, ignore on read
566  */
567 #define JL1111_MMDAC_RESERVERD_MASK (0x3FE0U)
568 #define JL1111_MMDAC_RESERVERD_SHIFT (5U)
569 #define JL1111_MMDAC_RESERVERD_SET(x) (((uint16_t)(x) << JL1111_MMDAC_RESERVERD_SHIFT) & JL1111_MMDAC_RESERVERD_MASK)
570 #define JL1111_MMDAC_RESERVERD_GET(x) (((uint16_t)(x) & JL1111_MMDAC_RESERVERD_MASK) >> JL1111_MMDAC_RESERVERD_SHIFT)
571 
572 /*
573  * MMD_DEVAD (RW)
574  *
575  * Device address
576  */
577 #define JL1111_MMDAC_MMD_DEVAD_MASK (0x1FU)
578 #define JL1111_MMDAC_MMD_DEVAD_SHIFT (0U)
579 #define JL1111_MMDAC_MMD_DEVAD_SET(x) (((uint16_t)(x) << JL1111_MMDAC_MMD_DEVAD_SHIFT) & JL1111_MMDAC_MMD_DEVAD_MASK)
580 #define JL1111_MMDAC_MMD_DEVAD_GET(x) (((uint16_t)(x) & JL1111_MMDAC_MMD_DEVAD_MASK) >> JL1111_MMDAC_MMD_DEVAD_SHIFT)
581 
582 /* Bitfield definition for register: MMDAAD */
583 /*
584  * MMD_ADDRESS_DATA (RW)
585  *
586  * If MMDAC[15:14]=00, MMD DEVAD's address register. Otherwise, MMD DEVAD's data register as indicated by the contents of its address register
587  */
588 #define JL1111_MMDAAD_MMD_ADDRESS_DATA_MASK (0xFFFFU)
589 #define JL1111_MMDAAD_MMD_ADDRESS_DATA_SHIFT (0U)
590 #define JL1111_MMDAAD_MMD_ADDRESS_DATA_SET(x) (((uint16_t)(x) << JL1111_MMDAAD_MMD_ADDRESS_DATA_SHIFT) & JL1111_MMDAAD_MMD_ADDRESS_DATA_MASK)
591 #define JL1111_MMDAAD_MMD_ADDRESS_DATA_GET(x) (((uint16_t)(x) & JL1111_MMDAAD_MMD_ADDRESS_DATA_MASK) >> JL1111_MMDAAD_MMD_ADDRESS_DATA_SHIFT)
592 
593 /* Bitfield definition for register: RMSR_P7 */
594 /*
595  * RMII_TX_LPI_ENABLE (RW)
596  *
597  * Enable transmition LPI signal of RMII
598  * TX_EN=0 and TXD=1 will represent MII LPI
599  */
600 #define JL1111_RMSR_P7_RMII_TX_LPI_ENABLE_MASK (0x8000U)
601 #define JL1111_RMSR_P7_RMII_TX_LPI_ENABLE_SHIFT (15U)
602 #define JL1111_RMSR_P7_RMII_TX_LPI_ENABLE_SET(x) (((uint16_t)(x) << JL1111_RMSR_P7_RMII_TX_LPI_ENABLE_SHIFT) & JL1111_RMSR_P7_RMII_TX_LPI_ENABLE_MASK)
603 #define JL1111_RMSR_P7_RMII_TX_LPI_ENABLE_GET(x) (((uint16_t)(x) & JL1111_RMSR_P7_RMII_TX_LPI_ENABLE_MASK) >> JL1111_RMSR_P7_RMII_TX_LPI_ENABLE_SHIFT)
604 
605 /*
606  * RMII_RX_LPI_ENABLE (RW)
607  *
608  * Enable reception LPI signal of RMII
609  * CRS_DV=0 and RXD=1 will represent MII LPI
610  */
611 #define JL1111_RMSR_P7_RMII_RX_LPI_ENABLE_MASK (0x4000U)
612 #define JL1111_RMSR_P7_RMII_RX_LPI_ENABLE_SHIFT (14U)
613 #define JL1111_RMSR_P7_RMII_RX_LPI_ENABLE_SET(x) (((uint16_t)(x) << JL1111_RMSR_P7_RMII_RX_LPI_ENABLE_SHIFT) & JL1111_RMSR_P7_RMII_RX_LPI_ENABLE_MASK)
614 #define JL1111_RMSR_P7_RMII_RX_LPI_ENABLE_GET(x) (((uint16_t)(x) & JL1111_RMSR_P7_RMII_RX_LPI_ENABLE_MASK) >> JL1111_RMSR_P7_RMII_RX_LPI_ENABLE_SHIFT)
615 
616 /*
617  * RMII_RX_ER_IN_RXD (RW)
618  *
619  * For Non-Bad-SSD rx_er, RXD will be 1
620  */
621 #define JL1111_RMSR_P7_RMII_RX_ER_IN_RXD_MASK (0x2000U)
622 #define JL1111_RMSR_P7_RMII_RX_ER_IN_RXD_SHIFT (13U)
623 #define JL1111_RMSR_P7_RMII_RX_ER_IN_RXD_SET(x) (((uint16_t)(x) << JL1111_RMSR_P7_RMII_RX_ER_IN_RXD_SHIFT) & JL1111_RMSR_P7_RMII_RX_ER_IN_RXD_MASK)
624 #define JL1111_RMSR_P7_RMII_RX_ER_IN_RXD_GET(x) (((uint16_t)(x) & JL1111_RMSR_P7_RMII_RX_ER_IN_RXD_MASK) >> JL1111_RMSR_P7_RMII_RX_ER_IN_RXD_SHIFT)
625 
626 /*
627  * RMII_CLOCK_DIRECTION (RW)
628  *
629  * Clock Direction of TX_CLK in RMII Mode.
630  * 0: 50MHz Output
631  * 1: 50MHz Input
632  */
633 #define JL1111_RMSR_P7_RMII_CLOCK_DIRECTION_MASK (0x1000U)
634 #define JL1111_RMSR_P7_RMII_CLOCK_DIRECTION_SHIFT (12U)
635 #define JL1111_RMSR_P7_RMII_CLOCK_DIRECTION_SET(x) (((uint16_t)(x) << JL1111_RMSR_P7_RMII_CLOCK_DIRECTION_SHIFT) & JL1111_RMSR_P7_RMII_CLOCK_DIRECTION_MASK)
636 #define JL1111_RMSR_P7_RMII_CLOCK_DIRECTION_GET(x) (((uint16_t)(x) & JL1111_RMSR_P7_RMII_CLOCK_DIRECTION_MASK) >> JL1111_RMSR_P7_RMII_CLOCK_DIRECTION_SHIFT)
637 
638 /*
639  * RMII_TX_SKEW (RW)
640  *
641  * Adjust RMII TX Interface Timing
642  */
643 #define JL1111_RMSR_P7_RMII_TX_SKEW_MASK (0xF00U)
644 #define JL1111_RMSR_P7_RMII_TX_SKEW_SHIFT (8U)
645 #define JL1111_RMSR_P7_RMII_TX_SKEW_SET(x) (((uint16_t)(x) << JL1111_RMSR_P7_RMII_TX_SKEW_SHIFT) & JL1111_RMSR_P7_RMII_TX_SKEW_MASK)
646 #define JL1111_RMSR_P7_RMII_TX_SKEW_GET(x) (((uint16_t)(x) & JL1111_RMSR_P7_RMII_TX_SKEW_MASK) >> JL1111_RMSR_P7_RMII_TX_SKEW_SHIFT)
647 
648 /*
649  * RMII_RX_SKEW (RW)
650  *
651  * Adjust RMII RX Interface Timing
652  */
653 #define JL1111_RMSR_P7_RMII_RX_SKEW_MASK (0xF0U)
654 #define JL1111_RMSR_P7_RMII_RX_SKEW_SHIFT (4U)
655 #define JL1111_RMSR_P7_RMII_RX_SKEW_SET(x) (((uint16_t)(x) << JL1111_RMSR_P7_RMII_RX_SKEW_SHIFT) & JL1111_RMSR_P7_RMII_RX_SKEW_MASK)
656 #define JL1111_RMSR_P7_RMII_RX_SKEW_GET(x) (((uint16_t)(x) & JL1111_RMSR_P7_RMII_RX_SKEW_MASK) >> JL1111_RMSR_P7_RMII_RX_SKEW_SHIFT)
657 
658 /*
659  * MII_RMII_MODE_SELECTION (RW)
660  *
661  * 0: RMII Mode
662  * 1: RMII Mode
663  */
664 #define JL1111_RMSR_P7_MII_RMII_MODE_SELECTION_MASK (0x8U)
665 #define JL1111_RMSR_P7_MII_RMII_MODE_SELECTION_SHIFT (3U)
666 #define JL1111_RMSR_P7_MII_RMII_MODE_SELECTION_SET(x) (((uint16_t)(x) << JL1111_RMSR_P7_MII_RMII_MODE_SELECTION_SHIFT) & JL1111_RMSR_P7_MII_RMII_MODE_SELECTION_MASK)
667 #define JL1111_RMSR_P7_MII_RMII_MODE_SELECTION_GET(x) (((uint16_t)(x) & JL1111_RMSR_P7_MII_RMII_MODE_SELECTION_MASK) >> JL1111_RMSR_P7_MII_RMII_MODE_SELECTION_SHIFT)
668 
669 /*
670  * RMII_CRS_DV_FUNCTIONAL (RW)
671  *
672  * 0: CRS_DV pin is CRS_DV signal
673  * 1: CRS_DV pin is RXDV signal
674  */
675 #define JL1111_RMSR_P7_RMII_CRS_DV_FUNCTIONAL_MASK (0x4U)
676 #define JL1111_RMSR_P7_RMII_CRS_DV_FUNCTIONAL_SHIFT (2U)
677 #define JL1111_RMSR_P7_RMII_CRS_DV_FUNCTIONAL_SET(x) (((uint16_t)(x) << JL1111_RMSR_P7_RMII_CRS_DV_FUNCTIONAL_SHIFT) & JL1111_RMSR_P7_RMII_CRS_DV_FUNCTIONAL_MASK)
678 #define JL1111_RMSR_P7_RMII_CRS_DV_FUNCTIONAL_GET(x) (((uint16_t)(x) & JL1111_RMSR_P7_RMII_CRS_DV_FUNCTIONAL_MASK) >> JL1111_RMSR_P7_RMII_CRS_DV_FUNCTIONAL_SHIFT)
679 
680 /*
681  * RMII_RXD_BAD_SSD_ENABLE (RW)
682  *
683  * 0: RMII data only
684  * 1: RMII data with SSD Error
685  */
686 #define JL1111_RMSR_P7_RMII_RXD_BAD_SSD_ENABLE_MASK (0x2U)
687 #define JL1111_RMSR_P7_RMII_RXD_BAD_SSD_ENABLE_SHIFT (1U)
688 #define JL1111_RMSR_P7_RMII_RXD_BAD_SSD_ENABLE_SET(x) (((uint16_t)(x) << JL1111_RMSR_P7_RMII_RXD_BAD_SSD_ENABLE_SHIFT) & JL1111_RMSR_P7_RMII_RXD_BAD_SSD_ENABLE_MASK)
689 #define JL1111_RMSR_P7_RMII_RXD_BAD_SSD_ENABLE_GET(x) (((uint16_t)(x) & JL1111_RMSR_P7_RMII_RXD_BAD_SSD_ENABLE_MASK) >> JL1111_RMSR_P7_RMII_RXD_BAD_SSD_ENABLE_SHIFT)
690 
691 /* Bitfield definition for register: INTSQI */
692 /*
693  * AUTONEG_ERROR (RC)
694  *
695  * Auto-Negotiation Error Interrupt
696  */
697 #define JL1111_INTSQI_AUTONEG_ERROR_MASK (0x8000U)
698 #define JL1111_INTSQI_AUTONEG_ERROR_SHIFT (15U)
699 #define JL1111_INTSQI_AUTONEG_ERROR_GET(x) (((uint16_t)(x) & JL1111_INTSQI_AUTONEG_ERROR_MASK) >> JL1111_INTSQI_AUTONEG_ERROR_SHIFT)
700 
701 /*
702  * LINK_STATUS_CHANGE (RC)
703  *
704  * Link_Status_Change_Interrupt
705  * 1: Enable
706  * 0: Disable
707  */
708 #define JL1111_INTSQI_LINK_STATUS_CHANGE_MASK (0x800U)
709 #define JL1111_INTSQI_LINK_STATUS_CHANGE_SHIFT (11U)
710 #define JL1111_INTSQI_LINK_STATUS_CHANGE_GET(x) (((uint16_t)(x) & JL1111_INTSQI_LINK_STATUS_CHANGE_MASK) >> JL1111_INTSQI_LINK_STATUS_CHANGE_SHIFT)
711 
712 /*
713  * SIGNAL_QUALITY_INDICATOR (RO)
714  *
715  * Signal Quality Indicator, lower is better. The value is only valid in 100Base-TX mode and its link status is ON
716  */
717 #define JL1111_INTSQI_SIGNAL_QUALITY_INDICATOR_MASK (0x1FU)
718 #define JL1111_INTSQI_SIGNAL_QUALITY_INDICATOR_SHIFT (0U)
719 #define JL1111_INTSQI_SIGNAL_QUALITY_INDICATOR_GET(x) (((uint16_t)(x) & JL1111_INTSQI_SIGNAL_QUALITY_INDICATOR_MASK) >> JL1111_INTSQI_SIGNAL_QUALITY_INDICATOR_SHIFT)
720 
721 /* Bitfield definition for register: PAGESEL */
722 /*
723  * PAGE_SELECTION (RW)
724  *
725  */
726 #define JL1111_PAGESEL_PAGE_SELECTION_MASK (0xFFU)
727 #define JL1111_PAGESEL_PAGE_SELECTION_SHIFT (0U)
728 #define JL1111_PAGESEL_PAGE_SELECTION_SET(x) (((uint16_t)(x) << JL1111_PAGESEL_PAGE_SELECTION_SHIFT) & JL1111_PAGESEL_PAGE_SELECTION_MASK)
729 #define JL1111_PAGESEL_PAGE_SELECTION_GET(x) (((uint16_t)(x) & JL1111_PAGESEL_PAGE_SELECTION_MASK) >> JL1111_PAGESEL_PAGE_SELECTION_SHIFT)
730 
731 
732 
733 
734 #endif /* HPM_JL1111_REGS_H */
JL1111_REG_Type
JL1111_REG_Type
Definition: hpm_jl1111_regs.h:12
JL1111_PHYID1
@ JL1111_PHYID1
Definition: hpm_jl1111_regs.h:15
JL1111_RMSR_P7
@ JL1111_RMSR_P7
Definition: hpm_jl1111_regs.h:21
JL1111_PHYID2
@ JL1111_PHYID2
Definition: hpm_jl1111_regs.h:16
JL1111_PAGESEL
@ JL1111_PAGESEL
Definition: hpm_jl1111_regs.h:23
JL1111_INTSQI
@ JL1111_INTSQI
Definition: hpm_jl1111_regs.h:22
JL1111_MMDAC
@ JL1111_MMDAC
Definition: hpm_jl1111_regs.h:19
JL1111_BMSR
@ JL1111_BMSR
Definition: hpm_jl1111_regs.h:14
JL1111_ANAR
@ JL1111_ANAR
Definition: hpm_jl1111_regs.h:17
JL1111_MMDAAD
@ JL1111_MMDAAD
Definition: hpm_jl1111_regs.h:20
JL1111_ANLPAR
@ JL1111_ANLPAR
Definition: hpm_jl1111_regs.h:18
JL1111_BMCR
@ JL1111_BMCR
Definition: hpm_jl1111_regs.h:13