HPM SDK
HPMicro Software Development Kit
hpm_soc_feature.h
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/*
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* Copyright (c) 2021-2025 HPMicro
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef HPM_SOC_FEATURE_H
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#define HPM_SOC_FEATURE_H
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#include "
hpm_soc.h
"
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#include "
hpm_soc_ip_feature.h
"
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/*
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* Cache section
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*/
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#define HPM_L1C_CACHE_SIZE (uint32_t)(32 * SIZE_1KB)
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#define HPM_L1C_ICACHE_SIZE (HPM_L1C_CACHE_SIZE)
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#define HPM_L1C_DCACHE_SIZE (HPM_L1C_CACHE_SIZE)
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#define HPM_L1C_CACHELINE_SIZE (64)
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#define HPM_L1C_CACHELINES_PER_WAY (128)
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#define HPM_L1C_CACHELINE_ALIGN_DOWN(n) ((uint32_t)(n) & ~(HPM_L1C_CACHELINE_SIZE - 1U))
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#define HPM_L1C_CACHELINE_ALIGN_UP(n) HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)(n) + HPM_L1C_CACHELINE_SIZE - 1U)
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/*
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* UART section
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*/
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#define UART_SOC_FIFO_SIZE (32U)
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/*
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* I2C Section
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*/
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#define I2C_SOC_FIFO_SIZE (4U)
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#define I2C_SOC_TRANSFER_COUNT_MAX (4096U)
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/*
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* PMIC Section
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*/
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#define PCFG_SOC_LDO1P1_MIN_VOLTAGE_IN_MV (700U)
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#define PCFG_SOC_LDO1P1_MAX_VOLTAGE_IN_MV (1320U)
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#define PCFG_SOC_LDO2P5_MIN_VOLTAGE_IN_MV (2125)
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#define PCFG_SOC_LDO2P5_MAX_VOLTAGE_IN_MV (2900U)
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#define PCFG_SOC_DCDC_MIN_VOLTAGE_IN_MV (600U)
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#define PCFG_SOC_DCDC_MAX_VOLTAGE_IN_MV (1375U)
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/*
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* I2S Section
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*/
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#define I2S_SOC_MAX_CHANNEL_NUM (16U)
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#define I2S_SOC_MAX_TX_CHANNEL_NUM (8U)
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#define I2S_SOC_MAX_TX_FIFO_DEPTH (8U)
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#define PDM_I2S HPM_I2S0
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#define DAO_I2S HPM_I2S1
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#define PDM_SOC_SAMPLE_RATE_IN_HZ (16000U)
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#define DAO_SOC_SAMPLE_RATE_IN_HZ (48000U)
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#define DAO_SOC_PDM_SAMPLE_RATE_RATIO (3U)
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/*
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* PLLCTL Section
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*/
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#define PLLCTL_SOC_PLL_MAX_COUNT (3U)
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/* PLL reference clock in hz */
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#define PLLCTL_SOC_PLL_REFCLK_FREQ (24U * 1000000UL)
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/* only PLL1 and PLL2 have DIV0, DIV1 */
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#define PLLCTL_SOC_PLL_HAS_DIV0(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0)
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#define PLLCTL_SOC_PLL_HAS_DIV1(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0)
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/*
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* PWM Section
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*/
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#define PWM_SOC_PWM_MAX_COUNT (8U)
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#define PWM_SOC_CMP_MAX_COUNT (24U)
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#define PWM_SOC_OUTPUT_TO_PWM_MAX_COUNT (8U)
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/*
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* DMA Section
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*/
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#define DMA_SOC_TRANSFER_WIDTH_MAX(x) (((x) == HPM_XDMA) ? DMA_TRANSFER_WIDTH_DOUBLE_WORD : DMA_TRANSFER_WIDTH_WORD)
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#define DMA_SOC_TRANSFER_PER_BURST_MAX(x) (((x) == HPM_XDMA) ? DMA_NUM_TRANSFER_PER_BURST_1024T : DMA_NUM_TRANSFER_PER_BURST_128T)
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#define DMA_SOC_CHANNEL_NUM (32U)
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#define DMA_SOC_MAX_COUNT (2U)
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#define DMA_SOC_CHN_TO_DMAMUX_CHN(x, n) (((x) == HPM_XDMA) ? (DMAMUX_MUXCFG_XDMA_MUX0 + n) : (DMAMUX_MUXCFG_HDMA_MUX0 + n))
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#define DMA_SOC_HAS_IDLE_FLAG (1U)
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/*
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* PDMA Section
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*/
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#define PDMA_SOC_PS_MAX_COUNT (0U)
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/*
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* LCDC Section
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*/
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#define LCDC_SOC_MAX_LAYER_COUNT (0U)
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#define LCDC_SOC_MAX_CSC_LAYER_COUNT (0U)
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#define LCDC_SOC_LAYER_SUPPORTS_CSC(x) ((x) < 2)
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#define LCDC_SOC_LAYER_SUPPORTS_YUV(x) ((x) < 2)
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/*
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* USB Section
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*/
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#define USB_SOC_MAX_COUNT (1U)
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#define USB_SOC_DCD_QTD_NEXT_INVALID (1U)
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#define USB_SOC_DCD_QHD_BUFFER_COUNT (5U)
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#define USB_SOC_DCD_MAX_ENDPOINT_COUNT (16U)
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#ifndef USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT
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#define USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT (8U)
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#endif
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#define USB_SOC_DCD_MAX_QTD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U * USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT)
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#define USB_SOS_DCD_MAX_QHD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U)
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#define USB_SOC_DCD_DATA_RAM_ADDRESS_ALIGNMENT (2048U)
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#define USB_SOC_HCD_FRAMELIST_MAX_ELEMENTS (1024U)
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/*
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* ENET Section
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*/
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#define ENET_SOC_DESC_ADDR_ALIGNMENT (32U)
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#define ENET_SOC_BUFF_ADDR_ALIGNMENT (8U)
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#define ENET_SOC_ADDR_MAX_COUNT (5U)
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#define ENET_SOC_ALT_EHD_DES_MIN_LEN (4U)
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#define ENET_SOC_ALT_EHD_DES_MAX_LEN (8U)
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#define ENET_SOC_ALT_EHD_DES_LEN (8U)
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#define ENET_SOC_PPS_MAX_COUNT (2L)
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#define ENET_SOC_DMA_BUS_WIDTH_IN_BYTES (8U)
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/*
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* ADC Section
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*/
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#define ADC_SOC_IP_VERSION (3U)
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#define ADC_SOC_SEQ_MAX_LEN (16U)
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#define ADC_SOC_SEQ_HCFG_EN (1U)
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#define ADC_SOC_MAX_TRIG_CH_LEN (4U)
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#define ADC_SOC_MAX_TRIG_CH_NUM (11U)
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#define ADC_SOC_DMA_ADDR_ALIGNMENT (4U)
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#define ADC_SOC_CONFIG_INTEN_CHAN_BIT_SIZE (8U)
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#define ADC_SOC_BUSMODE_ENABLE_CTRL_SUPPORT (1U)
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#define ADC_SOC_PREEMPT_ENABLE_CTRL_SUPPORT (1U)
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#define ADC_SOC_SEQ_MAX_DMA_BUFF_LEN_IN_4BYTES (16777216U)
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#define ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES (48U)
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#define ADC16_SOC_PARAMS_LEN (34U)
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#define ADC16_SOC_MAX_CH_NUM (15U)
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#define ADC16_SOC_MAX_SAMPLE_VALUE (65535U)
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#define ADC16_SOC_MAX_CONV_CLK_NUM (21U)
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/*
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* SYSCTL Section
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*/
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#define SYSCTL_SOC_CPU_GPR_COUNT (14U)
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#define SYSCTL_SOC_MONITOR_SLICE_COUNT (4U)
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/*
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* PTPC Section
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*/
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#define PTPC_SOC_TIMER_MAX_COUNT (2U)
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/*
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* SDP Section
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*/
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#define SDP_REGISTER_DESCRIPTOR_COUNT (1U)
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#define SDP_HAS_SM3_SUPPORT (1U)
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#define SDP_HAS_SM4_SUPPORT (1U)
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/*
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* SOC Privilege mode
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*/
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#define SOC_HAS_S_MODE (1U)
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/*
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* DAC Section
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*/
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#define DAC_SOC_BUFF_ALIGNED_SIZE (32U)
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#define DAC_SOC_MAX_DATA (4095U)
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#define DAC_SOC_MAX_BUFF_COUNT (65536U)
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#define DAC_SOC_MAX_OUTPUT_FREQ (1000000UL)
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/*
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* SPI Section
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*/
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#define SPI_SOC_TRANSFER_COUNT_MAX (0xFFFFFFFFU)
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#define SPI_SOC_FIFO_DEPTH (8U)
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/*
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* ROM API section
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*/
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#define ROMAPI_HAS_SW_SM3 (1)
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#define ROMAPI_HAS_SW_SM4 (1)
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/*
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* OTP Section
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*/
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#define OTP_SOC_MAC0_IDX (65U)
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#define OTP_SOC_MAC0_LEN (6U)
/* in bytes */
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#define OTP_SOC_UUID_IDX (88U)
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#define OTP_SOC_UUID_LEN (16U)
/* in bytes */
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#define PWM_SOC_HRPWM_SUPPORT (1U)
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#define PWM_SOC_SHADOW_TRIG_SUPPORT (0U)
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#define PWM_SOC_TIMER_RESET_SUPPORT (1U)
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/*
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* TRGM section
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*/
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#define TRGM_SOC_HAS_FILTER_SHIFT (1U)
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#define TRGM_SOC_HAS_DMAMUX_EN (1U)
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#define TRGM_SOC_HAS_ADC_MATRIX_SEL (1U)
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#define TRGM_SOC_HAS_DAC_MATRIX_SEL (1U)
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#define TRGM_SOC_HAS_POS_MATRIX_SEL (1U)
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#define TRGM_SOC_TRIM_IN_GROUP_MAX (6U)
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#define TRGM_SOC_TRIM_OUT_GROUP_MAX (6U)
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/*
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* MCAN Section
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*/
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#define MCAN_SOC_MAX_COUNT (4U)
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#define MCAN_SOC_MSG_BUF_IN_IP (0U)
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#define MCAN_SOC_MSG_BUF_IN_AHB_RAM (1U)
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#define CAN_SOC_MAX_COUNT MCAN_SOC_MAX_COUNT
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/*
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* EWDG Section
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*/
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#define EWDG_SOC_CLK_DIV_VAL_MAX (32U)
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#define EWDG_SOC_OVERTIME_REG_WIDTH (32U)
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#define EWDG_TIMEOUT_INTERRUPT_REQUIRE_EDGE_TRIGGER (0)
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/*
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* Sync Timer Section
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*/
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#define SYNT_SOC_HAS_TIMESTAMP (1U)
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#define SYNT_SOC_HAS_EXTENSION_CMP (1U)
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#define FFA_SOC_BUFFER_MAX (4096U)
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#define PLB_SOC_TYPEA_TRGM_INPUT0 (TRGM_TRGOCFG_PLB_IN_00)
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#define PLB_SOC_TYPEA_TRGM_OUTPUT0 (HPM_TRGM0_INPUT_SRC_PLB_OUT00)
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#define PLB_SOC_TYPEB_TRGM_INPUT0 (TRGM_TRGOCFG_PLB_IN_32)
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#define PLB_SOC_TYPEB_TRGM_OUTPUT0 (HPM_TRGM0_INPUT_SRC_PLB_OUT32)
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/*
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* GPIO
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*/
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#define GPIO_SOC_HAS_EDGE_BOTH_INTERRUPT (1U)
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#endif
/* HPM_SOC_FEATURE_H */
hpm_soc.h
hpm_soc_ip_feature.h
soc
HPM6P00
HPM6P81
hpm_soc_feature.h
Generated on Mon Jun 30 2025 23:27:26 for HPM SDK by
1.9.1
1.9.1