hpm_dmav2_drv.h

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/*
 * Copyright (c) 2021-2022 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
 */
 
 
#ifndef HPM_DMAV2_DRV_H
#define HPM_DMAV2_DRV_H
#include "hpm_common.h"
#include "hpm_soc_feature.h"
#include "hpm_dmav2_regs.h"
 
#define DMA_Type DMAV2_Type
 
#define DMA_CHANNEL_PRIORITY_LOW                (0U)
#define DMA_CHANNEL_PRIORITY_HIGH               (1U)
 
#define DMA_NUM_TRANSFER_PER_BURST_1T           (0U)
#define DMA_NUM_TRANSFER_PER_BURST_2T           (1U)
#define DMA_NUM_TRANSFER_PER_BURST_4T           (2U)
#define DMA_NUM_TRANSFER_PER_BURST_8T           (3U)
#define DMA_NUM_TRANSFER_PER_BURST_16T          (4U)
#define DMA_NUM_TRANSFER_PER_BURST_32T          (5U)
#define DMA_NUM_TRANSFER_PER_BURST_64T          (6U)
#define DMA_NUM_TRANSFER_PER_BURST_128T         (7U)
#define DMA_NUM_TRANSFER_PER_BURST_256T         (8U)
#define DMA_NUM_TRANSFER_PER_BURST_512T         (9U)
#define DMA_NUM_TRANSFER_PER_BURST_1024T        (10U)
 
#define DMA_TRANSFER_WIDTH_BYTE                 (0U)
#define DMA_TRANSFER_WIDTH_HALF_WORD            (1U)
#define DMA_TRANSFER_WIDTH_WORD                 (2U)
#define DMA_TRANSFER_WIDTH_DOUBLE_WORD          (3U)
 
#define DMA_ALIGN_HALF_WORD(x)                  (x & ~(1u))
#define DMA_ALIGN_WORD(x)                       (x & ~(3u))
#define DMA_ALIGN_DOUBLE_WORD(x)                (x & ~(7u))
 
#define DMA_CHANNEL_STATUS_ONGOING              (1U)
#define DMA_CHANNEL_STATUS_ERROR                (2U)
#define DMA_CHANNEL_STATUS_ABORT                (4U)
#define DMA_CHANNEL_STATUS_TC                   (8U)
#define DMA_CHANNEL_STATUS_HALF_TC              (16U)
 
#define DMA_CHANNEL_IRQ_STATUS_ERROR(x)         (uint32_t)(1 << x)
#define DMA_CHANNEL_IRQ_STATUS_ABORT(x)         (uint32_t)(1 << x)
#define DMA_CHANNEL_IRQ_STATUS_TC(x)            (uint32_t)(1 << x)
#define DMA_CHANNEL_IRQ_STATUS_HALF_TC(x)       (uint32_t)(1 << x)
 
#define DMA_HANDSHAKE_MODE_NORMAL               (0U)
#define DMA_HANDSHAKE_MODE_HANDSHAKE            (1U)
 
#define DMA_ADDRESS_CONTROL_INCREMENT           (0U)
#define DMA_ADDRESS_CONTROL_DECREMENT           (1U)
#define DMA_ADDRESS_CONTROL_FIXED               (2U)
 
#define DMA_SRC_BURST_OPT_STANDAND_SIZE         (0U)
#define DMA_SRC_BURST_OPT_CUSTOM_SIZE           (1U)
 
#define DMA_HANDSHAKE_OPT_ONE_BURST             (0U)
#define DMA_HANDSHAKE_OPT_ALL_TRANSIZE          (1U)
 
#define DMA_INTERRUPT_MASK_NONE                 (0U)
#define DMA_INTERRUPT_MASK_ERROR  DMAV2_CHCTRL_CTRL_INTERRMASK_MASK
#define DMA_INTERRUPT_MASK_ABORT  DMAV2_CHCTRL_CTRL_INTABTMASK_MASK
#define DMA_INTERRUPT_MASK_TERMINAL_COUNT DMAV2_CHCTRL_CTRL_INTTCMASK_MASK
#define DMA_INTERRUPT_MASK_HALF_TC DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_MASK
#define DMA_INTERRUPT_MASK_ALL \
    (uint8_t)(DMA_INTERRUPT_MASK_TERMINAL_COUNT \
            | DMA_INTERRUPT_MASK_ABORT \
            | DMA_INTERRUPT_MASK_ERROR \
            | DMA_INTERRUPT_MASK_HALF_TC)
 
#define DMA_SUPPORT_64BIT_ADDR (0)
 
 
enum {
    dmav2_state_idle = 0,
    dmav2_state_read,
    dmav2_state_read_ack,
    dmav2_state_write,
    dmav2_state_write_ack,
    dmav2_state_ll,
    dmav2_state_end,
    dmav2_state_end_wait,
};
 
typedef struct dma_linked_descriptor {
    uint32_t ctrl;              
    uint32_t trans_size;        
    uint32_t src_addr;          
    uint32_t req_ctrl;          
    uint32_t dst_addr;          
    uint32_t reserved0;         
    uint32_t linked_ptr;        
    uint32_t reserved1;         
} dma_linked_descriptor_t;
 
/* @brief Channel config */
typedef struct dma_channel_config {
    uint8_t priority;               
    uint8_t src_burst_size;         
    uint8_t src_mode;               
    uint8_t dst_mode;               
    uint8_t src_width;              
    uint8_t dst_width;              
    uint8_t src_addr_ctrl;          
    uint8_t dst_addr_ctrl;          
    uint16_t interrupt_mask;        
    uint32_t src_addr;              
    uint32_t dst_addr;              
    uint32_t linked_ptr;            
    uint32_t size_in_byte;          
    bool en_infiniteloop;           
    uint8_t handshake_opt;          
    uint8_t burst_opt;              
} dma_channel_config_t;
 
/* @brief Channel config */
typedef struct dma_handshake_config {
    uint32_t dst;
    uint32_t src;
    uint32_t size_in_byte;
    uint8_t data_width;            /* data width, value defined by DMA_TRANSFER_WIDTH_xxx */
    uint8_t ch_index;
    bool dst_fixed;
    bool src_fixed;
    bool en_infiniteloop;
    uint16_t interrupt_mask;
} dma_handshake_config_t;
 
 
/* @brief DMA specific status */
enum {
    status_dma_transfer_done = MAKE_STATUS(status_group_dma, 0),
    status_dma_transfer_error = MAKE_STATUS(status_group_dma, 1),
    status_dma_transfer_abort = MAKE_STATUS(status_group_dma, 2),
    status_dma_transfer_ongoing = MAKE_STATUS(status_group_dma, 3),
    status_dma_alignment_error = MAKE_STATUS(status_group_dma, 4),
    status_dma_transfer_half_done = MAKE_STATUS(status_group_dma, 5),
};
 
#ifdef __cplusplus
extern "C" {
#endif
 
static inline void dma_reset(DMAV2_Type *ptr)
{
    ptr->DMACTRL |= DMAV2_DMACTRL_RESET_MASK;
}
 
static inline hpm_stat_t dma_enable_channel(DMAV2_Type *ptr, uint32_t ch_index)
{
    ptr->CHCTRL[ch_index].CTRL |= DMAV2_CHCTRL_CTRL_ENABLE_MASK;
 
    if ((ptr->CHEN == 0) || !(ptr->CHEN & 1 << ch_index)) {
        return status_fail;
    }
    return status_success;
}
 
static inline void dma_disable_channel(DMAV2_Type *ptr, uint32_t ch_index)
{
    ptr->CHCTRL[ch_index].CTRL &= ~DMAV2_CHCTRL_CTRL_ENABLE_MASK;
}
 
static inline bool dma_channel_is_enable(DMAV2_Type *ptr, uint32_t ch_index)
{
    return (ptr->CHCTRL[ch_index].CTRL & DMAV2_CHCTRL_CTRL_ENABLE_MASK) ? true : false;
}
 
static inline void dma_set_priority(DMAV2_Type *ptr, uint32_t ch_index, uint8_t priority)
{
    ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_PRIORITY_MASK) | DMAV2_CHCTRL_CTRL_PRIORITY_SET(priority);
}
 
static inline void dma_set_source_work_mode(DMAV2_Type *ptr, uint32_t ch_index, uint8_t mode)
{
    ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_SRCMODE_MASK) | DMAV2_CHCTRL_CTRL_SRCMODE_SET(mode);
}
 
static inline void dma_set_destination_work_mode(DMAV2_Type *ptr, uint32_t ch_index, uint8_t mode)
{
    ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_DSTMODE_MASK) | DMAV2_CHCTRL_CTRL_DSTMODE_SET(mode);
}
 
static inline void dma_set_source_burst_size(DMAV2_Type *ptr, uint32_t ch_index, uint8_t burstsize)
{
    ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_MASK) | DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_SET(burstsize);
}
 
static inline uint32_t dma_get_remaining_transfer_size(DMAV2_Type *ptr, uint32_t ch_index)
{
    return ptr->CHCTRL[ch_index].TRANSIZE;
}
 
static inline void dma_set_transfer_size(DMAV2_Type *ptr, uint32_t ch_index, uint32_t size_in_width)
{
    ptr->CHCTRL[ch_index].TRANSIZE = DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SET(size_in_width);
}
 
static inline void dma_set_source_width(DMAV2_Type *ptr, uint32_t ch_index, uint8_t width)
{
    ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_SRCWIDTH_MASK) | DMAV2_CHCTRL_CTRL_SRCWIDTH_SET(width);
}
 
static inline void dma_set_destination_width(DMAV2_Type *ptr, uint32_t ch_index, uint8_t width)
{
    ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_DSTWIDTH_MASK) | DMAV2_CHCTRL_CTRL_DSTWIDTH_SET(width);
}
 
static inline void dma_set_transfer_src_width_byte_size(DMAV2_Type *ptr, uint32_t ch_index, uint8_t src_width, uint32_t size_in_byte)
{
    assert((src_width == DMA_TRANSFER_WIDTH_BYTE) || (src_width == DMA_TRANSFER_WIDTH_HALF_WORD)
        || (src_width == DMA_TRANSFER_WIDTH_WORD) || (src_width == DMA_TRANSFER_WIDTH_DOUBLE_WORD));
 
    ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_SRCWIDTH_MASK) | DMAV2_CHCTRL_CTRL_SRCWIDTH_SET(src_width);
    ptr->CHCTRL[ch_index].TRANSIZE = DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SET(size_in_byte >> src_width);
}
 
static inline void dma_set_source_address(DMAV2_Type *ptr, uint32_t ch_index, uint32_t addr)
{
    ptr->CHCTRL[ch_index].SRCADDR = addr;
}
 
static inline void dma_set_destination_address(DMAV2_Type *ptr, uint32_t ch_index, uint32_t addr)
{
    ptr->CHCTRL[ch_index].DSTADDR = addr;
}
 
static inline void dma_set_source_address_ctrl(DMAV2_Type *ptr, uint32_t ch_index, uint8_t addr_ctrl)
{
    ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_SRCADDRCTRL_MASK) | DMAV2_CHCTRL_CTRL_SRCADDRCTRL_SET(addr_ctrl);
}
 
static inline void dma_set_destination_address_ctrl(DMAV2_Type *ptr, uint32_t ch_index, uint8_t addr_ctrl)
{
    ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_DSTADDRCTRL_MASK) | DMAV2_CHCTRL_CTRL_DSTADDRCTRL_SET(addr_ctrl);
}
 
static inline void dma_set_infinite_loop_mode(DMAV2_Type *ptr, uint32_t ch_index, bool infinite_loop)
{
    ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_INFINITELOOP_MASK) | DMAV2_CHCTRL_CTRL_INFINITELOOP_SET(infinite_loop);
}
 
static inline void dma_set_src_busrt_option(DMAV2_Type *ptr, uint32_t ch_index, uint8_t burst_opt)
{
    ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_BURSTOPT_MASK) | DMAV2_CHCTRL_CTRL_BURSTOPT_SET(burst_opt);
}
 
static inline void dma_set_handshake_option(DMAV2_Type *ptr, uint32_t ch_index, uint8_t handshake_opt)
{
    ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_MASK) | DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_SET(handshake_opt);
}
 
static inline void dma_abort_channel(DMAV2_Type *ptr, uint32_t ch_index_mask)
{
    ptr->CHABORT |= DMAV2_CHABORT_CHABORT_SET(ch_index_mask);
}
 
static inline uint32_t dma_check_enabled_channel(DMAV2_Type *ptr,
                                                  uint32_t ch_index_mask)
{
    return (ch_index_mask & ptr->CHEN);
}
 
static inline bool dma_has_linked_pointer_configured(DMAV2_Type *ptr, uint32_t ch_index)
{
    return ptr->CHCTRL[ch_index].LLPOINTER != 0;
}
 
static inline uint32_t dma_check_transfer_status(DMAV2_Type *ptr, uint8_t ch_index)
{
    uint32_t dma_status = 0;
 
    if (ptr->INTTCSTS & (1 << ch_index)) {
        dma_status |= DMA_CHANNEL_STATUS_TC;
        ptr->INTTCSTS = (1 << ch_index); /* W1C clear status*/
    }
    if (ptr->INTHALFSTS & (1 << ch_index)) {
        dma_status |= DMA_CHANNEL_STATUS_HALF_TC;
        ptr->INTHALFSTS = (1 << ch_index); /* W1C clear status*/
    }
    if (ptr->INTERRSTS & (1 << ch_index)) {
        dma_status |= DMA_CHANNEL_STATUS_ERROR;
        ptr->INTERRSTS = (1 << ch_index); /* W1C clear status*/
    }
    if (ptr->INTABORTSTS & (1 << ch_index)) {
        dma_status |= DMA_CHANNEL_STATUS_ABORT;
        ptr->INTABORTSTS = (1 << ch_index); /* W1C clear status*/
    }
    if (dma_status == 0) {
        dma_status = DMA_CHANNEL_STATUS_ONGOING;
    }
    return dma_status;
}
 
static inline void dma_clear_transfer_status(DMAV2_Type *ptr, uint8_t ch_index)
{
    /* W1C */
    ptr->INTHALFSTS  = (1 << ch_index);
    ptr->INTTCSTS    = (1 << ch_index);
    ptr->INTABORTSTS = (1 << ch_index);
    ptr->INTERRSTS   = (1 << ch_index);
}
 
static inline void dma_enable_channel_interrupt(DMAV2_Type *ptr, uint8_t ch_index, int32_t interrupt_mask)
{
    ptr->CHCTRL[ch_index].CTRL &= ~(interrupt_mask & DMA_INTERRUPT_MASK_ALL);
}
 
static inline void dma_disable_channel_interrupt(DMAV2_Type *ptr, uint8_t ch_index, int32_t interrupt_mask)
{
    ptr->CHCTRL[ch_index].CTRL |= (interrupt_mask & DMA_INTERRUPT_MASK_ALL);
}
 
 
static inline uint32_t dma_check_channel_interrupt_mask(DMAV2_Type *ptr, uint8_t ch_index)
{
    return ptr->CHCTRL[ch_index].CTRL & DMA_INTERRUPT_MASK_ALL;
}
 
void dma_default_channel_config(DMAV2_Type *ptr, dma_channel_config_t *ch);
 
hpm_stat_t dma_setup_channel(DMAV2_Type *ptr, uint8_t ch_num,
                            dma_channel_config_t *ch, bool start_transfer);
 
hpm_stat_t dma_config_linked_descriptor(DMAV2_Type *ptr, dma_linked_descriptor_t *descriptor, uint8_t ch_num, dma_channel_config_t *config);
 
hpm_stat_t dma_start_memcpy(DMAV2_Type *ptr, uint8_t ch_num,
                               uint32_t dst, uint32_t src,
                               uint32_t size_in_byte, uint32_t burst_len_in_byte);
 
void dma_default_handshake_config(DMAV2_Type *ptr, dma_handshake_config_t *config);
 
hpm_stat_t dma_setup_handshake(DMAV2_Type *ptr,  dma_handshake_config_t *pconfig, bool start_transfer);
 
static inline bool dma_is_idle(DMAV2_Type *ptr)
{
    return (DMAV2_IDMISC_DMASTATE_GET(ptr->IDMISC) == dmav2_state_idle) ? true : false;
}
 
 
#ifdef __cplusplus
}
#endif
#endif /* HPM_DMAV2_DRV_H */