HPM SDK
HPMicro Software Development Kit
hpm_qeiv2_regs.h
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1 /*
2  * Copyright (c) 2021-2023 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_QEIV2_H
10 #define HPM_QEIV2_H
11 
12 typedef struct {
13  __RW uint32_t CR; /* 0x0: Control register */
14  __RW uint32_t PHCFG; /* 0x4: Phase configure register */
15  __RW uint32_t WDGCFG; /* 0x8: Watchdog configure register */
16  __RW uint32_t PHIDX; /* 0xC: Phase index register */
17  __RW uint32_t TRGOEN; /* 0x10: Tigger output enable register */
18  __RW uint32_t READEN; /* 0x14: Read event enable register */
19  __RW uint32_t ZCMP; /* 0x18: Z comparator */
20  __RW uint32_t PHCMP; /* 0x1C: Phase comparator */
21  __RW uint32_t SPDCMP; /* 0x20: Speed comparator */
22  __RW uint32_t DMAEN; /* 0x24: DMA request enable register */
23  __RW uint32_t SR; /* 0x28: Status register */
24  __RW uint32_t IRQEN; /* 0x2C: Interrupt request register */
25  struct {
26  __RW uint32_t Z; /* 0x30: Z counter */
27  __R uint32_t PH; /* 0x34: Phase counter */
28  __RW uint32_t SPD; /* 0x38: Speed counter */
29  __R uint32_t TMR; /* 0x3C: Timer counter */
30  } COUNT[4];
31  __R uint8_t RESERVED0[16]; /* 0x70 - 0x7F: Reserved */
32  __RW uint32_t ZCMP2; /* 0x80: Z comparator */
33  __RW uint32_t PHCMP2; /* 0x84: Phase comparator */
34  __RW uint32_t SPDCMP2; /* 0x88: Speed comparator */
35  __RW uint32_t MATCH_CFG; /* 0x8C: */
36  __RW uint32_t FILT_CFG[6]; /* 0x90 - 0xA4: A signal filter config */
37  __R uint8_t RESERVED1[88]; /* 0xA8 - 0xFF: Reserved */
38  __RW uint32_t QEI_CFG; /* 0x100: qei config register */
39  __R uint8_t RESERVED2[12]; /* 0x104 - 0x10F: Reserved */
40  __RW uint32_t PULSE0_NUM; /* 0x110: pulse0_num */
41  __RW uint32_t PULSE1_NUM; /* 0x114: pulse1_num */
42  __R uint32_t CYCLE0_CNT; /* 0x118: cycle0_cnt */
43  __R uint32_t CYCLE0PULSE_CNT; /* 0x11C: cycle0pulse_cnt */
44  __R uint32_t CYCLE1_CNT; /* 0x120: cycle1_cnt */
45  __R uint32_t CYCLE1PULSE_CNT; /* 0x124: cycle1pulse_cnt */
46  __R uint32_t CYCLE0_SNAP0; /* 0x128: cycle0_snap0 */
47  __R uint32_t CYCLE0_SNAP1; /* 0x12C: cycle0_snap1 */
48  __R uint32_t CYCLE1_SNAP0; /* 0x130: cycle1_snap0 */
49  __R uint32_t CYCLE1_SNAP1; /* 0x134: cycle1_snap1 */
50  __R uint8_t RESERVED3[8]; /* 0x138 - 0x13F: Reserved */
51  __RW uint32_t CYCLE0_NUM; /* 0x140: cycle0_num */
52  __RW uint32_t CYCLE1_NUM; /* 0x144: cycle1_num */
53  __R uint32_t PULSE0_CNT; /* 0x148: pulse0_cnt */
54  __R uint32_t PULSE0CYCLE_CNT; /* 0x14C: pulse0cycle_cnt */
55  __R uint32_t PULSE1_CNT; /* 0x150: pulse1_cnt */
56  __R uint32_t PULSE1CYCLE_CNT; /* 0x154: pulse1cycle_cnt */
57  __R uint32_t PULSE0_SNAP0; /* 0x158: pulse0_snap0 */
58  __R uint32_t PULSE0CYCLE_SNAP0; /* 0x15C: pulse0cycle_snap0 */
59  __R uint32_t PULSE0_SNAP1; /* 0x160: pulse0_snap1 */
60  __R uint32_t PULSE0CYCLE_SNAP1; /* 0x164: pulse0cycle_snap1 */
61  __R uint32_t PULSE1_SNAP0; /* 0x168: pulse1_snap0 */
62  __R uint32_t PULSE1CYCLE_SNAP0; /* 0x16C: pulse1cycle_snap0 */
63  __R uint32_t PULSE1_SNAP1; /* 0x170: pulse1_snap1 */
64  __R uint32_t PULSE1CYCLE_SNAP1; /* 0x174: pulse1cycle_snap1 */
65  __R uint8_t RESERVED4[136]; /* 0x178 - 0x1FF: Reserved */
66  __RW uint32_t ADCX_CFG0; /* 0x200: adcx_cfg0 */
67  __RW uint32_t ADCX_CFG1; /* 0x204: adcx_cfg1 */
68  __RW uint32_t ADCX_CFG2; /* 0x208: adcx_cfg2 */
69  __R uint8_t RESERVED5[4]; /* 0x20C - 0x20F: Reserved */
70  __RW uint32_t ADCY_CFG0; /* 0x210: adcy_cfg0 */
71  __RW uint32_t ADCY_CFG1; /* 0x214: adcy_cfg1 */
72  __RW uint32_t ADCY_CFG2; /* 0x218: adcy_cfg2 */
73  __R uint8_t RESERVED6[4]; /* 0x21C - 0x21F: Reserved */
74  __RW uint32_t CAL_CFG; /* 0x220: cal_cfg */
75  __R uint8_t RESERVED7[12]; /* 0x224 - 0x22F: Reserved */
76  __RW uint32_t PHASE_PARAM; /* 0x230: phase_param */
77  __RW uint32_t ANGLE_ADJ; /* 0x234: angle_adj */
78  __RW uint32_t POS_THRESHOLD; /* 0x238: pos_threshold */
79  __R uint8_t RESERVED8[4]; /* 0x23C - 0x23F: Reserved */
80  __RW uint32_t UVW_POS[6]; /* 0x240 - 0x254: uvw_pos0 */
81  __RW uint32_t UVW_POS_CFG[6]; /* 0x258 - 0x26C: */
82  __R uint8_t RESERVED9[16]; /* 0x270 - 0x27F: Reserved */
83  __RW uint32_t PHASE_CNT; /* 0x280: phase_cnt */
84  __W uint32_t PHASE_UPDATE; /* 0x284: phase_update */
85  __RW uint32_t POSITION; /* 0x288: position */
86  __W uint32_t POSITION_UPDATE; /* 0x28C: position_update */
87  __R uint32_t ANGLE; /* 0x290: */
88  __RW uint32_t POS_TIMEOUT; /* 0x294: pos_timeout */
89 } QEIV2_Type;
90 
91 
92 /* Bitfield definition for register: CR */
93 /*
94  * READ (WO)
95  *
96  * 1- load phcnt, zcnt, spdcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0
97  */
98 #define QEIV2_CR_READ_MASK (0x80000000UL)
99 #define QEIV2_CR_READ_SHIFT (31U)
100 #define QEIV2_CR_READ_SET(x) (((uint32_t)(x) << QEIV2_CR_READ_SHIFT) & QEIV2_CR_READ_MASK)
101 #define QEIV2_CR_READ_GET(x) (((uint32_t)(x) & QEIV2_CR_READ_MASK) >> QEIV2_CR_READ_SHIFT)
102 
103 /*
104  * ZCNTCFG (RW)
105  *
106  * 1- zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0
107  * 0- zcnt will increment or decrement when Z input assert
108  */
109 #define QEIV2_CR_ZCNTCFG_MASK (0x400000UL)
110 #define QEIV2_CR_ZCNTCFG_SHIFT (22U)
111 #define QEIV2_CR_ZCNTCFG_SET(x) (((uint32_t)(x) << QEIV2_CR_ZCNTCFG_SHIFT) & QEIV2_CR_ZCNTCFG_MASK)
112 #define QEIV2_CR_ZCNTCFG_GET(x) (((uint32_t)(x) & QEIV2_CR_ZCNTCFG_MASK) >> QEIV2_CR_ZCNTCFG_SHIFT)
113 
114 /*
115  * PHCALIZ (RW)
116  *
117  * 1- phcnt will set to phidx when Z input assert(for abz digital signsl)
118  */
119 #define QEIV2_CR_PHCALIZ_MASK (0x200000UL)
120 #define QEIV2_CR_PHCALIZ_SHIFT (21U)
121 #define QEIV2_CR_PHCALIZ_SET(x) (((uint32_t)(x) << QEIV2_CR_PHCALIZ_SHIFT) & QEIV2_CR_PHCALIZ_MASK)
122 #define QEIV2_CR_PHCALIZ_GET(x) (((uint32_t)(x) & QEIV2_CR_PHCALIZ_MASK) >> QEIV2_CR_PHCALIZ_SHIFT)
123 
124 /*
125  * Z_ONLY_EN (RW)
126  *
127  * 1- phcnt will set to phidx when Z input assert(for xy analog signal and digital z, also need set phcaliz)
128  */
129 #define QEIV2_CR_Z_ONLY_EN_MASK (0x100000UL)
130 #define QEIV2_CR_Z_ONLY_EN_SHIFT (20U)
131 #define QEIV2_CR_Z_ONLY_EN_SET(x) (((uint32_t)(x) << QEIV2_CR_Z_ONLY_EN_SHIFT) & QEIV2_CR_Z_ONLY_EN_MASK)
132 #define QEIV2_CR_Z_ONLY_EN_GET(x) (((uint32_t)(x) & QEIV2_CR_Z_ONLY_EN_MASK) >> QEIV2_CR_Z_ONLY_EN_SHIFT)
133 
134 /*
135  * H2FDIR0 (RW)
136  *
137  */
138 #define QEIV2_CR_H2FDIR0_MASK (0x80000UL)
139 #define QEIV2_CR_H2FDIR0_SHIFT (19U)
140 #define QEIV2_CR_H2FDIR0_SET(x) (((uint32_t)(x) << QEIV2_CR_H2FDIR0_SHIFT) & QEIV2_CR_H2FDIR0_MASK)
141 #define QEIV2_CR_H2FDIR0_GET(x) (((uint32_t)(x) & QEIV2_CR_H2FDIR0_MASK) >> QEIV2_CR_H2FDIR0_SHIFT)
142 
143 /*
144  * H2FDIR1 (RW)
145  *
146  */
147 #define QEIV2_CR_H2FDIR1_MASK (0x40000UL)
148 #define QEIV2_CR_H2FDIR1_SHIFT (18U)
149 #define QEIV2_CR_H2FDIR1_SET(x) (((uint32_t)(x) << QEIV2_CR_H2FDIR1_SHIFT) & QEIV2_CR_H2FDIR1_MASK)
150 #define QEIV2_CR_H2FDIR1_GET(x) (((uint32_t)(x) & QEIV2_CR_H2FDIR1_MASK) >> QEIV2_CR_H2FDIR1_SHIFT)
151 
152 /*
153  * H2RDIR0 (RW)
154  *
155  */
156 #define QEIV2_CR_H2RDIR0_MASK (0x20000UL)
157 #define QEIV2_CR_H2RDIR0_SHIFT (17U)
158 #define QEIV2_CR_H2RDIR0_SET(x) (((uint32_t)(x) << QEIV2_CR_H2RDIR0_SHIFT) & QEIV2_CR_H2RDIR0_MASK)
159 #define QEIV2_CR_H2RDIR0_GET(x) (((uint32_t)(x) & QEIV2_CR_H2RDIR0_MASK) >> QEIV2_CR_H2RDIR0_SHIFT)
160 
161 /*
162  * H2RDIR1 (RW)
163  *
164  */
165 #define QEIV2_CR_H2RDIR1_MASK (0x10000UL)
166 #define QEIV2_CR_H2RDIR1_SHIFT (16U)
167 #define QEIV2_CR_H2RDIR1_SET(x) (((uint32_t)(x) << QEIV2_CR_H2RDIR1_SHIFT) & QEIV2_CR_H2RDIR1_MASK)
168 #define QEIV2_CR_H2RDIR1_GET(x) (((uint32_t)(x) & QEIV2_CR_H2RDIR1_MASK) >> QEIV2_CR_H2RDIR1_SHIFT)
169 
170 /*
171  * PAUSEPOS (RW)
172  *
173  * 1- pause position output valid when PAUSE assert
174  */
175 #define QEIV2_CR_PAUSEPOS_MASK (0x8000U)
176 #define QEIV2_CR_PAUSEPOS_SHIFT (15U)
177 #define QEIV2_CR_PAUSEPOS_SET(x) (((uint32_t)(x) << QEIV2_CR_PAUSEPOS_SHIFT) & QEIV2_CR_PAUSEPOS_MASK)
178 #define QEIV2_CR_PAUSEPOS_GET(x) (((uint32_t)(x) & QEIV2_CR_PAUSEPOS_MASK) >> QEIV2_CR_PAUSEPOS_SHIFT)
179 
180 /*
181  * PAUSESPD (RW)
182  *
183  * 1- pause spdcnt when PAUSE assert
184  */
185 #define QEIV2_CR_PAUSESPD_MASK (0x4000U)
186 #define QEIV2_CR_PAUSESPD_SHIFT (14U)
187 #define QEIV2_CR_PAUSESPD_SET(x) (((uint32_t)(x) << QEIV2_CR_PAUSESPD_SHIFT) & QEIV2_CR_PAUSESPD_MASK)
188 #define QEIV2_CR_PAUSESPD_GET(x) (((uint32_t)(x) & QEIV2_CR_PAUSESPD_MASK) >> QEIV2_CR_PAUSESPD_SHIFT)
189 
190 /*
191  * PAUSEPH (RW)
192  *
193  * 1- pause phcnt when PAUSE assert
194  */
195 #define QEIV2_CR_PAUSEPH_MASK (0x2000U)
196 #define QEIV2_CR_PAUSEPH_SHIFT (13U)
197 #define QEIV2_CR_PAUSEPH_SET(x) (((uint32_t)(x) << QEIV2_CR_PAUSEPH_SHIFT) & QEIV2_CR_PAUSEPH_MASK)
198 #define QEIV2_CR_PAUSEPH_GET(x) (((uint32_t)(x) & QEIV2_CR_PAUSEPH_MASK) >> QEIV2_CR_PAUSEPH_SHIFT)
199 
200 /*
201  * PAUSEZ (RW)
202  *
203  * 1- pause zcnt when PAUSE assert
204  */
205 #define QEIV2_CR_PAUSEZ_MASK (0x1000U)
206 #define QEIV2_CR_PAUSEZ_SHIFT (12U)
207 #define QEIV2_CR_PAUSEZ_SET(x) (((uint32_t)(x) << QEIV2_CR_PAUSEZ_SHIFT) & QEIV2_CR_PAUSEZ_MASK)
208 #define QEIV2_CR_PAUSEZ_GET(x) (((uint32_t)(x) & QEIV2_CR_PAUSEZ_MASK) >> QEIV2_CR_PAUSEZ_SHIFT)
209 
210 /*
211  * HFDIR0 (RW)
212  *
213  * 1- HOMEF will set at H rising edge when dir == 1 (negative rotation direction)
214  */
215 #define QEIV2_CR_HFDIR0_MASK (0x800U)
216 #define QEIV2_CR_HFDIR0_SHIFT (11U)
217 #define QEIV2_CR_HFDIR0_SET(x) (((uint32_t)(x) << QEIV2_CR_HFDIR0_SHIFT) & QEIV2_CR_HFDIR0_MASK)
218 #define QEIV2_CR_HFDIR0_GET(x) (((uint32_t)(x) & QEIV2_CR_HFDIR0_MASK) >> QEIV2_CR_HFDIR0_SHIFT)
219 
220 /*
221  * HFDIR1 (RW)
222  *
223  * 1- HOMEF will set at H rising edge when dir == 0 (positive rotation direction)
224  */
225 #define QEIV2_CR_HFDIR1_MASK (0x400U)
226 #define QEIV2_CR_HFDIR1_SHIFT (10U)
227 #define QEIV2_CR_HFDIR1_SET(x) (((uint32_t)(x) << QEIV2_CR_HFDIR1_SHIFT) & QEIV2_CR_HFDIR1_MASK)
228 #define QEIV2_CR_HFDIR1_GET(x) (((uint32_t)(x) & QEIV2_CR_HFDIR1_MASK) >> QEIV2_CR_HFDIR1_SHIFT)
229 
230 /*
231  * HRDIR0 (RW)
232  *
233  * 1- HOMEF will set at H falling edge when dir == 1 (negative rotation direction)
234  */
235 #define QEIV2_CR_HRDIR0_MASK (0x200U)
236 #define QEIV2_CR_HRDIR0_SHIFT (9U)
237 #define QEIV2_CR_HRDIR0_SET(x) (((uint32_t)(x) << QEIV2_CR_HRDIR0_SHIFT) & QEIV2_CR_HRDIR0_MASK)
238 #define QEIV2_CR_HRDIR0_GET(x) (((uint32_t)(x) & QEIV2_CR_HRDIR0_MASK) >> QEIV2_CR_HRDIR0_SHIFT)
239 
240 /*
241  * HRDIR1 (RW)
242  *
243  * 1- HOMEF will set at H falling edge when dir == 1 (positive rotation direction)
244  */
245 #define QEIV2_CR_HRDIR1_MASK (0x100U)
246 #define QEIV2_CR_HRDIR1_SHIFT (8U)
247 #define QEIV2_CR_HRDIR1_SET(x) (((uint32_t)(x) << QEIV2_CR_HRDIR1_SHIFT) & QEIV2_CR_HRDIR1_MASK)
248 #define QEIV2_CR_HRDIR1_GET(x) (((uint32_t)(x) & QEIV2_CR_HRDIR1_MASK) >> QEIV2_CR_HRDIR1_SHIFT)
249 
250 /*
251  * FAULTPOS (RW)
252  *
253  */
254 #define QEIV2_CR_FAULTPOS_MASK (0x40U)
255 #define QEIV2_CR_FAULTPOS_SHIFT (6U)
256 #define QEIV2_CR_FAULTPOS_SET(x) (((uint32_t)(x) << QEIV2_CR_FAULTPOS_SHIFT) & QEIV2_CR_FAULTPOS_MASK)
257 #define QEIV2_CR_FAULTPOS_GET(x) (((uint32_t)(x) & QEIV2_CR_FAULTPOS_MASK) >> QEIV2_CR_FAULTPOS_SHIFT)
258 
259 /*
260  * SNAPEN (RW)
261  *
262  * 1- load phcnt, zcnt, spdcnt and tmrcnt into their snap registers when snapi input assert
263  */
264 #define QEIV2_CR_SNAPEN_MASK (0x20U)
265 #define QEIV2_CR_SNAPEN_SHIFT (5U)
266 #define QEIV2_CR_SNAPEN_SET(x) (((uint32_t)(x) << QEIV2_CR_SNAPEN_SHIFT) & QEIV2_CR_SNAPEN_MASK)
267 #define QEIV2_CR_SNAPEN_GET(x) (((uint32_t)(x) & QEIV2_CR_SNAPEN_MASK) >> QEIV2_CR_SNAPEN_SHIFT)
268 
269 /*
270  * RSTCNT (RW)
271  *
272  * 1- reset zcnt, spdcnt and tmrcnt to 0. reset phcnt to phidx
273  */
274 #define QEIV2_CR_RSTCNT_MASK (0x10U)
275 #define QEIV2_CR_RSTCNT_SHIFT (4U)
276 #define QEIV2_CR_RSTCNT_SET(x) (((uint32_t)(x) << QEIV2_CR_RSTCNT_SHIFT) & QEIV2_CR_RSTCNT_MASK)
277 #define QEIV2_CR_RSTCNT_GET(x) (((uint32_t)(x) & QEIV2_CR_RSTCNT_MASK) >> QEIV2_CR_RSTCNT_SHIFT)
278 
279 /*
280  * RD_SEL (RW)
281  *
282  * define the width/counter value(affect width_match, width_match2, width_cur, timer_cur, width_read, timer_read, width_snap0,width_snap1, timer_snap0, timer_snap1)
283  * 0 : same as hpm1000/500/500s;
284  * 1: use width for position; use timer for angle
285  */
286 #define QEIV2_CR_RD_SEL_MASK (0x8U)
287 #define QEIV2_CR_RD_SEL_SHIFT (3U)
288 #define QEIV2_CR_RD_SEL_SET(x) (((uint32_t)(x) << QEIV2_CR_RD_SEL_SHIFT) & QEIV2_CR_RD_SEL_MASK)
289 #define QEIV2_CR_RD_SEL_GET(x) (((uint32_t)(x) & QEIV2_CR_RD_SEL_MASK) >> QEIV2_CR_RD_SEL_SHIFT)
290 
291 /*
292  * ENCTYP (RW)
293  *
294  * 000-abz; 001-pd; 010-ud; 011-UVW(hal)
295  * 100-single A; 101-single sin; 110: sin&cos
296  */
297 #define QEIV2_CR_ENCTYP_MASK (0x7U)
298 #define QEIV2_CR_ENCTYP_SHIFT (0U)
299 #define QEIV2_CR_ENCTYP_SET(x) (((uint32_t)(x) << QEIV2_CR_ENCTYP_SHIFT) & QEIV2_CR_ENCTYP_MASK)
300 #define QEIV2_CR_ENCTYP_GET(x) (((uint32_t)(x) & QEIV2_CR_ENCTYP_MASK) >> QEIV2_CR_ENCTYP_SHIFT)
301 
302 /* Bitfield definition for register: PHCFG */
303 /*
304  * PHMAX (RW)
305  *
306  * maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax
307  */
308 #define QEIV2_PHCFG_PHMAX_MASK (0xFFFFFFFFUL)
309 #define QEIV2_PHCFG_PHMAX_SHIFT (0U)
310 #define QEIV2_PHCFG_PHMAX_SET(x) (((uint32_t)(x) << QEIV2_PHCFG_PHMAX_SHIFT) & QEIV2_PHCFG_PHMAX_MASK)
311 #define QEIV2_PHCFG_PHMAX_GET(x) (((uint32_t)(x) & QEIV2_PHCFG_PHMAX_MASK) >> QEIV2_PHCFG_PHMAX_SHIFT)
312 
313 /* Bitfield definition for register: WDGCFG */
314 /*
315  * WDGEN (RW)
316  *
317  * 1- enable wdog counter
318  */
319 #define QEIV2_WDGCFG_WDGEN_MASK (0x80000000UL)
320 #define QEIV2_WDGCFG_WDGEN_SHIFT (31U)
321 #define QEIV2_WDGCFG_WDGEN_SET(x) (((uint32_t)(x) << QEIV2_WDGCFG_WDGEN_SHIFT) & QEIV2_WDGCFG_WDGEN_MASK)
322 #define QEIV2_WDGCFG_WDGEN_GET(x) (((uint32_t)(x) & QEIV2_WDGCFG_WDGEN_MASK) >> QEIV2_WDGCFG_WDGEN_SHIFT)
323 
324 /*
325  * WDOG_CFG (RW)
326  *
327  * define as stop if phase_cnt change is less than it
328  * if 0, then each change of phase_cnt will clear wdog counter;
329  * if 2, then phase_cnt change larger than 2 will clear wdog counter
330  */
331 #define QEIV2_WDGCFG_WDOG_CFG_MASK (0x70000000UL)
332 #define QEIV2_WDGCFG_WDOG_CFG_SHIFT (28U)
333 #define QEIV2_WDGCFG_WDOG_CFG_SET(x) (((uint32_t)(x) << QEIV2_WDGCFG_WDOG_CFG_SHIFT) & QEIV2_WDGCFG_WDOG_CFG_MASK)
334 #define QEIV2_WDGCFG_WDOG_CFG_GET(x) (((uint32_t)(x) & QEIV2_WDGCFG_WDOG_CFG_MASK) >> QEIV2_WDGCFG_WDOG_CFG_SHIFT)
335 
336 /*
337  * WDGTO (RW)
338  *
339  * watch dog timeout value
340  */
341 #define QEIV2_WDGCFG_WDGTO_MASK (0xFFFFFFFUL)
342 #define QEIV2_WDGCFG_WDGTO_SHIFT (0U)
343 #define QEIV2_WDGCFG_WDGTO_SET(x) (((uint32_t)(x) << QEIV2_WDGCFG_WDGTO_SHIFT) & QEIV2_WDGCFG_WDGTO_MASK)
344 #define QEIV2_WDGCFG_WDGTO_GET(x) (((uint32_t)(x) & QEIV2_WDGCFG_WDGTO_MASK) >> QEIV2_WDGCFG_WDGTO_SHIFT)
345 
346 /* Bitfield definition for register: PHIDX */
347 /*
348  * PHIDX (RW)
349  *
350  * phcnt reset value, phcnt will reset to phidx when phcaliz set to 1
351  */
352 #define QEIV2_PHIDX_PHIDX_MASK (0xFFFFFFFFUL)
353 #define QEIV2_PHIDX_PHIDX_SHIFT (0U)
354 #define QEIV2_PHIDX_PHIDX_SET(x) (((uint32_t)(x) << QEIV2_PHIDX_PHIDX_SHIFT) & QEIV2_PHIDX_PHIDX_MASK)
355 #define QEIV2_PHIDX_PHIDX_GET(x) (((uint32_t)(x) & QEIV2_PHIDX_PHIDX_MASK) >> QEIV2_PHIDX_PHIDX_SHIFT)
356 
357 /* Bitfield definition for register: TRGOEN */
358 /*
359  * WDGFEN (RW)
360  *
361  * 1- enable trigger output when wdg flag set
362  */
363 #define QEIV2_TRGOEN_WDGFEN_MASK (0x80000000UL)
364 #define QEIV2_TRGOEN_WDGFEN_SHIFT (31U)
365 #define QEIV2_TRGOEN_WDGFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_WDGFEN_SHIFT) & QEIV2_TRGOEN_WDGFEN_MASK)
366 #define QEIV2_TRGOEN_WDGFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_WDGFEN_MASK) >> QEIV2_TRGOEN_WDGFEN_SHIFT)
367 
368 /*
369  * HOMEFEN (RW)
370  *
371  * 1- enable trigger output when homef flag set
372  */
373 #define QEIV2_TRGOEN_HOMEFEN_MASK (0x40000000UL)
374 #define QEIV2_TRGOEN_HOMEFEN_SHIFT (30U)
375 #define QEIV2_TRGOEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_HOMEFEN_SHIFT) & QEIV2_TRGOEN_HOMEFEN_MASK)
376 #define QEIV2_TRGOEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_HOMEFEN_MASK) >> QEIV2_TRGOEN_HOMEFEN_SHIFT)
377 
378 /*
379  * POSCMPFEN (RW)
380  *
381  * 1- enable trigger output when poscmpf flag set
382  */
383 #define QEIV2_TRGOEN_POSCMPFEN_MASK (0x20000000UL)
384 #define QEIV2_TRGOEN_POSCMPFEN_SHIFT (29U)
385 #define QEIV2_TRGOEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_POSCMPFEN_SHIFT) & QEIV2_TRGOEN_POSCMPFEN_MASK)
386 #define QEIV2_TRGOEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_POSCMPFEN_MASK) >> QEIV2_TRGOEN_POSCMPFEN_SHIFT)
387 
388 /*
389  * ZPHFEN (RW)
390  *
391  * 1- enable trigger output when zphf flag set
392  */
393 #define QEIV2_TRGOEN_ZPHFEN_MASK (0x10000000UL)
394 #define QEIV2_TRGOEN_ZPHFEN_SHIFT (28U)
395 #define QEIV2_TRGOEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_ZPHFEN_SHIFT) & QEIV2_TRGOEN_ZPHFEN_MASK)
396 #define QEIV2_TRGOEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_ZPHFEN_MASK) >> QEIV2_TRGOEN_ZPHFEN_SHIFT)
397 
398 /*
399  * ZMISSFEN (RW)
400  *
401  */
402 #define QEIV2_TRGOEN_ZMISSFEN_MASK (0x8000000UL)
403 #define QEIV2_TRGOEN_ZMISSFEN_SHIFT (27U)
404 #define QEIV2_TRGOEN_ZMISSFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_ZMISSFEN_SHIFT) & QEIV2_TRGOEN_ZMISSFEN_MASK)
405 #define QEIV2_TRGOEN_ZMISSFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_ZMISSFEN_MASK) >> QEIV2_TRGOEN_ZMISSFEN_SHIFT)
406 
407 /*
408  * WIDTHTMFEN (RW)
409  *
410  */
411 #define QEIV2_TRGOEN_WIDTHTMFEN_MASK (0x4000000UL)
412 #define QEIV2_TRGOEN_WIDTHTMFEN_SHIFT (26U)
413 #define QEIV2_TRGOEN_WIDTHTMFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_WIDTHTMFEN_SHIFT) & QEIV2_TRGOEN_WIDTHTMFEN_MASK)
414 #define QEIV2_TRGOEN_WIDTHTMFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_WIDTHTMFEN_MASK) >> QEIV2_TRGOEN_WIDTHTMFEN_SHIFT)
415 
416 /*
417  * POS2CMPFEN (RW)
418  *
419  */
420 #define QEIV2_TRGOEN_POS2CMPFEN_MASK (0x2000000UL)
421 #define QEIV2_TRGOEN_POS2CMPFEN_SHIFT (25U)
422 #define QEIV2_TRGOEN_POS2CMPFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_POS2CMPFEN_SHIFT) & QEIV2_TRGOEN_POS2CMPFEN_MASK)
423 #define QEIV2_TRGOEN_POS2CMPFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_POS2CMPFEN_MASK) >> QEIV2_TRGOEN_POS2CMPFEN_SHIFT)
424 
425 /*
426  * DIRCHGFEN (RW)
427  *
428  */
429 #define QEIV2_TRGOEN_DIRCHGFEN_MASK (0x1000000UL)
430 #define QEIV2_TRGOEN_DIRCHGFEN_SHIFT (24U)
431 #define QEIV2_TRGOEN_DIRCHGFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_DIRCHGFEN_SHIFT) & QEIV2_TRGOEN_DIRCHGFEN_MASK)
432 #define QEIV2_TRGOEN_DIRCHGFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_DIRCHGFEN_MASK) >> QEIV2_TRGOEN_DIRCHGFEN_SHIFT)
433 
434 /*
435  * CYCLE0FEN (RW)
436  *
437  */
438 #define QEIV2_TRGOEN_CYCLE0FEN_MASK (0x800000UL)
439 #define QEIV2_TRGOEN_CYCLE0FEN_SHIFT (23U)
440 #define QEIV2_TRGOEN_CYCLE0FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_CYCLE0FEN_SHIFT) & QEIV2_TRGOEN_CYCLE0FEN_MASK)
441 #define QEIV2_TRGOEN_CYCLE0FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_CYCLE0FEN_MASK) >> QEIV2_TRGOEN_CYCLE0FEN_SHIFT)
442 
443 /*
444  * CYCLE1FEN (RW)
445  *
446  */
447 #define QEIV2_TRGOEN_CYCLE1FEN_MASK (0x400000UL)
448 #define QEIV2_TRGOEN_CYCLE1FEN_SHIFT (22U)
449 #define QEIV2_TRGOEN_CYCLE1FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_CYCLE1FEN_SHIFT) & QEIV2_TRGOEN_CYCLE1FEN_MASK)
450 #define QEIV2_TRGOEN_CYCLE1FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_CYCLE1FEN_MASK) >> QEIV2_TRGOEN_CYCLE1FEN_SHIFT)
451 
452 /*
453  * PULSE0FEN (RW)
454  *
455  */
456 #define QEIV2_TRGOEN_PULSE0FEN_MASK (0x200000UL)
457 #define QEIV2_TRGOEN_PULSE0FEN_SHIFT (21U)
458 #define QEIV2_TRGOEN_PULSE0FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_PULSE0FEN_SHIFT) & QEIV2_TRGOEN_PULSE0FEN_MASK)
459 #define QEIV2_TRGOEN_PULSE0FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_PULSE0FEN_MASK) >> QEIV2_TRGOEN_PULSE0FEN_SHIFT)
460 
461 /*
462  * PULSE1FEN (RW)
463  *
464  */
465 #define QEIV2_TRGOEN_PULSE1FEN_MASK (0x100000UL)
466 #define QEIV2_TRGOEN_PULSE1FEN_SHIFT (20U)
467 #define QEIV2_TRGOEN_PULSE1FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_PULSE1FEN_SHIFT) & QEIV2_TRGOEN_PULSE1FEN_MASK)
468 #define QEIV2_TRGOEN_PULSE1FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_PULSE1FEN_MASK) >> QEIV2_TRGOEN_PULSE1FEN_SHIFT)
469 
470 /*
471  * HOME2FEN (RW)
472  *
473  */
474 #define QEIV2_TRGOEN_HOME2FEN_MASK (0x80000UL)
475 #define QEIV2_TRGOEN_HOME2FEN_SHIFT (19U)
476 #define QEIV2_TRGOEN_HOME2FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_HOME2FEN_SHIFT) & QEIV2_TRGOEN_HOME2FEN_MASK)
477 #define QEIV2_TRGOEN_HOME2FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_HOME2FEN_MASK) >> QEIV2_TRGOEN_HOME2FEN_SHIFT)
478 
479 /*
480  * FAULTFEN (RW)
481  *
482  */
483 #define QEIV2_TRGOEN_FAULTFEN_MASK (0x40000UL)
484 #define QEIV2_TRGOEN_FAULTFEN_SHIFT (18U)
485 #define QEIV2_TRGOEN_FAULTFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_FAULTFEN_SHIFT) & QEIV2_TRGOEN_FAULTFEN_MASK)
486 #define QEIV2_TRGOEN_FAULTFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_FAULTFEN_MASK) >> QEIV2_TRGOEN_FAULTFEN_SHIFT)
487 
488 /* Bitfield definition for register: READEN */
489 /*
490  * WDGFEN (RW)
491  *
492  * 1- load counters to their read registers when wdg flag set
493  */
494 #define QEIV2_READEN_WDGFEN_MASK (0x80000000UL)
495 #define QEIV2_READEN_WDGFEN_SHIFT (31U)
496 #define QEIV2_READEN_WDGFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_WDGFEN_SHIFT) & QEIV2_READEN_WDGFEN_MASK)
497 #define QEIV2_READEN_WDGFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_WDGFEN_MASK) >> QEIV2_READEN_WDGFEN_SHIFT)
498 
499 /*
500  * HOMEFEN (RW)
501  *
502  * 1- load counters to their read registers when homef flag set
503  */
504 #define QEIV2_READEN_HOMEFEN_MASK (0x40000000UL)
505 #define QEIV2_READEN_HOMEFEN_SHIFT (30U)
506 #define QEIV2_READEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_HOMEFEN_SHIFT) & QEIV2_READEN_HOMEFEN_MASK)
507 #define QEIV2_READEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_HOMEFEN_MASK) >> QEIV2_READEN_HOMEFEN_SHIFT)
508 
509 /*
510  * POSCMPFEN (RW)
511  *
512  * 1- load counters to their read registers when poscmpf flag set
513  */
514 #define QEIV2_READEN_POSCMPFEN_MASK (0x20000000UL)
515 #define QEIV2_READEN_POSCMPFEN_SHIFT (29U)
516 #define QEIV2_READEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_POSCMPFEN_SHIFT) & QEIV2_READEN_POSCMPFEN_MASK)
517 #define QEIV2_READEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_POSCMPFEN_MASK) >> QEIV2_READEN_POSCMPFEN_SHIFT)
518 
519 /*
520  * ZPHFEN (RW)
521  *
522  * 1- load counters to their read registers when zphf flag set
523  */
524 #define QEIV2_READEN_ZPHFEN_MASK (0x10000000UL)
525 #define QEIV2_READEN_ZPHFEN_SHIFT (28U)
526 #define QEIV2_READEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_ZPHFEN_SHIFT) & QEIV2_READEN_ZPHFEN_MASK)
527 #define QEIV2_READEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_ZPHFEN_MASK) >> QEIV2_READEN_ZPHFEN_SHIFT)
528 
529 /*
530  * ZMISSFEN (RW)
531  *
532  */
533 #define QEIV2_READEN_ZMISSFEN_MASK (0x8000000UL)
534 #define QEIV2_READEN_ZMISSFEN_SHIFT (27U)
535 #define QEIV2_READEN_ZMISSFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_ZMISSFEN_SHIFT) & QEIV2_READEN_ZMISSFEN_MASK)
536 #define QEIV2_READEN_ZMISSFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_ZMISSFEN_MASK) >> QEIV2_READEN_ZMISSFEN_SHIFT)
537 
538 /*
539  * WIDTHTMFEN (RW)
540  *
541  */
542 #define QEIV2_READEN_WIDTHTMFEN_MASK (0x4000000UL)
543 #define QEIV2_READEN_WIDTHTMFEN_SHIFT (26U)
544 #define QEIV2_READEN_WIDTHTMFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_WIDTHTMFEN_SHIFT) & QEIV2_READEN_WIDTHTMFEN_MASK)
545 #define QEIV2_READEN_WIDTHTMFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_WIDTHTMFEN_MASK) >> QEIV2_READEN_WIDTHTMFEN_SHIFT)
546 
547 /*
548  * POS2CMPFEN (RW)
549  *
550  */
551 #define QEIV2_READEN_POS2CMPFEN_MASK (0x2000000UL)
552 #define QEIV2_READEN_POS2CMPFEN_SHIFT (25U)
553 #define QEIV2_READEN_POS2CMPFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_POS2CMPFEN_SHIFT) & QEIV2_READEN_POS2CMPFEN_MASK)
554 #define QEIV2_READEN_POS2CMPFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_POS2CMPFEN_MASK) >> QEIV2_READEN_POS2CMPFEN_SHIFT)
555 
556 /*
557  * DIRCHGFEN (RW)
558  *
559  */
560 #define QEIV2_READEN_DIRCHGFEN_MASK (0x1000000UL)
561 #define QEIV2_READEN_DIRCHGFEN_SHIFT (24U)
562 #define QEIV2_READEN_DIRCHGFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_DIRCHGFEN_SHIFT) & QEIV2_READEN_DIRCHGFEN_MASK)
563 #define QEIV2_READEN_DIRCHGFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_DIRCHGFEN_MASK) >> QEIV2_READEN_DIRCHGFEN_SHIFT)
564 
565 /*
566  * CYCLE0FEN (RW)
567  *
568  */
569 #define QEIV2_READEN_CYCLE0FEN_MASK (0x800000UL)
570 #define QEIV2_READEN_CYCLE0FEN_SHIFT (23U)
571 #define QEIV2_READEN_CYCLE0FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_CYCLE0FEN_SHIFT) & QEIV2_READEN_CYCLE0FEN_MASK)
572 #define QEIV2_READEN_CYCLE0FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_CYCLE0FEN_MASK) >> QEIV2_READEN_CYCLE0FEN_SHIFT)
573 
574 /*
575  * CYCLE1FEN (RW)
576  *
577  */
578 #define QEIV2_READEN_CYCLE1FEN_MASK (0x400000UL)
579 #define QEIV2_READEN_CYCLE1FEN_SHIFT (22U)
580 #define QEIV2_READEN_CYCLE1FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_CYCLE1FEN_SHIFT) & QEIV2_READEN_CYCLE1FEN_MASK)
581 #define QEIV2_READEN_CYCLE1FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_CYCLE1FEN_MASK) >> QEIV2_READEN_CYCLE1FEN_SHIFT)
582 
583 /*
584  * PULSE0FEN (RW)
585  *
586  */
587 #define QEIV2_READEN_PULSE0FEN_MASK (0x200000UL)
588 #define QEIV2_READEN_PULSE0FEN_SHIFT (21U)
589 #define QEIV2_READEN_PULSE0FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_PULSE0FEN_SHIFT) & QEIV2_READEN_PULSE0FEN_MASK)
590 #define QEIV2_READEN_PULSE0FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_PULSE0FEN_MASK) >> QEIV2_READEN_PULSE0FEN_SHIFT)
591 
592 /*
593  * PULSE1FEN (RW)
594  *
595  */
596 #define QEIV2_READEN_PULSE1FEN_MASK (0x100000UL)
597 #define QEIV2_READEN_PULSE1FEN_SHIFT (20U)
598 #define QEIV2_READEN_PULSE1FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_PULSE1FEN_SHIFT) & QEIV2_READEN_PULSE1FEN_MASK)
599 #define QEIV2_READEN_PULSE1FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_PULSE1FEN_MASK) >> QEIV2_READEN_PULSE1FEN_SHIFT)
600 
601 /*
602  * HOME2FEN (RW)
603  *
604  */
605 #define QEIV2_READEN_HOME2FEN_MASK (0x80000UL)
606 #define QEIV2_READEN_HOME2FEN_SHIFT (19U)
607 #define QEIV2_READEN_HOME2FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_HOME2FEN_SHIFT) & QEIV2_READEN_HOME2FEN_MASK)
608 #define QEIV2_READEN_HOME2FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_HOME2FEN_MASK) >> QEIV2_READEN_HOME2FEN_SHIFT)
609 
610 /*
611  * FAULTFEN (RW)
612  *
613  */
614 #define QEIV2_READEN_FAULTFEN_MASK (0x40000UL)
615 #define QEIV2_READEN_FAULTFEN_SHIFT (18U)
616 #define QEIV2_READEN_FAULTFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_FAULTFEN_SHIFT) & QEIV2_READEN_FAULTFEN_MASK)
617 #define QEIV2_READEN_FAULTFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_FAULTFEN_MASK) >> QEIV2_READEN_FAULTFEN_SHIFT)
618 
619 /* Bitfield definition for register: ZCMP */
620 /*
621  * ZCMP (RW)
622  *
623  * zcnt postion compare value
624  */
625 #define QEIV2_ZCMP_ZCMP_MASK (0xFFFFFFFFUL)
626 #define QEIV2_ZCMP_ZCMP_SHIFT (0U)
627 #define QEIV2_ZCMP_ZCMP_SET(x) (((uint32_t)(x) << QEIV2_ZCMP_ZCMP_SHIFT) & QEIV2_ZCMP_ZCMP_MASK)
628 #define QEIV2_ZCMP_ZCMP_GET(x) (((uint32_t)(x) & QEIV2_ZCMP_ZCMP_MASK) >> QEIV2_ZCMP_ZCMP_SHIFT)
629 
630 /* Bitfield definition for register: PHCMP */
631 /*
632  * PHCMP (RW)
633  *
634  * phcnt position compare value
635  */
636 #define QEIV2_PHCMP_PHCMP_MASK (0xFFFFFFFFUL)
637 #define QEIV2_PHCMP_PHCMP_SHIFT (0U)
638 #define QEIV2_PHCMP_PHCMP_SET(x) (((uint32_t)(x) << QEIV2_PHCMP_PHCMP_SHIFT) & QEIV2_PHCMP_PHCMP_MASK)
639 #define QEIV2_PHCMP_PHCMP_GET(x) (((uint32_t)(x) & QEIV2_PHCMP_PHCMP_MASK) >> QEIV2_PHCMP_PHCMP_SHIFT)
640 
641 /* Bitfield definition for register: SPDCMP */
642 /*
643  * SPDCMP (RW)
644  *
645  * spdcnt position compare value
646  */
647 #define QEIV2_SPDCMP_SPDCMP_MASK (0xFFFFFFFFUL)
648 #define QEIV2_SPDCMP_SPDCMP_SHIFT (0U)
649 #define QEIV2_SPDCMP_SPDCMP_SET(x) (((uint32_t)(x) << QEIV2_SPDCMP_SPDCMP_SHIFT) & QEIV2_SPDCMP_SPDCMP_MASK)
650 #define QEIV2_SPDCMP_SPDCMP_GET(x) (((uint32_t)(x) & QEIV2_SPDCMP_SPDCMP_MASK) >> QEIV2_SPDCMP_SPDCMP_SHIFT)
651 
652 /* Bitfield definition for register: DMAEN */
653 /*
654  * WDGFEN (RW)
655  *
656  * 1- generate dma request when wdg flag set
657  */
658 #define QEIV2_DMAEN_WDGFEN_MASK (0x80000000UL)
659 #define QEIV2_DMAEN_WDGFEN_SHIFT (31U)
660 #define QEIV2_DMAEN_WDGFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_WDGFEN_SHIFT) & QEIV2_DMAEN_WDGFEN_MASK)
661 #define QEIV2_DMAEN_WDGFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_WDGFEN_MASK) >> QEIV2_DMAEN_WDGFEN_SHIFT)
662 
663 /*
664  * HOMEFEN (RW)
665  *
666  * 1- generate dma request when homef flag set
667  */
668 #define QEIV2_DMAEN_HOMEFEN_MASK (0x40000000UL)
669 #define QEIV2_DMAEN_HOMEFEN_SHIFT (30U)
670 #define QEIV2_DMAEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_HOMEFEN_SHIFT) & QEIV2_DMAEN_HOMEFEN_MASK)
671 #define QEIV2_DMAEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_HOMEFEN_MASK) >> QEIV2_DMAEN_HOMEFEN_SHIFT)
672 
673 /*
674  * POSCMPFEN (RW)
675  *
676  * 1- generate dma request when poscmpf flag set
677  */
678 #define QEIV2_DMAEN_POSCMPFEN_MASK (0x20000000UL)
679 #define QEIV2_DMAEN_POSCMPFEN_SHIFT (29U)
680 #define QEIV2_DMAEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_POSCMPFEN_SHIFT) & QEIV2_DMAEN_POSCMPFEN_MASK)
681 #define QEIV2_DMAEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_POSCMPFEN_MASK) >> QEIV2_DMAEN_POSCMPFEN_SHIFT)
682 
683 /*
684  * ZPHFEN (RW)
685  *
686  * 1- generate dma request when zphf flag set
687  */
688 #define QEIV2_DMAEN_ZPHFEN_MASK (0x10000000UL)
689 #define QEIV2_DMAEN_ZPHFEN_SHIFT (28U)
690 #define QEIV2_DMAEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_ZPHFEN_SHIFT) & QEIV2_DMAEN_ZPHFEN_MASK)
691 #define QEIV2_DMAEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_ZPHFEN_MASK) >> QEIV2_DMAEN_ZPHFEN_SHIFT)
692 
693 /*
694  * ZMISSFEN (RW)
695  *
696  */
697 #define QEIV2_DMAEN_ZMISSFEN_MASK (0x8000000UL)
698 #define QEIV2_DMAEN_ZMISSFEN_SHIFT (27U)
699 #define QEIV2_DMAEN_ZMISSFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_ZMISSFEN_SHIFT) & QEIV2_DMAEN_ZMISSFEN_MASK)
700 #define QEIV2_DMAEN_ZMISSFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_ZMISSFEN_MASK) >> QEIV2_DMAEN_ZMISSFEN_SHIFT)
701 
702 /*
703  * WIDTHTMFEN (RW)
704  *
705  */
706 #define QEIV2_DMAEN_WIDTHTMFEN_MASK (0x4000000UL)
707 #define QEIV2_DMAEN_WIDTHTMFEN_SHIFT (26U)
708 #define QEIV2_DMAEN_WIDTHTMFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_WIDTHTMFEN_SHIFT) & QEIV2_DMAEN_WIDTHTMFEN_MASK)
709 #define QEIV2_DMAEN_WIDTHTMFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_WIDTHTMFEN_MASK) >> QEIV2_DMAEN_WIDTHTMFEN_SHIFT)
710 
711 /*
712  * POS2CMPFEN (RW)
713  *
714  */
715 #define QEIV2_DMAEN_POS2CMPFEN_MASK (0x2000000UL)
716 #define QEIV2_DMAEN_POS2CMPFEN_SHIFT (25U)
717 #define QEIV2_DMAEN_POS2CMPFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_POS2CMPFEN_SHIFT) & QEIV2_DMAEN_POS2CMPFEN_MASK)
718 #define QEIV2_DMAEN_POS2CMPFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_POS2CMPFEN_MASK) >> QEIV2_DMAEN_POS2CMPFEN_SHIFT)
719 
720 /*
721  * DIRCHGFEN (RW)
722  *
723  */
724 #define QEIV2_DMAEN_DIRCHGFEN_MASK (0x1000000UL)
725 #define QEIV2_DMAEN_DIRCHGFEN_SHIFT (24U)
726 #define QEIV2_DMAEN_DIRCHGFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_DIRCHGFEN_SHIFT) & QEIV2_DMAEN_DIRCHGFEN_MASK)
727 #define QEIV2_DMAEN_DIRCHGFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_DIRCHGFEN_MASK) >> QEIV2_DMAEN_DIRCHGFEN_SHIFT)
728 
729 /*
730  * CYCLE0FEN (RW)
731  *
732  */
733 #define QEIV2_DMAEN_CYCLE0FEN_MASK (0x800000UL)
734 #define QEIV2_DMAEN_CYCLE0FEN_SHIFT (23U)
735 #define QEIV2_DMAEN_CYCLE0FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_CYCLE0FEN_SHIFT) & QEIV2_DMAEN_CYCLE0FEN_MASK)
736 #define QEIV2_DMAEN_CYCLE0FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_CYCLE0FEN_MASK) >> QEIV2_DMAEN_CYCLE0FEN_SHIFT)
737 
738 /*
739  * CYCLE1FEN (RW)
740  *
741  */
742 #define QEIV2_DMAEN_CYCLE1FEN_MASK (0x400000UL)
743 #define QEIV2_DMAEN_CYCLE1FEN_SHIFT (22U)
744 #define QEIV2_DMAEN_CYCLE1FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_CYCLE1FEN_SHIFT) & QEIV2_DMAEN_CYCLE1FEN_MASK)
745 #define QEIV2_DMAEN_CYCLE1FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_CYCLE1FEN_MASK) >> QEIV2_DMAEN_CYCLE1FEN_SHIFT)
746 
747 /*
748  * PULSE0FEN (RW)
749  *
750  */
751 #define QEIV2_DMAEN_PULSE0FEN_MASK (0x200000UL)
752 #define QEIV2_DMAEN_PULSE0FEN_SHIFT (21U)
753 #define QEIV2_DMAEN_PULSE0FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_PULSE0FEN_SHIFT) & QEIV2_DMAEN_PULSE0FEN_MASK)
754 #define QEIV2_DMAEN_PULSE0FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_PULSE0FEN_MASK) >> QEIV2_DMAEN_PULSE0FEN_SHIFT)
755 
756 /*
757  * PULSE1FEN (RW)
758  *
759  */
760 #define QEIV2_DMAEN_PULSE1FEN_MASK (0x100000UL)
761 #define QEIV2_DMAEN_PULSE1FEN_SHIFT (20U)
762 #define QEIV2_DMAEN_PULSE1FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_PULSE1FEN_SHIFT) & QEIV2_DMAEN_PULSE1FEN_MASK)
763 #define QEIV2_DMAEN_PULSE1FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_PULSE1FEN_MASK) >> QEIV2_DMAEN_PULSE1FEN_SHIFT)
764 
765 /*
766  * HOME2FEN (RW)
767  *
768  */
769 #define QEIV2_DMAEN_HOME2FEN_MASK (0x80000UL)
770 #define QEIV2_DMAEN_HOME2FEN_SHIFT (19U)
771 #define QEIV2_DMAEN_HOME2FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_HOME2FEN_SHIFT) & QEIV2_DMAEN_HOME2FEN_MASK)
772 #define QEIV2_DMAEN_HOME2FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_HOME2FEN_MASK) >> QEIV2_DMAEN_HOME2FEN_SHIFT)
773 
774 /*
775  * FAULTFEN (RW)
776  *
777  */
778 #define QEIV2_DMAEN_FAULTFEN_MASK (0x40000UL)
779 #define QEIV2_DMAEN_FAULTFEN_SHIFT (18U)
780 #define QEIV2_DMAEN_FAULTFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_FAULTFEN_SHIFT) & QEIV2_DMAEN_FAULTFEN_MASK)
781 #define QEIV2_DMAEN_FAULTFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_FAULTFEN_MASK) >> QEIV2_DMAEN_FAULTFEN_SHIFT)
782 
783 /* Bitfield definition for register: SR */
784 /*
785  * WDGF (RW)
786  *
787  * watchdog flag
788  */
789 #define QEIV2_SR_WDGF_MASK (0x80000000UL)
790 #define QEIV2_SR_WDGF_SHIFT (31U)
791 #define QEIV2_SR_WDGF_SET(x) (((uint32_t)(x) << QEIV2_SR_WDGF_SHIFT) & QEIV2_SR_WDGF_MASK)
792 #define QEIV2_SR_WDGF_GET(x) (((uint32_t)(x) & QEIV2_SR_WDGF_MASK) >> QEIV2_SR_WDGF_SHIFT)
793 
794 /*
795  * HOMEF (RW)
796  *
797  * home flag
798  */
799 #define QEIV2_SR_HOMEF_MASK (0x40000000UL)
800 #define QEIV2_SR_HOMEF_SHIFT (30U)
801 #define QEIV2_SR_HOMEF_SET(x) (((uint32_t)(x) << QEIV2_SR_HOMEF_SHIFT) & QEIV2_SR_HOMEF_MASK)
802 #define QEIV2_SR_HOMEF_GET(x) (((uint32_t)(x) & QEIV2_SR_HOMEF_MASK) >> QEIV2_SR_HOMEF_SHIFT)
803 
804 /*
805  * POSCMPF (RW)
806  *
807  * postion compare match flag
808  */
809 #define QEIV2_SR_POSCMPF_MASK (0x20000000UL)
810 #define QEIV2_SR_POSCMPF_SHIFT (29U)
811 #define QEIV2_SR_POSCMPF_SET(x) (((uint32_t)(x) << QEIV2_SR_POSCMPF_SHIFT) & QEIV2_SR_POSCMPF_MASK)
812 #define QEIV2_SR_POSCMPF_GET(x) (((uint32_t)(x) & QEIV2_SR_POSCMPF_MASK) >> QEIV2_SR_POSCMPF_SHIFT)
813 
814 /*
815  * ZPHF (RW)
816  *
817  * z input flag
818  */
819 #define QEIV2_SR_ZPHF_MASK (0x10000000UL)
820 #define QEIV2_SR_ZPHF_SHIFT (28U)
821 #define QEIV2_SR_ZPHF_SET(x) (((uint32_t)(x) << QEIV2_SR_ZPHF_SHIFT) & QEIV2_SR_ZPHF_MASK)
822 #define QEIV2_SR_ZPHF_GET(x) (((uint32_t)(x) & QEIV2_SR_ZPHF_MASK) >> QEIV2_SR_ZPHF_SHIFT)
823 
824 /*
825  * ZMISSF (RW)
826  *
827  */
828 #define QEIV2_SR_ZMISSF_MASK (0x8000000UL)
829 #define QEIV2_SR_ZMISSF_SHIFT (27U)
830 #define QEIV2_SR_ZMISSF_SET(x) (((uint32_t)(x) << QEIV2_SR_ZMISSF_SHIFT) & QEIV2_SR_ZMISSF_MASK)
831 #define QEIV2_SR_ZMISSF_GET(x) (((uint32_t)(x) & QEIV2_SR_ZMISSF_MASK) >> QEIV2_SR_ZMISSF_SHIFT)
832 
833 /*
834  * WIDTHTMF (RW)
835  *
836  */
837 #define QEIV2_SR_WIDTHTMF_MASK (0x4000000UL)
838 #define QEIV2_SR_WIDTHTMF_SHIFT (26U)
839 #define QEIV2_SR_WIDTHTMF_SET(x) (((uint32_t)(x) << QEIV2_SR_WIDTHTMF_SHIFT) & QEIV2_SR_WIDTHTMF_MASK)
840 #define QEIV2_SR_WIDTHTMF_GET(x) (((uint32_t)(x) & QEIV2_SR_WIDTHTMF_MASK) >> QEIV2_SR_WIDTHTMF_SHIFT)
841 
842 /*
843  * POS2CMPF (RW)
844  *
845  */
846 #define QEIV2_SR_POS2CMPF_MASK (0x2000000UL)
847 #define QEIV2_SR_POS2CMPF_SHIFT (25U)
848 #define QEIV2_SR_POS2CMPF_SET(x) (((uint32_t)(x) << QEIV2_SR_POS2CMPF_SHIFT) & QEIV2_SR_POS2CMPF_MASK)
849 #define QEIV2_SR_POS2CMPF_GET(x) (((uint32_t)(x) & QEIV2_SR_POS2CMPF_MASK) >> QEIV2_SR_POS2CMPF_SHIFT)
850 
851 /*
852  * DIRCHGF (RW)
853  *
854  */
855 #define QEIV2_SR_DIRCHGF_MASK (0x1000000UL)
856 #define QEIV2_SR_DIRCHGF_SHIFT (24U)
857 #define QEIV2_SR_DIRCHGF_SET(x) (((uint32_t)(x) << QEIV2_SR_DIRCHGF_SHIFT) & QEIV2_SR_DIRCHGF_MASK)
858 #define QEIV2_SR_DIRCHGF_GET(x) (((uint32_t)(x) & QEIV2_SR_DIRCHGF_MASK) >> QEIV2_SR_DIRCHGF_SHIFT)
859 
860 /*
861  * CYCLE0F (RW)
862  *
863  */
864 #define QEIV2_SR_CYCLE0F_MASK (0x800000UL)
865 #define QEIV2_SR_CYCLE0F_SHIFT (23U)
866 #define QEIV2_SR_CYCLE0F_SET(x) (((uint32_t)(x) << QEIV2_SR_CYCLE0F_SHIFT) & QEIV2_SR_CYCLE0F_MASK)
867 #define QEIV2_SR_CYCLE0F_GET(x) (((uint32_t)(x) & QEIV2_SR_CYCLE0F_MASK) >> QEIV2_SR_CYCLE0F_SHIFT)
868 
869 /*
870  * CYCLE1F (RW)
871  *
872  */
873 #define QEIV2_SR_CYCLE1F_MASK (0x400000UL)
874 #define QEIV2_SR_CYCLE1F_SHIFT (22U)
875 #define QEIV2_SR_CYCLE1F_SET(x) (((uint32_t)(x) << QEIV2_SR_CYCLE1F_SHIFT) & QEIV2_SR_CYCLE1F_MASK)
876 #define QEIV2_SR_CYCLE1F_GET(x) (((uint32_t)(x) & QEIV2_SR_CYCLE1F_MASK) >> QEIV2_SR_CYCLE1F_SHIFT)
877 
878 /*
879  * PULSE0F (RW)
880  *
881  */
882 #define QEIV2_SR_PULSE0F_MASK (0x200000UL)
883 #define QEIV2_SR_PULSE0F_SHIFT (21U)
884 #define QEIV2_SR_PULSE0F_SET(x) (((uint32_t)(x) << QEIV2_SR_PULSE0F_SHIFT) & QEIV2_SR_PULSE0F_MASK)
885 #define QEIV2_SR_PULSE0F_GET(x) (((uint32_t)(x) & QEIV2_SR_PULSE0F_MASK) >> QEIV2_SR_PULSE0F_SHIFT)
886 
887 /*
888  * PULSE1F (RW)
889  *
890  */
891 #define QEIV2_SR_PULSE1F_MASK (0x100000UL)
892 #define QEIV2_SR_PULSE1F_SHIFT (20U)
893 #define QEIV2_SR_PULSE1F_SET(x) (((uint32_t)(x) << QEIV2_SR_PULSE1F_SHIFT) & QEIV2_SR_PULSE1F_MASK)
894 #define QEIV2_SR_PULSE1F_GET(x) (((uint32_t)(x) & QEIV2_SR_PULSE1F_MASK) >> QEIV2_SR_PULSE1F_SHIFT)
895 
896 /*
897  * HOME2F (RW)
898  *
899  */
900 #define QEIV2_SR_HOME2F_MASK (0x80000UL)
901 #define QEIV2_SR_HOME2F_SHIFT (19U)
902 #define QEIV2_SR_HOME2F_SET(x) (((uint32_t)(x) << QEIV2_SR_HOME2F_SHIFT) & QEIV2_SR_HOME2F_MASK)
903 #define QEIV2_SR_HOME2F_GET(x) (((uint32_t)(x) & QEIV2_SR_HOME2F_MASK) >> QEIV2_SR_HOME2F_SHIFT)
904 
905 /*
906  * FAULTF (RW)
907  *
908  */
909 #define QEIV2_SR_FAULTF_MASK (0x40000UL)
910 #define QEIV2_SR_FAULTF_SHIFT (18U)
911 #define QEIV2_SR_FAULTF_SET(x) (((uint32_t)(x) << QEIV2_SR_FAULTF_SHIFT) & QEIV2_SR_FAULTF_MASK)
912 #define QEIV2_SR_FAULTF_GET(x) (((uint32_t)(x) & QEIV2_SR_FAULTF_MASK) >> QEIV2_SR_FAULTF_SHIFT)
913 
914 /* Bitfield definition for register: IRQEN */
915 /*
916  * WDGIE (RW)
917  *
918  * 1- generate interrupt when wdg flag set
919  */
920 #define QEIV2_IRQEN_WDGIE_MASK (0x80000000UL)
921 #define QEIV2_IRQEN_WDGIE_SHIFT (31U)
922 #define QEIV2_IRQEN_WDGIE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_WDGIE_SHIFT) & QEIV2_IRQEN_WDGIE_MASK)
923 #define QEIV2_IRQEN_WDGIE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_WDGIE_MASK) >> QEIV2_IRQEN_WDGIE_SHIFT)
924 
925 /*
926  * HOMEIE (RW)
927  *
928  * 1- generate interrupt when homef flag set
929  */
930 #define QEIV2_IRQEN_HOMEIE_MASK (0x40000000UL)
931 #define QEIV2_IRQEN_HOMEIE_SHIFT (30U)
932 #define QEIV2_IRQEN_HOMEIE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_HOMEIE_SHIFT) & QEIV2_IRQEN_HOMEIE_MASK)
933 #define QEIV2_IRQEN_HOMEIE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_HOMEIE_MASK) >> QEIV2_IRQEN_HOMEIE_SHIFT)
934 
935 /*
936  * POSCMPIE (RW)
937  *
938  * 1- generate interrupt when poscmpf flag set
939  */
940 #define QEIV2_IRQEN_POSCMPIE_MASK (0x20000000UL)
941 #define QEIV2_IRQEN_POSCMPIE_SHIFT (29U)
942 #define QEIV2_IRQEN_POSCMPIE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_POSCMPIE_SHIFT) & QEIV2_IRQEN_POSCMPIE_MASK)
943 #define QEIV2_IRQEN_POSCMPIE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_POSCMPIE_MASK) >> QEIV2_IRQEN_POSCMPIE_SHIFT)
944 
945 /*
946  * ZPHIE (RW)
947  *
948  * 1- generate interrupt when zphf flag set
949  */
950 #define QEIV2_IRQEN_ZPHIE_MASK (0x10000000UL)
951 #define QEIV2_IRQEN_ZPHIE_SHIFT (28U)
952 #define QEIV2_IRQEN_ZPHIE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_ZPHIE_SHIFT) & QEIV2_IRQEN_ZPHIE_MASK)
953 #define QEIV2_IRQEN_ZPHIE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_ZPHIE_MASK) >> QEIV2_IRQEN_ZPHIE_SHIFT)
954 
955 /*
956  * ZMISSE (RW)
957  *
958  */
959 #define QEIV2_IRQEN_ZMISSE_MASK (0x8000000UL)
960 #define QEIV2_IRQEN_ZMISSE_SHIFT (27U)
961 #define QEIV2_IRQEN_ZMISSE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_ZMISSE_SHIFT) & QEIV2_IRQEN_ZMISSE_MASK)
962 #define QEIV2_IRQEN_ZMISSE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_ZMISSE_MASK) >> QEIV2_IRQEN_ZMISSE_SHIFT)
963 
964 /*
965  * WIDTHTME (RW)
966  *
967  */
968 #define QEIV2_IRQEN_WIDTHTME_MASK (0x4000000UL)
969 #define QEIV2_IRQEN_WIDTHTME_SHIFT (26U)
970 #define QEIV2_IRQEN_WIDTHTME_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_WIDTHTME_SHIFT) & QEIV2_IRQEN_WIDTHTME_MASK)
971 #define QEIV2_IRQEN_WIDTHTME_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_WIDTHTME_MASK) >> QEIV2_IRQEN_WIDTHTME_SHIFT)
972 
973 /*
974  * POS2CMPE (RW)
975  *
976  */
977 #define QEIV2_IRQEN_POS2CMPE_MASK (0x2000000UL)
978 #define QEIV2_IRQEN_POS2CMPE_SHIFT (25U)
979 #define QEIV2_IRQEN_POS2CMPE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_POS2CMPE_SHIFT) & QEIV2_IRQEN_POS2CMPE_MASK)
980 #define QEIV2_IRQEN_POS2CMPE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_POS2CMPE_MASK) >> QEIV2_IRQEN_POS2CMPE_SHIFT)
981 
982 /*
983  * DIRCHGE (RW)
984  *
985  */
986 #define QEIV2_IRQEN_DIRCHGE_MASK (0x1000000UL)
987 #define QEIV2_IRQEN_DIRCHGE_SHIFT (24U)
988 #define QEIV2_IRQEN_DIRCHGE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_DIRCHGE_SHIFT) & QEIV2_IRQEN_DIRCHGE_MASK)
989 #define QEIV2_IRQEN_DIRCHGE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_DIRCHGE_MASK) >> QEIV2_IRQEN_DIRCHGE_SHIFT)
990 
991 /*
992  * CYCLE0E (RW)
993  *
994  */
995 #define QEIV2_IRQEN_CYCLE0E_MASK (0x800000UL)
996 #define QEIV2_IRQEN_CYCLE0E_SHIFT (23U)
997 #define QEIV2_IRQEN_CYCLE0E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_CYCLE0E_SHIFT) & QEIV2_IRQEN_CYCLE0E_MASK)
998 #define QEIV2_IRQEN_CYCLE0E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_CYCLE0E_MASK) >> QEIV2_IRQEN_CYCLE0E_SHIFT)
999 
1000 /*
1001  * CYCLE1E (RW)
1002  *
1003  */
1004 #define QEIV2_IRQEN_CYCLE1E_MASK (0x400000UL)
1005 #define QEIV2_IRQEN_CYCLE1E_SHIFT (22U)
1006 #define QEIV2_IRQEN_CYCLE1E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_CYCLE1E_SHIFT) & QEIV2_IRQEN_CYCLE1E_MASK)
1007 #define QEIV2_IRQEN_CYCLE1E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_CYCLE1E_MASK) >> QEIV2_IRQEN_CYCLE1E_SHIFT)
1008 
1009 /*
1010  * PULSE0E (RW)
1011  *
1012  */
1013 #define QEIV2_IRQEN_PULSE0E_MASK (0x200000UL)
1014 #define QEIV2_IRQEN_PULSE0E_SHIFT (21U)
1015 #define QEIV2_IRQEN_PULSE0E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_PULSE0E_SHIFT) & QEIV2_IRQEN_PULSE0E_MASK)
1016 #define QEIV2_IRQEN_PULSE0E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_PULSE0E_MASK) >> QEIV2_IRQEN_PULSE0E_SHIFT)
1017 
1018 /*
1019  * PULSE1E (RW)
1020  *
1021  */
1022 #define QEIV2_IRQEN_PULSE1E_MASK (0x100000UL)
1023 #define QEIV2_IRQEN_PULSE1E_SHIFT (20U)
1024 #define QEIV2_IRQEN_PULSE1E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_PULSE1E_SHIFT) & QEIV2_IRQEN_PULSE1E_MASK)
1025 #define QEIV2_IRQEN_PULSE1E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_PULSE1E_MASK) >> QEIV2_IRQEN_PULSE1E_SHIFT)
1026 
1027 /*
1028  * HOME2E (RW)
1029  *
1030  */
1031 #define QEIV2_IRQEN_HOME2E_MASK (0x80000UL)
1032 #define QEIV2_IRQEN_HOME2E_SHIFT (19U)
1033 #define QEIV2_IRQEN_HOME2E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_HOME2E_SHIFT) & QEIV2_IRQEN_HOME2E_MASK)
1034 #define QEIV2_IRQEN_HOME2E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_HOME2E_MASK) >> QEIV2_IRQEN_HOME2E_SHIFT)
1035 
1036 /*
1037  * FAULTE (RW)
1038  *
1039  */
1040 #define QEIV2_IRQEN_FAULTE_MASK (0x40000UL)
1041 #define QEIV2_IRQEN_FAULTE_SHIFT (18U)
1042 #define QEIV2_IRQEN_FAULTE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_FAULTE_SHIFT) & QEIV2_IRQEN_FAULTE_MASK)
1043 #define QEIV2_IRQEN_FAULTE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_FAULTE_MASK) >> QEIV2_IRQEN_FAULTE_SHIFT)
1044 
1045 /* Bitfield definition for register of struct array COUNT: Z */
1046 /*
1047  * ZCNT (RW)
1048  *
1049  * zcnt value
1050  */
1051 #define QEIV2_COUNT_Z_ZCNT_MASK (0xFFFFFFFFUL)
1052 #define QEIV2_COUNT_Z_ZCNT_SHIFT (0U)
1053 #define QEIV2_COUNT_Z_ZCNT_SET(x) (((uint32_t)(x) << QEIV2_COUNT_Z_ZCNT_SHIFT) & QEIV2_COUNT_Z_ZCNT_MASK)
1054 #define QEIV2_COUNT_Z_ZCNT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_Z_ZCNT_MASK) >> QEIV2_COUNT_Z_ZCNT_SHIFT)
1055 
1056 /* Bitfield definition for register of struct array COUNT: PH */
1057 /*
1058  * DIR (RO)
1059  *
1060  * 1- reverse rotation
1061  * 0- forward rotation
1062  */
1063 #define QEIV2_COUNT_PH_DIR_MASK (0x40000000UL)
1064 #define QEIV2_COUNT_PH_DIR_SHIFT (30U)
1065 #define QEIV2_COUNT_PH_DIR_GET(x) (((uint32_t)(x) & QEIV2_COUNT_PH_DIR_MASK) >> QEIV2_COUNT_PH_DIR_SHIFT)
1066 
1067 /*
1068  * ASTAT (RO)
1069  *
1070  * 1- a input is high
1071  * 0- a input is low
1072  */
1073 #define QEIV2_COUNT_PH_ASTAT_MASK (0x4000000UL)
1074 #define QEIV2_COUNT_PH_ASTAT_SHIFT (26U)
1075 #define QEIV2_COUNT_PH_ASTAT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_PH_ASTAT_MASK) >> QEIV2_COUNT_PH_ASTAT_SHIFT)
1076 
1077 /*
1078  * BSTAT (RO)
1079  *
1080  * 1- b input is high
1081  * 0- b input is low
1082  */
1083 #define QEIV2_COUNT_PH_BSTAT_MASK (0x2000000UL)
1084 #define QEIV2_COUNT_PH_BSTAT_SHIFT (25U)
1085 #define QEIV2_COUNT_PH_BSTAT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_PH_BSTAT_MASK) >> QEIV2_COUNT_PH_BSTAT_SHIFT)
1086 
1087 /*
1088  * PHCNT (RO)
1089  *
1090  * phcnt value
1091  */
1092 #define QEIV2_COUNT_PH_PHCNT_MASK (0x1FFFFFUL)
1093 #define QEIV2_COUNT_PH_PHCNT_SHIFT (0U)
1094 #define QEIV2_COUNT_PH_PHCNT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_PH_PHCNT_MASK) >> QEIV2_COUNT_PH_PHCNT_SHIFT)
1095 
1096 /* Bitfield definition for register of struct array COUNT: SPD */
1097 /*
1098  * DIR (RO)
1099  *
1100  * 1- reverse rotation
1101  * 0- forward rotation
1102  */
1103 #define QEIV2_COUNT_SPD_DIR_MASK (0x80000000UL)
1104 #define QEIV2_COUNT_SPD_DIR_SHIFT (31U)
1105 #define QEIV2_COUNT_SPD_DIR_GET(x) (((uint32_t)(x) & QEIV2_COUNT_SPD_DIR_MASK) >> QEIV2_COUNT_SPD_DIR_SHIFT)
1106 
1107 /*
1108  * ASTAT (RO)
1109  *
1110  * 1- a input is high
1111  * 0- a input is low
1112  */
1113 #define QEIV2_COUNT_SPD_ASTAT_MASK (0x40000000UL)
1114 #define QEIV2_COUNT_SPD_ASTAT_SHIFT (30U)
1115 #define QEIV2_COUNT_SPD_ASTAT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_SPD_ASTAT_MASK) >> QEIV2_COUNT_SPD_ASTAT_SHIFT)
1116 
1117 /*
1118  * BSTAT (RW)
1119  *
1120  * 1- b input is high
1121  * 0- b input is low
1122  */
1123 #define QEIV2_COUNT_SPD_BSTAT_MASK (0x20000000UL)
1124 #define QEIV2_COUNT_SPD_BSTAT_SHIFT (29U)
1125 #define QEIV2_COUNT_SPD_BSTAT_SET(x) (((uint32_t)(x) << QEIV2_COUNT_SPD_BSTAT_SHIFT) & QEIV2_COUNT_SPD_BSTAT_MASK)
1126 #define QEIV2_COUNT_SPD_BSTAT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_SPD_BSTAT_MASK) >> QEIV2_COUNT_SPD_BSTAT_SHIFT)
1127 
1128 /*
1129  * SPDCNT (RO)
1130  *
1131  * spdcnt value
1132  */
1133 #define QEIV2_COUNT_SPD_SPDCNT_MASK (0xFFFFFFFUL)
1134 #define QEIV2_COUNT_SPD_SPDCNT_SHIFT (0U)
1135 #define QEIV2_COUNT_SPD_SPDCNT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_SPD_SPDCNT_MASK) >> QEIV2_COUNT_SPD_SPDCNT_SHIFT)
1136 
1137 /* Bitfield definition for register of struct array COUNT: TMR */
1138 /*
1139  * TMRCNT (RO)
1140  *
1141  * 32 bit free run timer
1142  */
1143 #define QEIV2_COUNT_TMR_TMRCNT_MASK (0xFFFFFFFFUL)
1144 #define QEIV2_COUNT_TMR_TMRCNT_SHIFT (0U)
1145 #define QEIV2_COUNT_TMR_TMRCNT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_TMR_TMRCNT_MASK) >> QEIV2_COUNT_TMR_TMRCNT_SHIFT)
1146 
1147 /* Bitfield definition for register: ZCMP2 */
1148 /*
1149  * ZCMP2 (RW)
1150  *
1151  */
1152 #define QEIV2_ZCMP2_ZCMP2_MASK (0xFFFFFFFFUL)
1153 #define QEIV2_ZCMP2_ZCMP2_SHIFT (0U)
1154 #define QEIV2_ZCMP2_ZCMP2_SET(x) (((uint32_t)(x) << QEIV2_ZCMP2_ZCMP2_SHIFT) & QEIV2_ZCMP2_ZCMP2_MASK)
1155 #define QEIV2_ZCMP2_ZCMP2_GET(x) (((uint32_t)(x) & QEIV2_ZCMP2_ZCMP2_MASK) >> QEIV2_ZCMP2_ZCMP2_SHIFT)
1156 
1157 /* Bitfield definition for register: PHCMP2 */
1158 /*
1159  * PHCMP2 (RW)
1160  *
1161  */
1162 #define QEIV2_PHCMP2_PHCMP2_MASK (0xFFFFFFFFUL)
1163 #define QEIV2_PHCMP2_PHCMP2_SHIFT (0U)
1164 #define QEIV2_PHCMP2_PHCMP2_SET(x) (((uint32_t)(x) << QEIV2_PHCMP2_PHCMP2_SHIFT) & QEIV2_PHCMP2_PHCMP2_MASK)
1165 #define QEIV2_PHCMP2_PHCMP2_GET(x) (((uint32_t)(x) & QEIV2_PHCMP2_PHCMP2_MASK) >> QEIV2_PHCMP2_PHCMP2_SHIFT)
1166 
1167 /* Bitfield definition for register: SPDCMP2 */
1168 /*
1169  * SPDCMP2 (RW)
1170  *
1171  */
1172 #define QEIV2_SPDCMP2_SPDCMP2_MASK (0xFFFFFFFFUL)
1173 #define QEIV2_SPDCMP2_SPDCMP2_SHIFT (0U)
1174 #define QEIV2_SPDCMP2_SPDCMP2_SET(x) (((uint32_t)(x) << QEIV2_SPDCMP2_SPDCMP2_SHIFT) & QEIV2_SPDCMP2_SPDCMP2_MASK)
1175 #define QEIV2_SPDCMP2_SPDCMP2_GET(x) (((uint32_t)(x) & QEIV2_SPDCMP2_SPDCMP2_MASK) >> QEIV2_SPDCMP2_SPDCMP2_SHIFT)
1176 
1177 /* Bitfield definition for register: MATCH_CFG */
1178 /*
1179  * ZCMPDIS (RW)
1180  *
1181  * 1- postion compare not include zcnt
1182  */
1183 #define QEIV2_MATCH_CFG_ZCMPDIS_MASK (0x80000000UL)
1184 #define QEIV2_MATCH_CFG_ZCMPDIS_SHIFT (31U)
1185 #define QEIV2_MATCH_CFG_ZCMPDIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_ZCMPDIS_SHIFT) & QEIV2_MATCH_CFG_ZCMPDIS_MASK)
1186 #define QEIV2_MATCH_CFG_ZCMPDIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_ZCMPDIS_MASK) >> QEIV2_MATCH_CFG_ZCMPDIS_SHIFT)
1187 
1188 /*
1189  * DIRCMPDIS (RW)
1190  *
1191  * 1- postion compare not include rotation direction
1192  */
1193 #define QEIV2_MATCH_CFG_DIRCMPDIS_MASK (0x40000000UL)
1194 #define QEIV2_MATCH_CFG_DIRCMPDIS_SHIFT (30U)
1195 #define QEIV2_MATCH_CFG_DIRCMPDIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMPDIS_SHIFT) & QEIV2_MATCH_CFG_DIRCMPDIS_MASK)
1196 #define QEIV2_MATCH_CFG_DIRCMPDIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMPDIS_MASK) >> QEIV2_MATCH_CFG_DIRCMPDIS_SHIFT)
1197 
1198 /*
1199  * DIRCMP (RW)
1200  *
1201  * 0- position compare need positive rotation
1202  * 1- position compare need negative rotation
1203  */
1204 #define QEIV2_MATCH_CFG_DIRCMP_MASK (0x20000000UL)
1205 #define QEIV2_MATCH_CFG_DIRCMP_SHIFT (29U)
1206 #define QEIV2_MATCH_CFG_DIRCMP_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMP_SHIFT) & QEIV2_MATCH_CFG_DIRCMP_MASK)
1207 #define QEIV2_MATCH_CFG_DIRCMP_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMP_MASK) >> QEIV2_MATCH_CFG_DIRCMP_SHIFT)
1208 
1209 /*
1210  * SPDCMPDIS (RW)
1211  *
1212  */
1213 #define QEIV2_MATCH_CFG_SPDCMPDIS_MASK (0x10000000UL)
1214 #define QEIV2_MATCH_CFG_SPDCMPDIS_SHIFT (28U)
1215 #define QEIV2_MATCH_CFG_SPDCMPDIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_SPDCMPDIS_SHIFT) & QEIV2_MATCH_CFG_SPDCMPDIS_MASK)
1216 #define QEIV2_MATCH_CFG_SPDCMPDIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_SPDCMPDIS_MASK) >> QEIV2_MATCH_CFG_SPDCMPDIS_SHIFT)
1217 
1218 /*
1219  * PHASE_MATCH_DIS (RW)
1220  *
1221  */
1222 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_MASK (0x8000000UL)
1223 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SHIFT (27U)
1224 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SHIFT) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS_MASK)
1225 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS_MASK) >> QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SHIFT)
1226 
1227 /*
1228  * POS_MATCH_DIR (RW)
1229  *
1230  */
1231 #define QEIV2_MATCH_CFG_POS_MATCH_DIR_MASK (0x4000000UL)
1232 #define QEIV2_MATCH_CFG_POS_MATCH_DIR_SHIFT (26U)
1233 #define QEIV2_MATCH_CFG_POS_MATCH_DIR_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH_DIR_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH_DIR_MASK)
1234 #define QEIV2_MATCH_CFG_POS_MATCH_DIR_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH_DIR_MASK) >> QEIV2_MATCH_CFG_POS_MATCH_DIR_SHIFT)
1235 
1236 /*
1237  * POS_MATCH_OPT (RW)
1238  *
1239  */
1240 #define QEIV2_MATCH_CFG_POS_MATCH_OPT_MASK (0x2000000UL)
1241 #define QEIV2_MATCH_CFG_POS_MATCH_OPT_SHIFT (25U)
1242 #define QEIV2_MATCH_CFG_POS_MATCH_OPT_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH_OPT_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH_OPT_MASK)
1243 #define QEIV2_MATCH_CFG_POS_MATCH_OPT_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH_OPT_MASK) >> QEIV2_MATCH_CFG_POS_MATCH_OPT_SHIFT)
1244 
1245 /*
1246  * ZCMP2DIS (RW)
1247  *
1248  */
1249 #define QEIV2_MATCH_CFG_ZCMP2DIS_MASK (0x8000U)
1250 #define QEIV2_MATCH_CFG_ZCMP2DIS_SHIFT (15U)
1251 #define QEIV2_MATCH_CFG_ZCMP2DIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_ZCMP2DIS_SHIFT) & QEIV2_MATCH_CFG_ZCMP2DIS_MASK)
1252 #define QEIV2_MATCH_CFG_ZCMP2DIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_ZCMP2DIS_MASK) >> QEIV2_MATCH_CFG_ZCMP2DIS_SHIFT)
1253 
1254 /*
1255  * DIRCMP2DIS (RW)
1256  *
1257  */
1258 #define QEIV2_MATCH_CFG_DIRCMP2DIS_MASK (0x4000U)
1259 #define QEIV2_MATCH_CFG_DIRCMP2DIS_SHIFT (14U)
1260 #define QEIV2_MATCH_CFG_DIRCMP2DIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMP2DIS_SHIFT) & QEIV2_MATCH_CFG_DIRCMP2DIS_MASK)
1261 #define QEIV2_MATCH_CFG_DIRCMP2DIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMP2DIS_MASK) >> QEIV2_MATCH_CFG_DIRCMP2DIS_SHIFT)
1262 
1263 /*
1264  * DIRCMP2 (RW)
1265  *
1266  */
1267 #define QEIV2_MATCH_CFG_DIRCMP2_MASK (0x2000U)
1268 #define QEIV2_MATCH_CFG_DIRCMP2_SHIFT (13U)
1269 #define QEIV2_MATCH_CFG_DIRCMP2_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMP2_SHIFT) & QEIV2_MATCH_CFG_DIRCMP2_MASK)
1270 #define QEIV2_MATCH_CFG_DIRCMP2_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMP2_MASK) >> QEIV2_MATCH_CFG_DIRCMP2_SHIFT)
1271 
1272 /*
1273  * SPDCMP2DIS (RW)
1274  *
1275  */
1276 #define QEIV2_MATCH_CFG_SPDCMP2DIS_MASK (0x1000U)
1277 #define QEIV2_MATCH_CFG_SPDCMP2DIS_SHIFT (12U)
1278 #define QEIV2_MATCH_CFG_SPDCMP2DIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_SPDCMP2DIS_SHIFT) & QEIV2_MATCH_CFG_SPDCMP2DIS_MASK)
1279 #define QEIV2_MATCH_CFG_SPDCMP2DIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_SPDCMP2DIS_MASK) >> QEIV2_MATCH_CFG_SPDCMP2DIS_SHIFT)
1280 
1281 /*
1282  * PHASE_MATCH_DIS2 (RW)
1283  *
1284  */
1285 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_MASK (0x800U)
1286 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SHIFT (11U)
1287 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SHIFT) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_MASK)
1288 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_MASK) >> QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SHIFT)
1289 
1290 /*
1291  * POS_MATCH2_DIR (RW)
1292  *
1293  */
1294 #define QEIV2_MATCH_CFG_POS_MATCH2_DIR_MASK (0x400U)
1295 #define QEIV2_MATCH_CFG_POS_MATCH2_DIR_SHIFT (10U)
1296 #define QEIV2_MATCH_CFG_POS_MATCH2_DIR_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH2_DIR_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH2_DIR_MASK)
1297 #define QEIV2_MATCH_CFG_POS_MATCH2_DIR_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH2_DIR_MASK) >> QEIV2_MATCH_CFG_POS_MATCH2_DIR_SHIFT)
1298 
1299 /*
1300  * POS_MATCH2_OPT (RW)
1301  *
1302  */
1303 #define QEIV2_MATCH_CFG_POS_MATCH2_OPT_MASK (0x200U)
1304 #define QEIV2_MATCH_CFG_POS_MATCH2_OPT_SHIFT (9U)
1305 #define QEIV2_MATCH_CFG_POS_MATCH2_OPT_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH2_OPT_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH2_OPT_MASK)
1306 #define QEIV2_MATCH_CFG_POS_MATCH2_OPT_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH2_OPT_MASK) >> QEIV2_MATCH_CFG_POS_MATCH2_OPT_SHIFT)
1307 
1308 /* Bitfield definition for register array: FILT_CFG */
1309 /*
1310  * OUTINV (RW)
1311  *
1312  * 1- Filter will invert the output
1313  * 0- Filter will not invert the output
1314  */
1315 #define QEIV2_FILT_CFG_OUTINV_MASK (0x10000UL)
1316 #define QEIV2_FILT_CFG_OUTINV_SHIFT (16U)
1317 #define QEIV2_FILT_CFG_OUTINV_SET(x) (((uint32_t)(x) << QEIV2_FILT_CFG_OUTINV_SHIFT) & QEIV2_FILT_CFG_OUTINV_MASK)
1318 #define QEIV2_FILT_CFG_OUTINV_GET(x) (((uint32_t)(x) & QEIV2_FILT_CFG_OUTINV_MASK) >> QEIV2_FILT_CFG_OUTINV_SHIFT)
1319 
1320 /*
1321  * MODE (RW)
1322  *
1323  * This bitfields defines the filter mode
1324  * 000-bypass;
1325  * 100-rapid change mode;
1326  * 101-delay filter mode;
1327  * 110-stable low mode;
1328  * 111-stable high mode
1329  */
1330 #define QEIV2_FILT_CFG_MODE_MASK (0xE000U)
1331 #define QEIV2_FILT_CFG_MODE_SHIFT (13U)
1332 #define QEIV2_FILT_CFG_MODE_SET(x) (((uint32_t)(x) << QEIV2_FILT_CFG_MODE_SHIFT) & QEIV2_FILT_CFG_MODE_MASK)
1333 #define QEIV2_FILT_CFG_MODE_GET(x) (((uint32_t)(x) & QEIV2_FILT_CFG_MODE_MASK) >> QEIV2_FILT_CFG_MODE_SHIFT)
1334 
1335 /*
1336  * SYNCEN (RW)
1337  *
1338  * set to enable sychronization input signal with TRGM clock
1339  */
1340 #define QEIV2_FILT_CFG_SYNCEN_MASK (0x1000U)
1341 #define QEIV2_FILT_CFG_SYNCEN_SHIFT (12U)
1342 #define QEIV2_FILT_CFG_SYNCEN_SET(x) (((uint32_t)(x) << QEIV2_FILT_CFG_SYNCEN_SHIFT) & QEIV2_FILT_CFG_SYNCEN_MASK)
1343 #define QEIV2_FILT_CFG_SYNCEN_GET(x) (((uint32_t)(x) & QEIV2_FILT_CFG_SYNCEN_MASK) >> QEIV2_FILT_CFG_SYNCEN_SHIFT)
1344 
1345 /*
1346  * FILTLEN (RW)
1347  *
1348  * This bitfields defines the filter counter length.
1349  */
1350 #define QEIV2_FILT_CFG_FILTLEN_MASK (0xFFFU)
1351 #define QEIV2_FILT_CFG_FILTLEN_SHIFT (0U)
1352 #define QEIV2_FILT_CFG_FILTLEN_SET(x) (((uint32_t)(x) << QEIV2_FILT_CFG_FILTLEN_SHIFT) & QEIV2_FILT_CFG_FILTLEN_MASK)
1353 #define QEIV2_FILT_CFG_FILTLEN_GET(x) (((uint32_t)(x) & QEIV2_FILT_CFG_FILTLEN_MASK) >> QEIV2_FILT_CFG_FILTLEN_SHIFT)
1354 
1355 /* Bitfield definition for register: QEI_CFG */
1356 /*
1357  * SPEED_DIR_CHG_EN (RW)
1358  *
1359  * clear counter if detect direction change
1360  */
1361 #define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK (0x1000U)
1362 #define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SHIFT (12U)
1363 #define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SHIFT) & QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK)
1364 #define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK) >> QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SHIFT)
1365 
1366 /*
1367  * UVW_POS_OPT0 (RW)
1368  *
1369  * set to output next area position for QEO use;
1370  * clr to output exact point position for MMC use
1371  */
1372 #define QEIV2_QEI_CFG_UVW_POS_OPT0_MASK (0x20U)
1373 #define QEIV2_QEI_CFG_UVW_POS_OPT0_SHIFT (5U)
1374 #define QEIV2_QEI_CFG_UVW_POS_OPT0_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_UVW_POS_OPT0_SHIFT) & QEIV2_QEI_CFG_UVW_POS_OPT0_MASK)
1375 #define QEIV2_QEI_CFG_UVW_POS_OPT0_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_UVW_POS_OPT0_MASK) >> QEIV2_QEI_CFG_UVW_POS_OPT0_SHIFT)
1376 
1377 /*
1378  * NEGEDGE_EN (RW)
1379  *
1380  * bit4: negedge enable
1381  * bit3: posedge enable
1382  * bit2: W in hal enable
1383  * bit1: signal b(or V in hal) enable
1384  * bit0: signal a(or U in hal) enable
1385  * such as:
1386  * 01001: use posedge A
1387  * 11010: use both edge of signal B
1388  * 11111: use both edge of all HAL siganls
1389  */
1390 #define QEIV2_QEI_CFG_NEGEDGE_EN_MASK (0x10U)
1391 #define QEIV2_QEI_CFG_NEGEDGE_EN_SHIFT (4U)
1392 #define QEIV2_QEI_CFG_NEGEDGE_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_NEGEDGE_EN_SHIFT) & QEIV2_QEI_CFG_NEGEDGE_EN_MASK)
1393 #define QEIV2_QEI_CFG_NEGEDGE_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_NEGEDGE_EN_MASK) >> QEIV2_QEI_CFG_NEGEDGE_EN_SHIFT)
1394 
1395 /*
1396  * POSIDGE_EN (RW)
1397  *
1398  */
1399 #define QEIV2_QEI_CFG_POSIDGE_EN_MASK (0x8U)
1400 #define QEIV2_QEI_CFG_POSIDGE_EN_SHIFT (3U)
1401 #define QEIV2_QEI_CFG_POSIDGE_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_POSIDGE_EN_SHIFT) & QEIV2_QEI_CFG_POSIDGE_EN_MASK)
1402 #define QEIV2_QEI_CFG_POSIDGE_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_POSIDGE_EN_MASK) >> QEIV2_QEI_CFG_POSIDGE_EN_SHIFT)
1403 
1404 /*
1405  * SIGZ_EN (RW)
1406  *
1407  */
1408 #define QEIV2_QEI_CFG_SIGZ_EN_MASK (0x4U)
1409 #define QEIV2_QEI_CFG_SIGZ_EN_SHIFT (2U)
1410 #define QEIV2_QEI_CFG_SIGZ_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SIGZ_EN_SHIFT) & QEIV2_QEI_CFG_SIGZ_EN_MASK)
1411 #define QEIV2_QEI_CFG_SIGZ_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SIGZ_EN_MASK) >> QEIV2_QEI_CFG_SIGZ_EN_SHIFT)
1412 
1413 /*
1414  * SIGB_EN (RW)
1415  *
1416  */
1417 #define QEIV2_QEI_CFG_SIGB_EN_MASK (0x2U)
1418 #define QEIV2_QEI_CFG_SIGB_EN_SHIFT (1U)
1419 #define QEIV2_QEI_CFG_SIGB_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SIGB_EN_SHIFT) & QEIV2_QEI_CFG_SIGB_EN_MASK)
1420 #define QEIV2_QEI_CFG_SIGB_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SIGB_EN_MASK) >> QEIV2_QEI_CFG_SIGB_EN_SHIFT)
1421 
1422 /*
1423  * SIGA_EN (RW)
1424  *
1425  */
1426 #define QEIV2_QEI_CFG_SIGA_EN_MASK (0x1U)
1427 #define QEIV2_QEI_CFG_SIGA_EN_SHIFT (0U)
1428 #define QEIV2_QEI_CFG_SIGA_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SIGA_EN_SHIFT) & QEIV2_QEI_CFG_SIGA_EN_MASK)
1429 #define QEIV2_QEI_CFG_SIGA_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SIGA_EN_MASK) >> QEIV2_QEI_CFG_SIGA_EN_SHIFT)
1430 
1431 /* Bitfield definition for register: PULSE0_NUM */
1432 /*
1433  * PULSE0_NUM (RW)
1434  *
1435  * for speed detection, will count the cycle number for configed pulse_num
1436  */
1437 #define QEIV2_PULSE0_NUM_PULSE0_NUM_MASK (0xFFFFFFFFUL)
1438 #define QEIV2_PULSE0_NUM_PULSE0_NUM_SHIFT (0U)
1439 #define QEIV2_PULSE0_NUM_PULSE0_NUM_SET(x) (((uint32_t)(x) << QEIV2_PULSE0_NUM_PULSE0_NUM_SHIFT) & QEIV2_PULSE0_NUM_PULSE0_NUM_MASK)
1440 #define QEIV2_PULSE0_NUM_PULSE0_NUM_GET(x) (((uint32_t)(x) & QEIV2_PULSE0_NUM_PULSE0_NUM_MASK) >> QEIV2_PULSE0_NUM_PULSE0_NUM_SHIFT)
1441 
1442 /* Bitfield definition for register: PULSE1_NUM */
1443 /*
1444  * PULSE1_NUM (RW)
1445  *
1446  */
1447 #define QEIV2_PULSE1_NUM_PULSE1_NUM_MASK (0xFFFFFFFFUL)
1448 #define QEIV2_PULSE1_NUM_PULSE1_NUM_SHIFT (0U)
1449 #define QEIV2_PULSE1_NUM_PULSE1_NUM_SET(x) (((uint32_t)(x) << QEIV2_PULSE1_NUM_PULSE1_NUM_SHIFT) & QEIV2_PULSE1_NUM_PULSE1_NUM_MASK)
1450 #define QEIV2_PULSE1_NUM_PULSE1_NUM_GET(x) (((uint32_t)(x) & QEIV2_PULSE1_NUM_PULSE1_NUM_MASK) >> QEIV2_PULSE1_NUM_PULSE1_NUM_SHIFT)
1451 
1452 /* Bitfield definition for register: CYCLE0_CNT */
1453 /*
1454  * CYCLE0_CNT (RO)
1455  *
1456  */
1457 #define QEIV2_CYCLE0_CNT_CYCLE0_CNT_MASK (0xFFFFFFFFUL)
1458 #define QEIV2_CYCLE0_CNT_CYCLE0_CNT_SHIFT (0U)
1459 #define QEIV2_CYCLE0_CNT_CYCLE0_CNT_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0_CNT_CYCLE0_CNT_MASK) >> QEIV2_CYCLE0_CNT_CYCLE0_CNT_SHIFT)
1460 
1461 /* Bitfield definition for register: CYCLE0PULSE_CNT */
1462 /*
1463  * CYCLE0PULSE_CNT (RO)
1464  *
1465  */
1466 #define QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_MASK (0xFFFFFFFFUL)
1467 #define QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_SHIFT (0U)
1468 #define QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_MASK) >> QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_SHIFT)
1469 
1470 /* Bitfield definition for register: CYCLE1_CNT */
1471 /*
1472  * CYCLE1_CNT (RO)
1473  *
1474  */
1475 #define QEIV2_CYCLE1_CNT_CYCLE1_CNT_MASK (0xFFFFFFFFUL)
1476 #define QEIV2_CYCLE1_CNT_CYCLE1_CNT_SHIFT (0U)
1477 #define QEIV2_CYCLE1_CNT_CYCLE1_CNT_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1_CNT_CYCLE1_CNT_MASK) >> QEIV2_CYCLE1_CNT_CYCLE1_CNT_SHIFT)
1478 
1479 /* Bitfield definition for register: CYCLE1PULSE_CNT */
1480 /*
1481  * CYCLE1PULSE_CNT (RO)
1482  *
1483  */
1484 #define QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_MASK (0xFFFFFFFFUL)
1485 #define QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_SHIFT (0U)
1486 #define QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_MASK) >> QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_SHIFT)
1487 
1488 /* Bitfield definition for register: CYCLE0_SNAP0 */
1489 /*
1490  * CYCLE0_SNAP0 (RO)
1491  *
1492  */
1493 #define QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_MASK (0xFFFFFFFFUL)
1494 #define QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_SHIFT (0U)
1495 #define QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_MASK) >> QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_SHIFT)
1496 
1497 /* Bitfield definition for register: CYCLE0_SNAP1 */
1498 /*
1499  * CYCLE0_SNAP1 (RO)
1500  *
1501  */
1502 #define QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_MASK (0xFFFFFFFFUL)
1503 #define QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_SHIFT (0U)
1504 #define QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_MASK) >> QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_SHIFT)
1505 
1506 /* Bitfield definition for register: CYCLE1_SNAP0 */
1507 /*
1508  * CYCLE1_SNAP0 (RO)
1509  *
1510  */
1511 #define QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_MASK (0xFFFFFFFFUL)
1512 #define QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_SHIFT (0U)
1513 #define QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_MASK) >> QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_SHIFT)
1514 
1515 /* Bitfield definition for register: CYCLE1_SNAP1 */
1516 /*
1517  * CYCLE1_SNAP1 (RO)
1518  *
1519  */
1520 #define QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_MASK (0xFFFFFFFFUL)
1521 #define QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_SHIFT (0U)
1522 #define QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_MASK) >> QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_SHIFT)
1523 
1524 /* Bitfield definition for register: CYCLE0_NUM */
1525 /*
1526  * CYCLE0_NUM (RW)
1527  *
1528  */
1529 #define QEIV2_CYCLE0_NUM_CYCLE0_NUM_MASK (0xFFFFFFFFUL)
1530 #define QEIV2_CYCLE0_NUM_CYCLE0_NUM_SHIFT (0U)
1531 #define QEIV2_CYCLE0_NUM_CYCLE0_NUM_SET(x) (((uint32_t)(x) << QEIV2_CYCLE0_NUM_CYCLE0_NUM_SHIFT) & QEIV2_CYCLE0_NUM_CYCLE0_NUM_MASK)
1532 #define QEIV2_CYCLE0_NUM_CYCLE0_NUM_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0_NUM_CYCLE0_NUM_MASK) >> QEIV2_CYCLE0_NUM_CYCLE0_NUM_SHIFT)
1533 
1534 /* Bitfield definition for register: CYCLE1_NUM */
1535 /*
1536  * CYCLE1_NUM (RW)
1537  *
1538  */
1539 #define QEIV2_CYCLE1_NUM_CYCLE1_NUM_MASK (0xFFFFFFFFUL)
1540 #define QEIV2_CYCLE1_NUM_CYCLE1_NUM_SHIFT (0U)
1541 #define QEIV2_CYCLE1_NUM_CYCLE1_NUM_SET(x) (((uint32_t)(x) << QEIV2_CYCLE1_NUM_CYCLE1_NUM_SHIFT) & QEIV2_CYCLE1_NUM_CYCLE1_NUM_MASK)
1542 #define QEIV2_CYCLE1_NUM_CYCLE1_NUM_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1_NUM_CYCLE1_NUM_MASK) >> QEIV2_CYCLE1_NUM_CYCLE1_NUM_SHIFT)
1543 
1544 /* Bitfield definition for register: PULSE0_CNT */
1545 /*
1546  * PULSE0_CNT (RO)
1547  *
1548  */
1549 #define QEIV2_PULSE0_CNT_PULSE0_CNT_MASK (0xFFFFFFFFUL)
1550 #define QEIV2_PULSE0_CNT_PULSE0_CNT_SHIFT (0U)
1551 #define QEIV2_PULSE0_CNT_PULSE0_CNT_GET(x) (((uint32_t)(x) & QEIV2_PULSE0_CNT_PULSE0_CNT_MASK) >> QEIV2_PULSE0_CNT_PULSE0_CNT_SHIFT)
1552 
1553 /* Bitfield definition for register: PULSE0CYCLE_CNT */
1554 /*
1555  * PULSE0CYCLE_CNT (RO)
1556  *
1557  */
1558 #define QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_MASK (0xFFFFFFFFUL)
1559 #define QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_SHIFT (0U)
1560 #define QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_GET(x) (((uint32_t)(x) & QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_MASK) >> QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_SHIFT)
1561 
1562 /* Bitfield definition for register: PULSE1_CNT */
1563 /*
1564  * PULSE1_CNT (RO)
1565  *
1566  */
1567 #define QEIV2_PULSE1_CNT_PULSE1_CNT_MASK (0xFFFFFFFFUL)
1568 #define QEIV2_PULSE1_CNT_PULSE1_CNT_SHIFT (0U)
1569 #define QEIV2_PULSE1_CNT_PULSE1_CNT_GET(x) (((uint32_t)(x) & QEIV2_PULSE1_CNT_PULSE1_CNT_MASK) >> QEIV2_PULSE1_CNT_PULSE1_CNT_SHIFT)
1570 
1571 /* Bitfield definition for register: PULSE1CYCLE_CNT */
1572 /*
1573  * PULSE1CYCLE_CNT (RO)
1574  *
1575  */
1576 #define QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_MASK (0xFFFFFFFFUL)
1577 #define QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_SHIFT (0U)
1578 #define QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_GET(x) (((uint32_t)(x) & QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_MASK) >> QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_SHIFT)
1579 
1580 /* Bitfield definition for register: PULSE0_SNAP0 */
1581 /*
1582  * PULSE0_SNAP0 (RO)
1583  *
1584  */
1585 #define QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_MASK (0xFFFFFFFFUL)
1586 #define QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_SHIFT (0U)
1587 #define QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_MASK) >> QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_SHIFT)
1588 
1589 /* Bitfield definition for register: PULSE0CYCLE_SNAP0 */
1590 /*
1591  * PULSE0CYCLE_SNAP0 (RO)
1592  *
1593  */
1594 #define QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_MASK (0xFFFFFFFFUL)
1595 #define QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_SHIFT (0U)
1596 #define QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_MASK) >> QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_SHIFT)
1597 
1598 /* Bitfield definition for register: PULSE0_SNAP1 */
1599 /*
1600  * PULSE0_SNAP1 (RO)
1601  *
1602  */
1603 #define QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_MASK (0xFFFFFFFFUL)
1604 #define QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_SHIFT (0U)
1605 #define QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_MASK) >> QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_SHIFT)
1606 
1607 /* Bitfield definition for register: PULSE0CYCLE_SNAP1 */
1608 /*
1609  * PULSE0CYCLE_SNAP1 (RO)
1610  *
1611  */
1612 #define QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_MASK (0xFFFFFFFFUL)
1613 #define QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_SHIFT (0U)
1614 #define QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_MASK) >> QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_SHIFT)
1615 
1616 /* Bitfield definition for register: PULSE1_SNAP0 */
1617 /*
1618  * PULSE1_SNAP0 (RO)
1619  *
1620  */
1621 #define QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_MASK (0xFFFFFFFFUL)
1622 #define QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_SHIFT (0U)
1623 #define QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_MASK) >> QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_SHIFT)
1624 
1625 /* Bitfield definition for register: PULSE1CYCLE_SNAP0 */
1626 /*
1627  * PULSE1CYCLE_SNAP0 (RO)
1628  *
1629  */
1630 #define QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_MASK (0xFFFFFFFFUL)
1631 #define QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_SHIFT (0U)
1632 #define QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_MASK) >> QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_SHIFT)
1633 
1634 /* Bitfield definition for register: PULSE1_SNAP1 */
1635 /*
1636  * PULSE1_SNAP1 (RO)
1637  *
1638  */
1639 #define QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_MASK (0xFFFFFFFFUL)
1640 #define QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_SHIFT (0U)
1641 #define QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_MASK) >> QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_SHIFT)
1642 
1643 /* Bitfield definition for register: PULSE1CYCLE_SNAP1 */
1644 /*
1645  * PULSE1CYCLE_SNAP1 (RO)
1646  *
1647  */
1648 #define QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_MASK (0xFFFFFFFFUL)
1649 #define QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_SHIFT (0U)
1650 #define QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_MASK) >> QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_SHIFT)
1651 
1652 /* Bitfield definition for register: ADCX_CFG0 */
1653 /*
1654  * X_ADCSEL (RW)
1655  *
1656  */
1657 #define QEIV2_ADCX_CFG0_X_ADCSEL_MASK (0x100U)
1658 #define QEIV2_ADCX_CFG0_X_ADCSEL_SHIFT (8U)
1659 #define QEIV2_ADCX_CFG0_X_ADCSEL_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG0_X_ADCSEL_SHIFT) & QEIV2_ADCX_CFG0_X_ADCSEL_MASK)
1660 #define QEIV2_ADCX_CFG0_X_ADCSEL_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG0_X_ADCSEL_MASK) >> QEIV2_ADCX_CFG0_X_ADCSEL_SHIFT)
1661 
1662 /*
1663  * X_ADC_ENABLE (RW)
1664  *
1665  */
1666 #define QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK (0x80U)
1667 #define QEIV2_ADCX_CFG0_X_ADC_ENABLE_SHIFT (7U)
1668 #define QEIV2_ADCX_CFG0_X_ADC_ENABLE_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG0_X_ADC_ENABLE_SHIFT) & QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK)
1669 #define QEIV2_ADCX_CFG0_X_ADC_ENABLE_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK) >> QEIV2_ADCX_CFG0_X_ADC_ENABLE_SHIFT)
1670 
1671 /*
1672  * X_CHAN (RW)
1673  *
1674  */
1675 #define QEIV2_ADCX_CFG0_X_CHAN_MASK (0x1FU)
1676 #define QEIV2_ADCX_CFG0_X_CHAN_SHIFT (0U)
1677 #define QEIV2_ADCX_CFG0_X_CHAN_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG0_X_CHAN_SHIFT) & QEIV2_ADCX_CFG0_X_CHAN_MASK)
1678 #define QEIV2_ADCX_CFG0_X_CHAN_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG0_X_CHAN_MASK) >> QEIV2_ADCX_CFG0_X_CHAN_SHIFT)
1679 
1680 /* Bitfield definition for register: ADCX_CFG1 */
1681 /*
1682  * X_PARAM1 (RW)
1683  *
1684  */
1685 #define QEIV2_ADCX_CFG1_X_PARAM1_MASK (0xFFFF0000UL)
1686 #define QEIV2_ADCX_CFG1_X_PARAM1_SHIFT (16U)
1687 #define QEIV2_ADCX_CFG1_X_PARAM1_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG1_X_PARAM1_SHIFT) & QEIV2_ADCX_CFG1_X_PARAM1_MASK)
1688 #define QEIV2_ADCX_CFG1_X_PARAM1_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG1_X_PARAM1_MASK) >> QEIV2_ADCX_CFG1_X_PARAM1_SHIFT)
1689 
1690 /*
1691  * X_PARAM0 (RW)
1692  *
1693  */
1694 #define QEIV2_ADCX_CFG1_X_PARAM0_MASK (0xFFFFU)
1695 #define QEIV2_ADCX_CFG1_X_PARAM0_SHIFT (0U)
1696 #define QEIV2_ADCX_CFG1_X_PARAM0_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG1_X_PARAM0_SHIFT) & QEIV2_ADCX_CFG1_X_PARAM0_MASK)
1697 #define QEIV2_ADCX_CFG1_X_PARAM0_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG1_X_PARAM0_MASK) >> QEIV2_ADCX_CFG1_X_PARAM0_SHIFT)
1698 
1699 /* Bitfield definition for register: ADCX_CFG2 */
1700 /*
1701  * X_OFFSET (RW)
1702  *
1703  */
1704 #define QEIV2_ADCX_CFG2_X_OFFSET_MASK (0xFFFFFFFFUL)
1705 #define QEIV2_ADCX_CFG2_X_OFFSET_SHIFT (0U)
1706 #define QEIV2_ADCX_CFG2_X_OFFSET_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG2_X_OFFSET_SHIFT) & QEIV2_ADCX_CFG2_X_OFFSET_MASK)
1707 #define QEIV2_ADCX_CFG2_X_OFFSET_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG2_X_OFFSET_MASK) >> QEIV2_ADCX_CFG2_X_OFFSET_SHIFT)
1708 
1709 /* Bitfield definition for register: ADCY_CFG0 */
1710 /*
1711  * Y_ADCSEL (RW)
1712  *
1713  */
1714 #define QEIV2_ADCY_CFG0_Y_ADCSEL_MASK (0x100U)
1715 #define QEIV2_ADCY_CFG0_Y_ADCSEL_SHIFT (8U)
1716 #define QEIV2_ADCY_CFG0_Y_ADCSEL_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG0_Y_ADCSEL_SHIFT) & QEIV2_ADCY_CFG0_Y_ADCSEL_MASK)
1717 #define QEIV2_ADCY_CFG0_Y_ADCSEL_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG0_Y_ADCSEL_MASK) >> QEIV2_ADCY_CFG0_Y_ADCSEL_SHIFT)
1718 
1719 /*
1720  * Y_ADC_ENABLE (RW)
1721  *
1722  */
1723 #define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK (0x80U)
1724 #define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SHIFT (7U)
1725 #define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SHIFT) & QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK)
1726 #define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK) >> QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SHIFT)
1727 
1728 /*
1729  * Y_CHAN (RW)
1730  *
1731  */
1732 #define QEIV2_ADCY_CFG0_Y_CHAN_MASK (0x1FU)
1733 #define QEIV2_ADCY_CFG0_Y_CHAN_SHIFT (0U)
1734 #define QEIV2_ADCY_CFG0_Y_CHAN_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG0_Y_CHAN_SHIFT) & QEIV2_ADCY_CFG0_Y_CHAN_MASK)
1735 #define QEIV2_ADCY_CFG0_Y_CHAN_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG0_Y_CHAN_MASK) >> QEIV2_ADCY_CFG0_Y_CHAN_SHIFT)
1736 
1737 /* Bitfield definition for register: ADCY_CFG1 */
1738 /*
1739  * Y_PARAM1 (RW)
1740  *
1741  */
1742 #define QEIV2_ADCY_CFG1_Y_PARAM1_MASK (0xFFFF0000UL)
1743 #define QEIV2_ADCY_CFG1_Y_PARAM1_SHIFT (16U)
1744 #define QEIV2_ADCY_CFG1_Y_PARAM1_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG1_Y_PARAM1_SHIFT) & QEIV2_ADCY_CFG1_Y_PARAM1_MASK)
1745 #define QEIV2_ADCY_CFG1_Y_PARAM1_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG1_Y_PARAM1_MASK) >> QEIV2_ADCY_CFG1_Y_PARAM1_SHIFT)
1746 
1747 /*
1748  * Y_PARAM0 (RW)
1749  *
1750  */
1751 #define QEIV2_ADCY_CFG1_Y_PARAM0_MASK (0xFFFFU)
1752 #define QEIV2_ADCY_CFG1_Y_PARAM0_SHIFT (0U)
1753 #define QEIV2_ADCY_CFG1_Y_PARAM0_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG1_Y_PARAM0_SHIFT) & QEIV2_ADCY_CFG1_Y_PARAM0_MASK)
1754 #define QEIV2_ADCY_CFG1_Y_PARAM0_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG1_Y_PARAM0_MASK) >> QEIV2_ADCY_CFG1_Y_PARAM0_SHIFT)
1755 
1756 /* Bitfield definition for register: ADCY_CFG2 */
1757 /*
1758  * Y_OFFSET (RW)
1759  *
1760  */
1761 #define QEIV2_ADCY_CFG2_Y_OFFSET_MASK (0xFFFFFFFFUL)
1762 #define QEIV2_ADCY_CFG2_Y_OFFSET_SHIFT (0U)
1763 #define QEIV2_ADCY_CFG2_Y_OFFSET_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG2_Y_OFFSET_SHIFT) & QEIV2_ADCY_CFG2_Y_OFFSET_MASK)
1764 #define QEIV2_ADCY_CFG2_Y_OFFSET_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG2_Y_OFFSET_MASK) >> QEIV2_ADCY_CFG2_Y_OFFSET_SHIFT)
1765 
1766 /* Bitfield definition for register: CAL_CFG */
1767 /*
1768  * XY_DELAY (RW)
1769  *
1770  * valid x/y delay, larger than this delay will be treated as invalid data.
1771  * Default 1.25us@200MHz; max 80ms;
1772  */
1773 #define QEIV2_CAL_CFG_XY_DELAY_MASK (0xFFFFFFUL)
1774 #define QEIV2_CAL_CFG_XY_DELAY_SHIFT (0U)
1775 #define QEIV2_CAL_CFG_XY_DELAY_SET(x) (((uint32_t)(x) << QEIV2_CAL_CFG_XY_DELAY_SHIFT) & QEIV2_CAL_CFG_XY_DELAY_MASK)
1776 #define QEIV2_CAL_CFG_XY_DELAY_GET(x) (((uint32_t)(x) & QEIV2_CAL_CFG_XY_DELAY_MASK) >> QEIV2_CAL_CFG_XY_DELAY_SHIFT)
1777 
1778 /* Bitfield definition for register: PHASE_PARAM */
1779 /*
1780  * PHASE_PARAM (RW)
1781  *
1782  */
1783 #define QEIV2_PHASE_PARAM_PHASE_PARAM_MASK (0xFFFFFFFFUL)
1784 #define QEIV2_PHASE_PARAM_PHASE_PARAM_SHIFT (0U)
1785 #define QEIV2_PHASE_PARAM_PHASE_PARAM_SET(x) (((uint32_t)(x) << QEIV2_PHASE_PARAM_PHASE_PARAM_SHIFT) & QEIV2_PHASE_PARAM_PHASE_PARAM_MASK)
1786 #define QEIV2_PHASE_PARAM_PHASE_PARAM_GET(x) (((uint32_t)(x) & QEIV2_PHASE_PARAM_PHASE_PARAM_MASK) >> QEIV2_PHASE_PARAM_PHASE_PARAM_SHIFT)
1787 
1788 /* Bitfield definition for register: ANGLE_ADJ */
1789 /*
1790  * ANGLE_ADJ (RW)
1791  *
1792  */
1793 #define QEIV2_ANGLE_ADJ_ANGLE_ADJ_MASK (0xFFFFFFFFUL)
1794 #define QEIV2_ANGLE_ADJ_ANGLE_ADJ_SHIFT (0U)
1795 #define QEIV2_ANGLE_ADJ_ANGLE_ADJ_SET(x) (((uint32_t)(x) << QEIV2_ANGLE_ADJ_ANGLE_ADJ_SHIFT) & QEIV2_ANGLE_ADJ_ANGLE_ADJ_MASK)
1796 #define QEIV2_ANGLE_ADJ_ANGLE_ADJ_GET(x) (((uint32_t)(x) & QEIV2_ANGLE_ADJ_ANGLE_ADJ_MASK) >> QEIV2_ANGLE_ADJ_ANGLE_ADJ_SHIFT)
1797 
1798 /* Bitfield definition for register: POS_THRESHOLD */
1799 /*
1800  * POS_THRESHOLD (RW)
1801  *
1802  */
1803 #define QEIV2_POS_THRESHOLD_POS_THRESHOLD_MASK (0xFFFFFFFFUL)
1804 #define QEIV2_POS_THRESHOLD_POS_THRESHOLD_SHIFT (0U)
1805 #define QEIV2_POS_THRESHOLD_POS_THRESHOLD_SET(x) (((uint32_t)(x) << QEIV2_POS_THRESHOLD_POS_THRESHOLD_SHIFT) & QEIV2_POS_THRESHOLD_POS_THRESHOLD_MASK)
1806 #define QEIV2_POS_THRESHOLD_POS_THRESHOLD_GET(x) (((uint32_t)(x) & QEIV2_POS_THRESHOLD_POS_THRESHOLD_MASK) >> QEIV2_POS_THRESHOLD_POS_THRESHOLD_SHIFT)
1807 
1808 /* Bitfield definition for register array: UVW_POS */
1809 /*
1810  * UVW_POS0 (RW)
1811  *
1812  */
1813 #define QEIV2_UVW_POS_UVW_POS0_MASK (0xFFFFFFFFUL)
1814 #define QEIV2_UVW_POS_UVW_POS0_SHIFT (0U)
1815 #define QEIV2_UVW_POS_UVW_POS0_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_UVW_POS0_SHIFT) & QEIV2_UVW_POS_UVW_POS0_MASK)
1816 #define QEIV2_UVW_POS_UVW_POS0_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_UVW_POS0_MASK) >> QEIV2_UVW_POS_UVW_POS0_SHIFT)
1817 
1818 /* Bitfield definition for register array: UVW_POS_CFG */
1819 /*
1820  * POS_EN (RW)
1821  *
1822  */
1823 #define QEIV2_UVW_POS_CFG_POS_EN_MASK (0x40U)
1824 #define QEIV2_UVW_POS_CFG_POS_EN_SHIFT (6U)
1825 #define QEIV2_UVW_POS_CFG_POS_EN_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_CFG_POS_EN_SHIFT) & QEIV2_UVW_POS_CFG_POS_EN_MASK)
1826 #define QEIV2_UVW_POS_CFG_POS_EN_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_CFG_POS_EN_MASK) >> QEIV2_UVW_POS_CFG_POS_EN_SHIFT)
1827 
1828 /*
1829  * U_POS_SEL (RW)
1830  *
1831  */
1832 #define QEIV2_UVW_POS_CFG_U_POS_SEL_MASK (0x30U)
1833 #define QEIV2_UVW_POS_CFG_U_POS_SEL_SHIFT (4U)
1834 #define QEIV2_UVW_POS_CFG_U_POS_SEL_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_CFG_U_POS_SEL_SHIFT) & QEIV2_UVW_POS_CFG_U_POS_SEL_MASK)
1835 #define QEIV2_UVW_POS_CFG_U_POS_SEL_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_CFG_U_POS_SEL_MASK) >> QEIV2_UVW_POS_CFG_U_POS_SEL_SHIFT)
1836 
1837 /*
1838  * V_POS_SEL (RW)
1839  *
1840  */
1841 #define QEIV2_UVW_POS_CFG_V_POS_SEL_MASK (0xCU)
1842 #define QEIV2_UVW_POS_CFG_V_POS_SEL_SHIFT (2U)
1843 #define QEIV2_UVW_POS_CFG_V_POS_SEL_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_CFG_V_POS_SEL_SHIFT) & QEIV2_UVW_POS_CFG_V_POS_SEL_MASK)
1844 #define QEIV2_UVW_POS_CFG_V_POS_SEL_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_CFG_V_POS_SEL_MASK) >> QEIV2_UVW_POS_CFG_V_POS_SEL_SHIFT)
1845 
1846 /*
1847  * W_POS_SEL (RW)
1848  *
1849  */
1850 #define QEIV2_UVW_POS_CFG_W_POS_SEL_MASK (0x3U)
1851 #define QEIV2_UVW_POS_CFG_W_POS_SEL_SHIFT (0U)
1852 #define QEIV2_UVW_POS_CFG_W_POS_SEL_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_CFG_W_POS_SEL_SHIFT) & QEIV2_UVW_POS_CFG_W_POS_SEL_MASK)
1853 #define QEIV2_UVW_POS_CFG_W_POS_SEL_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_CFG_W_POS_SEL_MASK) >> QEIV2_UVW_POS_CFG_W_POS_SEL_SHIFT)
1854 
1855 /* Bitfield definition for register: PHASE_CNT */
1856 /*
1857  * PHASE_CNT (RW)
1858  *
1859  */
1860 #define QEIV2_PHASE_CNT_PHASE_CNT_MASK (0xFFFFFFFFUL)
1861 #define QEIV2_PHASE_CNT_PHASE_CNT_SHIFT (0U)
1862 #define QEIV2_PHASE_CNT_PHASE_CNT_SET(x) (((uint32_t)(x) << QEIV2_PHASE_CNT_PHASE_CNT_SHIFT) & QEIV2_PHASE_CNT_PHASE_CNT_MASK)
1863 #define QEIV2_PHASE_CNT_PHASE_CNT_GET(x) (((uint32_t)(x) & QEIV2_PHASE_CNT_PHASE_CNT_MASK) >> QEIV2_PHASE_CNT_PHASE_CNT_SHIFT)
1864 
1865 /* Bitfield definition for register: PHASE_UPDATE */
1866 /*
1867  * INC (WO)
1868  *
1869  * set to add value to phase_cnt
1870  */
1871 #define QEIV2_PHASE_UPDATE_INC_MASK (0x80000000UL)
1872 #define QEIV2_PHASE_UPDATE_INC_SHIFT (31U)
1873 #define QEIV2_PHASE_UPDATE_INC_SET(x) (((uint32_t)(x) << QEIV2_PHASE_UPDATE_INC_SHIFT) & QEIV2_PHASE_UPDATE_INC_MASK)
1874 #define QEIV2_PHASE_UPDATE_INC_GET(x) (((uint32_t)(x) & QEIV2_PHASE_UPDATE_INC_MASK) >> QEIV2_PHASE_UPDATE_INC_SHIFT)
1875 
1876 /*
1877  * DEC (WO)
1878  *
1879  * set to minus value from phase_cnt(set inc and dec same time willl act inc)
1880  */
1881 #define QEIV2_PHASE_UPDATE_DEC_MASK (0x40000000UL)
1882 #define QEIV2_PHASE_UPDATE_DEC_SHIFT (30U)
1883 #define QEIV2_PHASE_UPDATE_DEC_SET(x) (((uint32_t)(x) << QEIV2_PHASE_UPDATE_DEC_SHIFT) & QEIV2_PHASE_UPDATE_DEC_MASK)
1884 #define QEIV2_PHASE_UPDATE_DEC_GET(x) (((uint32_t)(x) & QEIV2_PHASE_UPDATE_DEC_MASK) >> QEIV2_PHASE_UPDATE_DEC_SHIFT)
1885 
1886 /*
1887  * VALUE (WO)
1888  *
1889  * value to be added or minus from phase_cnt. only valid when inc or dec is set in one 32bit write operation
1890  */
1891 #define QEIV2_PHASE_UPDATE_VALUE_MASK (0x3FFFFFFFUL)
1892 #define QEIV2_PHASE_UPDATE_VALUE_SHIFT (0U)
1893 #define QEIV2_PHASE_UPDATE_VALUE_SET(x) (((uint32_t)(x) << QEIV2_PHASE_UPDATE_VALUE_SHIFT) & QEIV2_PHASE_UPDATE_VALUE_MASK)
1894 #define QEIV2_PHASE_UPDATE_VALUE_GET(x) (((uint32_t)(x) & QEIV2_PHASE_UPDATE_VALUE_MASK) >> QEIV2_PHASE_UPDATE_VALUE_SHIFT)
1895 
1896 /* Bitfield definition for register: POSITION */
1897 /*
1898  * POSITION (RW)
1899  *
1900  */
1901 #define QEIV2_POSITION_POSITION_MASK (0xFFFFFFFFUL)
1902 #define QEIV2_POSITION_POSITION_SHIFT (0U)
1903 #define QEIV2_POSITION_POSITION_SET(x) (((uint32_t)(x) << QEIV2_POSITION_POSITION_SHIFT) & QEIV2_POSITION_POSITION_MASK)
1904 #define QEIV2_POSITION_POSITION_GET(x) (((uint32_t)(x) & QEIV2_POSITION_POSITION_MASK) >> QEIV2_POSITION_POSITION_SHIFT)
1905 
1906 /* Bitfield definition for register: POSITION_UPDATE */
1907 /*
1908  * INC (WO)
1909  *
1910  * set to add value to position
1911  */
1912 #define QEIV2_POSITION_UPDATE_INC_MASK (0x80000000UL)
1913 #define QEIV2_POSITION_UPDATE_INC_SHIFT (31U)
1914 #define QEIV2_POSITION_UPDATE_INC_SET(x) (((uint32_t)(x) << QEIV2_POSITION_UPDATE_INC_SHIFT) & QEIV2_POSITION_UPDATE_INC_MASK)
1915 #define QEIV2_POSITION_UPDATE_INC_GET(x) (((uint32_t)(x) & QEIV2_POSITION_UPDATE_INC_MASK) >> QEIV2_POSITION_UPDATE_INC_SHIFT)
1916 
1917 /*
1918  * DEC (WO)
1919  *
1920  * set to minus value from position(set inc and dec same time willl act inc)
1921  */
1922 #define QEIV2_POSITION_UPDATE_DEC_MASK (0x40000000UL)
1923 #define QEIV2_POSITION_UPDATE_DEC_SHIFT (30U)
1924 #define QEIV2_POSITION_UPDATE_DEC_SET(x) (((uint32_t)(x) << QEIV2_POSITION_UPDATE_DEC_SHIFT) & QEIV2_POSITION_UPDATE_DEC_MASK)
1925 #define QEIV2_POSITION_UPDATE_DEC_GET(x) (((uint32_t)(x) & QEIV2_POSITION_UPDATE_DEC_MASK) >> QEIV2_POSITION_UPDATE_DEC_SHIFT)
1926 
1927 /*
1928  * VALUE (WO)
1929  *
1930  * value to be added or minus from position. only valid when inc or dec is set in one 32bit write operation
1931  */
1932 #define QEIV2_POSITION_UPDATE_VALUE_MASK (0x3FFFFFFFUL)
1933 #define QEIV2_POSITION_UPDATE_VALUE_SHIFT (0U)
1934 #define QEIV2_POSITION_UPDATE_VALUE_SET(x) (((uint32_t)(x) << QEIV2_POSITION_UPDATE_VALUE_SHIFT) & QEIV2_POSITION_UPDATE_VALUE_MASK)
1935 #define QEIV2_POSITION_UPDATE_VALUE_GET(x) (((uint32_t)(x) & QEIV2_POSITION_UPDATE_VALUE_MASK) >> QEIV2_POSITION_UPDATE_VALUE_SHIFT)
1936 
1937 /* Bitfield definition for register: ANGLE */
1938 /*
1939  * ANGLE (RO)
1940  *
1941  */
1942 #define QEIV2_ANGLE_ANGLE_MASK (0xFFFFFFFFUL)
1943 #define QEIV2_ANGLE_ANGLE_SHIFT (0U)
1944 #define QEIV2_ANGLE_ANGLE_GET(x) (((uint32_t)(x) & QEIV2_ANGLE_ANGLE_MASK) >> QEIV2_ANGLE_ANGLE_SHIFT)
1945 
1946 /* Bitfield definition for register: POS_TIMEOUT */
1947 /*
1948  * ENABLE (RW)
1949  *
1950  * enable position timeout feature, if timeout, send valid again
1951  */
1952 #define QEIV2_POS_TIMEOUT_ENABLE_MASK (0x80000000UL)
1953 #define QEIV2_POS_TIMEOUT_ENABLE_SHIFT (31U)
1954 #define QEIV2_POS_TIMEOUT_ENABLE_SET(x) (((uint32_t)(x) << QEIV2_POS_TIMEOUT_ENABLE_SHIFT) & QEIV2_POS_TIMEOUT_ENABLE_MASK)
1955 #define QEIV2_POS_TIMEOUT_ENABLE_GET(x) (((uint32_t)(x) & QEIV2_POS_TIMEOUT_ENABLE_MASK) >> QEIV2_POS_TIMEOUT_ENABLE_SHIFT)
1956 
1957 /*
1958  * TIMEOUT (RW)
1959  *
1960  * postion timeout value
1961  */
1962 #define QEIV2_POS_TIMEOUT_TIMEOUT_MASK (0x7FFFFFFFUL)
1963 #define QEIV2_POS_TIMEOUT_TIMEOUT_SHIFT (0U)
1964 #define QEIV2_POS_TIMEOUT_TIMEOUT_SET(x) (((uint32_t)(x) << QEIV2_POS_TIMEOUT_TIMEOUT_SHIFT) & QEIV2_POS_TIMEOUT_TIMEOUT_MASK)
1965 #define QEIV2_POS_TIMEOUT_TIMEOUT_GET(x) (((uint32_t)(x) & QEIV2_POS_TIMEOUT_TIMEOUT_MASK) >> QEIV2_POS_TIMEOUT_TIMEOUT_SHIFT)
1966 
1967 
1968 
1969 /* COUNT register group index macro definition */
1970 #define QEIV2_COUNT_CURRENT (0UL)
1971 #define QEIV2_COUNT_READ (1UL)
1972 #define QEIV2_COUNT_SNAP0 (2UL)
1973 #define QEIV2_COUNT_SNAP1 (3UL)
1974 
1975 /* FILT_CFG register group index macro definition */
1976 #define QEIV2_FILT_CFG_FILT_CFG_A (0UL)
1977 #define QEIV2_FILT_CFG_FILT_CFG_B (1UL)
1978 #define QEIV2_FILT_CFG_FILT_CFG_Z (2UL)
1979 #define QEIV2_FILT_CFG_FILT_CFG_H (3UL)
1980 #define QEIV2_FILT_CFG_FILT_CFG_H2 (4UL)
1981 #define QEIV2_FILT_CFG_FILT_CFG_F (5UL)
1982 
1983 /* UVW_POS register group index macro definition */
1984 #define QEIV2_UVW_POS_UVW_POS0 (0UL)
1985 #define QEIV2_UVW_POS_UVW_POS1 (1UL)
1986 #define QEIV2_UVW_POS_UVW_POS2 (2UL)
1987 #define QEIV2_UVW_POS_UVW_POS3 (3UL)
1988 #define QEIV2_UVW_POS_UVW_POS4 (4UL)
1989 #define QEIV2_UVW_POS_UVW_POS5 (5UL)
1990 
1991 /* UVW_POS_CFG register group index macro definition */
1992 #define QEIV2_UVW_POS_CFG_UVW_POS0_CFG (0UL)
1993 #define QEIV2_UVW_POS_CFG_UVW_POS1_CFG (1UL)
1994 #define QEIV2_UVW_POS_CFG_UVW_POS2_CFG (2UL)
1995 #define QEIV2_UVW_POS_CFG_UVW_POS3_CFG (3UL)
1996 #define QEIV2_UVW_POS_CFG_UVW_POS4_CFG (4UL)
1997 #define QEIV2_UVW_POS_CFG_UVW_POS5_CFG (5UL)
1998 
1999 
2000 #endif /* HPM_QEIV2_H */
QEIV2_Type
Definition: hpm_qeiv2_regs.h:12