hpm_rdc_drv.h

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/*
 * Copyright (c) 2023 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
 */
 
#ifndef HPM_RDC_DRV_H
#define HPM_RDC_DRV_H
 
#include "hpm_common.h"
#include "hpm_rdc_regs.h"
#include "hpm_soc_feature.h"
 
#ifdef __cplusplus
extern "C" {
#endif
typedef enum rdc_output_precision {
    rdc_output_precision_4_point = 0,
    rdc_output_precision_8_point = 1,
    rdc_output_precision_16_point = 2,
    rdc_output_precision_32_point = 3,
    rdc_output_precision_64_point = 4,
    rdc_output_precision_128_point = 5,
    rdc_output_precision_256_point = 6,
    rdc_output_precision_512_point = 7,
    rdc_output_precision_1024_point = 8,
} rdc_output_precision_t;
 
typedef enum rdc_output_pwm_period {
    rdc_output_pwm_period_1_sample = 0,
    rdc_output_pwm_period_2_sample,
    rdc_output_pwm_period_3_sample,
    rdc_output_pwm_period_4_sample,
    rdc_output_pwm_period_5_sample,
    rdc_output_pwm_period_6_sample,
    rdc_output_pwm_period_7_sample,
    rdc_output_pwm_period_8_sample,
    rdc_output_pwm_period_9_sample,
    rdc_output_pwm_period_10_sample,
    rdc_output_pwm_period_11_sample,
    rdc_output_pwm_period_12_sample,
    rdc_output_pwm_period_13_sample,
    rdc_output_pwm_period_14_sample,
    rdc_output_pwm_period_15_sample,
    rdc_output_pwm_period_16_sample,
} rdc_output_pwm_period_t;
 
 
 
typedef enum rdc_output_mode {
    rdc_output_dac,
    rdc_output_pwm
} rdc_output_mode_t;
 
typedef enum rdc_sync_out_src {
    rdc_sync_out_exc_0_ph = RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SET(0),
    rdc_sync_out_exc_90_ph = RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SET(1),
    rdc_sync_out_exc_180_ph = RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SET(2),
    rdc_sync_out_exc_270_ph = RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SET(3),
    rdc_sync_out_max = RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_MASK,
    rdc_sync_out_min = RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_MASK,
} rdc_sync_out_src_t;
 
typedef enum rdc_rectify_signal {
    rdc_rectify_signal_exc_0_ph = 0,
    rdc_rectify_signal_exc_90_ph = 1,
    rdc_rectify_signal_exc_180_ph = 2,
    rdc_rectify_signal_exc_270_ph = 3,
    rdc_rectify_signal_external = 4,
    rdc_rectify_signal_external_invert = 5,
} rdc_rectify_signal_t;
 
typedef enum rdc_acc_stamp_time {
    rdc_acc_stamp_end_of_acc = 0,   
    rdc_acc_stamp_start_of_acc = 1, 
    rdc_acc_stamp_center_of_acc = 2,    
} rdc_acc_stamp_time_t;
 
typedef enum rdc_output_trig_chn {
    trigger_out_0 = 0,
    trigger_out_1 = 1
} rdc_output_trig_chn_t;
 
 
typedef enum rdc_input_acc_chn {
    rdc_acc_chn_i = 0,
    rdc_acc_chn_q = 1
} rdc_input_acc_chn_t;
 
typedef enum rdc_interrupt_stat {
    acc_vld_i_stat = RDC_INT_EN_ACC_VLD_I_EN_MASK,
    acc_vld_q_stat = RDC_INT_EN_ACC_VLD_Q_EN_MASK,
    rising_delay_i_stat = RDC_INT_EN_RISING_DELAY_I_EN_MASK,
    falling_delay_i_stat = RDC_INT_EN_FALLING_DELAY_I_EN_MASK,
    rising_delay_q_stat = RDC_INT_EN_RISING_DELAY_Q_EN_MASK,
    falling_delay_q_stat = RDC_INT_EN_FALLING_DELAY_Q_EN_MASK,
    sample_rising_i_stat = RDC_INT_EN_SAMPLE_RISING_I_EN_MASK,
    sample_falling_i_stat = RDC_INT_EN_SAMPLE_FALLING_I_EN_MASK,
    sample_rising_q_stat = RDC_INT_EN_SAMPLE_RISING_Q_EN_MASK,
    sample_falling_q_stat = RDC_INT_EN_SAMPLE_FALLING_Q_EN_MASK,
    acc_vld_i_ovh_stat = RDC_INT_EN_ACC_VLD_I_OVH_EN_MASK,
    acc_vld_q_ovh_stat = RDC_INT_EN_ACC_VLD_Q_OVH_EN_MASK,
    acc_vld_i_ovl_stat = RDC_INT_EN_ACC_VLD_I_OVL_EN_MASK,
    acc_vld_q_ovl_stat = RDC_INT_EN_ACC_VLD_Q_OVL_EN_MASK,
    acc_amp_ovh_stat = RDC_INT_EN_ACC_AMP_OVH_EN_MASK,
    acc_amp_ovl_stat = RDC_INT_EN_ACC_AMP_OVL_EN_MASK,
} rdc_interrupt_stat_t;
 
typedef struct rdc_output_cfg {
    rdc_output_mode_t mode; 
    uint32_t excitation_period_cycle;   
    rdc_output_precision_t excitation_precision;    
    rdc_output_pwm_period_t pwm_period; 
    bool output_swap;   
    int32_t amp_offset; 
    uint16_t amp_man;   
    uint16_t amp_exp;   
    bool pwm_dither_enable; 
    bool pwm_exc_p_low_active;  
    bool pwm_exc_n_low_active;  
    bool trig_by_hw;    
    uint32_t hw_trig_delay; 
    uint8_t dac_chn_i_sel;  
    uint8_t dac_chn_q_sel;  
    uint8_t pwm_deadzone_p; 
    uint8_t pwm_deadzone_n; 
} rdc_output_cfg_t;
 
 
typedef struct rdc_input_cfg {
    rdc_rectify_signal_t rectify_signal_sel;    
    uint8_t acc_cycle_len;  
    rdc_acc_stamp_time_t acc_stamp; 
    uint32_t acc_input_chn_i;   
    uint32_t acc_input_port_i;  
    uint32_t acc_input_chn_q;   
    uint32_t acc_input_port_q;  
} rdc_input_cfg_t;
 
typedef struct rdc_acc_cfg {
    struct {
        uint16_t continue_edge_num: 3;  
        uint16_t edge_distance: 6;  
    };
    uint8_t right_shift_without_sign;   
    bool error_data_remove; 
    uint32_t exc_carrier_period;    
    uint32_t sync_delay_i;  
    uint32_t sync_delay_q;  
    uint32_t amp_max;   
    uint32_t amp_min;   
} rdc_acc_cfg_t;
 
void rdc_output_config(RDC_Type *ptr, rdc_output_cfg_t *cfg);
 
void rdc_input_config(RDC_Type *ptr, rdc_input_cfg_t *cfg);
 
static inline void rdc_set_acc_len(RDC_Type *ptr, uint8_t len)
{
    ptr->RDC_CTL = (ptr->RDC_CTL & (~RDC_RDC_CTL_ACC_LEN_MASK))
                    | RDC_RDC_CTL_ACC_LEN_SET(len);
}
 
static inline void rdc_acc_enable(RDC_Type *ptr)
{
    ptr->RDC_CTL |= RDC_RDC_CTL_ACC_EN_MASK;
}
 
static inline void rdc_acc_disable(RDC_Type *ptr)
{
    ptr->RDC_CTL &= ~RDC_RDC_CTL_ACC_EN_MASK;
}
 
uint32_t rdc_get_acc_avl(RDC_Type *ptr, rdc_input_acc_chn_t chn);
 
void rdc_output_trig_offset_config(RDC_Type *ptr, rdc_output_trig_chn_t chn, int32_t offset);
 
void rdc_output_trig_enable(RDC_Type *ptr, rdc_output_trig_chn_t chn);
 
void rdc_output_trig_disable(RDC_Type *ptr, rdc_output_trig_chn_t chn);
 
static inline void rdc_sync_output_trig_adc_cfg(RDC_Type *ptr, rdc_sync_out_src_t sel)
{
    ptr->SYNC_OUT_CTRL = sel;
}
 
static inline void rdc_exc_enable(RDC_Type *ptr)
{
    ptr->RDC_CTL |= RDC_RDC_CTL_EXC_EN_MASK;
}
 
static inline void rdc_exc_disable(RDC_Type *ptr)
{
    ptr->RDC_CTL &= ~RDC_RDC_CTL_EXC_EN_MASK;
}
 
static inline void rdc_output_trig_sw(RDC_Type *ptr)
{
    ptr->RDC_CTL |= RDC_RDC_CTL_EXC_START_MASK;
}
 
int32_t rdc_get_i_maxval(RDC_Type *ptr);
 
static inline void rdc_clear_i_maxval(RDC_Type *ptr)
{
    ptr->MAX_I = 0;
}
 
int32_t rdc_get_i_minval(RDC_Type *ptr);
 
static inline void rdc_clear_i_minval(RDC_Type *ptr)
{
    ptr->MIN_I = 0;
}
 
void rdc_set_acc_sync_delay(RDC_Type *ptr, rdc_input_acc_chn_t chn, uint32_t delay);
 
static inline uint32_t rdc_get_sync_output_delay(RDC_Type *ptr)
{
    return RDC_SYNC_OUT_CTRL_PWM_OUT_DLY_GET(ptr->SYNC_OUT_CTRL);
}
 
int32_t rdc_get_q_maxval(RDC_Type *ptr);
 
static inline void rdc_clear_q_maxval(RDC_Type *ptr)
{
    ptr->MAX_Q = 0;
}
 
int32_t rdc_get_q_minval(RDC_Type *ptr);
 
static inline void rdc_clear_q_minval(RDC_Type *ptr)
{
    ptr->MIN_Q = 0;
}
 
void rdc_set_edge_detection_offset(RDC_Type *ptr, rdc_input_acc_chn_t chn, int32_t offset);
 
void rdc_set_acc_config(RDC_Type *ptr, rdc_acc_cfg_t *cfg);
 
static inline uint32_t rdc_get_rise_delay_i(RDC_Type *ptr)
{
    return RDC_RISE_DELAY_I_RISE_DELAY_GET(ptr->RISE_DELAY_I);
}
 
static inline uint32_t rdc_get_fall_delay_i(RDC_Type *ptr)
{
    return RDC_FALL_DELAY_I_FALL_DELAY_GET(ptr->FALL_DELAY_I);
}
 
static inline uint32_t rdc_get_sample_rise_i(RDC_Type *ptr)
{
    return RDC_SAMPLE_RISE_I_VALUE_GET(ptr->SAMPLE_RISE_I);
}
 
static inline uint32_t rdc_get_sample_fall_i(RDC_Type *ptr)
{
    return RDC_SAMPLE_FALL_I_VALUE_GET(ptr->SAMPLE_FALL_I);
}
 
static inline uint32_t rdc_get_acc_cnt_positive_i(RDC_Type *ptr)
{
    return RDC_ACC_CNT_I_CNT_POS_GET(ptr->ACC_CNT_I);
}
 
static inline uint32_t rdc_get_acc_cnt_negative_i(RDC_Type *ptr)
{
    return RDC_ACC_CNT_I_CNT_POS_GET(ptr->ACC_CNT_I);
}
 
static inline uint32_t rdc_get_sign_cnt_poitive_i(RDC_Type *ptr)
{
    return RDC_SIGN_CNT_I_CNT_POS_GET(ptr->SIGN_CNT_I);
}
 
static inline uint32_t rdc_get_sign_cnt_negative_i(RDC_Type *ptr)
{
    return RDC_SIGN_CNT_I_CNT_NEG_GET(ptr->SIGN_CNT_I);
}
 
static inline uint32_t rdc_get_rise_delay_q(RDC_Type *ptr)
{
    return RDC_RISE_DELAY_Q_RISE_DELAY_GET(ptr->RISE_DELAY_Q);
}
 
static inline uint32_t rdc_get_fall_delay_q(RDC_Type *ptr)
{
    return RDC_FALL_DELAY_Q_FALL_DELAY_GET(ptr->FALL_DELAY_Q);
}
 
static inline uint32_t rdc_get_sample_rise_q(RDC_Type *ptr)
{
    return RDC_SAMPLE_RISE_Q_VALUE_GET(ptr->SAMPLE_RISE_Q);
}
 
static inline uint32_t rdc_get_sample_fall_q(RDC_Type *ptr)
{
    return RDC_SAMPLE_FALL_Q_VALUE_GET(ptr->SAMPLE_FALL_Q);
}
 
static inline uint32_t rdc_get_acc_cnt_positive_q(RDC_Type *ptr)
{
    return RDC_ACC_CNT_Q_CNT_POS_GET(ptr->ACC_CNT_Q);
}
 
static inline uint32_t rdc_get_acc_cnt_negative_q(RDC_Type *ptr)
{
    return RDC_ACC_CNT_Q_CNT_POS_GET(ptr->ACC_CNT_Q);
}
 
static inline uint32_t rdc_get_sign_cnt_poitive_q(RDC_Type *ptr)
{
    return RDC_SIGN_CNT_Q_CNT_POS_GET(ptr->SIGN_CNT_Q);
}
 
static inline uint32_t rdc_get_sign_cnt_negative_q(RDC_Type *ptr)
{
    return RDC_SIGN_CNT_Q_CNT_NEG_GET(ptr->SIGN_CNT_Q);
}
 
static inline void rdc_interrupt_config(RDC_Type *ptr, uint32_t status)
{
    ptr->INT_EN |= status;
}
 
static inline void rdc_interrupt_reset_config(RDC_Type *ptr, uint32_t status)
{
    ptr->INT_EN &= ~status;
}
 
static inline void rdc_interrupt_enable(RDC_Type *ptr)
{
    ptr->INT_EN |= RDC_INT_EN_INT_EN_MASK;
}
 
static inline void rdc_interrupt_disable(RDC_Type *ptr)
{
    ptr->INT_EN &= ~RDC_INT_EN_INT_EN_MASK;
}
 
static inline void rdc_interrupt_clear_flag_bits(RDC_Type *ptr, uint32_t mask)
{
    ptr->ADC_INT_STATE &= mask;
}
 
static inline uint32_t get_interrupt_status(RDC_Type *ptr)
{
    return ptr->ADC_INT_STATE;
}
 
#ifdef __cplusplus
}
#endif
 
#endif /* HPM_ADC12_DRV_H */