HPM SDK
HPMicro Software Development Kit
hpm_sei_regs.h
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1 /*
2  * Copyright (c) 2021-2023 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_SEI_H
10 #define HPM_SEI_H
11 
12 typedef struct {
13  struct {
14  struct {
15  __RW uint32_t CTRL; /* 0x0: Engine control register */
16  __RW uint32_t PTR_CFG; /* 0x4: Pointer configuration register */
17  __RW uint32_t WDG_CFG; /* 0x8: Watch dog configuration register */
18  __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */
19  __R uint32_t EXE_STA; /* 0x10: Execution status */
20  __R uint32_t EXE_PTR; /* 0x14: Execution pointer */
21  __R uint32_t EXE_INST; /* 0x18: Execution instruction */
22  __R uint32_t WDG_STA; /* 0x1C: Watch dog status */
23  } ENGINE;
24  struct {
25  __RW uint32_t CTRL; /* 0x20: Transceiver control register */
26  __RW uint32_t TYPE_CFG; /* 0x24: Transceiver configuration register */
27  __RW uint32_t BAUD_CFG; /* 0x28: Transceiver baud rate register */
28  __RW uint32_t DATA_CFG; /* 0x2C: Transceiver data timing configuration */
29  __RW uint32_t CLK_CFG; /* 0x30: Transceiver clock timing configuration */
30  __R uint8_t RESERVED0[4]; /* 0x34 - 0x37: Reserved */
31  __R uint32_t PIN; /* 0x38: Transceiver pin status */
32  __R uint32_t STATE; /* 0x3C: FSM of asynchronous */
33  } XCVR;
34  struct {
35  __RW uint32_t IN_CFG; /* 0x40: Trigger input configuration */
36  __W uint32_t SW; /* 0x44: Software trigger */
37  __RW uint32_t PRD_CFG; /* 0x48: Period trigger configuration */
38  __RW uint32_t PRD; /* 0x4C: Trigger period */
39  __RW uint32_t OUT_CFG; /* 0x50: Trigger output configuration */
40  __R uint8_t RESERVED0[12]; /* 0x54 - 0x5F: Reserved */
41  __R uint32_t PRD_STS; /* 0x60: Period trigger status */
42  __R uint32_t PRD_CNT; /* 0x64: Period trigger counter */
43  __R uint8_t RESERVED1[24]; /* 0x68 - 0x7F: Reserved */
44  } TRG;
45  struct {
46  __RW uint32_t CMD[4]; /* 0x80 - 0x8C: Trigger command */
47  __R uint8_t RESERVED0[16]; /* 0x90 - 0x9F: Reserved */
48  __R uint32_t TIME[4]; /* 0xA0 - 0xAC: Trigger Time */
49  __R uint8_t RESERVED1[16]; /* 0xB0 - 0xBF: Reserved */
50  } TRG_TABLE;
51  struct {
52  __RW uint32_t MODE; /* 0xC0: command register mode */
53  __RW uint32_t IDX; /* 0xC4: command register configuration */
54  __RW uint32_t GOLD; /* 0xC8: Command gold value */
55  __RW uint32_t CRCINIT; /* 0xCC: Command Initial value */
56  __RW uint32_t CRCPOLY; /* 0xD0: Command CRC polymial */
57  __R uint8_t RESERVED0[12]; /* 0xD4 - 0xDF: Reserved */
58  __RW uint32_t CMD; /* 0xE0: command */
59  __RW uint32_t SET; /* 0xE4: command bit set register */
60  __RW uint32_t CLR; /* 0xE8: command bit clear register */
61  __RW uint32_t INV; /* 0xEC: command bit invert register */
62  __R uint32_t IN; /* 0xF0: Commad input */
63  __R uint32_t OUT; /* 0xF4: Command output */
64  __RW uint32_t STS; /* 0xF8: Command status */
65  __R uint8_t RESERVED1[4]; /* 0xFC - 0xFF: Reserved */
66  } CMD;
67  struct {
68  __RW uint32_t MIN; /* 0x100: command start value */
69  __RW uint32_t MAX; /* 0x104: command end value */
70  __RW uint32_t MSK; /* 0x108: command compare bit enable */
71  __R uint8_t RESERVED0[4]; /* 0x10C - 0x10F: Reserved */
72  __RW uint32_t PTA; /* 0x110: command pointer 0 - 3 */
73  __RW uint32_t PTB; /* 0x114: command pointer 4 - 7 */
74  __RW uint32_t PTC; /* 0x118: command pointer 8 - 11 */
75  __RW uint32_t PTD; /* 0x11C: command pointer 12 - 15 */
76  } CMD_TABLE[8];
77  struct {
78  __RW uint32_t TRAN[4]; /* 0x200 - 0x20C: Latch state transition configuration */
79  __RW uint32_t CFG; /* 0x210: Latch configuration */
80  __R uint8_t RESERVED0[4]; /* 0x214 - 0x217: Reserved */
81  __R uint32_t TIME; /* 0x218: Latch time */
82  __R uint32_t STS; /* 0x21C: Latch status */
83  } LATCH[4];
84  struct {
85  __RW uint32_t SMP_EN; /* 0x280: Sample selection register */
86  __RW uint32_t SMP_CFG; /* 0x284: Sample configuration */
87  __RW uint32_t SMP_DAT; /* 0x288: Sample data */
88  __R uint8_t RESERVED0[4]; /* 0x28C - 0x28F: Reserved */
89  __RW uint32_t SMP_POS; /* 0x290: Sample override position */
90  __RW uint32_t SMP_REV; /* 0x294: Sample override revolution */
91  __RW uint32_t SMP_SPD; /* 0x298: Sample override speed */
92  __RW uint32_t SMP_ACC; /* 0x29C: Sample override accelerate */
93  __RW uint32_t UPD_EN; /* 0x2A0: Update configuration */
94  __RW uint32_t UPD_CFG; /* 0x2A4: Update configuration */
95  __RW uint32_t UPD_DAT; /* 0x2A8: Update data */
96  __RW uint32_t UPD_TIME; /* 0x2AC: Update overide time */
97  __RW uint32_t UPD_POS; /* 0x2B0: Update override position */
98  __RW uint32_t UPD_REV; /* 0x2B4: Update override revolution */
99  __RW uint32_t UPD_SPD; /* 0x2B8: Update override speed */
100  __RW uint32_t UPD_ACC; /* 0x2BC: Update override accelerate */
101  __R uint32_t SMP_VAL; /* 0x2C0: Sample valid */
102  __R uint32_t SMP_STS; /* 0x2C4: Sample status */
103  __R uint8_t RESERVED1[4]; /* 0x2C8 - 0x2CB: Reserved */
104  __R uint32_t TIME_IN; /* 0x2CC: input time */
105  __R uint32_t POS_IN; /* 0x2D0: Input position */
106  __R uint32_t REV_IN; /* 0x2D4: Input revolution */
107  __R uint32_t SPD_IN; /* 0x2D8: Input speed */
108  __R uint32_t ACC_IN; /* 0x2DC: Input accelerate */
109  __R uint8_t RESERVED2[4]; /* 0x2E0 - 0x2E3: Reserved */
110  __R uint32_t UPD_STS; /* 0x2E4: Update status */
111  __R uint8_t RESERVED3[24]; /* 0x2E8 - 0x2FF: Reserved */
112  } POS;
113  struct {
114  __RW uint32_t INT_EN; /* 0x300: Interrupt Enable */
115  __W uint32_t INT_FLAG; /* 0x304: Interrupt flag */
116  __R uint32_t INT_STS; /* 0x308: Interrupt status */
117  __R uint8_t RESERVED0[4]; /* 0x30C - 0x30F: Reserved */
118  __RW uint32_t POINTER0; /* 0x310: Match pointer 0 */
119  __RW uint32_t POINTER1; /* 0x314: Match pointer 1 */
120  __RW uint32_t INSTR0; /* 0x318: Match instruction 0 */
121  __RW uint32_t INSTR1; /* 0x31C: Match instruction 1 */
122  } IRQ;
123  __R uint8_t RESERVED0[224]; /* 0x320 - 0x3FF: Reserved */
124  } CTRL[13];
125  __RW uint32_t INSTR[256]; /* 0x3400 - 0x37FC: Instructions */
126  struct {
127  __RW uint32_t MODE; /* 0x3800: */
128  __RW uint32_t IDX; /* 0x3804: Data register bit index */
129  __RW uint32_t GOLD; /* 0x3808: Gold data for data check */
130  __RW uint32_t CRCINIT; /* 0x380C: CRC calculation initial vector */
131  __RW uint32_t CRCPOLY; /* 0x3810: CRC calculation polynomial */
132  __R uint8_t RESERVED0[12]; /* 0x3814 - 0x381F: Reserved */
133  __RW uint32_t DATA; /* 0x3820: Data value */
134  __RW uint32_t SET; /* 0x3824: Data bit set */
135  __RW uint32_t CLR; /* 0x3828: Data bit clear */
136  __RW uint32_t INV; /* 0x382C: Data bit invert */
137  __R uint32_t IN; /* 0x3830: Data input */
138  __R uint32_t OUT; /* 0x3834: Data output */
139  __RW uint32_t STS; /* 0x3838: Data status */
140  __R uint8_t RESERVED1[4]; /* 0x383C - 0x383F: Reserved */
141  } DAT[32];
142 } SEI_Type;
143 
144 
145 /* Bitfield definition for register of struct array CTRL: CTRL */
146 /*
147  * WATCH (RW)
148  *
149  * Enable watch dog
150  * 0: Watch dog disabled
151  * 1: Watch dog enabled
152  */
153 #define SEI_CTRL_ENGINE_CTRL_WATCH_MASK (0x1000000UL)
154 #define SEI_CTRL_ENGINE_CTRL_WATCH_SHIFT (24U)
155 #define SEI_CTRL_ENGINE_CTRL_WATCH_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_WATCH_SHIFT) & SEI_CTRL_ENGINE_CTRL_WATCH_MASK)
156 #define SEI_CTRL_ENGINE_CTRL_WATCH_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_WATCH_MASK) >> SEI_CTRL_ENGINE_CTRL_WATCH_SHIFT)
157 
158 /*
159  * ARMING (RW)
160  *
161  * Wait for trigger before excuting
162  * 0: Execute on enable
163  * 1: Wait trigger before exection after enabled
164  */
165 #define SEI_CTRL_ENGINE_CTRL_ARMING_MASK (0x10000UL)
166 #define SEI_CTRL_ENGINE_CTRL_ARMING_SHIFT (16U)
167 #define SEI_CTRL_ENGINE_CTRL_ARMING_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_ARMING_SHIFT) & SEI_CTRL_ENGINE_CTRL_ARMING_MASK)
168 #define SEI_CTRL_ENGINE_CTRL_ARMING_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_ARMING_MASK) >> SEI_CTRL_ENGINE_CTRL_ARMING_SHIFT)
169 
170 /*
171  * EXCEPT (RW)
172  *
173  * Explain timout as exception
174  * 0: when timeout, pointer move to next instruction
175  * 1: when timeout, pointer jump to timeout vector
176  */
177 #define SEI_CTRL_ENGINE_CTRL_EXCEPT_MASK (0x100U)
178 #define SEI_CTRL_ENGINE_CTRL_EXCEPT_SHIFT (8U)
179 #define SEI_CTRL_ENGINE_CTRL_EXCEPT_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_EXCEPT_SHIFT) & SEI_CTRL_ENGINE_CTRL_EXCEPT_MASK)
180 #define SEI_CTRL_ENGINE_CTRL_EXCEPT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_EXCEPT_MASK) >> SEI_CTRL_ENGINE_CTRL_EXCEPT_SHIFT)
181 
182 /*
183  * REWIND (RW)
184  *
185  * Rewind execution pointer
186  * 0: run
187  * 1: clean status and rewind
188  */
189 #define SEI_CTRL_ENGINE_CTRL_REWIND_MASK (0x10U)
190 #define SEI_CTRL_ENGINE_CTRL_REWIND_SHIFT (4U)
191 #define SEI_CTRL_ENGINE_CTRL_REWIND_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_REWIND_SHIFT) & SEI_CTRL_ENGINE_CTRL_REWIND_MASK)
192 #define SEI_CTRL_ENGINE_CTRL_REWIND_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_REWIND_MASK) >> SEI_CTRL_ENGINE_CTRL_REWIND_SHIFT)
193 
194 /*
195  * ENABLE (RW)
196  *
197  * Enable
198  * 0: disable
199  * 1: enable
200  */
201 #define SEI_CTRL_ENGINE_CTRL_ENABLE_MASK (0x1U)
202 #define SEI_CTRL_ENGINE_CTRL_ENABLE_SHIFT (0U)
203 #define SEI_CTRL_ENGINE_CTRL_ENABLE_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_ENABLE_SHIFT) & SEI_CTRL_ENGINE_CTRL_ENABLE_MASK)
204 #define SEI_CTRL_ENGINE_CTRL_ENABLE_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_ENABLE_MASK) >> SEI_CTRL_ENGINE_CTRL_ENABLE_SHIFT)
205 
206 /* Bitfield definition for register of struct array CTRL: PTR_CFG */
207 /*
208  * DAT_CDM (RW)
209  *
210  * Select DATA register to receive CDM bit in BiSSC slave mode
211  * 0: ignore
212  * 1: command
213  * 2: data register 2
214  * 3: data register 3
215  * ...
216  * 29:data register 29
217  * 30: value 0 when send, ignore in receive
218  * 31: value1 when send, ignore in receive
219  */
220 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_MASK (0x1F000000UL)
221 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SHIFT (24U)
222 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_MASK)
223 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SHIFT)
224 
225 /*
226  * DAT_BASE (RW)
227  *
228  * Bias for data register access, if calculated index bigger than 32, index will wrap around
229  * 0: real data index
230  * 1: access index is 1 greater than instruction address
231  * 2: access index is 2 greater than instruction address
232  * ...
233  * 31: access index is 31 greater than instruction address
234  */
235 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_MASK (0x1F0000UL)
236 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SHIFT (16U)
237 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_MASK)
238 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SHIFT)
239 
240 /*
241  * POINTER_WDOG (RW)
242  *
243  * Pointer to the instruction that the program starts executing after the instruction timeout. The timeout is WDOG_TIME
244  */
245 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_MASK (0xFF00U)
246 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SHIFT (8U)
247 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_MASK)
248 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SHIFT)
249 
250 /*
251  * POINTER_INIT (RW)
252  *
253  * Initial execute pointer
254  */
255 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_MASK (0xFFU)
256 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SHIFT (0U)
257 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_MASK)
258 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SHIFT)
259 
260 /* Bitfield definition for register of struct array CTRL: WDG_CFG */
261 /*
262  * WDOG_TIME (RW)
263  *
264  * Time out count for each instruction, counter in bit time.
265  */
266 #define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_MASK (0xFFFFU)
267 #define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SHIFT (0U)
268 #define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SHIFT) & SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_MASK)
269 #define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_MASK) >> SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SHIFT)
270 
271 /* Bitfield definition for register of struct array CTRL: EXE_STA */
272 /*
273  * TRIGERED (RO)
274  *
275  * Execution has been triggered
276  * 0: Execution not triggered
277  * 1: Execution triggered
278  */
279 #define SEI_CTRL_ENGINE_EXE_STA_TRIGERED_MASK (0x100000UL)
280 #define SEI_CTRL_ENGINE_EXE_STA_TRIGERED_SHIFT (20U)
281 #define SEI_CTRL_ENGINE_EXE_STA_TRIGERED_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_TRIGERED_MASK) >> SEI_CTRL_ENGINE_EXE_STA_TRIGERED_SHIFT)
282 
283 /*
284  * ARMED (RO)
285  *
286  * Waiting for trigger for execution
287  * 0: Not in waiting status
288  * 1: In waiting status
289  */
290 #define SEI_CTRL_ENGINE_EXE_STA_ARMED_MASK (0x10000UL)
291 #define SEI_CTRL_ENGINE_EXE_STA_ARMED_SHIFT (16U)
292 #define SEI_CTRL_ENGINE_EXE_STA_ARMED_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_ARMED_MASK) >> SEI_CTRL_ENGINE_EXE_STA_ARMED_SHIFT)
293 
294 /*
295  * EXPIRE (RO)
296  *
297  * Watchdog timer expired
298  * 0: Not expired
299  * 1: Expired
300  */
301 #define SEI_CTRL_ENGINE_EXE_STA_EXPIRE_MASK (0x100U)
302 #define SEI_CTRL_ENGINE_EXE_STA_EXPIRE_SHIFT (8U)
303 #define SEI_CTRL_ENGINE_EXE_STA_EXPIRE_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_EXPIRE_MASK) >> SEI_CTRL_ENGINE_EXE_STA_EXPIRE_SHIFT)
304 
305 /*
306  * STALL (RO)
307  *
308  * Program finished
309  * 0: Program is executing
310  * 1: Program finished
311  */
312 #define SEI_CTRL_ENGINE_EXE_STA_STALL_MASK (0x1U)
313 #define SEI_CTRL_ENGINE_EXE_STA_STALL_SHIFT (0U)
314 #define SEI_CTRL_ENGINE_EXE_STA_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_STALL_MASK) >> SEI_CTRL_ENGINE_EXE_STA_STALL_SHIFT)
315 
316 /* Bitfield definition for register of struct array CTRL: EXE_PTR */
317 /*
318  * HALT_CNT (RO)
319  *
320  * Halt count in halt instrution
321  */
322 #define SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_MASK (0x1F000000UL)
323 #define SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_SHIFT (24U)
324 #define SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_MASK) >> SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_SHIFT)
325 
326 /*
327  * BIT_CNT (RO)
328  *
329  * Bit count in send and receive instruction execution
330  */
331 #define SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_MASK (0x1F0000UL)
332 #define SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_SHIFT (16U)
333 #define SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_MASK) >> SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_SHIFT)
334 
335 /*
336  * POINTER (RO)
337  *
338  * Current program pointer
339  */
340 #define SEI_CTRL_ENGINE_EXE_PTR_POINTER_MASK (0xFFU)
341 #define SEI_CTRL_ENGINE_EXE_PTR_POINTER_SHIFT (0U)
342 #define SEI_CTRL_ENGINE_EXE_PTR_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_PTR_POINTER_MASK) >> SEI_CTRL_ENGINE_EXE_PTR_POINTER_SHIFT)
343 
344 /* Bitfield definition for register of struct array CTRL: EXE_INST */
345 /*
346  * INST (RO)
347  *
348  * Current instruction
349  */
350 #define SEI_CTRL_ENGINE_EXE_INST_INST_MASK (0xFFFFFFFFUL)
351 #define SEI_CTRL_ENGINE_EXE_INST_INST_SHIFT (0U)
352 #define SEI_CTRL_ENGINE_EXE_INST_INST_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_INST_INST_MASK) >> SEI_CTRL_ENGINE_EXE_INST_INST_SHIFT)
353 
354 /* Bitfield definition for register of struct array CTRL: WDG_STA */
355 /*
356  * WDOG_CNT (RO)
357  *
358  * Current watch dog counter value
359  */
360 #define SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_MASK (0xFFFFU)
361 #define SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_SHIFT (0U)
362 #define SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_MASK) >> SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_SHIFT)
363 
364 /* Bitfield definition for register of struct array CTRL: CTRL */
365 /*
366  * TRISMP (RW)
367  *
368  * Tipple sampe
369  * 0: sample 1 time for data transition
370  * 1: sample 3 times in receive and result in 2oo3
371  */
372 #define SEI_CTRL_XCVR_CTRL_TRISMP_MASK (0x1000U)
373 #define SEI_CTRL_XCVR_CTRL_TRISMP_SHIFT (12U)
374 #define SEI_CTRL_XCVR_CTRL_TRISMP_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_TRISMP_SHIFT) & SEI_CTRL_XCVR_CTRL_TRISMP_MASK)
375 #define SEI_CTRL_XCVR_CTRL_TRISMP_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_TRISMP_MASK) >> SEI_CTRL_XCVR_CTRL_TRISMP_SHIFT)
376 
377 /*
378  * PAR_CLR (WC)
379  *
380  * Clear parity error, this is a self clear bit
381  * 0: no effect
382  * 1: clear parity error
383  */
384 #define SEI_CTRL_XCVR_CTRL_PAR_CLR_MASK (0x100U)
385 #define SEI_CTRL_XCVR_CTRL_PAR_CLR_SHIFT (8U)
386 #define SEI_CTRL_XCVR_CTRL_PAR_CLR_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_PAR_CLR_SHIFT) & SEI_CTRL_XCVR_CTRL_PAR_CLR_MASK)
387 #define SEI_CTRL_XCVR_CTRL_PAR_CLR_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_PAR_CLR_MASK) >> SEI_CTRL_XCVR_CTRL_PAR_CLR_SHIFT)
388 
389 /*
390  * RESTART (WC)
391  *
392  * Restart tranceiver, this is a self clear bit
393  * 0: no effect
394  * 1: reset tranceiver
395  */
396 #define SEI_CTRL_XCVR_CTRL_RESTART_MASK (0x10U)
397 #define SEI_CTRL_XCVR_CTRL_RESTART_SHIFT (4U)
398 #define SEI_CTRL_XCVR_CTRL_RESTART_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_RESTART_SHIFT) & SEI_CTRL_XCVR_CTRL_RESTART_MASK)
399 #define SEI_CTRL_XCVR_CTRL_RESTART_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_RESTART_MASK) >> SEI_CTRL_XCVR_CTRL_RESTART_SHIFT)
400 
401 /*
402  * MODE (RW)
403  *
404  * Tranceiver mode
405  * 0: synchronous maaster
406  * 1: synchronous slave
407  * 2: asynchronous mode
408  * 3: asynchronous mode
409  */
410 #define SEI_CTRL_XCVR_CTRL_MODE_MASK (0x3U)
411 #define SEI_CTRL_XCVR_CTRL_MODE_SHIFT (0U)
412 #define SEI_CTRL_XCVR_CTRL_MODE_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_MODE_SHIFT) & SEI_CTRL_XCVR_CTRL_MODE_MASK)
413 #define SEI_CTRL_XCVR_CTRL_MODE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_MODE_MASK) >> SEI_CTRL_XCVR_CTRL_MODE_SHIFT)
414 
415 /* Bitfield definition for register of struct array CTRL: TYPE_CFG */
416 /*
417  * WAIT_LEN (RW)
418  *
419  * Number of extra stop bit for asynchronous mode
420  * 0: 1 bit
421  * 1: 2 bit
422  * ...
423  * 255: 256 bit
424  */
425 #define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_MASK (0xFF000000UL)
426 #define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SHIFT (24U)
427 #define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_MASK)
428 #define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SHIFT)
429 
430 /*
431  * DATA_LEN (RW)
432  *
433  * Number of data bit for asynchronous mode
434  * 0: 1 bit
435  * 1: 2 bit
436  * ...
437  * 31: 32 bit
438  */
439 #define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_MASK (0x1F0000UL)
440 #define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SHIFT (16U)
441 #define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_MASK)
442 #define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SHIFT)
443 
444 /*
445  * PAR_POL (RW)
446  *
447  * Polarity of parity for asynchronous mode
448  * 0: even
449  * 1: odd
450  */
451 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_MASK (0x200U)
452 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SHIFT (9U)
453 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_MASK)
454 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SHIFT)
455 
456 /*
457  * PAR_EN (RW)
458  *
459  * enable parity check for asynchronous mode
460  * 0: disable
461  * 1: enable
462  */
463 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_MASK (0x100U)
464 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SHIFT (8U)
465 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_MASK)
466 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SHIFT)
467 
468 /*
469  * DA_IDLEZ (RW)
470  *
471  * Idle state driver of data line
472  * 0: output
473  * 1: high-Z
474  */
475 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_MASK (0x8U)
476 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SHIFT (3U)
477 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_MASK)
478 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SHIFT)
479 
480 /*
481  * CK_IDLEZ (RW)
482  *
483  * Idle state driver of clock line
484  * 0: output
485  * 1: high-Z
486  */
487 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_MASK (0x4U)
488 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SHIFT (2U)
489 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_MASK)
490 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SHIFT)
491 
492 /*
493  * DA_IDLEV (RW)
494  *
495  * Idle state value of data line
496  * 0: data'0'
497  * 1: data'1'
498  */
499 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_MASK (0x2U)
500 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SHIFT (1U)
501 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_MASK)
502 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SHIFT)
503 
504 /*
505  * CK_IDLEV (RW)
506  *
507  * Idle state value of clock line
508  * 0: data'0'
509  * 1: data'1'
510  */
511 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_MASK (0x1U)
512 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SHIFT (0U)
513 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_MASK)
514 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SHIFT)
515 
516 /* Bitfield definition for register of struct array CTRL: BAUD_CFG */
517 /*
518  * SYNC_POINT (RW)
519  *
520  * Baud synchronous time, minmum bit time
521  */
522 #define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_MASK (0xFFFF0000UL)
523 #define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SHIFT (16U)
524 #define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SHIFT) & SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_MASK)
525 #define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_MASK) >> SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SHIFT)
526 
527 /*
528  * BAUD_DIV (RW)
529  *
530  * Baud rate, bit time in system clock cycle
531  */
532 #define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_MASK (0xFFFFU)
533 #define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SHIFT (0U)
534 #define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SHIFT) & SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_MASK)
535 #define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_MASK) >> SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SHIFT)
536 
537 /* Bitfield definition for register of struct array CTRL: DATA_CFG */
538 /*
539  * TXD_POINT (RW)
540  *
541  * data transmit point in system clcok cycle
542  */
543 #define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_MASK (0xFFFF0000UL)
544 #define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SHIFT (16U)
545 #define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SHIFT) & SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_MASK)
546 #define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_MASK) >> SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SHIFT)
547 
548 /*
549  * RXD_POINT (RW)
550  *
551  * data receive point in system clcok cycle
552  */
553 #define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_MASK (0xFFFFU)
554 #define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SHIFT (0U)
555 #define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SHIFT) & SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_MASK)
556 #define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_MASK) >> SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SHIFT)
557 
558 /* Bitfield definition for register of struct array CTRL: CLK_CFG */
559 /*
560  * CK1_POINT (RW)
561  *
562  * clock point 1 in system clcok cycle
563  */
564 #define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_MASK (0xFFFF0000UL)
565 #define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SHIFT (16U)
566 #define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SHIFT) & SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_MASK)
567 #define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_MASK) >> SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SHIFT)
568 
569 /*
570  * CK0_POINT (RW)
571  *
572  * clock point 0 in system clcok cycle
573  */
574 #define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_MASK (0xFFFFU)
575 #define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SHIFT (0U)
576 #define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SHIFT) & SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_MASK)
577 #define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_MASK) >> SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SHIFT)
578 
579 /* Bitfield definition for register of struct array CTRL: PIN */
580 /*
581  * OE_CK (RO)
582  *
583  * CK drive state
584  * 0: input
585  * 1: output
586  */
587 #define SEI_CTRL_XCVR_PIN_OE_CK_MASK (0x4000000UL)
588 #define SEI_CTRL_XCVR_PIN_OE_CK_SHIFT (26U)
589 #define SEI_CTRL_XCVR_PIN_OE_CK_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_CK_MASK) >> SEI_CTRL_XCVR_PIN_OE_CK_SHIFT)
590 
591 /*
592  * DI_CK (RO)
593  *
594  * CK state
595  * 0: data 0
596  * 1: data 1
597  */
598 #define SEI_CTRL_XCVR_PIN_DI_CK_MASK (0x2000000UL)
599 #define SEI_CTRL_XCVR_PIN_DI_CK_SHIFT (25U)
600 #define SEI_CTRL_XCVR_PIN_DI_CK_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_CK_MASK) >> SEI_CTRL_XCVR_PIN_DI_CK_SHIFT)
601 
602 /*
603  * DO_CK (RO)
604  *
605  * CK output
606  * 0: data 0
607  * 1: data 1
608  */
609 #define SEI_CTRL_XCVR_PIN_DO_CK_MASK (0x1000000UL)
610 #define SEI_CTRL_XCVR_PIN_DO_CK_SHIFT (24U)
611 #define SEI_CTRL_XCVR_PIN_DO_CK_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_CK_MASK) >> SEI_CTRL_XCVR_PIN_DO_CK_SHIFT)
612 
613 /*
614  * OE_RX (RO)
615  *
616  * RX drive state
617  * 0: input
618  * 1: output
619  */
620 #define SEI_CTRL_XCVR_PIN_OE_RX_MASK (0x40000UL)
621 #define SEI_CTRL_XCVR_PIN_OE_RX_SHIFT (18U)
622 #define SEI_CTRL_XCVR_PIN_OE_RX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_RX_MASK) >> SEI_CTRL_XCVR_PIN_OE_RX_SHIFT)
623 
624 /*
625  * DI_RX (RO)
626  *
627  * RX state
628  * 0: data 0
629  * 1: data 1
630  */
631 #define SEI_CTRL_XCVR_PIN_DI_RX_MASK (0x20000UL)
632 #define SEI_CTRL_XCVR_PIN_DI_RX_SHIFT (17U)
633 #define SEI_CTRL_XCVR_PIN_DI_RX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_RX_MASK) >> SEI_CTRL_XCVR_PIN_DI_RX_SHIFT)
634 
635 /*
636  * DO_RX (RO)
637  *
638  * RX output
639  * 0: data 0
640  * 1: data 1
641  */
642 #define SEI_CTRL_XCVR_PIN_DO_RX_MASK (0x10000UL)
643 #define SEI_CTRL_XCVR_PIN_DO_RX_SHIFT (16U)
644 #define SEI_CTRL_XCVR_PIN_DO_RX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_RX_MASK) >> SEI_CTRL_XCVR_PIN_DO_RX_SHIFT)
645 
646 /*
647  * OE_DE (RO)
648  *
649  * DE drive state
650  * 0: input
651  * 1: output
652  */
653 #define SEI_CTRL_XCVR_PIN_OE_DE_MASK (0x400U)
654 #define SEI_CTRL_XCVR_PIN_OE_DE_SHIFT (10U)
655 #define SEI_CTRL_XCVR_PIN_OE_DE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_DE_MASK) >> SEI_CTRL_XCVR_PIN_OE_DE_SHIFT)
656 
657 /*
658  * DI_DE (RO)
659  *
660  * DE state
661  * 0: data 0
662  * 1: data 1
663  */
664 #define SEI_CTRL_XCVR_PIN_DI_DE_MASK (0x200U)
665 #define SEI_CTRL_XCVR_PIN_DI_DE_SHIFT (9U)
666 #define SEI_CTRL_XCVR_PIN_DI_DE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_DE_MASK) >> SEI_CTRL_XCVR_PIN_DI_DE_SHIFT)
667 
668 /*
669  * DO_DE (RO)
670  *
671  * DE output
672  * 0: data 0
673  * 1: data 1
674  */
675 #define SEI_CTRL_XCVR_PIN_DO_DE_MASK (0x100U)
676 #define SEI_CTRL_XCVR_PIN_DO_DE_SHIFT (8U)
677 #define SEI_CTRL_XCVR_PIN_DO_DE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_DE_MASK) >> SEI_CTRL_XCVR_PIN_DO_DE_SHIFT)
678 
679 /*
680  * OE_TX (RO)
681  *
682  * TX drive state
683  * 0: input
684  * 1: output
685  */
686 #define SEI_CTRL_XCVR_PIN_OE_TX_MASK (0x4U)
687 #define SEI_CTRL_XCVR_PIN_OE_TX_SHIFT (2U)
688 #define SEI_CTRL_XCVR_PIN_OE_TX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_TX_MASK) >> SEI_CTRL_XCVR_PIN_OE_TX_SHIFT)
689 
690 /*
691  * DI_TX (RO)
692  *
693  * TX state
694  * 0: data 0
695  * 1: data 1
696  */
697 #define SEI_CTRL_XCVR_PIN_DI_TX_MASK (0x2U)
698 #define SEI_CTRL_XCVR_PIN_DI_TX_SHIFT (1U)
699 #define SEI_CTRL_XCVR_PIN_DI_TX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_TX_MASK) >> SEI_CTRL_XCVR_PIN_DI_TX_SHIFT)
700 
701 /*
702  * DO_TX (RO)
703  *
704  * TX output
705  * 0: data 0
706  * 1: data 1
707  */
708 #define SEI_CTRL_XCVR_PIN_DO_TX_MASK (0x1U)
709 #define SEI_CTRL_XCVR_PIN_DO_TX_SHIFT (0U)
710 #define SEI_CTRL_XCVR_PIN_DO_TX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_TX_MASK) >> SEI_CTRL_XCVR_PIN_DO_TX_SHIFT)
711 
712 /* Bitfield definition for register of struct array CTRL: STATE */
713 /*
714  * RECV_STATE (RO)
715  *
716  * FSM of asynchronous receive
717  */
718 #define SEI_CTRL_XCVR_STATE_RECV_STATE_MASK (0x7000000UL)
719 #define SEI_CTRL_XCVR_STATE_RECV_STATE_SHIFT (24U)
720 #define SEI_CTRL_XCVR_STATE_RECV_STATE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_STATE_RECV_STATE_MASK) >> SEI_CTRL_XCVR_STATE_RECV_STATE_SHIFT)
721 
722 /*
723  * SEND_STATE (RO)
724  *
725  * FSM of asynchronous transmit
726  */
727 #define SEI_CTRL_XCVR_STATE_SEND_STATE_MASK (0x70000UL)
728 #define SEI_CTRL_XCVR_STATE_SEND_STATE_SHIFT (16U)
729 #define SEI_CTRL_XCVR_STATE_SEND_STATE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_STATE_SEND_STATE_MASK) >> SEI_CTRL_XCVR_STATE_SEND_STATE_SHIFT)
730 
731 /* Bitfield definition for register of struct array CTRL: IN_CFG */
732 /*
733  * PRD_EN (RW)
734  *
735  * Enable period trigger (tigger 2)
736  * 0: periodical trigger disabled
737  * 1: periodical trigger enabled
738  */
739 #define SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK (0x800000UL)
740 #define SEI_CTRL_TRG_IN_CFG_PRD_EN_SHIFT (23U)
741 #define SEI_CTRL_TRG_IN_CFG_PRD_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_PRD_EN_SHIFT) & SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK)
742 #define SEI_CTRL_TRG_IN_CFG_PRD_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK) >> SEI_CTRL_TRG_IN_CFG_PRD_EN_SHIFT)
743 
744 /*
745  * SYNC_SEL (RW)
746  *
747  * Synchronize sigal selection (tigger 2)
748  * 0: trigger in 0
749  * 1: trigger in 1
750  * ...
751  * 7: trigger in 7
752  */
753 #define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_MASK (0x70000UL)
754 #define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SHIFT (16U)
755 #define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SHIFT) & SEI_CTRL_TRG_IN_CFG_SYNC_SEL_MASK)
756 #define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_SYNC_SEL_MASK) >> SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SHIFT)
757 
758 /*
759  * IN1_EN (RW)
760  *
761  * Enable trigger 1
762  * 0: disable trigger 1
763  * 1: enable trigger 1
764  */
765 #define SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK (0x8000U)
766 #define SEI_CTRL_TRG_IN_CFG_IN1_EN_SHIFT (15U)
767 #define SEI_CTRL_TRG_IN_CFG_IN1_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN1_EN_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK)
768 #define SEI_CTRL_TRG_IN_CFG_IN1_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK) >> SEI_CTRL_TRG_IN_CFG_IN1_EN_SHIFT)
769 
770 /*
771  * IN1_SEL (RW)
772  *
773  * Trigger 1 sigal selection
774  * 0: trigger in 0
775  * 1: trigger in 1
776  * ...
777  * 7: trigger in 7
778  */
779 #define SEI_CTRL_TRG_IN_CFG_IN1_SEL_MASK (0x700U)
780 #define SEI_CTRL_TRG_IN_CFG_IN1_SEL_SHIFT (8U)
781 #define SEI_CTRL_TRG_IN_CFG_IN1_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN1_SEL_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN1_SEL_MASK)
782 #define SEI_CTRL_TRG_IN_CFG_IN1_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN1_SEL_MASK) >> SEI_CTRL_TRG_IN_CFG_IN1_SEL_SHIFT)
783 
784 /*
785  * IN0_EN (RW)
786  *
787  * Enable trigger 0
788  * 0: disable trigger 1
789  * 1: enable trigger 1
790  */
791 #define SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK (0x80U)
792 #define SEI_CTRL_TRG_IN_CFG_IN0_EN_SHIFT (7U)
793 #define SEI_CTRL_TRG_IN_CFG_IN0_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN0_EN_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK)
794 #define SEI_CTRL_TRG_IN_CFG_IN0_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK) >> SEI_CTRL_TRG_IN_CFG_IN0_EN_SHIFT)
795 
796 /*
797  * IN0_SEL (RW)
798  *
799  * Trigger 0 sigal selection
800  * 0: trigger in 0
801  * 1: trigger in 1
802  * ...
803  * 7: trigger in 7
804  */
805 #define SEI_CTRL_TRG_IN_CFG_IN0_SEL_MASK (0x7U)
806 #define SEI_CTRL_TRG_IN_CFG_IN0_SEL_SHIFT (0U)
807 #define SEI_CTRL_TRG_IN_CFG_IN0_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN0_SEL_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN0_SEL_MASK)
808 #define SEI_CTRL_TRG_IN_CFG_IN0_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN0_SEL_MASK) >> SEI_CTRL_TRG_IN_CFG_IN0_SEL_SHIFT)
809 
810 /* Bitfield definition for register of struct array CTRL: SW */
811 /*
812  * SOFT (WC)
813  *
814  * Software trigger (tigger 3). this bit is self-clear
815  * 0: trigger source disabled
816  * 1: trigger source enabled
817  */
818 #define SEI_CTRL_TRG_SW_SOFT_MASK (0x1U)
819 #define SEI_CTRL_TRG_SW_SOFT_SHIFT (0U)
820 #define SEI_CTRL_TRG_SW_SOFT_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_SW_SOFT_SHIFT) & SEI_CTRL_TRG_SW_SOFT_MASK)
821 #define SEI_CTRL_TRG_SW_SOFT_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_SW_SOFT_MASK) >> SEI_CTRL_TRG_SW_SOFT_SHIFT)
822 
823 /* Bitfield definition for register of struct array CTRL: PRD_CFG */
824 /*
825  * ARMING (RW)
826  *
827  * Wait for trigger synchronous before trigger
828  * 0: Trigger directly
829  * 1: Wait trigger source before period trigger
830  */
831 #define SEI_CTRL_TRG_PRD_CFG_ARMING_MASK (0x10000UL)
832 #define SEI_CTRL_TRG_PRD_CFG_ARMING_SHIFT (16U)
833 #define SEI_CTRL_TRG_PRD_CFG_ARMING_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_PRD_CFG_ARMING_SHIFT) & SEI_CTRL_TRG_PRD_CFG_ARMING_MASK)
834 #define SEI_CTRL_TRG_PRD_CFG_ARMING_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_CFG_ARMING_MASK) >> SEI_CTRL_TRG_PRD_CFG_ARMING_SHIFT)
835 
836 /*
837  * SYNC (RW)
838  *
839  * Synchronous
840  * 0: Not synchronous
841  * 1: Synchronous every trigger source
842  */
843 #define SEI_CTRL_TRG_PRD_CFG_SYNC_MASK (0x1U)
844 #define SEI_CTRL_TRG_PRD_CFG_SYNC_SHIFT (0U)
845 #define SEI_CTRL_TRG_PRD_CFG_SYNC_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_PRD_CFG_SYNC_SHIFT) & SEI_CTRL_TRG_PRD_CFG_SYNC_MASK)
846 #define SEI_CTRL_TRG_PRD_CFG_SYNC_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_CFG_SYNC_MASK) >> SEI_CTRL_TRG_PRD_CFG_SYNC_SHIFT)
847 
848 /* Bitfield definition for register of struct array CTRL: PRD */
849 /*
850  * PERIOD (RW)
851  *
852  * Trigger period
853  */
854 #define SEI_CTRL_TRG_PRD_PERIOD_MASK (0xFFFFFFFFUL)
855 #define SEI_CTRL_TRG_PRD_PERIOD_SHIFT (0U)
856 #define SEI_CTRL_TRG_PRD_PERIOD_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_PRD_PERIOD_SHIFT) & SEI_CTRL_TRG_PRD_PERIOD_MASK)
857 #define SEI_CTRL_TRG_PRD_PERIOD_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_PERIOD_MASK) >> SEI_CTRL_TRG_PRD_PERIOD_SHIFT)
858 
859 /* Bitfield definition for register of struct array CTRL: OUT_CFG */
860 /*
861  * OUT3_EN (RW)
862  *
863  * Enable trigger 3
864  * 0: disable trigger 3
865  * 1: enable trigger 3
866  */
867 #define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_MASK (0x80000000UL)
868 #define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SHIFT (31U)
869 #define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT3_EN_MASK)
870 #define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT3_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SHIFT)
871 
872 /*
873  * OUT3_SEL (RW)
874  *
875  * Trigger 3 sigal selection
876  * 0: trigger out 0
877  * 1: trigger out 1
878  * ...
879  * 7: trigger out 7
880  */
881 #define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_MASK (0x7000000UL)
882 #define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SHIFT (24U)
883 #define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_MASK)
884 #define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SHIFT)
885 
886 /*
887  * OUT2_EN (RW)
888  *
889  * Enable trigger 2
890  * 0: disable trigger 2
891  * 1: enable trigger 2
892  */
893 #define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_MASK (0x800000UL)
894 #define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SHIFT (23U)
895 #define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT2_EN_MASK)
896 #define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT2_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SHIFT)
897 
898 /*
899  * OUT2_SEL (RW)
900  *
901  * Trigger 2 sigal selection
902  * 0: trigger out 0
903  * 1: trigger out 1
904  * ...
905  * 7: trigger out 7
906  */
907 #define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_MASK (0x70000UL)
908 #define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SHIFT (16U)
909 #define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_MASK)
910 #define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SHIFT)
911 
912 /*
913  * OUT1_EN (RW)
914  *
915  * Enable trigger 1
916  * 0: disable trigger 1
917  * 1: enable trigger 1
918  */
919 #define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_MASK (0x8000U)
920 #define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SHIFT (15U)
921 #define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT1_EN_MASK)
922 #define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT1_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SHIFT)
923 
924 /*
925  * OUT1_SEL (RW)
926  *
927  * Trigger 1 sigal selection
928  * 0: trigger out 0
929  * 1: trigger out 1
930  * ...
931  * 7: trigger out 7
932  */
933 #define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_MASK (0x700U)
934 #define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SHIFT (8U)
935 #define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_MASK)
936 #define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SHIFT)
937 
938 /*
939  * OUT0_EN (RW)
940  *
941  * Enable trigger 0
942  * 0: disable trigger 1
943  * 1: enable trigger 1
944  */
945 #define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_MASK (0x80U)
946 #define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SHIFT (7U)
947 #define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT0_EN_MASK)
948 #define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT0_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SHIFT)
949 
950 /*
951  * OUT0_SEL (RW)
952  *
953  * Trigger 0 sigal selection
954  * 0: trigger out 0
955  * 1: trigger out 1
956  * ...
957  * 7: trigger out 7
958  */
959 #define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_MASK (0x7U)
960 #define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SHIFT (0U)
961 #define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_MASK)
962 #define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SHIFT)
963 
964 /* Bitfield definition for register of struct array CTRL: PRD_STS */
965 /*
966  * TRIGERED (RO)
967  *
968  * Period has been triggered
969  * 0: Not triggered
970  * 1: Triggered
971  */
972 #define SEI_CTRL_TRG_PRD_STS_TRIGERED_MASK (0x100000UL)
973 #define SEI_CTRL_TRG_PRD_STS_TRIGERED_SHIFT (20U)
974 #define SEI_CTRL_TRG_PRD_STS_TRIGERED_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_STS_TRIGERED_MASK) >> SEI_CTRL_TRG_PRD_STS_TRIGERED_SHIFT)
975 
976 /*
977  * ARMED (RO)
978  *
979  * Waiting for trigger
980  * 0: Not in waiting status
981  * 1: In waiting status
982  */
983 #define SEI_CTRL_TRG_PRD_STS_ARMED_MASK (0x10000UL)
984 #define SEI_CTRL_TRG_PRD_STS_ARMED_SHIFT (16U)
985 #define SEI_CTRL_TRG_PRD_STS_ARMED_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_STS_ARMED_MASK) >> SEI_CTRL_TRG_PRD_STS_ARMED_SHIFT)
986 
987 /* Bitfield definition for register of struct array CTRL: PRD_CNT */
988 /*
989  * PERIOD_CNT (RO)
990  *
991  * Trigger period counter
992  */
993 #define SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_MASK (0xFFFFFFFFUL)
994 #define SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_SHIFT (0U)
995 #define SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_MASK) >> SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_SHIFT)
996 
997 /* Bitfield definition for register of struct array CTRL: 0 */
998 /*
999  * CMD_TRIGGER0 (RW)
1000  *
1001  * Trigger command
1002  */
1003 #define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_MASK (0xFFFFFFFFUL)
1004 #define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SHIFT (0U)
1005 #define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SHIFT) & SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_MASK)
1006 #define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_MASK) >> SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SHIFT)
1007 
1008 /* Bitfield definition for register of struct array CTRL: 0 */
1009 /*
1010  * TRIGGER0_TIME (RO)
1011  *
1012  * Trigger time
1013  */
1014 #define SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_MASK (0xFFFFFFFFUL)
1015 #define SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_SHIFT (0U)
1016 #define SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_MASK) >> SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_SHIFT)
1017 
1018 /* Bitfield definition for register of struct array CTRL: MODE */
1019 /*
1020  * WLEN (RW)
1021  *
1022  * word length
1023  * 0: 1 bit
1024  * 1: 2 bit
1025  * ...
1026  * 31: 32 bit
1027  */
1028 #define SEI_CTRL_CMD_MODE_WLEN_MASK (0x1F0000UL)
1029 #define SEI_CTRL_CMD_MODE_WLEN_SHIFT (16U)
1030 #define SEI_CTRL_CMD_MODE_WLEN_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_WLEN_SHIFT) & SEI_CTRL_CMD_MODE_WLEN_MASK)
1031 #define SEI_CTRL_CMD_MODE_WLEN_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_WLEN_MASK) >> SEI_CTRL_CMD_MODE_WLEN_SHIFT)
1032 
1033 /*
1034  * WORDER (RW)
1035  *
1036  * word order
1037  * 0: sample as bit order
1038  * 1: different from bit order
1039  */
1040 #define SEI_CTRL_CMD_MODE_WORDER_MASK (0x800U)
1041 #define SEI_CTRL_CMD_MODE_WORDER_SHIFT (11U)
1042 #define SEI_CTRL_CMD_MODE_WORDER_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_WORDER_SHIFT) & SEI_CTRL_CMD_MODE_WORDER_MASK)
1043 #define SEI_CTRL_CMD_MODE_WORDER_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_WORDER_MASK) >> SEI_CTRL_CMD_MODE_WORDER_SHIFT)
1044 
1045 /*
1046  * BORDER (RW)
1047  *
1048  * bit order
1049  * 0: LSB first
1050  * 1: MSB first
1051  */
1052 #define SEI_CTRL_CMD_MODE_BORDER_MASK (0x400U)
1053 #define SEI_CTRL_CMD_MODE_BORDER_SHIFT (10U)
1054 #define SEI_CTRL_CMD_MODE_BORDER_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_BORDER_SHIFT) & SEI_CTRL_CMD_MODE_BORDER_MASK)
1055 #define SEI_CTRL_CMD_MODE_BORDER_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_BORDER_MASK) >> SEI_CTRL_CMD_MODE_BORDER_SHIFT)
1056 
1057 /*
1058  * SIGNED (RW)
1059  *
1060  * Signed
1061  * 0: unsigned value
1062  * 1: signed value
1063  */
1064 #define SEI_CTRL_CMD_MODE_SIGNED_MASK (0x200U)
1065 #define SEI_CTRL_CMD_MODE_SIGNED_SHIFT (9U)
1066 #define SEI_CTRL_CMD_MODE_SIGNED_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_SIGNED_SHIFT) & SEI_CTRL_CMD_MODE_SIGNED_MASK)
1067 #define SEI_CTRL_CMD_MODE_SIGNED_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_SIGNED_MASK) >> SEI_CTRL_CMD_MODE_SIGNED_SHIFT)
1068 
1069 /*
1070  * REWIND (WC)
1071  *
1072  * Write 1 to rewind read/write pointer, this is a self clear bit
1073  */
1074 #define SEI_CTRL_CMD_MODE_REWIND_MASK (0x100U)
1075 #define SEI_CTRL_CMD_MODE_REWIND_SHIFT (8U)
1076 #define SEI_CTRL_CMD_MODE_REWIND_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_REWIND_SHIFT) & SEI_CTRL_CMD_MODE_REWIND_MASK)
1077 #define SEI_CTRL_CMD_MODE_REWIND_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_REWIND_MASK) >> SEI_CTRL_CMD_MODE_REWIND_SHIFT)
1078 
1079 /*
1080  * MODE (RW)
1081  *
1082  * Data mode
1083  * 0: data mode
1084  * 1: check mode
1085  * 2: CRC mode
1086  */
1087 #define SEI_CTRL_CMD_MODE_MODE_MASK (0x3U)
1088 #define SEI_CTRL_CMD_MODE_MODE_SHIFT (0U)
1089 #define SEI_CTRL_CMD_MODE_MODE_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_MODE_SHIFT) & SEI_CTRL_CMD_MODE_MODE_MASK)
1090 #define SEI_CTRL_CMD_MODE_MODE_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_MODE_MASK) >> SEI_CTRL_CMD_MODE_MODE_SHIFT)
1091 
1092 /* Bitfield definition for register of struct array CTRL: IDX */
1093 /*
1094  * LAST_BIT (RW)
1095  *
1096  * Last bit index for tranceive
1097  */
1098 #define SEI_CTRL_CMD_IDX_LAST_BIT_MASK (0x1F000000UL)
1099 #define SEI_CTRL_CMD_IDX_LAST_BIT_SHIFT (24U)
1100 #define SEI_CTRL_CMD_IDX_LAST_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_LAST_BIT_SHIFT) & SEI_CTRL_CMD_IDX_LAST_BIT_MASK)
1101 #define SEI_CTRL_CMD_IDX_LAST_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_LAST_BIT_MASK) >> SEI_CTRL_CMD_IDX_LAST_BIT_SHIFT)
1102 
1103 /*
1104  * FIRST_BIT (RW)
1105  *
1106  * First bit index for tranceive
1107  */
1108 #define SEI_CTRL_CMD_IDX_FIRST_BIT_MASK (0x1F0000UL)
1109 #define SEI_CTRL_CMD_IDX_FIRST_BIT_SHIFT (16U)
1110 #define SEI_CTRL_CMD_IDX_FIRST_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_FIRST_BIT_SHIFT) & SEI_CTRL_CMD_IDX_FIRST_BIT_MASK)
1111 #define SEI_CTRL_CMD_IDX_FIRST_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_FIRST_BIT_MASK) >> SEI_CTRL_CMD_IDX_FIRST_BIT_SHIFT)
1112 
1113 /*
1114  * MAX_BIT (RW)
1115  *
1116  * Highest bit index
1117  */
1118 #define SEI_CTRL_CMD_IDX_MAX_BIT_MASK (0x1F00U)
1119 #define SEI_CTRL_CMD_IDX_MAX_BIT_SHIFT (8U)
1120 #define SEI_CTRL_CMD_IDX_MAX_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_MAX_BIT_SHIFT) & SEI_CTRL_CMD_IDX_MAX_BIT_MASK)
1121 #define SEI_CTRL_CMD_IDX_MAX_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_MAX_BIT_MASK) >> SEI_CTRL_CMD_IDX_MAX_BIT_SHIFT)
1122 
1123 /*
1124  * MIN_BIT (RW)
1125  *
1126  * Lowest bit index
1127  */
1128 #define SEI_CTRL_CMD_IDX_MIN_BIT_MASK (0x1FU)
1129 #define SEI_CTRL_CMD_IDX_MIN_BIT_SHIFT (0U)
1130 #define SEI_CTRL_CMD_IDX_MIN_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_MIN_BIT_SHIFT) & SEI_CTRL_CMD_IDX_MIN_BIT_MASK)
1131 #define SEI_CTRL_CMD_IDX_MIN_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_MIN_BIT_MASK) >> SEI_CTRL_CMD_IDX_MIN_BIT_SHIFT)
1132 
1133 /* Bitfield definition for register of struct array CTRL: GOLD */
1134 /*
1135  * GOLD_VALUE (RW)
1136  *
1137  * Gold value for check mode
1138  */
1139 #define SEI_CTRL_CMD_GOLD_GOLD_VALUE_MASK (0xFFFFFFFFUL)
1140 #define SEI_CTRL_CMD_GOLD_GOLD_VALUE_SHIFT (0U)
1141 #define SEI_CTRL_CMD_GOLD_GOLD_VALUE_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_GOLD_GOLD_VALUE_SHIFT) & SEI_CTRL_CMD_GOLD_GOLD_VALUE_MASK)
1142 #define SEI_CTRL_CMD_GOLD_GOLD_VALUE_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_GOLD_GOLD_VALUE_MASK) >> SEI_CTRL_CMD_GOLD_GOLD_VALUE_SHIFT)
1143 
1144 /* Bitfield definition for register of struct array CTRL: CRCINIT */
1145 /*
1146  * CRC_INIT (RW)
1147  *
1148  * CRC initial value
1149  */
1150 #define SEI_CTRL_CMD_CRCINIT_CRC_INIT_MASK (0xFFFFFFFFUL)
1151 #define SEI_CTRL_CMD_CRCINIT_CRC_INIT_SHIFT (0U)
1152 #define SEI_CTRL_CMD_CRCINIT_CRC_INIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_CRCINIT_CRC_INIT_SHIFT) & SEI_CTRL_CMD_CRCINIT_CRC_INIT_MASK)
1153 #define SEI_CTRL_CMD_CRCINIT_CRC_INIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_CRCINIT_CRC_INIT_MASK) >> SEI_CTRL_CMD_CRCINIT_CRC_INIT_SHIFT)
1154 
1155 /* Bitfield definition for register of struct array CTRL: CRCPOLY */
1156 /*
1157  * CRC_POLY (RW)
1158  *
1159  * CRC polymonial
1160  */
1161 #define SEI_CTRL_CMD_CRCPOLY_CRC_POLY_MASK (0xFFFFFFFFUL)
1162 #define SEI_CTRL_CMD_CRCPOLY_CRC_POLY_SHIFT (0U)
1163 #define SEI_CTRL_CMD_CRCPOLY_CRC_POLY_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_CRCPOLY_CRC_POLY_SHIFT) & SEI_CTRL_CMD_CRCPOLY_CRC_POLY_MASK)
1164 #define SEI_CTRL_CMD_CRCPOLY_CRC_POLY_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_CRCPOLY_CRC_POLY_MASK) >> SEI_CTRL_CMD_CRCPOLY_CRC_POLY_SHIFT)
1165 
1166 /* Bitfield definition for register of struct array CTRL: CMD */
1167 /*
1168  * DATA (RW)
1169  *
1170  * DATA
1171  */
1172 #define SEI_CTRL_CMD_CMD_DATA_MASK (0xFFFFFFFFUL)
1173 #define SEI_CTRL_CMD_CMD_DATA_SHIFT (0U)
1174 #define SEI_CTRL_CMD_CMD_DATA_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_CMD_DATA_SHIFT) & SEI_CTRL_CMD_CMD_DATA_MASK)
1175 #define SEI_CTRL_CMD_CMD_DATA_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_CMD_DATA_MASK) >> SEI_CTRL_CMD_CMD_DATA_SHIFT)
1176 
1177 /* Bitfield definition for register of struct array CTRL: SET */
1178 /*
1179  * DATA_SET (RW)
1180  *
1181  * DATA bit set
1182  */
1183 #define SEI_CTRL_CMD_SET_DATA_SET_MASK (0xFFFFFFFFUL)
1184 #define SEI_CTRL_CMD_SET_DATA_SET_SHIFT (0U)
1185 #define SEI_CTRL_CMD_SET_DATA_SET_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_SET_DATA_SET_SHIFT) & SEI_CTRL_CMD_SET_DATA_SET_MASK)
1186 #define SEI_CTRL_CMD_SET_DATA_SET_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_SET_DATA_SET_MASK) >> SEI_CTRL_CMD_SET_DATA_SET_SHIFT)
1187 
1188 /* Bitfield definition for register of struct array CTRL: CLR */
1189 /*
1190  * DATA_CLR (RW)
1191  *
1192  * DATA bit clear
1193  */
1194 #define SEI_CTRL_CMD_CLR_DATA_CLR_MASK (0xFFFFFFFFUL)
1195 #define SEI_CTRL_CMD_CLR_DATA_CLR_SHIFT (0U)
1196 #define SEI_CTRL_CMD_CLR_DATA_CLR_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_CLR_DATA_CLR_SHIFT) & SEI_CTRL_CMD_CLR_DATA_CLR_MASK)
1197 #define SEI_CTRL_CMD_CLR_DATA_CLR_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_CLR_DATA_CLR_MASK) >> SEI_CTRL_CMD_CLR_DATA_CLR_SHIFT)
1198 
1199 /* Bitfield definition for register of struct array CTRL: INV */
1200 /*
1201  * DATA_TGL (RW)
1202  *
1203  * DATA bit toggle
1204  */
1205 #define SEI_CTRL_CMD_INV_DATA_TGL_MASK (0xFFFFFFFFUL)
1206 #define SEI_CTRL_CMD_INV_DATA_TGL_SHIFT (0U)
1207 #define SEI_CTRL_CMD_INV_DATA_TGL_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_INV_DATA_TGL_SHIFT) & SEI_CTRL_CMD_INV_DATA_TGL_MASK)
1208 #define SEI_CTRL_CMD_INV_DATA_TGL_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_INV_DATA_TGL_MASK) >> SEI_CTRL_CMD_INV_DATA_TGL_SHIFT)
1209 
1210 /* Bitfield definition for register of struct array CTRL: IN */
1211 /*
1212  * DATA_IN (RO)
1213  *
1214  * Commad input
1215  */
1216 #define SEI_CTRL_CMD_IN_DATA_IN_MASK (0xFFFFFFFFUL)
1217 #define SEI_CTRL_CMD_IN_DATA_IN_SHIFT (0U)
1218 #define SEI_CTRL_CMD_IN_DATA_IN_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IN_DATA_IN_MASK) >> SEI_CTRL_CMD_IN_DATA_IN_SHIFT)
1219 
1220 /* Bitfield definition for register of struct array CTRL: OUT */
1221 /*
1222  * DATA_OUT (RO)
1223  *
1224  * Command output
1225  */
1226 #define SEI_CTRL_CMD_OUT_DATA_OUT_MASK (0xFFFFFFFFUL)
1227 #define SEI_CTRL_CMD_OUT_DATA_OUT_SHIFT (0U)
1228 #define SEI_CTRL_CMD_OUT_DATA_OUT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_OUT_DATA_OUT_MASK) >> SEI_CTRL_CMD_OUT_DATA_OUT_SHIFT)
1229 
1230 /* Bitfield definition for register of struct array CTRL: STS */
1231 /*
1232  * CRC_IDX (RO)
1233  *
1234  * CRC index
1235  */
1236 #define SEI_CTRL_CMD_STS_CRC_IDX_MASK (0x1F000000UL)
1237 #define SEI_CTRL_CMD_STS_CRC_IDX_SHIFT (24U)
1238 #define SEI_CTRL_CMD_STS_CRC_IDX_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_STS_CRC_IDX_MASK) >> SEI_CTRL_CMD_STS_CRC_IDX_SHIFT)
1239 
1240 /*
1241  * WORD_IDX (RO)
1242  *
1243  * Word index
1244  */
1245 #define SEI_CTRL_CMD_STS_WORD_IDX_MASK (0x1F0000UL)
1246 #define SEI_CTRL_CMD_STS_WORD_IDX_SHIFT (16U)
1247 #define SEI_CTRL_CMD_STS_WORD_IDX_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_STS_WORD_IDX_MASK) >> SEI_CTRL_CMD_STS_WORD_IDX_SHIFT)
1248 
1249 /*
1250  * WORD_CNT (RO)
1251  *
1252  * Word counter
1253  */
1254 #define SEI_CTRL_CMD_STS_WORD_CNT_MASK (0x1F00U)
1255 #define SEI_CTRL_CMD_STS_WORD_CNT_SHIFT (8U)
1256 #define SEI_CTRL_CMD_STS_WORD_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_STS_WORD_CNT_MASK) >> SEI_CTRL_CMD_STS_WORD_CNT_SHIFT)
1257 
1258 /*
1259  * BIT_IDX (RO)
1260  *
1261  * Bit index
1262  */
1263 #define SEI_CTRL_CMD_STS_BIT_IDX_MASK (0x1FU)
1264 #define SEI_CTRL_CMD_STS_BIT_IDX_SHIFT (0U)
1265 #define SEI_CTRL_CMD_STS_BIT_IDX_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_STS_BIT_IDX_MASK) >> SEI_CTRL_CMD_STS_BIT_IDX_SHIFT)
1266 
1267 /* Bitfield definition for register of struct array CTRL: MIN */
1268 /*
1269  * CMD_MIN (RW)
1270  *
1271  * minimum command value
1272  */
1273 #define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_MASK (0xFFFFFFFFUL)
1274 #define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SHIFT (0U)
1275 #define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SHIFT) & SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_MASK)
1276 #define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_MASK) >> SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SHIFT)
1277 
1278 /* Bitfield definition for register of struct array CTRL: MAX */
1279 /*
1280  * CMD_MAX (RW)
1281  *
1282  * maximum command value
1283  */
1284 #define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_MASK (0xFFFFFFFFUL)
1285 #define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SHIFT (0U)
1286 #define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SHIFT) & SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_MASK)
1287 #define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_MASK) >> SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SHIFT)
1288 
1289 /* Bitfield definition for register of struct array CTRL: MSK */
1290 /*
1291  * CMD_MASK (RW)
1292  *
1293  * compare mask
1294  */
1295 #define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_MASK (0xFFFFFFFFUL)
1296 #define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SHIFT (0U)
1297 #define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SHIFT) & SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_MASK)
1298 #define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_MASK) >> SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SHIFT)
1299 
1300 /* Bitfield definition for register of struct array CTRL: PTA */
1301 /*
1302  * PTR3 (RW)
1303  *
1304  * pointer3
1305  */
1306 #define SEI_CTRL_CMD_TABLE_PTA_PTR3_MASK (0xFF000000UL)
1307 #define SEI_CTRL_CMD_TABLE_PTA_PTR3_SHIFT (24U)
1308 #define SEI_CTRL_CMD_TABLE_PTA_PTR3_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR3_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR3_MASK)
1309 #define SEI_CTRL_CMD_TABLE_PTA_PTR3_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR3_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR3_SHIFT)
1310 
1311 /*
1312  * PTR2 (RW)
1313  *
1314  * pointer2
1315  */
1316 #define SEI_CTRL_CMD_TABLE_PTA_PTR2_MASK (0xFF0000UL)
1317 #define SEI_CTRL_CMD_TABLE_PTA_PTR2_SHIFT (16U)
1318 #define SEI_CTRL_CMD_TABLE_PTA_PTR2_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR2_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR2_MASK)
1319 #define SEI_CTRL_CMD_TABLE_PTA_PTR2_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR2_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR2_SHIFT)
1320 
1321 /*
1322  * PTR1 (RW)
1323  *
1324  * pointer1
1325  */
1326 #define SEI_CTRL_CMD_TABLE_PTA_PTR1_MASK (0xFF00U)
1327 #define SEI_CTRL_CMD_TABLE_PTA_PTR1_SHIFT (8U)
1328 #define SEI_CTRL_CMD_TABLE_PTA_PTR1_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR1_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR1_MASK)
1329 #define SEI_CTRL_CMD_TABLE_PTA_PTR1_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR1_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR1_SHIFT)
1330 
1331 /*
1332  * PTR0 (RW)
1333  *
1334  * pointer0
1335  */
1336 #define SEI_CTRL_CMD_TABLE_PTA_PTR0_MASK (0xFFU)
1337 #define SEI_CTRL_CMD_TABLE_PTA_PTR0_SHIFT (0U)
1338 #define SEI_CTRL_CMD_TABLE_PTA_PTR0_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR0_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR0_MASK)
1339 #define SEI_CTRL_CMD_TABLE_PTA_PTR0_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR0_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR0_SHIFT)
1340 
1341 /* Bitfield definition for register of struct array CTRL: PTB */
1342 /*
1343  * PTR7 (RW)
1344  *
1345  * pointer7
1346  */
1347 #define SEI_CTRL_CMD_TABLE_PTB_PTR7_MASK (0xFF000000UL)
1348 #define SEI_CTRL_CMD_TABLE_PTB_PTR7_SHIFT (24U)
1349 #define SEI_CTRL_CMD_TABLE_PTB_PTR7_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR7_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR7_MASK)
1350 #define SEI_CTRL_CMD_TABLE_PTB_PTR7_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR7_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR7_SHIFT)
1351 
1352 /*
1353  * PTR6 (RW)
1354  *
1355  * pointer6
1356  */
1357 #define SEI_CTRL_CMD_TABLE_PTB_PTR6_MASK (0xFF0000UL)
1358 #define SEI_CTRL_CMD_TABLE_PTB_PTR6_SHIFT (16U)
1359 #define SEI_CTRL_CMD_TABLE_PTB_PTR6_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR6_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR6_MASK)
1360 #define SEI_CTRL_CMD_TABLE_PTB_PTR6_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR6_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR6_SHIFT)
1361 
1362 /*
1363  * PTR5 (RW)
1364  *
1365  * pointer5
1366  */
1367 #define SEI_CTRL_CMD_TABLE_PTB_PTR5_MASK (0xFF00U)
1368 #define SEI_CTRL_CMD_TABLE_PTB_PTR5_SHIFT (8U)
1369 #define SEI_CTRL_CMD_TABLE_PTB_PTR5_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR5_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR5_MASK)
1370 #define SEI_CTRL_CMD_TABLE_PTB_PTR5_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR5_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR5_SHIFT)
1371 
1372 /*
1373  * PTR4 (RW)
1374  *
1375  * pointer4
1376  */
1377 #define SEI_CTRL_CMD_TABLE_PTB_PTR4_MASK (0xFFU)
1378 #define SEI_CTRL_CMD_TABLE_PTB_PTR4_SHIFT (0U)
1379 #define SEI_CTRL_CMD_TABLE_PTB_PTR4_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR4_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR4_MASK)
1380 #define SEI_CTRL_CMD_TABLE_PTB_PTR4_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR4_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR4_SHIFT)
1381 
1382 /* Bitfield definition for register of struct array CTRL: PTC */
1383 /*
1384  * PTR11 (RW)
1385  *
1386  * pointer11
1387  */
1388 #define SEI_CTRL_CMD_TABLE_PTC_PTR11_MASK (0xFF000000UL)
1389 #define SEI_CTRL_CMD_TABLE_PTC_PTR11_SHIFT (24U)
1390 #define SEI_CTRL_CMD_TABLE_PTC_PTR11_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTC_PTR11_SHIFT) & SEI_CTRL_CMD_TABLE_PTC_PTR11_MASK)
1391 #define SEI_CTRL_CMD_TABLE_PTC_PTR11_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTC_PTR11_MASK) >> SEI_CTRL_CMD_TABLE_PTC_PTR11_SHIFT)
1392 
1393 /*
1394  * PTR10 (RW)
1395  *
1396  * pointer10
1397  */
1398 #define SEI_CTRL_CMD_TABLE_PTC_PTR10_MASK (0xFF0000UL)
1399 #define SEI_CTRL_CMD_TABLE_PTC_PTR10_SHIFT (16U)
1400 #define SEI_CTRL_CMD_TABLE_PTC_PTR10_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTC_PTR10_SHIFT) & SEI_CTRL_CMD_TABLE_PTC_PTR10_MASK)
1401 #define SEI_CTRL_CMD_TABLE_PTC_PTR10_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTC_PTR10_MASK) >> SEI_CTRL_CMD_TABLE_PTC_PTR10_SHIFT)
1402 
1403 /*
1404  * PTR9 (RW)
1405  *
1406  * pointer9
1407  */
1408 #define SEI_CTRL_CMD_TABLE_PTC_PTR9_MASK (0xFF00U)
1409 #define SEI_CTRL_CMD_TABLE_PTC_PTR9_SHIFT (8U)
1410 #define SEI_CTRL_CMD_TABLE_PTC_PTR9_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTC_PTR9_SHIFT) & SEI_CTRL_CMD_TABLE_PTC_PTR9_MASK)
1411 #define SEI_CTRL_CMD_TABLE_PTC_PTR9_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTC_PTR9_MASK) >> SEI_CTRL_CMD_TABLE_PTC_PTR9_SHIFT)
1412 
1413 /*
1414  * PTR8 (RW)
1415  *
1416  * pointer8
1417  */
1418 #define SEI_CTRL_CMD_TABLE_PTC_PTR8_MASK (0xFFU)
1419 #define SEI_CTRL_CMD_TABLE_PTC_PTR8_SHIFT (0U)
1420 #define SEI_CTRL_CMD_TABLE_PTC_PTR8_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTC_PTR8_SHIFT) & SEI_CTRL_CMD_TABLE_PTC_PTR8_MASK)
1421 #define SEI_CTRL_CMD_TABLE_PTC_PTR8_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTC_PTR8_MASK) >> SEI_CTRL_CMD_TABLE_PTC_PTR8_SHIFT)
1422 
1423 /* Bitfield definition for register of struct array CTRL: PTD */
1424 /*
1425  * PTR15 (RW)
1426  *
1427  * pointer15
1428  */
1429 #define SEI_CTRL_CMD_TABLE_PTD_PTR15_MASK (0xFF000000UL)
1430 #define SEI_CTRL_CMD_TABLE_PTD_PTR15_SHIFT (24U)
1431 #define SEI_CTRL_CMD_TABLE_PTD_PTR15_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTD_PTR15_SHIFT) & SEI_CTRL_CMD_TABLE_PTD_PTR15_MASK)
1432 #define SEI_CTRL_CMD_TABLE_PTD_PTR15_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTD_PTR15_MASK) >> SEI_CTRL_CMD_TABLE_PTD_PTR15_SHIFT)
1433 
1434 /*
1435  * PTR14 (RW)
1436  *
1437  * pointer14
1438  */
1439 #define SEI_CTRL_CMD_TABLE_PTD_PTR14_MASK (0xFF0000UL)
1440 #define SEI_CTRL_CMD_TABLE_PTD_PTR14_SHIFT (16U)
1441 #define SEI_CTRL_CMD_TABLE_PTD_PTR14_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTD_PTR14_SHIFT) & SEI_CTRL_CMD_TABLE_PTD_PTR14_MASK)
1442 #define SEI_CTRL_CMD_TABLE_PTD_PTR14_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTD_PTR14_MASK) >> SEI_CTRL_CMD_TABLE_PTD_PTR14_SHIFT)
1443 
1444 /*
1445  * PTR13 (RW)
1446  *
1447  * pointer13
1448  */
1449 #define SEI_CTRL_CMD_TABLE_PTD_PTR13_MASK (0xFF00U)
1450 #define SEI_CTRL_CMD_TABLE_PTD_PTR13_SHIFT (8U)
1451 #define SEI_CTRL_CMD_TABLE_PTD_PTR13_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTD_PTR13_SHIFT) & SEI_CTRL_CMD_TABLE_PTD_PTR13_MASK)
1452 #define SEI_CTRL_CMD_TABLE_PTD_PTR13_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTD_PTR13_MASK) >> SEI_CTRL_CMD_TABLE_PTD_PTR13_SHIFT)
1453 
1454 /*
1455  * PTR12 (RW)
1456  *
1457  * pointer12
1458  */
1459 #define SEI_CTRL_CMD_TABLE_PTD_PTR12_MASK (0xFFU)
1460 #define SEI_CTRL_CMD_TABLE_PTD_PTR12_SHIFT (0U)
1461 #define SEI_CTRL_CMD_TABLE_PTD_PTR12_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTD_PTR12_SHIFT) & SEI_CTRL_CMD_TABLE_PTD_PTR12_MASK)
1462 #define SEI_CTRL_CMD_TABLE_PTD_PTR12_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTD_PTR12_MASK) >> SEI_CTRL_CMD_TABLE_PTD_PTR12_SHIFT)
1463 
1464 /* Bitfield definition for register of struct array CTRL: 0_1 */
1465 /*
1466  * POINTER (RW)
1467  *
1468  * pointer
1469  */
1470 #define SEI_CTRL_LATCH_TRAN_POINTER_MASK (0xFF000000UL)
1471 #define SEI_CTRL_LATCH_TRAN_POINTER_SHIFT (24U)
1472 #define SEI_CTRL_LATCH_TRAN_POINTER_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_POINTER_SHIFT) & SEI_CTRL_LATCH_TRAN_POINTER_MASK)
1473 #define SEI_CTRL_LATCH_TRAN_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_POINTER_MASK) >> SEI_CTRL_LATCH_TRAN_POINTER_SHIFT)
1474 
1475 /*
1476  * CFG_TM (RW)
1477  *
1478  * timeout
1479  * 0: high
1480  * 1: low
1481  * 2: rise
1482  * 3: fall
1483  */
1484 #define SEI_CTRL_LATCH_TRAN_CFG_TM_MASK (0x30000UL)
1485 #define SEI_CTRL_LATCH_TRAN_CFG_TM_SHIFT (16U)
1486 #define SEI_CTRL_LATCH_TRAN_CFG_TM_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_TM_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_TM_MASK)
1487 #define SEI_CTRL_LATCH_TRAN_CFG_TM_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_TM_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_TM_SHIFT)
1488 
1489 /*
1490  * CFG_TXD (RW)
1491  *
1492  * data send
1493  * 0: high
1494  * 1: low
1495  * 2: rise
1496  * 3: fall
1497  */
1498 #define SEI_CTRL_LATCH_TRAN_CFG_TXD_MASK (0x3000U)
1499 #define SEI_CTRL_LATCH_TRAN_CFG_TXD_SHIFT (12U)
1500 #define SEI_CTRL_LATCH_TRAN_CFG_TXD_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_TXD_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_TXD_MASK)
1501 #define SEI_CTRL_LATCH_TRAN_CFG_TXD_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_TXD_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_TXD_SHIFT)
1502 
1503 /*
1504  * CFG_CLK (RW)
1505  *
1506  * clock
1507  * 0: high
1508  * 1: low
1509  * 2: rise
1510  * 3: fall
1511  */
1512 #define SEI_CTRL_LATCH_TRAN_CFG_CLK_MASK (0xC00U)
1513 #define SEI_CTRL_LATCH_TRAN_CFG_CLK_SHIFT (10U)
1514 #define SEI_CTRL_LATCH_TRAN_CFG_CLK_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_CLK_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_CLK_MASK)
1515 #define SEI_CTRL_LATCH_TRAN_CFG_CLK_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_CLK_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_CLK_SHIFT)
1516 
1517 /*
1518  * CFG_PTR (RW)
1519  *
1520  * pointer
1521  * 0: match
1522  * 1: not match
1523  * 2:entry
1524  * 3:leave
1525  */
1526 #define SEI_CTRL_LATCH_TRAN_CFG_PTR_MASK (0x300U)
1527 #define SEI_CTRL_LATCH_TRAN_CFG_PTR_SHIFT (8U)
1528 #define SEI_CTRL_LATCH_TRAN_CFG_PTR_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_PTR_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_PTR_MASK)
1529 #define SEI_CTRL_LATCH_TRAN_CFG_PTR_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_PTR_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_PTR_SHIFT)
1530 
1531 /*
1532  * OV_TM (RW)
1533  *
1534  * override timeout check
1535  */
1536 #define SEI_CTRL_LATCH_TRAN_OV_TM_MASK (0x10U)
1537 #define SEI_CTRL_LATCH_TRAN_OV_TM_SHIFT (4U)
1538 #define SEI_CTRL_LATCH_TRAN_OV_TM_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_TM_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_TM_MASK)
1539 #define SEI_CTRL_LATCH_TRAN_OV_TM_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_TM_MASK) >> SEI_CTRL_LATCH_TRAN_OV_TM_SHIFT)
1540 
1541 /*
1542  * OV_TXD (RW)
1543  *
1544  * override TX data check
1545  */
1546 #define SEI_CTRL_LATCH_TRAN_OV_TXD_MASK (0x4U)
1547 #define SEI_CTRL_LATCH_TRAN_OV_TXD_SHIFT (2U)
1548 #define SEI_CTRL_LATCH_TRAN_OV_TXD_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_TXD_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_TXD_MASK)
1549 #define SEI_CTRL_LATCH_TRAN_OV_TXD_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_TXD_MASK) >> SEI_CTRL_LATCH_TRAN_OV_TXD_SHIFT)
1550 
1551 /*
1552  * OV_CLK (RW)
1553  *
1554  * override clock check
1555  */
1556 #define SEI_CTRL_LATCH_TRAN_OV_CLK_MASK (0x2U)
1557 #define SEI_CTRL_LATCH_TRAN_OV_CLK_SHIFT (1U)
1558 #define SEI_CTRL_LATCH_TRAN_OV_CLK_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_CLK_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_CLK_MASK)
1559 #define SEI_CTRL_LATCH_TRAN_OV_CLK_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_CLK_MASK) >> SEI_CTRL_LATCH_TRAN_OV_CLK_SHIFT)
1560 
1561 /*
1562  * OV_PTR (RW)
1563  *
1564  * override pointer check
1565  */
1566 #define SEI_CTRL_LATCH_TRAN_OV_PTR_MASK (0x1U)
1567 #define SEI_CTRL_LATCH_TRAN_OV_PTR_SHIFT (0U)
1568 #define SEI_CTRL_LATCH_TRAN_OV_PTR_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_PTR_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_PTR_MASK)
1569 #define SEI_CTRL_LATCH_TRAN_OV_PTR_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_PTR_MASK) >> SEI_CTRL_LATCH_TRAN_OV_PTR_SHIFT)
1570 
1571 /* Bitfield definition for register of struct array CTRL: CFG */
1572 /*
1573  * EN (RW)
1574  *
1575  * Enable latch
1576  * 0: disable
1577  * 1: enable
1578  */
1579 #define SEI_CTRL_LATCH_CFG_EN_MASK (0x80000000UL)
1580 #define SEI_CTRL_LATCH_CFG_EN_SHIFT (31U)
1581 #define SEI_CTRL_LATCH_CFG_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_CFG_EN_SHIFT) & SEI_CTRL_LATCH_CFG_EN_MASK)
1582 #define SEI_CTRL_LATCH_CFG_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_CFG_EN_MASK) >> SEI_CTRL_LATCH_CFG_EN_SHIFT)
1583 
1584 /*
1585  * SELECT (RW)
1586  *
1587  * Output select
1588  * 0: state0-state1
1589  * 1: state1-state2
1590  * 2: state2-state3
1591  * 3: state3-state0
1592  */
1593 #define SEI_CTRL_LATCH_CFG_SELECT_MASK (0x7000000UL)
1594 #define SEI_CTRL_LATCH_CFG_SELECT_SHIFT (24U)
1595 #define SEI_CTRL_LATCH_CFG_SELECT_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_CFG_SELECT_SHIFT) & SEI_CTRL_LATCH_CFG_SELECT_MASK)
1596 #define SEI_CTRL_LATCH_CFG_SELECT_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_CFG_SELECT_MASK) >> SEI_CTRL_LATCH_CFG_SELECT_SHIFT)
1597 
1598 /*
1599  * DELAY (RW)
1600  *
1601  * Delay in system clock cycle, for state transition
1602  */
1603 #define SEI_CTRL_LATCH_CFG_DELAY_MASK (0xFFFFU)
1604 #define SEI_CTRL_LATCH_CFG_DELAY_SHIFT (0U)
1605 #define SEI_CTRL_LATCH_CFG_DELAY_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_CFG_DELAY_SHIFT) & SEI_CTRL_LATCH_CFG_DELAY_MASK)
1606 #define SEI_CTRL_LATCH_CFG_DELAY_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_CFG_DELAY_MASK) >> SEI_CTRL_LATCH_CFG_DELAY_SHIFT)
1607 
1608 /* Bitfield definition for register of struct array CTRL: TIME */
1609 /*
1610  * LAT_TIME (RO)
1611  *
1612  * Latch time
1613  */
1614 #define SEI_CTRL_LATCH_TIME_LAT_TIME_MASK (0xFFFFFFFFUL)
1615 #define SEI_CTRL_LATCH_TIME_LAT_TIME_SHIFT (0U)
1616 #define SEI_CTRL_LATCH_TIME_LAT_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TIME_LAT_TIME_MASK) >> SEI_CTRL_LATCH_TIME_LAT_TIME_SHIFT)
1617 
1618 /* Bitfield definition for register of struct array CTRL: STS */
1619 /*
1620  * STATE (RO)
1621  *
1622  * State
1623  */
1624 #define SEI_CTRL_LATCH_STS_STATE_MASK (0x7000000UL)
1625 #define SEI_CTRL_LATCH_STS_STATE_SHIFT (24U)
1626 #define SEI_CTRL_LATCH_STS_STATE_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_STS_STATE_MASK) >> SEI_CTRL_LATCH_STS_STATE_SHIFT)
1627 
1628 /*
1629  * LAT_CNT (RO)
1630  *
1631  * Latch counter
1632  */
1633 #define SEI_CTRL_LATCH_STS_LAT_CNT_MASK (0xFFFFU)
1634 #define SEI_CTRL_LATCH_STS_LAT_CNT_SHIFT (0U)
1635 #define SEI_CTRL_LATCH_STS_LAT_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_STS_LAT_CNT_MASK) >> SEI_CTRL_LATCH_STS_LAT_CNT_SHIFT)
1636 
1637 /* Bitfield definition for register of struct array CTRL: SMP_EN */
1638 /*
1639  * ACC_EN (RW)
1640  *
1641  * Position include acceleration
1642  */
1643 #define SEI_CTRL_POS_SMP_EN_ACC_EN_MASK (0x80000000UL)
1644 #define SEI_CTRL_POS_SMP_EN_ACC_EN_SHIFT (31U)
1645 #define SEI_CTRL_POS_SMP_EN_ACC_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_ACC_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_ACC_EN_MASK)
1646 #define SEI_CTRL_POS_SMP_EN_ACC_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_ACC_EN_MASK) >> SEI_CTRL_POS_SMP_EN_ACC_EN_SHIFT)
1647 
1648 /*
1649  * ACC_SEL (RW)
1650  *
1651  * Data register for acceleration transfer
1652  */
1653 #define SEI_CTRL_POS_SMP_EN_ACC_SEL_MASK (0x1F000000UL)
1654 #define SEI_CTRL_POS_SMP_EN_ACC_SEL_SHIFT (24U)
1655 #define SEI_CTRL_POS_SMP_EN_ACC_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_ACC_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_ACC_SEL_MASK)
1656 #define SEI_CTRL_POS_SMP_EN_ACC_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_ACC_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_ACC_SEL_SHIFT)
1657 
1658 /*
1659  * SPD_EN (RW)
1660  *
1661  * Position include speed
1662  */
1663 #define SEI_CTRL_POS_SMP_EN_SPD_EN_MASK (0x800000UL)
1664 #define SEI_CTRL_POS_SMP_EN_SPD_EN_SHIFT (23U)
1665 #define SEI_CTRL_POS_SMP_EN_SPD_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_SPD_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_SPD_EN_MASK)
1666 #define SEI_CTRL_POS_SMP_EN_SPD_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_SPD_EN_MASK) >> SEI_CTRL_POS_SMP_EN_SPD_EN_SHIFT)
1667 
1668 /*
1669  * SPD_SEL (RW)
1670  *
1671  * Data register for speed transfer
1672  */
1673 #define SEI_CTRL_POS_SMP_EN_SPD_SEL_MASK (0x1F0000UL)
1674 #define SEI_CTRL_POS_SMP_EN_SPD_SEL_SHIFT (16U)
1675 #define SEI_CTRL_POS_SMP_EN_SPD_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_SPD_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_SPD_SEL_MASK)
1676 #define SEI_CTRL_POS_SMP_EN_SPD_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_SPD_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_SPD_SEL_SHIFT)
1677 
1678 /*
1679  * REV_EN (RW)
1680  *
1681  * Position include revolution
1682  */
1683 #define SEI_CTRL_POS_SMP_EN_REV_EN_MASK (0x8000U)
1684 #define SEI_CTRL_POS_SMP_EN_REV_EN_SHIFT (15U)
1685 #define SEI_CTRL_POS_SMP_EN_REV_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_REV_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_REV_EN_MASK)
1686 #define SEI_CTRL_POS_SMP_EN_REV_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_REV_EN_MASK) >> SEI_CTRL_POS_SMP_EN_REV_EN_SHIFT)
1687 
1688 /*
1689  * REV_SEL (RW)
1690  *
1691  * Data register for revolution transfer
1692  */
1693 #define SEI_CTRL_POS_SMP_EN_REV_SEL_MASK (0x1F00U)
1694 #define SEI_CTRL_POS_SMP_EN_REV_SEL_SHIFT (8U)
1695 #define SEI_CTRL_POS_SMP_EN_REV_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_REV_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_REV_SEL_MASK)
1696 #define SEI_CTRL_POS_SMP_EN_REV_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_REV_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_REV_SEL_SHIFT)
1697 
1698 /*
1699  * POS_EN (RW)
1700  *
1701  * Position include position
1702  */
1703 #define SEI_CTRL_POS_SMP_EN_POS_EN_MASK (0x80U)
1704 #define SEI_CTRL_POS_SMP_EN_POS_EN_SHIFT (7U)
1705 #define SEI_CTRL_POS_SMP_EN_POS_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_POS_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_POS_EN_MASK)
1706 #define SEI_CTRL_POS_SMP_EN_POS_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_POS_EN_MASK) >> SEI_CTRL_POS_SMP_EN_POS_EN_SHIFT)
1707 
1708 /*
1709  * POS_SEL (RW)
1710  *
1711  * Data register for position transfer
1712  */
1713 #define SEI_CTRL_POS_SMP_EN_POS_SEL_MASK (0x1FU)
1714 #define SEI_CTRL_POS_SMP_EN_POS_SEL_SHIFT (0U)
1715 #define SEI_CTRL_POS_SMP_EN_POS_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_POS_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_POS_SEL_MASK)
1716 #define SEI_CTRL_POS_SMP_EN_POS_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_POS_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_POS_SEL_SHIFT)
1717 
1718 /* Bitfield definition for register of struct array CTRL: SMP_CFG */
1719 /*
1720  * ONCE (RW)
1721  *
1722  * Sample one time
1723  * 0: Sample during windows time
1724  * 1: Close sample window after first sample
1725  */
1726 #define SEI_CTRL_POS_SMP_CFG_ONCE_MASK (0x1000000UL)
1727 #define SEI_CTRL_POS_SMP_CFG_ONCE_SHIFT (24U)
1728 #define SEI_CTRL_POS_SMP_CFG_ONCE_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_CFG_ONCE_SHIFT) & SEI_CTRL_POS_SMP_CFG_ONCE_MASK)
1729 #define SEI_CTRL_POS_SMP_CFG_ONCE_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_CFG_ONCE_MASK) >> SEI_CTRL_POS_SMP_CFG_ONCE_SHIFT)
1730 
1731 /*
1732  * LAT_SEL (RW)
1733  *
1734  * Latch selection
1735  * 0: latch 0
1736  * 1: latch 1
1737  * 2: latch 2
1738  * 3: latch 3
1739  */
1740 #define SEI_CTRL_POS_SMP_CFG_LAT_SEL_MASK (0x30000UL)
1741 #define SEI_CTRL_POS_SMP_CFG_LAT_SEL_SHIFT (16U)
1742 #define SEI_CTRL_POS_SMP_CFG_LAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_CFG_LAT_SEL_SHIFT) & SEI_CTRL_POS_SMP_CFG_LAT_SEL_MASK)
1743 #define SEI_CTRL_POS_SMP_CFG_LAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_CFG_LAT_SEL_MASK) >> SEI_CTRL_POS_SMP_CFG_LAT_SEL_SHIFT)
1744 
1745 /*
1746  * WINDOW (RW)
1747  *
1748  * Sample window, in clock cycle
1749  */
1750 #define SEI_CTRL_POS_SMP_CFG_WINDOW_MASK (0xFFFFU)
1751 #define SEI_CTRL_POS_SMP_CFG_WINDOW_SHIFT (0U)
1752 #define SEI_CTRL_POS_SMP_CFG_WINDOW_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_CFG_WINDOW_SHIFT) & SEI_CTRL_POS_SMP_CFG_WINDOW_MASK)
1753 #define SEI_CTRL_POS_SMP_CFG_WINDOW_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_CFG_WINDOW_MASK) >> SEI_CTRL_POS_SMP_CFG_WINDOW_SHIFT)
1754 
1755 /* Bitfield definition for register of struct array CTRL: SMP_DAT */
1756 /*
1757  * DAT_SEL (RW)
1758  *
1759  * Data register sampled, each bit represent a data register
1760  */
1761 #define SEI_CTRL_POS_SMP_DAT_DAT_SEL_MASK (0xFFFFFFFFUL)
1762 #define SEI_CTRL_POS_SMP_DAT_DAT_SEL_SHIFT (0U)
1763 #define SEI_CTRL_POS_SMP_DAT_DAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_DAT_DAT_SEL_SHIFT) & SEI_CTRL_POS_SMP_DAT_DAT_SEL_MASK)
1764 #define SEI_CTRL_POS_SMP_DAT_DAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_DAT_DAT_SEL_MASK) >> SEI_CTRL_POS_SMP_DAT_DAT_SEL_SHIFT)
1765 
1766 /* Bitfield definition for register of struct array CTRL: SMP_POS */
1767 /*
1768  * POS (RW)
1769  *
1770  * Sample override position
1771  */
1772 #define SEI_CTRL_POS_SMP_POS_POS_MASK (0xFFFFFFFFUL)
1773 #define SEI_CTRL_POS_SMP_POS_POS_SHIFT (0U)
1774 #define SEI_CTRL_POS_SMP_POS_POS_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_POS_POS_SHIFT) & SEI_CTRL_POS_SMP_POS_POS_MASK)
1775 #define SEI_CTRL_POS_SMP_POS_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_POS_POS_MASK) >> SEI_CTRL_POS_SMP_POS_POS_SHIFT)
1776 
1777 /* Bitfield definition for register of struct array CTRL: SMP_REV */
1778 /*
1779  * REV (RW)
1780  *
1781  * Sample override revolution
1782  */
1783 #define SEI_CTRL_POS_SMP_REV_REV_MASK (0xFFFFFFFFUL)
1784 #define SEI_CTRL_POS_SMP_REV_REV_SHIFT (0U)
1785 #define SEI_CTRL_POS_SMP_REV_REV_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_REV_REV_SHIFT) & SEI_CTRL_POS_SMP_REV_REV_MASK)
1786 #define SEI_CTRL_POS_SMP_REV_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_REV_REV_MASK) >> SEI_CTRL_POS_SMP_REV_REV_SHIFT)
1787 
1788 /* Bitfield definition for register of struct array CTRL: SMP_SPD */
1789 /*
1790  * SPD (RW)
1791  *
1792  * Sample override speed
1793  */
1794 #define SEI_CTRL_POS_SMP_SPD_SPD_MASK (0xFFFFFFFFUL)
1795 #define SEI_CTRL_POS_SMP_SPD_SPD_SHIFT (0U)
1796 #define SEI_CTRL_POS_SMP_SPD_SPD_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_SPD_SPD_SHIFT) & SEI_CTRL_POS_SMP_SPD_SPD_MASK)
1797 #define SEI_CTRL_POS_SMP_SPD_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_SPD_SPD_MASK) >> SEI_CTRL_POS_SMP_SPD_SPD_SHIFT)
1798 
1799 /* Bitfield definition for register of struct array CTRL: SMP_ACC */
1800 /*
1801  * ACC (RW)
1802  *
1803  * Sample override accelerate
1804  */
1805 #define SEI_CTRL_POS_SMP_ACC_ACC_MASK (0xFFFFFFFFUL)
1806 #define SEI_CTRL_POS_SMP_ACC_ACC_SHIFT (0U)
1807 #define SEI_CTRL_POS_SMP_ACC_ACC_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_ACC_ACC_SHIFT) & SEI_CTRL_POS_SMP_ACC_ACC_MASK)
1808 #define SEI_CTRL_POS_SMP_ACC_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_ACC_ACC_MASK) >> SEI_CTRL_POS_SMP_ACC_ACC_SHIFT)
1809 
1810 /* Bitfield definition for register of struct array CTRL: UPD_EN */
1811 /*
1812  * ACC_EN (RW)
1813  *
1814  * Position include acceleration
1815  */
1816 #define SEI_CTRL_POS_UPD_EN_ACC_EN_MASK (0x80000000UL)
1817 #define SEI_CTRL_POS_UPD_EN_ACC_EN_SHIFT (31U)
1818 #define SEI_CTRL_POS_UPD_EN_ACC_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_ACC_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_ACC_EN_MASK)
1819 #define SEI_CTRL_POS_UPD_EN_ACC_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_ACC_EN_MASK) >> SEI_CTRL_POS_UPD_EN_ACC_EN_SHIFT)
1820 
1821 /*
1822  * ACC_SEL (RW)
1823  *
1824  * Data register for acceleration transfer
1825  */
1826 #define SEI_CTRL_POS_UPD_EN_ACC_SEL_MASK (0x1F000000UL)
1827 #define SEI_CTRL_POS_UPD_EN_ACC_SEL_SHIFT (24U)
1828 #define SEI_CTRL_POS_UPD_EN_ACC_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_ACC_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_ACC_SEL_MASK)
1829 #define SEI_CTRL_POS_UPD_EN_ACC_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_ACC_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_ACC_SEL_SHIFT)
1830 
1831 /*
1832  * SPD_EN (RW)
1833  *
1834  * Position include speed
1835  */
1836 #define SEI_CTRL_POS_UPD_EN_SPD_EN_MASK (0x800000UL)
1837 #define SEI_CTRL_POS_UPD_EN_SPD_EN_SHIFT (23U)
1838 #define SEI_CTRL_POS_UPD_EN_SPD_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_SPD_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_SPD_EN_MASK)
1839 #define SEI_CTRL_POS_UPD_EN_SPD_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_SPD_EN_MASK) >> SEI_CTRL_POS_UPD_EN_SPD_EN_SHIFT)
1840 
1841 /*
1842  * SPD_SEL (RW)
1843  *
1844  * Data register for speed transfer
1845  */
1846 #define SEI_CTRL_POS_UPD_EN_SPD_SEL_MASK (0x1F0000UL)
1847 #define SEI_CTRL_POS_UPD_EN_SPD_SEL_SHIFT (16U)
1848 #define SEI_CTRL_POS_UPD_EN_SPD_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_SPD_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_SPD_SEL_MASK)
1849 #define SEI_CTRL_POS_UPD_EN_SPD_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_SPD_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_SPD_SEL_SHIFT)
1850 
1851 /*
1852  * REV_EN (RW)
1853  *
1854  * Position include revolution
1855  */
1856 #define SEI_CTRL_POS_UPD_EN_REV_EN_MASK (0x8000U)
1857 #define SEI_CTRL_POS_UPD_EN_REV_EN_SHIFT (15U)
1858 #define SEI_CTRL_POS_UPD_EN_REV_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_REV_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_REV_EN_MASK)
1859 #define SEI_CTRL_POS_UPD_EN_REV_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_REV_EN_MASK) >> SEI_CTRL_POS_UPD_EN_REV_EN_SHIFT)
1860 
1861 /*
1862  * REV_SEL (RW)
1863  *
1864  * Data register for revolution transfer
1865  */
1866 #define SEI_CTRL_POS_UPD_EN_REV_SEL_MASK (0x1F00U)
1867 #define SEI_CTRL_POS_UPD_EN_REV_SEL_SHIFT (8U)
1868 #define SEI_CTRL_POS_UPD_EN_REV_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_REV_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_REV_SEL_MASK)
1869 #define SEI_CTRL_POS_UPD_EN_REV_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_REV_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_REV_SEL_SHIFT)
1870 
1871 /*
1872  * POS_EN (RW)
1873  *
1874  * Position include position
1875  */
1876 #define SEI_CTRL_POS_UPD_EN_POS_EN_MASK (0x80U)
1877 #define SEI_CTRL_POS_UPD_EN_POS_EN_SHIFT (7U)
1878 #define SEI_CTRL_POS_UPD_EN_POS_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_POS_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_POS_EN_MASK)
1879 #define SEI_CTRL_POS_UPD_EN_POS_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_POS_EN_MASK) >> SEI_CTRL_POS_UPD_EN_POS_EN_SHIFT)
1880 
1881 /*
1882  * POS_SEL (RW)
1883  *
1884  * Data register for position transfer
1885  */
1886 #define SEI_CTRL_POS_UPD_EN_POS_SEL_MASK (0x1FU)
1887 #define SEI_CTRL_POS_UPD_EN_POS_SEL_SHIFT (0U)
1888 #define SEI_CTRL_POS_UPD_EN_POS_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_POS_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_POS_SEL_MASK)
1889 #define SEI_CTRL_POS_UPD_EN_POS_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_POS_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_POS_SEL_SHIFT)
1890 
1891 /* Bitfield definition for register of struct array CTRL: UPD_CFG */
1892 /*
1893  * TIME_OVRD (RW)
1894  *
1895  * Use override time
1896  * 0: use time sample from motor group
1897  * 1: use override time
1898  */
1899 #define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_MASK (0x80000000UL)
1900 #define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SHIFT (31U)
1901 #define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SHIFT) & SEI_CTRL_POS_UPD_CFG_TIME_OVRD_MASK)
1902 #define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_CFG_TIME_OVRD_MASK) >> SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SHIFT)
1903 
1904 /*
1905  * ONERR (RW)
1906  *
1907  * Sample one time
1908  * 0: Sample during windows time
1909  * 1: Close sample window after first sample
1910  */
1911 #define SEI_CTRL_POS_UPD_CFG_ONERR_MASK (0x1000000UL)
1912 #define SEI_CTRL_POS_UPD_CFG_ONERR_SHIFT (24U)
1913 #define SEI_CTRL_POS_UPD_CFG_ONERR_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_CFG_ONERR_SHIFT) & SEI_CTRL_POS_UPD_CFG_ONERR_MASK)
1914 #define SEI_CTRL_POS_UPD_CFG_ONERR_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_CFG_ONERR_MASK) >> SEI_CTRL_POS_UPD_CFG_ONERR_SHIFT)
1915 
1916 /*
1917  * LAT_SEL (RW)
1918  *
1919  * Latch selection
1920  * 0: latch 0
1921  * 1: latch 1
1922  * 2: latch 2
1923  * 3: latch 3
1924  */
1925 #define SEI_CTRL_POS_UPD_CFG_LAT_SEL_MASK (0x30000UL)
1926 #define SEI_CTRL_POS_UPD_CFG_LAT_SEL_SHIFT (16U)
1927 #define SEI_CTRL_POS_UPD_CFG_LAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_CFG_LAT_SEL_SHIFT) & SEI_CTRL_POS_UPD_CFG_LAT_SEL_MASK)
1928 #define SEI_CTRL_POS_UPD_CFG_LAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_CFG_LAT_SEL_MASK) >> SEI_CTRL_POS_UPD_CFG_LAT_SEL_SHIFT)
1929 
1930 /* Bitfield definition for register of struct array CTRL: UPD_DAT */
1931 /*
1932  * DAT_SEL (RW)
1933  *
1934  * Data register sampled, each bit represent a data register
1935  */
1936 #define SEI_CTRL_POS_UPD_DAT_DAT_SEL_MASK (0xFFFFFFFFUL)
1937 #define SEI_CTRL_POS_UPD_DAT_DAT_SEL_SHIFT (0U)
1938 #define SEI_CTRL_POS_UPD_DAT_DAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_DAT_DAT_SEL_SHIFT) & SEI_CTRL_POS_UPD_DAT_DAT_SEL_MASK)
1939 #define SEI_CTRL_POS_UPD_DAT_DAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_DAT_DAT_SEL_MASK) >> SEI_CTRL_POS_UPD_DAT_DAT_SEL_SHIFT)
1940 
1941 /* Bitfield definition for register of struct array CTRL: UPD_TIME */
1942 /*
1943  * TIME (RW)
1944  *
1945  * Update override time
1946  */
1947 #define SEI_CTRL_POS_UPD_TIME_TIME_MASK (0xFFFFFFFFUL)
1948 #define SEI_CTRL_POS_UPD_TIME_TIME_SHIFT (0U)
1949 #define SEI_CTRL_POS_UPD_TIME_TIME_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_TIME_TIME_SHIFT) & SEI_CTRL_POS_UPD_TIME_TIME_MASK)
1950 #define SEI_CTRL_POS_UPD_TIME_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_TIME_TIME_MASK) >> SEI_CTRL_POS_UPD_TIME_TIME_SHIFT)
1951 
1952 /* Bitfield definition for register of struct array CTRL: UPD_POS */
1953 /*
1954  * POS (RW)
1955  *
1956  * Update override position
1957  */
1958 #define SEI_CTRL_POS_UPD_POS_POS_MASK (0xFFFFFFFFUL)
1959 #define SEI_CTRL_POS_UPD_POS_POS_SHIFT (0U)
1960 #define SEI_CTRL_POS_UPD_POS_POS_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_POS_POS_SHIFT) & SEI_CTRL_POS_UPD_POS_POS_MASK)
1961 #define SEI_CTRL_POS_UPD_POS_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_POS_POS_MASK) >> SEI_CTRL_POS_UPD_POS_POS_SHIFT)
1962 
1963 /* Bitfield definition for register of struct array CTRL: UPD_REV */
1964 /*
1965  * REV (RW)
1966  *
1967  * Update override revolution
1968  */
1969 #define SEI_CTRL_POS_UPD_REV_REV_MASK (0xFFFFFFFFUL)
1970 #define SEI_CTRL_POS_UPD_REV_REV_SHIFT (0U)
1971 #define SEI_CTRL_POS_UPD_REV_REV_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_REV_REV_SHIFT) & SEI_CTRL_POS_UPD_REV_REV_MASK)
1972 #define SEI_CTRL_POS_UPD_REV_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_REV_REV_MASK) >> SEI_CTRL_POS_UPD_REV_REV_SHIFT)
1973 
1974 /* Bitfield definition for register of struct array CTRL: UPD_SPD */
1975 /*
1976  * SPD (RW)
1977  *
1978  * Update override speed
1979  */
1980 #define SEI_CTRL_POS_UPD_SPD_SPD_MASK (0xFFFFFFFFUL)
1981 #define SEI_CTRL_POS_UPD_SPD_SPD_SHIFT (0U)
1982 #define SEI_CTRL_POS_UPD_SPD_SPD_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_SPD_SPD_SHIFT) & SEI_CTRL_POS_UPD_SPD_SPD_MASK)
1983 #define SEI_CTRL_POS_UPD_SPD_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_SPD_SPD_MASK) >> SEI_CTRL_POS_UPD_SPD_SPD_SHIFT)
1984 
1985 /* Bitfield definition for register of struct array CTRL: UPD_ACC */
1986 /*
1987  * ACC (RW)
1988  *
1989  * Update override accelerate
1990  */
1991 #define SEI_CTRL_POS_UPD_ACC_ACC_MASK (0xFFFFFFFFUL)
1992 #define SEI_CTRL_POS_UPD_ACC_ACC_SHIFT (0U)
1993 #define SEI_CTRL_POS_UPD_ACC_ACC_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_ACC_ACC_SHIFT) & SEI_CTRL_POS_UPD_ACC_ACC_MASK)
1994 #define SEI_CTRL_POS_UPD_ACC_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_ACC_ACC_MASK) >> SEI_CTRL_POS_UPD_ACC_ACC_SHIFT)
1995 
1996 /* Bitfield definition for register of struct array CTRL: SMP_VAL */
1997 /*
1998  * ACC (RO)
1999  *
2000  * Position include acceleration
2001  */
2002 #define SEI_CTRL_POS_SMP_VAL_ACC_MASK (0x80000000UL)
2003 #define SEI_CTRL_POS_SMP_VAL_ACC_SHIFT (31U)
2004 #define SEI_CTRL_POS_SMP_VAL_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_ACC_MASK) >> SEI_CTRL_POS_SMP_VAL_ACC_SHIFT)
2005 
2006 /*
2007  * SPD (RO)
2008  *
2009  * Position include speed
2010  */
2011 #define SEI_CTRL_POS_SMP_VAL_SPD_MASK (0x800000UL)
2012 #define SEI_CTRL_POS_SMP_VAL_SPD_SHIFT (23U)
2013 #define SEI_CTRL_POS_SMP_VAL_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_SPD_MASK) >> SEI_CTRL_POS_SMP_VAL_SPD_SHIFT)
2014 
2015 /*
2016  * REV (RO)
2017  *
2018  * Position include revolution
2019  */
2020 #define SEI_CTRL_POS_SMP_VAL_REV_MASK (0x8000U)
2021 #define SEI_CTRL_POS_SMP_VAL_REV_SHIFT (15U)
2022 #define SEI_CTRL_POS_SMP_VAL_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_REV_MASK) >> SEI_CTRL_POS_SMP_VAL_REV_SHIFT)
2023 
2024 /*
2025  * POS (RO)
2026  *
2027  * Position include position
2028  */
2029 #define SEI_CTRL_POS_SMP_VAL_POS_MASK (0x80U)
2030 #define SEI_CTRL_POS_SMP_VAL_POS_SHIFT (7U)
2031 #define SEI_CTRL_POS_SMP_VAL_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_POS_MASK) >> SEI_CTRL_POS_SMP_VAL_POS_SHIFT)
2032 
2033 /* Bitfield definition for register of struct array CTRL: SMP_STS */
2034 /*
2035  * OCCUR (RO)
2036  *
2037  * Sample occured
2038  * 0: Sample not happened
2039  * 1: Sample occured
2040  */
2041 #define SEI_CTRL_POS_SMP_STS_OCCUR_MASK (0x1000000UL)
2042 #define SEI_CTRL_POS_SMP_STS_OCCUR_SHIFT (24U)
2043 #define SEI_CTRL_POS_SMP_STS_OCCUR_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_STS_OCCUR_MASK) >> SEI_CTRL_POS_SMP_STS_OCCUR_SHIFT)
2044 
2045 /*
2046  * WIN_CNT (RO)
2047  *
2048  * Sample window counter
2049  */
2050 #define SEI_CTRL_POS_SMP_STS_WIN_CNT_MASK (0xFFFFU)
2051 #define SEI_CTRL_POS_SMP_STS_WIN_CNT_SHIFT (0U)
2052 #define SEI_CTRL_POS_SMP_STS_WIN_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_STS_WIN_CNT_MASK) >> SEI_CTRL_POS_SMP_STS_WIN_CNT_SHIFT)
2053 
2054 /* Bitfield definition for register of struct array CTRL: TIME_IN */
2055 /*
2056  * TIME (RO)
2057  *
2058  * input time
2059  */
2060 #define SEI_CTRL_POS_TIME_IN_TIME_MASK (0xFFFFFFFFUL)
2061 #define SEI_CTRL_POS_TIME_IN_TIME_SHIFT (0U)
2062 #define SEI_CTRL_POS_TIME_IN_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_TIME_IN_TIME_MASK) >> SEI_CTRL_POS_TIME_IN_TIME_SHIFT)
2063 
2064 /* Bitfield definition for register of struct array CTRL: POS_IN */
2065 /*
2066  * POS (RO)
2067  *
2068  * Input position
2069  */
2070 #define SEI_CTRL_POS_POS_IN_POS_MASK (0xFFFFFFFFUL)
2071 #define SEI_CTRL_POS_POS_IN_POS_SHIFT (0U)
2072 #define SEI_CTRL_POS_POS_IN_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_POS_IN_POS_MASK) >> SEI_CTRL_POS_POS_IN_POS_SHIFT)
2073 
2074 /* Bitfield definition for register of struct array CTRL: REV_IN */
2075 /*
2076  * REV (RO)
2077  *
2078  * Input revolution
2079  */
2080 #define SEI_CTRL_POS_REV_IN_REV_MASK (0xFFFFFFFFUL)
2081 #define SEI_CTRL_POS_REV_IN_REV_SHIFT (0U)
2082 #define SEI_CTRL_POS_REV_IN_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_REV_IN_REV_MASK) >> SEI_CTRL_POS_REV_IN_REV_SHIFT)
2083 
2084 /* Bitfield definition for register of struct array CTRL: SPD_IN */
2085 /*
2086  * SPD (RO)
2087  *
2088  * Input speed
2089  */
2090 #define SEI_CTRL_POS_SPD_IN_SPD_MASK (0xFFFFFFFFUL)
2091 #define SEI_CTRL_POS_SPD_IN_SPD_SHIFT (0U)
2092 #define SEI_CTRL_POS_SPD_IN_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SPD_IN_SPD_MASK) >> SEI_CTRL_POS_SPD_IN_SPD_SHIFT)
2093 
2094 /* Bitfield definition for register of struct array CTRL: ACC_IN */
2095 /*
2096  * ACC (RO)
2097  *
2098  * Input accelerate
2099  */
2100 #define SEI_CTRL_POS_ACC_IN_ACC_MASK (0xFFFFFFFFUL)
2101 #define SEI_CTRL_POS_ACC_IN_ACC_SHIFT (0U)
2102 #define SEI_CTRL_POS_ACC_IN_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_ACC_IN_ACC_MASK) >> SEI_CTRL_POS_ACC_IN_ACC_SHIFT)
2103 
2104 /* Bitfield definition for register of struct array CTRL: UPD_STS */
2105 /*
2106  * UPD_ERR (RO)
2107  *
2108  * Update error
2109  * 0: data receive normally
2110  * 1: data receive error
2111  */
2112 #define SEI_CTRL_POS_UPD_STS_UPD_ERR_MASK (0x1000000UL)
2113 #define SEI_CTRL_POS_UPD_STS_UPD_ERR_SHIFT (24U)
2114 #define SEI_CTRL_POS_UPD_STS_UPD_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_STS_UPD_ERR_MASK) >> SEI_CTRL_POS_UPD_STS_UPD_ERR_SHIFT)
2115 
2116 /* Bitfield definition for register of struct array CTRL: INT_EN */
2117 /*
2118  * TRG_ERR3 (RW)
2119  *
2120  * Trigger3 failed
2121  */
2122 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_MASK (0x80000000UL)
2123 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SHIFT (31U)
2124 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR3_MASK)
2125 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR3_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SHIFT)
2126 
2127 /*
2128  * TRG_ERR2 (RW)
2129  *
2130  * Trigger2 failed
2131  */
2132 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_MASK (0x40000000UL)
2133 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SHIFT (30U)
2134 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR2_MASK)
2135 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR2_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SHIFT)
2136 
2137 /*
2138  * TRG_ERR1 (RW)
2139  *
2140  * Trigger1 failed
2141  */
2142 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_MASK (0x20000000UL)
2143 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SHIFT (29U)
2144 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR1_MASK)
2145 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR1_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SHIFT)
2146 
2147 /*
2148  * TRG_ERR0 (RW)
2149  *
2150  * Trigger0 failed
2151  */
2152 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_MASK (0x10000000UL)
2153 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SHIFT (28U)
2154 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR0_MASK)
2155 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR0_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SHIFT)
2156 
2157 /*
2158  * TRIGER3 (RW)
2159  *
2160  * Trigger3
2161  */
2162 #define SEI_CTRL_IRQ_INT_EN_TRIGER3_MASK (0x8000000UL)
2163 #define SEI_CTRL_IRQ_INT_EN_TRIGER3_SHIFT (27U)
2164 #define SEI_CTRL_IRQ_INT_EN_TRIGER3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER3_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER3_MASK)
2165 #define SEI_CTRL_IRQ_INT_EN_TRIGER3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER3_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER3_SHIFT)
2166 
2167 /*
2168  * TRIGER2 (RW)
2169  *
2170  * Trigger2
2171  */
2172 #define SEI_CTRL_IRQ_INT_EN_TRIGER2_MASK (0x4000000UL)
2173 #define SEI_CTRL_IRQ_INT_EN_TRIGER2_SHIFT (26U)
2174 #define SEI_CTRL_IRQ_INT_EN_TRIGER2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER2_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER2_MASK)
2175 #define SEI_CTRL_IRQ_INT_EN_TRIGER2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER2_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER2_SHIFT)
2176 
2177 /*
2178  * TRIGER1 (RW)
2179  *
2180  * Trigger1
2181  */
2182 #define SEI_CTRL_IRQ_INT_EN_TRIGER1_MASK (0x2000000UL)
2183 #define SEI_CTRL_IRQ_INT_EN_TRIGER1_SHIFT (25U)
2184 #define SEI_CTRL_IRQ_INT_EN_TRIGER1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER1_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER1_MASK)
2185 #define SEI_CTRL_IRQ_INT_EN_TRIGER1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER1_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER1_SHIFT)
2186 
2187 /*
2188  * TRIGER0 (RW)
2189  *
2190  * Trigger0
2191  */
2192 #define SEI_CTRL_IRQ_INT_EN_TRIGER0_MASK (0x1000000UL)
2193 #define SEI_CTRL_IRQ_INT_EN_TRIGER0_SHIFT (24U)
2194 #define SEI_CTRL_IRQ_INT_EN_TRIGER0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER0_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER0_MASK)
2195 #define SEI_CTRL_IRQ_INT_EN_TRIGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER0_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER0_SHIFT)
2196 
2197 /*
2198  * SMP_ERR (RW)
2199  *
2200  * Sample error
2201  */
2202 #define SEI_CTRL_IRQ_INT_EN_SMP_ERR_MASK (0x100000UL)
2203 #define SEI_CTRL_IRQ_INT_EN_SMP_ERR_SHIFT (20U)
2204 #define SEI_CTRL_IRQ_INT_EN_SMP_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_SMP_ERR_SHIFT) & SEI_CTRL_IRQ_INT_EN_SMP_ERR_MASK)
2205 #define SEI_CTRL_IRQ_INT_EN_SMP_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_SMP_ERR_MASK) >> SEI_CTRL_IRQ_INT_EN_SMP_ERR_SHIFT)
2206 
2207 /*
2208  * LATCH3 (RW)
2209  *
2210  * Latch3
2211  */
2212 #define SEI_CTRL_IRQ_INT_EN_LATCH3_MASK (0x80000UL)
2213 #define SEI_CTRL_IRQ_INT_EN_LATCH3_SHIFT (19U)
2214 #define SEI_CTRL_IRQ_INT_EN_LATCH3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH3_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH3_MASK)
2215 #define SEI_CTRL_IRQ_INT_EN_LATCH3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH3_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH3_SHIFT)
2216 
2217 /*
2218  * LATCH2 (RW)
2219  *
2220  * Latch2
2221  */
2222 #define SEI_CTRL_IRQ_INT_EN_LATCH2_MASK (0x40000UL)
2223 #define SEI_CTRL_IRQ_INT_EN_LATCH2_SHIFT (18U)
2224 #define SEI_CTRL_IRQ_INT_EN_LATCH2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH2_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH2_MASK)
2225 #define SEI_CTRL_IRQ_INT_EN_LATCH2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH2_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH2_SHIFT)
2226 
2227 /*
2228  * LATCH1 (RW)
2229  *
2230  * Latch1
2231  */
2232 #define SEI_CTRL_IRQ_INT_EN_LATCH1_MASK (0x20000UL)
2233 #define SEI_CTRL_IRQ_INT_EN_LATCH1_SHIFT (17U)
2234 #define SEI_CTRL_IRQ_INT_EN_LATCH1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH1_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH1_MASK)
2235 #define SEI_CTRL_IRQ_INT_EN_LATCH1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH1_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH1_SHIFT)
2236 
2237 /*
2238  * LATCH0 (RW)
2239  *
2240  * Latch0
2241  */
2242 #define SEI_CTRL_IRQ_INT_EN_LATCH0_MASK (0x10000UL)
2243 #define SEI_CTRL_IRQ_INT_EN_LATCH0_SHIFT (16U)
2244 #define SEI_CTRL_IRQ_INT_EN_LATCH0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH0_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH0_MASK)
2245 #define SEI_CTRL_IRQ_INT_EN_LATCH0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH0_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH0_SHIFT)
2246 
2247 /*
2248  * TIMEOUT (RW)
2249  *
2250  * Timeout
2251  */
2252 #define SEI_CTRL_IRQ_INT_EN_TIMEOUT_MASK (0x2000U)
2253 #define SEI_CTRL_IRQ_INT_EN_TIMEOUT_SHIFT (13U)
2254 #define SEI_CTRL_IRQ_INT_EN_TIMEOUT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TIMEOUT_SHIFT) & SEI_CTRL_IRQ_INT_EN_TIMEOUT_MASK)
2255 #define SEI_CTRL_IRQ_INT_EN_TIMEOUT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TIMEOUT_MASK) >> SEI_CTRL_IRQ_INT_EN_TIMEOUT_SHIFT)
2256 
2257 /*
2258  * TRX_ERR (RW)
2259  *
2260  * Transfer error
2261  */
2262 #define SEI_CTRL_IRQ_INT_EN_TRX_ERR_MASK (0x1000U)
2263 #define SEI_CTRL_IRQ_INT_EN_TRX_ERR_SHIFT (12U)
2264 #define SEI_CTRL_IRQ_INT_EN_TRX_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRX_ERR_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRX_ERR_MASK)
2265 #define SEI_CTRL_IRQ_INT_EN_TRX_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRX_ERR_MASK) >> SEI_CTRL_IRQ_INT_EN_TRX_ERR_SHIFT)
2266 
2267 /*
2268  * INSTR1_END (RW)
2269  *
2270  * Instruction 1 end
2271  */
2272 #define SEI_CTRL_IRQ_INT_EN_INSTR1_END_MASK (0x800U)
2273 #define SEI_CTRL_IRQ_INT_EN_INSTR1_END_SHIFT (11U)
2274 #define SEI_CTRL_IRQ_INT_EN_INSTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR1_END_MASK)
2275 #define SEI_CTRL_IRQ_INT_EN_INSTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR1_END_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR1_END_SHIFT)
2276 
2277 /*
2278  * INSTR0_END (RW)
2279  *
2280  * Instruction 0 end
2281  */
2282 #define SEI_CTRL_IRQ_INT_EN_INSTR0_END_MASK (0x400U)
2283 #define SEI_CTRL_IRQ_INT_EN_INSTR0_END_SHIFT (10U)
2284 #define SEI_CTRL_IRQ_INT_EN_INSTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR0_END_MASK)
2285 #define SEI_CTRL_IRQ_INT_EN_INSTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR0_END_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR0_END_SHIFT)
2286 
2287 /*
2288  * PTR1_END (RW)
2289  *
2290  * Pointer 1 end
2291  */
2292 #define SEI_CTRL_IRQ_INT_EN_PTR1_END_MASK (0x200U)
2293 #define SEI_CTRL_IRQ_INT_EN_PTR1_END_SHIFT (9U)
2294 #define SEI_CTRL_IRQ_INT_EN_PTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR1_END_MASK)
2295 #define SEI_CTRL_IRQ_INT_EN_PTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR1_END_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR1_END_SHIFT)
2296 
2297 /*
2298  * PTR0_END (RW)
2299  *
2300  * Pointer 0 end
2301  */
2302 #define SEI_CTRL_IRQ_INT_EN_PTR0_END_MASK (0x100U)
2303 #define SEI_CTRL_IRQ_INT_EN_PTR0_END_SHIFT (8U)
2304 #define SEI_CTRL_IRQ_INT_EN_PTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR0_END_MASK)
2305 #define SEI_CTRL_IRQ_INT_EN_PTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR0_END_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR0_END_SHIFT)
2306 
2307 /*
2308  * INSTR1_ST (RW)
2309  *
2310  * Instruction 1 start
2311  */
2312 #define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_MASK (0x80U)
2313 #define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SHIFT (7U)
2314 #define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR1_ST_MASK)
2315 #define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SHIFT)
2316 
2317 /*
2318  * INSTR0_ST (RW)
2319  *
2320  * Instruction 0 start
2321  */
2322 #define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_MASK (0x40U)
2323 #define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SHIFT (6U)
2324 #define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR0_ST_MASK)
2325 #define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SHIFT)
2326 
2327 /*
2328  * PTR1_ST (RW)
2329  *
2330  * Pointer 1 start
2331  */
2332 #define SEI_CTRL_IRQ_INT_EN_PTR1_ST_MASK (0x20U)
2333 #define SEI_CTRL_IRQ_INT_EN_PTR1_ST_SHIFT (5U)
2334 #define SEI_CTRL_IRQ_INT_EN_PTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR1_ST_MASK)
2335 #define SEI_CTRL_IRQ_INT_EN_PTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR1_ST_SHIFT)
2336 
2337 /*
2338  * PTR0_ST (RW)
2339  *
2340  * Pointer 0 start
2341  */
2342 #define SEI_CTRL_IRQ_INT_EN_PTR0_ST_MASK (0x10U)
2343 #define SEI_CTRL_IRQ_INT_EN_PTR0_ST_SHIFT (4U)
2344 #define SEI_CTRL_IRQ_INT_EN_PTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR0_ST_MASK)
2345 #define SEI_CTRL_IRQ_INT_EN_PTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR0_ST_SHIFT)
2346 
2347 /*
2348  * WDOG (RW)
2349  *
2350  * Watch dog
2351  */
2352 #define SEI_CTRL_IRQ_INT_EN_WDOG_MASK (0x4U)
2353 #define SEI_CTRL_IRQ_INT_EN_WDOG_SHIFT (2U)
2354 #define SEI_CTRL_IRQ_INT_EN_WDOG_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_WDOG_SHIFT) & SEI_CTRL_IRQ_INT_EN_WDOG_MASK)
2355 #define SEI_CTRL_IRQ_INT_EN_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_WDOG_MASK) >> SEI_CTRL_IRQ_INT_EN_WDOG_SHIFT)
2356 
2357 /*
2358  * EXECPT (RW)
2359  *
2360  * Exception
2361  */
2362 #define SEI_CTRL_IRQ_INT_EN_EXECPT_MASK (0x2U)
2363 #define SEI_CTRL_IRQ_INT_EN_EXECPT_SHIFT (1U)
2364 #define SEI_CTRL_IRQ_INT_EN_EXECPT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_EXECPT_SHIFT) & SEI_CTRL_IRQ_INT_EN_EXECPT_MASK)
2365 #define SEI_CTRL_IRQ_INT_EN_EXECPT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_EXECPT_MASK) >> SEI_CTRL_IRQ_INT_EN_EXECPT_SHIFT)
2366 
2367 /*
2368  * STALL (RW)
2369  *
2370  * Stall
2371  */
2372 #define SEI_CTRL_IRQ_INT_EN_STALL_MASK (0x1U)
2373 #define SEI_CTRL_IRQ_INT_EN_STALL_SHIFT (0U)
2374 #define SEI_CTRL_IRQ_INT_EN_STALL_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_STALL_SHIFT) & SEI_CTRL_IRQ_INT_EN_STALL_MASK)
2375 #define SEI_CTRL_IRQ_INT_EN_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_STALL_MASK) >> SEI_CTRL_IRQ_INT_EN_STALL_SHIFT)
2376 
2377 /* Bitfield definition for register of struct array CTRL: INT_FLAG */
2378 /*
2379  * TRG_ERR3 (W1C)
2380  *
2381  * Trigger3 failed
2382  */
2383 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_MASK (0x80000000UL)
2384 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SHIFT (31U)
2385 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_MASK)
2386 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SHIFT)
2387 
2388 /*
2389  * TRG_ERR2 (W1C)
2390  *
2391  * Trigger2 failed
2392  */
2393 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_MASK (0x40000000UL)
2394 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SHIFT (30U)
2395 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_MASK)
2396 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SHIFT)
2397 
2398 /*
2399  * TRG_ERR1 (W1C)
2400  *
2401  * Trigger1 failed
2402  */
2403 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_MASK (0x20000000UL)
2404 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SHIFT (29U)
2405 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_MASK)
2406 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SHIFT)
2407 
2408 /*
2409  * TRG_ERR0 (W1C)
2410  *
2411  * Trigger0 failed
2412  */
2413 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_MASK (0x10000000UL)
2414 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SHIFT (28U)
2415 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_MASK)
2416 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SHIFT)
2417 
2418 /*
2419  * TRIGER3 (W1C)
2420  *
2421  * Trigger3
2422  */
2423 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_MASK (0x8000000UL)
2424 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SHIFT (27U)
2425 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER3_MASK)
2426 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER3_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SHIFT)
2427 
2428 /*
2429  * TRIGER2 (W1C)
2430  *
2431  * Trigger2
2432  */
2433 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_MASK (0x4000000UL)
2434 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SHIFT (26U)
2435 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER2_MASK)
2436 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER2_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SHIFT)
2437 
2438 /*
2439  * TRIGER1 (W1C)
2440  *
2441  * Trigger1
2442  */
2443 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_MASK (0x2000000UL)
2444 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SHIFT (25U)
2445 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER1_MASK)
2446 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER1_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SHIFT)
2447 
2448 /*
2449  * TRIGER0 (W1C)
2450  *
2451  * Trigger0
2452  */
2453 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_MASK (0x1000000UL)
2454 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SHIFT (24U)
2455 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER0_MASK)
2456 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER0_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SHIFT)
2457 
2458 /*
2459  * SMP_ERR (W1C)
2460  *
2461  * Sample error
2462  */
2463 #define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_MASK (0x100000UL)
2464 #define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SHIFT (20U)
2465 #define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_MASK)
2466 #define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_MASK) >> SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SHIFT)
2467 
2468 /*
2469  * LATCH3 (W1C)
2470  *
2471  * Latch3
2472  */
2473 #define SEI_CTRL_IRQ_INT_FLAG_LATCH3_MASK (0x80000UL)
2474 #define SEI_CTRL_IRQ_INT_FLAG_LATCH3_SHIFT (19U)
2475 #define SEI_CTRL_IRQ_INT_FLAG_LATCH3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH3_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH3_MASK)
2476 #define SEI_CTRL_IRQ_INT_FLAG_LATCH3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH3_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH3_SHIFT)
2477 
2478 /*
2479  * LATCH2 (W1C)
2480  *
2481  * Latch2
2482  */
2483 #define SEI_CTRL_IRQ_INT_FLAG_LATCH2_MASK (0x40000UL)
2484 #define SEI_CTRL_IRQ_INT_FLAG_LATCH2_SHIFT (18U)
2485 #define SEI_CTRL_IRQ_INT_FLAG_LATCH2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH2_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH2_MASK)
2486 #define SEI_CTRL_IRQ_INT_FLAG_LATCH2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH2_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH2_SHIFT)
2487 
2488 /*
2489  * LATCH1 (W1C)
2490  *
2491  * Latch1
2492  */
2493 #define SEI_CTRL_IRQ_INT_FLAG_LATCH1_MASK (0x20000UL)
2494 #define SEI_CTRL_IRQ_INT_FLAG_LATCH1_SHIFT (17U)
2495 #define SEI_CTRL_IRQ_INT_FLAG_LATCH1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH1_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH1_MASK)
2496 #define SEI_CTRL_IRQ_INT_FLAG_LATCH1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH1_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH1_SHIFT)
2497 
2498 /*
2499  * LATCH0 (W1C)
2500  *
2501  * Latch0
2502  */
2503 #define SEI_CTRL_IRQ_INT_FLAG_LATCH0_MASK (0x10000UL)
2504 #define SEI_CTRL_IRQ_INT_FLAG_LATCH0_SHIFT (16U)
2505 #define SEI_CTRL_IRQ_INT_FLAG_LATCH0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH0_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH0_MASK)
2506 #define SEI_CTRL_IRQ_INT_FLAG_LATCH0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH0_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH0_SHIFT)
2507 
2508 /*
2509  * TIMEOUT (W1C)
2510  *
2511  * Timeout
2512  */
2513 #define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_MASK (0x2000U)
2514 #define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SHIFT (13U)
2515 #define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_MASK)
2516 #define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SHIFT)
2517 
2518 /*
2519  * TRX_ERR (W1C)
2520  *
2521  * Transfer error
2522  */
2523 #define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_MASK (0x1000U)
2524 #define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SHIFT (12U)
2525 #define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_MASK)
2526 #define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SHIFT)
2527 
2528 /*
2529  * INSTR1_END (W1C)
2530  *
2531  * Instruction 1 end
2532  */
2533 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_MASK (0x800U)
2534 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SHIFT (11U)
2535 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_MASK)
2536 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SHIFT)
2537 
2538 /*
2539  * INSTR0_END (W1C)
2540  *
2541  * Instruction 0 end
2542  */
2543 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_MASK (0x400U)
2544 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SHIFT (10U)
2545 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_MASK)
2546 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SHIFT)
2547 
2548 /*
2549  * PTR1_END (W1C)
2550  *
2551  * Pointer 1 end
2552  */
2553 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_MASK (0x200U)
2554 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SHIFT (9U)
2555 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR1_END_MASK)
2556 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR1_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SHIFT)
2557 
2558 /*
2559  * PTR0_END (W1C)
2560  *
2561  * Pointer 0 end
2562  */
2563 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_MASK (0x100U)
2564 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SHIFT (8U)
2565 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR0_END_MASK)
2566 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR0_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SHIFT)
2567 
2568 /*
2569  * INSTR1_ST (W1C)
2570  *
2571  * Instruction 1 start
2572  */
2573 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_MASK (0x80U)
2574 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SHIFT (7U)
2575 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_MASK)
2576 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SHIFT)
2577 
2578 /*
2579  * INSTR0_ST (W1C)
2580  *
2581  * Instruction 0 start
2582  */
2583 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_MASK (0x40U)
2584 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SHIFT (6U)
2585 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_MASK)
2586 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SHIFT)
2587 
2588 /*
2589  * PTR1_ST (W1C)
2590  *
2591  * Pointer 1 start
2592  */
2593 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_MASK (0x20U)
2594 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SHIFT (5U)
2595 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_MASK)
2596 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SHIFT)
2597 
2598 /*
2599  * PTR0_ST (W1C)
2600  *
2601  * Pointer 0 start
2602  */
2603 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_MASK (0x10U)
2604 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SHIFT (4U)
2605 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_MASK)
2606 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SHIFT)
2607 
2608 /*
2609  * WDOG (W1C)
2610  *
2611  * Watch dog
2612  */
2613 #define SEI_CTRL_IRQ_INT_FLAG_WDOG_MASK (0x4U)
2614 #define SEI_CTRL_IRQ_INT_FLAG_WDOG_SHIFT (2U)
2615 #define SEI_CTRL_IRQ_INT_FLAG_WDOG_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_WDOG_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_WDOG_MASK)
2616 #define SEI_CTRL_IRQ_INT_FLAG_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_WDOG_MASK) >> SEI_CTRL_IRQ_INT_FLAG_WDOG_SHIFT)
2617 
2618 /*
2619  * EXECPT (W1C)
2620  *
2621  * Exception
2622  */
2623 #define SEI_CTRL_IRQ_INT_FLAG_EXECPT_MASK (0x2U)
2624 #define SEI_CTRL_IRQ_INT_FLAG_EXECPT_SHIFT (1U)
2625 #define SEI_CTRL_IRQ_INT_FLAG_EXECPT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_EXECPT_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_EXECPT_MASK)
2626 #define SEI_CTRL_IRQ_INT_FLAG_EXECPT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_EXECPT_MASK) >> SEI_CTRL_IRQ_INT_FLAG_EXECPT_SHIFT)
2627 
2628 /*
2629  * STALL (W1C)
2630  *
2631  * Stall
2632  */
2633 #define SEI_CTRL_IRQ_INT_FLAG_STALL_MASK (0x1U)
2634 #define SEI_CTRL_IRQ_INT_FLAG_STALL_SHIFT (0U)
2635 #define SEI_CTRL_IRQ_INT_FLAG_STALL_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_STALL_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_STALL_MASK)
2636 #define SEI_CTRL_IRQ_INT_FLAG_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_STALL_MASK) >> SEI_CTRL_IRQ_INT_FLAG_STALL_SHIFT)
2637 
2638 /* Bitfield definition for register of struct array CTRL: INT_STS */
2639 /*
2640  * TRG_ERR3 (RO)
2641  *
2642  * Trigger3 failed
2643  */
2644 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR3_MASK (0x80000000UL)
2645 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR3_SHIFT (31U)
2646 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR3_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR3_SHIFT)
2647 
2648 /*
2649  * TRG_ERR2 (RO)
2650  *
2651  * Trigger2 failed
2652  */
2653 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR2_MASK (0x40000000UL)
2654 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR2_SHIFT (30U)
2655 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR2_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR2_SHIFT)
2656 
2657 /*
2658  * TRG_ERR1 (RO)
2659  *
2660  * Trigger1 failed
2661  */
2662 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR1_MASK (0x20000000UL)
2663 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR1_SHIFT (29U)
2664 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR1_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR1_SHIFT)
2665 
2666 /*
2667  * TRG_ERR0 (RO)
2668  *
2669  * Trigger0 failed
2670  */
2671 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR0_MASK (0x10000000UL)
2672 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR0_SHIFT (28U)
2673 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR0_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR0_SHIFT)
2674 
2675 /*
2676  * TRIGER3 (RO)
2677  *
2678  * Trigger3
2679  */
2680 #define SEI_CTRL_IRQ_INT_STS_TRIGER3_MASK (0x8000000UL)
2681 #define SEI_CTRL_IRQ_INT_STS_TRIGER3_SHIFT (27U)
2682 #define SEI_CTRL_IRQ_INT_STS_TRIGER3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER3_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER3_SHIFT)
2683 
2684 /*
2685  * TRIGER2 (RO)
2686  *
2687  * Trigger2
2688  */
2689 #define SEI_CTRL_IRQ_INT_STS_TRIGER2_MASK (0x4000000UL)
2690 #define SEI_CTRL_IRQ_INT_STS_TRIGER2_SHIFT (26U)
2691 #define SEI_CTRL_IRQ_INT_STS_TRIGER2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER2_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER2_SHIFT)
2692 
2693 /*
2694  * TRIGER1 (RO)
2695  *
2696  * Trigger1
2697  */
2698 #define SEI_CTRL_IRQ_INT_STS_TRIGER1_MASK (0x2000000UL)
2699 #define SEI_CTRL_IRQ_INT_STS_TRIGER1_SHIFT (25U)
2700 #define SEI_CTRL_IRQ_INT_STS_TRIGER1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER1_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER1_SHIFT)
2701 
2702 /*
2703  * TRIGER0 (RO)
2704  *
2705  * Trigger0
2706  */
2707 #define SEI_CTRL_IRQ_INT_STS_TRIGER0_MASK (0x1000000UL)
2708 #define SEI_CTRL_IRQ_INT_STS_TRIGER0_SHIFT (24U)
2709 #define SEI_CTRL_IRQ_INT_STS_TRIGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER0_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER0_SHIFT)
2710 
2711 /*
2712  * SMP_ERR (RO)
2713  *
2714  * Sample error
2715  */
2716 #define SEI_CTRL_IRQ_INT_STS_SMP_ERR_MASK (0x100000UL)
2717 #define SEI_CTRL_IRQ_INT_STS_SMP_ERR_SHIFT (20U)
2718 #define SEI_CTRL_IRQ_INT_STS_SMP_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_SMP_ERR_MASK) >> SEI_CTRL_IRQ_INT_STS_SMP_ERR_SHIFT)
2719 
2720 /*
2721  * LATCH3 (RO)
2722  *
2723  * Latch3
2724  */
2725 #define SEI_CTRL_IRQ_INT_STS_LATCH3_MASK (0x80000UL)
2726 #define SEI_CTRL_IRQ_INT_STS_LATCH3_SHIFT (19U)
2727 #define SEI_CTRL_IRQ_INT_STS_LATCH3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH3_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH3_SHIFT)
2728 
2729 /*
2730  * LATCH2 (RO)
2731  *
2732  * Latch2
2733  */
2734 #define SEI_CTRL_IRQ_INT_STS_LATCH2_MASK (0x40000UL)
2735 #define SEI_CTRL_IRQ_INT_STS_LATCH2_SHIFT (18U)
2736 #define SEI_CTRL_IRQ_INT_STS_LATCH2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH2_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH2_SHIFT)
2737 
2738 /*
2739  * LATCH1 (RO)
2740  *
2741  * Latch1
2742  */
2743 #define SEI_CTRL_IRQ_INT_STS_LATCH1_MASK (0x20000UL)
2744 #define SEI_CTRL_IRQ_INT_STS_LATCH1_SHIFT (17U)
2745 #define SEI_CTRL_IRQ_INT_STS_LATCH1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH1_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH1_SHIFT)
2746 
2747 /*
2748  * LATCH0 (RO)
2749  *
2750  * Latch0
2751  */
2752 #define SEI_CTRL_IRQ_INT_STS_LATCH0_MASK (0x10000UL)
2753 #define SEI_CTRL_IRQ_INT_STS_LATCH0_SHIFT (16U)
2754 #define SEI_CTRL_IRQ_INT_STS_LATCH0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH0_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH0_SHIFT)
2755 
2756 /*
2757  * TIMEOUT (RO)
2758  *
2759  * Timeout
2760  */
2761 #define SEI_CTRL_IRQ_INT_STS_TIMEOUT_MASK (0x2000U)
2762 #define SEI_CTRL_IRQ_INT_STS_TIMEOUT_SHIFT (13U)
2763 #define SEI_CTRL_IRQ_INT_STS_TIMEOUT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TIMEOUT_MASK) >> SEI_CTRL_IRQ_INT_STS_TIMEOUT_SHIFT)
2764 
2765 /*
2766  * TRX_ERR (RO)
2767  *
2768  * Transfer error
2769  */
2770 #define SEI_CTRL_IRQ_INT_STS_TRX_ERR_MASK (0x1000U)
2771 #define SEI_CTRL_IRQ_INT_STS_TRX_ERR_SHIFT (12U)
2772 #define SEI_CTRL_IRQ_INT_STS_TRX_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRX_ERR_MASK) >> SEI_CTRL_IRQ_INT_STS_TRX_ERR_SHIFT)
2773 
2774 /*
2775  * INSTR1_END (RO)
2776  *
2777  * Instruction 1 end
2778  */
2779 #define SEI_CTRL_IRQ_INT_STS_INSTR1_END_MASK (0x800U)
2780 #define SEI_CTRL_IRQ_INT_STS_INSTR1_END_SHIFT (11U)
2781 #define SEI_CTRL_IRQ_INT_STS_INSTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR1_END_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR1_END_SHIFT)
2782 
2783 /*
2784  * INSTR0_END (RO)
2785  *
2786  * Instruction 0 end
2787  */
2788 #define SEI_CTRL_IRQ_INT_STS_INSTR0_END_MASK (0x400U)
2789 #define SEI_CTRL_IRQ_INT_STS_INSTR0_END_SHIFT (10U)
2790 #define SEI_CTRL_IRQ_INT_STS_INSTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR0_END_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR0_END_SHIFT)
2791 
2792 /*
2793  * PTR1_END (RO)
2794  *
2795  * Pointer 1 end
2796  */
2797 #define SEI_CTRL_IRQ_INT_STS_PTR1_END_MASK (0x200U)
2798 #define SEI_CTRL_IRQ_INT_STS_PTR1_END_SHIFT (9U)
2799 #define SEI_CTRL_IRQ_INT_STS_PTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR1_END_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR1_END_SHIFT)
2800 
2801 /*
2802  * PTR0_END (RO)
2803  *
2804  * Pointer 0 end
2805  */
2806 #define SEI_CTRL_IRQ_INT_STS_PTR0_END_MASK (0x100U)
2807 #define SEI_CTRL_IRQ_INT_STS_PTR0_END_SHIFT (8U)
2808 #define SEI_CTRL_IRQ_INT_STS_PTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR0_END_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR0_END_SHIFT)
2809 
2810 /*
2811  * INSTR1_ST (RO)
2812  *
2813  * Instruction 1 start
2814  */
2815 #define SEI_CTRL_IRQ_INT_STS_INSTR1_ST_MASK (0x80U)
2816 #define SEI_CTRL_IRQ_INT_STS_INSTR1_ST_SHIFT (7U)
2817 #define SEI_CTRL_IRQ_INT_STS_INSTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR1_ST_SHIFT)
2818 
2819 /*
2820  * INSTR0_ST (RO)
2821  *
2822  * Instruction 0 start
2823  */
2824 #define SEI_CTRL_IRQ_INT_STS_INSTR0_ST_MASK (0x40U)
2825 #define SEI_CTRL_IRQ_INT_STS_INSTR0_ST_SHIFT (6U)
2826 #define SEI_CTRL_IRQ_INT_STS_INSTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR0_ST_SHIFT)
2827 
2828 /*
2829  * PTR1_ST (RO)
2830  *
2831  * Pointer 1 start
2832  */
2833 #define SEI_CTRL_IRQ_INT_STS_PTR1_ST_MASK (0x20U)
2834 #define SEI_CTRL_IRQ_INT_STS_PTR1_ST_SHIFT (5U)
2835 #define SEI_CTRL_IRQ_INT_STS_PTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR1_ST_SHIFT)
2836 
2837 /*
2838  * PTR0_ST (RO)
2839  *
2840  * Pointer 0 start
2841  */
2842 #define SEI_CTRL_IRQ_INT_STS_PTR0_ST_MASK (0x10U)
2843 #define SEI_CTRL_IRQ_INT_STS_PTR0_ST_SHIFT (4U)
2844 #define SEI_CTRL_IRQ_INT_STS_PTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR0_ST_SHIFT)
2845 
2846 /*
2847  * WDOG (RO)
2848  *
2849  * Watch dog
2850  */
2851 #define SEI_CTRL_IRQ_INT_STS_WDOG_MASK (0x4U)
2852 #define SEI_CTRL_IRQ_INT_STS_WDOG_SHIFT (2U)
2853 #define SEI_CTRL_IRQ_INT_STS_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_WDOG_MASK) >> SEI_CTRL_IRQ_INT_STS_WDOG_SHIFT)
2854 
2855 /*
2856  * EXECPT (RO)
2857  *
2858  * Exception
2859  */
2860 #define SEI_CTRL_IRQ_INT_STS_EXECPT_MASK (0x2U)
2861 #define SEI_CTRL_IRQ_INT_STS_EXECPT_SHIFT (1U)
2862 #define SEI_CTRL_IRQ_INT_STS_EXECPT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_EXECPT_MASK) >> SEI_CTRL_IRQ_INT_STS_EXECPT_SHIFT)
2863 
2864 /*
2865  * STALL (RO)
2866  *
2867  * Stall
2868  */
2869 #define SEI_CTRL_IRQ_INT_STS_STALL_MASK (0x1U)
2870 #define SEI_CTRL_IRQ_INT_STS_STALL_SHIFT (0U)
2871 #define SEI_CTRL_IRQ_INT_STS_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_STALL_MASK) >> SEI_CTRL_IRQ_INT_STS_STALL_SHIFT)
2872 
2873 /* Bitfield definition for register of struct array CTRL: POINTER0 */
2874 /*
2875  * POINTER (RW)
2876  *
2877  * Match pointer 0
2878  */
2879 #define SEI_CTRL_IRQ_POINTER0_POINTER_MASK (0xFFU)
2880 #define SEI_CTRL_IRQ_POINTER0_POINTER_SHIFT (0U)
2881 #define SEI_CTRL_IRQ_POINTER0_POINTER_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_POINTER0_POINTER_SHIFT) & SEI_CTRL_IRQ_POINTER0_POINTER_MASK)
2882 #define SEI_CTRL_IRQ_POINTER0_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_POINTER0_POINTER_MASK) >> SEI_CTRL_IRQ_POINTER0_POINTER_SHIFT)
2883 
2884 /* Bitfield definition for register of struct array CTRL: POINTER1 */
2885 /*
2886  * POINTER (RW)
2887  *
2888  * Match pointer 1
2889  */
2890 #define SEI_CTRL_IRQ_POINTER1_POINTER_MASK (0xFFU)
2891 #define SEI_CTRL_IRQ_POINTER1_POINTER_SHIFT (0U)
2892 #define SEI_CTRL_IRQ_POINTER1_POINTER_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_POINTER1_POINTER_SHIFT) & SEI_CTRL_IRQ_POINTER1_POINTER_MASK)
2893 #define SEI_CTRL_IRQ_POINTER1_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_POINTER1_POINTER_MASK) >> SEI_CTRL_IRQ_POINTER1_POINTER_SHIFT)
2894 
2895 /* Bitfield definition for register of struct array CTRL: INSTR0 */
2896 /*
2897  * INSTR (RW)
2898  *
2899  * Match instruction 0
2900  */
2901 #define SEI_CTRL_IRQ_INSTR0_INSTR_MASK (0xFFFFFFFFUL)
2902 #define SEI_CTRL_IRQ_INSTR0_INSTR_SHIFT (0U)
2903 #define SEI_CTRL_IRQ_INSTR0_INSTR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INSTR0_INSTR_SHIFT) & SEI_CTRL_IRQ_INSTR0_INSTR_MASK)
2904 #define SEI_CTRL_IRQ_INSTR0_INSTR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INSTR0_INSTR_MASK) >> SEI_CTRL_IRQ_INSTR0_INSTR_SHIFT)
2905 
2906 /* Bitfield definition for register of struct array CTRL: INSTR1 */
2907 /*
2908  * INSTR (RW)
2909  *
2910  * Match instruction 1
2911  */
2912 #define SEI_CTRL_IRQ_INSTR1_INSTR_MASK (0xFFFFFFFFUL)
2913 #define SEI_CTRL_IRQ_INSTR1_INSTR_SHIFT (0U)
2914 #define SEI_CTRL_IRQ_INSTR1_INSTR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INSTR1_INSTR_SHIFT) & SEI_CTRL_IRQ_INSTR1_INSTR_MASK)
2915 #define SEI_CTRL_IRQ_INSTR1_INSTR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INSTR1_INSTR_MASK) >> SEI_CTRL_IRQ_INSTR1_INSTR_SHIFT)
2916 
2917 /* Bitfield definition for register array: INSTR */
2918 /*
2919  * OP (RW)
2920  *
2921  * operation
2922  * 0: halt
2923  * 1: jump
2924  * 2: send with timeout check
2925  * 3: send without timout check
2926  * 4: wait with timeout check
2927  * 5: wait without timout check
2928  * 6: receive with timeout check
2929  * 7: receive without timout check
2930  */
2931 #define SEI_INSTR_OP_MASK (0x1C000000UL)
2932 #define SEI_INSTR_OP_SHIFT (26U)
2933 #define SEI_INSTR_OP_SET(x) (((uint32_t)(x) << SEI_INSTR_OP_SHIFT) & SEI_INSTR_OP_MASK)
2934 #define SEI_INSTR_OP_GET(x) (((uint32_t)(x) & SEI_INSTR_OP_MASK) >> SEI_INSTR_OP_SHIFT)
2935 
2936 /*
2937  * CK (RW)
2938  *
2939  * clock
2940  * 0: low
2941  * 1: rise-fall
2942  * 2: fall-rise
2943  * 3: high
2944  */
2945 #define SEI_INSTR_CK_MASK (0x3000000UL)
2946 #define SEI_INSTR_CK_SHIFT (24U)
2947 #define SEI_INSTR_CK_SET(x) (((uint32_t)(x) << SEI_INSTR_CK_SHIFT) & SEI_INSTR_CK_MASK)
2948 #define SEI_INSTR_CK_GET(x) (((uint32_t)(x) & SEI_INSTR_CK_MASK) >> SEI_INSTR_CK_SHIFT)
2949 
2950 /*
2951  * CRC (RW)
2952  *
2953  * CRC register
2954  * 0: don't calculate CRC
2955  * 1: do not set this value
2956  * 2: data register 2
2957  * 3: data register 3
2958  * ...
2959  * 29: data register 29
2960  * 30: value 0 when send, wait 0 in receive
2961  * 31: value1 when send, wait 1 in receive
2962  */
2963 #define SEI_INSTR_CRC_MASK (0x1F0000UL)
2964 #define SEI_INSTR_CRC_SHIFT (16U)
2965 #define SEI_INSTR_CRC_SET(x) (((uint32_t)(x) << SEI_INSTR_CRC_SHIFT) & SEI_INSTR_CRC_MASK)
2966 #define SEI_INSTR_CRC_GET(x) (((uint32_t)(x) & SEI_INSTR_CRC_MASK) >> SEI_INSTR_CRC_SHIFT)
2967 
2968 /*
2969  * DAT (RW)
2970  *
2971  * DATA register
2972  * 0: ignore data
2973  * 1: command
2974  * 2: data register 2
2975  * 3: data register 3
2976  * ...
2977  * 29: data register 29
2978  * 30: value 0 when send, wait 0 in receive
2979  * 31: value1 when send, wait 1 in receive
2980  */
2981 #define SEI_INSTR_DAT_MASK (0x1F00U)
2982 #define SEI_INSTR_DAT_SHIFT (8U)
2983 #define SEI_INSTR_DAT_SET(x) (((uint32_t)(x) << SEI_INSTR_DAT_SHIFT) & SEI_INSTR_DAT_MASK)
2984 #define SEI_INSTR_DAT_GET(x) (((uint32_t)(x) & SEI_INSTR_DAT_MASK) >> SEI_INSTR_DAT_SHIFT)
2985 
2986 /*
2987  * OPR (RW)
2988  *
2989  * [1] When OP is 0, this area is the halt time in baudrate, 0 represents infinite time.
2990  * [2] When OP is 1, this area is the the pointer to the command table.
2991  * OPR[4]=1, OPR[3:0] value is CMD_TABLE instruct pointer;
2992  * OPR[4]=0, OPR[3:0]=0 is INIT_POINTER;
2993  * OPR[4]=0, OPR[3:0]=1 is WDG_POINTER.
2994  * [3] When OP is 2-7, this area is the data length as fellow:
2995  * 0: 1 bit
2996  * 1: 2 bit
2997  * ...
2998  * 31: 32 bit
2999  */
3000 #define SEI_INSTR_OPR_MASK (0x1FU)
3001 #define SEI_INSTR_OPR_SHIFT (0U)
3002 #define SEI_INSTR_OPR_SET(x) (((uint32_t)(x) << SEI_INSTR_OPR_SHIFT) & SEI_INSTR_OPR_MASK)
3003 #define SEI_INSTR_OPR_GET(x) (((uint32_t)(x) & SEI_INSTR_OPR_MASK) >> SEI_INSTR_OPR_SHIFT)
3004 
3005 /* Bitfield definition for register of struct array DAT: MODE */
3006 /*
3007  * CRC_LEN (RW)
3008  *
3009  * CRC length
3010  * 0: 1 bit
3011  * 1: 2 bit
3012  * ...
3013  * 31: 32 bit
3014  */
3015 #define SEI_DAT_MODE_CRC_LEN_MASK (0x1F000000UL)
3016 #define SEI_DAT_MODE_CRC_LEN_SHIFT (24U)
3017 #define SEI_DAT_MODE_CRC_LEN_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_CRC_LEN_SHIFT) & SEI_DAT_MODE_CRC_LEN_MASK)
3018 #define SEI_DAT_MODE_CRC_LEN_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_CRC_LEN_MASK) >> SEI_DAT_MODE_CRC_LEN_SHIFT)
3019 
3020 /*
3021  * WLEN (RW)
3022  *
3023  * word length
3024  * 0: 1 bit
3025  * 1: 2 bit
3026  * ...
3027  * 31: 32 bit
3028  */
3029 #define SEI_DAT_MODE_WLEN_MASK (0x1F0000UL)
3030 #define SEI_DAT_MODE_WLEN_SHIFT (16U)
3031 #define SEI_DAT_MODE_WLEN_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_WLEN_SHIFT) & SEI_DAT_MODE_WLEN_MASK)
3032 #define SEI_DAT_MODE_WLEN_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_WLEN_MASK) >> SEI_DAT_MODE_WLEN_SHIFT)
3033 
3034 /*
3035  * CRC_SHIFT (RW)
3036  *
3037  * CRC shift mode, this mode is used to perform repeat code check
3038  * 0: CRC
3039  * 1: shift mode
3040  */
3041 #define SEI_DAT_MODE_CRC_SHIFT_MASK (0x2000U)
3042 #define SEI_DAT_MODE_CRC_SHIFT_SHIFT (13U)
3043 #define SEI_DAT_MODE_CRC_SHIFT_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_CRC_SHIFT_SHIFT) & SEI_DAT_MODE_CRC_SHIFT_MASK)
3044 #define SEI_DAT_MODE_CRC_SHIFT_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_CRC_SHIFT_MASK) >> SEI_DAT_MODE_CRC_SHIFT_SHIFT)
3045 
3046 /*
3047  * CRC_INV (RW)
3048  *
3049  * CRC invert
3050  * 0: use CRC
3051  * 1: use inverted CRC
3052  */
3053 #define SEI_DAT_MODE_CRC_INV_MASK (0x1000U)
3054 #define SEI_DAT_MODE_CRC_INV_SHIFT (12U)
3055 #define SEI_DAT_MODE_CRC_INV_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_CRC_INV_SHIFT) & SEI_DAT_MODE_CRC_INV_MASK)
3056 #define SEI_DAT_MODE_CRC_INV_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_CRC_INV_MASK) >> SEI_DAT_MODE_CRC_INV_SHIFT)
3057 
3058 /*
3059  * WORDER (RW)
3060  *
3061  * word order
3062  * 0: sample as bit order
3063  * 1: different from bit order
3064  */
3065 #define SEI_DAT_MODE_WORDER_MASK (0x800U)
3066 #define SEI_DAT_MODE_WORDER_SHIFT (11U)
3067 #define SEI_DAT_MODE_WORDER_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_WORDER_SHIFT) & SEI_DAT_MODE_WORDER_MASK)
3068 #define SEI_DAT_MODE_WORDER_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_WORDER_MASK) >> SEI_DAT_MODE_WORDER_SHIFT)
3069 
3070 /*
3071  * BORDER (RW)
3072  *
3073  * bit order
3074  * 0: LSB first
3075  * 1: MSB first
3076  */
3077 #define SEI_DAT_MODE_BORDER_MASK (0x400U)
3078 #define SEI_DAT_MODE_BORDER_SHIFT (10U)
3079 #define SEI_DAT_MODE_BORDER_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_BORDER_SHIFT) & SEI_DAT_MODE_BORDER_MASK)
3080 #define SEI_DAT_MODE_BORDER_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_BORDER_MASK) >> SEI_DAT_MODE_BORDER_SHIFT)
3081 
3082 /*
3083  * SIGNED (RW)
3084  *
3085  * Signed
3086  * 0: unsigned value
3087  * 1: signed value
3088  */
3089 #define SEI_DAT_MODE_SIGNED_MASK (0x200U)
3090 #define SEI_DAT_MODE_SIGNED_SHIFT (9U)
3091 #define SEI_DAT_MODE_SIGNED_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_SIGNED_SHIFT) & SEI_DAT_MODE_SIGNED_MASK)
3092 #define SEI_DAT_MODE_SIGNED_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_SIGNED_MASK) >> SEI_DAT_MODE_SIGNED_SHIFT)
3093 
3094 /*
3095  * REWIND (RW)
3096  *
3097  * Write 1 to rewind read/write pointer, this is a self clear bit
3098  */
3099 #define SEI_DAT_MODE_REWIND_MASK (0x100U)
3100 #define SEI_DAT_MODE_REWIND_SHIFT (8U)
3101 #define SEI_DAT_MODE_REWIND_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_REWIND_SHIFT) & SEI_DAT_MODE_REWIND_MASK)
3102 #define SEI_DAT_MODE_REWIND_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_REWIND_MASK) >> SEI_DAT_MODE_REWIND_SHIFT)
3103 
3104 /*
3105  * MODE (RW)
3106  *
3107  * Data mode
3108  * 0: data mode
3109  * 1: check mode
3110  * 2: CRC mode
3111  */
3112 #define SEI_DAT_MODE_MODE_MASK (0x3U)
3113 #define SEI_DAT_MODE_MODE_SHIFT (0U)
3114 #define SEI_DAT_MODE_MODE_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_MODE_SHIFT) & SEI_DAT_MODE_MODE_MASK)
3115 #define SEI_DAT_MODE_MODE_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_MODE_MASK) >> SEI_DAT_MODE_MODE_SHIFT)
3116 
3117 /* Bitfield definition for register of struct array DAT: IDX */
3118 /*
3119  * LAST_BIT (RW)
3120  *
3121  * Last bit index for tranceive
3122  */
3123 #define SEI_DAT_IDX_LAST_BIT_MASK (0x1F000000UL)
3124 #define SEI_DAT_IDX_LAST_BIT_SHIFT (24U)
3125 #define SEI_DAT_IDX_LAST_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_LAST_BIT_SHIFT) & SEI_DAT_IDX_LAST_BIT_MASK)
3126 #define SEI_DAT_IDX_LAST_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_LAST_BIT_MASK) >> SEI_DAT_IDX_LAST_BIT_SHIFT)
3127 
3128 /*
3129  * FIRST_BIT (RW)
3130  *
3131  * First bit index for tranceive
3132  */
3133 #define SEI_DAT_IDX_FIRST_BIT_MASK (0x1F0000UL)
3134 #define SEI_DAT_IDX_FIRST_BIT_SHIFT (16U)
3135 #define SEI_DAT_IDX_FIRST_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_FIRST_BIT_SHIFT) & SEI_DAT_IDX_FIRST_BIT_MASK)
3136 #define SEI_DAT_IDX_FIRST_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_FIRST_BIT_MASK) >> SEI_DAT_IDX_FIRST_BIT_SHIFT)
3137 
3138 /*
3139  * MAX_BIT (RW)
3140  *
3141  * Highest bit index
3142  */
3143 #define SEI_DAT_IDX_MAX_BIT_MASK (0x1F00U)
3144 #define SEI_DAT_IDX_MAX_BIT_SHIFT (8U)
3145 #define SEI_DAT_IDX_MAX_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_MAX_BIT_SHIFT) & SEI_DAT_IDX_MAX_BIT_MASK)
3146 #define SEI_DAT_IDX_MAX_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_MAX_BIT_MASK) >> SEI_DAT_IDX_MAX_BIT_SHIFT)
3147 
3148 /*
3149  * MIN_BIT (RW)
3150  *
3151  * Lowest bit index
3152  */
3153 #define SEI_DAT_IDX_MIN_BIT_MASK (0x1FU)
3154 #define SEI_DAT_IDX_MIN_BIT_SHIFT (0U)
3155 #define SEI_DAT_IDX_MIN_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_MIN_BIT_SHIFT) & SEI_DAT_IDX_MIN_BIT_MASK)
3156 #define SEI_DAT_IDX_MIN_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_MIN_BIT_MASK) >> SEI_DAT_IDX_MIN_BIT_SHIFT)
3157 
3158 /* Bitfield definition for register of struct array DAT: GOLD */
3159 /*
3160  * GOLD_VALUE (RW)
3161  *
3162  * Gold value for check mode
3163  */
3164 #define SEI_DAT_GOLD_GOLD_VALUE_MASK (0xFFFFFFFFUL)
3165 #define SEI_DAT_GOLD_GOLD_VALUE_SHIFT (0U)
3166 #define SEI_DAT_GOLD_GOLD_VALUE_SET(x) (((uint32_t)(x) << SEI_DAT_GOLD_GOLD_VALUE_SHIFT) & SEI_DAT_GOLD_GOLD_VALUE_MASK)
3167 #define SEI_DAT_GOLD_GOLD_VALUE_GET(x) (((uint32_t)(x) & SEI_DAT_GOLD_GOLD_VALUE_MASK) >> SEI_DAT_GOLD_GOLD_VALUE_SHIFT)
3168 
3169 /* Bitfield definition for register of struct array DAT: CRCINIT */
3170 /*
3171  * CRC_INIT (RW)
3172  *
3173  * CRC initial value
3174  */
3175 #define SEI_DAT_CRCINIT_CRC_INIT_MASK (0xFFFFFFFFUL)
3176 #define SEI_DAT_CRCINIT_CRC_INIT_SHIFT (0U)
3177 #define SEI_DAT_CRCINIT_CRC_INIT_SET(x) (((uint32_t)(x) << SEI_DAT_CRCINIT_CRC_INIT_SHIFT) & SEI_DAT_CRCINIT_CRC_INIT_MASK)
3178 #define SEI_DAT_CRCINIT_CRC_INIT_GET(x) (((uint32_t)(x) & SEI_DAT_CRCINIT_CRC_INIT_MASK) >> SEI_DAT_CRCINIT_CRC_INIT_SHIFT)
3179 
3180 /* Bitfield definition for register of struct array DAT: CRCPOLY */
3181 /*
3182  * CRC_POLY (RW)
3183  *
3184  * CRC polymonial
3185  */
3186 #define SEI_DAT_CRCPOLY_CRC_POLY_MASK (0xFFFFFFFFUL)
3187 #define SEI_DAT_CRCPOLY_CRC_POLY_SHIFT (0U)
3188 #define SEI_DAT_CRCPOLY_CRC_POLY_SET(x) (((uint32_t)(x) << SEI_DAT_CRCPOLY_CRC_POLY_SHIFT) & SEI_DAT_CRCPOLY_CRC_POLY_MASK)
3189 #define SEI_DAT_CRCPOLY_CRC_POLY_GET(x) (((uint32_t)(x) & SEI_DAT_CRCPOLY_CRC_POLY_MASK) >> SEI_DAT_CRCPOLY_CRC_POLY_SHIFT)
3190 
3191 /* Bitfield definition for register of struct array DAT: DATA */
3192 /*
3193  * DATA (RW)
3194  *
3195  * DATA
3196  */
3197 #define SEI_DAT_DATA_DATA_MASK (0xFFFFFFFFUL)
3198 #define SEI_DAT_DATA_DATA_SHIFT (0U)
3199 #define SEI_DAT_DATA_DATA_SET(x) (((uint32_t)(x) << SEI_DAT_DATA_DATA_SHIFT) & SEI_DAT_DATA_DATA_MASK)
3200 #define SEI_DAT_DATA_DATA_GET(x) (((uint32_t)(x) & SEI_DAT_DATA_DATA_MASK) >> SEI_DAT_DATA_DATA_SHIFT)
3201 
3202 /* Bitfield definition for register of struct array DAT: SET */
3203 /*
3204  * DATA_SET (RW)
3205  *
3206  * DATA bit set
3207  */
3208 #define SEI_DAT_SET_DATA_SET_MASK (0xFFFFFFFFUL)
3209 #define SEI_DAT_SET_DATA_SET_SHIFT (0U)
3210 #define SEI_DAT_SET_DATA_SET_SET(x) (((uint32_t)(x) << SEI_DAT_SET_DATA_SET_SHIFT) & SEI_DAT_SET_DATA_SET_MASK)
3211 #define SEI_DAT_SET_DATA_SET_GET(x) (((uint32_t)(x) & SEI_DAT_SET_DATA_SET_MASK) >> SEI_DAT_SET_DATA_SET_SHIFT)
3212 
3213 /* Bitfield definition for register of struct array DAT: CLR */
3214 /*
3215  * DATA_CLR (RW)
3216  *
3217  * DATA bit clear
3218  */
3219 #define SEI_DAT_CLR_DATA_CLR_MASK (0xFFFFFFFFUL)
3220 #define SEI_DAT_CLR_DATA_CLR_SHIFT (0U)
3221 #define SEI_DAT_CLR_DATA_CLR_SET(x) (((uint32_t)(x) << SEI_DAT_CLR_DATA_CLR_SHIFT) & SEI_DAT_CLR_DATA_CLR_MASK)
3222 #define SEI_DAT_CLR_DATA_CLR_GET(x) (((uint32_t)(x) & SEI_DAT_CLR_DATA_CLR_MASK) >> SEI_DAT_CLR_DATA_CLR_SHIFT)
3223 
3224 /* Bitfield definition for register of struct array DAT: INV */
3225 /*
3226  * DATA_INV (RW)
3227  *
3228  * DATA bit toggle
3229  */
3230 #define SEI_DAT_INV_DATA_INV_MASK (0xFFFFFFFFUL)
3231 #define SEI_DAT_INV_DATA_INV_SHIFT (0U)
3232 #define SEI_DAT_INV_DATA_INV_SET(x) (((uint32_t)(x) << SEI_DAT_INV_DATA_INV_SHIFT) & SEI_DAT_INV_DATA_INV_MASK)
3233 #define SEI_DAT_INV_DATA_INV_GET(x) (((uint32_t)(x) & SEI_DAT_INV_DATA_INV_MASK) >> SEI_DAT_INV_DATA_INV_SHIFT)
3234 
3235 /* Bitfield definition for register of struct array DAT: IN */
3236 /*
3237  * DATA_IN (RO)
3238  *
3239  * Data input
3240  */
3241 #define SEI_DAT_IN_DATA_IN_MASK (0xFFFFFFFFUL)
3242 #define SEI_DAT_IN_DATA_IN_SHIFT (0U)
3243 #define SEI_DAT_IN_DATA_IN_GET(x) (((uint32_t)(x) & SEI_DAT_IN_DATA_IN_MASK) >> SEI_DAT_IN_DATA_IN_SHIFT)
3244 
3245 /* Bitfield definition for register of struct array DAT: OUT */
3246 /*
3247  * DATA_OUT (RO)
3248  *
3249  * Data output
3250  */
3251 #define SEI_DAT_OUT_DATA_OUT_MASK (0xFFFFFFFFUL)
3252 #define SEI_DAT_OUT_DATA_OUT_SHIFT (0U)
3253 #define SEI_DAT_OUT_DATA_OUT_GET(x) (((uint32_t)(x) & SEI_DAT_OUT_DATA_OUT_MASK) >> SEI_DAT_OUT_DATA_OUT_SHIFT)
3254 
3255 /* Bitfield definition for register of struct array DAT: STS */
3256 /*
3257  * CRC_IDX (RO)
3258  *
3259  * CRC index
3260  */
3261 #define SEI_DAT_STS_CRC_IDX_MASK (0x1F000000UL)
3262 #define SEI_DAT_STS_CRC_IDX_SHIFT (24U)
3263 #define SEI_DAT_STS_CRC_IDX_GET(x) (((uint32_t)(x) & SEI_DAT_STS_CRC_IDX_MASK) >> SEI_DAT_STS_CRC_IDX_SHIFT)
3264 
3265 /*
3266  * WORD_IDX (RO)
3267  *
3268  * Word index
3269  */
3270 #define SEI_DAT_STS_WORD_IDX_MASK (0x1F0000UL)
3271 #define SEI_DAT_STS_WORD_IDX_SHIFT (16U)
3272 #define SEI_DAT_STS_WORD_IDX_GET(x) (((uint32_t)(x) & SEI_DAT_STS_WORD_IDX_MASK) >> SEI_DAT_STS_WORD_IDX_SHIFT)
3273 
3274 /*
3275  * WORD_CNT (RO)
3276  *
3277  * Word counter
3278  */
3279 #define SEI_DAT_STS_WORD_CNT_MASK (0x1F00U)
3280 #define SEI_DAT_STS_WORD_CNT_SHIFT (8U)
3281 #define SEI_DAT_STS_WORD_CNT_GET(x) (((uint32_t)(x) & SEI_DAT_STS_WORD_CNT_MASK) >> SEI_DAT_STS_WORD_CNT_SHIFT)
3282 
3283 /*
3284  * BIT_IDX (RO)
3285  *
3286  * Bit index
3287  */
3288 #define SEI_DAT_STS_BIT_IDX_MASK (0x1FU)
3289 #define SEI_DAT_STS_BIT_IDX_SHIFT (0U)
3290 #define SEI_DAT_STS_BIT_IDX_GET(x) (((uint32_t)(x) & SEI_DAT_STS_BIT_IDX_MASK) >> SEI_DAT_STS_BIT_IDX_SHIFT)
3291 
3292 
3293 
3294 /* CMD register group index macro definition */
3295 #define SEI_CTRL_TRG_TABLE_CMD_0 (0UL)
3296 #define SEI_CTRL_TRG_TABLE_CMD_1 (1UL)
3297 #define SEI_CTRL_TRG_TABLE_CMD_2 (2UL)
3298 #define SEI_CTRL_TRG_TABLE_CMD_3 (3UL)
3299 
3300 /* TIME register group index macro definition */
3301 #define SEI_CTRL_TRG_TABLE_TIME_0 (0UL)
3302 #define SEI_CTRL_TRG_TABLE_TIME_1 (1UL)
3303 #define SEI_CTRL_TRG_TABLE_TIME_2 (2UL)
3304 #define SEI_CTRL_TRG_TABLE_TIME_3 (3UL)
3305 
3306 /* CMD_TABLE register group index macro definition */
3307 #define SEI_CMD_TABLE_0 (0UL)
3308 #define SEI_CMD_TABLE_1 (1UL)
3309 #define SEI_CMD_TABLE_2 (2UL)
3310 #define SEI_CMD_TABLE_3 (3UL)
3311 #define SEI_CMD_TABLE_4 (4UL)
3312 #define SEI_CMD_TABLE_5 (5UL)
3313 #define SEI_CMD_TABLE_6 (6UL)
3314 #define SEI_CMD_TABLE_7 (7UL)
3315 
3316 /* TRAN register group index macro definition */
3317 #define SEI_CTRL_LATCH_TRAN_0_1 (0UL)
3318 #define SEI_CTRL_LATCH_TRAN_1_2 (1UL)
3319 #define SEI_CTRL_LATCH_TRAN_2_3 (2UL)
3320 #define SEI_CTRL_LATCH_TRAN_3_0 (3UL)
3321 
3322 /* LATCH register group index macro definition */
3323 #define SEI_LATCH_0 (0UL)
3324 #define SEI_LATCH_1 (1UL)
3325 #define SEI_LATCH_2 (2UL)
3326 #define SEI_LATCH_3 (3UL)
3327 
3328 /* CTRL register group index macro definition */
3329 #define SEI_CTRL_0 (0UL)
3330 #define SEI_CTRL_1 (1UL)
3331 #define SEI_CTRL_2 (2UL)
3332 #define SEI_CTRL_3 (3UL)
3333 #define SEI_CTRL_4 (4UL)
3334 #define SEI_CTRL_5 (5UL)
3335 #define SEI_CTRL_6 (6UL)
3336 #define SEI_CTRL_7 (7UL)
3337 #define SEI_CTRL_8 (8UL)
3338 #define SEI_CTRL_9 (9UL)
3339 #define SEI_CTRL_10 (10UL)
3340 #define SEI_CTRL_11 (11UL)
3341 #define SEI_CTRL_12 (12UL)
3342 
3343 /* INSTR register group index macro definition */
3344 #define SEI_INSTR_0 (0UL)
3345 #define SEI_INSTR_1 (1UL)
3346 #define SEI_INSTR_2 (2UL)
3347 #define SEI_INSTR_3 (3UL)
3348 #define SEI_INSTR_4 (4UL)
3349 #define SEI_INSTR_5 (5UL)
3350 #define SEI_INSTR_6 (6UL)
3351 #define SEI_INSTR_7 (7UL)
3352 #define SEI_INSTR_8 (8UL)
3353 #define SEI_INSTR_9 (9UL)
3354 #define SEI_INSTR_10 (10UL)
3355 #define SEI_INSTR_11 (11UL)
3356 #define SEI_INSTR_12 (12UL)
3357 #define SEI_INSTR_13 (13UL)
3358 #define SEI_INSTR_14 (14UL)
3359 #define SEI_INSTR_15 (15UL)
3360 #define SEI_INSTR_16 (16UL)
3361 #define SEI_INSTR_17 (17UL)
3362 #define SEI_INSTR_18 (18UL)
3363 #define SEI_INSTR_19 (19UL)
3364 #define SEI_INSTR_20 (20UL)
3365 #define SEI_INSTR_21 (21UL)
3366 #define SEI_INSTR_22 (22UL)
3367 #define SEI_INSTR_23 (23UL)
3368 #define SEI_INSTR_24 (24UL)
3369 #define SEI_INSTR_25 (25UL)
3370 #define SEI_INSTR_26 (26UL)
3371 #define SEI_INSTR_27 (27UL)
3372 #define SEI_INSTR_28 (28UL)
3373 #define SEI_INSTR_29 (29UL)
3374 #define SEI_INSTR_30 (30UL)
3375 #define SEI_INSTR_31 (31UL)
3376 #define SEI_INSTR_32 (32UL)
3377 #define SEI_INSTR_33 (33UL)
3378 #define SEI_INSTR_34 (34UL)
3379 #define SEI_INSTR_35 (35UL)
3380 #define SEI_INSTR_36 (36UL)
3381 #define SEI_INSTR_37 (37UL)
3382 #define SEI_INSTR_38 (38UL)
3383 #define SEI_INSTR_39 (39UL)
3384 #define SEI_INSTR_40 (40UL)
3385 #define SEI_INSTR_41 (41UL)
3386 #define SEI_INSTR_42 (42UL)
3387 #define SEI_INSTR_43 (43UL)
3388 #define SEI_INSTR_44 (44UL)
3389 #define SEI_INSTR_45 (45UL)
3390 #define SEI_INSTR_46 (46UL)
3391 #define SEI_INSTR_47 (47UL)
3392 #define SEI_INSTR_48 (48UL)
3393 #define SEI_INSTR_49 (49UL)
3394 #define SEI_INSTR_50 (50UL)
3395 #define SEI_INSTR_51 (51UL)
3396 #define SEI_INSTR_52 (52UL)
3397 #define SEI_INSTR_53 (53UL)
3398 #define SEI_INSTR_54 (54UL)
3399 #define SEI_INSTR_55 (55UL)
3400 #define SEI_INSTR_56 (56UL)
3401 #define SEI_INSTR_57 (57UL)
3402 #define SEI_INSTR_58 (58UL)
3403 #define SEI_INSTR_59 (59UL)
3404 #define SEI_INSTR_60 (60UL)
3405 #define SEI_INSTR_61 (61UL)
3406 #define SEI_INSTR_62 (62UL)
3407 #define SEI_INSTR_63 (63UL)
3408 #define SEI_INSTR_64 (64UL)
3409 #define SEI_INSTR_65 (65UL)
3410 #define SEI_INSTR_66 (66UL)
3411 #define SEI_INSTR_67 (67UL)
3412 #define SEI_INSTR_68 (68UL)
3413 #define SEI_INSTR_69 (69UL)
3414 #define SEI_INSTR_70 (70UL)
3415 #define SEI_INSTR_71 (71UL)
3416 #define SEI_INSTR_72 (72UL)
3417 #define SEI_INSTR_73 (73UL)
3418 #define SEI_INSTR_74 (74UL)
3419 #define SEI_INSTR_75 (75UL)
3420 #define SEI_INSTR_76 (76UL)
3421 #define SEI_INSTR_77 (77UL)
3422 #define SEI_INSTR_78 (78UL)
3423 #define SEI_INSTR_79 (79UL)
3424 #define SEI_INSTR_80 (80UL)
3425 #define SEI_INSTR_81 (81UL)
3426 #define SEI_INSTR_82 (82UL)
3427 #define SEI_INSTR_83 (83UL)
3428 #define SEI_INSTR_84 (84UL)
3429 #define SEI_INSTR_85 (85UL)
3430 #define SEI_INSTR_86 (86UL)
3431 #define SEI_INSTR_87 (87UL)
3432 #define SEI_INSTR_88 (88UL)
3433 #define SEI_INSTR_89 (89UL)
3434 #define SEI_INSTR_90 (90UL)
3435 #define SEI_INSTR_91 (91UL)
3436 #define SEI_INSTR_92 (92UL)
3437 #define SEI_INSTR_93 (93UL)
3438 #define SEI_INSTR_94 (94UL)
3439 #define SEI_INSTR_95 (95UL)
3440 #define SEI_INSTR_96 (96UL)
3441 #define SEI_INSTR_97 (97UL)
3442 #define SEI_INSTR_98 (98UL)
3443 #define SEI_INSTR_99 (99UL)
3444 #define SEI_INSTR_100 (100UL)
3445 #define SEI_INSTR_101 (101UL)
3446 #define SEI_INSTR_102 (102UL)
3447 #define SEI_INSTR_103 (103UL)
3448 #define SEI_INSTR_104 (104UL)
3449 #define SEI_INSTR_105 (105UL)
3450 #define SEI_INSTR_106 (106UL)
3451 #define SEI_INSTR_107 (107UL)
3452 #define SEI_INSTR_108 (108UL)
3453 #define SEI_INSTR_109 (109UL)
3454 #define SEI_INSTR_110 (110UL)
3455 #define SEI_INSTR_111 (111UL)
3456 #define SEI_INSTR_112 (112UL)
3457 #define SEI_INSTR_113 (113UL)
3458 #define SEI_INSTR_114 (114UL)
3459 #define SEI_INSTR_115 (115UL)
3460 #define SEI_INSTR_116 (116UL)
3461 #define SEI_INSTR_117 (117UL)
3462 #define SEI_INSTR_118 (118UL)
3463 #define SEI_INSTR_119 (119UL)
3464 #define SEI_INSTR_120 (120UL)
3465 #define SEI_INSTR_121 (121UL)
3466 #define SEI_INSTR_122 (122UL)
3467 #define SEI_INSTR_123 (123UL)
3468 #define SEI_INSTR_124 (124UL)
3469 #define SEI_INSTR_125 (125UL)
3470 #define SEI_INSTR_126 (126UL)
3471 #define SEI_INSTR_127 (127UL)
3472 #define SEI_INSTR_128 (128UL)
3473 #define SEI_INSTR_129 (129UL)
3474 #define SEI_INSTR_130 (130UL)
3475 #define SEI_INSTR_131 (131UL)
3476 #define SEI_INSTR_132 (132UL)
3477 #define SEI_INSTR_133 (133UL)
3478 #define SEI_INSTR_134 (134UL)
3479 #define SEI_INSTR_135 (135UL)
3480 #define SEI_INSTR_136 (136UL)
3481 #define SEI_INSTR_137 (137UL)
3482 #define SEI_INSTR_138 (138UL)
3483 #define SEI_INSTR_139 (139UL)
3484 #define SEI_INSTR_140 (140UL)
3485 #define SEI_INSTR_141 (141UL)
3486 #define SEI_INSTR_142 (142UL)
3487 #define SEI_INSTR_143 (143UL)
3488 #define SEI_INSTR_144 (144UL)
3489 #define SEI_INSTR_145 (145UL)
3490 #define SEI_INSTR_146 (146UL)
3491 #define SEI_INSTR_147 (147UL)
3492 #define SEI_INSTR_148 (148UL)
3493 #define SEI_INSTR_149 (149UL)
3494 #define SEI_INSTR_150 (150UL)
3495 #define SEI_INSTR_151 (151UL)
3496 #define SEI_INSTR_152 (152UL)
3497 #define SEI_INSTR_153 (153UL)
3498 #define SEI_INSTR_154 (154UL)
3499 #define SEI_INSTR_155 (155UL)
3500 #define SEI_INSTR_156 (156UL)
3501 #define SEI_INSTR_157 (157UL)
3502 #define SEI_INSTR_158 (158UL)
3503 #define SEI_INSTR_159 (159UL)
3504 #define SEI_INSTR_160 (160UL)
3505 #define SEI_INSTR_161 (161UL)
3506 #define SEI_INSTR_162 (162UL)
3507 #define SEI_INSTR_163 (163UL)
3508 #define SEI_INSTR_164 (164UL)
3509 #define SEI_INSTR_165 (165UL)
3510 #define SEI_INSTR_166 (166UL)
3511 #define SEI_INSTR_167 (167UL)
3512 #define SEI_INSTR_168 (168UL)
3513 #define SEI_INSTR_169 (169UL)
3514 #define SEI_INSTR_170 (170UL)
3515 #define SEI_INSTR_171 (171UL)
3516 #define SEI_INSTR_172 (172UL)
3517 #define SEI_INSTR_173 (173UL)
3518 #define SEI_INSTR_174 (174UL)
3519 #define SEI_INSTR_175 (175UL)
3520 #define SEI_INSTR_176 (176UL)
3521 #define SEI_INSTR_177 (177UL)
3522 #define SEI_INSTR_178 (178UL)
3523 #define SEI_INSTR_179 (179UL)
3524 #define SEI_INSTR_180 (180UL)
3525 #define SEI_INSTR_181 (181UL)
3526 #define SEI_INSTR_182 (182UL)
3527 #define SEI_INSTR_183 (183UL)
3528 #define SEI_INSTR_184 (184UL)
3529 #define SEI_INSTR_185 (185UL)
3530 #define SEI_INSTR_186 (186UL)
3531 #define SEI_INSTR_187 (187UL)
3532 #define SEI_INSTR_188 (188UL)
3533 #define SEI_INSTR_189 (189UL)
3534 #define SEI_INSTR_190 (190UL)
3535 #define SEI_INSTR_191 (191UL)
3536 #define SEI_INSTR_192 (192UL)
3537 #define SEI_INSTR_193 (193UL)
3538 #define SEI_INSTR_194 (194UL)
3539 #define SEI_INSTR_195 (195UL)
3540 #define SEI_INSTR_196 (196UL)
3541 #define SEI_INSTR_197 (197UL)
3542 #define SEI_INSTR_198 (198UL)
3543 #define SEI_INSTR_199 (199UL)
3544 #define SEI_INSTR_200 (200UL)
3545 #define SEI_INSTR_201 (201UL)
3546 #define SEI_INSTR_202 (202UL)
3547 #define SEI_INSTR_203 (203UL)
3548 #define SEI_INSTR_204 (204UL)
3549 #define SEI_INSTR_205 (205UL)
3550 #define SEI_INSTR_206 (206UL)
3551 #define SEI_INSTR_207 (207UL)
3552 #define SEI_INSTR_208 (208UL)
3553 #define SEI_INSTR_209 (209UL)
3554 #define SEI_INSTR_210 (210UL)
3555 #define SEI_INSTR_211 (211UL)
3556 #define SEI_INSTR_212 (212UL)
3557 #define SEI_INSTR_213 (213UL)
3558 #define SEI_INSTR_214 (214UL)
3559 #define SEI_INSTR_215 (215UL)
3560 #define SEI_INSTR_216 (216UL)
3561 #define SEI_INSTR_217 (217UL)
3562 #define SEI_INSTR_218 (218UL)
3563 #define SEI_INSTR_219 (219UL)
3564 #define SEI_INSTR_220 (220UL)
3565 #define SEI_INSTR_221 (221UL)
3566 #define SEI_INSTR_222 (222UL)
3567 #define SEI_INSTR_223 (223UL)
3568 #define SEI_INSTR_224 (224UL)
3569 #define SEI_INSTR_225 (225UL)
3570 #define SEI_INSTR_226 (226UL)
3571 #define SEI_INSTR_227 (227UL)
3572 #define SEI_INSTR_228 (228UL)
3573 #define SEI_INSTR_229 (229UL)
3574 #define SEI_INSTR_230 (230UL)
3575 #define SEI_INSTR_231 (231UL)
3576 #define SEI_INSTR_232 (232UL)
3577 #define SEI_INSTR_233 (233UL)
3578 #define SEI_INSTR_234 (234UL)
3579 #define SEI_INSTR_235 (235UL)
3580 #define SEI_INSTR_236 (236UL)
3581 #define SEI_INSTR_237 (237UL)
3582 #define SEI_INSTR_238 (238UL)
3583 #define SEI_INSTR_239 (239UL)
3584 #define SEI_INSTR_240 (240UL)
3585 #define SEI_INSTR_241 (241UL)
3586 #define SEI_INSTR_242 (242UL)
3587 #define SEI_INSTR_243 (243UL)
3588 #define SEI_INSTR_244 (244UL)
3589 #define SEI_INSTR_245 (245UL)
3590 #define SEI_INSTR_246 (246UL)
3591 #define SEI_INSTR_247 (247UL)
3592 #define SEI_INSTR_248 (248UL)
3593 #define SEI_INSTR_249 (249UL)
3594 #define SEI_INSTR_250 (250UL)
3595 #define SEI_INSTR_251 (251UL)
3596 #define SEI_INSTR_252 (252UL)
3597 #define SEI_INSTR_253 (253UL)
3598 #define SEI_INSTR_254 (254UL)
3599 #define SEI_INSTR_255 (255UL)
3600 
3601 /* DAT register group index macro definition */
3602 #define SEI_DAT_0 (0UL)
3603 #define SEI_DAT_1 (1UL)
3604 #define SEI_DAT_2 (2UL)
3605 #define SEI_DAT_3 (3UL)
3606 #define SEI_DAT_4 (4UL)
3607 #define SEI_DAT_5 (5UL)
3608 #define SEI_DAT_6 (6UL)
3609 #define SEI_DAT_7 (7UL)
3610 #define SEI_DAT_8 (8UL)
3611 #define SEI_DAT_9 (9UL)
3612 #define SEI_DAT_10 (10UL)
3613 #define SEI_DAT_11 (11UL)
3614 #define SEI_DAT_12 (12UL)
3615 #define SEI_DAT_13 (13UL)
3616 #define SEI_DAT_14 (14UL)
3617 #define SEI_DAT_15 (15UL)
3618 #define SEI_DAT_16 (16UL)
3619 #define SEI_DAT_17 (17UL)
3620 #define SEI_DAT_18 (18UL)
3621 #define SEI_DAT_19 (19UL)
3622 #define SEI_DAT_20 (20UL)
3623 #define SEI_DAT_21 (21UL)
3624 #define SEI_DAT_22 (22UL)
3625 #define SEI_DAT_23 (23UL)
3626 #define SEI_DAT_24 (24UL)
3627 #define SEI_DAT_25 (25UL)
3628 #define SEI_DAT_26 (26UL)
3629 #define SEI_DAT_27 (27UL)
3630 #define SEI_DAT_28 (28UL)
3631 #define SEI_DAT_29 (29UL)
3632 #define SEI_DAT_30 (30UL)
3633 #define SEI_DAT_31 (31UL)
3634 
3635 
3636 #endif /* HPM_SEI_H */
MIN
#define MIN(a, b)
Definition: hpm_common.h:49
MAX
#define MAX(a, b)
Definition: hpm_common.h:46
SEI_Type
Definition: hpm_sei_regs.h:12