hpm_spi_drv.h

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/*
 * Copyright (c) 2021 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
 */
 
#ifndef HPM_SPI_DRV_H
#define HPM_SPI_DRV_H
#include "hpm_spi_regs.h"
#include "hpm_soc_feature.h"
 
typedef enum {
    spi_tx_dma_enable = SPI_CTRL_TXDMAEN_MASK,
    spi_rx_dma_enable = SPI_CTRL_RXDMAEN_MASK
} spi_dma_enable_t;
 
typedef enum {
    spi_rx_fifo_overflow_int  = SPI_INTREN_RXFIFOORINTEN_MASK,
    spi_tx_fifo_underflow_int = SPI_INTREN_TXFIFOURINTEN_MASK,
    spi_rx_fifo_threshold_int = SPI_INTREN_RXFIFOINTEN_MASK,
    spi_tx_fifo_threshold_int = SPI_INTREN_TXFIFOINTEN_MASK,
    spi_end_int               = SPI_INTREN_ENDINTEN_MASK,
    spi_slave_cmd_int         = SPI_INTREN_SLVCMDEN_MASK,
} spi_interrupt_t;
 
typedef enum {
    spi_master_mode = 0,
    spi_slave_mode
} spi_mode_selection_t;
 
typedef enum {
    spi_sclk_low_idle = 0,
    spi_sclk_high_idle
} spi_sclk_idle_state_t;
 
typedef enum {
    spi_sclk_sampling_odd_clk_edges = 0,
    spi_sclk_sampling_even_clk_edges
} spi_sclk_sampling_clk_edges_t;
 
typedef enum {
    spi_cs2sclk_half_sclk_1 = 0,
    spi_cs2sclk_half_sclk_2,
    spi_cs2sclk_half_sclk_3,
    spi_cs2sclk_half_sclk_4
} spi_cs2sclk_duration_t;
 
typedef enum {
    spi_csht_half_sclk_1 = 0,
    spi_csht_half_sclk_2,
    spi_csht_half_sclk_3,
    spi_csht_half_sclk_4,
    spi_csht_half_sclk_5,
    spi_csht_half_sclk_6,
    spi_csht_half_sclk_7,
    spi_csht_half_sclk_8,
    spi_csht_half_sclk_9,
    spi_csht_half_sclk_10,
    spi_csht_half_sclk_11,
    spi_csht_half_sclk_12,
    spi_csht_half_sclk_13,
    spi_csht_half_sclk_14,
    spi_csht_half_sclk_15,
    spi_csht_half_sclk_16,
} spi_csht_duration_t;
 
typedef enum {
    spi_address_phase_format_single_io_mode = 0,
    spi_address_phase_format_dualquad_io_mode
} spi_addr_phase_format_t;
 
typedef enum {
    spi_trans_write_read_together = 0,
    spi_trans_write_only,
    spi_trans_read_only,
    spi_trans_write_read,
    spi_trans_read_write,
    spi_trans_write_dummy_read,
    spi_trans_read_dummy_write,
    spi_trans_no_data,
    spi_trans_dummy_write,
    spi_trans_dummy_read
} spi_trans_mode_t;
 
typedef enum {
    spi_single_io_mode = 0,
    spi_dual_io_mode,
    spi_quad_io_mode,
} spi_data_phase_format_t;
 
typedef enum {
    spi_token_value_0x00 = 0,
    spi_token_value_0x69
} spi_token_value_t;
 
typedef enum {
    spi_dummy_count_1 = 0,
    spi_dummy_count_2,
    spi_dummy_count_3,
    spi_dummy_count_4
} spi_dummy_count_t;
 
typedef struct {
    uint32_t clk_src_freq_in_hz;
    uint32_t sclk_freq_in_hz;
    uint8_t cs2sclk;
    uint8_t csht;
} spi_master_timing_config_t;
 
typedef struct {
    spi_master_timing_config_t master_config;
} spi_timing_config_t;
 
typedef struct {
    uint8_t addr_len_in_bytes;
} spi_master_format_config_t;
 
typedef struct {
    uint8_t data_len_in_bits;
    bool data_merge;
    bool mosi_bidir;
    bool lsb;
    uint8_t mode;
    uint8_t cpol;
    uint8_t cpha;
} spi_common_format_config_t;
 
typedef struct {
    spi_master_format_config_t master_config;
    spi_common_format_config_t common_config;
} spi_format_config_t;
 
typedef struct {
    bool cmd_enable;
    bool addr_enable;
    uint8_t addr_phase_fmt;
    bool token_enable;
    uint8_t token_value;
} spi_master_control_config_t;
 
typedef struct {
    bool slave_data_only;
} spi_slave_control_config_t;
 
typedef struct {
    bool tx_dma_enable;
    bool rx_dma_enable;
    uint8_t trans_mode;
    uint8_t data_phase_fmt;
    uint8_t dummy_cnt;
#if defined(HPM_IP_FEATURE_SPI_CS_SELECT) && (HPM_IP_FEATURE_SPI_CS_SELECT == 1)
    uint8_t cs_index;
#endif
} spi_common_control_config_t; 
typedef struct {
    spi_master_control_config_t master_config;
    spi_slave_control_config_t  slave_config;
    spi_common_control_config_t common_config;
} spi_control_config_t;
 
#if defined(HPM_IP_FEATURE_SPI_CS_SELECT) && (HPM_IP_FEATURE_SPI_CS_SELECT == 1)
typedef enum {
    spi_cs_0 = 1,
    spi_cs_1 = 2,
    spi_cs_2 = 4,
    spi_cs_3 = 8,
} spi_cs_index_t;
#endif
 
typedef enum {
    addrlen_8bit = 0,
    addrlen_16bit,
    addrlen_24bit,
    addrlen_32bit
} spi_address_len_t;
 
#if defined(HPM_IP_FEATURE_SPI_SUPPORT_DIRECTIO) && (HPM_IP_FEATURE_SPI_SUPPORT_DIRECTIO == 1)
typedef enum {
    hold_pin = 0,
    wp_pin,
    miso_pin,
    mosi_pin,
    sclk_pin,
    cs_pin
} spi_directio_pin_t;
#endif
 
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
 
void spi_master_get_default_timing_config(spi_timing_config_t *config);
 
void spi_master_get_default_format_config(spi_format_config_t *config);
 
void spi_master_get_default_control_config(spi_control_config_t *config);
 
void spi_slave_get_default_format_config(spi_format_config_t *config);
 
void spi_slave_get_default_control_config(spi_control_config_t *config);
 
hpm_stat_t spi_master_timing_init(SPI_Type *ptr, spi_timing_config_t *config);
 
void spi_format_init(SPI_Type *ptr, spi_format_config_t *config);
 
hpm_stat_t spi_transfer(SPI_Type *ptr,
                        spi_control_config_t *config,
                        uint8_t *cmd, uint32_t *addr,
                        uint8_t *wbuff, uint32_t wcount,  uint8_t *rbuff, uint32_t rcount);
 
hpm_stat_t spi_setup_dma_transfer(SPI_Type *ptr,
                        spi_control_config_t *config,
                        uint8_t *cmd, uint32_t *addr,
                        uint32_t wcount, uint32_t rcount);
 
hpm_stat_t spi_wait_for_idle_status(SPI_Type *ptr);
 
hpm_stat_t spi_wait_for_busy_status(SPI_Type *ptr);
 
static inline void spi_set_tx_fifo_threshold(SPI_Type *ptr, uint32_t threshold)
{
    ptr->CTRL = (ptr->CTRL & ~SPI_CTRL_TXTHRES_MASK) | SPI_CTRL_TXTHRES_SET(threshold);
}
 
static inline void spi_set_rx_fifo_threshold(SPI_Type *ptr, uint32_t threshold)
{
    ptr->CTRL = (ptr->CTRL & ~SPI_CTRL_RXTHRES_MASK) | SPI_CTRL_RXTHRES_SET(threshold);
}
 
static inline void spi_enable_dma(SPI_Type *ptr, uint32_t mask)
{
    ptr->CTRL |= mask;
}
 
static inline void spi_disable_dma(SPI_Type *ptr, uint32_t mask)
{
    ptr->CTRL &= ~mask;
}
 
static inline uint32_t spi_get_interrupt_status(SPI_Type *ptr)
{
    return ptr->INTRST;
}
 
static inline void spi_clear_interrupt_status(SPI_Type *ptr, uint32_t mask)
{
    /* write 1 to clear */
    ptr->INTRST = mask;
}
 
static inline void spi_enable_interrupt(SPI_Type *ptr, uint32_t mask)
{
    ptr->INTREN |= mask;
}
 
static inline void spi_disable_interrupt(SPI_Type *ptr, uint32_t mask)
{
    ptr->INTREN &= ~mask;
}
 
hpm_stat_t spi_write_read_data(SPI_Type *ptr, uint8_t data_len_in_bytes, uint8_t *wbuff, uint32_t wcount, uint8_t *rbuff, uint32_t rcount);
 
hpm_stat_t spi_read_data(SPI_Type *ptr, uint8_t data_len_in_bytes, uint8_t *buff, uint32_t count);
 
hpm_stat_t spi_write_data(SPI_Type *ptr, uint8_t data_len_in_bytes, uint8_t *buff, uint32_t count);
 
hpm_stat_t spi_write_command(SPI_Type *ptr, spi_mode_selection_t mode, spi_control_config_t *config, uint8_t *cmd);
 
hpm_stat_t spi_read_command(SPI_Type *ptr, spi_mode_selection_t mode, spi_control_config_t *config, uint8_t *cmd);
 
hpm_stat_t spi_write_address(SPI_Type *ptr, spi_mode_selection_t mode, spi_control_config_t *config, uint32_t *addr);
 
hpm_stat_t spi_control_init(SPI_Type *ptr, spi_control_config_t *config, uint32_t wcount, uint32_t rcount);
 
static inline uint8_t spi_get_data_length_in_bits(SPI_Type *ptr)
{
    return ((ptr->TRANSFMT & SPI_TRANSFMT_DATALEN_MASK) >> SPI_TRANSFMT_DATALEN_SHIFT) + 1;
}
 
static inline uint8_t spi_get_data_length_in_bytes(SPI_Type *ptr)
{
    return ((spi_get_data_length_in_bits(ptr) + 7U) / 8U);
}
 
static inline bool spi_is_active(SPI_Type *ptr)
{
    return ((ptr->STATUS & SPI_STATUS_SPIACTIVE_MASK) == SPI_STATUS_SPIACTIVE_MASK) ? true : false;
}
 
static inline void spi_enable_tx_dma(SPI_Type *ptr)
{
    ptr->CTRL |= SPI_CTRL_TXDMAEN_MASK;
}
 
static inline void spi_disable_tx_dma(SPI_Type *ptr)
{
    ptr->CTRL &= ~SPI_CTRL_TXDMAEN_MASK;
}
 
static inline void spi_enable_rx_dma(SPI_Type *ptr)
{
    ptr->CTRL |= SPI_CTRL_RXDMAEN_MASK;
}
 
static inline void spi_disable_rx_dma(SPI_Type *ptr)
{
    ptr->CTRL &= ~SPI_CTRL_RXDMAEN_MASK;
}
 
static inline uint32_t spi_slave_get_sent_data_count(SPI_Type *ptr)
{
#if defined(HPM_IP_FEATURE_SPI_NEW_TRANS_COUNT) && (HPM_IP_FEATURE_SPI_NEW_TRANS_COUNT == 1)
    return ptr->SLVDATAWCNT;
#else
    return SPI_SLVDATACNT_WCNT_GET(ptr->SLVDATACNT);
#endif
}
 
static inline uint32_t spi_slave_get_received_data_count(SPI_Type *ptr)
{
#if defined(HPM_IP_FEATURE_SPI_NEW_TRANS_COUNT) && (HPM_IP_FEATURE_SPI_NEW_TRANS_COUNT == 1)
    return ptr->SLVDATARCNT;
#else
    return SPI_SLVDATACNT_RCNT_GET(ptr->SLVDATACNT);
#endif
}
 
static inline void spi_set_clock_phase(SPI_Type *ptr, spi_sclk_sampling_clk_edges_t clock_phase)
{
    ptr->TRANSCTRL |= SPI_TRANSFMT_CPHA_SET(clock_phase);
}
 
static inline spi_sclk_sampling_clk_edges_t spi_get_clock_phase(SPI_Type *ptr)
{
    return SPI_TRANSFMT_CPHA_GET(ptr->TRANSCTRL);
}
 
static inline void spi_set_clock_polarity(SPI_Type *ptr, spi_sclk_idle_state_t clock_polarity)
{
    ptr->TRANSCTRL |= SPI_TRANSFMT_CPOL_SET(clock_polarity);
}
 
static inline spi_sclk_idle_state_t spi_get_clock_polarity(SPI_Type *ptr)
{
    return SPI_TRANSFMT_CPOL_GET(ptr->TRANSCTRL);
}
 
static inline hpm_stat_t spi_set_data_bits(SPI_Type *ptr, uint8_t nbits)
{
    if (nbits > 32) {
        return status_invalid_argument;
    } else {
        ptr->TRANSFMT = (ptr->TRANSFMT & ~SPI_TRANSFMT_DATALEN_MASK) | SPI_TRANSFMT_DATALEN_SET(nbits - 1);
        return status_success;
    }
}
 
static inline void spi_transmit_fifo_reset(SPI_Type *ptr)
{
    ptr->CTRL |= SPI_CTRL_TXFIFORST_MASK;
}
 
static inline void spi_receive_fifo_reset(SPI_Type *ptr)
{
    ptr->CTRL |= SPI_CTRL_RXFIFORST_MASK;
}
 
static inline void spi_reset(SPI_Type *ptr)
{
    ptr->CTRL |= SPI_CTRL_SPIRST_MASK;
}
 
static inline void spi_set_address_len(SPI_Type *ptr, spi_address_len_t addrlen)
{
    ptr->TRANSFMT = (ptr->TRANSFMT & ~SPI_TRANSFMT_ADDRLEN_MASK) | SPI_TRANSFMT_ADDRLEN_SET(addrlen);
}
 
static inline void spi_enable_data_merge(SPI_Type *ptr)
{
    ptr->TRANSFMT |= SPI_TRANSFMT_DATAMERGE_MASK;
}
 
static inline void spi_disable_data_merge(SPI_Type *ptr)
{
    ptr->TRANSFMT &= ~SPI_TRANSFMT_DATAMERGE_MASK;
}
 
#if defined(HPM_IP_FEATURE_SPI_SUPPORT_DIRECTIO) && (HPM_IP_FEATURE_SPI_SUPPORT_DIRECTIO == 1)
hpm_stat_t spi_directio_enable_output(SPI_Type *ptr, spi_directio_pin_t pin);
 
hpm_stat_t spi_directio_disable_output(SPI_Type *ptr, spi_directio_pin_t pin);
 
hpm_stat_t spi_directio_write(SPI_Type *ptr, spi_directio_pin_t pin, bool high);
 
uint8_t spi_directio_read(SPI_Type *ptr, spi_directio_pin_t pin);
 
static inline void spi_enable_directio(SPI_Type *ptr)
{
    ptr->DIRECTIO |= SPI_DIRECTIO_DIRECTIOEN_MASK;
}
 
static inline void spi_disable_directio(SPI_Type *ptr)
{
    ptr->DIRECTIO &= ~SPI_DIRECTIO_DIRECTIOEN_MASK;
}
 
static inline uint8_t spi_get_directio_enable_status(SPI_Type *ptr)
{
    return SPI_DIRECTIO_DIRECTIOEN_GET(ptr->DIRECTIO);
}
 
#endif
 
static inline uint8_t spi_get_rx_fifo_valid_data_size(SPI_Type *ptr)
{
    return ((SPI_STATUS_RXNUM_7_6_GET(ptr->STATUS) << 5) | SPI_STATUS_RXNUM_5_0_GET(ptr->STATUS));
}
 
static inline uint8_t spi_get_tx_fifo_valid_data_size(SPI_Type *ptr)
{
    return ((SPI_STATUS_TXNUM_7_6_GET(ptr->STATUS) << 5) | SPI_STATUS_TXNUM_5_0_GET(ptr->STATUS));
}
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* HPM_SPI_DRV_H */