HPM SDK
HPMicro Software Development Kit
hpm_trgmmux_src.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_TRGMMUX_SRC_H
10 #define HPM_TRGMMUX_SRC_H
11 
12 /* trgm0_input mux definitions */
13 #define HPM_TRGM0_INPUT_SRC_VSS (0x0UL) /* Low level */
14 #define HPM_TRGM0_INPUT_SRC_VDD (0x1UL) /* High level */
15 #define HPM_TRGM0_INPUT_SRC_DEBUG_FLAG (0x2UL) /* the flag bit of debug mode enters */
16 #define HPM_TRGM0_INPUT_SRC_USB0_SOF (0x3UL) /* USB0 frame start */
17 #define HPM_TRGM0_INPUT_SRC_PTPC_CMP0 (0x4UL) /* PTPC output comparison 0 */
18 #define HPM_TRGM0_INPUT_SRC_PTPC_CMP1 (0x5UL) /* PTPC output comparison 1 */
19 #define HPM_TRGM0_INPUT_SRC_ACMP0_OUT (0x6UL) /* Comparator 0 output */
20 #define HPM_TRGM0_INPUT_SRC_ACMP1_OUT (0x7UL) /* Comparator 1 output */
21 #define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT2 (0x8UL) /* GPTMR0 channel 2 */
22 #define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT3 (0x9UL) /* GPTMR0 channel 3 */
23 #define HPM_TRGM0_INPUT_SRC_GPTMR1_OUT2 (0xAUL) /* GPTMR1 channel 2 */
24 #define HPM_TRGM0_INPUT_SRC_GPTMR1_OUT3 (0xBUL) /* GPTMR1 channel 3 */
25 #define HPM_TRGM0_INPUT_SRC_GPTMR2_OUT2 (0xCUL) /* GPTMR2 channel 2 */
26 #define HPM_TRGM0_INPUT_SRC_GPTMR2_OUT3 (0xDUL) /* GPTMR2 channel 3 */
27 #define HPM_TRGM0_INPUT_SRC_GPTMR3_OUT2 (0xEUL) /* GPTMR3 channel 2 */
28 #define HPM_TRGM0_INPUT_SRC_GPTMR3_OUT3 (0xFUL) /* GPTMR3 channel 3 */
29 #define HPM_TRGM0_INPUT_SRC_TRGM0_P0 (0x10UL) /* TRGM0 Input 0 (from IO) */
30 #define HPM_TRGM0_INPUT_SRC_TRGM0_P1 (0x11UL) /* TRGM0 Input 1 (from IO) */
31 #define HPM_TRGM0_INPUT_SRC_TRGM0_P2 (0x12UL) /* TRGM0 Input 2 (from IO) */
32 #define HPM_TRGM0_INPUT_SRC_TRGM0_P3 (0x13UL) /* TRGM0 Input 3 (from IO) */
33 #define HPM_TRGM0_INPUT_SRC_TRGM0_P4 (0x14UL) /* TRGM0 Input 4 (from IO) */
34 #define HPM_TRGM0_INPUT_SRC_TRGM0_P5 (0x15UL) /* TRGM0 Input 5 (from IO) */
35 #define HPM_TRGM0_INPUT_SRC_TRGM0_P6 (0x16UL) /* TRGM0 Input 6 (from IO) */
36 #define HPM_TRGM0_INPUT_SRC_TRGM0_P7 (0x17UL) /* TRGM0 Input 7 (from IO) */
37 #define HPM_TRGM0_INPUT_SRC_SYNT0_CH0 (0x18UL) /* SYNT0 Channel 0 */
38 #define HPM_TRGM0_INPUT_SRC_SYNT0_CH1 (0x19UL) /* SYNT0 Channel 1 */
39 #define HPM_TRGM0_INPUT_SRC_SYNT0_CH2 (0x1AUL) /* SYNT0 Channel 2 */
40 #define HPM_TRGM0_INPUT_SRC_SYNT0_CH3 (0x1BUL) /* SYNT0 channel 3 */
41 #define HPM_TRGM0_INPUT_SRC_MMC0_TRGO_0 (0x1CUL) /* MMC0 triggers output 0 */
42 #define HPM_TRGM0_INPUT_SRC_MMC0_TRGO_1 (0x1DUL) /* MMC0 triggers output 1 */
43 #define HPM_TRGM0_INPUT_SRC_MMC1_TRGO_0 (0x1EUL) /* MMC1 triggers output 0 */
44 #define HPM_TRGM0_INPUT_SRC_MMC1_TRGO_1 (0x1FUL) /* MMC1 triggers output 1 */
45 #define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_0 (0x20UL) /* QEO0 triggers output 0 */
46 #define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_1 (0x21UL) /* QEO0 triggers output 1 */
47 #define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_2 (0x22UL) /* QEO0 triggers output 2 */
48 #define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_3 (0x23UL) /* QEO0 triggers output 3 */
49 #define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_4 (0x24UL) /* QEO0 triggers output 4 */
50 #define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_5 (0x25UL) /* QEO0 triggers output 5 */
51 #define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_6 (0x26UL) /* QEO0 triggers output 6 */
52 #define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_7 (0x27UL) /* QEO0 triggers output 7 */
53 #define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_0 (0x28UL) /* QEO1 triggers output 0 */
54 #define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_1 (0x29UL) /* QEO1 triggers output 1 */
55 #define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_2 (0x2AUL) /* QEO1 triggers output 2 */
56 #define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_3 (0x2BUL) /* QEO1 triggers output 3 */
57 #define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_4 (0x2CUL) /* QEO1 triggers output 4 */
58 #define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_5 (0x2DUL) /* QEO1 triggers output 5 */
59 #define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_6 (0x2EUL) /* QEO1 triggers output 6 */
60 #define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_7 (0x2FUL) /* QEO1 triggers output 7 */
61 #define HPM_TRGM0_INPUT_SRC_PWM0_CH8REF (0x30UL) /* PWM timer 0 channel 8 reference output */
62 #define HPM_TRGM0_INPUT_SRC_PWM0_CH9REF (0x31UL) /* PWM timer 0 channel 9 reference output */
63 #define HPM_TRGM0_INPUT_SRC_PWM0_CH10REF (0x32UL) /* PWM timer 0 channel 10 reference output */
64 #define HPM_TRGM0_INPUT_SRC_PWM0_CH11REF (0x33UL) /* PWM timer 0 channel 11 reference output */
65 #define HPM_TRGM0_INPUT_SRC_PWM0_CH12REF (0x34UL) /* PWM timer 0 channel 12 reference output */
66 #define HPM_TRGM0_INPUT_SRC_PWM0_CH13REF (0x35UL) /* PWM timer 0 channel 13 reference output */
67 #define HPM_TRGM0_INPUT_SRC_PWM0_CH14REF (0x36UL) /* PWM timer 0 channel 14 reference output */
68 #define HPM_TRGM0_INPUT_SRC_PWM0_CH15REF (0x37UL) /* PWM timer 0 channel 15 reference output */
69 #define HPM_TRGM0_INPUT_SRC_PWM1_CH8REF (0x38UL) /* PWM timer 1 channel 8 reference output */
70 #define HPM_TRGM0_INPUT_SRC_PWM1_CH9REF (0x39UL) /* PWM timer 1 channel 9 reference output */
71 #define HPM_TRGM0_INPUT_SRC_PWM1_CH10REF (0x3AUL) /* PWM timer 1 channel 10 reference output */
72 #define HPM_TRGM0_INPUT_SRC_PWM1_CH11REF (0x3BUL) /* PWM timer 1 channel 11 reference output */
73 #define HPM_TRGM0_INPUT_SRC_PWM1_CH12REF (0x3CUL) /* PWM timer 1 channel 12 reference output */
74 #define HPM_TRGM0_INPUT_SRC_PWM1_CH13REF (0x3DUL) /* PWM timer 1 channel 13 reference output */
75 #define HPM_TRGM0_INPUT_SRC_PWM1_CH14REF (0x3EUL) /* PWM timer 1 channel 14 reference output */
76 #define HPM_TRGM0_INPUT_SRC_PWM1_CH15REF (0x3FUL) /* PWM timer 1 channel 15 reference output */
77 #define HPM_TRGM0_INPUT_SRC_PLB_OUT00 (0x40UL) /* PLB module output 0 */
78 #define HPM_TRGM0_INPUT_SRC_PLB_OUT01 (0x41UL) /* PLB module output 1 */
79 #define HPM_TRGM0_INPUT_SRC_PLB_OUT02 (0x42UL) /* PLB module output 2 */
80 #define HPM_TRGM0_INPUT_SRC_PLB_OUT03 (0x43UL) /* PLB module output 3 */
81 #define HPM_TRGM0_INPUT_SRC_PLB_OUT04 (0x44UL) /* PLB module output 4 */
82 #define HPM_TRGM0_INPUT_SRC_PLB_OUT05 (0x45UL) /* PLB module output 5 */
83 #define HPM_TRGM0_INPUT_SRC_PLB_OUT06 (0x46UL) /* PLB module output 6 */
84 #define HPM_TRGM0_INPUT_SRC_PLB_OUT07 (0x47UL) /* PLB module output 7 */
85 #define HPM_TRGM0_INPUT_SRC_PLB_OUT08 (0x48UL) /* PLB module output 8 */
86 #define HPM_TRGM0_INPUT_SRC_PLB_OUT09 (0x49UL) /* PLB module output 9 */
87 #define HPM_TRGM0_INPUT_SRC_PLB_OUT10 (0x4AUL) /* PLB module output 10 */
88 #define HPM_TRGM0_INPUT_SRC_PLB_OUT11 (0x4BUL) /* PLB module output 11 */
89 #define HPM_TRGM0_INPUT_SRC_PLB_OUT12 (0x4CUL) /* PLB module output 12 */
90 #define HPM_TRGM0_INPUT_SRC_PLB_OUT13 (0x4DUL) /* PLB module output 13 */
91 #define HPM_TRGM0_INPUT_SRC_PLB_OUT14 (0x4EUL) /* PLB module output 14 */
92 #define HPM_TRGM0_INPUT_SRC_PLB_OUT15 (0x4FUL) /* PLB module output 15 */
93 #define HPM_TRGM0_INPUT_SRC_PLB_OUT16 (0x50UL) /* PLB module output 16 */
94 #define HPM_TRGM0_INPUT_SRC_PLB_OUT17 (0x51UL) /* PLB module output 17 */
95 #define HPM_TRGM0_INPUT_SRC_PLB_OUT18 (0x52UL) /* PLB module output 18 */
96 #define HPM_TRGM0_INPUT_SRC_PLB_OUT19 (0x53UL) /* PLB module output 19 */
97 #define HPM_TRGM0_INPUT_SRC_PLB_OUT20 (0x54UL) /* PLB module output 20 */
98 #define HPM_TRGM0_INPUT_SRC_PLB_OUT21 (0x55UL) /* PLB module output 21 */
99 #define HPM_TRGM0_INPUT_SRC_PLB_OUT22 (0x56UL) /* PLB module output 22 */
100 #define HPM_TRGM0_INPUT_SRC_PLB_OUT23 (0x57UL) /* PLB module output 23 */
101 #define HPM_TRGM0_INPUT_SRC_PLB_OUT24 (0x58UL) /* PLB module output 24 */
102 #define HPM_TRGM0_INPUT_SRC_PLB_OUT25 (0x59UL) /* PLB module output 25 */
103 #define HPM_TRGM0_INPUT_SRC_PLB_OUT26 (0x5AUL) /* PLB module output 26 */
104 #define HPM_TRGM0_INPUT_SRC_PLB_OUT27 (0x5BUL) /* PLB module output 27 */
105 #define HPM_TRGM0_INPUT_SRC_PLB_OUT28 (0x5CUL) /* PLB module output 28 */
106 #define HPM_TRGM0_INPUT_SRC_PLB_OUT29 (0x5DUL) /* PLB module output 29 */
107 #define HPM_TRGM0_INPUT_SRC_PLB_OUT30 (0x5EUL) /* PLB module output 30 */
108 #define HPM_TRGM0_INPUT_SRC_PLB_OUT31 (0x5FUL) /* PLB module output 31 */
109 #define HPM_TRGM0_INPUT_SRC_RDC_TRGO_0 (0x60UL) /* RDC triggers output 0 */
110 #define HPM_TRGM0_INPUT_SRC_RDC_TRGO_1 (0x61UL) /* RDC triggers output 1 */
111 #define HPM_TRGM0_INPUT_SRC_QEI1_TRGO (0x62UL) /* QEI1 triggers output */
112 #define HPM_TRGM0_INPUT_SRC_QEI0_TRGO (0x63UL) /* QEI0 triggers output */
113 #define HPM_TRGM0_INPUT_SRC_SEI_TRGO_0 (0x64UL) /* SEI triggers output 0 */
114 #define HPM_TRGM0_INPUT_SRC_SEI_TRGO_1 (0x65UL) /* SEI triggers output 1 */
115 #define HPM_TRGM0_INPUT_SRC_SEI_TRGO_2 (0x66UL) /* SEI triggers output 2 */
116 #define HPM_TRGM0_INPUT_SRC_SEI_TRGO_3 (0x67UL) /* SEI triggers output 3 */
117 #define HPM_TRGM0_INPUT_SRC_SEI_TRGO_4 (0x68UL) /* SEI triggers output 4 */
118 #define HPM_TRGM0_INPUT_SRC_SEI_TRGO_5 (0x69UL) /* SEI triggers output 5 */
119 #define HPM_TRGM0_INPUT_SRC_SEI_TRGO_6 (0x6AUL) /* SEI triggers output 6 */
120 #define HPM_TRGM0_INPUT_SRC_SEI_TRGO_7 (0x6BUL) /* SEI triggers output 7 */
121 #define HPM_TRGM0_INPUT_SRC_PWM0_FAULT0 (0x6CUL) /* PWM0 fault Input 0 (from IO) */
122 #define HPM_TRGM0_INPUT_SRC_PWM0_FAULT1 (0x6DUL) /* PWM0 fault Input 1 (from IO) */
123 #define HPM_TRGM0_INPUT_SRC_PWM1_FAULT0 (0x6EUL) /* PWM1 fault Input 0 (from IO) */
124 #define HPM_TRGM0_INPUT_SRC_PWM1_FAULT1 (0x6FUL) /* PWM1 fault Input 1 (from IO) */
125 #define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN0 (0x70UL) /* PWM0 Input 0 (from IO) */
126 #define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN1 (0x71UL) /* PWM0 Input 1 (from IO) */
127 #define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN2 (0x72UL) /* PWM0 Input 2 (from IO) */
128 #define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN3 (0x73UL) /* PWM0 Input 3 (from IO) */
129 #define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN4 (0x74UL) /* PWM0 Input 4 (from IO) */
130 #define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN5 (0x75UL) /* PWM0 Input 5 (from IO) */
131 #define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN6 (0x76UL) /* PWM0 Input 6 (from IO) */
132 #define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN7 (0x77UL) /* PWM0 Input 7 (from IO) */
133 #define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN0 (0x78UL) /* PWM1 Input 0 (from IO) */
134 #define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN1 (0x79UL) /* PWM1 Input 1 (from IO) */
135 #define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN2 (0x7AUL) /* PWM1 Input 2 (from IO) */
136 #define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN3 (0x7BUL) /* PWM1 Input 3 (from IO) */
137 #define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN4 (0x7CUL) /* PWM1 Input 4 (from IO) */
138 #define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN5 (0x7DUL) /* PWM1 Input 5 (from IO) */
139 #define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN6 (0x7EUL) /* PWM1 Input 6 (from IO) */
140 #define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN7 (0x7FUL) /* PWM1 Input 7 (from IO) */
141 
142 /* trgm0_output mux definitions */
143 #define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_0 (0x0UL) /* OPAMP0 triggers input 0 */
144 #define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_1 (0x1UL) /* OPAMP0 triggers input 1 */
145 #define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_2 (0x2UL) /* OPAMP0 triggers input 2 */
146 #define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_3 (0x3UL) /* OPAMP0 triggers input 3 */
147 #define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_4 (0x4UL) /* OPAMP0 triggers input 4 */
148 #define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_5 (0x5UL) /* OPAMP0 triggers input 5 */
149 #define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_6 (0x6UL) /* OPAMP0 triggers input 6 */
150 #define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_7 (0x7UL) /* OPAMP0 triggers input 7 */
151 #define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_0 (0x8UL) /* OPAMP1 triggers input 0 */
152 #define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_1 (0x9UL) /* OPAMP1 triggers input 1 */
153 #define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_2 (0xAUL) /* OPAMP1 triggers input 2 */
154 #define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_3 (0xBUL) /* OPAMP1 triggers input 3 */
155 #define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_4 (0xCUL) /* OPAMP1 triggers input 4 */
156 #define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_5 (0xDUL) /* OPAMP1 triggers input 5 */
157 #define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_6 (0xEUL) /* OPAMP1 triggers input 6 */
158 #define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_7 (0xFUL) /* OPAMP1 triggers input 7 */
159 #define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN2 (0x10UL) /* GPTMR0 channel 2 input */
160 #define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN3 (0x11UL) /* GPTMR0 channel 3 input */
161 #define HPM_TRGM0_OUTPUT_SRC_GPTMR0_SYNCI (0x12UL) /* GPTMR0 counter synchronous input */
162 #define HPM_TRGM0_OUTPUT_SRC_GPTMR1_IN2 (0x13UL) /* GPTMR1 channel 2 input */
163 #define HPM_TRGM0_OUTPUT_SRC_GPTMR1_IN3 (0x14UL) /* GPTMR1 channel 3 input */
164 #define HPM_TRGM0_OUTPUT_SRC_GPTMR1_SYNCI (0x15UL) /* GPTMR1 counter synchronous input */
165 #define HPM_TRGM0_OUTPUT_SRC_GPTMR2_IN2 (0x16UL) /* GPTMR2 channel 2 input; This bit is also activated as DAC0 ladder mode 1 */
166 #define HPM_TRGM0_OUTPUT_SRC_GPTMR2_IN3 (0x17UL) /* GPTMR2 channel 3 input; This bit is also activated as DAC0 ladder mode 2 */
167 #define HPM_TRGM0_OUTPUT_SRC_GPTMR2_SYNCI (0x18UL) /* GPTMR2 counter synchronous input; This bit is also activated as DAC0 ladder mode 3 */
168 #define HPM_TRGM0_OUTPUT_SRC_GPTMR3_IN2 (0x19UL) /* GPTMR3 channel 2 input; This bit is also activated as DAC1 ladder mode 1 */
169 #define HPM_TRGM0_OUTPUT_SRC_GPTMR3_IN3 (0x1AUL) /* GPTMR3 channel 3 input; This bit is also activated as DAC1 ladder mode 2 */
170 #define HPM_TRGM0_OUTPUT_SRC_GPTMR3_SYNCI (0x1BUL) /* GPTMR3 counter synchronous input; This bit is also activated as DAC1 ladder mode 3 */
171 #define HPM_TRGM0_OUTPUT_SRC_ACMP0_WIN (0x1CUL) /* Comparator 0 window mode input */
172 #define HPM_TRGM0_OUTPUT_SRC_ACMP1_WIN (0x1DUL) /* Comparator 1 window mode input */
173 #define HPM_TRGM0_OUTPUT_SRC_DAC0_BUFTRG (0x1EUL) /* DAC0 buffer mode starts to trigger; This bit is also activated as DAC0 ladder mode 0 */
174 #define HPM_TRGM0_OUTPUT_SRC_DAC1_BUFTRG (0x1FUL) /* DAC1 buffer mode starts to trigger; This bit is also activated as DAC1 ladder mode 0 */
175 #define HPM_TRGM0_OUTPUT_SRC_ADC0_STRGI (0x20UL) /* The sequence conversion of ADC0 triggers input */
176 #define HPM_TRGM0_OUTPUT_SRC_ADC1_STRGI (0x21UL) /* The sequence conversion of ADC1 triggers input */
177 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A (0x22UL) /* The preemption conversion of ADC0, 1 triggers input 0A */
178 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0B (0x23UL) /* The preemption conversion of ADC0, 1 triggers input 0B */
179 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0C (0x24UL) /* The preemption conversion of ADC0, 1 triggers input 0C */
180 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI1A (0x25UL) /* The preemption conversion of ADC0, 1 triggers input 1A */
181 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI1B (0x26UL) /* The preemption conversion of ADC0, 1 triggers input 1B */
182 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI1C (0x27UL) /* The preemption conversion of ADC0, 1 triggers input 1C */
183 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI2A (0x28UL) /* The preemption conversion of ADC0, 1 triggers input 2A */
184 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI2B (0x29UL) /* The preemption conversion of ADC0, 1 triggers input 2B */
185 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI2C (0x2AUL) /* The preemption conversion of ADC0, 1 triggers input 2C */
186 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI3A (0x2BUL) /* The preemption conversion of ADC0, 1 triggers input 3A */
187 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI3B (0x2CUL) /* The preemption conversion of ADC0, 1 triggers input 3B */
188 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI3C (0x2DUL) /* The preemption conversion of ADC0, 1 triggers input 3C */
189 #define HPM_TRGM0_OUTPUT_SRC_MCAN_PTPC0_CAP (0x2EUL) /* PTPC input capture 0 */
190 #define HPM_TRGM0_OUTPUT_SRC_MCAN_PTPC1_CAP (0x2FUL) /* PTPC input capture 1 */
191 #define HPM_TRGM0_OUTPUT_SRC_QEO0_TRIG_IN0 (0x30UL) /* QEO0 triggers input 0 */
192 #define HPM_TRGM0_OUTPUT_SRC_QEO0_TRIG_IN1 (0x31UL) /* QEO0 triggers input 1 */
193 #define HPM_TRGM0_OUTPUT_SRC_QEO1_TRIG_IN0 (0x32UL) /* QEO1 triggers input 0 */
194 #define HPM_TRGM0_OUTPUT_SRC_QEO1_TRIG_IN1 (0x33UL) /* QEO1 triggers input 1 */
195 #define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN0 (0x34UL) /* SEI triggers input 0 */
196 #define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN1 (0x35UL) /* SEI triggers input 1 */
197 #define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN2 (0x36UL) /* SEI triggers input 2 */
198 #define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN3 (0x37UL) /* SEI triggers input 3 */
199 #define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN4 (0x38UL) /* SEI triggers input 4 */
200 #define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN5 (0x39UL) /* SEI triggers input 5 */
201 #define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN6 (0x3AUL) /* SEI triggers input 6 */
202 #define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN7 (0x3BUL) /* SEI triggers input 7 */
203 #define HPM_TRGM0_OUTPUT_SRC_MMC0_TRIG_IN0 (0x3CUL) /* MMC0 triggers input 0 */
204 #define HPM_TRGM0_OUTPUT_SRC_MMC0_TRIG_IN1 (0x3DUL) /* MMC0 triggers input 1 */
205 #define HPM_TRGM0_OUTPUT_SRC_MMC1_TRIG_IN0 (0x3EUL) /* MMC1 triggers input 0 */
206 #define HPM_TRGM0_OUTPUT_SRC_MMC1_TRIG_IN1 (0x3FUL) /* MMC1 triggers input 1 */
207 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_00 (0x40UL) /* PLB module input 00 */
208 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_01 (0x41UL) /* PLB module input 01 */
209 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_02 (0x42UL) /* PLB module input 02 */
210 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_03 (0x43UL) /* PLB module input 03 */
211 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_04 (0x44UL) /* PLB module input 04 */
212 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_05 (0x45UL) /* PLB module input 05 */
213 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_06 (0x46UL) /* PLB module input 06 */
214 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_07 (0x47UL) /* PLB module input 07 */
215 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_08 (0x48UL) /* PLB module input 08 */
216 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_09 (0x49UL) /* PLB module input 09 */
217 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_10 (0x4AUL) /* PLB module input 10 */
218 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_11 (0x4BUL) /* PLB module input 11 */
219 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_12 (0x4CUL) /* PLB module input 12 */
220 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_13 (0x4DUL) /* PLB module input 13 */
221 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_14 (0x4EUL) /* PLB module input 14 */
222 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_15 (0x4FUL) /* PLB module input 15 */
223 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_16 (0x50UL) /* PLB module input 16 */
224 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_17 (0x51UL) /* PLB module input 17 */
225 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_18 (0x52UL) /* PLB module input 18 */
226 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_19 (0x53UL) /* PLB module input 19 */
227 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_20 (0x54UL) /* PLB module input 20 */
228 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_21 (0x55UL) /* PLB module input 21 */
229 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_22 (0x56UL) /* PLB module input 22 */
230 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_23 (0x57UL) /* PLB module input 23 */
231 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_24 (0x58UL) /* PLB module input 24 */
232 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_25 (0x59UL) /* PLB module input 25 */
233 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_26 (0x5AUL) /* PLB module input 26 */
234 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_27 (0x5BUL) /* PLB module input 27 */
235 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_28 (0x5CUL) /* PLB module input 28 */
236 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_29 (0x5DUL) /* PLB module input 29 */
237 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_30 (0x5EUL) /* PLB module input 30 */
238 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_31 (0x5FUL) /* PLB module input 31 */
239 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO0 (0x60UL) /* TRGM Output 0 (output to IO) (dropped macro please use macro TRGM0_P0) */
240 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P0 (0x60UL) /* TRGM Output 0 (output to IO) */
241 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO1 (0x61UL) /* TRGM Output 1 (output to IO) (dropped macro please use macro TRGM0_P1) */
242 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P1 (0x61UL) /* TRGM Output 1 (output to IO) */
243 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO2 (0x62UL) /* TRGM Output 2 (output to IO) (dropped macro please use macro TRGM0_P2) */
244 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P2 (0x62UL) /* TRGM Output 2 (output to IO) */
245 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO3 (0x63UL) /* TRGM Output 3 (output to IO) (dropped macro please use macro TRGM0_P3) */
246 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P3 (0x63UL) /* TRGM Output 3 (output to IO) */
247 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO4 (0x64UL) /* TRGM Output 4 (output to IO) (dropped macro please use macro TRGM0_P4) */
248 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P4 (0x64UL) /* TRGM Output 4 (output to IO) */
249 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO5 (0x65UL) /* TRGM Output 5 (output to IO) (dropped macro please use macro TRGM0_P5) */
250 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P5 (0x65UL) /* TRGM Output 5 (output to IO) */
251 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO6 (0x66UL) /* TRGM Output 6 (output to IO) (dropped macro please use macro TRGM0_P6) */
252 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P6 (0x66UL) /* TRGM Output 6 (output to IO) */
253 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO7 (0x67UL) /* TRGM Output 7 (output to IO) (dropped macro please use macro TRGM0_P7) */
254 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P7 (0x67UL) /* TRGM Output 7 (output to IO) */
255 #define HPM_TRGM0_OUTPUT_SRC_PWM_IN8 (0x68UL) /* PWM timer x capture input 8 */
256 #define HPM_TRGM0_OUTPUT_SRC_PWM_IN9 (0x69UL) /* PWM timer x capture input 9 */
257 #define HPM_TRGM0_OUTPUT_SRC_PWM_IN10 (0x6AUL) /* PWM timer x capture input 10 */
258 #define HPM_TRGM0_OUTPUT_SRC_PWM_IN11 (0x6BUL) /* PWM timer x capture input 11 */
259 #define HPM_TRGM0_OUTPUT_SRC_PWM_IN12 (0x6CUL) /* PWM timer x capture input 12 */
260 #define HPM_TRGM0_OUTPUT_SRC_PWM_IN13 (0x6DUL) /* PWM timer x capture input 13 */
261 #define HPM_TRGM0_OUTPUT_SRC_PWM_IN14 (0x6EUL) /* PWM timer x capture input 14 */
262 #define HPM_TRGM0_OUTPUT_SRC_PWM_IN15 (0x6FUL) /* PWM timer x capture input 15 */
263 #define HPM_TRGM0_OUTPUT_SRC_PWM0_FRCI (0x70UL) /* the input value for PWM timer 0 forces control */
264 #define HPM_TRGM0_OUTPUT_SRC_PWM0_FRCSYNCI (0x71UL) /* the synchronous input for PWM timer 0 forces control */
265 #define HPM_TRGM0_OUTPUT_SRC_PWM0_SYNCI (0x72UL) /* PWM timer 0 counter synchronously triggers input */
266 #define HPM_TRGM0_OUTPUT_SRC_PWM0_SHRLDSYNCI (0x73UL) /* PWM timer 0 Shadow register to activate trigger input */
267 #define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI0 (0x74UL) /* PWM timer 0 Fault protection input 0 */
268 #define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI1 (0x75UL) /* PWM timer 0 Fault protection input 1 */
269 #define HPM_TRGM0_OUTPUT_SRC_PWM1_FRCI (0x76UL) /* the input value for PWM timer 1 forces control */
270 #define HPM_TRGM0_OUTPUT_SRC_PWM1_FRCSYNCI (0x77UL) /* the synchronous input for PWM timer 1 forces control */
271 #define HPM_TRGM0_OUTPUT_SRC_PWM1_SYNCI (0x78UL) /* PWM timer 1 Counter synchronizes trigger input */
272 #define HPM_TRGM0_OUTPUT_SRC_PWM1_SHRLDSYNCI (0x79UL) /* PWM timer 1 Shadow register kicks in trigger input */
273 #define HPM_TRGM0_OUTPUT_SRC_PWM1_FAULTI0 (0x7AUL) /* PWM timer 1 Fault protection input 0 */
274 #define HPM_TRGM0_OUTPUT_SRC_PWM1_FAULTI1 (0x7BUL) /* PWM timer 1 Fault protection Input 1 */
275 #define HPM_TRGM0_OUTPUT_SRC_RDC_TRIG_IN0 (0x7CUL) /* RDC triggers input 0 */
276 #define HPM_TRGM0_OUTPUT_SRC_RDC_TRIG_IN1 (0x7DUL) /* RDC triggers input 1 */
277 #define HPM_TRGM0_OUTPUT_SRC_SYNCTIMER_TRIG (0x7EUL) /* SYNT triggers input */
278 #define HPM_TRGM0_OUTPUT_SRC_QEI0_TRIG_IN (0x7FUL) /* QEI0 triggers input */
279 #define HPM_TRGM0_OUTPUT_SRC_QEI1_TRIG_IN (0x80UL) /* QEI1 triggers input */
280 #define HPM_TRGM0_OUTPUT_SRC_QEI0_PAUSE (0x81UL) /* QEI0 Pause input */
281 #define HPM_TRGM0_OUTPUT_SRC_QEI1_PAUSE (0x82UL) /* QEI1 Pause input */
282 #define HPM_TRGM0_OUTPUT_SRC_UART_TRIG0 (0x83UL) /* UART0/1/2/3 Trigger signal */
283 #define HPM_TRGM0_OUTPUT_SRC_UART_TRIG1 (0x84UL) /* UART4/5/6/7 Trigger signal */
284 #define HPM_TRGM0_OUTPUT_SRC_TRGM_IRQ0 (0x85UL) /* TRGM interrupt signal 0 */
285 #define HPM_TRGM0_OUTPUT_SRC_TRGM_IRQ1 (0x86UL) /* TRGM interrupt signal 1 */
286 #define HPM_TRGM0_OUTPUT_SRC_TRGM_DMA0 (0x87UL) /* TRGM DMA request 0 */
287 #define HPM_TRGM0_OUTPUT_SRC_TRGM_DMA1 (0x88UL) /* TRGM DMA request 1 */
288 
289 /* trgm0_filter mux definitions */
290 #define HPM_TRGM0_FILTER_SRC_PWM0_IN0 (0x0UL) /* PWM timer 0 capture Input 0 */
291 #define HPM_TRGM0_FILTER_SRC_PWM0_IN1 (0x1UL) /* PWM timer 0 capture Input 1 */
292 #define HPM_TRGM0_FILTER_SRC_PWM0_IN2 (0x2UL) /* PWM timer 0 capture Input 2 */
293 #define HPM_TRGM0_FILTER_SRC_PWM0_IN3 (0x3UL) /* PWM timer 0 capture Input 3 */
294 #define HPM_TRGM0_FILTER_SRC_PWM0_IN4 (0x4UL) /* PWM timer 0 capture Input 4 */
295 #define HPM_TRGM0_FILTER_SRC_PWM0_IN5 (0x5UL) /* PWM timer 0 capture Input 5 */
296 #define HPM_TRGM0_FILTER_SRC_PWM0_IN6 (0x6UL) /* PWM timer 0 capture Input 6 */
297 #define HPM_TRGM0_FILTER_SRC_PWM0_IN7 (0x7UL) /* PWM timer 0 capture Input 7 */
298 #define HPM_TRGM0_FILTER_SRC_PWM1_IN0 (0x8UL) /* PWM timer 1 capture Input 0 */
299 #define HPM_TRGM0_FILTER_SRC_PWM1_IN1 (0x9UL) /* PWM timer 1 capture Input 1 */
300 #define HPM_TRGM0_FILTER_SRC_PWM1_IN2 (0xAUL) /* PWM timer 1 capture Input 2 */
301 #define HPM_TRGM0_FILTER_SRC_PWM1_IN3 (0xBUL) /* PWM timer 1 capture Input 3 */
302 #define HPM_TRGM0_FILTER_SRC_PWM1_IN4 (0xCUL) /* PWM timer 1 capture Input 4 */
303 #define HPM_TRGM0_FILTER_SRC_PWM1_IN5 (0xDUL) /* PWM timer 1 capture Input 5 */
304 #define HPM_TRGM0_FILTER_SRC_PWM1_IN6 (0xEUL) /* PWM timer 1 capture Input 6 */
305 #define HPM_TRGM0_FILTER_SRC_PWM1_IN7 (0xFUL) /* PWM timer 1 capture Input 7 */
306 #define HPM_TRGM0_FILTER_SRC_TRGM_IN0 (0x10UL) /* TRGM input 0 (dropped macro please use macro TRGM0_P00) */
307 #define HPM_TRGM0_FILTER_SRC_TRGM_P00 (0x10UL) /* TRGM input 0 from IO */
308 #define HPM_TRGM0_FILTER_SRC_TRGM_IN1 (0x11UL) /* TRGM input 1 (dropped macro please use macro TRGM0_P00) */
309 #define HPM_TRGM0_FILTER_SRC_TRGM_P01 (0x11UL) /* TRGM input 1 from IO */
310 #define HPM_TRGM0_FILTER_SRC_TRGM_IN2 (0x12UL) /* TRGM input 2 (dropped macro please use macro TRGM0_P00) */
311 #define HPM_TRGM0_FILTER_SRC_TRGM_P02 (0x12UL) /* TRGM input 2 from IO */
312 #define HPM_TRGM0_FILTER_SRC_TRGM_IN3 (0x13UL) /* TRGM input 3 (dropped macro please use macro TRGM0_P00) */
313 #define HPM_TRGM0_FILTER_SRC_TRGM_P03 (0x13UL) /* TRGM input 3 from IO */
314 #define HPM_TRGM0_FILTER_SRC_TRGM_IN4 (0x14UL) /* TRGM input 4 (dropped macro please use macro TRGM0_P00) */
315 #define HPM_TRGM0_FILTER_SRC_TRGM_P04 (0x14UL) /* TRGM input 4 from IO */
316 #define HPM_TRGM0_FILTER_SRC_TRGM_IN5 (0x15UL) /* TRGM input 5 (dropped macro please use macro TRGM0_P00) */
317 #define HPM_TRGM0_FILTER_SRC_TRGM_P05 (0x15UL) /* TRGM input 5 from IO */
318 #define HPM_TRGM0_FILTER_SRC_TRGM_IN6 (0x16UL) /* TRGM input 6 (dropped macro please use macro TRGM0_P00) */
319 #define HPM_TRGM0_FILTER_SRC_TRGM_P06 (0x16UL) /* TRGM input 6 from IO */
320 #define HPM_TRGM0_FILTER_SRC_TRGM_IN7 (0x17UL) /* TRGM input 7 (dropped macro please use macro TRGM0_P00) */
321 #define HPM_TRGM0_FILTER_SRC_TRGM_P07 (0x17UL) /* TRGM input 7 from IO */
322 #define HPM_TRGM0_FILTER_SRC_PWM0_FAULT0 (0x18UL) /* PWM timer 0 Input fault0 */
323 #define HPM_TRGM0_FILTER_SRC_PWM0_FAULT1 (0x19UL) /* PWM timer 0 Input fault1 */
324 #define HPM_TRGM0_FILTER_SRC_PWM1_FAULT0 (0x1AUL) /* PWM timer 1 Input fault0 */
325 #define HPM_TRGM0_FILTER_SRC_PWM1_FAULT1 (0x1BUL) /* PWM timer 1 Input fault1 */
326 
327 /* trgm0_dma mux definitions */
328 #define HPM_TRGM0_DMA_SRC_PWM0_CMP0 (0x0UL) /* The capture input or matches output of PWM timer 0 comparator 0 */
329 #define HPM_TRGM0_DMA_SRC_PWM0_CMP1 (0x1UL) /* The capture input or matches output of PWM timer 0 comparator 1 */
330 #define HPM_TRGM0_DMA_SRC_PWM0_CMP2 (0x2UL) /* The capture input or matches output of PWM timer 0 comparator 2 */
331 #define HPM_TRGM0_DMA_SRC_PWM0_CMP3 (0x3UL) /* The capture input or matches output of PWM timer 0 comparator 3 */
332 #define HPM_TRGM0_DMA_SRC_PWM0_CMP4 (0x4UL) /* The capture input or matches output of PWM timer 0 comparator 4 */
333 #define HPM_TRGM0_DMA_SRC_PWM0_CMP5 (0x5UL) /* The capture input or matches output of PWM timer 0 comparator 5 */
334 #define HPM_TRGM0_DMA_SRC_PWM0_CMP6 (0x6UL) /* The capture input or matches output of PWM timer 0 comparator 6 */
335 #define HPM_TRGM0_DMA_SRC_PWM0_CMP7 (0x7UL) /* The capture input or matches output of PWM timer 0 comparator 7 */
336 #define HPM_TRGM0_DMA_SRC_PWM0_CMP8 (0x8UL) /* The capture input or matches output of PWM timer 0 comparator 8 */
337 #define HPM_TRGM0_DMA_SRC_PWM0_CMP9 (0x9UL) /* The capture input or matches output of PWM timer 0 comparator 9 */
338 #define HPM_TRGM0_DMA_SRC_PWM0_CMP10 (0xAUL) /* The capture input or matches output of PWM timer 0 comparator 10 */
339 #define HPM_TRGM0_DMA_SRC_PWM0_CMP11 (0xBUL) /* The capture input or matches output of PWM timer 0 comparator 11 */
340 #define HPM_TRGM0_DMA_SRC_PWM0_CMP12 (0xCUL) /* The capture input or matches output of PWM timer 0 comparator 12 */
341 #define HPM_TRGM0_DMA_SRC_PWM0_CMP13 (0xDUL) /* The capture input or matches output of PWM timer 0 comparator 13 */
342 #define HPM_TRGM0_DMA_SRC_PWM0_CMP14 (0xEUL) /* The capture input or matches output of PWM timer 0 comparator 14 */
343 #define HPM_TRGM0_DMA_SRC_PWM0_CMP15 (0xFUL) /* The capture input or matches output of PWM timer 0 comparator 15 */
344 #define HPM_TRGM0_DMA_SRC_PWM0_CMP16 (0x10UL) /* The capture input or matches output of PWM timer 0 comparator 16 */
345 #define HPM_TRGM0_DMA_SRC_PWM0_CMP17 (0x11UL) /* The capture input or matches output of PWM timer 0 comparator 17 */
346 #define HPM_TRGM0_DMA_SRC_PWM0_CMP18 (0x12UL) /* The capture input or matches output of PWM timer 0 comparator 18 */
347 #define HPM_TRGM0_DMA_SRC_PWM0_CMP19 (0x13UL) /* The capture input or matches output of PWM timer 0 comparator 19 */
348 #define HPM_TRGM0_DMA_SRC_PWM0_CMP20 (0x14UL) /* The capture input or matches output of PWM timer 0 comparator 20 */
349 #define HPM_TRGM0_DMA_SRC_PWM0_CMP21 (0x15UL) /* The capture input or matches output of PWM timer 0 comparator 21 */
350 #define HPM_TRGM0_DMA_SRC_PWM0_CMP22 (0x16UL) /* The capture input or matches output of PWM timer 0 comparator 22 */
351 #define HPM_TRGM0_DMA_SRC_PWM0_CMP23 (0x17UL) /* The capture input or matches output of PWM timer 0 comparator 23 */
352 #define HPM_TRGM0_DMA_SRC_PWM0_RLD (0x18UL) /* PWM timer 0 counter reload */
353 #define HPM_TRGM0_DMA_SRC_PWM0_HALFRLD (0x19UL) /* PWM timer 0 half cycle reload */
354 #define HPM_TRGM0_DMA_SRC_PWM0_XRLD (0x1AUL) /* PWM timer 0 extended counter reload */
355 #define HPM_TRGM0_DMA_SRC_PWM1_CMP0 (0x1BUL) /* The capture input or matches output of PWM timer 1 comparator 0 */
356 #define HPM_TRGM0_DMA_SRC_PWM1_CMP1 (0x1CUL) /* The capture input or matches output of PWM timer 1 comparator 1 */
357 #define HPM_TRGM0_DMA_SRC_PWM1_CMP2 (0x1DUL) /* The capture input or matches output of PWM timer 1 comparator 2 */
358 #define HPM_TRGM0_DMA_SRC_PWM1_CMP3 (0x1EUL) /* The capture input or matches output of PWM timer 1 comparator 3 */
359 #define HPM_TRGM0_DMA_SRC_PWM1_CMP4 (0x1FUL) /* The capture input or matches output of PWM timer 1 comparator 4 */
360 #define HPM_TRGM0_DMA_SRC_PWM1_CMP5 (0x20UL) /* The capture input or matches output of PWM timer 1 comparator 5 */
361 #define HPM_TRGM0_DMA_SRC_PWM1_CMP6 (0x21UL) /* The capture input or matches output of PWM timer 1 comparator 6 */
362 #define HPM_TRGM0_DMA_SRC_PWM1_CMP7 (0x22UL) /* The capture input or matches output of PWM timer 1 comparator 7 */
363 #define HPM_TRGM0_DMA_SRC_PWM1_CMP8 (0x23UL) /* The capture input or matches output of PWM timer 1 comparator 8 */
364 #define HPM_TRGM0_DMA_SRC_PWM1_CMP9 (0x24UL) /* The capture input or matches output of PWM timer 1 comparator 9 */
365 #define HPM_TRGM0_DMA_SRC_PWM1_CMP10 (0x25UL) /* The capture input or matches output of PWM timer 1 comparator 10 */
366 #define HPM_TRGM0_DMA_SRC_PWM1_CMP11 (0x26UL) /* The capture input or matches output of PWM timer 1 comparator 11 */
367 #define HPM_TRGM0_DMA_SRC_PWM1_CMP12 (0x27UL) /* The capture input or matches output of PWM timer 1 comparator 12 */
368 #define HPM_TRGM0_DMA_SRC_PWM1_CMP13 (0x28UL) /* The capture input or matches output of PWM timer 1 comparator 13 */
369 #define HPM_TRGM0_DMA_SRC_PWM1_CMP14 (0x29UL) /* The capture input or matches output of PWM timer 1 comparator 14 */
370 #define HPM_TRGM0_DMA_SRC_PWM1_CMP15 (0x2AUL) /* The capture input or matches output of PWM timer 1 comparator 15 */
371 #define HPM_TRGM0_DMA_SRC_PWM1_CMP16 (0x2BUL) /* The capture input or matches output of PWM timer 1 comparator 16 */
372 #define HPM_TRGM0_DMA_SRC_PWM1_CMP17 (0x2CUL) /* The capture input or matches output of PWM timer 1 comparator 17 */
373 #define HPM_TRGM0_DMA_SRC_PWM1_CMP18 (0x2DUL) /* The capture input or matches output of PWM timer 1 comparator 18 */
374 #define HPM_TRGM0_DMA_SRC_PWM1_CMP19 (0x2EUL) /* The capture input or matches output of PWM timer 1 comparator 19 */
375 #define HPM_TRGM0_DMA_SRC_PWM1_CMP20 (0x2FUL) /* The capture input or matches output of PWM timer 1 comparator 20 */
376 #define HPM_TRGM0_DMA_SRC_PWM1_CMP21 (0x30UL) /* The capture input or matches output of PWM timer 1 comparator 21 */
377 #define HPM_TRGM0_DMA_SRC_PWM1_CMP22 (0x31UL) /* The capture input or matches output of PWM timer 1 comparator 22 */
378 #define HPM_TRGM0_DMA_SRC_PWM1_CMP23 (0x32UL) /* The capture input or matches output of PWM timer 1 comparator 23 */
379 #define HPM_TRGM0_DMA_SRC_PWM1_RLD (0x33UL) /* PWM timer 1 Counter reload */
380 #define HPM_TRGM0_DMA_SRC_PWM1_HALFRLD (0x34UL) /* PWM timer 1 half cycle reload */
381 #define HPM_TRGM0_DMA_SRC_PWM1_XRLD (0x35UL) /* PWM timer 1 Extended counter reload */
382 #define HPM_TRGM0_DMA_SRC_QEI0 (0x36UL) /* DMA request for QEI0 */
383 #define HPM_TRGM0_DMA_SRC_QEI1 (0x37UL) /* DMA request for QEI1 */
384 #define HPM_TRGM0_DMA_SRC_MMC0 (0x38UL) /* DMA request for MMC0 */
385 #define HPM_TRGM0_DMA_SRC_MMC1 (0x39UL) /* DMA request for MMC1 */
386 #define HPM_TRGM0_DMA_SRC_SEI0 (0x3AUL) /* DMA request 0 for SEI0 */
387 #define HPM_TRGM0_DMA_SRC_SEI1 (0x3BUL) /* DMA request 0 for SEI1 */
388 #define HPM_TRGM0_DMA_SRC_TRGM0 (0x3CUL) /* DMA request 0 for TRGM (from TRGM output 135) */
389 #define HPM_TRGM0_DMA_SRC_TRGM1 (0x3DUL) /* DMA request 1 for TRGM (from TRGM output 136) */
390 
391 
392 
393 #endif /* HPM_TRGMMUX_SRC_H */