HPM SDK
HPMicro Software Development Kit
hpm_adc16_regs.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_ADC16_H
10 #define HPM_ADC16_H
11 
12 typedef struct {
13  __RW uint32_t CONFIG[12]; /* 0x0 - 0x2C: */
14  __RW uint32_t TRG_DMA_ADDR; /* 0x30: */
15  __RW uint32_t TRG_SW_STA; /* 0x34: */
16  __R uint8_t RESERVED0[968]; /* 0x38 - 0x3FF: Reserved */
17  __R uint32_t BUS_RESULT[16]; /* 0x400 - 0x43C: */
18  __R uint8_t RESERVED1[192]; /* 0x440 - 0x4FF: Reserved */
19  __RW uint32_t BUF_CFG0; /* 0x500: */
20  __R uint8_t RESERVED2[764]; /* 0x504 - 0x7FF: Reserved */
21  __RW uint32_t SEQ_CFG0; /* 0x800: */
22  __RW uint32_t SEQ_DMA_ADDR; /* 0x804: */
23  __R uint32_t SEQ_WR_ADDR; /* 0x808: */
24  __RW uint32_t SEQ_DMA_CFG; /* 0x80C: */
25  __RW uint32_t SEQ_QUE[16]; /* 0x810 - 0x84C: */
26  __RW uint32_t SEQ_HIGH_CFG; /* 0x850: */
27  __R uint8_t RESERVED3[940]; /* 0x854 - 0xBFF: Reserved */
28  struct {
29  __RW uint32_t PRD_CFG; /* 0xC00: */
30  __RW uint32_t PRD_THSHD_CFG; /* 0xC04: */
31  __R uint32_t PRD_RESULT; /* 0xC08: */
32  __R uint8_t RESERVED0[4]; /* 0xC0C - 0xC0F: Reserved */
33  } PRD_CFG[16];
34  __R uint8_t RESERVED4[768]; /* 0xD00 - 0xFFF: Reserved */
35  __RW uint32_t SAMPLE_CFG[16]; /* 0x1000 - 0x103C: */
36  __R uint8_t RESERVED5[196]; /* 0x1040 - 0x1103: Reserved */
37  __RW uint32_t CONV_CFG1; /* 0x1104: */
38  __RW uint32_t ADC_CFG0; /* 0x1108: */
39  __R uint8_t RESERVED6[4]; /* 0x110C - 0x110F: Reserved */
40  __RW uint32_t INT_STS; /* 0x1110: */
41  __RW uint32_t INT_EN; /* 0x1114: */
42  __R uint8_t RESERVED7[232]; /* 0x1118 - 0x11FF: Reserved */
43  __RW uint32_t ANA_CTRL0; /* 0x1200: */
44  __R uint8_t RESERVED8[12]; /* 0x1204 - 0x120F: Reserved */
45  __RW uint32_t ANA_STATUS; /* 0x1210: */
46  __R uint8_t RESERVED9[492]; /* 0x1214 - 0x13FF: Reserved */
47  __RW uint16_t ADC16_PARAMS[34]; /* 0x1400 - 0x1442: */
48  __RW uint32_t ADC16_CONFIG0; /* 0x1444: */
49  __R uint8_t RESERVED10[24]; /* 0x1448 - 0x145F: Reserved */
50  __RW uint32_t ADC16_CONFIG1; /* 0x1460: */
51 } ADC16_Type;
52 
53 
54 /* Bitfield definition for register array: CONFIG */
55 /*
56  * TRIG_LEN (WO)
57  *
58  * length for current trigger, can up to 4 conversions for one trigger, from 0 to 3
59  */
60 #define ADC16_CONFIG_TRIG_LEN_MASK (0xC0000000UL)
61 #define ADC16_CONFIG_TRIG_LEN_SHIFT (30U)
62 #define ADC16_CONFIG_TRIG_LEN_SET(x) (((uint32_t)(x) << ADC16_CONFIG_TRIG_LEN_SHIFT) & ADC16_CONFIG_TRIG_LEN_MASK)
63 #define ADC16_CONFIG_TRIG_LEN_GET(x) (((uint32_t)(x) & ADC16_CONFIG_TRIG_LEN_MASK) >> ADC16_CONFIG_TRIG_LEN_SHIFT)
64 
65 /*
66  * INTEN3 (RW)
67  *
68  * interrupt enable for 4th conversion
69  */
70 #define ADC16_CONFIG_INTEN3_MASK (0x20000000UL)
71 #define ADC16_CONFIG_INTEN3_SHIFT (29U)
72 #define ADC16_CONFIG_INTEN3_SET(x) (((uint32_t)(x) << ADC16_CONFIG_INTEN3_SHIFT) & ADC16_CONFIG_INTEN3_MASK)
73 #define ADC16_CONFIG_INTEN3_GET(x) (((uint32_t)(x) & ADC16_CONFIG_INTEN3_MASK) >> ADC16_CONFIG_INTEN3_SHIFT)
74 
75 /*
76  * CHAN3 (RW)
77  *
78  * channel number for 4th conversion
79  */
80 #define ADC16_CONFIG_CHAN3_MASK (0x1F000000UL)
81 #define ADC16_CONFIG_CHAN3_SHIFT (24U)
82 #define ADC16_CONFIG_CHAN3_SET(x) (((uint32_t)(x) << ADC16_CONFIG_CHAN3_SHIFT) & ADC16_CONFIG_CHAN3_MASK)
83 #define ADC16_CONFIG_CHAN3_GET(x) (((uint32_t)(x) & ADC16_CONFIG_CHAN3_MASK) >> ADC16_CONFIG_CHAN3_SHIFT)
84 
85 /*
86  * INTEN2 (RW)
87  *
88  * interrupt enable for 3rd conversion
89  */
90 #define ADC16_CONFIG_INTEN2_MASK (0x200000UL)
91 #define ADC16_CONFIG_INTEN2_SHIFT (21U)
92 #define ADC16_CONFIG_INTEN2_SET(x) (((uint32_t)(x) << ADC16_CONFIG_INTEN2_SHIFT) & ADC16_CONFIG_INTEN2_MASK)
93 #define ADC16_CONFIG_INTEN2_GET(x) (((uint32_t)(x) & ADC16_CONFIG_INTEN2_MASK) >> ADC16_CONFIG_INTEN2_SHIFT)
94 
95 /*
96  * CHAN2 (RW)
97  *
98  * channel number for 3rd conversion
99  */
100 #define ADC16_CONFIG_CHAN2_MASK (0x1F0000UL)
101 #define ADC16_CONFIG_CHAN2_SHIFT (16U)
102 #define ADC16_CONFIG_CHAN2_SET(x) (((uint32_t)(x) << ADC16_CONFIG_CHAN2_SHIFT) & ADC16_CONFIG_CHAN2_MASK)
103 #define ADC16_CONFIG_CHAN2_GET(x) (((uint32_t)(x) & ADC16_CONFIG_CHAN2_MASK) >> ADC16_CONFIG_CHAN2_SHIFT)
104 
105 /*
106  * INTEN1 (RW)
107  *
108  * interrupt enable for 2nd conversion
109  */
110 #define ADC16_CONFIG_INTEN1_MASK (0x2000U)
111 #define ADC16_CONFIG_INTEN1_SHIFT (13U)
112 #define ADC16_CONFIG_INTEN1_SET(x) (((uint32_t)(x) << ADC16_CONFIG_INTEN1_SHIFT) & ADC16_CONFIG_INTEN1_MASK)
113 #define ADC16_CONFIG_INTEN1_GET(x) (((uint32_t)(x) & ADC16_CONFIG_INTEN1_MASK) >> ADC16_CONFIG_INTEN1_SHIFT)
114 
115 /*
116  * CHAN1 (RW)
117  *
118  * channel number for 2nd conversion
119  */
120 #define ADC16_CONFIG_CHAN1_MASK (0x1F00U)
121 #define ADC16_CONFIG_CHAN1_SHIFT (8U)
122 #define ADC16_CONFIG_CHAN1_SET(x) (((uint32_t)(x) << ADC16_CONFIG_CHAN1_SHIFT) & ADC16_CONFIG_CHAN1_MASK)
123 #define ADC16_CONFIG_CHAN1_GET(x) (((uint32_t)(x) & ADC16_CONFIG_CHAN1_MASK) >> ADC16_CONFIG_CHAN1_SHIFT)
124 
125 /*
126  * QUEUE_EN (RW)
127  *
128  * preemption queue enable control
129  */
130 #define ADC16_CONFIG_QUEUE_EN_MASK (0x40U)
131 #define ADC16_CONFIG_QUEUE_EN_SHIFT (6U)
132 #define ADC16_CONFIG_QUEUE_EN_SET(x) (((uint32_t)(x) << ADC16_CONFIG_QUEUE_EN_SHIFT) & ADC16_CONFIG_QUEUE_EN_MASK)
133 #define ADC16_CONFIG_QUEUE_EN_GET(x) (((uint32_t)(x) & ADC16_CONFIG_QUEUE_EN_MASK) >> ADC16_CONFIG_QUEUE_EN_SHIFT)
134 
135 /*
136  * INTEN0 (RW)
137  *
138  * interrupt enable for 1st conversion
139  */
140 #define ADC16_CONFIG_INTEN0_MASK (0x20U)
141 #define ADC16_CONFIG_INTEN0_SHIFT (5U)
142 #define ADC16_CONFIG_INTEN0_SET(x) (((uint32_t)(x) << ADC16_CONFIG_INTEN0_SHIFT) & ADC16_CONFIG_INTEN0_MASK)
143 #define ADC16_CONFIG_INTEN0_GET(x) (((uint32_t)(x) & ADC16_CONFIG_INTEN0_MASK) >> ADC16_CONFIG_INTEN0_SHIFT)
144 
145 /*
146  * CHAN0 (RW)
147  *
148  * channel number for 1st conversion
149  */
150 #define ADC16_CONFIG_CHAN0_MASK (0x1FU)
151 #define ADC16_CONFIG_CHAN0_SHIFT (0U)
152 #define ADC16_CONFIG_CHAN0_SET(x) (((uint32_t)(x) << ADC16_CONFIG_CHAN0_SHIFT) & ADC16_CONFIG_CHAN0_MASK)
153 #define ADC16_CONFIG_CHAN0_GET(x) (((uint32_t)(x) & ADC16_CONFIG_CHAN0_MASK) >> ADC16_CONFIG_CHAN0_SHIFT)
154 
155 /* Bitfield definition for register: TRG_DMA_ADDR */
156 /*
157  * TRG_DMA_ADDR (RW)
158  *
159  * buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion)
160  */
161 #define ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK (0xFFFFFFFCUL)
162 #define ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT (2U)
163 #define ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_SET(x) (((uint32_t)(x) << ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT) & ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK)
164 #define ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_GET(x) (((uint32_t)(x) & ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK) >> ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT)
165 
166 /* Bitfield definition for register: TRG_SW_STA */
167 /*
168  * TRG_SW_STA (RW)
169  *
170  * SW trigger start bit, HW will clear it after all conversions(up to 4) finished. SW should make sure it's 0 before set it.
171  */
172 #define ADC16_TRG_SW_STA_TRG_SW_STA_MASK (0x10U)
173 #define ADC16_TRG_SW_STA_TRG_SW_STA_SHIFT (4U)
174 #define ADC16_TRG_SW_STA_TRG_SW_STA_SET(x) (((uint32_t)(x) << ADC16_TRG_SW_STA_TRG_SW_STA_SHIFT) & ADC16_TRG_SW_STA_TRG_SW_STA_MASK)
175 #define ADC16_TRG_SW_STA_TRG_SW_STA_GET(x) (((uint32_t)(x) & ADC16_TRG_SW_STA_TRG_SW_STA_MASK) >> ADC16_TRG_SW_STA_TRG_SW_STA_SHIFT)
176 
177 /*
178  * TRIG_SW_INDEX (RW)
179  *
180  * which trigger for the SW trigger
181  * 0 for trig0a, 1 for trig0b…
182  * 3 for trig1a, …11 for trig3c
183  */
184 #define ADC16_TRG_SW_STA_TRIG_SW_INDEX_MASK (0xFU)
185 #define ADC16_TRG_SW_STA_TRIG_SW_INDEX_SHIFT (0U)
186 #define ADC16_TRG_SW_STA_TRIG_SW_INDEX_SET(x) (((uint32_t)(x) << ADC16_TRG_SW_STA_TRIG_SW_INDEX_SHIFT) & ADC16_TRG_SW_STA_TRIG_SW_INDEX_MASK)
187 #define ADC16_TRG_SW_STA_TRIG_SW_INDEX_GET(x) (((uint32_t)(x) & ADC16_TRG_SW_STA_TRIG_SW_INDEX_MASK) >> ADC16_TRG_SW_STA_TRIG_SW_INDEX_SHIFT)
188 
189 /* Bitfield definition for register array: BUS_RESULT */
190 /*
191  * VALID (RO)
192  *
193  * set after conversion finished if wait_dis is set, cleared after software read.
194  * The first time read with 0 will trigger one new conversion.
195  * If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set.
196  * the result may not realtime if software read once and wait long time to read again
197  */
198 #define ADC16_BUS_RESULT_VALID_MASK (0x10000UL)
199 #define ADC16_BUS_RESULT_VALID_SHIFT (16U)
200 #define ADC16_BUS_RESULT_VALID_GET(x) (((uint32_t)(x) & ADC16_BUS_RESULT_VALID_MASK) >> ADC16_BUS_RESULT_VALID_SHIFT)
201 
202 /*
203  * CHAN_RESULT (RO)
204  *
205  * read this register will trigger one adc conversion.
206  * If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result
207  * If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long
208  */
209 #define ADC16_BUS_RESULT_CHAN_RESULT_MASK (0xFFFFU)
210 #define ADC16_BUS_RESULT_CHAN_RESULT_SHIFT (0U)
211 #define ADC16_BUS_RESULT_CHAN_RESULT_GET(x) (((uint32_t)(x) & ADC16_BUS_RESULT_CHAN_RESULT_MASK) >> ADC16_BUS_RESULT_CHAN_RESULT_SHIFT)
212 
213 /* Bitfield definition for register: BUF_CFG0 */
214 /*
215  * BUS_MODE_EN (RW)
216  *
217  * bus mode enable
218  */
219 #define ADC16_BUF_CFG0_BUS_MODE_EN_MASK (0x2U)
220 #define ADC16_BUF_CFG0_BUS_MODE_EN_SHIFT (1U)
221 #define ADC16_BUF_CFG0_BUS_MODE_EN_SET(x) (((uint32_t)(x) << ADC16_BUF_CFG0_BUS_MODE_EN_SHIFT) & ADC16_BUF_CFG0_BUS_MODE_EN_MASK)
222 #define ADC16_BUF_CFG0_BUS_MODE_EN_GET(x) (((uint32_t)(x) & ADC16_BUF_CFG0_BUS_MODE_EN_MASK) >> ADC16_BUF_CFG0_BUS_MODE_EN_SHIFT)
223 
224 /*
225  * WAIT_DIS (RW)
226  *
227  * set to disable read waiting, get result immediately but maybe not current conversion result.
228  */
229 #define ADC16_BUF_CFG0_WAIT_DIS_MASK (0x1U)
230 #define ADC16_BUF_CFG0_WAIT_DIS_SHIFT (0U)
231 #define ADC16_BUF_CFG0_WAIT_DIS_SET(x) (((uint32_t)(x) << ADC16_BUF_CFG0_WAIT_DIS_SHIFT) & ADC16_BUF_CFG0_WAIT_DIS_MASK)
232 #define ADC16_BUF_CFG0_WAIT_DIS_GET(x) (((uint32_t)(x) & ADC16_BUF_CFG0_WAIT_DIS_MASK) >> ADC16_BUF_CFG0_WAIT_DIS_SHIFT)
233 
234 /* Bitfield definition for register: SEQ_CFG0 */
235 /*
236  * CYCLE (RO)
237  *
238  * current dma write cycle bit
239  */
240 #define ADC16_SEQ_CFG0_CYCLE_MASK (0x80000000UL)
241 #define ADC16_SEQ_CFG0_CYCLE_SHIFT (31U)
242 #define ADC16_SEQ_CFG0_CYCLE_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_CYCLE_MASK) >> ADC16_SEQ_CFG0_CYCLE_SHIFT)
243 
244 /*
245  * SEQ_LEN (RW)
246  *
247  * sequence queue length, 0 for one, 0xF for 16
248  */
249 #define ADC16_SEQ_CFG0_SEQ_LEN_MASK (0xF00U)
250 #define ADC16_SEQ_CFG0_SEQ_LEN_SHIFT (8U)
251 #define ADC16_SEQ_CFG0_SEQ_LEN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_SEQ_LEN_SHIFT) & ADC16_SEQ_CFG0_SEQ_LEN_MASK)
252 #define ADC16_SEQ_CFG0_SEQ_LEN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_SEQ_LEN_MASK) >> ADC16_SEQ_CFG0_SEQ_LEN_SHIFT)
253 
254 /*
255  * RESTART_EN (RW)
256  *
257  * if set together with cont_en, HW will continue process the whole queue after trigger once.
258  * If cont_en is 0, this bit is not used
259  */
260 #define ADC16_SEQ_CFG0_RESTART_EN_MASK (0x10U)
261 #define ADC16_SEQ_CFG0_RESTART_EN_SHIFT (4U)
262 #define ADC16_SEQ_CFG0_RESTART_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_RESTART_EN_SHIFT) & ADC16_SEQ_CFG0_RESTART_EN_MASK)
263 #define ADC16_SEQ_CFG0_RESTART_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_RESTART_EN_MASK) >> ADC16_SEQ_CFG0_RESTART_EN_SHIFT)
264 
265 /*
266  * CONT_EN (RW)
267  *
268  * if set, HW will continue process the queue till end(seq_len) after trigger once
269  */
270 #define ADC16_SEQ_CFG0_CONT_EN_MASK (0x8U)
271 #define ADC16_SEQ_CFG0_CONT_EN_SHIFT (3U)
272 #define ADC16_SEQ_CFG0_CONT_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_CONT_EN_SHIFT) & ADC16_SEQ_CFG0_CONT_EN_MASK)
273 #define ADC16_SEQ_CFG0_CONT_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_CONT_EN_MASK) >> ADC16_SEQ_CFG0_CONT_EN_SHIFT)
274 
275 /*
276  * SW_TRIG (WO)
277  *
278  * SW trigger, pulse signal, cleared by HW one cycle later
279  */
280 #define ADC16_SEQ_CFG0_SW_TRIG_MASK (0x4U)
281 #define ADC16_SEQ_CFG0_SW_TRIG_SHIFT (2U)
282 #define ADC16_SEQ_CFG0_SW_TRIG_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_SW_TRIG_SHIFT) & ADC16_SEQ_CFG0_SW_TRIG_MASK)
283 #define ADC16_SEQ_CFG0_SW_TRIG_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_SW_TRIG_MASK) >> ADC16_SEQ_CFG0_SW_TRIG_SHIFT)
284 
285 /*
286  * SW_TRIG_EN (RW)
287  *
288  * set to enable SW trigger
289  */
290 #define ADC16_SEQ_CFG0_SW_TRIG_EN_MASK (0x2U)
291 #define ADC16_SEQ_CFG0_SW_TRIG_EN_SHIFT (1U)
292 #define ADC16_SEQ_CFG0_SW_TRIG_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_SW_TRIG_EN_SHIFT) & ADC16_SEQ_CFG0_SW_TRIG_EN_MASK)
293 #define ADC16_SEQ_CFG0_SW_TRIG_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_SW_TRIG_EN_MASK) >> ADC16_SEQ_CFG0_SW_TRIG_EN_SHIFT)
294 
295 /*
296  * HW_TRIG_EN (RW)
297  *
298  * set to enable external HW trigger, only trigger on posedge
299  */
300 #define ADC16_SEQ_CFG0_HW_TRIG_EN_MASK (0x1U)
301 #define ADC16_SEQ_CFG0_HW_TRIG_EN_SHIFT (0U)
302 #define ADC16_SEQ_CFG0_HW_TRIG_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_HW_TRIG_EN_SHIFT) & ADC16_SEQ_CFG0_HW_TRIG_EN_MASK)
303 #define ADC16_SEQ_CFG0_HW_TRIG_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_HW_TRIG_EN_MASK) >> ADC16_SEQ_CFG0_HW_TRIG_EN_SHIFT)
304 
305 /* Bitfield definition for register: SEQ_DMA_ADDR */
306 /*
307  * TAR_ADDR (RW)
308  *
309  * dma target address, should be 4-byte aligned
310  */
311 #define ADC16_SEQ_DMA_ADDR_TAR_ADDR_MASK (0xFFFFFFFCUL)
312 #define ADC16_SEQ_DMA_ADDR_TAR_ADDR_SHIFT (2U)
313 #define ADC16_SEQ_DMA_ADDR_TAR_ADDR_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_ADDR_TAR_ADDR_SHIFT) & ADC16_SEQ_DMA_ADDR_TAR_ADDR_MASK)
314 #define ADC16_SEQ_DMA_ADDR_TAR_ADDR_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_ADDR_TAR_ADDR_MASK) >> ADC16_SEQ_DMA_ADDR_TAR_ADDR_SHIFT)
315 
316 /* Bitfield definition for register: SEQ_WR_ADDR */
317 /*
318  * SEQ_WR_POINTER (RO)
319  *
320  * HW update this field after each dma write, it indicate the next dma write pointer.
321  * dma write address is (tar_addr+seq_wr_pointer)*4
322  */
323 #define ADC16_SEQ_WR_ADDR_SEQ_WR_POINTER_MASK (0xFFFFFFUL)
324 #define ADC16_SEQ_WR_ADDR_SEQ_WR_POINTER_SHIFT (0U)
325 #define ADC16_SEQ_WR_ADDR_SEQ_WR_POINTER_GET(x) (((uint32_t)(x) & ADC16_SEQ_WR_ADDR_SEQ_WR_POINTER_MASK) >> ADC16_SEQ_WR_ADDR_SEQ_WR_POINTER_SHIFT)
326 
327 /* Bitfield definition for register: SEQ_DMA_CFG */
328 /*
329  * STOP_POS (RW)
330  *
331  * if stop_en is set, SW is responsible to update this field to the next read point, HW should not write data to this point since it's not read out by SW yet
332  */
333 #define ADC16_SEQ_DMA_CFG_STOP_POS_MASK (0xFFF0000UL)
334 #define ADC16_SEQ_DMA_CFG_STOP_POS_SHIFT (16U)
335 #define ADC16_SEQ_DMA_CFG_STOP_POS_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_CFG_STOP_POS_SHIFT) & ADC16_SEQ_DMA_CFG_STOP_POS_MASK)
336 #define ADC16_SEQ_DMA_CFG_STOP_POS_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_CFG_STOP_POS_MASK) >> ADC16_SEQ_DMA_CFG_STOP_POS_SHIFT)
337 
338 /*
339  * DMA_RST (RW)
340  *
341  * set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set.
342  * SW should clear all cycle bit in buffer to 0 before clear dma_rst
343  */
344 #define ADC16_SEQ_DMA_CFG_DMA_RST_MASK (0x2000U)
345 #define ADC16_SEQ_DMA_CFG_DMA_RST_SHIFT (13U)
346 #define ADC16_SEQ_DMA_CFG_DMA_RST_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_CFG_DMA_RST_SHIFT) & ADC16_SEQ_DMA_CFG_DMA_RST_MASK)
347 #define ADC16_SEQ_DMA_CFG_DMA_RST_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_CFG_DMA_RST_MASK) >> ADC16_SEQ_DMA_CFG_DMA_RST_SHIFT)
348 
349 /*
350  * STOP_EN (RW)
351  *
352  * set to stop dma if reach the stop_pos
353  */
354 #define ADC16_SEQ_DMA_CFG_STOP_EN_MASK (0x1000U)
355 #define ADC16_SEQ_DMA_CFG_STOP_EN_SHIFT (12U)
356 #define ADC16_SEQ_DMA_CFG_STOP_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_CFG_STOP_EN_SHIFT) & ADC16_SEQ_DMA_CFG_STOP_EN_MASK)
357 #define ADC16_SEQ_DMA_CFG_STOP_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_CFG_STOP_EN_MASK) >> ADC16_SEQ_DMA_CFG_STOP_EN_SHIFT)
358 
359 /*
360  * BUF_LEN (RW)
361  *
362  * dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4
363  * 0 for 4byte;
364  * 0xFFF for 16kbyte.
365  */
366 #define ADC16_SEQ_DMA_CFG_BUF_LEN_MASK (0xFFFU)
367 #define ADC16_SEQ_DMA_CFG_BUF_LEN_SHIFT (0U)
368 #define ADC16_SEQ_DMA_CFG_BUF_LEN_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_CFG_BUF_LEN_SHIFT) & ADC16_SEQ_DMA_CFG_BUF_LEN_MASK)
369 #define ADC16_SEQ_DMA_CFG_BUF_LEN_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_CFG_BUF_LEN_MASK) >> ADC16_SEQ_DMA_CFG_BUF_LEN_SHIFT)
370 
371 /* Bitfield definition for register array: SEQ_QUE */
372 /*
373  * SEQ_INT_EN (RW)
374  *
375  * interrupt enable for current conversion
376  */
377 #define ADC16_SEQ_QUE_SEQ_INT_EN_MASK (0x20U)
378 #define ADC16_SEQ_QUE_SEQ_INT_EN_SHIFT (5U)
379 #define ADC16_SEQ_QUE_SEQ_INT_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_QUE_SEQ_INT_EN_SHIFT) & ADC16_SEQ_QUE_SEQ_INT_EN_MASK)
380 #define ADC16_SEQ_QUE_SEQ_INT_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_QUE_SEQ_INT_EN_MASK) >> ADC16_SEQ_QUE_SEQ_INT_EN_SHIFT)
381 
382 /*
383  * CHAN_NUM_4_0 (RW)
384  *
385  * channel number for current conversion
386  */
387 #define ADC16_SEQ_QUE_CHAN_NUM_4_0_MASK (0x1FU)
388 #define ADC16_SEQ_QUE_CHAN_NUM_4_0_SHIFT (0U)
389 #define ADC16_SEQ_QUE_CHAN_NUM_4_0_SET(x) (((uint32_t)(x) << ADC16_SEQ_QUE_CHAN_NUM_4_0_SHIFT) & ADC16_SEQ_QUE_CHAN_NUM_4_0_MASK)
390 #define ADC16_SEQ_QUE_CHAN_NUM_4_0_GET(x) (((uint32_t)(x) & ADC16_SEQ_QUE_CHAN_NUM_4_0_MASK) >> ADC16_SEQ_QUE_CHAN_NUM_4_0_SHIFT)
391 
392 /* Bitfield definition for register: SEQ_HIGH_CFG */
393 /*
394  * STOP_POS_HIGH (RW)
395  *
396  */
397 #define ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_MASK (0xFFF000UL)
398 #define ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_SHIFT (12U)
399 #define ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_SET(x) (((uint32_t)(x) << ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_SHIFT) & ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_MASK)
400 #define ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_GET(x) (((uint32_t)(x) & ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_MASK) >> ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_SHIFT)
401 
402 /*
403  * BUF_LEN_HIGH (RW)
404  *
405  */
406 #define ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_MASK (0xFFFU)
407 #define ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_SHIFT (0U)
408 #define ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_SET(x) (((uint32_t)(x) << ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_SHIFT) & ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_MASK)
409 #define ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_GET(x) (((uint32_t)(x) & ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_MASK) >> ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_SHIFT)
410 
411 /* Bitfield definition for register of struct array PRD_CFG: PRD_CFG */
412 /*
413  * PRESCALE (RW)
414  *
415  * 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx
416  */
417 #define ADC16_PRD_CFG_PRD_CFG_PRESCALE_MASK (0x1F00U)
418 #define ADC16_PRD_CFG_PRD_CFG_PRESCALE_SHIFT (8U)
419 #define ADC16_PRD_CFG_PRD_CFG_PRESCALE_SET(x) (((uint32_t)(x) << ADC16_PRD_CFG_PRD_CFG_PRESCALE_SHIFT) & ADC16_PRD_CFG_PRD_CFG_PRESCALE_MASK)
420 #define ADC16_PRD_CFG_PRD_CFG_PRESCALE_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_CFG_PRESCALE_MASK) >> ADC16_PRD_CFG_PRD_CFG_PRESCALE_SHIFT)
421 
422 /*
423  * PRD (RW)
424  *
425  * conver period, with prescale.
426  * Set to 0 means disable current channel
427  */
428 #define ADC16_PRD_CFG_PRD_CFG_PRD_MASK (0xFFU)
429 #define ADC16_PRD_CFG_PRD_CFG_PRD_SHIFT (0U)
430 #define ADC16_PRD_CFG_PRD_CFG_PRD_SET(x) (((uint32_t)(x) << ADC16_PRD_CFG_PRD_CFG_PRD_SHIFT) & ADC16_PRD_CFG_PRD_CFG_PRD_MASK)
431 #define ADC16_PRD_CFG_PRD_CFG_PRD_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_CFG_PRD_MASK) >> ADC16_PRD_CFG_PRD_CFG_PRD_SHIFT)
432 
433 /* Bitfield definition for register of struct array PRD_CFG: PRD_THSHD_CFG */
434 /*
435  * THSHDH (RW)
436  *
437  * threshold high, assert interrupt(if enabled) if result exceed high or low.
438  */
439 #define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK (0xFFFF0000UL)
440 #define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT (16U)
441 #define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_SET(x) (((uint32_t)(x) << ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT) & ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK)
442 #define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK) >> ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT)
443 
444 /*
445  * THSHDL (RW)
446  *
447  * threshold low
448  */
449 #define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK (0xFFFFU)
450 #define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT (0U)
451 #define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_SET(x) (((uint32_t)(x) << ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT) & ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK)
452 #define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK) >> ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT)
453 
454 /* Bitfield definition for register of struct array PRD_CFG: PRD_RESULT */
455 /*
456  * CHAN_RESULT (RO)
457  *
458  * adc convert result, update after each valid conversion.
459  * it may be updated period according to config, also may be updated due to other queue convert the same channel
460  */
461 #define ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_MASK (0xFFFFU)
462 #define ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_SHIFT (0U)
463 #define ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_MASK) >> ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_SHIFT)
464 
465 /* Bitfield definition for register array: SAMPLE_CFG */
466 /*
467  * SAMPLE_CLOCK_NUMBER_SHIFT (RW)
468  *
469  * shift for sample clock number
470  */
471 #define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_MASK (0xE00U)
472 #define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SHIFT (9U)
473 #define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SET(x) (((uint32_t)(x) << ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SHIFT) & ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_MASK)
474 #define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_GET(x) (((uint32_t)(x) & ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_MASK) >> ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SHIFT)
475 
476 /*
477  * SAMPLE_CLOCK_NUMBER (RW)
478  *
479  * sample clock number, base on clock_period, default one period
480  */
481 #define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_MASK (0x1FFU)
482 #define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT (0U)
483 #define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SET(x) (((uint32_t)(x) << ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT) & ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_MASK)
484 #define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_GET(x) (((uint32_t)(x) & ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_MASK) >> ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT)
485 
486 /* Bitfield definition for register: CONV_CFG1 */
487 /*
488  * CONVERT_CLOCK_NUMBER (RW)
489  *
490  * convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 21 adc clock cycles(based on clock after divider);
491  * user can use small value to get faster conversion, but less accuracy, need to config cov_end_cnt at adc16_config1 also.
492  * Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divider to 3, then each ADC conversion(plus sample) need 25 cycles(50MHz).
493  */
494 #define ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_MASK (0x1F0U)
495 #define ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SHIFT (4U)
496 #define ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SET(x) (((uint32_t)(x) << ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SHIFT) & ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_MASK)
497 #define ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_GET(x) (((uint32_t)(x) & ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_MASK) >> ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SHIFT)
498 
499 /*
500  * CLOCK_DIVIDER (RW)
501  *
502  * clock_period, N half clock cycle per half adc cycle
503  * 0 for same adc_clk and bus_clk,
504  * 1 for 1:2,
505  * 2 for 1:3,
506  * ...
507  * 15 for 1:16
508  * Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk
509  */
510 #define ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK (0xFU)
511 #define ADC16_CONV_CFG1_CLOCK_DIVIDER_SHIFT (0U)
512 #define ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(x) (((uint32_t)(x) << ADC16_CONV_CFG1_CLOCK_DIVIDER_SHIFT) & ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK)
513 #define ADC16_CONV_CFG1_CLOCK_DIVIDER_GET(x) (((uint32_t)(x) & ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) >> ADC16_CONV_CFG1_CLOCK_DIVIDER_SHIFT)
514 
515 /* Bitfield definition for register: ADC_CFG0 */
516 /*
517  * SEL_SYNC_AHB (RW)
518  *
519  * set to 1 will enable sync AHB bus, to get better bus performance.
520  * Adc_clk must to be set to same as bus clock at this mode
521  */
522 #define ADC16_ADC_CFG0_SEL_SYNC_AHB_MASK (0x80000000UL)
523 #define ADC16_ADC_CFG0_SEL_SYNC_AHB_SHIFT (31U)
524 #define ADC16_ADC_CFG0_SEL_SYNC_AHB_SET(x) (((uint32_t)(x) << ADC16_ADC_CFG0_SEL_SYNC_AHB_SHIFT) & ADC16_ADC_CFG0_SEL_SYNC_AHB_MASK)
525 #define ADC16_ADC_CFG0_SEL_SYNC_AHB_GET(x) (((uint32_t)(x) & ADC16_ADC_CFG0_SEL_SYNC_AHB_MASK) >> ADC16_ADC_CFG0_SEL_SYNC_AHB_SHIFT)
526 
527 /*
528  * ADC_AHB_EN (RW)
529  *
530  * set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue;
531  */
532 #define ADC16_ADC_CFG0_ADC_AHB_EN_MASK (0x20000000UL)
533 #define ADC16_ADC_CFG0_ADC_AHB_EN_SHIFT (29U)
534 #define ADC16_ADC_CFG0_ADC_AHB_EN_SET(x) (((uint32_t)(x) << ADC16_ADC_CFG0_ADC_AHB_EN_SHIFT) & ADC16_ADC_CFG0_ADC_AHB_EN_MASK)
535 #define ADC16_ADC_CFG0_ADC_AHB_EN_GET(x) (((uint32_t)(x) & ADC16_ADC_CFG0_ADC_AHB_EN_MASK) >> ADC16_ADC_CFG0_ADC_AHB_EN_SHIFT)
536 
537 /*
538  * PORT3_REALTIME (RW)
539  *
540  * set to enable trg queue stop other queues
541  */
542 #define ADC16_ADC_CFG0_PORT3_REALTIME_MASK (0x1U)
543 #define ADC16_ADC_CFG0_PORT3_REALTIME_SHIFT (0U)
544 #define ADC16_ADC_CFG0_PORT3_REALTIME_SET(x) (((uint32_t)(x) << ADC16_ADC_CFG0_PORT3_REALTIME_SHIFT) & ADC16_ADC_CFG0_PORT3_REALTIME_MASK)
545 #define ADC16_ADC_CFG0_PORT3_REALTIME_GET(x) (((uint32_t)(x) & ADC16_ADC_CFG0_PORT3_REALTIME_MASK) >> ADC16_ADC_CFG0_PORT3_REALTIME_SHIFT)
546 
547 /* Bitfield definition for register: INT_STS */
548 /*
549  * TRIG_CMPT (RW1C)
550  *
551  * interrupt for one trigger conversion complete if enabled
552  */
553 #define ADC16_INT_STS_TRIG_CMPT_MASK (0x80000000UL)
554 #define ADC16_INT_STS_TRIG_CMPT_SHIFT (31U)
555 #define ADC16_INT_STS_TRIG_CMPT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_TRIG_CMPT_SHIFT) & ADC16_INT_STS_TRIG_CMPT_MASK)
556 #define ADC16_INT_STS_TRIG_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_TRIG_CMPT_MASK) >> ADC16_INT_STS_TRIG_CMPT_SHIFT)
557 
558 /*
559  * TRIG_SW_CFLCT (RW1C)
560  *
561  */
562 #define ADC16_INT_STS_TRIG_SW_CFLCT_MASK (0x40000000UL)
563 #define ADC16_INT_STS_TRIG_SW_CFLCT_SHIFT (30U)
564 #define ADC16_INT_STS_TRIG_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_TRIG_SW_CFLCT_SHIFT) & ADC16_INT_STS_TRIG_SW_CFLCT_MASK)
565 #define ADC16_INT_STS_TRIG_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_TRIG_SW_CFLCT_MASK) >> ADC16_INT_STS_TRIG_SW_CFLCT_SHIFT)
566 
567 /*
568  * TRIG_HW_CFLCT (RW1C)
569  *
570  */
571 #define ADC16_INT_STS_TRIG_HW_CFLCT_MASK (0x20000000UL)
572 #define ADC16_INT_STS_TRIG_HW_CFLCT_SHIFT (29U)
573 #define ADC16_INT_STS_TRIG_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_TRIG_HW_CFLCT_SHIFT) & ADC16_INT_STS_TRIG_HW_CFLCT_MASK)
574 #define ADC16_INT_STS_TRIG_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_TRIG_HW_CFLCT_MASK) >> ADC16_INT_STS_TRIG_HW_CFLCT_SHIFT)
575 
576 /*
577  * READ_CFLCT (RW1C)
578  *
579  * read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel
580  */
581 #define ADC16_INT_STS_READ_CFLCT_MASK (0x10000000UL)
582 #define ADC16_INT_STS_READ_CFLCT_SHIFT (28U)
583 #define ADC16_INT_STS_READ_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_READ_CFLCT_SHIFT) & ADC16_INT_STS_READ_CFLCT_MASK)
584 #define ADC16_INT_STS_READ_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_READ_CFLCT_MASK) >> ADC16_INT_STS_READ_CFLCT_SHIFT)
585 
586 /*
587  * SEQ_SW_CFLCT (RW1C)
588  *
589  * sequence queue conflict interrupt, set if HW or SW trigger received during conversion
590  */
591 #define ADC16_INT_STS_SEQ_SW_CFLCT_MASK (0x8000000UL)
592 #define ADC16_INT_STS_SEQ_SW_CFLCT_SHIFT (27U)
593 #define ADC16_INT_STS_SEQ_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_SW_CFLCT_SHIFT) & ADC16_INT_STS_SEQ_SW_CFLCT_MASK)
594 #define ADC16_INT_STS_SEQ_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_SW_CFLCT_MASK) >> ADC16_INT_STS_SEQ_SW_CFLCT_SHIFT)
595 
596 /*
597  * SEQ_HW_CFLCT (RW1C)
598  *
599  */
600 #define ADC16_INT_STS_SEQ_HW_CFLCT_MASK (0x4000000UL)
601 #define ADC16_INT_STS_SEQ_HW_CFLCT_SHIFT (26U)
602 #define ADC16_INT_STS_SEQ_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_HW_CFLCT_SHIFT) & ADC16_INT_STS_SEQ_HW_CFLCT_MASK)
603 #define ADC16_INT_STS_SEQ_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_HW_CFLCT_MASK) >> ADC16_INT_STS_SEQ_HW_CFLCT_SHIFT)
604 
605 /*
606  * SEQ_DMAABT (RW1C)
607  *
608  * dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set
609  */
610 #define ADC16_INT_STS_SEQ_DMAABT_MASK (0x2000000UL)
611 #define ADC16_INT_STS_SEQ_DMAABT_SHIFT (25U)
612 #define ADC16_INT_STS_SEQ_DMAABT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_DMAABT_SHIFT) & ADC16_INT_STS_SEQ_DMAABT_MASK)
613 #define ADC16_INT_STS_SEQ_DMAABT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_DMAABT_MASK) >> ADC16_INT_STS_SEQ_DMAABT_SHIFT)
614 
615 /*
616  * SEQ_CMPT (RW1C)
617  *
618  * the whole sequence complete interrupt
619  */
620 #define ADC16_INT_STS_SEQ_CMPT_MASK (0x1000000UL)
621 #define ADC16_INT_STS_SEQ_CMPT_SHIFT (24U)
622 #define ADC16_INT_STS_SEQ_CMPT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_CMPT_SHIFT) & ADC16_INT_STS_SEQ_CMPT_MASK)
623 #define ADC16_INT_STS_SEQ_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_CMPT_MASK) >> ADC16_INT_STS_SEQ_CMPT_SHIFT)
624 
625 /*
626  * SEQ_CVC (RW1C)
627  *
628  * one conversion complete in seq_queue if related seq_int_en is set
629  */
630 #define ADC16_INT_STS_SEQ_CVC_MASK (0x800000UL)
631 #define ADC16_INT_STS_SEQ_CVC_SHIFT (23U)
632 #define ADC16_INT_STS_SEQ_CVC_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_CVC_SHIFT) & ADC16_INT_STS_SEQ_CVC_MASK)
633 #define ADC16_INT_STS_SEQ_CVC_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_CVC_MASK) >> ADC16_INT_STS_SEQ_CVC_SHIFT)
634 
635 /*
636  * DMA_FIFO_FULL (RW1C)
637  *
638  * DMA fifo full interrupt, user need to check clock frequency if it's set.
639  */
640 #define ADC16_INT_STS_DMA_FIFO_FULL_MASK (0x400000UL)
641 #define ADC16_INT_STS_DMA_FIFO_FULL_SHIFT (22U)
642 #define ADC16_INT_STS_DMA_FIFO_FULL_SET(x) (((uint32_t)(x) << ADC16_INT_STS_DMA_FIFO_FULL_SHIFT) & ADC16_INT_STS_DMA_FIFO_FULL_MASK)
643 #define ADC16_INT_STS_DMA_FIFO_FULL_GET(x) (((uint32_t)(x) & ADC16_INT_STS_DMA_FIFO_FULL_MASK) >> ADC16_INT_STS_DMA_FIFO_FULL_SHIFT)
644 
645 /*
646  * AHB_ERR (RW1C)
647  *
648  * set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr
649  */
650 #define ADC16_INT_STS_AHB_ERR_MASK (0x200000UL)
651 #define ADC16_INT_STS_AHB_ERR_SHIFT (21U)
652 #define ADC16_INT_STS_AHB_ERR_SET(x) (((uint32_t)(x) << ADC16_INT_STS_AHB_ERR_SHIFT) & ADC16_INT_STS_AHB_ERR_MASK)
653 #define ADC16_INT_STS_AHB_ERR_GET(x) (((uint32_t)(x) & ADC16_INT_STS_AHB_ERR_MASK) >> ADC16_INT_STS_AHB_ERR_SHIFT)
654 
655 /*
656  * WDOG (RW1C)
657  *
658  * set if one chanel watch dog event triggered
659  */
660 #define ADC16_INT_STS_WDOG_MASK (0xFFFFU)
661 #define ADC16_INT_STS_WDOG_SHIFT (0U)
662 #define ADC16_INT_STS_WDOG_SET(x) (((uint32_t)(x) << ADC16_INT_STS_WDOG_SHIFT) & ADC16_INT_STS_WDOG_MASK)
663 #define ADC16_INT_STS_WDOG_GET(x) (((uint32_t)(x) & ADC16_INT_STS_WDOG_MASK) >> ADC16_INT_STS_WDOG_SHIFT)
664 
665 /* Bitfield definition for register: INT_EN */
666 /*
667  * TRIG_CMPT (RW)
668  *
669  * interrupt for one trigger conversion complete if enabled
670  */
671 #define ADC16_INT_EN_TRIG_CMPT_MASK (0x80000000UL)
672 #define ADC16_INT_EN_TRIG_CMPT_SHIFT (31U)
673 #define ADC16_INT_EN_TRIG_CMPT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_TRIG_CMPT_SHIFT) & ADC16_INT_EN_TRIG_CMPT_MASK)
674 #define ADC16_INT_EN_TRIG_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_TRIG_CMPT_MASK) >> ADC16_INT_EN_TRIG_CMPT_SHIFT)
675 
676 /*
677  * TRIG_SW_CFLCT (RW)
678  *
679  */
680 #define ADC16_INT_EN_TRIG_SW_CFLCT_MASK (0x40000000UL)
681 #define ADC16_INT_EN_TRIG_SW_CFLCT_SHIFT (30U)
682 #define ADC16_INT_EN_TRIG_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_TRIG_SW_CFLCT_SHIFT) & ADC16_INT_EN_TRIG_SW_CFLCT_MASK)
683 #define ADC16_INT_EN_TRIG_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_TRIG_SW_CFLCT_MASK) >> ADC16_INT_EN_TRIG_SW_CFLCT_SHIFT)
684 
685 /*
686  * TRIG_HW_CFLCT (RW)
687  *
688  */
689 #define ADC16_INT_EN_TRIG_HW_CFLCT_MASK (0x20000000UL)
690 #define ADC16_INT_EN_TRIG_HW_CFLCT_SHIFT (29U)
691 #define ADC16_INT_EN_TRIG_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_TRIG_HW_CFLCT_SHIFT) & ADC16_INT_EN_TRIG_HW_CFLCT_MASK)
692 #define ADC16_INT_EN_TRIG_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_TRIG_HW_CFLCT_MASK) >> ADC16_INT_EN_TRIG_HW_CFLCT_SHIFT)
693 
694 /*
695  * READ_CFLCT (RW)
696  *
697  * read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel
698  */
699 #define ADC16_INT_EN_READ_CFLCT_MASK (0x10000000UL)
700 #define ADC16_INT_EN_READ_CFLCT_SHIFT (28U)
701 #define ADC16_INT_EN_READ_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_READ_CFLCT_SHIFT) & ADC16_INT_EN_READ_CFLCT_MASK)
702 #define ADC16_INT_EN_READ_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_READ_CFLCT_MASK) >> ADC16_INT_EN_READ_CFLCT_SHIFT)
703 
704 /*
705  * SEQ_SW_CFLCT (RW)
706  *
707  * sequence queue conflict interrupt, set if HW or SW trigger received during conversion
708  */
709 #define ADC16_INT_EN_SEQ_SW_CFLCT_MASK (0x8000000UL)
710 #define ADC16_INT_EN_SEQ_SW_CFLCT_SHIFT (27U)
711 #define ADC16_INT_EN_SEQ_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_SW_CFLCT_SHIFT) & ADC16_INT_EN_SEQ_SW_CFLCT_MASK)
712 #define ADC16_INT_EN_SEQ_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_SW_CFLCT_MASK) >> ADC16_INT_EN_SEQ_SW_CFLCT_SHIFT)
713 
714 /*
715  * SEQ_HW_CFLCT (RW)
716  *
717  */
718 #define ADC16_INT_EN_SEQ_HW_CFLCT_MASK (0x4000000UL)
719 #define ADC16_INT_EN_SEQ_HW_CFLCT_SHIFT (26U)
720 #define ADC16_INT_EN_SEQ_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_HW_CFLCT_SHIFT) & ADC16_INT_EN_SEQ_HW_CFLCT_MASK)
721 #define ADC16_INT_EN_SEQ_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_HW_CFLCT_MASK) >> ADC16_INT_EN_SEQ_HW_CFLCT_SHIFT)
722 
723 /*
724  * SEQ_DMAABT (RW)
725  *
726  * dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set
727  */
728 #define ADC16_INT_EN_SEQ_DMAABT_MASK (0x2000000UL)
729 #define ADC16_INT_EN_SEQ_DMAABT_SHIFT (25U)
730 #define ADC16_INT_EN_SEQ_DMAABT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_DMAABT_SHIFT) & ADC16_INT_EN_SEQ_DMAABT_MASK)
731 #define ADC16_INT_EN_SEQ_DMAABT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_DMAABT_MASK) >> ADC16_INT_EN_SEQ_DMAABT_SHIFT)
732 
733 /*
734  * SEQ_CMPT (RW)
735  *
736  * the whole sequence complete interrupt
737  */
738 #define ADC16_INT_EN_SEQ_CMPT_MASK (0x1000000UL)
739 #define ADC16_INT_EN_SEQ_CMPT_SHIFT (24U)
740 #define ADC16_INT_EN_SEQ_CMPT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_CMPT_SHIFT) & ADC16_INT_EN_SEQ_CMPT_MASK)
741 #define ADC16_INT_EN_SEQ_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_CMPT_MASK) >> ADC16_INT_EN_SEQ_CMPT_SHIFT)
742 
743 /*
744  * SEQ_CVC (RW)
745  *
746  * one conversion complete in seq_queue if related seq_int_en is set
747  */
748 #define ADC16_INT_EN_SEQ_CVC_MASK (0x800000UL)
749 #define ADC16_INT_EN_SEQ_CVC_SHIFT (23U)
750 #define ADC16_INT_EN_SEQ_CVC_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_CVC_SHIFT) & ADC16_INT_EN_SEQ_CVC_MASK)
751 #define ADC16_INT_EN_SEQ_CVC_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_CVC_MASK) >> ADC16_INT_EN_SEQ_CVC_SHIFT)
752 
753 /*
754  * DMA_FIFO_FULL (RW)
755  *
756  * DMA fifo full interrupt, user need to check clock frequency if it's set.
757  */
758 #define ADC16_INT_EN_DMA_FIFO_FULL_MASK (0x400000UL)
759 #define ADC16_INT_EN_DMA_FIFO_FULL_SHIFT (22U)
760 #define ADC16_INT_EN_DMA_FIFO_FULL_SET(x) (((uint32_t)(x) << ADC16_INT_EN_DMA_FIFO_FULL_SHIFT) & ADC16_INT_EN_DMA_FIFO_FULL_MASK)
761 #define ADC16_INT_EN_DMA_FIFO_FULL_GET(x) (((uint32_t)(x) & ADC16_INT_EN_DMA_FIFO_FULL_MASK) >> ADC16_INT_EN_DMA_FIFO_FULL_SHIFT)
762 
763 /*
764  * AHB_ERR (RW)
765  *
766  * set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr
767  */
768 #define ADC16_INT_EN_AHB_ERR_MASK (0x200000UL)
769 #define ADC16_INT_EN_AHB_ERR_SHIFT (21U)
770 #define ADC16_INT_EN_AHB_ERR_SET(x) (((uint32_t)(x) << ADC16_INT_EN_AHB_ERR_SHIFT) & ADC16_INT_EN_AHB_ERR_MASK)
771 #define ADC16_INT_EN_AHB_ERR_GET(x) (((uint32_t)(x) & ADC16_INT_EN_AHB_ERR_MASK) >> ADC16_INT_EN_AHB_ERR_SHIFT)
772 
773 /*
774  * WDOG (RW)
775  *
776  * set if one chanel watch dog event triggered
777  */
778 #define ADC16_INT_EN_WDOG_MASK (0xFFFFU)
779 #define ADC16_INT_EN_WDOG_SHIFT (0U)
780 #define ADC16_INT_EN_WDOG_SET(x) (((uint32_t)(x) << ADC16_INT_EN_WDOG_SHIFT) & ADC16_INT_EN_WDOG_MASK)
781 #define ADC16_INT_EN_WDOG_GET(x) (((uint32_t)(x) & ADC16_INT_EN_WDOG_MASK) >> ADC16_INT_EN_WDOG_SHIFT)
782 
783 /* Bitfield definition for register: ANA_CTRL0 */
784 /*
785  * MOTO_EN (RW)
786  *
787  * "set to enable moto_soc and moto_valid.
788  * Should use AHB clock for adc, this bit can be used avoid async output"
789  */
790 #define ADC16_ANA_CTRL0_MOTO_EN_MASK (0x80000000UL)
791 #define ADC16_ANA_CTRL0_MOTO_EN_SHIFT (31U)
792 #define ADC16_ANA_CTRL0_MOTO_EN_SET(x) (((uint32_t)(x) << ADC16_ANA_CTRL0_MOTO_EN_SHIFT) & ADC16_ANA_CTRL0_MOTO_EN_MASK)
793 #define ADC16_ANA_CTRL0_MOTO_EN_GET(x) (((uint32_t)(x) & ADC16_ANA_CTRL0_MOTO_EN_MASK) >> ADC16_ANA_CTRL0_MOTO_EN_SHIFT)
794 
795 /*
796  * ADC_CLK_ON (RW)
797  *
798  * set to enable adc clock to analog, Software should set this bit before access to any adc16_* register.
799  * MUST set clock_period to 0 or 1 for adc16 reg access
800  */
801 #define ADC16_ANA_CTRL0_ADC_CLK_ON_MASK (0x1000U)
802 #define ADC16_ANA_CTRL0_ADC_CLK_ON_SHIFT (12U)
803 #define ADC16_ANA_CTRL0_ADC_CLK_ON_SET(x) (((uint32_t)(x) << ADC16_ANA_CTRL0_ADC_CLK_ON_SHIFT) & ADC16_ANA_CTRL0_ADC_CLK_ON_MASK)
804 #define ADC16_ANA_CTRL0_ADC_CLK_ON_GET(x) (((uint32_t)(x) & ADC16_ANA_CTRL0_ADC_CLK_ON_MASK) >> ADC16_ANA_CTRL0_ADC_CLK_ON_SHIFT)
805 
806 /*
807  * STARTCAL (RW)
808  *
809  * set to start the offset calibration cycle (Active H). user need to clear it after setting it.
810  */
811 #define ADC16_ANA_CTRL0_STARTCAL_MASK (0x4U)
812 #define ADC16_ANA_CTRL0_STARTCAL_SHIFT (2U)
813 #define ADC16_ANA_CTRL0_STARTCAL_SET(x) (((uint32_t)(x) << ADC16_ANA_CTRL0_STARTCAL_SHIFT) & ADC16_ANA_CTRL0_STARTCAL_MASK)
814 #define ADC16_ANA_CTRL0_STARTCAL_GET(x) (((uint32_t)(x) & ADC16_ANA_CTRL0_STARTCAL_MASK) >> ADC16_ANA_CTRL0_STARTCAL_SHIFT)
815 
816 /* Bitfield definition for register: ANA_STATUS */
817 /*
818  * CALON (RW)
819  *
820  * Indicates if the ADC is in calibration mode (Active H).
821  */
822 #define ADC16_ANA_STATUS_CALON_MASK (0x80U)
823 #define ADC16_ANA_STATUS_CALON_SHIFT (7U)
824 #define ADC16_ANA_STATUS_CALON_SET(x) (((uint32_t)(x) << ADC16_ANA_STATUS_CALON_SHIFT) & ADC16_ANA_STATUS_CALON_MASK)
825 #define ADC16_ANA_STATUS_CALON_GET(x) (((uint32_t)(x) & ADC16_ANA_STATUS_CALON_MASK) >> ADC16_ANA_STATUS_CALON_SHIFT)
826 
827 /* Bitfield definition for register array: ADC16_PARAMS */
828 /*
829  * PARAM_VAL (RW)
830  *
831  */
832 #define ADC16_ADC16_PARAMS_PARAM_VAL_MASK (0xFFFFU)
833 #define ADC16_ADC16_PARAMS_PARAM_VAL_SHIFT (0U)
834 #define ADC16_ADC16_PARAMS_PARAM_VAL_SET(x) (((uint16_t)(x) << ADC16_ADC16_PARAMS_PARAM_VAL_SHIFT) & ADC16_ADC16_PARAMS_PARAM_VAL_MASK)
835 #define ADC16_ADC16_PARAMS_PARAM_VAL_GET(x) (((uint16_t)(x) & ADC16_ADC16_PARAMS_PARAM_VAL_MASK) >> ADC16_ADC16_PARAMS_PARAM_VAL_SHIFT)
836 
837 /* Bitfield definition for register: ADC16_CONFIG0 */
838 /*
839  * REG_EN (RW)
840  *
841  * set to enable regulator
842  */
843 #define ADC16_ADC16_CONFIG0_REG_EN_MASK (0x1000000UL)
844 #define ADC16_ADC16_CONFIG0_REG_EN_SHIFT (24U)
845 #define ADC16_ADC16_CONFIG0_REG_EN_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_REG_EN_SHIFT) & ADC16_ADC16_CONFIG0_REG_EN_MASK)
846 #define ADC16_ADC16_CONFIG0_REG_EN_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_REG_EN_MASK) >> ADC16_ADC16_CONFIG0_REG_EN_SHIFT)
847 
848 /*
849  * BANDGAP_EN (RW)
850  *
851  * set to enable bandgap. user should set reg_en and bandgap_en before use adc16.
852  */
853 #define ADC16_ADC16_CONFIG0_BANDGAP_EN_MASK (0x800000UL)
854 #define ADC16_ADC16_CONFIG0_BANDGAP_EN_SHIFT (23U)
855 #define ADC16_ADC16_CONFIG0_BANDGAP_EN_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_BANDGAP_EN_SHIFT) & ADC16_ADC16_CONFIG0_BANDGAP_EN_MASK)
856 #define ADC16_ADC16_CONFIG0_BANDGAP_EN_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_BANDGAP_EN_MASK) >> ADC16_ADC16_CONFIG0_BANDGAP_EN_SHIFT)
857 
858 /*
859  * CAL_AVG_CFG (RW)
860  *
861  * for average the calibration result.
862  * 0- 1 loop; 1- 2 loops; 2- 4 loops; 3- 8 loops;
863  * 4- 16 loops; 5-32 loops; others reserved
864  */
865 #define ADC16_ADC16_CONFIG0_CAL_AVG_CFG_MASK (0x700000UL)
866 #define ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SHIFT (20U)
867 #define ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SHIFT) & ADC16_ADC16_CONFIG0_CAL_AVG_CFG_MASK)
868 #define ADC16_ADC16_CONFIG0_CAL_AVG_CFG_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_CAL_AVG_CFG_MASK) >> ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SHIFT)
869 
870 /*
871  * PREEMPT_EN (RW)
872  *
873  * set to enable preemption feature
874  */
875 #define ADC16_ADC16_CONFIG0_PREEMPT_EN_MASK (0x4000U)
876 #define ADC16_ADC16_CONFIG0_PREEMPT_EN_SHIFT (14U)
877 #define ADC16_ADC16_CONFIG0_PREEMPT_EN_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_PREEMPT_EN_SHIFT) & ADC16_ADC16_CONFIG0_PREEMPT_EN_MASK)
878 #define ADC16_ADC16_CONFIG0_PREEMPT_EN_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_PREEMPT_EN_MASK) >> ADC16_ADC16_CONFIG0_PREEMPT_EN_SHIFT)
879 
880 /*
881  * CONV_PARAM (RW)
882  *
883  * conversion parameter
884  */
885 #define ADC16_ADC16_CONFIG0_CONV_PARAM_MASK (0x3FFFU)
886 #define ADC16_ADC16_CONFIG0_CONV_PARAM_SHIFT (0U)
887 #define ADC16_ADC16_CONFIG0_CONV_PARAM_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_CONV_PARAM_SHIFT) & ADC16_ADC16_CONFIG0_CONV_PARAM_MASK)
888 #define ADC16_ADC16_CONFIG0_CONV_PARAM_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_CONV_PARAM_MASK) >> ADC16_ADC16_CONFIG0_CONV_PARAM_SHIFT)
889 
890 /* Bitfield definition for register: ADC16_CONFIG1 */
891 /*
892  * COV_END_CNT (RW)
893  *
894  * used for faster conversion, user can change it to get higher convert speed(but less accuracy).
895  * should set to (21-convert_clock_number+1).
896  */
897 #define ADC16_ADC16_CONFIG1_COV_END_CNT_MASK (0x1F00U)
898 #define ADC16_ADC16_CONFIG1_COV_END_CNT_SHIFT (8U)
899 #define ADC16_ADC16_CONFIG1_COV_END_CNT_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG1_COV_END_CNT_SHIFT) & ADC16_ADC16_CONFIG1_COV_END_CNT_MASK)
900 #define ADC16_ADC16_CONFIG1_COV_END_CNT_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG1_COV_END_CNT_MASK) >> ADC16_ADC16_CONFIG1_COV_END_CNT_SHIFT)
901 
902 
903 
904 /* CONFIG register group index macro definition */
905 #define ADC16_CONFIG_TRG0A (0UL)
906 #define ADC16_CONFIG_TRG0B (1UL)
907 #define ADC16_CONFIG_TRG0C (2UL)
908 #define ADC16_CONFIG_TRG1A (3UL)
909 #define ADC16_CONFIG_TRG1B (4UL)
910 #define ADC16_CONFIG_TRG1C (5UL)
911 #define ADC16_CONFIG_TRG2A (6UL)
912 #define ADC16_CONFIG_TRG2B (7UL)
913 #define ADC16_CONFIG_TRG2C (8UL)
914 #define ADC16_CONFIG_TRG3A (9UL)
915 #define ADC16_CONFIG_TRG3B (10UL)
916 #define ADC16_CONFIG_TRG3C (11UL)
917 
918 /* BUS_RESULT register group index macro definition */
919 #define ADC16_BUS_RESULT_CHN0 (0UL)
920 #define ADC16_BUS_RESULT_CHN1 (1UL)
921 #define ADC16_BUS_RESULT_CHN2 (2UL)
922 #define ADC16_BUS_RESULT_CHN3 (3UL)
923 #define ADC16_BUS_RESULT_CHN4 (4UL)
924 #define ADC16_BUS_RESULT_CHN5 (5UL)
925 #define ADC16_BUS_RESULT_CHN6 (6UL)
926 #define ADC16_BUS_RESULT_CHN7 (7UL)
927 #define ADC16_BUS_RESULT_CHN8 (8UL)
928 #define ADC16_BUS_RESULT_CHN9 (9UL)
929 #define ADC16_BUS_RESULT_CHN10 (10UL)
930 #define ADC16_BUS_RESULT_CHN11 (11UL)
931 #define ADC16_BUS_RESULT_CHN12 (12UL)
932 #define ADC16_BUS_RESULT_CHN13 (13UL)
933 #define ADC16_BUS_RESULT_CHN14 (14UL)
934 #define ADC16_BUS_RESULT_CHN15 (15UL)
935 
936 /* SEQ_QUE register group index macro definition */
937 #define ADC16_SEQ_QUE_CFG0 (0UL)
938 #define ADC16_SEQ_QUE_CFG1 (1UL)
939 #define ADC16_SEQ_QUE_CFG2 (2UL)
940 #define ADC16_SEQ_QUE_CFG3 (3UL)
941 #define ADC16_SEQ_QUE_CFG4 (4UL)
942 #define ADC16_SEQ_QUE_CFG5 (5UL)
943 #define ADC16_SEQ_QUE_CFG6 (6UL)
944 #define ADC16_SEQ_QUE_CFG7 (7UL)
945 #define ADC16_SEQ_QUE_CFG8 (8UL)
946 #define ADC16_SEQ_QUE_CFG9 (9UL)
947 #define ADC16_SEQ_QUE_CFG10 (10UL)
948 #define ADC16_SEQ_QUE_CFG11 (11UL)
949 #define ADC16_SEQ_QUE_CFG12 (12UL)
950 #define ADC16_SEQ_QUE_CFG13 (13UL)
951 #define ADC16_SEQ_QUE_CFG14 (14UL)
952 #define ADC16_SEQ_QUE_CFG15 (15UL)
953 
954 /* PRD_CFG register group index macro definition */
955 #define ADC16_PRD_CFG_CHN0 (0UL)
956 #define ADC16_PRD_CFG_CHN1 (1UL)
957 #define ADC16_PRD_CFG_CHN2 (2UL)
958 #define ADC16_PRD_CFG_CHN3 (3UL)
959 #define ADC16_PRD_CFG_CHN4 (4UL)
960 #define ADC16_PRD_CFG_CHN5 (5UL)
961 #define ADC16_PRD_CFG_CHN6 (6UL)
962 #define ADC16_PRD_CFG_CHN7 (7UL)
963 #define ADC16_PRD_CFG_CHN8 (8UL)
964 #define ADC16_PRD_CFG_CHN9 (9UL)
965 #define ADC16_PRD_CFG_CHN10 (10UL)
966 #define ADC16_PRD_CFG_CHN11 (11UL)
967 #define ADC16_PRD_CFG_CHN12 (12UL)
968 #define ADC16_PRD_CFG_CHN13 (13UL)
969 #define ADC16_PRD_CFG_CHN14 (14UL)
970 #define ADC16_PRD_CFG_CHN15 (15UL)
971 
972 /* SAMPLE_CFG register group index macro definition */
973 #define ADC16_SAMPLE_CFG_CHN0 (0UL)
974 #define ADC16_SAMPLE_CFG_CHN1 (1UL)
975 #define ADC16_SAMPLE_CFG_CHN2 (2UL)
976 #define ADC16_SAMPLE_CFG_CHN3 (3UL)
977 #define ADC16_SAMPLE_CFG_CHN4 (4UL)
978 #define ADC16_SAMPLE_CFG_CHN5 (5UL)
979 #define ADC16_SAMPLE_CFG_CHN6 (6UL)
980 #define ADC16_SAMPLE_CFG_CHN7 (7UL)
981 #define ADC16_SAMPLE_CFG_CHN8 (8UL)
982 #define ADC16_SAMPLE_CFG_CHN9 (9UL)
983 #define ADC16_SAMPLE_CFG_CHN10 (10UL)
984 #define ADC16_SAMPLE_CFG_CHN11 (11UL)
985 #define ADC16_SAMPLE_CFG_CHN12 (12UL)
986 #define ADC16_SAMPLE_CFG_CHN13 (13UL)
987 #define ADC16_SAMPLE_CFG_CHN14 (14UL)
988 #define ADC16_SAMPLE_CFG_CHN15 (15UL)
989 
990 /* ADC16_PARAMS register group index macro definition */
991 #define ADC16_ADC16_PARAMS_ADC16_PARA00 (0UL)
992 #define ADC16_ADC16_PARAMS_ADC16_PARA01 (1UL)
993 #define ADC16_ADC16_PARAMS_ADC16_PARA02 (2UL)
994 #define ADC16_ADC16_PARAMS_ADC16_PARA03 (3UL)
995 #define ADC16_ADC16_PARAMS_ADC16_PARA04 (4UL)
996 #define ADC16_ADC16_PARAMS_ADC16_PARA05 (5UL)
997 #define ADC16_ADC16_PARAMS_ADC16_PARA06 (6UL)
998 #define ADC16_ADC16_PARAMS_ADC16_PARA07 (7UL)
999 #define ADC16_ADC16_PARAMS_ADC16_PARA08 (8UL)
1000 #define ADC16_ADC16_PARAMS_ADC16_PARA09 (9UL)
1001 #define ADC16_ADC16_PARAMS_ADC16_PARA10 (10UL)
1002 #define ADC16_ADC16_PARAMS_ADC16_PARA11 (11UL)
1003 #define ADC16_ADC16_PARAMS_ADC16_PARA12 (12UL)
1004 #define ADC16_ADC16_PARAMS_ADC16_PARA13 (13UL)
1005 #define ADC16_ADC16_PARAMS_ADC16_PARA14 (14UL)
1006 #define ADC16_ADC16_PARAMS_ADC16_PARA15 (15UL)
1007 #define ADC16_ADC16_PARAMS_ADC16_PARA16 (16UL)
1008 #define ADC16_ADC16_PARAMS_ADC16_PARA17 (17UL)
1009 #define ADC16_ADC16_PARAMS_ADC16_PARA18 (18UL)
1010 #define ADC16_ADC16_PARAMS_ADC16_PARA19 (19UL)
1011 #define ADC16_ADC16_PARAMS_ADC16_PARA20 (20UL)
1012 #define ADC16_ADC16_PARAMS_ADC16_PARA21 (21UL)
1013 #define ADC16_ADC16_PARAMS_ADC16_PARA22 (22UL)
1014 #define ADC16_ADC16_PARAMS_ADC16_PARA23 (23UL)
1015 #define ADC16_ADC16_PARAMS_ADC16_PARA24 (24UL)
1016 #define ADC16_ADC16_PARAMS_ADC16_PARA25 (25UL)
1017 #define ADC16_ADC16_PARAMS_ADC16_PARA26 (26UL)
1018 #define ADC16_ADC16_PARAMS_ADC16_PARA27 (27UL)
1019 #define ADC16_ADC16_PARAMS_ADC16_PARA28 (28UL)
1020 #define ADC16_ADC16_PARAMS_ADC16_PARA29 (29UL)
1021 #define ADC16_ADC16_PARAMS_ADC16_PARA30 (30UL)
1022 #define ADC16_ADC16_PARAMS_ADC16_PARA31 (31UL)
1023 #define ADC16_ADC16_PARAMS_ADC16_PARA32 (32UL)
1024 #define ADC16_ADC16_PARAMS_ADC16_PARA33 (33UL)
1025 
1026 
1027 #endif /* HPM_ADC16_H */
ADC16_Type
Definition: hpm_adc16_regs.h:12