HPM SDK
HPMicro Software Development Kit
hpm_adc16_regs.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_ADC16_H
10 #define HPM_ADC16_H
11 
12 typedef struct {
13  __RW uint32_t CONFIG[12]; /* 0x0 - 0x2C: */
14  __RW uint32_t TRG_DMA_ADDR; /* 0x30: */
15  __RW uint32_t TRG_SW_STA; /* 0x34: */
16  __R uint8_t RESERVED0[968]; /* 0x38 - 0x3FF: Reserved */
17  __R uint32_t BUS_RESULT[16]; /* 0x400 - 0x43C: */
18  __R uint8_t RESERVED1[192]; /* 0x440 - 0x4FF: Reserved */
19  __RW uint32_t BUF_CFG0; /* 0x500: */
20  __R uint8_t RESERVED2[764]; /* 0x504 - 0x7FF: Reserved */
21  __RW uint32_t SEQ_CFG0; /* 0x800: */
22  __RW uint32_t SEQ_DMA_ADDR; /* 0x804: */
23  __R uint8_t RESERVED3[4]; /* 0x808 - 0x80B: Reserved */
24  __RW uint32_t SEQ_DMA_CFG; /* 0x80C: */
25  __RW uint32_t SEQ_QUE[16]; /* 0x810 - 0x84C: */
26  __R uint8_t RESERVED4[944]; /* 0x850 - 0xBFF: Reserved */
27  struct {
28  __RW uint32_t PRD_CFG; /* 0xC00: */
29  __RW uint32_t PRD_THSHD_CFG; /* 0xC04: */
30  __R uint32_t PRD_RESULT; /* 0xC08: */
31  __R uint8_t RESERVED0[4]; /* 0xC0C - 0xC0F: Reserved */
32  } PRD_CFG[16];
33  __R uint8_t RESERVED5[768]; /* 0xD00 - 0xFFF: Reserved */
34  __RW uint32_t SAMPLE_CFG[16]; /* 0x1000 - 0x103C: */
35  __R uint8_t RESERVED6[196]; /* 0x1040 - 0x1103: Reserved */
36  __RW uint32_t CONV_CFG1; /* 0x1104: */
37  __RW uint32_t ADC_CFG0; /* 0x1108: */
38  __R uint8_t RESERVED7[4]; /* 0x110C - 0x110F: Reserved */
39  __RW uint32_t INT_STS; /* 0x1110: */
40  __RW uint32_t INT_EN; /* 0x1114: */
41  __R uint8_t RESERVED8[232]; /* 0x1118 - 0x11FF: Reserved */
42  __RW uint32_t ANA_CTRL0; /* 0x1200: */
43  __R uint8_t RESERVED9[12]; /* 0x1204 - 0x120F: Reserved */
44  __RW uint32_t ANA_STATUS; /* 0x1210: */
45  __R uint8_t RESERVED10[492]; /* 0x1214 - 0x13FF: Reserved */
46  __RW uint16_t ADC16_PARAMS[34]; /* 0x1400 - 0x1442: */
47  __RW uint32_t ADC16_CONFIG0; /* 0x1444: */
48  __R uint8_t RESERVED11[24]; /* 0x1448 - 0x145F: Reserved */
49  __RW uint32_t ADC16_CONFIG1; /* 0x1460: */
50 } ADC16_Type;
51 
52 
53 /* Bitfield definition for register array: CONFIG */
54 /*
55  * TRIG_LEN (WO)
56  *
57  * length for current trigger, can up to 4 conversions for one trigger, from 0 to 3
58  */
59 #define ADC16_CONFIG_TRIG_LEN_MASK (0xC0000000UL)
60 #define ADC16_CONFIG_TRIG_LEN_SHIFT (30U)
61 #define ADC16_CONFIG_TRIG_LEN_SET(x) (((uint32_t)(x) << ADC16_CONFIG_TRIG_LEN_SHIFT) & ADC16_CONFIG_TRIG_LEN_MASK)
62 #define ADC16_CONFIG_TRIG_LEN_GET(x) (((uint32_t)(x) & ADC16_CONFIG_TRIG_LEN_MASK) >> ADC16_CONFIG_TRIG_LEN_SHIFT)
63 
64 /*
65  * INTEN3 (RW)
66  *
67  * interrupt enable for 4th conversion
68  */
69 #define ADC16_CONFIG_INTEN3_MASK (0x20000000UL)
70 #define ADC16_CONFIG_INTEN3_SHIFT (29U)
71 #define ADC16_CONFIG_INTEN3_SET(x) (((uint32_t)(x) << ADC16_CONFIG_INTEN3_SHIFT) & ADC16_CONFIG_INTEN3_MASK)
72 #define ADC16_CONFIG_INTEN3_GET(x) (((uint32_t)(x) & ADC16_CONFIG_INTEN3_MASK) >> ADC16_CONFIG_INTEN3_SHIFT)
73 
74 /*
75  * CHAN3 (RW)
76  *
77  * channel number for 4th conversion
78  */
79 #define ADC16_CONFIG_CHAN3_MASK (0x1F000000UL)
80 #define ADC16_CONFIG_CHAN3_SHIFT (24U)
81 #define ADC16_CONFIG_CHAN3_SET(x) (((uint32_t)(x) << ADC16_CONFIG_CHAN3_SHIFT) & ADC16_CONFIG_CHAN3_MASK)
82 #define ADC16_CONFIG_CHAN3_GET(x) (((uint32_t)(x) & ADC16_CONFIG_CHAN3_MASK) >> ADC16_CONFIG_CHAN3_SHIFT)
83 
84 /*
85  * INTEN2 (RW)
86  *
87  * interrupt enable for 3rd conversion
88  */
89 #define ADC16_CONFIG_INTEN2_MASK (0x200000UL)
90 #define ADC16_CONFIG_INTEN2_SHIFT (21U)
91 #define ADC16_CONFIG_INTEN2_SET(x) (((uint32_t)(x) << ADC16_CONFIG_INTEN2_SHIFT) & ADC16_CONFIG_INTEN2_MASK)
92 #define ADC16_CONFIG_INTEN2_GET(x) (((uint32_t)(x) & ADC16_CONFIG_INTEN2_MASK) >> ADC16_CONFIG_INTEN2_SHIFT)
93 
94 /*
95  * CHAN2 (RW)
96  *
97  * channel number for 3rd conversion
98  */
99 #define ADC16_CONFIG_CHAN2_MASK (0x1F0000UL)
100 #define ADC16_CONFIG_CHAN2_SHIFT (16U)
101 #define ADC16_CONFIG_CHAN2_SET(x) (((uint32_t)(x) << ADC16_CONFIG_CHAN2_SHIFT) & ADC16_CONFIG_CHAN2_MASK)
102 #define ADC16_CONFIG_CHAN2_GET(x) (((uint32_t)(x) & ADC16_CONFIG_CHAN2_MASK) >> ADC16_CONFIG_CHAN2_SHIFT)
103 
104 /*
105  * INTEN1 (RW)
106  *
107  * interrupt enable for 2nd conversion
108  */
109 #define ADC16_CONFIG_INTEN1_MASK (0x2000U)
110 #define ADC16_CONFIG_INTEN1_SHIFT (13U)
111 #define ADC16_CONFIG_INTEN1_SET(x) (((uint32_t)(x) << ADC16_CONFIG_INTEN1_SHIFT) & ADC16_CONFIG_INTEN1_MASK)
112 #define ADC16_CONFIG_INTEN1_GET(x) (((uint32_t)(x) & ADC16_CONFIG_INTEN1_MASK) >> ADC16_CONFIG_INTEN1_SHIFT)
113 
114 /*
115  * CHAN1 (RW)
116  *
117  * channel number for 2nd conversion
118  */
119 #define ADC16_CONFIG_CHAN1_MASK (0x1F00U)
120 #define ADC16_CONFIG_CHAN1_SHIFT (8U)
121 #define ADC16_CONFIG_CHAN1_SET(x) (((uint32_t)(x) << ADC16_CONFIG_CHAN1_SHIFT) & ADC16_CONFIG_CHAN1_MASK)
122 #define ADC16_CONFIG_CHAN1_GET(x) (((uint32_t)(x) & ADC16_CONFIG_CHAN1_MASK) >> ADC16_CONFIG_CHAN1_SHIFT)
123 
124 /*
125  * QUEUE_EN (RW)
126  *
127  * preemption queue enable control
128  */
129 #define ADC16_CONFIG_QUEUE_EN_MASK (0x40U)
130 #define ADC16_CONFIG_QUEUE_EN_SHIFT (6U)
131 #define ADC16_CONFIG_QUEUE_EN_SET(x) (((uint32_t)(x) << ADC16_CONFIG_QUEUE_EN_SHIFT) & ADC16_CONFIG_QUEUE_EN_MASK)
132 #define ADC16_CONFIG_QUEUE_EN_GET(x) (((uint32_t)(x) & ADC16_CONFIG_QUEUE_EN_MASK) >> ADC16_CONFIG_QUEUE_EN_SHIFT)
133 
134 /*
135  * INTEN0 (RW)
136  *
137  * interrupt enable for 1st conversion
138  */
139 #define ADC16_CONFIG_INTEN0_MASK (0x20U)
140 #define ADC16_CONFIG_INTEN0_SHIFT (5U)
141 #define ADC16_CONFIG_INTEN0_SET(x) (((uint32_t)(x) << ADC16_CONFIG_INTEN0_SHIFT) & ADC16_CONFIG_INTEN0_MASK)
142 #define ADC16_CONFIG_INTEN0_GET(x) (((uint32_t)(x) & ADC16_CONFIG_INTEN0_MASK) >> ADC16_CONFIG_INTEN0_SHIFT)
143 
144 /*
145  * CHAN0 (RW)
146  *
147  * channel number for 1st conversion
148  */
149 #define ADC16_CONFIG_CHAN0_MASK (0x1FU)
150 #define ADC16_CONFIG_CHAN0_SHIFT (0U)
151 #define ADC16_CONFIG_CHAN0_SET(x) (((uint32_t)(x) << ADC16_CONFIG_CHAN0_SHIFT) & ADC16_CONFIG_CHAN0_MASK)
152 #define ADC16_CONFIG_CHAN0_GET(x) (((uint32_t)(x) & ADC16_CONFIG_CHAN0_MASK) >> ADC16_CONFIG_CHAN0_SHIFT)
153 
154 /* Bitfield definition for register: TRG_DMA_ADDR */
155 /*
156  * TRG_DMA_ADDR (RW)
157  *
158  * buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion)
159  */
160 #define ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK (0xFFFFFFFCUL)
161 #define ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT (2U)
162 #define ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_SET(x) (((uint32_t)(x) << ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT) & ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK)
163 #define ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_GET(x) (((uint32_t)(x) & ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK) >> ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT)
164 
165 /* Bitfield definition for register: TRG_SW_STA */
166 /*
167  * TRG_SW_STA (RW)
168  *
169  * SW trigger start bit, HW will clear it after all conversions(up to 4) finished. SW should make sure it's 0 before set it.
170  */
171 #define ADC16_TRG_SW_STA_TRG_SW_STA_MASK (0x10U)
172 #define ADC16_TRG_SW_STA_TRG_SW_STA_SHIFT (4U)
173 #define ADC16_TRG_SW_STA_TRG_SW_STA_SET(x) (((uint32_t)(x) << ADC16_TRG_SW_STA_TRG_SW_STA_SHIFT) & ADC16_TRG_SW_STA_TRG_SW_STA_MASK)
174 #define ADC16_TRG_SW_STA_TRG_SW_STA_GET(x) (((uint32_t)(x) & ADC16_TRG_SW_STA_TRG_SW_STA_MASK) >> ADC16_TRG_SW_STA_TRG_SW_STA_SHIFT)
175 
176 /*
177  * TRIG_SW_INDEX (RW)
178  *
179  * which trigger for the SW trigger
180  * 0 for trig0a, 1 for trig0b…
181  * 3 for trig1a, …11 for trig3c
182  */
183 #define ADC16_TRG_SW_STA_TRIG_SW_INDEX_MASK (0xFU)
184 #define ADC16_TRG_SW_STA_TRIG_SW_INDEX_SHIFT (0U)
185 #define ADC16_TRG_SW_STA_TRIG_SW_INDEX_SET(x) (((uint32_t)(x) << ADC16_TRG_SW_STA_TRIG_SW_INDEX_SHIFT) & ADC16_TRG_SW_STA_TRIG_SW_INDEX_MASK)
186 #define ADC16_TRG_SW_STA_TRIG_SW_INDEX_GET(x) (((uint32_t)(x) & ADC16_TRG_SW_STA_TRIG_SW_INDEX_MASK) >> ADC16_TRG_SW_STA_TRIG_SW_INDEX_SHIFT)
187 
188 /* Bitfield definition for register array: BUS_RESULT */
189 /*
190  * VALID (RO)
191  *
192  * set after conversion finished if wait_dis is set, cleared after software read.
193  * The first time read with 0 will trigger one new conversion.
194  * If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set.
195  * the result may not realtime if software read once and wait long time to read again
196  */
197 #define ADC16_BUS_RESULT_VALID_MASK (0x10000UL)
198 #define ADC16_BUS_RESULT_VALID_SHIFT (16U)
199 #define ADC16_BUS_RESULT_VALID_GET(x) (((uint32_t)(x) & ADC16_BUS_RESULT_VALID_MASK) >> ADC16_BUS_RESULT_VALID_SHIFT)
200 
201 /*
202  * CHAN_RESULT (RO)
203  *
204  * read this register will trigger one adc conversion.
205  * If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result
206  * If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long
207  */
208 #define ADC16_BUS_RESULT_CHAN_RESULT_MASK (0xFFFFU)
209 #define ADC16_BUS_RESULT_CHAN_RESULT_SHIFT (0U)
210 #define ADC16_BUS_RESULT_CHAN_RESULT_GET(x) (((uint32_t)(x) & ADC16_BUS_RESULT_CHAN_RESULT_MASK) >> ADC16_BUS_RESULT_CHAN_RESULT_SHIFT)
211 
212 /* Bitfield definition for register: BUF_CFG0 */
213 /*
214  * WAIT_DIS (RW)
215  *
216  * set to disable read waiting, get result immediately but maybe not current conversion result.
217  */
218 #define ADC16_BUF_CFG0_WAIT_DIS_MASK (0x1U)
219 #define ADC16_BUF_CFG0_WAIT_DIS_SHIFT (0U)
220 #define ADC16_BUF_CFG0_WAIT_DIS_SET(x) (((uint32_t)(x) << ADC16_BUF_CFG0_WAIT_DIS_SHIFT) & ADC16_BUF_CFG0_WAIT_DIS_MASK)
221 #define ADC16_BUF_CFG0_WAIT_DIS_GET(x) (((uint32_t)(x) & ADC16_BUF_CFG0_WAIT_DIS_MASK) >> ADC16_BUF_CFG0_WAIT_DIS_SHIFT)
222 
223 /* Bitfield definition for register: SEQ_CFG0 */
224 /*
225  * CYCLE (RO)
226  *
227  * current dma write cycle bit
228  */
229 #define ADC16_SEQ_CFG0_CYCLE_MASK (0x80000000UL)
230 #define ADC16_SEQ_CFG0_CYCLE_SHIFT (31U)
231 #define ADC16_SEQ_CFG0_CYCLE_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_CYCLE_MASK) >> ADC16_SEQ_CFG0_CYCLE_SHIFT)
232 
233 /*
234  * SEQ_LEN (RW)
235  *
236  * sequence queue length, 0 for one, 0xF for 16
237  */
238 #define ADC16_SEQ_CFG0_SEQ_LEN_MASK (0xF00U)
239 #define ADC16_SEQ_CFG0_SEQ_LEN_SHIFT (8U)
240 #define ADC16_SEQ_CFG0_SEQ_LEN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_SEQ_LEN_SHIFT) & ADC16_SEQ_CFG0_SEQ_LEN_MASK)
241 #define ADC16_SEQ_CFG0_SEQ_LEN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_SEQ_LEN_MASK) >> ADC16_SEQ_CFG0_SEQ_LEN_SHIFT)
242 
243 /*
244  * RESTART_EN (RW)
245  *
246  * if set together with cont_en, HW will continue process the whole queue after trigger once.
247  * If cont_en is 0, this bit is not used
248  */
249 #define ADC16_SEQ_CFG0_RESTART_EN_MASK (0x10U)
250 #define ADC16_SEQ_CFG0_RESTART_EN_SHIFT (4U)
251 #define ADC16_SEQ_CFG0_RESTART_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_RESTART_EN_SHIFT) & ADC16_SEQ_CFG0_RESTART_EN_MASK)
252 #define ADC16_SEQ_CFG0_RESTART_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_RESTART_EN_MASK) >> ADC16_SEQ_CFG0_RESTART_EN_SHIFT)
253 
254 /*
255  * CONT_EN (RW)
256  *
257  * if set, HW will continue process the queue till end(seq_len) after trigger once
258  */
259 #define ADC16_SEQ_CFG0_CONT_EN_MASK (0x8U)
260 #define ADC16_SEQ_CFG0_CONT_EN_SHIFT (3U)
261 #define ADC16_SEQ_CFG0_CONT_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_CONT_EN_SHIFT) & ADC16_SEQ_CFG0_CONT_EN_MASK)
262 #define ADC16_SEQ_CFG0_CONT_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_CONT_EN_MASK) >> ADC16_SEQ_CFG0_CONT_EN_SHIFT)
263 
264 /*
265  * SW_TRIG (WO)
266  *
267  * SW trigger, pulse signal, cleared by HW one cycle later
268  */
269 #define ADC16_SEQ_CFG0_SW_TRIG_MASK (0x4U)
270 #define ADC16_SEQ_CFG0_SW_TRIG_SHIFT (2U)
271 #define ADC16_SEQ_CFG0_SW_TRIG_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_SW_TRIG_SHIFT) & ADC16_SEQ_CFG0_SW_TRIG_MASK)
272 #define ADC16_SEQ_CFG0_SW_TRIG_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_SW_TRIG_MASK) >> ADC16_SEQ_CFG0_SW_TRIG_SHIFT)
273 
274 /*
275  * SW_TRIG_EN (RW)
276  *
277  * set to enable SW trigger
278  */
279 #define ADC16_SEQ_CFG0_SW_TRIG_EN_MASK (0x2U)
280 #define ADC16_SEQ_CFG0_SW_TRIG_EN_SHIFT (1U)
281 #define ADC16_SEQ_CFG0_SW_TRIG_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_SW_TRIG_EN_SHIFT) & ADC16_SEQ_CFG0_SW_TRIG_EN_MASK)
282 #define ADC16_SEQ_CFG0_SW_TRIG_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_SW_TRIG_EN_MASK) >> ADC16_SEQ_CFG0_SW_TRIG_EN_SHIFT)
283 
284 /*
285  * HW_TRIG_EN (RW)
286  *
287  * set to enable external HW trigger, only trigger on posedge
288  */
289 #define ADC16_SEQ_CFG0_HW_TRIG_EN_MASK (0x1U)
290 #define ADC16_SEQ_CFG0_HW_TRIG_EN_SHIFT (0U)
291 #define ADC16_SEQ_CFG0_HW_TRIG_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_HW_TRIG_EN_SHIFT) & ADC16_SEQ_CFG0_HW_TRIG_EN_MASK)
292 #define ADC16_SEQ_CFG0_HW_TRIG_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_HW_TRIG_EN_MASK) >> ADC16_SEQ_CFG0_HW_TRIG_EN_SHIFT)
293 
294 /* Bitfield definition for register: SEQ_DMA_ADDR */
295 /*
296  * TAR_ADDR (RW)
297  *
298  * dma target address, should be 4-byte aligned
299  */
300 #define ADC16_SEQ_DMA_ADDR_TAR_ADDR_MASK (0xFFFFFFFCUL)
301 #define ADC16_SEQ_DMA_ADDR_TAR_ADDR_SHIFT (2U)
302 #define ADC16_SEQ_DMA_ADDR_TAR_ADDR_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_ADDR_TAR_ADDR_SHIFT) & ADC16_SEQ_DMA_ADDR_TAR_ADDR_MASK)
303 #define ADC16_SEQ_DMA_ADDR_TAR_ADDR_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_ADDR_TAR_ADDR_MASK) >> ADC16_SEQ_DMA_ADDR_TAR_ADDR_SHIFT)
304 
305 /* Bitfield definition for register: SEQ_DMA_CFG */
306 /*
307  * STOP_POS (RW)
308  *
309  * if stop_en is set, SW is responsible to update this field to the next read point, HW should not write data to this point since it's not read out by SW yet
310  */
311 #define ADC16_SEQ_DMA_CFG_STOP_POS_MASK (0xFFF0000UL)
312 #define ADC16_SEQ_DMA_CFG_STOP_POS_SHIFT (16U)
313 #define ADC16_SEQ_DMA_CFG_STOP_POS_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_CFG_STOP_POS_SHIFT) & ADC16_SEQ_DMA_CFG_STOP_POS_MASK)
314 #define ADC16_SEQ_DMA_CFG_STOP_POS_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_CFG_STOP_POS_MASK) >> ADC16_SEQ_DMA_CFG_STOP_POS_SHIFT)
315 
316 /*
317  * DMA_RST (RW)
318  *
319  * set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set.
320  * SW should clear all cycle bit in buffer to 0 before clear dma_rst
321  */
322 #define ADC16_SEQ_DMA_CFG_DMA_RST_MASK (0x2000U)
323 #define ADC16_SEQ_DMA_CFG_DMA_RST_SHIFT (13U)
324 #define ADC16_SEQ_DMA_CFG_DMA_RST_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_CFG_DMA_RST_SHIFT) & ADC16_SEQ_DMA_CFG_DMA_RST_MASK)
325 #define ADC16_SEQ_DMA_CFG_DMA_RST_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_CFG_DMA_RST_MASK) >> ADC16_SEQ_DMA_CFG_DMA_RST_SHIFT)
326 
327 /*
328  * STOP_EN (RW)
329  *
330  * set to stop dma if reach the stop_pos
331  */
332 #define ADC16_SEQ_DMA_CFG_STOP_EN_MASK (0x1000U)
333 #define ADC16_SEQ_DMA_CFG_STOP_EN_SHIFT (12U)
334 #define ADC16_SEQ_DMA_CFG_STOP_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_CFG_STOP_EN_SHIFT) & ADC16_SEQ_DMA_CFG_STOP_EN_MASK)
335 #define ADC16_SEQ_DMA_CFG_STOP_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_CFG_STOP_EN_MASK) >> ADC16_SEQ_DMA_CFG_STOP_EN_SHIFT)
336 
337 /*
338  * BUF_LEN (RW)
339  *
340  * dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4
341  * 0 for 4byte;
342  * 0xFFF for 16kbyte.
343  */
344 #define ADC16_SEQ_DMA_CFG_BUF_LEN_MASK (0xFFFU)
345 #define ADC16_SEQ_DMA_CFG_BUF_LEN_SHIFT (0U)
346 #define ADC16_SEQ_DMA_CFG_BUF_LEN_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_CFG_BUF_LEN_SHIFT) & ADC16_SEQ_DMA_CFG_BUF_LEN_MASK)
347 #define ADC16_SEQ_DMA_CFG_BUF_LEN_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_CFG_BUF_LEN_MASK) >> ADC16_SEQ_DMA_CFG_BUF_LEN_SHIFT)
348 
349 /* Bitfield definition for register array: SEQ_QUE */
350 /*
351  * SEQ_INT_EN (RW)
352  *
353  * interrupt enable for current conversion
354  */
355 #define ADC16_SEQ_QUE_SEQ_INT_EN_MASK (0x20U)
356 #define ADC16_SEQ_QUE_SEQ_INT_EN_SHIFT (5U)
357 #define ADC16_SEQ_QUE_SEQ_INT_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_QUE_SEQ_INT_EN_SHIFT) & ADC16_SEQ_QUE_SEQ_INT_EN_MASK)
358 #define ADC16_SEQ_QUE_SEQ_INT_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_QUE_SEQ_INT_EN_MASK) >> ADC16_SEQ_QUE_SEQ_INT_EN_SHIFT)
359 
360 /*
361  * CHAN_NUM_4_0 (RW)
362  *
363  * channel number for current conversion
364  */
365 #define ADC16_SEQ_QUE_CHAN_NUM_4_0_MASK (0x1FU)
366 #define ADC16_SEQ_QUE_CHAN_NUM_4_0_SHIFT (0U)
367 #define ADC16_SEQ_QUE_CHAN_NUM_4_0_SET(x) (((uint32_t)(x) << ADC16_SEQ_QUE_CHAN_NUM_4_0_SHIFT) & ADC16_SEQ_QUE_CHAN_NUM_4_0_MASK)
368 #define ADC16_SEQ_QUE_CHAN_NUM_4_0_GET(x) (((uint32_t)(x) & ADC16_SEQ_QUE_CHAN_NUM_4_0_MASK) >> ADC16_SEQ_QUE_CHAN_NUM_4_0_SHIFT)
369 
370 /* Bitfield definition for register of struct array PRD_CFG: PRD_CFG */
371 /*
372  * PRESCALE (RW)
373  *
374  * 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx
375  */
376 #define ADC16_PRD_CFG_PRD_CFG_PRESCALE_MASK (0x1F00U)
377 #define ADC16_PRD_CFG_PRD_CFG_PRESCALE_SHIFT (8U)
378 #define ADC16_PRD_CFG_PRD_CFG_PRESCALE_SET(x) (((uint32_t)(x) << ADC16_PRD_CFG_PRD_CFG_PRESCALE_SHIFT) & ADC16_PRD_CFG_PRD_CFG_PRESCALE_MASK)
379 #define ADC16_PRD_CFG_PRD_CFG_PRESCALE_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_CFG_PRESCALE_MASK) >> ADC16_PRD_CFG_PRD_CFG_PRESCALE_SHIFT)
380 
381 /*
382  * PRD (RW)
383  *
384  * conver period, with prescale.
385  * Set to 0 means disable current channel
386  */
387 #define ADC16_PRD_CFG_PRD_CFG_PRD_MASK (0xFFU)
388 #define ADC16_PRD_CFG_PRD_CFG_PRD_SHIFT (0U)
389 #define ADC16_PRD_CFG_PRD_CFG_PRD_SET(x) (((uint32_t)(x) << ADC16_PRD_CFG_PRD_CFG_PRD_SHIFT) & ADC16_PRD_CFG_PRD_CFG_PRD_MASK)
390 #define ADC16_PRD_CFG_PRD_CFG_PRD_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_CFG_PRD_MASK) >> ADC16_PRD_CFG_PRD_CFG_PRD_SHIFT)
391 
392 /* Bitfield definition for register of struct array PRD_CFG: PRD_THSHD_CFG */
393 /*
394  * THSHDH (RW)
395  *
396  * threshold high, assert interrupt(if enabled) if result exceed high or low.
397  */
398 #define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK (0xFFFF0000UL)
399 #define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT (16U)
400 #define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_SET(x) (((uint32_t)(x) << ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT) & ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK)
401 #define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK) >> ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT)
402 
403 /*
404  * THSHDL (RW)
405  *
406  * threshold low
407  */
408 #define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK (0xFFFFU)
409 #define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT (0U)
410 #define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_SET(x) (((uint32_t)(x) << ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT) & ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK)
411 #define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK) >> ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT)
412 
413 /* Bitfield definition for register of struct array PRD_CFG: PRD_RESULT */
414 /*
415  * CHAN_RESULT (RO)
416  *
417  * adc convert result, update after each valid conversion.
418  * it may be updated period according to config, also may be updated due to other queue convert the same channel
419  */
420 #define ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_MASK (0xFFFFU)
421 #define ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_SHIFT (0U)
422 #define ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_MASK) >> ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_SHIFT)
423 
424 /* Bitfield definition for register array: SAMPLE_CFG */
425 /*
426  * SAMPLE_CLOCK_NUMBER_SHIFT (RW)
427  *
428  * shift for sample clock number
429  */
430 #define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_MASK (0xE00U)
431 #define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SHIFT (9U)
432 #define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SET(x) (((uint32_t)(x) << ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SHIFT) & ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_MASK)
433 #define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_GET(x) (((uint32_t)(x) & ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_MASK) >> ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SHIFT)
434 
435 /*
436  * SAMPLE_CLOCK_NUMBER (RW)
437  *
438  * sample clock number, base on clock_period, default one period
439  */
440 #define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_MASK (0x1FFU)
441 #define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT (0U)
442 #define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SET(x) (((uint32_t)(x) << ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT) & ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_MASK)
443 #define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_GET(x) (((uint32_t)(x) & ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_MASK) >> ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT)
444 
445 /* Bitfield definition for register: CONV_CFG1 */
446 /*
447  * CONVERT_CLOCK_NUMBER (RW)
448  *
449  * convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 21 adc clock cycles(based on clock after divider);
450  * user can use small value to get faster conversion, but less accuracy, need to config cov_end_cnt at adc16_config1 also.
451  * Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divider to 3, then each ADC conversion(plus sample) need 25 cycles(50MHz).
452  */
453 #define ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_MASK (0x1F0U)
454 #define ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SHIFT (4U)
455 #define ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SET(x) (((uint32_t)(x) << ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SHIFT) & ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_MASK)
456 #define ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_GET(x) (((uint32_t)(x) & ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_MASK) >> ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SHIFT)
457 
458 /*
459  * CLOCK_DIVIDER (RW)
460  *
461  * clock_period, N half clock cycle per half adc cycle
462  * 0 for same adc_clk and bus_clk,
463  * 1 for 1:2,
464  * 2 for 1:3,
465  * ...
466  * 15 for 1:16
467  * Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk
468  */
469 #define ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK (0xFU)
470 #define ADC16_CONV_CFG1_CLOCK_DIVIDER_SHIFT (0U)
471 #define ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(x) (((uint32_t)(x) << ADC16_CONV_CFG1_CLOCK_DIVIDER_SHIFT) & ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK)
472 #define ADC16_CONV_CFG1_CLOCK_DIVIDER_GET(x) (((uint32_t)(x) & ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) >> ADC16_CONV_CFG1_CLOCK_DIVIDER_SHIFT)
473 
474 /* Bitfield definition for register: ADC_CFG0 */
475 /*
476  * SEL_SYNC_AHB (RW)
477  *
478  * set to 1 will enable sync AHB bus, to get better bus performance.
479  * Adc_clk must to be set to same as bus clock at this mode
480  */
481 #define ADC16_ADC_CFG0_SEL_SYNC_AHB_MASK (0x80000000UL)
482 #define ADC16_ADC_CFG0_SEL_SYNC_AHB_SHIFT (31U)
483 #define ADC16_ADC_CFG0_SEL_SYNC_AHB_SET(x) (((uint32_t)(x) << ADC16_ADC_CFG0_SEL_SYNC_AHB_SHIFT) & ADC16_ADC_CFG0_SEL_SYNC_AHB_MASK)
484 #define ADC16_ADC_CFG0_SEL_SYNC_AHB_GET(x) (((uint32_t)(x) & ADC16_ADC_CFG0_SEL_SYNC_AHB_MASK) >> ADC16_ADC_CFG0_SEL_SYNC_AHB_SHIFT)
485 
486 /*
487  * ADC_AHB_EN (RW)
488  *
489  * set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue;
490  */
491 #define ADC16_ADC_CFG0_ADC_AHB_EN_MASK (0x20000000UL)
492 #define ADC16_ADC_CFG0_ADC_AHB_EN_SHIFT (29U)
493 #define ADC16_ADC_CFG0_ADC_AHB_EN_SET(x) (((uint32_t)(x) << ADC16_ADC_CFG0_ADC_AHB_EN_SHIFT) & ADC16_ADC_CFG0_ADC_AHB_EN_MASK)
494 #define ADC16_ADC_CFG0_ADC_AHB_EN_GET(x) (((uint32_t)(x) & ADC16_ADC_CFG0_ADC_AHB_EN_MASK) >> ADC16_ADC_CFG0_ADC_AHB_EN_SHIFT)
495 
496 /*
497  * PORT3_REALTIME (RW)
498  *
499  * set to enable trg queue stop other queues
500  */
501 #define ADC16_ADC_CFG0_PORT3_REALTIME_MASK (0x1U)
502 #define ADC16_ADC_CFG0_PORT3_REALTIME_SHIFT (0U)
503 #define ADC16_ADC_CFG0_PORT3_REALTIME_SET(x) (((uint32_t)(x) << ADC16_ADC_CFG0_PORT3_REALTIME_SHIFT) & ADC16_ADC_CFG0_PORT3_REALTIME_MASK)
504 #define ADC16_ADC_CFG0_PORT3_REALTIME_GET(x) (((uint32_t)(x) & ADC16_ADC_CFG0_PORT3_REALTIME_MASK) >> ADC16_ADC_CFG0_PORT3_REALTIME_SHIFT)
505 
506 /* Bitfield definition for register: INT_STS */
507 /*
508  * TRIG_CMPT (RW1C)
509  *
510  * interrupt for one trigger conversion complete if enabled
511  */
512 #define ADC16_INT_STS_TRIG_CMPT_MASK (0x80000000UL)
513 #define ADC16_INT_STS_TRIG_CMPT_SHIFT (31U)
514 #define ADC16_INT_STS_TRIG_CMPT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_TRIG_CMPT_SHIFT) & ADC16_INT_STS_TRIG_CMPT_MASK)
515 #define ADC16_INT_STS_TRIG_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_TRIG_CMPT_MASK) >> ADC16_INT_STS_TRIG_CMPT_SHIFT)
516 
517 /*
518  * TRIG_SW_CFLCT (RW1C)
519  *
520  */
521 #define ADC16_INT_STS_TRIG_SW_CFLCT_MASK (0x40000000UL)
522 #define ADC16_INT_STS_TRIG_SW_CFLCT_SHIFT (30U)
523 #define ADC16_INT_STS_TRIG_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_TRIG_SW_CFLCT_SHIFT) & ADC16_INT_STS_TRIG_SW_CFLCT_MASK)
524 #define ADC16_INT_STS_TRIG_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_TRIG_SW_CFLCT_MASK) >> ADC16_INT_STS_TRIG_SW_CFLCT_SHIFT)
525 
526 /*
527  * TRIG_HW_CFLCT (RW1C)
528  *
529  */
530 #define ADC16_INT_STS_TRIG_HW_CFLCT_MASK (0x20000000UL)
531 #define ADC16_INT_STS_TRIG_HW_CFLCT_SHIFT (29U)
532 #define ADC16_INT_STS_TRIG_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_TRIG_HW_CFLCT_SHIFT) & ADC16_INT_STS_TRIG_HW_CFLCT_MASK)
533 #define ADC16_INT_STS_TRIG_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_TRIG_HW_CFLCT_MASK) >> ADC16_INT_STS_TRIG_HW_CFLCT_SHIFT)
534 
535 /*
536  * READ_CFLCT (RW1C)
537  *
538  * read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel
539  */
540 #define ADC16_INT_STS_READ_CFLCT_MASK (0x10000000UL)
541 #define ADC16_INT_STS_READ_CFLCT_SHIFT (28U)
542 #define ADC16_INT_STS_READ_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_READ_CFLCT_SHIFT) & ADC16_INT_STS_READ_CFLCT_MASK)
543 #define ADC16_INT_STS_READ_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_READ_CFLCT_MASK) >> ADC16_INT_STS_READ_CFLCT_SHIFT)
544 
545 /*
546  * SEQ_SW_CFLCT (RW1C)
547  *
548  * sequence queue conflict interrupt, set if HW or SW trigger received during conversion
549  */
550 #define ADC16_INT_STS_SEQ_SW_CFLCT_MASK (0x8000000UL)
551 #define ADC16_INT_STS_SEQ_SW_CFLCT_SHIFT (27U)
552 #define ADC16_INT_STS_SEQ_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_SW_CFLCT_SHIFT) & ADC16_INT_STS_SEQ_SW_CFLCT_MASK)
553 #define ADC16_INT_STS_SEQ_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_SW_CFLCT_MASK) >> ADC16_INT_STS_SEQ_SW_CFLCT_SHIFT)
554 
555 /*
556  * SEQ_HW_CFLCT (RW1C)
557  *
558  */
559 #define ADC16_INT_STS_SEQ_HW_CFLCT_MASK (0x4000000UL)
560 #define ADC16_INT_STS_SEQ_HW_CFLCT_SHIFT (26U)
561 #define ADC16_INT_STS_SEQ_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_HW_CFLCT_SHIFT) & ADC16_INT_STS_SEQ_HW_CFLCT_MASK)
562 #define ADC16_INT_STS_SEQ_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_HW_CFLCT_MASK) >> ADC16_INT_STS_SEQ_HW_CFLCT_SHIFT)
563 
564 /*
565  * SEQ_DMAABT (RW1C)
566  *
567  * dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set
568  */
569 #define ADC16_INT_STS_SEQ_DMAABT_MASK (0x2000000UL)
570 #define ADC16_INT_STS_SEQ_DMAABT_SHIFT (25U)
571 #define ADC16_INT_STS_SEQ_DMAABT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_DMAABT_SHIFT) & ADC16_INT_STS_SEQ_DMAABT_MASK)
572 #define ADC16_INT_STS_SEQ_DMAABT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_DMAABT_MASK) >> ADC16_INT_STS_SEQ_DMAABT_SHIFT)
573 
574 /*
575  * SEQ_CMPT (RW1C)
576  *
577  * the whole sequence complete interrupt
578  */
579 #define ADC16_INT_STS_SEQ_CMPT_MASK (0x1000000UL)
580 #define ADC16_INT_STS_SEQ_CMPT_SHIFT (24U)
581 #define ADC16_INT_STS_SEQ_CMPT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_CMPT_SHIFT) & ADC16_INT_STS_SEQ_CMPT_MASK)
582 #define ADC16_INT_STS_SEQ_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_CMPT_MASK) >> ADC16_INT_STS_SEQ_CMPT_SHIFT)
583 
584 /*
585  * SEQ_CVC (RW1C)
586  *
587  * one conversion complete in seq_queue if related seq_int_en is set
588  */
589 #define ADC16_INT_STS_SEQ_CVC_MASK (0x800000UL)
590 #define ADC16_INT_STS_SEQ_CVC_SHIFT (23U)
591 #define ADC16_INT_STS_SEQ_CVC_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_CVC_SHIFT) & ADC16_INT_STS_SEQ_CVC_MASK)
592 #define ADC16_INT_STS_SEQ_CVC_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_CVC_MASK) >> ADC16_INT_STS_SEQ_CVC_SHIFT)
593 
594 /*
595  * DMA_FIFO_FULL (RW1C)
596  *
597  * DMA fifo full interrupt, user need to check clock frequency if it's set.
598  */
599 #define ADC16_INT_STS_DMA_FIFO_FULL_MASK (0x400000UL)
600 #define ADC16_INT_STS_DMA_FIFO_FULL_SHIFT (22U)
601 #define ADC16_INT_STS_DMA_FIFO_FULL_SET(x) (((uint32_t)(x) << ADC16_INT_STS_DMA_FIFO_FULL_SHIFT) & ADC16_INT_STS_DMA_FIFO_FULL_MASK)
602 #define ADC16_INT_STS_DMA_FIFO_FULL_GET(x) (((uint32_t)(x) & ADC16_INT_STS_DMA_FIFO_FULL_MASK) >> ADC16_INT_STS_DMA_FIFO_FULL_SHIFT)
603 
604 /*
605  * AHB_ERR (RW1C)
606  *
607  * set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr
608  */
609 #define ADC16_INT_STS_AHB_ERR_MASK (0x200000UL)
610 #define ADC16_INT_STS_AHB_ERR_SHIFT (21U)
611 #define ADC16_INT_STS_AHB_ERR_SET(x) (((uint32_t)(x) << ADC16_INT_STS_AHB_ERR_SHIFT) & ADC16_INT_STS_AHB_ERR_MASK)
612 #define ADC16_INT_STS_AHB_ERR_GET(x) (((uint32_t)(x) & ADC16_INT_STS_AHB_ERR_MASK) >> ADC16_INT_STS_AHB_ERR_SHIFT)
613 
614 /*
615  * WDOG (RW1C)
616  *
617  * set if one chanel watch dog event triggered
618  */
619 #define ADC16_INT_STS_WDOG_MASK (0xFFFFU)
620 #define ADC16_INT_STS_WDOG_SHIFT (0U)
621 #define ADC16_INT_STS_WDOG_SET(x) (((uint32_t)(x) << ADC16_INT_STS_WDOG_SHIFT) & ADC16_INT_STS_WDOG_MASK)
622 #define ADC16_INT_STS_WDOG_GET(x) (((uint32_t)(x) & ADC16_INT_STS_WDOG_MASK) >> ADC16_INT_STS_WDOG_SHIFT)
623 
624 /* Bitfield definition for register: INT_EN */
625 /*
626  * TRIG_CMPT (RW)
627  *
628  * interrupt for one trigger conversion complete if enabled
629  */
630 #define ADC16_INT_EN_TRIG_CMPT_MASK (0x80000000UL)
631 #define ADC16_INT_EN_TRIG_CMPT_SHIFT (31U)
632 #define ADC16_INT_EN_TRIG_CMPT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_TRIG_CMPT_SHIFT) & ADC16_INT_EN_TRIG_CMPT_MASK)
633 #define ADC16_INT_EN_TRIG_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_TRIG_CMPT_MASK) >> ADC16_INT_EN_TRIG_CMPT_SHIFT)
634 
635 /*
636  * TRIG_SW_CFLCT (RW)
637  *
638  */
639 #define ADC16_INT_EN_TRIG_SW_CFLCT_MASK (0x40000000UL)
640 #define ADC16_INT_EN_TRIG_SW_CFLCT_SHIFT (30U)
641 #define ADC16_INT_EN_TRIG_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_TRIG_SW_CFLCT_SHIFT) & ADC16_INT_EN_TRIG_SW_CFLCT_MASK)
642 #define ADC16_INT_EN_TRIG_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_TRIG_SW_CFLCT_MASK) >> ADC16_INT_EN_TRIG_SW_CFLCT_SHIFT)
643 
644 /*
645  * TRIG_HW_CFLCT (RW)
646  *
647  */
648 #define ADC16_INT_EN_TRIG_HW_CFLCT_MASK (0x20000000UL)
649 #define ADC16_INT_EN_TRIG_HW_CFLCT_SHIFT (29U)
650 #define ADC16_INT_EN_TRIG_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_TRIG_HW_CFLCT_SHIFT) & ADC16_INT_EN_TRIG_HW_CFLCT_MASK)
651 #define ADC16_INT_EN_TRIG_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_TRIG_HW_CFLCT_MASK) >> ADC16_INT_EN_TRIG_HW_CFLCT_SHIFT)
652 
653 /*
654  * READ_CFLCT (RW)
655  *
656  * read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel
657  */
658 #define ADC16_INT_EN_READ_CFLCT_MASK (0x10000000UL)
659 #define ADC16_INT_EN_READ_CFLCT_SHIFT (28U)
660 #define ADC16_INT_EN_READ_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_READ_CFLCT_SHIFT) & ADC16_INT_EN_READ_CFLCT_MASK)
661 #define ADC16_INT_EN_READ_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_READ_CFLCT_MASK) >> ADC16_INT_EN_READ_CFLCT_SHIFT)
662 
663 /*
664  * SEQ_SW_CFLCT (RW)
665  *
666  * sequence queue conflict interrupt, set if HW or SW trigger received during conversion
667  */
668 #define ADC16_INT_EN_SEQ_SW_CFLCT_MASK (0x8000000UL)
669 #define ADC16_INT_EN_SEQ_SW_CFLCT_SHIFT (27U)
670 #define ADC16_INT_EN_SEQ_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_SW_CFLCT_SHIFT) & ADC16_INT_EN_SEQ_SW_CFLCT_MASK)
671 #define ADC16_INT_EN_SEQ_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_SW_CFLCT_MASK) >> ADC16_INT_EN_SEQ_SW_CFLCT_SHIFT)
672 
673 /*
674  * SEQ_HW_CFLCT (RW)
675  *
676  */
677 #define ADC16_INT_EN_SEQ_HW_CFLCT_MASK (0x4000000UL)
678 #define ADC16_INT_EN_SEQ_HW_CFLCT_SHIFT (26U)
679 #define ADC16_INT_EN_SEQ_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_HW_CFLCT_SHIFT) & ADC16_INT_EN_SEQ_HW_CFLCT_MASK)
680 #define ADC16_INT_EN_SEQ_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_HW_CFLCT_MASK) >> ADC16_INT_EN_SEQ_HW_CFLCT_SHIFT)
681 
682 /*
683  * SEQ_DMAABT (RW)
684  *
685  * dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set
686  */
687 #define ADC16_INT_EN_SEQ_DMAABT_MASK (0x2000000UL)
688 #define ADC16_INT_EN_SEQ_DMAABT_SHIFT (25U)
689 #define ADC16_INT_EN_SEQ_DMAABT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_DMAABT_SHIFT) & ADC16_INT_EN_SEQ_DMAABT_MASK)
690 #define ADC16_INT_EN_SEQ_DMAABT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_DMAABT_MASK) >> ADC16_INT_EN_SEQ_DMAABT_SHIFT)
691 
692 /*
693  * SEQ_CMPT (RW)
694  *
695  * the whole sequence complete interrupt
696  */
697 #define ADC16_INT_EN_SEQ_CMPT_MASK (0x1000000UL)
698 #define ADC16_INT_EN_SEQ_CMPT_SHIFT (24U)
699 #define ADC16_INT_EN_SEQ_CMPT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_CMPT_SHIFT) & ADC16_INT_EN_SEQ_CMPT_MASK)
700 #define ADC16_INT_EN_SEQ_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_CMPT_MASK) >> ADC16_INT_EN_SEQ_CMPT_SHIFT)
701 
702 /*
703  * SEQ_CVC (RW)
704  *
705  * one conversion complete in seq_queue if related seq_int_en is set
706  */
707 #define ADC16_INT_EN_SEQ_CVC_MASK (0x800000UL)
708 #define ADC16_INT_EN_SEQ_CVC_SHIFT (23U)
709 #define ADC16_INT_EN_SEQ_CVC_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_CVC_SHIFT) & ADC16_INT_EN_SEQ_CVC_MASK)
710 #define ADC16_INT_EN_SEQ_CVC_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_CVC_MASK) >> ADC16_INT_EN_SEQ_CVC_SHIFT)
711 
712 /*
713  * DMA_FIFO_FULL (RW)
714  *
715  * DMA fifo full interrupt, user need to check clock frequency if it's set.
716  */
717 #define ADC16_INT_EN_DMA_FIFO_FULL_MASK (0x400000UL)
718 #define ADC16_INT_EN_DMA_FIFO_FULL_SHIFT (22U)
719 #define ADC16_INT_EN_DMA_FIFO_FULL_SET(x) (((uint32_t)(x) << ADC16_INT_EN_DMA_FIFO_FULL_SHIFT) & ADC16_INT_EN_DMA_FIFO_FULL_MASK)
720 #define ADC16_INT_EN_DMA_FIFO_FULL_GET(x) (((uint32_t)(x) & ADC16_INT_EN_DMA_FIFO_FULL_MASK) >> ADC16_INT_EN_DMA_FIFO_FULL_SHIFT)
721 
722 /*
723  * AHB_ERR (RW)
724  *
725  * set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr
726  */
727 #define ADC16_INT_EN_AHB_ERR_MASK (0x200000UL)
728 #define ADC16_INT_EN_AHB_ERR_SHIFT (21U)
729 #define ADC16_INT_EN_AHB_ERR_SET(x) (((uint32_t)(x) << ADC16_INT_EN_AHB_ERR_SHIFT) & ADC16_INT_EN_AHB_ERR_MASK)
730 #define ADC16_INT_EN_AHB_ERR_GET(x) (((uint32_t)(x) & ADC16_INT_EN_AHB_ERR_MASK) >> ADC16_INT_EN_AHB_ERR_SHIFT)
731 
732 /*
733  * WDOG (RW)
734  *
735  * set if one chanel watch dog event triggered
736  */
737 #define ADC16_INT_EN_WDOG_MASK (0xFFFFU)
738 #define ADC16_INT_EN_WDOG_SHIFT (0U)
739 #define ADC16_INT_EN_WDOG_SET(x) (((uint32_t)(x) << ADC16_INT_EN_WDOG_SHIFT) & ADC16_INT_EN_WDOG_MASK)
740 #define ADC16_INT_EN_WDOG_GET(x) (((uint32_t)(x) & ADC16_INT_EN_WDOG_MASK) >> ADC16_INT_EN_WDOG_SHIFT)
741 
742 /* Bitfield definition for register: ANA_CTRL0 */
743 /*
744  * ADC_CLK_ON (RW)
745  *
746  * set to enable adc clock to analog, Software should set this bit before access to any adc16_* register.
747  * MUST set clock_period to 0 or 1 for adc16 reg access
748  */
749 #define ADC16_ANA_CTRL0_ADC_CLK_ON_MASK (0x1000U)
750 #define ADC16_ANA_CTRL0_ADC_CLK_ON_SHIFT (12U)
751 #define ADC16_ANA_CTRL0_ADC_CLK_ON_SET(x) (((uint32_t)(x) << ADC16_ANA_CTRL0_ADC_CLK_ON_SHIFT) & ADC16_ANA_CTRL0_ADC_CLK_ON_MASK)
752 #define ADC16_ANA_CTRL0_ADC_CLK_ON_GET(x) (((uint32_t)(x) & ADC16_ANA_CTRL0_ADC_CLK_ON_MASK) >> ADC16_ANA_CTRL0_ADC_CLK_ON_SHIFT)
753 
754 /*
755  * STARTCAL (RW)
756  *
757  * set to start the offset calibration cycle (Active H). user need to clear it after setting it.
758  */
759 #define ADC16_ANA_CTRL0_STARTCAL_MASK (0x4U)
760 #define ADC16_ANA_CTRL0_STARTCAL_SHIFT (2U)
761 #define ADC16_ANA_CTRL0_STARTCAL_SET(x) (((uint32_t)(x) << ADC16_ANA_CTRL0_STARTCAL_SHIFT) & ADC16_ANA_CTRL0_STARTCAL_MASK)
762 #define ADC16_ANA_CTRL0_STARTCAL_GET(x) (((uint32_t)(x) & ADC16_ANA_CTRL0_STARTCAL_MASK) >> ADC16_ANA_CTRL0_STARTCAL_SHIFT)
763 
764 /* Bitfield definition for register: ANA_STATUS */
765 /*
766  * CALON (RW)
767  *
768  * Indicates if the ADC is in calibration mode (Active H).
769  */
770 #define ADC16_ANA_STATUS_CALON_MASK (0x80U)
771 #define ADC16_ANA_STATUS_CALON_SHIFT (7U)
772 #define ADC16_ANA_STATUS_CALON_SET(x) (((uint32_t)(x) << ADC16_ANA_STATUS_CALON_SHIFT) & ADC16_ANA_STATUS_CALON_MASK)
773 #define ADC16_ANA_STATUS_CALON_GET(x) (((uint32_t)(x) & ADC16_ANA_STATUS_CALON_MASK) >> ADC16_ANA_STATUS_CALON_SHIFT)
774 
775 /* Bitfield definition for register array: ADC16_PARAMS */
776 /*
777  * PARAM_VAL (RW)
778  *
779  */
780 #define ADC16_ADC16_PARAMS_PARAM_VAL_MASK (0xFFFFU)
781 #define ADC16_ADC16_PARAMS_PARAM_VAL_SHIFT (0U)
782 #define ADC16_ADC16_PARAMS_PARAM_VAL_SET(x) (((uint16_t)(x) << ADC16_ADC16_PARAMS_PARAM_VAL_SHIFT) & ADC16_ADC16_PARAMS_PARAM_VAL_MASK)
783 #define ADC16_ADC16_PARAMS_PARAM_VAL_GET(x) (((uint16_t)(x) & ADC16_ADC16_PARAMS_PARAM_VAL_MASK) >> ADC16_ADC16_PARAMS_PARAM_VAL_SHIFT)
784 
785 /* Bitfield definition for register: ADC16_CONFIG0 */
786 /*
787  * REG_EN (RW)
788  *
789  * set to enable regulator
790  */
791 #define ADC16_ADC16_CONFIG0_REG_EN_MASK (0x1000000UL)
792 #define ADC16_ADC16_CONFIG0_REG_EN_SHIFT (24U)
793 #define ADC16_ADC16_CONFIG0_REG_EN_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_REG_EN_SHIFT) & ADC16_ADC16_CONFIG0_REG_EN_MASK)
794 #define ADC16_ADC16_CONFIG0_REG_EN_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_REG_EN_MASK) >> ADC16_ADC16_CONFIG0_REG_EN_SHIFT)
795 
796 /*
797  * BANDGAP_EN (RW)
798  *
799  * set to enable bandgap. user should set reg_en and bandgap_en before use adc16.
800  */
801 #define ADC16_ADC16_CONFIG0_BANDGAP_EN_MASK (0x800000UL)
802 #define ADC16_ADC16_CONFIG0_BANDGAP_EN_SHIFT (23U)
803 #define ADC16_ADC16_CONFIG0_BANDGAP_EN_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_BANDGAP_EN_SHIFT) & ADC16_ADC16_CONFIG0_BANDGAP_EN_MASK)
804 #define ADC16_ADC16_CONFIG0_BANDGAP_EN_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_BANDGAP_EN_MASK) >> ADC16_ADC16_CONFIG0_BANDGAP_EN_SHIFT)
805 
806 /*
807  * CAL_AVG_CFG (RW)
808  *
809  * for average the calibration result.
810  * 0- 1 loop; 1- 2 loops; 2- 4 loops; 3- 8 loops;
811  * 4- 16 loops; 5-32 loops; others reserved
812  */
813 #define ADC16_ADC16_CONFIG0_CAL_AVG_CFG_MASK (0x700000UL)
814 #define ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SHIFT (20U)
815 #define ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SHIFT) & ADC16_ADC16_CONFIG0_CAL_AVG_CFG_MASK)
816 #define ADC16_ADC16_CONFIG0_CAL_AVG_CFG_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_CAL_AVG_CFG_MASK) >> ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SHIFT)
817 
818 /*
819  * PREEMPT_EN (RW)
820  *
821  * set to enable preemption feature
822  */
823 #define ADC16_ADC16_CONFIG0_PREEMPT_EN_MASK (0x4000U)
824 #define ADC16_ADC16_CONFIG0_PREEMPT_EN_SHIFT (14U)
825 #define ADC16_ADC16_CONFIG0_PREEMPT_EN_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_PREEMPT_EN_SHIFT) & ADC16_ADC16_CONFIG0_PREEMPT_EN_MASK)
826 #define ADC16_ADC16_CONFIG0_PREEMPT_EN_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_PREEMPT_EN_MASK) >> ADC16_ADC16_CONFIG0_PREEMPT_EN_SHIFT)
827 
828 /*
829  * CONV_PARAM (RW)
830  *
831  * conversion parameter
832  */
833 #define ADC16_ADC16_CONFIG0_CONV_PARAM_MASK (0x3FFFU)
834 #define ADC16_ADC16_CONFIG0_CONV_PARAM_SHIFT (0U)
835 #define ADC16_ADC16_CONFIG0_CONV_PARAM_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_CONV_PARAM_SHIFT) & ADC16_ADC16_CONFIG0_CONV_PARAM_MASK)
836 #define ADC16_ADC16_CONFIG0_CONV_PARAM_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_CONV_PARAM_MASK) >> ADC16_ADC16_CONFIG0_CONV_PARAM_SHIFT)
837 
838 /* Bitfield definition for register: ADC16_CONFIG1 */
839 /*
840  * COV_END_CNT (RW)
841  *
842  * used for faster conversion, user can change it to get higher convert speed(but less accuracy).
843  * should set to (21-convert_clock_number+1).
844  */
845 #define ADC16_ADC16_CONFIG1_COV_END_CNT_MASK (0x1F00U)
846 #define ADC16_ADC16_CONFIG1_COV_END_CNT_SHIFT (8U)
847 #define ADC16_ADC16_CONFIG1_COV_END_CNT_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG1_COV_END_CNT_SHIFT) & ADC16_ADC16_CONFIG1_COV_END_CNT_MASK)
848 #define ADC16_ADC16_CONFIG1_COV_END_CNT_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG1_COV_END_CNT_MASK) >> ADC16_ADC16_CONFIG1_COV_END_CNT_SHIFT)
849 
850 
851 
852 /* CONFIG register group index macro definition */
853 #define ADC16_CONFIG_TRG0A (0UL)
854 #define ADC16_CONFIG_TRG0B (1UL)
855 #define ADC16_CONFIG_TRG0C (2UL)
856 #define ADC16_CONFIG_TRG1A (3UL)
857 #define ADC16_CONFIG_TRG1B (4UL)
858 #define ADC16_CONFIG_TRG1C (5UL)
859 #define ADC16_CONFIG_TRG2A (6UL)
860 #define ADC16_CONFIG_TRG2B (7UL)
861 #define ADC16_CONFIG_TRG2C (8UL)
862 #define ADC16_CONFIG_TRG3A (9UL)
863 #define ADC16_CONFIG_TRG3B (10UL)
864 #define ADC16_CONFIG_TRG3C (11UL)
865 
866 /* BUS_RESULT register group index macro definition */
867 #define ADC16_BUS_RESULT_CHN0 (0UL)
868 #define ADC16_BUS_RESULT_CHN1 (1UL)
869 #define ADC16_BUS_RESULT_CHN2 (2UL)
870 #define ADC16_BUS_RESULT_CHN3 (3UL)
871 #define ADC16_BUS_RESULT_CHN4 (4UL)
872 #define ADC16_BUS_RESULT_CHN5 (5UL)
873 #define ADC16_BUS_RESULT_CHN6 (6UL)
874 #define ADC16_BUS_RESULT_CHN7 (7UL)
875 #define ADC16_BUS_RESULT_CHN8 (8UL)
876 #define ADC16_BUS_RESULT_CHN9 (9UL)
877 #define ADC16_BUS_RESULT_CHN10 (10UL)
878 #define ADC16_BUS_RESULT_CHN11 (11UL)
879 #define ADC16_BUS_RESULT_CHN12 (12UL)
880 #define ADC16_BUS_RESULT_CHN13 (13UL)
881 #define ADC16_BUS_RESULT_CHN14 (14UL)
882 #define ADC16_BUS_RESULT_CHN15 (15UL)
883 
884 /* SEQ_QUE register group index macro definition */
885 #define ADC16_SEQ_QUE_CFG0 (0UL)
886 #define ADC16_SEQ_QUE_CFG1 (1UL)
887 #define ADC16_SEQ_QUE_CFG2 (2UL)
888 #define ADC16_SEQ_QUE_CFG3 (3UL)
889 #define ADC16_SEQ_QUE_CFG4 (4UL)
890 #define ADC16_SEQ_QUE_CFG5 (5UL)
891 #define ADC16_SEQ_QUE_CFG6 (6UL)
892 #define ADC16_SEQ_QUE_CFG7 (7UL)
893 #define ADC16_SEQ_QUE_CFG8 (8UL)
894 #define ADC16_SEQ_QUE_CFG9 (9UL)
895 #define ADC16_SEQ_QUE_CFG10 (10UL)
896 #define ADC16_SEQ_QUE_CFG11 (11UL)
897 #define ADC16_SEQ_QUE_CFG12 (12UL)
898 #define ADC16_SEQ_QUE_CFG13 (13UL)
899 #define ADC16_SEQ_QUE_CFG14 (14UL)
900 #define ADC16_SEQ_QUE_CFG15 (15UL)
901 
902 /* PRD_CFG register group index macro definition */
903 #define ADC16_PRD_CFG_CHN0 (0UL)
904 #define ADC16_PRD_CFG_CHN1 (1UL)
905 #define ADC16_PRD_CFG_CHN2 (2UL)
906 #define ADC16_PRD_CFG_CHN3 (3UL)
907 #define ADC16_PRD_CFG_CHN4 (4UL)
908 #define ADC16_PRD_CFG_CHN5 (5UL)
909 #define ADC16_PRD_CFG_CHN6 (6UL)
910 #define ADC16_PRD_CFG_CHN7 (7UL)
911 #define ADC16_PRD_CFG_CHN8 (8UL)
912 #define ADC16_PRD_CFG_CHN9 (9UL)
913 #define ADC16_PRD_CFG_CHN10 (10UL)
914 #define ADC16_PRD_CFG_CHN11 (11UL)
915 #define ADC16_PRD_CFG_CHN12 (12UL)
916 #define ADC16_PRD_CFG_CHN13 (13UL)
917 #define ADC16_PRD_CFG_CHN14 (14UL)
918 #define ADC16_PRD_CFG_CHN15 (15UL)
919 
920 /* SAMPLE_CFG register group index macro definition */
921 #define ADC16_SAMPLE_CFG_CHN0 (0UL)
922 #define ADC16_SAMPLE_CFG_CHN1 (1UL)
923 #define ADC16_SAMPLE_CFG_CHN2 (2UL)
924 #define ADC16_SAMPLE_CFG_CHN3 (3UL)
925 #define ADC16_SAMPLE_CFG_CHN4 (4UL)
926 #define ADC16_SAMPLE_CFG_CHN5 (5UL)
927 #define ADC16_SAMPLE_CFG_CHN6 (6UL)
928 #define ADC16_SAMPLE_CFG_CHN7 (7UL)
929 #define ADC16_SAMPLE_CFG_CHN8 (8UL)
930 #define ADC16_SAMPLE_CFG_CHN9 (9UL)
931 #define ADC16_SAMPLE_CFG_CHN10 (10UL)
932 #define ADC16_SAMPLE_CFG_CHN11 (11UL)
933 #define ADC16_SAMPLE_CFG_CHN12 (12UL)
934 #define ADC16_SAMPLE_CFG_CHN13 (13UL)
935 #define ADC16_SAMPLE_CFG_CHN14 (14UL)
936 #define ADC16_SAMPLE_CFG_CHN15 (15UL)
937 
938 /* ADC16_PARAMS register group index macro definition */
939 #define ADC16_ADC16_PARAMS_ADC16_PARA00 (0UL)
940 #define ADC16_ADC16_PARAMS_ADC16_PARA01 (1UL)
941 #define ADC16_ADC16_PARAMS_ADC16_PARA02 (2UL)
942 #define ADC16_ADC16_PARAMS_ADC16_PARA03 (3UL)
943 #define ADC16_ADC16_PARAMS_ADC16_PARA04 (4UL)
944 #define ADC16_ADC16_PARAMS_ADC16_PARA05 (5UL)
945 #define ADC16_ADC16_PARAMS_ADC16_PARA06 (6UL)
946 #define ADC16_ADC16_PARAMS_ADC16_PARA07 (7UL)
947 #define ADC16_ADC16_PARAMS_ADC16_PARA08 (8UL)
948 #define ADC16_ADC16_PARAMS_ADC16_PARA09 (9UL)
949 #define ADC16_ADC16_PARAMS_ADC16_PARA10 (10UL)
950 #define ADC16_ADC16_PARAMS_ADC16_PARA11 (11UL)
951 #define ADC16_ADC16_PARAMS_ADC16_PARA12 (12UL)
952 #define ADC16_ADC16_PARAMS_ADC16_PARA13 (13UL)
953 #define ADC16_ADC16_PARAMS_ADC16_PARA14 (14UL)
954 #define ADC16_ADC16_PARAMS_ADC16_PARA15 (15UL)
955 #define ADC16_ADC16_PARAMS_ADC16_PARA16 (16UL)
956 #define ADC16_ADC16_PARAMS_ADC16_PARA17 (17UL)
957 #define ADC16_ADC16_PARAMS_ADC16_PARA18 (18UL)
958 #define ADC16_ADC16_PARAMS_ADC16_PARA19 (19UL)
959 #define ADC16_ADC16_PARAMS_ADC16_PARA20 (20UL)
960 #define ADC16_ADC16_PARAMS_ADC16_PARA21 (21UL)
961 #define ADC16_ADC16_PARAMS_ADC16_PARA22 (22UL)
962 #define ADC16_ADC16_PARAMS_ADC16_PARA23 (23UL)
963 #define ADC16_ADC16_PARAMS_ADC16_PARA24 (24UL)
964 #define ADC16_ADC16_PARAMS_ADC16_PARA25 (25UL)
965 #define ADC16_ADC16_PARAMS_ADC16_PARA26 (26UL)
966 #define ADC16_ADC16_PARAMS_ADC16_PARA27 (27UL)
967 #define ADC16_ADC16_PARAMS_ADC16_PARA28 (28UL)
968 #define ADC16_ADC16_PARAMS_ADC16_PARA29 (29UL)
969 #define ADC16_ADC16_PARAMS_ADC16_PARA30 (30UL)
970 #define ADC16_ADC16_PARAMS_ADC16_PARA31 (31UL)
971 #define ADC16_ADC16_PARAMS_ADC16_PARA32 (32UL)
972 #define ADC16_ADC16_PARAMS_ADC16_PARA33 (33UL)
973 
974 
975 #endif /* HPM_ADC16_H */
ADC16_Type
Definition: hpm_adc16_regs.h:12