HPM SDK
HPMicro Software Development Kit
hpm_sysctl_regs.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_SYSCTL_H
10 #define HPM_SYSCTL_H
11 
12 typedef struct {
13  __RW uint32_t RESOURCE[318]; /* 0x0 - 0x4F4: Resource control register for cpu0_core */
14  __R uint8_t RESERVED0[776]; /* 0x4F8 - 0x7FF: Reserved */
15  struct {
16  __RW uint32_t VALUE; /* 0x800: Group setting */
17  __RW uint32_t SET; /* 0x804: Group setting */
18  __RW uint32_t CLEAR; /* 0x808: Group setting */
19  __RW uint32_t TOGGLE; /* 0x80C: Group setting */
20  } GROUP0[2];
21  __R uint8_t RESERVED1[224]; /* 0x820 - 0x8FF: Reserved */
22  struct {
23  __RW uint32_t VALUE; /* 0x900: Affiliate of Group */
24  __RW uint32_t SET; /* 0x904: Affiliate of Group */
25  __RW uint32_t CLEAR; /* 0x908: Affiliate of Group */
26  __RW uint32_t TOGGLE; /* 0x90C: Affiliate of Group */
27  } AFFILIATE[1];
28  __R uint8_t RESERVED2[16]; /* 0x910 - 0x91F: Reserved */
29  struct {
30  __RW uint32_t VALUE; /* 0x920: Retention Control */
31  __RW uint32_t SET; /* 0x924: Retention Control */
32  __RW uint32_t CLEAR; /* 0x928: Retention Control */
33  __RW uint32_t TOGGLE; /* 0x92C: Retention Control */
34  } RETENTION[1];
35  __R uint8_t RESERVED3[1744]; /* 0x930 - 0xFFF: Reserved */
36  struct {
37  __RW uint32_t STATUS; /* 0x1000: Power Setting */
38  __RW uint32_t LF_WAIT; /* 0x1004: Power Setting */
39  __R uint8_t RESERVED0[4]; /* 0x1008 - 0x100B: Reserved */
40  __RW uint32_t OFF_WAIT; /* 0x100C: Power Setting */
41  } POWER[1];
42  __R uint8_t RESERVED4[1008]; /* 0x1010 - 0x13FF: Reserved */
43  struct {
44  __RW uint32_t CONTROL; /* 0x1400: Reset Setting */
45  __RW uint32_t CONFIG; /* 0x1404: Reset Setting */
46  __R uint8_t RESERVED0[4]; /* 0x1408 - 0x140B: Reserved */
47  __RW uint32_t COUNTER; /* 0x140C: Reset Setting */
48  } RESET[2];
49  __R uint8_t RESERVED5[992]; /* 0x1420 - 0x17FF: Reserved */
50  __RW uint32_t CLOCK_CPU[1]; /* 0x1800: Clock setting */
51  __RW uint32_t CLOCK[39]; /* 0x1804 - 0x189C: Clock setting */
52  __R uint8_t RESERVED6[864]; /* 0x18A0 - 0x1BFF: Reserved */
53  __RW uint32_t ADCCLK[3]; /* 0x1C00 - 0x1C08: Clock setting */
54  __RW uint32_t DACCLK[1]; /* 0x1C0C: Clock setting */
55  __RW uint32_t I2SCLK[2]; /* 0x1C10 - 0x1C14: Clock setting */
56  __R uint8_t RESERVED7[1000]; /* 0x1C18 - 0x1FFF: Reserved */
57  __RW uint32_t GLOBAL00; /* 0x2000: Clock senario */
58  __R uint8_t RESERVED8[1020]; /* 0x2004 - 0x23FF: Reserved */
59  struct {
60  __RW uint32_t CONTROL; /* 0x2400: Clock measure and monitor control */
61  __R uint32_t CURRENT; /* 0x2404: Clock measure result */
62  __RW uint32_t LOW_LIMIT; /* 0x2408: Clock lower limit */
63  __RW uint32_t HIGH_LIMIT; /* 0x240C: Clock upper limit */
64  __R uint8_t RESERVED0[16]; /* 0x2410 - 0x241F: Reserved */
65  } MONITOR[4];
66  __R uint8_t RESERVED9[896]; /* 0x2480 - 0x27FF: Reserved */
67  struct {
68  __RW uint32_t LP; /* 0x2800: CPU0 LP control */
69  __RW uint32_t LOCK; /* 0x2804: CPU0 Lock GPR */
70  __RW uint32_t GPR[14]; /* 0x2808 - 0x283C: CPU0 GPR0 */
71  __R uint32_t WAKEUP_STATUS[4]; /* 0x2840 - 0x284C: CPU0 wakeup IRQ status */
72  __R uint8_t RESERVED0[48]; /* 0x2850 - 0x287F: Reserved */
73  __RW uint32_t WAKEUP_ENABLE[4]; /* 0x2880 - 0x288C: CPU0 wakeup IRQ enable */
74  __R uint8_t RESERVED1[880]; /* 0x2890 - 0x2BFF: Reserved */
75  } CPU[1];
76 } SYSCTL_Type;
77 
78 
79 /* Bitfield definition for register array: RESOURCE */
80 /*
81  * GLB_BUSY (RO)
82  *
83  * global busy
84  * 0: no changes pending to any nodes
85  * 1: any of nodes is changing status
86  */
87 #define SYSCTL_RESOURCE_GLB_BUSY_MASK (0x80000000UL)
88 #define SYSCTL_RESOURCE_GLB_BUSY_SHIFT (31U)
89 #define SYSCTL_RESOURCE_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_GLB_BUSY_MASK) >> SYSCTL_RESOURCE_GLB_BUSY_SHIFT)
90 
91 /*
92  * LOC_BUSY (RO)
93  *
94  * local busy
95  * 0: no change is pending for current node
96  * 1: current node is changing status
97  */
98 #define SYSCTL_RESOURCE_LOC_BUSY_MASK (0x40000000UL)
99 #define SYSCTL_RESOURCE_LOC_BUSY_SHIFT (30U)
100 #define SYSCTL_RESOURCE_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_LOC_BUSY_MASK) >> SYSCTL_RESOURCE_LOC_BUSY_SHIFT)
101 
102 /*
103  * MODE (RW)
104  *
105  * resource work mode
106  * 0:auto turn on and off as system required(recommended)
107  * 1:always on
108  * 2:always off
109  * 3:reserved
110  */
111 #define SYSCTL_RESOURCE_MODE_MASK (0x3U)
112 #define SYSCTL_RESOURCE_MODE_SHIFT (0U)
113 #define SYSCTL_RESOURCE_MODE_SET(x) (((uint32_t)(x) << SYSCTL_RESOURCE_MODE_SHIFT) & SYSCTL_RESOURCE_MODE_MASK)
114 #define SYSCTL_RESOURCE_MODE_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_MODE_MASK) >> SYSCTL_RESOURCE_MODE_SHIFT)
115 
116 /* Bitfield definition for register of struct array GROUP0: VALUE */
117 /*
118  * LINK (RW)
119  *
120  * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral
121  * 0: peripheral is not needed
122  * 1: periphera is needed
123  */
124 #define SYSCTL_GROUP0_VALUE_LINK_MASK (0xFFFFFFFFUL)
125 #define SYSCTL_GROUP0_VALUE_LINK_SHIFT (0U)
126 #define SYSCTL_GROUP0_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_VALUE_LINK_SHIFT) & SYSCTL_GROUP0_VALUE_LINK_MASK)
127 #define SYSCTL_GROUP0_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_VALUE_LINK_MASK) >> SYSCTL_GROUP0_VALUE_LINK_SHIFT)
128 
129 /* Bitfield definition for register of struct array GROUP0: SET */
130 /*
131  * LINK (RW)
132  *
133  * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral
134  * 0: no effect
135  * 1: add periphera into this group，periphera is needed
136  */
137 #define SYSCTL_GROUP0_SET_LINK_MASK (0xFFFFFFFFUL)
138 #define SYSCTL_GROUP0_SET_LINK_SHIFT (0U)
139 #define SYSCTL_GROUP0_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_SET_LINK_SHIFT) & SYSCTL_GROUP0_SET_LINK_MASK)
140 #define SYSCTL_GROUP0_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_SET_LINK_MASK) >> SYSCTL_GROUP0_SET_LINK_SHIFT)
141 
142 /* Bitfield definition for register of struct array GROUP0: CLEAR */
143 /*
144  * LINK (RW)
145  *
146  * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral
147  * 0: no effect
148  * 1: delete periphera in this group，periphera is not needed
149  */
150 #define SYSCTL_GROUP0_CLEAR_LINK_MASK (0xFFFFFFFFUL)
151 #define SYSCTL_GROUP0_CLEAR_LINK_SHIFT (0U)
152 #define SYSCTL_GROUP0_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_CLEAR_LINK_SHIFT) & SYSCTL_GROUP0_CLEAR_LINK_MASK)
153 #define SYSCTL_GROUP0_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_CLEAR_LINK_MASK) >> SYSCTL_GROUP0_CLEAR_LINK_SHIFT)
154 
155 /* Bitfield definition for register of struct array GROUP0: TOGGLE */
156 /*
157  * LINK (RW)
158  *
159  * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral
160  * 0: no effect
161  * 1: toggle the result that whether periphera is needed before
162  */
163 #define SYSCTL_GROUP0_TOGGLE_LINK_MASK (0xFFFFFFFFUL)
164 #define SYSCTL_GROUP0_TOGGLE_LINK_SHIFT (0U)
165 #define SYSCTL_GROUP0_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_TOGGLE_LINK_SHIFT) & SYSCTL_GROUP0_TOGGLE_LINK_MASK)
166 #define SYSCTL_GROUP0_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_TOGGLE_LINK_MASK) >> SYSCTL_GROUP0_TOGGLE_LINK_SHIFT)
167 
168 /* Bitfield definition for register of struct array AFFILIATE: VALUE */
169 /*
170  * LINK (RW)
171  *
172  * Affiliate groups of cpu0, each bit represents a group
173  * bit0: cpu0 depends on group0
174  * bit1: cpu0 depends on group1
175  * bit2: cpu0 depends on group2
176  * bit3: cpu0 depends on group3
177  */
178 #define SYSCTL_AFFILIATE_VALUE_LINK_MASK (0xFU)
179 #define SYSCTL_AFFILIATE_VALUE_LINK_SHIFT (0U)
180 #define SYSCTL_AFFILIATE_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_VALUE_LINK_SHIFT) & SYSCTL_AFFILIATE_VALUE_LINK_MASK)
181 #define SYSCTL_AFFILIATE_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_VALUE_LINK_MASK) >> SYSCTL_AFFILIATE_VALUE_LINK_SHIFT)
182 
183 /* Bitfield definition for register of struct array AFFILIATE: SET */
184 /*
185  * LINK (RW)
186  *
187  * Affiliate groups of cpu0，each bit represents a group
188  * 0: no effect
189  * 1: the group is assigned to CPU0
190  */
191 #define SYSCTL_AFFILIATE_SET_LINK_MASK (0xFU)
192 #define SYSCTL_AFFILIATE_SET_LINK_SHIFT (0U)
193 #define SYSCTL_AFFILIATE_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_SET_LINK_SHIFT) & SYSCTL_AFFILIATE_SET_LINK_MASK)
194 #define SYSCTL_AFFILIATE_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_SET_LINK_MASK) >> SYSCTL_AFFILIATE_SET_LINK_SHIFT)
195 
196 /* Bitfield definition for register of struct array AFFILIATE: CLEAR */
197 /*
198  * LINK (RW)
199  *
200  * Affiliate groups of cpu0, each bit represents a group
201  * 0: no effect
202  * 1: the group is not assigned to CPU0
203  */
204 #define SYSCTL_AFFILIATE_CLEAR_LINK_MASK (0xFU)
205 #define SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT (0U)
206 #define SYSCTL_AFFILIATE_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK)
207 #define SYSCTL_AFFILIATE_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK) >> SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT)
208 
209 /* Bitfield definition for register of struct array AFFILIATE: TOGGLE */
210 /*
211  * LINK (RW)
212  *
213  * Affiliate groups of cpu0, each bit represents a group
214  * 0: no effect
215  * 1: toggle the result that whether the group is assigned to CPU0 before
216  */
217 #define SYSCTL_AFFILIATE_TOGGLE_LINK_MASK (0xFU)
218 #define SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT (0U)
219 #define SYSCTL_AFFILIATE_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK)
220 #define SYSCTL_AFFILIATE_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK) >> SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT)
221 
222 /* Bitfield definition for register of struct array RETENTION: VALUE */
223 /*
224  * LINK (RW)
225  *
226  * retention setting while CPU0 enter stop mode, each bit represents a resource
227  * bit00: soc_mem is kept on while cpu stop,
228  * bit01: soc_ctx is kept on while cpu stop,
229  * bit02: cpu0_mem is kept on while cpu stop,
230  * bit03: cpu0_ctx is kept on while cpu stop,
231  * bit04: xtal_hold is kept on while cpu stop,
232  * bit05: pll0_hold is kept on while cpu stop,
233  * bit06: pll1_hold is kept on while cpu stop,
234  * bit07: pll2_hold is kept on while cpu stop,
235  */
236 #define SYSCTL_RETENTION_VALUE_LINK_MASK (0xFFU)
237 #define SYSCTL_RETENTION_VALUE_LINK_SHIFT (0U)
238 #define SYSCTL_RETENTION_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_VALUE_LINK_SHIFT) & SYSCTL_RETENTION_VALUE_LINK_MASK)
239 #define SYSCTL_RETENTION_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_VALUE_LINK_MASK) >> SYSCTL_RETENTION_VALUE_LINK_SHIFT)
240 
241 /* Bitfield definition for register of struct array RETENTION: SET */
242 /*
243  * LINK (RW)
244  *
245  * retention setting while CPU0 enter stop mode, each bit represents a resource
246  * 0: no effect
247  * 1: keep
248  */
249 #define SYSCTL_RETENTION_SET_LINK_MASK (0xFFU)
250 #define SYSCTL_RETENTION_SET_LINK_SHIFT (0U)
251 #define SYSCTL_RETENTION_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_SET_LINK_SHIFT) & SYSCTL_RETENTION_SET_LINK_MASK)
252 #define SYSCTL_RETENTION_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_SET_LINK_MASK) >> SYSCTL_RETENTION_SET_LINK_SHIFT)
253 
254 /* Bitfield definition for register of struct array RETENTION: CLEAR */
255 /*
256  * LINK (RW)
257  *
258  * retention setting while CPU0 enter stop mode, each bit represents a resource
259  * 0: no effect
260  * 1: no keep
261  */
262 #define SYSCTL_RETENTION_CLEAR_LINK_MASK (0xFFU)
263 #define SYSCTL_RETENTION_CLEAR_LINK_SHIFT (0U)
264 #define SYSCTL_RETENTION_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_CLEAR_LINK_SHIFT) & SYSCTL_RETENTION_CLEAR_LINK_MASK)
265 #define SYSCTL_RETENTION_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_CLEAR_LINK_MASK) >> SYSCTL_RETENTION_CLEAR_LINK_SHIFT)
266 
267 /* Bitfield definition for register of struct array RETENTION: TOGGLE */
268 /*
269  * LINK (RW)
270  *
271  * retention setting while CPU0 enter stop mode, each bit represents a resource
272  * 0: no effect
273  * 1: toggle the result that whether the resource is kept on while CPU0 stop before
274  */
275 #define SYSCTL_RETENTION_TOGGLE_LINK_MASK (0xFFU)
276 #define SYSCTL_RETENTION_TOGGLE_LINK_SHIFT (0U)
277 #define SYSCTL_RETENTION_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_TOGGLE_LINK_SHIFT) & SYSCTL_RETENTION_TOGGLE_LINK_MASK)
278 #define SYSCTL_RETENTION_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_TOGGLE_LINK_MASK) >> SYSCTL_RETENTION_TOGGLE_LINK_SHIFT)
279 
280 /* Bitfield definition for register of struct array POWER: STATUS */
281 /*
282  * FLAG (RW)
283  *
284  * flag represents power cycle happened from last clear of this bit
285  * 0: power domain did not edurance power cycle since last clear of this bit
286  * 1: power domain enduranced power cycle since last clear of this bit
287  */
288 #define SYSCTL_POWER_STATUS_FLAG_MASK (0x80000000UL)
289 #define SYSCTL_POWER_STATUS_FLAG_SHIFT (31U)
290 #define SYSCTL_POWER_STATUS_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_SHIFT) & SYSCTL_POWER_STATUS_FLAG_MASK)
291 #define SYSCTL_POWER_STATUS_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_MASK) >> SYSCTL_POWER_STATUS_FLAG_SHIFT)
292 
293 /*
294  * FLAG_WAKE (RW)
295  *
296  * flag represents wakeup power cycle happened from last clear of this bit
297  * 0: power domain did not edurance wakeup power cycle since last clear of this bit
298  * 1: power domain enduranced wakeup power cycle since last clear of this bit
299  */
300 #define SYSCTL_POWER_STATUS_FLAG_WAKE_MASK (0x40000000UL)
301 #define SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT (30U)
302 #define SYSCTL_POWER_STATUS_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK)
303 #define SYSCTL_POWER_STATUS_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK) >> SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT)
304 
305 /*
306  * LF_DISABLE (RO)
307  *
308  * low fanout power switch disable
309  * 0: low fanout power switches are turned on
310  * 1: low fanout power switches are truned off
311  */
312 #define SYSCTL_POWER_STATUS_LF_DISABLE_MASK (0x1000U)
313 #define SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT (12U)
314 #define SYSCTL_POWER_STATUS_LF_DISABLE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_DISABLE_MASK) >> SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT)
315 
316 /*
317  * LF_ACK (RO)
318  *
319  * low fanout power switch feedback
320  * 0: low fanout power switches are turned on
321  * 1: low fanout power switches are truned off
322  */
323 #define SYSCTL_POWER_STATUS_LF_ACK_MASK (0x100U)
324 #define SYSCTL_POWER_STATUS_LF_ACK_SHIFT (8U)
325 #define SYSCTL_POWER_STATUS_LF_ACK_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_ACK_MASK) >> SYSCTL_POWER_STATUS_LF_ACK_SHIFT)
326 
327 /* Bitfield definition for register of struct array POWER: LF_WAIT */
328 /*
329  * WAIT (RW)
330  *
331  * wait time for low fan out power switch turn on, default value is 255
332  * 0: 0 clock cycle
333  * 1: 1 clock cycles
334  * . . .
335  * clock cycles count on 24MHz
336  */
337 #define SYSCTL_POWER_LF_WAIT_WAIT_MASK (0xFFFFFUL)
338 #define SYSCTL_POWER_LF_WAIT_WAIT_SHIFT (0U)
339 #define SYSCTL_POWER_LF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_LF_WAIT_WAIT_MASK)
340 #define SYSCTL_POWER_LF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_LF_WAIT_WAIT_MASK) >> SYSCTL_POWER_LF_WAIT_WAIT_SHIFT)
341 
342 /* Bitfield definition for register of struct array POWER: OFF_WAIT */
343 /*
344  * WAIT (RW)
345  *
346  * wait time for power switch turn off, default value is 15
347  * 0: 0 clock cycle
348  * 1: 1 clock cycles
349  * . . .
350  * clock cycles count on 24MHz
351  */
352 #define SYSCTL_POWER_OFF_WAIT_WAIT_MASK (0xFFFFFUL)
353 #define SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT (0U)
354 #define SYSCTL_POWER_OFF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK)
355 #define SYSCTL_POWER_OFF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK) >> SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT)
356 
357 /* Bitfield definition for register of struct array RESET: CONTROL */
358 /*
359  * FLAG (RW)
360  *
361  * flag represents reset happened from last clear of this bit
362  * 0: domain did not edurance reset cycle since last clear of this bit
363  * 1: domain enduranced reset cycle since last clear of this bit
364  */
365 #define SYSCTL_RESET_CONTROL_FLAG_MASK (0x80000000UL)
366 #define SYSCTL_RESET_CONTROL_FLAG_SHIFT (31U)
367 #define SYSCTL_RESET_CONTROL_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_MASK)
368 #define SYSCTL_RESET_CONTROL_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_MASK) >> SYSCTL_RESET_CONTROL_FLAG_SHIFT)
369 
370 /*
371  * FLAG_WAKE (RW)
372  *
373  * flag represents wakeup reset happened from last clear of this bit
374  * 0: domain did not edurance wakeup reset cycle since last clear of this bit
375  * 1: domain enduranced wakeup reset cycle since last clear of this bit
376  */
377 #define SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK (0x40000000UL)
378 #define SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT (30U)
379 #define SYSCTL_RESET_CONTROL_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK)
380 #define SYSCTL_RESET_CONTROL_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK) >> SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT)
381 
382 /*
383  * HOLD (RW)
384  *
385  * perform reset and hold in reset, until ths bit cleared by software
386  * 0: reset is released for function
387  * 1: reset is assert and hold
388  */
389 #define SYSCTL_RESET_CONTROL_HOLD_MASK (0x10U)
390 #define SYSCTL_RESET_CONTROL_HOLD_SHIFT (4U)
391 #define SYSCTL_RESET_CONTROL_HOLD_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_HOLD_SHIFT) & SYSCTL_RESET_CONTROL_HOLD_MASK)
392 #define SYSCTL_RESET_CONTROL_HOLD_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_HOLD_MASK) >> SYSCTL_RESET_CONTROL_HOLD_SHIFT)
393 
394 /*
395  * RESET (RW)
396  *
397  * perform reset and release imediately
398  * 0: reset is released
399  * 1 reset is asserted and will release automatically
400  */
401 #define SYSCTL_RESET_CONTROL_RESET_MASK (0x1U)
402 #define SYSCTL_RESET_CONTROL_RESET_SHIFT (0U)
403 #define SYSCTL_RESET_CONTROL_RESET_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_RESET_SHIFT) & SYSCTL_RESET_CONTROL_RESET_MASK)
404 #define SYSCTL_RESET_CONTROL_RESET_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_RESET_MASK) >> SYSCTL_RESET_CONTROL_RESET_SHIFT)
405 
406 /* Bitfield definition for register of struct array RESET: CONFIG */
407 /*
408  * PRE_WAIT (RW)
409  *
410  * wait cycle numbers before assert reset
411  * 0: wait 0 cycle
412  * 1: wait 1 cycles
413  * . . .
414  * Note, clock cycle is base on 24M
415  */
416 #define SYSCTL_RESET_CONFIG_PRE_WAIT_MASK (0xFF0000UL)
417 #define SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT (16U)
418 #define SYSCTL_RESET_CONFIG_PRE_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK)
419 #define SYSCTL_RESET_CONFIG_PRE_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK) >> SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT)
420 
421 /*
422  * RSTCLK_NUM (RW)
423  *
424  * reset clock number(must be even number)
425  * 0: 0 cycle
426  * 1: 0 cycles
427  * 2: 2 cycles
428  * 3: 2 cycles
429  * . . .
430  * Note, clock cycle is base on 24M
431  */
432 #define SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK (0xFF00U)
433 #define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT (8U)
434 #define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK)
435 #define SYSCTL_RESET_CONFIG_RSTCLK_NUM_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK) >> SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT)
436 
437 /*
438  * POST_WAIT (RW)
439  *
440  * time guard band for reset release
441  * 0: wait 0 cycle
442  * 1: wait 1 cycles
443  * . . .
444  * Note, clock cycle is base on 24M
445  */
446 #define SYSCTL_RESET_CONFIG_POST_WAIT_MASK (0xFFU)
447 #define SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT (0U)
448 #define SYSCTL_RESET_CONFIG_POST_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK)
449 #define SYSCTL_RESET_CONFIG_POST_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK) >> SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT)
450 
451 /* Bitfield definition for register of struct array RESET: COUNTER */
452 /*
453  * COUNTER (RW)
454  *
455  * self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset
456  * 0: wait 0 cycle
457  * 1: wait 1 cycles
458  * . . .
459  * Note, clock cycle is base on 24M
460  */
461 #define SYSCTL_RESET_COUNTER_COUNTER_MASK (0xFFFFFUL)
462 #define SYSCTL_RESET_COUNTER_COUNTER_SHIFT (0U)
463 #define SYSCTL_RESET_COUNTER_COUNTER_SET(x) (((uint32_t)(x) << SYSCTL_RESET_COUNTER_COUNTER_SHIFT) & SYSCTL_RESET_COUNTER_COUNTER_MASK)
464 #define SYSCTL_RESET_COUNTER_COUNTER_GET(x) (((uint32_t)(x) & SYSCTL_RESET_COUNTER_COUNTER_MASK) >> SYSCTL_RESET_COUNTER_COUNTER_SHIFT)
465 
466 /* Bitfield definition for register array: CLOCK_CPU */
467 /*
468  * GLB_BUSY (RO)
469  *
470  * global busy
471  * 0: no changes pending to any clock
472  * 1: any of nodes is changing status
473  */
474 #define SYSCTL_CLOCK_CPU_GLB_BUSY_MASK (0x80000000UL)
475 #define SYSCTL_CLOCK_CPU_GLB_BUSY_SHIFT (31U)
476 #define SYSCTL_CLOCK_CPU_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_GLB_BUSY_MASK) >> SYSCTL_CLOCK_CPU_GLB_BUSY_SHIFT)
477 
478 /*
479  * LOC_BUSY (RO)
480  *
481  * local busy
482  * 0: a change is pending for current node
483  * 1: current node is changing status
484  */
485 #define SYSCTL_CLOCK_CPU_LOC_BUSY_MASK (0x40000000UL)
486 #define SYSCTL_CLOCK_CPU_LOC_BUSY_SHIFT (30U)
487 #define SYSCTL_CLOCK_CPU_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_LOC_BUSY_MASK) >> SYSCTL_CLOCK_CPU_LOC_BUSY_SHIFT)
488 
489 /*
490  * PRESERVE (RW)
491  *
492  * preserve function against global select
493  * 0: select global clock setting
494  * 1: not select global clock setting
495  */
496 #define SYSCTL_CLOCK_CPU_PRESERVE_MASK (0x10000000UL)
497 #define SYSCTL_CLOCK_CPU_PRESERVE_SHIFT (28U)
498 #define SYSCTL_CLOCK_CPU_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_PRESERVE_SHIFT) & SYSCTL_CLOCK_CPU_PRESERVE_MASK)
499 #define SYSCTL_CLOCK_CPU_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_PRESERVE_MASK) >> SYSCTL_CLOCK_CPU_PRESERVE_SHIFT)
500 
501 /*
502  * SUB1_DIV (RW)
503  *
504  * ahb bus divider, the bus clock is generated by cpu_clock/div
505  * 0: divider by 1
506  * 1: divider by 2
507  * …
508  */
509 #define SYSCTL_CLOCK_CPU_SUB1_DIV_MASK (0xF00000UL)
510 #define SYSCTL_CLOCK_CPU_SUB1_DIV_SHIFT (20U)
511 #define SYSCTL_CLOCK_CPU_SUB1_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_SUB1_DIV_SHIFT) & SYSCTL_CLOCK_CPU_SUB1_DIV_MASK)
512 #define SYSCTL_CLOCK_CPU_SUB1_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_SUB1_DIV_MASK) >> SYSCTL_CLOCK_CPU_SUB1_DIV_SHIFT)
513 
514 /*
515  * SUB0_DIV (RW)
516  *
517  * axi bus divider, the bus clock is generated by cpu_clock/div
518  * 0: divider by 1
519  * 1: divider by 2
520  * …
521  */
522 #define SYSCTL_CLOCK_CPU_SUB0_DIV_MASK (0xF0000UL)
523 #define SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT (16U)
524 #define SYSCTL_CLOCK_CPU_SUB0_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT) & SYSCTL_CLOCK_CPU_SUB0_DIV_MASK)
525 #define SYSCTL_CLOCK_CPU_SUB0_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_SUB0_DIV_MASK) >> SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT)
526 
527 /*
528  * MUX (RW)
529  *
530  * current mux in clock component
531  * 0:osc0_clk0
532  * 1:pll0_clk0
533  * 2:pll0_clk1
534  * 3:pll0_clk2
535  * 4:pll1_clk0
536  * 5:pll1_clk1
537  * 6:pll2_clk0
538  * 7:pll2_clk1
539  */
540 #define SYSCTL_CLOCK_CPU_MUX_MASK (0xF00U)
541 #define SYSCTL_CLOCK_CPU_MUX_SHIFT (8U)
542 #define SYSCTL_CLOCK_CPU_MUX_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_MUX_SHIFT) & SYSCTL_CLOCK_CPU_MUX_MASK)
543 #define SYSCTL_CLOCK_CPU_MUX_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_MUX_MASK) >> SYSCTL_CLOCK_CPU_MUX_SHIFT)
544 
545 /*
546  * DIV (RW)
547  *
548  * clock divider
549  * 0: divider by 1
550  * 1: divider by 2
551  * 2: divider by 3
552  * . . .
553  * 255: divider by 256
554  */
555 #define SYSCTL_CLOCK_CPU_DIV_MASK (0xFFU)
556 #define SYSCTL_CLOCK_CPU_DIV_SHIFT (0U)
557 #define SYSCTL_CLOCK_CPU_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_DIV_SHIFT) & SYSCTL_CLOCK_CPU_DIV_MASK)
558 #define SYSCTL_CLOCK_CPU_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_DIV_MASK) >> SYSCTL_CLOCK_CPU_DIV_SHIFT)
559 
560 /* Bitfield definition for register array: CLOCK */
561 /*
562  * GLB_BUSY (RO)
563  *
564  * global busy
565  * 0: no changes pending to any clock
566  * 1: any of nodes is changing status
567  */
568 #define SYSCTL_CLOCK_GLB_BUSY_MASK (0x80000000UL)
569 #define SYSCTL_CLOCK_GLB_BUSY_SHIFT (31U)
570 #define SYSCTL_CLOCK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_GLB_BUSY_MASK) >> SYSCTL_CLOCK_GLB_BUSY_SHIFT)
571 
572 /*
573  * LOC_BUSY (RO)
574  *
575  * local busy
576  * 0: a change is pending for current node
577  * 1: current node is changing status
578  */
579 #define SYSCTL_CLOCK_LOC_BUSY_MASK (0x40000000UL)
580 #define SYSCTL_CLOCK_LOC_BUSY_SHIFT (30U)
581 #define SYSCTL_CLOCK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_LOC_BUSY_MASK) >> SYSCTL_CLOCK_LOC_BUSY_SHIFT)
582 
583 /*
584  * PRESERVE (RW)
585  *
586  * preserve function against global select
587  * 0: select global clock setting
588  * 1: not select global clock setting
589  */
590 #define SYSCTL_CLOCK_PRESERVE_MASK (0x10000000UL)
591 #define SYSCTL_CLOCK_PRESERVE_SHIFT (28U)
592 #define SYSCTL_CLOCK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_PRESERVE_SHIFT) & SYSCTL_CLOCK_PRESERVE_MASK)
593 #define SYSCTL_CLOCK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_PRESERVE_MASK) >> SYSCTL_CLOCK_PRESERVE_SHIFT)
594 
595 /*
596  * MUX (RW)
597  *
598  * current mux in clock component
599  * 0:osc0_clk0
600  * 1:pll0_clk0
601  * 2:pll0_clk1
602  * 3:pll0_clk2
603  * 4:pll1_clk0
604  * 5:pll1_clk1
605  * 6:pll2_clk0
606  * 7:pll2_clk1
607  */
608 #define SYSCTL_CLOCK_MUX_MASK (0xF00U)
609 #define SYSCTL_CLOCK_MUX_SHIFT (8U)
610 #define SYSCTL_CLOCK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_MUX_SHIFT) & SYSCTL_CLOCK_MUX_MASK)
611 #define SYSCTL_CLOCK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_MUX_MASK) >> SYSCTL_CLOCK_MUX_SHIFT)
612 
613 /*
614  * DIV (RW)
615  *
616  * clock divider
617  * 0: divider by 1
618  * 1: divider by 2
619  * 2: divider by 3
620  * . . .
621  * 255: divider by 256
622  */
623 #define SYSCTL_CLOCK_DIV_MASK (0xFFU)
624 #define SYSCTL_CLOCK_DIV_SHIFT (0U)
625 #define SYSCTL_CLOCK_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_DIV_SHIFT) & SYSCTL_CLOCK_DIV_MASK)
626 #define SYSCTL_CLOCK_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_DIV_MASK) >> SYSCTL_CLOCK_DIV_SHIFT)
627 
628 /* Bitfield definition for register array: ADCCLK */
629 /*
630  * GLB_BUSY (RO)
631  *
632  * global busy
633  * 0: no changes pending to any clock
634  * 1: any of nodes is changing status
635  */
636 #define SYSCTL_ADCCLK_GLB_BUSY_MASK (0x80000000UL)
637 #define SYSCTL_ADCCLK_GLB_BUSY_SHIFT (31U)
638 #define SYSCTL_ADCCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_GLB_BUSY_MASK) >> SYSCTL_ADCCLK_GLB_BUSY_SHIFT)
639 
640 /*
641  * LOC_BUSY (RO)
642  *
643  * local busy
644  * 0: a change is pending for current node
645  * 1: current node is changing status
646  */
647 #define SYSCTL_ADCCLK_LOC_BUSY_MASK (0x40000000UL)
648 #define SYSCTL_ADCCLK_LOC_BUSY_SHIFT (30U)
649 #define SYSCTL_ADCCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_LOC_BUSY_MASK) >> SYSCTL_ADCCLK_LOC_BUSY_SHIFT)
650 
651 /*
652  * PRESERVE (RW)
653  *
654  * preserve function against global select
655  * 0: select global clock setting
656  * 1: not select global clock setting
657  */
658 #define SYSCTL_ADCCLK_PRESERVE_MASK (0x10000000UL)
659 #define SYSCTL_ADCCLK_PRESERVE_SHIFT (28U)
660 #define SYSCTL_ADCCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_PRESERVE_SHIFT) & SYSCTL_ADCCLK_PRESERVE_MASK)
661 #define SYSCTL_ADCCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_PRESERVE_MASK) >> SYSCTL_ADCCLK_PRESERVE_SHIFT)
662 
663 /*
664  * MUX (RW)
665  *
666  * current mux
667  * 0: ana clock N
668  * 1: ahb clock
669  */
670 #define SYSCTL_ADCCLK_MUX_MASK (0x100U)
671 #define SYSCTL_ADCCLK_MUX_SHIFT (8U)
672 #define SYSCTL_ADCCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_MUX_SHIFT) & SYSCTL_ADCCLK_MUX_MASK)
673 #define SYSCTL_ADCCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_MUX_MASK) >> SYSCTL_ADCCLK_MUX_SHIFT)
674 
675 /* Bitfield definition for register array: DACCLK */
676 /*
677  * GLB_BUSY (RO)
678  *
679  * global busy
680  * 0: no changes pending to any clock
681  * 1: any of nodes is changing status
682  */
683 #define SYSCTL_DACCLK_GLB_BUSY_MASK (0x80000000UL)
684 #define SYSCTL_DACCLK_GLB_BUSY_SHIFT (31U)
685 #define SYSCTL_DACCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_GLB_BUSY_MASK) >> SYSCTL_DACCLK_GLB_BUSY_SHIFT)
686 
687 /*
688  * LOC_BUSY (RO)
689  *
690  * local busy
691  * 0: a change is pending for current node
692  * 1: current node is changing status
693  */
694 #define SYSCTL_DACCLK_LOC_BUSY_MASK (0x40000000UL)
695 #define SYSCTL_DACCLK_LOC_BUSY_SHIFT (30U)
696 #define SYSCTL_DACCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_LOC_BUSY_MASK) >> SYSCTL_DACCLK_LOC_BUSY_SHIFT)
697 
698 /*
699  * PRESERVE (RW)
700  *
701  * preserve function against global select
702  * 0: select global clock setting
703  * 1: not select global clock setting
704  */
705 #define SYSCTL_DACCLK_PRESERVE_MASK (0x10000000UL)
706 #define SYSCTL_DACCLK_PRESERVE_SHIFT (28U)
707 #define SYSCTL_DACCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_DACCLK_PRESERVE_SHIFT) & SYSCTL_DACCLK_PRESERVE_MASK)
708 #define SYSCTL_DACCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_PRESERVE_MASK) >> SYSCTL_DACCLK_PRESERVE_SHIFT)
709 
710 /*
711  * MUX (RW)
712  *
713  * current mux
714  * 0: ana clock N
715  * 1: ahb clock
716  */
717 #define SYSCTL_DACCLK_MUX_MASK (0x100U)
718 #define SYSCTL_DACCLK_MUX_SHIFT (8U)
719 #define SYSCTL_DACCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_DACCLK_MUX_SHIFT) & SYSCTL_DACCLK_MUX_MASK)
720 #define SYSCTL_DACCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_MUX_MASK) >> SYSCTL_DACCLK_MUX_SHIFT)
721 
722 /* Bitfield definition for register array: I2SCLK */
723 /*
724  * GLB_BUSY (RO)
725  *
726  * global busy
727  * 0: no changes pending to any clock
728  * 1: any of nodes is changing status
729  */
730 #define SYSCTL_I2SCLK_GLB_BUSY_MASK (0x80000000UL)
731 #define SYSCTL_I2SCLK_GLB_BUSY_SHIFT (31U)
732 #define SYSCTL_I2SCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_GLB_BUSY_MASK) >> SYSCTL_I2SCLK_GLB_BUSY_SHIFT)
733 
734 /*
735  * LOC_BUSY (RO)
736  *
737  * local busy
738  * 0: a change is pending for current node
739  * 1: current node is changing status
740  */
741 #define SYSCTL_I2SCLK_LOC_BUSY_MASK (0x40000000UL)
742 #define SYSCTL_I2SCLK_LOC_BUSY_SHIFT (30U)
743 #define SYSCTL_I2SCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_LOC_BUSY_MASK) >> SYSCTL_I2SCLK_LOC_BUSY_SHIFT)
744 
745 /*
746  * PRESERVE (RW)
747  *
748  * preserve function against global select
749  * 0: select global clock setting
750  * 1: not select global clock setting
751  */
752 #define SYSCTL_I2SCLK_PRESERVE_MASK (0x10000000UL)
753 #define SYSCTL_I2SCLK_PRESERVE_SHIFT (28U)
754 #define SYSCTL_I2SCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_I2SCLK_PRESERVE_SHIFT) & SYSCTL_I2SCLK_PRESERVE_MASK)
755 #define SYSCTL_I2SCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_PRESERVE_MASK) >> SYSCTL_I2SCLK_PRESERVE_SHIFT)
756 
757 /*
758  * MUX (RW)
759  *
760  * current mux
761  * 0: aud clock 0
762  * 1: aud clock 0 for others , aud clock 1 for i2s0
763  */
764 #define SYSCTL_I2SCLK_MUX_MASK (0x100U)
765 #define SYSCTL_I2SCLK_MUX_SHIFT (8U)
766 #define SYSCTL_I2SCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_I2SCLK_MUX_SHIFT) & SYSCTL_I2SCLK_MUX_MASK)
767 #define SYSCTL_I2SCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_MUX_MASK) >> SYSCTL_I2SCLK_MUX_SHIFT)
768 
769 /* Bitfield definition for register: GLOBAL00 */
770 /*
771  * MUX (RW)
772  *
773  * global clock override request
774  * bit0: override to preset0
775  * bit1: override to preset1
776  * bit2: override to preset2
777  * bit3: override to preset3
778  */
779 #define SYSCTL_GLOBAL00_MUX_MASK (0xFU)
780 #define SYSCTL_GLOBAL00_MUX_SHIFT (0U)
781 #define SYSCTL_GLOBAL00_MUX_SET(x) (((uint32_t)(x) << SYSCTL_GLOBAL00_MUX_SHIFT) & SYSCTL_GLOBAL00_MUX_MASK)
782 #define SYSCTL_GLOBAL00_MUX_GET(x) (((uint32_t)(x) & SYSCTL_GLOBAL00_MUX_MASK) >> SYSCTL_GLOBAL00_MUX_SHIFT)
783 
784 /* Bitfield definition for register of struct array MONITOR: CONTROL */
785 /*
786  * VALID (RW)
787  *
788  * result is ready for read
789  * 0: not ready
790  * 1: result is ready
791  */
792 #define SYSCTL_MONITOR_CONTROL_VALID_MASK (0x80000000UL)
793 #define SYSCTL_MONITOR_CONTROL_VALID_SHIFT (31U)
794 #define SYSCTL_MONITOR_CONTROL_VALID_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_VALID_SHIFT) & SYSCTL_MONITOR_CONTROL_VALID_MASK)
795 #define SYSCTL_MONITOR_CONTROL_VALID_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_VALID_MASK) >> SYSCTL_MONITOR_CONTROL_VALID_SHIFT)
796 
797 /*
798  * DIV_BUSY (RO)
799  *
800  * divider is applying new setting
801  */
802 #define SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK (0x8000000UL)
803 #define SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT (27U)
804 #define SYSCTL_MONITOR_CONTROL_DIV_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT)
805 
806 /*
807  * OUTEN (RW)
808  *
809  * enable clock output
810  */
811 #define SYSCTL_MONITOR_CONTROL_OUTEN_MASK (0x1000000UL)
812 #define SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT (24U)
813 #define SYSCTL_MONITOR_CONTROL_OUTEN_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK)
814 #define SYSCTL_MONITOR_CONTROL_OUTEN_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK) >> SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT)
815 
816 /*
817  * DIV (RW)
818  *
819  * output divider
820  */
821 #define SYSCTL_MONITOR_CONTROL_DIV_MASK (0xFF0000UL)
822 #define SYSCTL_MONITOR_CONTROL_DIV_SHIFT (16U)
823 #define SYSCTL_MONITOR_CONTROL_DIV_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_DIV_SHIFT) & SYSCTL_MONITOR_CONTROL_DIV_MASK)
824 #define SYSCTL_MONITOR_CONTROL_DIV_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_SHIFT)
825 
826 /*
827  * HIGH (RW)
828  *
829  * clock frequency higher than upper limit
830  */
831 #define SYSCTL_MONITOR_CONTROL_HIGH_MASK (0x8000U)
832 #define SYSCTL_MONITOR_CONTROL_HIGH_SHIFT (15U)
833 #define SYSCTL_MONITOR_CONTROL_HIGH_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_HIGH_SHIFT) & SYSCTL_MONITOR_CONTROL_HIGH_MASK)
834 #define SYSCTL_MONITOR_CONTROL_HIGH_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_HIGH_MASK) >> SYSCTL_MONITOR_CONTROL_HIGH_SHIFT)
835 
836 /*
837  * LOW (RW)
838  *
839  * clock frequency lower than lower limit
840  */
841 #define SYSCTL_MONITOR_CONTROL_LOW_MASK (0x4000U)
842 #define SYSCTL_MONITOR_CONTROL_LOW_SHIFT (14U)
843 #define SYSCTL_MONITOR_CONTROL_LOW_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_LOW_SHIFT) & SYSCTL_MONITOR_CONTROL_LOW_MASK)
844 #define SYSCTL_MONITOR_CONTROL_LOW_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_LOW_MASK) >> SYSCTL_MONITOR_CONTROL_LOW_SHIFT)
845 
846 /*
847  * START (RW)
848  *
849  * start measurement
850  */
851 #define SYSCTL_MONITOR_CONTROL_START_MASK (0x1000U)
852 #define SYSCTL_MONITOR_CONTROL_START_SHIFT (12U)
853 #define SYSCTL_MONITOR_CONTROL_START_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_START_SHIFT) & SYSCTL_MONITOR_CONTROL_START_MASK)
854 #define SYSCTL_MONITOR_CONTROL_START_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_START_MASK) >> SYSCTL_MONITOR_CONTROL_START_SHIFT)
855 
856 /*
857  * MODE (RW)
858  *
859  * work mode,
860  * 0: register value will be compared to measurement
861  * 1: upper and lower value will be recordered in register
862  */
863 #define SYSCTL_MONITOR_CONTROL_MODE_MASK (0x400U)
864 #define SYSCTL_MONITOR_CONTROL_MODE_SHIFT (10U)
865 #define SYSCTL_MONITOR_CONTROL_MODE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_MODE_SHIFT) & SYSCTL_MONITOR_CONTROL_MODE_MASK)
866 #define SYSCTL_MONITOR_CONTROL_MODE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_MODE_MASK) >> SYSCTL_MONITOR_CONTROL_MODE_SHIFT)
867 
868 /*
869  * ACCURACY (RW)
870  *
871  * measurement accuracy,
872  * 0: resolution is 1kHz
873  * 1: resolution is 1Hz
874  */
875 #define SYSCTL_MONITOR_CONTROL_ACCURACY_MASK (0x200U)
876 #define SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT (9U)
877 #define SYSCTL_MONITOR_CONTROL_ACCURACY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK)
878 #define SYSCTL_MONITOR_CONTROL_ACCURACY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK) >> SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT)
879 
880 /*
881  * REFERENCE (RW)
882  *
883  * reference clock selection,
884  * 0: 32k
885  * 1: 24M
886  */
887 #define SYSCTL_MONITOR_CONTROL_REFERENCE_MASK (0x100U)
888 #define SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT (8U)
889 #define SYSCTL_MONITOR_CONTROL_REFERENCE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK)
890 #define SYSCTL_MONITOR_CONTROL_REFERENCE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK) >> SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT)
891 
892 /*
893  * SELECTION (RW)
894  *
895  * clock measurement selection
896  */
897 #define SYSCTL_MONITOR_CONTROL_SELECTION_MASK (0xFFU)
898 #define SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT (0U)
899 #define SYSCTL_MONITOR_CONTROL_SELECTION_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK)
900 #define SYSCTL_MONITOR_CONTROL_SELECTION_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK) >> SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT)
901 
902 /* Bitfield definition for register of struct array MONITOR: CURRENT */
903 /*
904  * FREQUENCY (RO)
905  *
906  * self updating measure result
907  */
908 #define SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK (0xFFFFFFFFUL)
909 #define SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT (0U)
910 #define SYSCTL_MONITOR_CURRENT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK) >> SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT)
911 
912 /* Bitfield definition for register of struct array MONITOR: LOW_LIMIT */
913 /*
914  * FREQUENCY (RW)
915  *
916  * lower frequency
917  */
918 #define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL)
919 #define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT (0U)
920 #define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK)
921 #define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT)
922 
923 /* Bitfield definition for register of struct array MONITOR: HIGH_LIMIT */
924 /*
925  * FREQUENCY (RW)
926  *
927  * upper frequency
928  */
929 #define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL)
930 #define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT (0U)
931 #define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK)
932 #define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT)
933 
934 /* Bitfield definition for register of struct array CPU: LP */
935 /*
936  * WAKE_CNT (RW)
937  *
938  * CPU0 wake up counter, counter satuated at 255, write 0x00 to clear
939  */
940 #define SYSCTL_CPU_LP_WAKE_CNT_MASK (0xFF000000UL)
941 #define SYSCTL_CPU_LP_WAKE_CNT_SHIFT (24U)
942 #define SYSCTL_CPU_LP_WAKE_CNT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_CNT_SHIFT) & SYSCTL_CPU_LP_WAKE_CNT_MASK)
943 #define SYSCTL_CPU_LP_WAKE_CNT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_CNT_MASK) >> SYSCTL_CPU_LP_WAKE_CNT_SHIFT)
944 
945 /*
946  * HALT (RW)
947  *
948  * halt request for CPU0,
949  * 0: CPU0 will start to execute after reset or receive wakeup request
950  * 1: CPU0 will not start after reset, or wakeup after WFI
951  */
952 #define SYSCTL_CPU_LP_HALT_MASK (0x10000UL)
953 #define SYSCTL_CPU_LP_HALT_SHIFT (16U)
954 #define SYSCTL_CPU_LP_HALT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_HALT_SHIFT) & SYSCTL_CPU_LP_HALT_MASK)
955 #define SYSCTL_CPU_LP_HALT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_HALT_MASK) >> SYSCTL_CPU_LP_HALT_SHIFT)
956 
957 /*
958  * WAKE (RO)
959  *
960  * CPU0 is waking up
961  * 0: CPU0 wake up not asserted
962  * 1: CPU0 wake up asserted
963  */
964 #define SYSCTL_CPU_LP_WAKE_MASK (0x2000U)
965 #define SYSCTL_CPU_LP_WAKE_SHIFT (13U)
966 #define SYSCTL_CPU_LP_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_MASK) >> SYSCTL_CPU_LP_WAKE_SHIFT)
967 
968 /*
969  * EXEC (RO)
970  *
971  * CPU0 is executing
972  * 0: CPU0 is not executing
973  * 1: CPU0 is executing
974  */
975 #define SYSCTL_CPU_LP_EXEC_MASK (0x1000U)
976 #define SYSCTL_CPU_LP_EXEC_SHIFT (12U)
977 #define SYSCTL_CPU_LP_EXEC_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_EXEC_MASK) >> SYSCTL_CPU_LP_EXEC_SHIFT)
978 
979 /*
980  * WAKE_FLAG (RW)
981  *
982  * CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit
983  * 0: CPU0 wakeup not happened
984  * 1: CPU0 wake up happened
985  */
986 #define SYSCTL_CPU_LP_WAKE_FLAG_MASK (0x400U)
987 #define SYSCTL_CPU_LP_WAKE_FLAG_SHIFT (10U)
988 #define SYSCTL_CPU_LP_WAKE_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_FLAG_SHIFT) & SYSCTL_CPU_LP_WAKE_FLAG_MASK)
989 #define SYSCTL_CPU_LP_WAKE_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_FLAG_MASK) >> SYSCTL_CPU_LP_WAKE_FLAG_SHIFT)
990 
991 /*
992  * SLEEP_FLAG (RW)
993  *
994  * CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit
995  * 0: CPU0 sleep not happened
996  * 1: CPU0 sleep happened
997  */
998 #define SYSCTL_CPU_LP_SLEEP_FLAG_MASK (0x200U)
999 #define SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT (9U)
1000 #define SYSCTL_CPU_LP_SLEEP_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK)
1001 #define SYSCTL_CPU_LP_SLEEP_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK) >> SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT)
1002 
1003 /*
1004  * RESET_FLAG (RW)
1005  *
1006  * CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit
1007  * 0: CPU0 reset not happened
1008  * 1: CPU0 reset happened
1009  */
1010 #define SYSCTL_CPU_LP_RESET_FLAG_MASK (0x100U)
1011 #define SYSCTL_CPU_LP_RESET_FLAG_SHIFT (8U)
1012 #define SYSCTL_CPU_LP_RESET_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_RESET_FLAG_SHIFT) & SYSCTL_CPU_LP_RESET_FLAG_MASK)
1013 #define SYSCTL_CPU_LP_RESET_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_RESET_FLAG_MASK) >> SYSCTL_CPU_LP_RESET_FLAG_SHIFT)
1014 
1015 /*
1016  * MODE (RW)
1017  *
1018  * Low power mode, system behavior after WFI
1019  * 00: CPU clock stop after WFI
1020  * 01: System enter low power mode after WFI
1021  * 10: Keep running after WFI
1022  * 11: reserved
1023  */
1024 #define SYSCTL_CPU_LP_MODE_MASK (0x3U)
1025 #define SYSCTL_CPU_LP_MODE_SHIFT (0U)
1026 #define SYSCTL_CPU_LP_MODE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_MODE_SHIFT) & SYSCTL_CPU_LP_MODE_MASK)
1027 #define SYSCTL_CPU_LP_MODE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_MODE_MASK) >> SYSCTL_CPU_LP_MODE_SHIFT)
1028 
1029 /* Bitfield definition for register of struct array CPU: LOCK */
1030 /*
1031  * GPR (RW)
1032  *
1033  * Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset
1034  */
1035 #define SYSCTL_CPU_LOCK_GPR_MASK (0xFFFCU)
1036 #define SYSCTL_CPU_LOCK_GPR_SHIFT (2U)
1037 #define SYSCTL_CPU_LOCK_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_GPR_SHIFT) & SYSCTL_CPU_LOCK_GPR_MASK)
1038 #define SYSCTL_CPU_LOCK_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_GPR_MASK) >> SYSCTL_CPU_LOCK_GPR_SHIFT)
1039 
1040 /*
1041  * LOCK (RW)
1042  *
1043  * Lock bit for CPU_LOCK
1044  */
1045 #define SYSCTL_CPU_LOCK_LOCK_MASK (0x2U)
1046 #define SYSCTL_CPU_LOCK_LOCK_SHIFT (1U)
1047 #define SYSCTL_CPU_LOCK_LOCK_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_LOCK_SHIFT) & SYSCTL_CPU_LOCK_LOCK_MASK)
1048 #define SYSCTL_CPU_LOCK_LOCK_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_LOCK_MASK) >> SYSCTL_CPU_LOCK_LOCK_SHIFT)
1049 
1050 /* Bitfield definition for register of struct array CPU: GPR0 */
1051 /*
1052  * GPR (RW)
1053  *
1054  * register for software to handle resume, can save resume address or status
1055  */
1056 #define SYSCTL_CPU_GPR_GPR_MASK (0xFFFFFFFFUL)
1057 #define SYSCTL_CPU_GPR_GPR_SHIFT (0U)
1058 #define SYSCTL_CPU_GPR_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_GPR_GPR_SHIFT) & SYSCTL_CPU_GPR_GPR_MASK)
1059 #define SYSCTL_CPU_GPR_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_GPR_GPR_MASK) >> SYSCTL_CPU_GPR_GPR_SHIFT)
1060 
1061 /* Bitfield definition for register of struct array CPU: STATUS0 */
1062 /*
1063  * STATUS (RO)
1064  *
1065  * IRQ values
1066  */
1067 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK (0xFFFFFFFFUL)
1068 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT (0U)
1069 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK) >> SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT)
1070 
1071 /* Bitfield definition for register of struct array CPU: ENABLE0 */
1072 /*
1073  * ENABLE (RW)
1074  *
1075  * IRQ wakeup enable
1076  */
1077 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK (0xFFFFFFFFUL)
1078 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT (0U)
1079 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK)
1080 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK) >> SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT)
1081 
1082 
1083 
1084 /* RESOURCE register group index macro definition */
1085 #define SYSCTL_RESOURCE_CPU0 (0UL)
1086 #define SYSCTL_RESOURCE_CPX0 (1UL)
1087 #define SYSCTL_RESOURCE_POW_CPU0 (21UL)
1088 #define SYSCTL_RESOURCE_RST_SOC (22UL)
1089 #define SYSCTL_RESOURCE_RST_CPU0 (23UL)
1090 #define SYSCTL_RESOURCE_CLK_SRC_XTAL (32UL)
1091 #define SYSCTL_RESOURCE_CLK_SRC_PLL0 (33UL)
1092 #define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL0 (34UL)
1093 #define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL0 (35UL)
1094 #define SYSCTL_RESOURCE_CLK_SRC_CLK2_PLL0 (36UL)
1095 #define SYSCTL_RESOURCE_CLK_SRC_PLL1 (37UL)
1096 #define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL1 (38UL)
1097 #define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL1 (39UL)
1098 #define SYSCTL_RESOURCE_CLK_SRC_PLL2 (40UL)
1099 #define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL2 (41UL)
1100 #define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL2 (42UL)
1101 #define SYSCTL_RESOURCE_CLK_SRC_PLL0_REF (43UL)
1102 #define SYSCTL_RESOURCE_CLK_SRC_PLL1_REF (44UL)
1103 #define SYSCTL_RESOURCE_CLK_SRC_PLL2_REF (45UL)
1104 #define SYSCTL_RESOURCE_CLK_TOP_CPU0 (64UL)
1105 #define SYSCTL_RESOURCE_CLK_TOP_MCT0 (65UL)
1106 #define SYSCTL_RESOURCE_CLK_TOP_FEMC (66UL)
1107 #define SYSCTL_RESOURCE_CLK_TOP_XPI0 (67UL)
1108 #define SYSCTL_RESOURCE_CLK_TOP_XPI1 (68UL)
1109 #define SYSCTL_RESOURCE_CLK_TOP_TMR0 (69UL)
1110 #define SYSCTL_RESOURCE_CLK_TOP_TMR1 (70UL)
1111 #define SYSCTL_RESOURCE_CLK_TOP_TMR2 (71UL)
1112 #define SYSCTL_RESOURCE_CLK_TOP_TMR3 (72UL)
1113 #define SYSCTL_RESOURCE_CLK_TOP_URT0 (73UL)
1114 #define SYSCTL_RESOURCE_CLK_TOP_URT1 (74UL)
1115 #define SYSCTL_RESOURCE_CLK_TOP_URT2 (75UL)
1116 #define SYSCTL_RESOURCE_CLK_TOP_URT3 (76UL)
1117 #define SYSCTL_RESOURCE_CLK_TOP_URT4 (77UL)
1118 #define SYSCTL_RESOURCE_CLK_TOP_URT5 (78UL)
1119 #define SYSCTL_RESOURCE_CLK_TOP_URT6 (79UL)
1120 #define SYSCTL_RESOURCE_CLK_TOP_URT7 (80UL)
1121 #define SYSCTL_RESOURCE_CLK_TOP_I2C0 (81UL)
1122 #define SYSCTL_RESOURCE_CLK_TOP_I2C1 (82UL)
1123 #define SYSCTL_RESOURCE_CLK_TOP_I2C2 (83UL)
1124 #define SYSCTL_RESOURCE_CLK_TOP_I2C3 (84UL)
1125 #define SYSCTL_RESOURCE_CLK_TOP_SPI0 (85UL)
1126 #define SYSCTL_RESOURCE_CLK_TOP_SPI1 (86UL)
1127 #define SYSCTL_RESOURCE_CLK_TOP_SPI2 (87UL)
1128 #define SYSCTL_RESOURCE_CLK_TOP_SPI3 (88UL)
1129 #define SYSCTL_RESOURCE_CLK_TOP_CAN0 (89UL)
1130 #define SYSCTL_RESOURCE_CLK_TOP_CAN1 (90UL)
1131 #define SYSCTL_RESOURCE_CLK_TOP_PTPC (91UL)
1132 #define SYSCTL_RESOURCE_CLK_TOP_ANA0 (92UL)
1133 #define SYSCTL_RESOURCE_CLK_TOP_ANA1 (93UL)
1134 #define SYSCTL_RESOURCE_CLK_TOP_ANA2 (94UL)
1135 #define SYSCTL_RESOURCE_CLK_TOP_ANA3 (95UL)
1136 #define SYSCTL_RESOURCE_CLK_TOP_AUD0 (96UL)
1137 #define SYSCTL_RESOURCE_CLK_TOP_AUD1 (97UL)
1138 #define SYSCTL_RESOURCE_CLK_TOP_ETH0 (98UL)
1139 #define SYSCTL_RESOURCE_CLK_TOP_PTP0 (99UL)
1140 #define SYSCTL_RESOURCE_CLK_TOP_REF0 (100UL)
1141 #define SYSCTL_RESOURCE_CLK_TOP_REF1 (101UL)
1142 #define SYSCTL_RESOURCE_CLK_TOP_NTM0 (102UL)
1143 #define SYSCTL_RESOURCE_CLK_TOP_SDC0 (103UL)
1144 #define SYSCTL_RESOURCE_CLK_TOP_ADC0 (128UL)
1145 #define SYSCTL_RESOURCE_CLK_TOP_ADC1 (129UL)
1146 #define SYSCTL_RESOURCE_CLK_TOP_ADC2 (130UL)
1147 #define SYSCTL_RESOURCE_CLK_TOP_DAC0 (131UL)
1148 #define SYSCTL_RESOURCE_CLK_TOP_I2S0 (132UL)
1149 #define SYSCTL_RESOURCE_CLK_TOP_I2S1 (133UL)
1150 #define SYSCTL_RESOURCE_AHBP (256UL)
1151 #define SYSCTL_RESOURCE_AXIS (257UL)
1152 #define SYSCTL_RESOURCE_AXIC (258UL)
1153 #define SYSCTL_RESOURCE_FEMC (259UL)
1154 #define SYSCTL_RESOURCE_ROM0 (260UL)
1155 #define SYSCTL_RESOURCE_LMM0 (261UL)
1156 #define SYSCTL_RESOURCE_RAM0 (262UL)
1157 #define SYSCTL_RESOURCE_MCT0 (263UL)
1158 #define SYSCTL_RESOURCE_XPI0 (264UL)
1159 #define SYSCTL_RESOURCE_XPI1 (265UL)
1160 #define SYSCTL_RESOURCE_SDP0 (266UL)
1161 #define SYSCTL_RESOURCE_RNG0 (267UL)
1162 #define SYSCTL_RESOURCE_KMAN (268UL)
1163 #define SYSCTL_RESOURCE_DMA0 (269UL)
1164 #define SYSCTL_RESOURCE_DMA1 (270UL)
1165 #define SYSCTL_RESOURCE_FFA0 (271UL)
1166 #define SYSCTL_RESOURCE_GPIO (272UL)
1167 #define SYSCTL_RESOURCE_MBX0 (273UL)
1168 #define SYSCTL_RESOURCE_WDG0 (274UL)
1169 #define SYSCTL_RESOURCE_WDG1 (275UL)
1170 #define SYSCTL_RESOURCE_TSNS (276UL)
1171 #define SYSCTL_RESOURCE_TMR0 (277UL)
1172 #define SYSCTL_RESOURCE_TMR1 (278UL)
1173 #define SYSCTL_RESOURCE_TMR2 (279UL)
1174 #define SYSCTL_RESOURCE_TMR3 (280UL)
1175 #define SYSCTL_RESOURCE_URT0 (281UL)
1176 #define SYSCTL_RESOURCE_URT1 (282UL)
1177 #define SYSCTL_RESOURCE_URT2 (283UL)
1178 #define SYSCTL_RESOURCE_URT3 (284UL)
1179 #define SYSCTL_RESOURCE_URT4 (285UL)
1180 #define SYSCTL_RESOURCE_URT5 (286UL)
1181 #define SYSCTL_RESOURCE_URT6 (287UL)
1182 #define SYSCTL_RESOURCE_URT7 (288UL)
1183 #define SYSCTL_RESOURCE_I2C0 (289UL)
1184 #define SYSCTL_RESOURCE_I2C1 (290UL)
1185 #define SYSCTL_RESOURCE_I2C2 (291UL)
1186 #define SYSCTL_RESOURCE_I2C3 (292UL)
1187 #define SYSCTL_RESOURCE_SPI0 (293UL)
1188 #define SYSCTL_RESOURCE_SPI1 (294UL)
1189 #define SYSCTL_RESOURCE_SPI2 (295UL)
1190 #define SYSCTL_RESOURCE_SPI3 (296UL)
1191 #define SYSCTL_RESOURCE_CAN0 (297UL)
1192 #define SYSCTL_RESOURCE_CAN1 (298UL)
1193 #define SYSCTL_RESOURCE_PTPC (299UL)
1194 #define SYSCTL_RESOURCE_ADC0 (300UL)
1195 #define SYSCTL_RESOURCE_ADC1 (301UL)
1196 #define SYSCTL_RESOURCE_ADC2 (302UL)
1197 #define SYSCTL_RESOURCE_DAC0 (303UL)
1198 #define SYSCTL_RESOURCE_ACMP (304UL)
1199 #define SYSCTL_RESOURCE_I2S0 (305UL)
1200 #define SYSCTL_RESOURCE_I2S1 (306UL)
1201 #define SYSCTL_RESOURCE_PDM0 (307UL)
1202 #define SYSCTL_RESOURCE_DAO (308UL)
1203 #define SYSCTL_RESOURCE_SYNT (309UL)
1204 #define SYSCTL_RESOURCE_MOT0 (310UL)
1205 #define SYSCTL_RESOURCE_MOT1 (311UL)
1206 #define SYSCTL_RESOURCE_ETH0 (312UL)
1207 #define SYSCTL_RESOURCE_NTM0 (313UL)
1208 #define SYSCTL_RESOURCE_SDC0 (314UL)
1209 #define SYSCTL_RESOURCE_USB0 (315UL)
1210 #define SYSCTL_RESOURCE_REF0 (316UL)
1211 #define SYSCTL_RESOURCE_REF1 (317UL)
1212 
1213 /* GROUP0 register group index macro definition */
1214 #define SYSCTL_GROUP0_LINK0 (0UL)
1215 #define SYSCTL_GROUP0_LINK1 (1UL)
1216 
1217 /* AFFILIATE register group index macro definition */
1218 #define SYSCTL_AFFILIATE_CPU0 (0UL)
1219 
1220 /* RETENTION register group index macro definition */
1221 #define SYSCTL_RETENTION_CPU0 (0UL)
1222 
1223 /* POWER register group index macro definition */
1224 #define SYSCTL_POWER_CPU0 (0UL)
1225 
1226 /* RESET register group index macro definition */
1227 #define SYSCTL_RESET_SOC (0UL)
1228 #define SYSCTL_RESET_CPU0 (1UL)
1229 
1230 /* CLOCK_CPU register group index macro definition */
1231 #define SYSCTL_CLOCK_CPU_CLK_TOP_CPU0 (0UL)
1232 
1233 /* CLOCK register group index macro definition */
1234 #define SYSCTL_CLOCK_CLK_TOP_MCT0 (0UL)
1235 #define SYSCTL_CLOCK_CLK_TOP_FEMC (1UL)
1236 #define SYSCTL_CLOCK_CLK_TOP_XPI0 (2UL)
1237 #define SYSCTL_CLOCK_CLK_TOP_XPI1 (3UL)
1238 #define SYSCTL_CLOCK_CLK_TOP_TMR0 (4UL)
1239 #define SYSCTL_CLOCK_CLK_TOP_TMR1 (5UL)
1240 #define SYSCTL_CLOCK_CLK_TOP_TMR2 (6UL)
1241 #define SYSCTL_CLOCK_CLK_TOP_TMR3 (7UL)
1242 #define SYSCTL_CLOCK_CLK_TOP_URT0 (8UL)
1243 #define SYSCTL_CLOCK_CLK_TOP_URT1 (9UL)
1244 #define SYSCTL_CLOCK_CLK_TOP_URT2 (10UL)
1245 #define SYSCTL_CLOCK_CLK_TOP_URT3 (11UL)
1246 #define SYSCTL_CLOCK_CLK_TOP_URT4 (12UL)
1247 #define SYSCTL_CLOCK_CLK_TOP_URT5 (13UL)
1248 #define SYSCTL_CLOCK_CLK_TOP_URT6 (14UL)
1249 #define SYSCTL_CLOCK_CLK_TOP_URT7 (15UL)
1250 #define SYSCTL_CLOCK_CLK_TOP_I2C0 (16UL)
1251 #define SYSCTL_CLOCK_CLK_TOP_I2C1 (17UL)
1252 #define SYSCTL_CLOCK_CLK_TOP_I2C2 (18UL)
1253 #define SYSCTL_CLOCK_CLK_TOP_I2C3 (19UL)
1254 #define SYSCTL_CLOCK_CLK_TOP_SPI0 (20UL)
1255 #define SYSCTL_CLOCK_CLK_TOP_SPI1 (21UL)
1256 #define SYSCTL_CLOCK_CLK_TOP_SPI2 (22UL)
1257 #define SYSCTL_CLOCK_CLK_TOP_SPI3 (23UL)
1258 #define SYSCTL_CLOCK_CLK_TOP_CAN0 (24UL)
1259 #define SYSCTL_CLOCK_CLK_TOP_CAN1 (25UL)
1260 #define SYSCTL_CLOCK_CLK_TOP_PTPC (26UL)
1261 #define SYSCTL_CLOCK_CLK_TOP_ANA0 (27UL)
1262 #define SYSCTL_CLOCK_CLK_TOP_ANA1 (28UL)
1263 #define SYSCTL_CLOCK_CLK_TOP_ANA2 (29UL)
1264 #define SYSCTL_CLOCK_CLK_TOP_ANA3 (30UL)
1265 #define SYSCTL_CLOCK_CLK_TOP_AUD0 (31UL)
1266 #define SYSCTL_CLOCK_CLK_TOP_AUD1 (32UL)
1267 #define SYSCTL_CLOCK_CLK_TOP_ETH0 (33UL)
1268 #define SYSCTL_CLOCK_CLK_TOP_PTP0 (34UL)
1269 #define SYSCTL_CLOCK_CLK_TOP_REF0 (35UL)
1270 #define SYSCTL_CLOCK_CLK_TOP_REF1 (36UL)
1271 #define SYSCTL_CLOCK_CLK_TOP_NTM0 (37UL)
1272 #define SYSCTL_CLOCK_CLK_TOP_SDC0 (38UL)
1273 
1274 /* ADCCLK register group index macro definition */
1275 #define SYSCTL_ADCCLK_CLK_TOP_ADC0 (0UL)
1276 #define SYSCTL_ADCCLK_CLK_TOP_ADC1 (1UL)
1277 #define SYSCTL_ADCCLK_CLK_TOP_ADC2 (2UL)
1278 
1279 /* DACCLK register group index macro definition */
1280 #define SYSCTL_DACCLK_CLK_TOP_DAC0 (0UL)
1281 
1282 /* I2SCLK register group index macro definition */
1283 #define SYSCTL_I2SCLK_CLK_TOP_I2S0 (0UL)
1284 #define SYSCTL_I2SCLK_CLK_TOP_I2S1 (1UL)
1285 
1286 /* MONITOR register group index macro definition */
1287 #define SYSCTL_MONITOR_SLICE0 (0UL)
1288 #define SYSCTL_MONITOR_SLICE1 (1UL)
1289 #define SYSCTL_MONITOR_SLICE2 (2UL)
1290 #define SYSCTL_MONITOR_SLICE3 (3UL)
1291 
1292 /* GPR register group index macro definition */
1293 #define SYSCTL_CPU_GPR_GPR0 (0UL)
1294 #define SYSCTL_CPU_GPR_GPR1 (1UL)
1295 #define SYSCTL_CPU_GPR_GPR2 (2UL)
1296 #define SYSCTL_CPU_GPR_GPR3 (3UL)
1297 #define SYSCTL_CPU_GPR_GPR4 (4UL)
1298 #define SYSCTL_CPU_GPR_GPR5 (5UL)
1299 #define SYSCTL_CPU_GPR_GPR6 (6UL)
1300 #define SYSCTL_CPU_GPR_GPR7 (7UL)
1301 #define SYSCTL_CPU_GPR_GPR8 (8UL)
1302 #define SYSCTL_CPU_GPR_GPR9 (9UL)
1303 #define SYSCTL_CPU_GPR_GPR10 (10UL)
1304 #define SYSCTL_CPU_GPR_GPR11 (11UL)
1305 #define SYSCTL_CPU_GPR_GPR12 (12UL)
1306 #define SYSCTL_CPU_GPR_GPR13 (13UL)
1307 
1308 /* WAKEUP_STATUS register group index macro definition */
1309 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS0 (0UL)
1310 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS1 (1UL)
1311 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS2 (2UL)
1312 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS3 (3UL)
1313 
1314 /* WAKEUP_ENABLE register group index macro definition */
1315 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE0 (0UL)
1316 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE1 (1UL)
1317 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE2 (2UL)
1318 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE3 (3UL)
1319 
1320 /* CPU register group index macro definition */
1321 #define SYSCTL_CPU_CPU0 (0UL)
1322 
1323 
1324 #endif /* HPM_SYSCTL_H */
SYSCTL_Type
Definition: hpm_sysctl_regs.h:12