HPM SDK
HPMicro Software Development Kit
hpm_dao_regs.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_DAO_H
10 #define HPM_DAO_H
11 
12 typedef struct {
13  __RW uint32_t CTRL; /* 0x0: Control Register */
14  __R uint8_t RESERVED0[4]; /* 0x4 - 0x7: Reserved */
15  __RW uint32_t CMD; /* 0x8: Command Register */
16  __RW uint32_t RX_CFGR; /* 0xC: Configuration Register */
17  __RW uint32_t RXSLT; /* 0x10: RX Slot Control Register */
18  __RW uint32_t HPF_MA; /* 0x14: HPF A Coef Register */
19  __RW uint32_t HPF_B; /* 0x18: HPF B Coef Register */
20 } DAO_Type;
21 
22 
23 /* Bitfield definition for register: CTRL */
24 /*
25  * HPF_EN (RW)
26  *
27  * Whether HPF is enabled. This HPF is used to filter out the DC part.
28  */
29 #define DAO_CTRL_HPF_EN_MASK (0x20000UL)
30 #define DAO_CTRL_HPF_EN_SHIFT (17U)
31 #define DAO_CTRL_HPF_EN_SET(x) (((uint32_t)(x) << DAO_CTRL_HPF_EN_SHIFT) & DAO_CTRL_HPF_EN_MASK)
32 #define DAO_CTRL_HPF_EN_GET(x) (((uint32_t)(x) & DAO_CTRL_HPF_EN_MASK) >> DAO_CTRL_HPF_EN_SHIFT)
33 
34 /*
35  * MONO (RW)
36  *
37  * Asserted to let the left and right channel output the same value.
38  */
39 #define DAO_CTRL_MONO_MASK (0x80U)
40 #define DAO_CTRL_MONO_SHIFT (7U)
41 #define DAO_CTRL_MONO_SET(x) (((uint32_t)(x) << DAO_CTRL_MONO_SHIFT) & DAO_CTRL_MONO_MASK)
42 #define DAO_CTRL_MONO_GET(x) (((uint32_t)(x) & DAO_CTRL_MONO_MASK) >> DAO_CTRL_MONO_SHIFT)
43 
44 /*
45  * RIGHT_EN (RW)
46  *
47  * Asserted to enable the right channel
48  */
49 #define DAO_CTRL_RIGHT_EN_MASK (0x40U)
50 #define DAO_CTRL_RIGHT_EN_SHIFT (6U)
51 #define DAO_CTRL_RIGHT_EN_SET(x) (((uint32_t)(x) << DAO_CTRL_RIGHT_EN_SHIFT) & DAO_CTRL_RIGHT_EN_MASK)
52 #define DAO_CTRL_RIGHT_EN_GET(x) (((uint32_t)(x) & DAO_CTRL_RIGHT_EN_MASK) >> DAO_CTRL_RIGHT_EN_SHIFT)
53 
54 /*
55  * LEFT_EN (RW)
56  *
57  * Asserted to enable the left channel
58  */
59 #define DAO_CTRL_LEFT_EN_MASK (0x20U)
60 #define DAO_CTRL_LEFT_EN_SHIFT (5U)
61 #define DAO_CTRL_LEFT_EN_SET(x) (((uint32_t)(x) << DAO_CTRL_LEFT_EN_SHIFT) & DAO_CTRL_LEFT_EN_MASK)
62 #define DAO_CTRL_LEFT_EN_GET(x) (((uint32_t)(x) & DAO_CTRL_LEFT_EN_MASK) >> DAO_CTRL_LEFT_EN_SHIFT)
63 
64 /*
65  * REMAP (RW)
66  *
67  * 1: Use remap pwm version. The remap version is a version that one pwm output is tied to zero when the input pcm signal is positive or negative
68  * 0: Don't use remap pwm version
69  */
70 #define DAO_CTRL_REMAP_MASK (0x10U)
71 #define DAO_CTRL_REMAP_SHIFT (4U)
72 #define DAO_CTRL_REMAP_SET(x) (((uint32_t)(x) << DAO_CTRL_REMAP_SHIFT) & DAO_CTRL_REMAP_MASK)
73 #define DAO_CTRL_REMAP_GET(x) (((uint32_t)(x) & DAO_CTRL_REMAP_MASK) >> DAO_CTRL_REMAP_SHIFT)
74 
75 /*
76  * INVERT (RW)
77  *
78  * all the outputs are inverted before sending to pad
79  */
80 #define DAO_CTRL_INVERT_MASK (0x8U)
81 #define DAO_CTRL_INVERT_SHIFT (3U)
82 #define DAO_CTRL_INVERT_SET(x) (((uint32_t)(x) << DAO_CTRL_INVERT_SHIFT) & DAO_CTRL_INVERT_MASK)
83 #define DAO_CTRL_INVERT_GET(x) (((uint32_t)(x) & DAO_CTRL_INVERT_MASK) >> DAO_CTRL_INVERT_SHIFT)
84 
85 /*
86  * FALSE_LEVEL (RW)
87  *
88  * the pad output in False run mode, or when the module is disabled
89  * 0: all low
90  * 1: all high
91  * 2: P-high, N-low
92  * 3. output is not enabled
93  */
94 #define DAO_CTRL_FALSE_LEVEL_MASK (0x6U)
95 #define DAO_CTRL_FALSE_LEVEL_SHIFT (1U)
96 #define DAO_CTRL_FALSE_LEVEL_SET(x) (((uint32_t)(x) << DAO_CTRL_FALSE_LEVEL_SHIFT) & DAO_CTRL_FALSE_LEVEL_MASK)
97 #define DAO_CTRL_FALSE_LEVEL_GET(x) (((uint32_t)(x) & DAO_CTRL_FALSE_LEVEL_MASK) >> DAO_CTRL_FALSE_LEVEL_SHIFT)
98 
99 /*
100  * FALSE_RUN (RW)
101  *
102  * the module continues to consume data, but all the pads are constant, thus no audio out
103  */
104 #define DAO_CTRL_FALSE_RUN_MASK (0x1U)
105 #define DAO_CTRL_FALSE_RUN_SHIFT (0U)
106 #define DAO_CTRL_FALSE_RUN_SET(x) (((uint32_t)(x) << DAO_CTRL_FALSE_RUN_SHIFT) & DAO_CTRL_FALSE_RUN_MASK)
107 #define DAO_CTRL_FALSE_RUN_GET(x) (((uint32_t)(x) & DAO_CTRL_FALSE_RUN_MASK) >> DAO_CTRL_FALSE_RUN_SHIFT)
108 
109 /* Bitfield definition for register: CMD */
110 /*
111  * SFTRST (RW)
112  *
113  * Self-clear
114  */
115 #define DAO_CMD_SFTRST_MASK (0x2U)
116 #define DAO_CMD_SFTRST_SHIFT (1U)
117 #define DAO_CMD_SFTRST_SET(x) (((uint32_t)(x) << DAO_CMD_SFTRST_SHIFT) & DAO_CMD_SFTRST_MASK)
118 #define DAO_CMD_SFTRST_GET(x) (((uint32_t)(x) & DAO_CMD_SFTRST_MASK) >> DAO_CMD_SFTRST_SHIFT)
119 
120 /*
121  * RUN (RW)
122  *
123  * Enable this module to run.
124  */
125 #define DAO_CMD_RUN_MASK (0x1U)
126 #define DAO_CMD_RUN_SHIFT (0U)
127 #define DAO_CMD_RUN_SET(x) (((uint32_t)(x) << DAO_CMD_RUN_SHIFT) & DAO_CMD_RUN_MASK)
128 #define DAO_CMD_RUN_GET(x) (((uint32_t)(x) & DAO_CMD_RUN_MASK) >> DAO_CMD_RUN_SHIFT)
129 
130 /* Bitfield definition for register: RX_CFGR */
131 /*
132  * CH_MAX (RW)
133  *
134  * CH_MAX[3:0] is the number if channels supported in TDM mode. When not in TDM mode, it must be set as 2.
135  * It must be an even number, so CH_MAX[0] is always 0.
136  * 4'h2: 2 channels
137  * 4'h4: 4 channels
138  * etc
139  */
140 #define DAO_RX_CFGR_CH_MAX_MASK (0x7C0U)
141 #define DAO_RX_CFGR_CH_MAX_SHIFT (6U)
142 #define DAO_RX_CFGR_CH_MAX_SET(x) (((uint32_t)(x) << DAO_RX_CFGR_CH_MAX_SHIFT) & DAO_RX_CFGR_CH_MAX_MASK)
143 #define DAO_RX_CFGR_CH_MAX_GET(x) (((uint32_t)(x) & DAO_RX_CFGR_CH_MAX_MASK) >> DAO_RX_CFGR_CH_MAX_SHIFT)
144 
145 /* Bitfield definition for register: RXSLT */
146 /*
147  * EN (RW)
148  *
149  * Slot enable for the channels.
150  */
151 #define DAO_RXSLT_EN_MASK (0xFFFFFFFFUL)
152 #define DAO_RXSLT_EN_SHIFT (0U)
153 #define DAO_RXSLT_EN_SET(x) (((uint32_t)(x) << DAO_RXSLT_EN_SHIFT) & DAO_RXSLT_EN_MASK)
154 #define DAO_RXSLT_EN_GET(x) (((uint32_t)(x) & DAO_RXSLT_EN_MASK) >> DAO_RXSLT_EN_SHIFT)
155 
156 /* Bitfield definition for register: HPF_MA */
157 /*
158  * COEF (RW)
159  *
160  * Composite value of coef A of the Order-1 HPF
161  */
162 #define DAO_HPF_MA_COEF_MASK (0xFFFFFFFFUL)
163 #define DAO_HPF_MA_COEF_SHIFT (0U)
164 #define DAO_HPF_MA_COEF_SET(x) (((uint32_t)(x) << DAO_HPF_MA_COEF_SHIFT) & DAO_HPF_MA_COEF_MASK)
165 #define DAO_HPF_MA_COEF_GET(x) (((uint32_t)(x) & DAO_HPF_MA_COEF_MASK) >> DAO_HPF_MA_COEF_SHIFT)
166 
167 /* Bitfield definition for register: HPF_B */
168 /*
169  * COEF (RW)
170  *
171  * coef B of the Order-1 HPF
172  */
173 #define DAO_HPF_B_COEF_MASK (0xFFFFFFFFUL)
174 #define DAO_HPF_B_COEF_SHIFT (0U)
175 #define DAO_HPF_B_COEF_SET(x) (((uint32_t)(x) << DAO_HPF_B_COEF_SHIFT) & DAO_HPF_B_COEF_MASK)
176 #define DAO_HPF_B_COEF_GET(x) (((uint32_t)(x) & DAO_HPF_B_COEF_MASK) >> DAO_HPF_B_COEF_SHIFT)
177 
178 
179 
180 
181 #endif /* HPM_DAO_H */
DAO_Type
Definition: hpm_dao_regs.h:12