HPM SDK
HPMicro Software Development Kit
hpm_sdxc_regs.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_SDXC_H
10 #define HPM_SDXC_H
11 
12 typedef struct {
13  __RW uint32_t SDMASA; /* 0x0: */
14  __RW uint32_t BLK_ATTR; /* 0x4: */
15  __RW uint32_t CMD_ARG; /* 0x8: */
16  __RW uint32_t CMD_XFER; /* 0xC: */
17  __R uint32_t RESP[4]; /* 0x10 - 0x1C: */
18  __RW uint32_t BUF_DATA; /* 0x20: */
19  __R uint32_t PSTATE; /* 0x24: */
20  __RW uint32_t PROT_CTRL; /* 0x28: */
21  __RW uint32_t SYS_CTRL; /* 0x2C: */
22  __RW uint32_t INT_STAT; /* 0x30: */
23  __RW uint32_t INT_STAT_EN; /* 0x34: */
24  __RW uint32_t INT_SIGNAL_EN; /* 0x38: */
25  __RW uint32_t AC_HOST_CTRL; /* 0x3C: */
26  __R uint32_t CAPABILITIES1; /* 0x40: */
27  __R uint32_t CAPABILITIES2; /* 0x44: */
28  __R uint32_t CURR_CAPABILITIES1; /* 0x48: */
29  __R uint32_t CURR_CAPABILITIES2; /* 0x4C: */
30  __W uint32_t FORCE_EVENT; /* 0x50: */
31  __R uint32_t ADMA_ERR_STAT; /* 0x54: */
32  __RW uint32_t ADMA_SYS_ADDR; /* 0x58: */
33  __R uint8_t RESERVED0[4]; /* 0x5C - 0x5F: Reserved */
34  __R uint16_t PRESET[11]; /* 0x60 - 0x74: */
35  __R uint8_t RESERVED1[2]; /* 0x76 - 0x77: Reserved */
36  __RW uint32_t ADMA_ID_ADDR; /* 0x78: */
37  __R uint8_t RESERVED2[106]; /* 0x7C - 0xE5: Reserved */
38  __R uint16_t P_EMBEDDED_CNTRL; /* 0xE6: */
39  __R uint16_t P_VENDOR_SPECIFIC_AREA; /* 0xE8: */
40  __R uint16_t P_VENDOR2_SPECIFIC_AREA; /* 0xEA: */
41  __R uint8_t RESERVED3[16]; /* 0xEC - 0xFB: Reserved */
42  __R uint16_t SLOT_INTR_STATUS; /* 0xFC: */
43  __R uint8_t RESERVED4[130]; /* 0xFE - 0x17F: Reserved */
44  __R uint32_t CQVER; /* 0x180: */
45  __R uint32_t CQCAP; /* 0x184: */
46  __RW uint32_t CQCFG; /* 0x188: */
47  __RW uint32_t CQCTL; /* 0x18C: */
48  __RW uint32_t CQIS; /* 0x190: */
49  __RW uint32_t CQISE; /* 0x194: */
50  __RW uint32_t CQISGE; /* 0x198: */
51  __RW uint32_t CQIC; /* 0x19C: */
52  __RW uint32_t CQTDLBA; /* 0x1A0: */
53  __R uint8_t RESERVED5[4]; /* 0x1A4 - 0x1A7: Reserved */
54  __RW uint32_t CQTDBR; /* 0x1A8: */
55  __RW uint32_t CQTCN; /* 0x1AC: */
56  __RW uint32_t CQDQS; /* 0x1B0: */
57  __RW uint32_t CQDPT; /* 0x1B4: */
58  __RW uint32_t CQTCLR; /* 0x1B8: */
59  __R uint8_t RESERVED6[4]; /* 0x1BC - 0x1BF: Reserved */
60  __RW uint32_t CQSSC1; /* 0x1C0: */
61  __RW uint32_t CQSSC2; /* 0x1C4: */
62  __R uint32_t CQCRDCT; /* 0x1C8: */
63  __R uint8_t RESERVED7[4]; /* 0x1CC - 0x1CF: Reserved */
64  __RW uint32_t CQRMEM; /* 0x1D0: */
65  __R uint32_t CQTERRI; /* 0x1D4: */
66  __R uint32_t CQCRI; /* 0x1D8: */
67  __R uint32_t CQCRA; /* 0x1DC: */
68  __R uint8_t RESERVED8[800]; /* 0x1E0 - 0x4FF: Reserved */
69  __R uint32_t MSHC_VER_ID; /* 0x500: */
70  __R uint32_t MSHC_VER_TYPE; /* 0x504: */
71  __R uint8_t RESERVED9[36]; /* 0x508 - 0x52B: Reserved */
72  __RW uint32_t EMMC_BOOT_CTRL; /* 0x52C: */
73  __R uint8_t RESERVED10[16]; /* 0x530 - 0x53F: Reserved */
74  __RW uint32_t AUTO_TUNING_CTRL; /* 0x540: */
75  __RW uint32_t AUTO_TUNING_STAT; /* 0x544: */
76 } SDXC_Type;
77 
78 
79 /* Bitfield definition for register: SDMASA */
80 /*
81  * BLOCKCNT_SDMASA (RW)
82  *
83  * 32-bit Block Count (SDMA System Address)
84  * - SDMA System Address (Host Version 4 Enable = 0): This register contains the system memory address for an SDMA transfer in the 32-bit addressing mode.
85  * When the Host Controller stops an SDMA transfer, this register points to the system address of the next contiguous data position.
86  * It can be accessed only if no transaction is executing. Reading this register during data transfers may
87  * return an invalid value.
88  * - 32-bit Block Count (Host Version 4 Enable = 1): From the Host Controller Version 4.10 specification, this register is redefined as 32-bit Block Count.
89  * The Host Controller decrements the block count of this register for every block transfer and the data transfer stops when the count reaches zero.
90  * This register must be accessed when no transaction is executing. Reading this register during data transfers may return invalid value.
91  * Following are the values for BLOCKCNT_SDMASA:
92  * - 0xFFFF_FFFF: 4G - 1 Block
93  * -
94  * - 0x0000_0002: 2 Blocks
95  * - 0x0000_0001: 1 Block
96  * - 0x0000_0000: Stop Count
97  * Note:
98  * - For Host Version 4 Enable = 0, the Host driver does not program the system address in this register while operating in ADMA mode.
99  * The system address must be programmed in the ADMA System Address register.
100  * - For Host Version 4 Enable = 0, the Host driver programs a non-zero 32-bit block count value in this register when Auto CMD23 is enabled for non-DMA and ADMA modes.
101  * Auto CMD23 cannot be used with SDMA.
102  * - This register must be programmed with a non-zero value for data transfer if the 32-bit Block count register is used instead of the 16-bit Block count register.
103  */
104 #define SDXC_SDMASA_BLOCKCNT_SDMASA_MASK (0xFFFFFFFFUL)
105 #define SDXC_SDMASA_BLOCKCNT_SDMASA_SHIFT (0U)
106 #define SDXC_SDMASA_BLOCKCNT_SDMASA_SET(x) (((uint32_t)(x) << SDXC_SDMASA_BLOCKCNT_SDMASA_SHIFT) & SDXC_SDMASA_BLOCKCNT_SDMASA_MASK)
107 #define SDXC_SDMASA_BLOCKCNT_SDMASA_GET(x) (((uint32_t)(x) & SDXC_SDMASA_BLOCKCNT_SDMASA_MASK) >> SDXC_SDMASA_BLOCKCNT_SDMASA_SHIFT)
108 
109 /* Bitfield definition for register: BLK_ATTR */
110 /*
111  * BLOCK_CNT (RW)
112  *
113  * 16-bit Block Count
114  * - If the Host Version 4 Enable bit is set 0 or the 16-bit Block Count register is set to non-zero, the 16-bit Block Count register is selected.
115  * - If the Host Version 4 Enable bit is set 1 and the 16-bit Block Count register is set to zero, the 32-bit Block Count register is selected.
116  * Following are the values for BLOCK_CNT:
117  * - 0x0: Stop Count
118  * - 0x1: 1 Block
119  * - 0x2: 2 Blocks
120  * - .
121  * - 0xFFFF: 65535 Blocks
122  * Note: For Host Version 4 Enable = 0, this register must be set to 0000h before programming the 32-bit block count register when Auto CMD23 is enabled for non-DMA and ADMA modes.
123  */
124 #define SDXC_BLK_ATTR_BLOCK_CNT_MASK (0xFFFF0000UL)
125 #define SDXC_BLK_ATTR_BLOCK_CNT_SHIFT (16U)
126 #define SDXC_BLK_ATTR_BLOCK_CNT_SET(x) (((uint32_t)(x) << SDXC_BLK_ATTR_BLOCK_CNT_SHIFT) & SDXC_BLK_ATTR_BLOCK_CNT_MASK)
127 #define SDXC_BLK_ATTR_BLOCK_CNT_GET(x) (((uint32_t)(x) & SDXC_BLK_ATTR_BLOCK_CNT_MASK) >> SDXC_BLK_ATTR_BLOCK_CNT_SHIFT)
128 
129 /*
130  * SDMA_BUF_BDARY (RW)
131  *
132  * SDMA Buffer Boundary
133  * These bits specify the size of contiguous buffer in system memory.
134  * The SDMA transfer waits at every boundary specified by these fields and the Host Controller generates the DMA interrupt to request the Host Driver to update the SDMA System Address register.
135  * Values:
136  * - 0x0 (BYTES_4K): 4K bytes SDMA Buffer Boundary
137  * - 0x1 (BYTES_8K): 8K bytes SDMA Buffer Boundary
138  * - 0x2 (BYTES_16K): 16K bytes SDMA Buffer Boundary
139  * - 0x3 (BYTES_32K): 32K bytes SDMA Buffer Boundary
140  * - 0x4 (BYTES_64K): 64K bytes SDMA Buffer Boundary
141  * - 0x5 (BYTES_128K): 128K bytes SDMA Buffer Boundary
142  * - 0x6 (BYTES_256K): 256K bytes SDMA Buffer Boundary
143  * - 0x7 (BYTES_512K): 512K bytes SDMA Buffer Boundary
144  */
145 #define SDXC_BLK_ATTR_SDMA_BUF_BDARY_MASK (0x7000U)
146 #define SDXC_BLK_ATTR_SDMA_BUF_BDARY_SHIFT (12U)
147 #define SDXC_BLK_ATTR_SDMA_BUF_BDARY_SET(x) (((uint32_t)(x) << SDXC_BLK_ATTR_SDMA_BUF_BDARY_SHIFT) & SDXC_BLK_ATTR_SDMA_BUF_BDARY_MASK)
148 #define SDXC_BLK_ATTR_SDMA_BUF_BDARY_GET(x) (((uint32_t)(x) & SDXC_BLK_ATTR_SDMA_BUF_BDARY_MASK) >> SDXC_BLK_ATTR_SDMA_BUF_BDARY_SHIFT)
149 
150 /*
151  * XFER_BLOCK_SIZE (RW)
152  *
153  * Transfer Block Size
154  * These bits specify the block size of data transfers. In case of memory, it is set to 512 bytes. It can be accessed only if no transaction is executing.
155  * Read operations during transfers may return an invalid value, and write operations are ignored. Following are the values for XFER_BLOCK_SIZE:
156  * - 0x1: 1 byte
157  * - 0x2: 2 bytes
158  * - 0x3: 3 bytes
159  * - .
160  * - 0x1FF: 511 byte
161  * - 0x200: 512 byt es
162  * - .
163  * - 0x800: 2048 bytes
164  * Note: This register must be programmed with a non-zero value for data transfer.
165  */
166 #define SDXC_BLK_ATTR_XFER_BLOCK_SIZE_MASK (0xFFFU)
167 #define SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SHIFT (0U)
168 #define SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SET(x) (((uint32_t)(x) << SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SHIFT) & SDXC_BLK_ATTR_XFER_BLOCK_SIZE_MASK)
169 #define SDXC_BLK_ATTR_XFER_BLOCK_SIZE_GET(x) (((uint32_t)(x) & SDXC_BLK_ATTR_XFER_BLOCK_SIZE_MASK) >> SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SHIFT)
170 
171 /* Bitfield definition for register: CMD_ARG */
172 /*
173  * ARGUMNET (RW)
174  *
175  * Command Argument
176  * These bits specify the SD/eMMC command argument that is specified in bits 39-8 of the Command format.
177  */
178 #define SDXC_CMD_ARG_ARGUMNET_MASK (0xFFFFFFFFUL)
179 #define SDXC_CMD_ARG_ARGUMNET_SHIFT (0U)
180 #define SDXC_CMD_ARG_ARGUMNET_SET(x) (((uint32_t)(x) << SDXC_CMD_ARG_ARGUMNET_SHIFT) & SDXC_CMD_ARG_ARGUMNET_MASK)
181 #define SDXC_CMD_ARG_ARGUMNET_GET(x) (((uint32_t)(x) & SDXC_CMD_ARG_ARGUMNET_MASK) >> SDXC_CMD_ARG_ARGUMNET_SHIFT)
182 
183 /* Bitfield definition for register: CMD_XFER */
184 /*
185  * CMD_INDEX (RW)
186  *
187  * Command Index
188  * These bits are set to the command number that is specified in bits 45-40 of the Command Format.
189  */
190 #define SDXC_CMD_XFER_CMD_INDEX_MASK (0x3F000000UL)
191 #define SDXC_CMD_XFER_CMD_INDEX_SHIFT (24U)
192 #define SDXC_CMD_XFER_CMD_INDEX_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_CMD_INDEX_SHIFT) & SDXC_CMD_XFER_CMD_INDEX_MASK)
193 #define SDXC_CMD_XFER_CMD_INDEX_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_CMD_INDEX_MASK) >> SDXC_CMD_XFER_CMD_INDEX_SHIFT)
194 
195 /*
196  * CMD_TYPE (RW)
197  *
198  * Command Type
199  * These bits indicate the command type.
200  * Note: While issuing Abort CMD using CMD12/CMD52 or reset CMD using CMD0/CMD52, CMD_TYPE field shall be set to 0x3.
201  * Values:
202  * 0x3 (ABORT_CMD): Abort
203  * 0x2 (RESUME_CMD): Resume
204  * 0x1 (SUSPEND_CMD): Suspend
205  * 0x0 (NORMAL_CMD): Normal
206  */
207 #define SDXC_CMD_XFER_CMD_TYPE_MASK (0xC00000UL)
208 #define SDXC_CMD_XFER_CMD_TYPE_SHIFT (22U)
209 #define SDXC_CMD_XFER_CMD_TYPE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_CMD_TYPE_SHIFT) & SDXC_CMD_XFER_CMD_TYPE_MASK)
210 #define SDXC_CMD_XFER_CMD_TYPE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_CMD_TYPE_MASK) >> SDXC_CMD_XFER_CMD_TYPE_SHIFT)
211 
212 /*
213  * DATA_PRESENT_SEL (RW)
214  *
215  * Data Present Select
216  * This bit is set to 1 to indicate that data is present and that the data is transferred using the DAT line. This bit is set to 0 in the following instances:
217  * Command using the CMD line
218  * Command with no data transfer but using busy signal on the DAT[0] line
219  * Resume Command
220  * Values:
221  * 0x0 (NO_DATA): No Data Present
222  * 0x1 (DATA): Data Present
223  */
224 #define SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK (0x200000UL)
225 #define SDXC_CMD_XFER_DATA_PRESENT_SEL_SHIFT (21U)
226 #define SDXC_CMD_XFER_DATA_PRESENT_SEL_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_DATA_PRESENT_SEL_SHIFT) & SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK)
227 #define SDXC_CMD_XFER_DATA_PRESENT_SEL_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK) >> SDXC_CMD_XFER_DATA_PRESENT_SEL_SHIFT)
228 
229 /*
230  * CMD_IDX_CHK_ENABLE (RW)
231  *
232  * Command Index Check Enable
233  * This bit enables the Host Controller to check the index field in the response to verify if it has the same value as the command index.
234  * If the value is not the same, it is reported as a Command Index error.
235  * Note:
236  * Index Check enable must be set to 0 for the command with no response, R2 response, R3 response and R4 response.
237  * For the tuning command, this bit must always be set to enable the index check.
238  * Values:
239  * 0x0 (DISABLED): Disable
240  * 0x1 (ENABLED): Enable
241  */
242 #define SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK (0x100000UL)
243 #define SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_SHIFT (20U)
244 #define SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_SHIFT) & SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK)
245 #define SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK) >> SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_SHIFT)
246 
247 /*
248  * CMD_CRC_CHK_ENABLE (RW)
249  *
250  * Command CRC Check Enable
251  * This bit enables the Host Controller to check the CRC field in the response. If an error is detected, it is reported as a Command CRC error.
252  * Note:
253  * CRC Check enable must be set to 0 for the command with no response, R3 response, and R4 response.
254  * For the tuning command, this bit must always be set to 1 to enable the CRC check.
255  * Values:
256  * 0x0 (DISABLED): Disable
257  * 0x1 (ENABLED): Enable
258  */
259 #define SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK (0x80000UL)
260 #define SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_SHIFT (19U)
261 #define SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_SHIFT) & SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK)
262 #define SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK) >> SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_SHIFT)
263 
264 /*
265  * SUB_CMD_FLAG (RW)
266  *
267  * Sub Command Flag
268  * This bit distinguishes between a main command and a sub command.
269  * Values:
270  * 0x0 (MAIN): Main Command
271  * 0x1 (SUB): Sub Command
272  */
273 #define SDXC_CMD_XFER_SUB_CMD_FLAG_MASK (0x40000UL)
274 #define SDXC_CMD_XFER_SUB_CMD_FLAG_SHIFT (18U)
275 #define SDXC_CMD_XFER_SUB_CMD_FLAG_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_SUB_CMD_FLAG_SHIFT) & SDXC_CMD_XFER_SUB_CMD_FLAG_MASK)
276 #define SDXC_CMD_XFER_SUB_CMD_FLAG_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_SUB_CMD_FLAG_MASK) >> SDXC_CMD_XFER_SUB_CMD_FLAG_SHIFT)
277 
278 /*
279  * RESP_TYPE_SELECT (RW)
280  *
281  * Response Type Select
282  * This bit indicates the type of response expected from the card.
283  * Values:
284  * 0x0 (NO_RESP): No Response
285  * 0x1 (RESP_LEN_136): Response Length 136
286  * 0x2 (RESP_LEN_48): Response Length 48
287  * 0x3 (RESP_LEN_48B): Response Length 48; Check Busy after response
288  */
289 #define SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK (0x30000UL)
290 #define SDXC_CMD_XFER_RESP_TYPE_SELECT_SHIFT (16U)
291 #define SDXC_CMD_XFER_RESP_TYPE_SELECT_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_RESP_TYPE_SELECT_SHIFT) & SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK)
292 #define SDXC_CMD_XFER_RESP_TYPE_SELECT_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK) >> SDXC_CMD_XFER_RESP_TYPE_SELECT_SHIFT)
293 
294 /*
295  * RESP_INT_DISABLE (RW)
296  *
297  * Response Interrupt Disable
298  * The Host Controller supports response check function to avoid overhead of response error check by the Host driver.
299  * Response types of only R1 and R5 can be checked by the Controller.
300  * If Host Driver checks the response error, set this bit to 0 and wait for Command Complete Interrupt and then check the response register.
301  * If the Host Controller checks the response error, set this bit to 1 and set the Response Error Check Enable bit to 1.
302  * The Command Complete Interrupt is disabled by this bit regardless of the Command Complete Signal Enable.
303  * Note: During tuning (when the Execute Tuning bit in the Host Control2 register is set), the Command Complete Interrupt is not generated irrespective of the Response Interrupt Disable setting.
304  * Values:
305  * - 0x0 (ENABLED): Response Interrupt is enabled
306  * - 0x1 (DISABLED): Response Interrupt is disabled
307  */
308 #define SDXC_CMD_XFER_RESP_INT_DISABLE_MASK (0x100U)
309 #define SDXC_CMD_XFER_RESP_INT_DISABLE_SHIFT (8U)
310 #define SDXC_CMD_XFER_RESP_INT_DISABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_RESP_INT_DISABLE_SHIFT) & SDXC_CMD_XFER_RESP_INT_DISABLE_MASK)
311 #define SDXC_CMD_XFER_RESP_INT_DISABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_RESP_INT_DISABLE_MASK) >> SDXC_CMD_XFER_RESP_INT_DISABLE_SHIFT)
312 
313 /*
314  * RESP_ERR_CHK_ENABLE (RW)
315  *
316  * Response Error Check Enable
317  * The Host Controller supports response check function to avoid overhead of response error check by Host driver. Response types of only R1 and R5 can be checked by the Controller.
318  * If the Host Controller checks the response error, set this bit to 1 and set Response Interrupt Disable to 1. If an error is detected, the Response Error interrupt is generated in the Error Interrupt Status register.
319  * Note:
320  * - Response error check must not be enabled for any response type other than R1 and R5.
321  * - Response check must not be enabled for the tuning command.
322  * Values:
323  * - 0x0 (DISABLED): Response Error Check is disabled
324  * - 0x1 (ENABLED): Response Error Check is enabled
325  */
326 #define SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_MASK (0x80U)
327 #define SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_SHIFT (7U)
328 #define SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_SHIFT) & SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_MASK)
329 #define SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_MASK) >> SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_SHIFT)
330 
331 /*
332  * RESP_TYPE (RW)
333  *
334  * Response Type R1/R5
335  * This bit selects either R1 or R5 as a response type when the Response Error Check is selected.
336  * Error statuses checked in R1:
337  * OUT_OF_RANGE
338  * ADDRESS_ERROR
339  * BLOCK_LEN_ERROR
340  * WP_VIOLATION
341  * CARD_IS_LOCKED
342  * COM_CRC_ERROR
343  * CARD_ECC_FAILED
344  * CC_ERROR
345  * ERROR
346  * Response Flags checked in R5:
347  * COM_CRC_ERROR
348  * ERROR
349  * FUNCTION_NUMBER
350  * OUT_OF_RANGE
351  * Values:
352  * 0x0 (RESP_R1): R1 (Memory)
353  * 0x1 (RESP_R5): R5 (SDIO)
354  */
355 #define SDXC_CMD_XFER_RESP_TYPE_MASK (0x40U)
356 #define SDXC_CMD_XFER_RESP_TYPE_SHIFT (6U)
357 #define SDXC_CMD_XFER_RESP_TYPE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_RESP_TYPE_SHIFT) & SDXC_CMD_XFER_RESP_TYPE_MASK)
358 #define SDXC_CMD_XFER_RESP_TYPE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_RESP_TYPE_MASK) >> SDXC_CMD_XFER_RESP_TYPE_SHIFT)
359 
360 /*
361  * MULTI_BLK_SEL (RW)
362  *
363  * Multi/Single Block Select
364  * This bit is set when issuing multiple-block transfer commands using the DAT line. If this bit is set to 0, it is not necessary to set the Block Count register.
365  * Values:
366  * 0x0 (SINGLE): Single Block
367  * 0x1 (MULTI): Multiple Block
368  */
369 #define SDXC_CMD_XFER_MULTI_BLK_SEL_MASK (0x20U)
370 #define SDXC_CMD_XFER_MULTI_BLK_SEL_SHIFT (5U)
371 #define SDXC_CMD_XFER_MULTI_BLK_SEL_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_MULTI_BLK_SEL_SHIFT) & SDXC_CMD_XFER_MULTI_BLK_SEL_MASK)
372 #define SDXC_CMD_XFER_MULTI_BLK_SEL_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_MULTI_BLK_SEL_MASK) >> SDXC_CMD_XFER_MULTI_BLK_SEL_SHIFT)
373 
374 /*
375  * DATA_XFER_DIR (RW)
376  *
377  * Data Transfer Direction Select
378  * This bit defines the direction of DAT line data transfers.
379  * This bit is set to 1 by the Host Driver to transfer data from the SD/eMMC card to the Host Controller and it is set to 0 for all other commands.
380  * Values:
381  * 0x1 (READ): Read (Card to Host)
382  * 0x0 (WRITE): Write (Host to Card)
383  */
384 #define SDXC_CMD_XFER_DATA_XFER_DIR_MASK (0x10U)
385 #define SDXC_CMD_XFER_DATA_XFER_DIR_SHIFT (4U)
386 #define SDXC_CMD_XFER_DATA_XFER_DIR_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_DATA_XFER_DIR_SHIFT) & SDXC_CMD_XFER_DATA_XFER_DIR_MASK)
387 #define SDXC_CMD_XFER_DATA_XFER_DIR_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_DATA_XFER_DIR_MASK) >> SDXC_CMD_XFER_DATA_XFER_DIR_SHIFT)
388 
389 /*
390  * AUTO_CMD_ENABLE (RW)
391  *
392  * Auto Command Enable
393  * This field determines use of Auto Command functions.
394  * Note: In SDIO, this field must be set as 00b (Auto Command Disabled).
395  * Values:
396  * 0x0 (AUTO_CMD_DISABLED): Auto Command Disabled
397  * 0x1 (AUTO_CMD12_ENABLED): Auto CMD12 Enable
398  * 0x2 (AUTO_CMD23_ENABLED): Auto CMD23 Enable
399  * 0x3 (AUTO_CMD_AUTO_SEL): Auto CMD Auto Sel
400  */
401 #define SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK (0xCU)
402 #define SDXC_CMD_XFER_AUTO_CMD_ENABLE_SHIFT (2U)
403 #define SDXC_CMD_XFER_AUTO_CMD_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_AUTO_CMD_ENABLE_SHIFT) & SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK)
404 #define SDXC_CMD_XFER_AUTO_CMD_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK) >> SDXC_CMD_XFER_AUTO_CMD_ENABLE_SHIFT)
405 
406 /*
407  * BLOCK_COUNT_ENABLE (RW)
408  *
409  * Block Count Enable
410  * This bit is used to enable the Block Count register, which is relevant for multiple block transfers.
411  * If this bit is set to 0, the Block Count register is disabled, which is useful in executing an infinite transfer.
412  * The Host Driver must set this bit to 0 when ADMA is used.
413  * Values:
414  * 0x1 (ENABLED): Enable
415  * 0x0 (DISABLED): Disable
416  */
417 #define SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK (0x2U)
418 #define SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_SHIFT (1U)
419 #define SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_SHIFT) & SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK)
420 #define SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK) >> SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_SHIFT)
421 
422 /*
423  * DMA_ENABLE (RW)
424  *
425  * DMA Enable
426  * This bit enables the DMA functionality. If this bit is set to 1, a DMA operation begins when the Host Driver writes to the Command register.
427  * You can select one of the DMA modes by using DMA Select in the Host Control 1 register.
428  * Values:
429  * 0x1 (ENABLED): DMA Data transfer
430  * 0x0 (DISABLED): No data transfer or Non-DMA data transfer
431  */
432 #define SDXC_CMD_XFER_DMA_ENABLE_MASK (0x1U)
433 #define SDXC_CMD_XFER_DMA_ENABLE_SHIFT (0U)
434 #define SDXC_CMD_XFER_DMA_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_DMA_ENABLE_SHIFT) & SDXC_CMD_XFER_DMA_ENABLE_MASK)
435 #define SDXC_CMD_XFER_DMA_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_DMA_ENABLE_MASK) >> SDXC_CMD_XFER_DMA_ENABLE_SHIFT)
436 
437 /* Bitfield definition for register array: RESP */
438 /*
439  * RESP01 (RO)
440  *
441  * Command Response
442  * These bits reflect 39-8 bits of SD/eMMC Response Field.
443  * Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP[RESP67] register.
444  */
445 #define SDXC_RESP_RESP01_MASK (0xFFFFFFFFUL)
446 #define SDXC_RESP_RESP01_SHIFT (0U)
447 #define SDXC_RESP_RESP01_GET(x) (((uint32_t)(x) & SDXC_RESP_RESP01_MASK) >> SDXC_RESP_RESP01_SHIFT)
448 
449 /* Bitfield definition for register: BUF_DATA */
450 /*
451  * BUF_DATA (RW)
452  *
453  * Buffer Data
454  * These bits enable access to the Host Controller packet buffer.
455  */
456 #define SDXC_BUF_DATA_BUF_DATA_MASK (0xFFFFFFFFUL)
457 #define SDXC_BUF_DATA_BUF_DATA_SHIFT (0U)
458 #define SDXC_BUF_DATA_BUF_DATA_SET(x) (((uint32_t)(x) << SDXC_BUF_DATA_BUF_DATA_SHIFT) & SDXC_BUF_DATA_BUF_DATA_MASK)
459 #define SDXC_BUF_DATA_BUF_DATA_GET(x) (((uint32_t)(x) & SDXC_BUF_DATA_BUF_DATA_MASK) >> SDXC_BUF_DATA_BUF_DATA_SHIFT)
460 
461 /* Bitfield definition for register: PSTATE */
462 /*
463  * SUB_CMD_STAT (RO)
464  *
465  * Sub Command Status
466  * This bit is used to distinguish between a main command and a sub command status.
467  * Values:
468  * 0x0 (FALSE): Main Command Status
469  * 0x1 (TRUE): Sub Command Status
470  */
471 #define SDXC_PSTATE_SUB_CMD_STAT_MASK (0x10000000UL)
472 #define SDXC_PSTATE_SUB_CMD_STAT_SHIFT (28U)
473 #define SDXC_PSTATE_SUB_CMD_STAT_GET(x) (((uint32_t)(x) & SDXC_PSTATE_SUB_CMD_STAT_MASK) >> SDXC_PSTATE_SUB_CMD_STAT_SHIFT)
474 
475 /*
476  * CMD_ISSUE_ERR (RO)
477  *
478  * Command Not Issued by Error
479  * This bit is set if a command cannot be issued after setting the command register due to an error except the Auto CMD12 error.
480  * Values:
481  * 0x0 (FALSE): No error for issuing a command
482  * 0x1 (TRUE): Command cannot be issued
483  */
484 #define SDXC_PSTATE_CMD_ISSUE_ERR_MASK (0x8000000UL)
485 #define SDXC_PSTATE_CMD_ISSUE_ERR_SHIFT (27U)
486 #define SDXC_PSTATE_CMD_ISSUE_ERR_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CMD_ISSUE_ERR_MASK) >> SDXC_PSTATE_CMD_ISSUE_ERR_SHIFT)
487 
488 /*
489  * CMD_LINE_LVL (RO)
490  *
491  * Command-Line Signal Level
492  * This bit is used to check the CMD line level to recover from errors and for debugging. These bits reflect the value of the sd_cmd_in signal.
493  */
494 #define SDXC_PSTATE_CMD_LINE_LVL_MASK (0x1000000UL)
495 #define SDXC_PSTATE_CMD_LINE_LVL_SHIFT (24U)
496 #define SDXC_PSTATE_CMD_LINE_LVL_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CMD_LINE_LVL_MASK) >> SDXC_PSTATE_CMD_LINE_LVL_SHIFT)
497 
498 /*
499  * DAT_3_0 (RO)
500  *
501  * DAT[3:0] Line Signal Level
502  * This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (lower nibble) signal.
503  */
504 #define SDXC_PSTATE_DAT_3_0_MASK (0xF00000UL)
505 #define SDXC_PSTATE_DAT_3_0_SHIFT (20U)
506 #define SDXC_PSTATE_DAT_3_0_GET(x) (((uint32_t)(x) & SDXC_PSTATE_DAT_3_0_MASK) >> SDXC_PSTATE_DAT_3_0_SHIFT)
507 
508 /*
509  * WR_PROTECT_SW_LVL (RO)
510  *
511  * Write Protect Switch Pin Level
512  * This bit is supported only for memory and combo cards. This bit reflects the synchronized value of the card_write_prot signal.
513  * Values:
514  * 0x0 (FALSE): Write protected
515  * 0x1 (TRUE): Write enabled
516  */
517 #define SDXC_PSTATE_WR_PROTECT_SW_LVL_MASK (0x80000UL)
518 #define SDXC_PSTATE_WR_PROTECT_SW_LVL_SHIFT (19U)
519 #define SDXC_PSTATE_WR_PROTECT_SW_LVL_GET(x) (((uint32_t)(x) & SDXC_PSTATE_WR_PROTECT_SW_LVL_MASK) >> SDXC_PSTATE_WR_PROTECT_SW_LVL_SHIFT)
520 
521 /*
522  * CARD_DETECT_PIN_LEVEL (RO)
523  *
524  * Card Detect Pin Level
525  * This bit reflects the inverse synchronized value of the card_detect_n signal.
526  * Values:
527  * 0x0 (FALSE): No card present
528  * 0x1 (TRUE): Card Present
529  */
530 #define SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_MASK (0x40000UL)
531 #define SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_SHIFT (18U)
532 #define SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_MASK) >> SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_SHIFT)
533 
534 /*
535  * CARD_STABLE (RO)
536  *
537  * Card Stable
538  * This bit indicates the stability of the Card Detect Pin Level. A card is not detected if this bit is set to 1 and the value of the CARD_INSERTED bit is 0.
539  * Values:
540  * 0x0 (FALSE): Reset or Debouncing
541  * 0x1 (TRUE): No Card or Inserted
542  */
543 #define SDXC_PSTATE_CARD_STABLE_MASK (0x20000UL)
544 #define SDXC_PSTATE_CARD_STABLE_SHIFT (17U)
545 #define SDXC_PSTATE_CARD_STABLE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CARD_STABLE_MASK) >> SDXC_PSTATE_CARD_STABLE_SHIFT)
546 
547 /*
548  * CARD_INSERTED (RO)
549  *
550  * Card Inserted
551  * This bit indicates whether a card has been inserted. The Host Controller debounces this signal so that Host Driver need not wait for it to stabilize.
552  * Values:
553  * 0x0 (FALSE): Reset, Debouncing, or No card
554  * 0x1 (TRUE): Card Inserted
555  */
556 #define SDXC_PSTATE_CARD_INSERTED_MASK (0x10000UL)
557 #define SDXC_PSTATE_CARD_INSERTED_SHIFT (16U)
558 #define SDXC_PSTATE_CARD_INSERTED_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CARD_INSERTED_MASK) >> SDXC_PSTATE_CARD_INSERTED_SHIFT)
559 
560 /*
561  * BUF_RD_ENABLE (RO)
562  *
563  * Buffer Read Enable
564  * This bit is used for non-DMA transfers. This bit is set if valid data exists in the Host buffer.
565  * Values:
566  * 0x0 (DISABLED): Read disable
567  * 0x1 (ENABLED): Read enable
568  */
569 #define SDXC_PSTATE_BUF_RD_ENABLE_MASK (0x800U)
570 #define SDXC_PSTATE_BUF_RD_ENABLE_SHIFT (11U)
571 #define SDXC_PSTATE_BUF_RD_ENABLE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_BUF_RD_ENABLE_MASK) >> SDXC_PSTATE_BUF_RD_ENABLE_SHIFT)
572 
573 /*
574  * BUF_WR_ENABLE (RO)
575  *
576  * Buffer Write Enable
577  * This bit is used for non-DMA transfers. This bit is set if space is available for writing data.
578  * Values:
579  * 0x0 (DISABLED): Write disable
580  * 0x1 (ENABLED): Write enable
581  */
582 #define SDXC_PSTATE_BUF_WR_ENABLE_MASK (0x400U)
583 #define SDXC_PSTATE_BUF_WR_ENABLE_SHIFT (10U)
584 #define SDXC_PSTATE_BUF_WR_ENABLE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_BUF_WR_ENABLE_MASK) >> SDXC_PSTATE_BUF_WR_ENABLE_SHIFT)
585 
586 /*
587  * RD_XFER_ACTIVE (RO)
588  *
589  * Read Transfer Active
590  * This bit indicates whether a read transfer is active for SD/eMMC mode.
591  * Values:
592  * 0x0 (INACTIVE): No valid data
593  * 0x1 (ACTIVE): Transferring data
594  */
595 #define SDXC_PSTATE_RD_XFER_ACTIVE_MASK (0x200U)
596 #define SDXC_PSTATE_RD_XFER_ACTIVE_SHIFT (9U)
597 #define SDXC_PSTATE_RD_XFER_ACTIVE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_RD_XFER_ACTIVE_MASK) >> SDXC_PSTATE_RD_XFER_ACTIVE_SHIFT)
598 
599 /*
600  * WR_XFER_ACTIVE (RO)
601  *
602  * Write Transfer Active
603  * This status indicates whether a write transfer is active for SD/eMMC mode.
604  * Values:
605  * 0x0 (INACTIVE): No valid data
606  * 0x1 (ACTIVE): Transferring data
607  */
608 #define SDXC_PSTATE_WR_XFER_ACTIVE_MASK (0x100U)
609 #define SDXC_PSTATE_WR_XFER_ACTIVE_SHIFT (8U)
610 #define SDXC_PSTATE_WR_XFER_ACTIVE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_WR_XFER_ACTIVE_MASK) >> SDXC_PSTATE_WR_XFER_ACTIVE_SHIFT)
611 
612 /*
613  * DAT_7_4 (RO)
614  *
615  * DAT[7:4] Line Signal Level
616  * This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (upper nibble) signal.
617  */
618 #define SDXC_PSTATE_DAT_7_4_MASK (0xF0U)
619 #define SDXC_PSTATE_DAT_7_4_SHIFT (4U)
620 #define SDXC_PSTATE_DAT_7_4_GET(x) (((uint32_t)(x) & SDXC_PSTATE_DAT_7_4_MASK) >> SDXC_PSTATE_DAT_7_4_SHIFT)
621 
622 /*
623  * RE_TUNE_REQ (RO)
624  *
625  * Re-Tuning Request
626  * SDXC does not generate retuning request. The software must maintain the Retuning timer.
627  */
628 #define SDXC_PSTATE_RE_TUNE_REQ_MASK (0x8U)
629 #define SDXC_PSTATE_RE_TUNE_REQ_SHIFT (3U)
630 #define SDXC_PSTATE_RE_TUNE_REQ_GET(x) (((uint32_t)(x) & SDXC_PSTATE_RE_TUNE_REQ_MASK) >> SDXC_PSTATE_RE_TUNE_REQ_SHIFT)
631 
632 /*
633  * DAT_LINE_ACTIVE (RO)
634  *
635  * DAT Line Active (
636  * This bit indicates whether one of the DAT lines on the SD/eMMC bus is in use.
637  * In the case of read transactions, this bit indicates whether a read transfer is executing on the SD/eMMC bus.
638  * In the case of write transactions, this bit indicates whether a write transfer is executing on the SD/eMMC bus.
639  * For a command with busy, this status indicates whether the command executing busy is executing on an SD or eMMC bus.
640  * Values:
641  * 0x0 (INACTIVE): DAT Line Inactive
642  * 0x1 (ACTIVE): DAT Line Active
643  */
644 #define SDXC_PSTATE_DAT_LINE_ACTIVE_MASK (0x4U)
645 #define SDXC_PSTATE_DAT_LINE_ACTIVE_SHIFT (2U)
646 #define SDXC_PSTATE_DAT_LINE_ACTIVE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_DAT_LINE_ACTIVE_MASK) >> SDXC_PSTATE_DAT_LINE_ACTIVE_SHIFT)
647 
648 /*
649  * DAT_INHIBIT (RO)
650  *
651  * Command Inhibit (DAT)
652  * This bit is generated if either DAT line active or Read transfer active is set to 1.
653  * If this bit is set to 0, it indicates that the Host Controller can issue subsequent SD/eMMC commands.
654  * Values:
655  * 0x0 (READY): Can issue command which used DAT line
656  * 0x1 (NOT_READY): Cannot issue command which used DAT line
657  */
658 #define SDXC_PSTATE_DAT_INHIBIT_MASK (0x2U)
659 #define SDXC_PSTATE_DAT_INHIBIT_SHIFT (1U)
660 #define SDXC_PSTATE_DAT_INHIBIT_GET(x) (((uint32_t)(x) & SDXC_PSTATE_DAT_INHIBIT_MASK) >> SDXC_PSTATE_DAT_INHIBIT_SHIFT)
661 
662 /*
663  * CMD_INHIBIT (RO)
664  *
665  * Command Inhibit (CMD)
666  * This bit indicates the following :
667  * If this bit is set to 0, it indicates that the CMD line is not in use and the Host controller can issue an SD/eMMC command using the CMD line.
668  * This bit is set when the command register is written. This bit is cleared when the command response is received.
669  * This bit is not cleared by the response of auto CMD12/23 but cleared by the response of read/write command.
670  * Values:
671  * 0x0 (READY): Host Controller is ready to issue a command
672  * 0x1 (NOT_READY): Host Controller is not ready to issue a command
673  */
674 #define SDXC_PSTATE_CMD_INHIBIT_MASK (0x1U)
675 #define SDXC_PSTATE_CMD_INHIBIT_SHIFT (0U)
676 #define SDXC_PSTATE_CMD_INHIBIT_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CMD_INHIBIT_MASK) >> SDXC_PSTATE_CMD_INHIBIT_SHIFT)
677 
678 /* Bitfield definition for register: PROT_CTRL */
679 /*
680  * CARD_REMOVAL (RW)
681  *
682  * Wakeup Event Enable on SD Card Removal
683  * This bit enables wakeup event through Card Removal assertion in the Normal Interrupt Status register.
684  * For the SDIO card, Wake Up Support (FN_WUS) in the Card Information Structure (CIS) register does not affect this bit.
685  * Values:
686  * 0x0 (DISABLED): Disable
687  * 0x1 (ENABLED): Enable
688  */
689 #define SDXC_PROT_CTRL_CARD_REMOVAL_MASK (0x4000000UL)
690 #define SDXC_PROT_CTRL_CARD_REMOVAL_SHIFT (26U)
691 #define SDXC_PROT_CTRL_CARD_REMOVAL_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_CARD_REMOVAL_SHIFT) & SDXC_PROT_CTRL_CARD_REMOVAL_MASK)
692 #define SDXC_PROT_CTRL_CARD_REMOVAL_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_CARD_REMOVAL_MASK) >> SDXC_PROT_CTRL_CARD_REMOVAL_SHIFT)
693 
694 /*
695  * CARD_INSERT (RW)
696  *
697  * Wakeup Event Enable on SD Card Insertion
698  * This bit enables wakeup event through Card Insertion assertion in the Normal Interrupt Status register.
699  * FN_WUS (Wake Up Support) in CIS does not affect this bit.
700  * Values:
701  * 0x0 (DISABLED): Disable
702  * 0x1 (ENABLED): Enable
703  */
704 #define SDXC_PROT_CTRL_CARD_INSERT_MASK (0x2000000UL)
705 #define SDXC_PROT_CTRL_CARD_INSERT_SHIFT (25U)
706 #define SDXC_PROT_CTRL_CARD_INSERT_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_CARD_INSERT_SHIFT) & SDXC_PROT_CTRL_CARD_INSERT_MASK)
707 #define SDXC_PROT_CTRL_CARD_INSERT_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_CARD_INSERT_MASK) >> SDXC_PROT_CTRL_CARD_INSERT_SHIFT)
708 
709 /*
710  * CARD_INT (RW)
711  *
712  * Wakeup Event Enable on Card Interrupt
713  * This bit enables wakeup event through a Card Interrupt assertion in the Normal Interrupt Status register.
714  * This bit can be set to 1 if FN_WUS (Wake Up Support) in CIS is set to 1.
715  * Values:
716  * 0x0 (DISABLED): Disable
717  * 0x1 (ENABLED): Enable
718  */
719 #define SDXC_PROT_CTRL_CARD_INT_MASK (0x1000000UL)
720 #define SDXC_PROT_CTRL_CARD_INT_SHIFT (24U)
721 #define SDXC_PROT_CTRL_CARD_INT_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_CARD_INT_SHIFT) & SDXC_PROT_CTRL_CARD_INT_MASK)
722 #define SDXC_PROT_CTRL_CARD_INT_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_CARD_INT_MASK) >> SDXC_PROT_CTRL_CARD_INT_SHIFT)
723 
724 /*
725  * INT_AT_BGAP (RW)
726  *
727  * Interrupt At Block Gap
728  * This bit is valid only in the 4-bit mode of an SDIO card and is used to select a sample point in the interrupt cycle.
729  * Setting to 1 enables interrupt detection at the block gap for a multiple block transfer.
730  * Values:
731  * 0x0 (DISABLE): Disabled
732  * 0x1 (ENABLE): Enabled
733  */
734 #define SDXC_PROT_CTRL_INT_AT_BGAP_MASK (0x80000UL)
735 #define SDXC_PROT_CTRL_INT_AT_BGAP_SHIFT (19U)
736 #define SDXC_PROT_CTRL_INT_AT_BGAP_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_INT_AT_BGAP_SHIFT) & SDXC_PROT_CTRL_INT_AT_BGAP_MASK)
737 #define SDXC_PROT_CTRL_INT_AT_BGAP_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_INT_AT_BGAP_MASK) >> SDXC_PROT_CTRL_INT_AT_BGAP_SHIFT)
738 
739 /*
740  * RD_WAIT_CTRL (RW)
741  *
742  * Read Wait Control
743  * This bit is used to enable the read wait protocol to stop read data using DAT[2] line if the card supports read wait.
744  * Otherwise, the Host Controller has to stop the card clock to hold the read data. In UHS-II mode, Read Wait is disabled.
745  * Values:
746  * 0x0 (DISABLE): Disable Read Wait Control
747  * 0x1 (ENABLE): Enable Read Wait Control
748  */
749 #define SDXC_PROT_CTRL_RD_WAIT_CTRL_MASK (0x40000UL)
750 #define SDXC_PROT_CTRL_RD_WAIT_CTRL_SHIFT (18U)
751 #define SDXC_PROT_CTRL_RD_WAIT_CTRL_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_RD_WAIT_CTRL_SHIFT) & SDXC_PROT_CTRL_RD_WAIT_CTRL_MASK)
752 #define SDXC_PROT_CTRL_RD_WAIT_CTRL_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_RD_WAIT_CTRL_MASK) >> SDXC_PROT_CTRL_RD_WAIT_CTRL_SHIFT)
753 
754 /*
755  * CONTINUE_REQ (RW)
756  *
757  * Continue Request
758  * This bit is used to restart the transaction, which was stopped using the Stop At Block Gap Request.
759  * The Host Controller automatically clears this bit when the transaction restarts.
760  * If stop at block gap request is set to 1, any write to this bit is ignored.
761  * Values:
762  * 0x0 (NO_AFFECT): No Affect
763  * 0x1 (RESTART): Restart
764  */
765 #define SDXC_PROT_CTRL_CONTINUE_REQ_MASK (0x20000UL)
766 #define SDXC_PROT_CTRL_CONTINUE_REQ_SHIFT (17U)
767 #define SDXC_PROT_CTRL_CONTINUE_REQ_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_CONTINUE_REQ_SHIFT) & SDXC_PROT_CTRL_CONTINUE_REQ_MASK)
768 #define SDXC_PROT_CTRL_CONTINUE_REQ_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_CONTINUE_REQ_MASK) >> SDXC_PROT_CTRL_CONTINUE_REQ_SHIFT)
769 
770 /*
771  * STOP_BG_REQ (RW)
772  *
773  * Stop At Block Gap Request
774  * This bit is used to stop executing read and write transactions at the next block gap for non-DMA, SDMA, and ADMA transfers.
775  * Values:
776  * 0x0 (XFER): Transfer
777  * 0x1 (STOP): Stop
778  */
779 #define SDXC_PROT_CTRL_STOP_BG_REQ_MASK (0x10000UL)
780 #define SDXC_PROT_CTRL_STOP_BG_REQ_SHIFT (16U)
781 #define SDXC_PROT_CTRL_STOP_BG_REQ_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_STOP_BG_REQ_SHIFT) & SDXC_PROT_CTRL_STOP_BG_REQ_MASK)
782 #define SDXC_PROT_CTRL_STOP_BG_REQ_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_STOP_BG_REQ_MASK) >> SDXC_PROT_CTRL_STOP_BG_REQ_SHIFT)
783 
784 /*
785  * SD_BUS_VOL_VDD1 (RW)
786  *
787  * SD Bus Voltage Select for VDD1/eMMC Bus Voltage Select for VDD
788  * These bits enable the Host Driver to select the voltage level for an SD/eMMC card.
789  * Before setting this register, the Host Driver checks the Voltage Support bits in the Capabilities register.
790  * If an unsupported voltage is selected, the Host System does not supply the SD Bus voltage.
791  * The value set in this field is available on the SDXC output signal (sd_vdd1_sel), which is used by the voltage switching circuitry.
792  * SD Bus Voltage Select options:
793  * 0x7 : 3.3V(Typical)
794  * 0x6 : 3.0V(Typical)
795  * 0x5 : 1.8V(Typical) for Embedded
796  * 0x4 : 0x0 - Reserved
797  * eMMC Bus Voltage Select options:
798  * 0x7 : 3.3V(Typical)
799  * 0x6 : 1.8V(Typical)
800  * 0x5 : 1.2V(Typical)
801  * 0x4 : 0x0 - Reserved
802  * Values:
803  * 0x7 (V_3_3): 3.3V (Typ.)
804  * 0x6 (V_3_0): 3.0V (Typ.)
805  * 0x5 (V_1_8): 1.8V (Typ.) for Embedded
806  * 0x4 (RSVD4): Reserved
807  * 0x3 (RSVD3): Reserved
808  * 0x2 (RSVD2): Reserved
809  * 0x1 (RSVD1): Reserved
810  * 0x0 (RSVD0): Reserved
811  */
812 #define SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_MASK (0xE00U)
813 #define SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SHIFT (9U)
814 #define SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SHIFT) & SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_MASK)
815 #define SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_MASK) >> SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SHIFT)
816 
817 /*
818  * SD_BUS_PWR_VDD1 (RW)
819  *
820  * SD Bus Power for VDD1
821  * This bit enables VDD1 power of the card.
822  * This setting is available on the sd_vdd1_on output of SDXC so that it can be used to control the VDD1 power supply of the card.
823  * Before setting this bit, the SD Host Driver sets the SD Bus Voltage Select bit. If the Host Controller detects a No Card state, this bit is cleared.
824  * In SD mode, if this bit is cleared, the Host Controller stops the SD Clock by clearing the SD_CLK_EN bit in the SYS_CTRL register.
825  * Values:
826  * 0x0 (OFF): Power off
827  * 0x1 (ON): Power on
828  */
829 #define SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_MASK (0x100U)
830 #define SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_SHIFT (8U)
831 #define SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_SHIFT) & SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_MASK)
832 #define SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_MASK) >> SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_SHIFT)
833 
834 /*
835  * EXT_DAT_XFER (RW)
836  *
837  * Extended Data Transfer Width
838  * This bit controls 8-bit bus width mode of embedded device.
839  * Values:
840  * 0x1 (EIGHT_BIT): 8-bit Bus Width
841  * 0x0 (DEFAULT): Bus Width is selected by the Data Transfer Width
842  */
843 #define SDXC_PROT_CTRL_EXT_DAT_XFER_MASK (0x20U)
844 #define SDXC_PROT_CTRL_EXT_DAT_XFER_SHIFT (5U)
845 #define SDXC_PROT_CTRL_EXT_DAT_XFER_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_EXT_DAT_XFER_SHIFT) & SDXC_PROT_CTRL_EXT_DAT_XFER_MASK)
846 #define SDXC_PROT_CTRL_EXT_DAT_XFER_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_EXT_DAT_XFER_MASK) >> SDXC_PROT_CTRL_EXT_DAT_XFER_SHIFT)
847 
848 /*
849  * DMA_SEL (RW)
850  *
851  * DMA Select
852  * This field is used to select the DMA type.
853  * When Host Version 4 Enable is 1 in Host Control 2 register:
854  * 0x0 : SDMA is selected
855  * 0x1 : Reserved
856  * 0x2 : ADMA2 is selected
857  * 0x3 : ADMA2 or ADMA3 is selected
858  * When Host Version 4 Enable is 0 in Host Control 2 register:
859  * 0x0 : SDMA is selected
860  * 0x1 : Reserved
861  * 0x2 : 32-bit Address ADMA2 is selected
862  * 0x3 : 64-bit Address ADMA2 is selected
863  * Values:
864  * 0x0 (SDMA): SDMA is selected
865  * 0x1 (RSVD_BIT): Reserved
866  * 0x2 (ADMA2): ADMA2 is selected
867  * 0x3 (ADMA2_3): ADMA2 or ADMA3 is selected
868  */
869 #define SDXC_PROT_CTRL_DMA_SEL_MASK (0x18U)
870 #define SDXC_PROT_CTRL_DMA_SEL_SHIFT (3U)
871 #define SDXC_PROT_CTRL_DMA_SEL_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_DMA_SEL_SHIFT) & SDXC_PROT_CTRL_DMA_SEL_MASK)
872 #define SDXC_PROT_CTRL_DMA_SEL_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_DMA_SEL_MASK) >> SDXC_PROT_CTRL_DMA_SEL_SHIFT)
873 
874 /*
875  * HIGH_SPEED_EN (RW)
876  *
877  * High Speed Enable
878  * this bit is used to determine the selection of preset value for High Speed mode.
879  * Before setting this bit, the Host Driver checks the High Speed Support in the Capabilities register.
880  * Note: SDXC always outputs the sd_cmd_out and sd_dat_out lines at the rising edge of cclk_tx clock irrespective of this bit.
881  * Values:
882  * 0x1 (HIGH_SPEED): High Speed mode
883  * 0x0 (NORMAL_SPEED): Normal Speed mode
884  */
885 #define SDXC_PROT_CTRL_HIGH_SPEED_EN_MASK (0x4U)
886 #define SDXC_PROT_CTRL_HIGH_SPEED_EN_SHIFT (2U)
887 #define SDXC_PROT_CTRL_HIGH_SPEED_EN_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_HIGH_SPEED_EN_SHIFT) & SDXC_PROT_CTRL_HIGH_SPEED_EN_MASK)
888 #define SDXC_PROT_CTRL_HIGH_SPEED_EN_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_HIGH_SPEED_EN_MASK) >> SDXC_PROT_CTRL_HIGH_SPEED_EN_SHIFT)
889 
890 /*
891  * DAT_XFER_WIDTH (RW)
892  *
893  * Data Transfer Width
894  * For SD/eMMC mode,this bit selects the data transfer width of the Host Controller.
895  * The Host Driver sets it to match the data width of the SD/eMMC card. In UHS-II mode, this bit is irrelevant.
896  * Values:
897  * 0x1 (FOUR_BIT): 4-bit mode
898  * 0x0 (ONE_BIT): 1-bit mode
899  */
900 #define SDXC_PROT_CTRL_DAT_XFER_WIDTH_MASK (0x2U)
901 #define SDXC_PROT_CTRL_DAT_XFER_WIDTH_SHIFT (1U)
902 #define SDXC_PROT_CTRL_DAT_XFER_WIDTH_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_DAT_XFER_WIDTH_SHIFT) & SDXC_PROT_CTRL_DAT_XFER_WIDTH_MASK)
903 #define SDXC_PROT_CTRL_DAT_XFER_WIDTH_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_DAT_XFER_WIDTH_MASK) >> SDXC_PROT_CTRL_DAT_XFER_WIDTH_SHIFT)
904 
905 /* Bitfield definition for register: SYS_CTRL */
906 /*
907  * SW_RST_DAT (RW)
908  *
909  * Software Reset For DAT line
910  * This bit is used in SD/eMMC mode and it resets only a part of the data circuit and the DMA circuit is also reset.
911  * The following registers and bits are cleared by this bit:
912  * Buffer Data Port register
913  * -Buffer is cleared and initialized.
914  * Present state register
915  * -Buffer Read Enable
916  * -Buffer Write Enable
917  * -Read Transfer Active
918  * -Write Transfer Active
919  * -DAT Line Active
920  * -Command Inhibit (DAT)
921  * Block Gap Control register
922  * -Continue Request
923  * -Stop At Block Gap Request
924  * Normal Interrupt status register
925  * -Buffer Read Ready
926  * -Buffer Write Ready
927  * -DMA Interrupt
928  * -Block Gap Event
929  * -Transfer Complete
930  * In UHS-II mode, this bit shall be set to 0
931  * Values:
932  * 0x0 (FALSE): Work
933  * 0x1 (TRUE): Reset
934  */
935 #define SDXC_SYS_CTRL_SW_RST_DAT_MASK (0x4000000UL)
936 #define SDXC_SYS_CTRL_SW_RST_DAT_SHIFT (26U)
937 #define SDXC_SYS_CTRL_SW_RST_DAT_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_SW_RST_DAT_SHIFT) & SDXC_SYS_CTRL_SW_RST_DAT_MASK)
938 #define SDXC_SYS_CTRL_SW_RST_DAT_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_SW_RST_DAT_MASK) >> SDXC_SYS_CTRL_SW_RST_DAT_SHIFT)
939 
940 /*
941  * SW_RST_CMD (RW)
942  *
943  * Software Reset For CMD line
944  * This bit resets only a part of the command circuit to be able to issue a command.
945  * It bit is also used to initialize a UHS-II command circuit.
946  * This reset is effective only for a command issuing circuit (including response error statuses related to Command Inhibit (CMD) control) and does not affect the data transfer circuit.
947  * Host Controller can continue data transfer even after this reset is executed while handling subcommand-response errors.
948  * The following registers and bits are cleared by this bit:
949  * Present State register : Command Inhibit (CMD) bit
950  * Normal Interrupt Status register : Command Complete bit
951  * Error Interrupt Status : Response error statuses related to Command Inhibit (CMD) bit
952  * Values:
953  * 0x0 (FALSE): Work
954  * 0x1 (TRUE): Reset
955  */
956 #define SDXC_SYS_CTRL_SW_RST_CMD_MASK (0x2000000UL)
957 #define SDXC_SYS_CTRL_SW_RST_CMD_SHIFT (25U)
958 #define SDXC_SYS_CTRL_SW_RST_CMD_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_SW_RST_CMD_SHIFT) & SDXC_SYS_CTRL_SW_RST_CMD_MASK)
959 #define SDXC_SYS_CTRL_SW_RST_CMD_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_SW_RST_CMD_MASK) >> SDXC_SYS_CTRL_SW_RST_CMD_SHIFT)
960 
961 /*
962  * SW_RST_ALL (RW)
963  *
964  * Software Reset For All
965  * This reset affects the entire Host Controller except for the card detection circuit.
966  * During its initialization, the Host Driver sets this bit to 1 to reset the Host Controller.
967  * All registers are reset except the capabilities register.
968  * If this bit is set to 1, the Host Driver must issue reset command and reinitialize the card.
969  * Values:
970  * 0x0 (FALSE): Work
971  * 0x1 (TRUE): Reset
972  */
973 #define SDXC_SYS_CTRL_SW_RST_ALL_MASK (0x1000000UL)
974 #define SDXC_SYS_CTRL_SW_RST_ALL_SHIFT (24U)
975 #define SDXC_SYS_CTRL_SW_RST_ALL_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_SW_RST_ALL_SHIFT) & SDXC_SYS_CTRL_SW_RST_ALL_MASK)
976 #define SDXC_SYS_CTRL_SW_RST_ALL_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_SW_RST_ALL_MASK) >> SDXC_SYS_CTRL_SW_RST_ALL_SHIFT)
977 
978 /*
979  * TOUT_CNT (RW)
980  *
981  * Data Timeout Counter Value.
982  * This value determines the interval by which DAT line timeouts are detected.
983  * The Timeout clock frequency is generated by dividing the base clock TMCLK value by this value.
984  * When setting this register, prevent inadvertent timeout events by clearing the Data Timeout Error Status Enable (in the Error Interrupt Status Enable register).
985  * The values for these bits are:
986  * 0xF : Reserved
987  * 0xE : TMCLK x 2^27
988  * .........
989  * 0x1 : TMCLK x 2^14
990  * 0x0 : TMCLK x 2^13
991  * Note: During a boot operating in an eMMC mode, an application must configure the boot data timeout value (approximately 1 sec) in this bit.
992  */
993 #define SDXC_SYS_CTRL_TOUT_CNT_MASK (0xF0000UL)
994 #define SDXC_SYS_CTRL_TOUT_CNT_SHIFT (16U)
995 #define SDXC_SYS_CTRL_TOUT_CNT_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_TOUT_CNT_SHIFT) & SDXC_SYS_CTRL_TOUT_CNT_MASK)
996 #define SDXC_SYS_CTRL_TOUT_CNT_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_TOUT_CNT_MASK) >> SDXC_SYS_CTRL_TOUT_CNT_SHIFT)
997 
998 /*
999  * FREQ_SEL (RW)
1000  *
1001  * SDCLK/RCLK Frequency Select
1002  * These bits are used to select the frequency of the SDCLK signal.
1003  * These bits depend on setting of Preset Value Enable in the Host Control 2 register.
1004  * If Preset Value Enable = 0, these bits are set by the Host Driver.
1005  * If Preset Value Enable = 1, these bits are automatically set to a value specified in one of the Preset Value register.
1006  * The value is reflected on the lower 8-bit of the card_clk_freq_selsignal.
1007  * 10-bit Divided Clock Mode:
1008  * 0x3FF : 1/2046 Divided clock
1009  * ..........
1010  * N : 1/2N Divided Clock
1011  * ..........
1012  * 0x002 : 1/4 Divided Clock
1013  * 0x001 : 1/2 Divided Clock
1014  * 0x000 : Base clock (10MHz - 255 MHz)
1015  * Programmable Clock Mode : Enables the Host System to select a fine grain SD clock frequency:
1016  * 0x3FF : Base clock * M /1024
1017  * ..........
1018  * N-1 : Base clock * M /N
1019  * ..........
1020  * 0x002 : Base clock * M /3
1021  * 0x001 : Base clock * M /2
1022  * 0x000 : Base clock * M
1023  */
1024 #define SDXC_SYS_CTRL_FREQ_SEL_MASK (0xFF00U)
1025 #define SDXC_SYS_CTRL_FREQ_SEL_SHIFT (8U)
1026 #define SDXC_SYS_CTRL_FREQ_SEL_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_FREQ_SEL_SHIFT) & SDXC_SYS_CTRL_FREQ_SEL_MASK)
1027 #define SDXC_SYS_CTRL_FREQ_SEL_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_FREQ_SEL_MASK) >> SDXC_SYS_CTRL_FREQ_SEL_SHIFT)
1028 
1029 /*
1030  * UPPER_FREQ_SEL (RW)
1031  *
1032  * These bits specify the upper 2 bits of 10-bit SDCLK/RCLK Frequency Select control.
1033  * The value is reflected on the upper 2 bits of the card_clk_freq_sel signal.
1034  */
1035 #define SDXC_SYS_CTRL_UPPER_FREQ_SEL_MASK (0xC0U)
1036 #define SDXC_SYS_CTRL_UPPER_FREQ_SEL_SHIFT (6U)
1037 #define SDXC_SYS_CTRL_UPPER_FREQ_SEL_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_UPPER_FREQ_SEL_SHIFT) & SDXC_SYS_CTRL_UPPER_FREQ_SEL_MASK)
1038 #define SDXC_SYS_CTRL_UPPER_FREQ_SEL_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_UPPER_FREQ_SEL_MASK) >> SDXC_SYS_CTRL_UPPER_FREQ_SEL_SHIFT)
1039 
1040 /*
1041  * CLK_GEN_SELECT (RW)
1042  *
1043  * Clock Generator Select
1044  * This bit is used to select the clock generator mode in SDCLK/RCLK Frequency Select.
1045  * If Preset Value Enable = 0, this bit is set by the Host Driver.
1046  * If Preset Value Enable = 1, this bit is automatically set to a value specified in one of the Preset Value registers.
1047  * The value is reflected on the card_clk_gen_sel signal.
1048  * Values:
1049  * 0x0 (FALSE): Divided Clock Mode
1050  * 0x1 (TRUE): Programmable Clock Mode
1051  */
1052 #define SDXC_SYS_CTRL_CLK_GEN_SELECT_MASK (0x20U)
1053 #define SDXC_SYS_CTRL_CLK_GEN_SELECT_SHIFT (5U)
1054 #define SDXC_SYS_CTRL_CLK_GEN_SELECT_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_CLK_GEN_SELECT_SHIFT) & SDXC_SYS_CTRL_CLK_GEN_SELECT_MASK)
1055 #define SDXC_SYS_CTRL_CLK_GEN_SELECT_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_CLK_GEN_SELECT_MASK) >> SDXC_SYS_CTRL_CLK_GEN_SELECT_SHIFT)
1056 
1057 /*
1058  * PLL_ENABLE (RW)
1059  *
1060  * PLL Enable
1061  * This bit is used to activate the PLL (applicable when Host Version 4 Enable = 1).
1062  * When Host Version 4 Enable = 0, INTERNAL_CLK_EN bit may be used to activate PLL. The value is reflected on the card_clk_en signal.
1063  * Note: If this bit is not used to to active the PLL when Host Version 4 Enable = 1, it is recommended to set this bit to '1' .
1064  * Values:
1065  * 0x0 (FALSE): PLL is in low power mode
1066  * 0x1 (TRUE): PLL is enabled
1067  */
1068 #define SDXC_SYS_CTRL_PLL_ENABLE_MASK (0x8U)
1069 #define SDXC_SYS_CTRL_PLL_ENABLE_SHIFT (3U)
1070 #define SDXC_SYS_CTRL_PLL_ENABLE_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_PLL_ENABLE_SHIFT) & SDXC_SYS_CTRL_PLL_ENABLE_MASK)
1071 #define SDXC_SYS_CTRL_PLL_ENABLE_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_PLL_ENABLE_MASK) >> SDXC_SYS_CTRL_PLL_ENABLE_SHIFT)
1072 
1073 /*
1074  * SD_CLK_EN (RW)
1075  *
1076  * SD/eMMC Clock Enable
1077  * This bit stops the SDCLK or RCLK when set to 0.
1078  * The SDCLK/RCLK Frequency Select bit can be changed when this bit is set to 0.
1079  * The value is reflected on the clk2card_on pin.
1080  * Values:
1081  * 0x0 (FALSE): Disable providing SDCLK/RCLK
1082  * 0x1 (TRUE): Enable providing SDCLK/RCLK
1083  */
1084 #define SDXC_SYS_CTRL_SD_CLK_EN_MASK (0x4U)
1085 #define SDXC_SYS_CTRL_SD_CLK_EN_SHIFT (2U)
1086 #define SDXC_SYS_CTRL_SD_CLK_EN_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_SD_CLK_EN_SHIFT) & SDXC_SYS_CTRL_SD_CLK_EN_MASK)
1087 #define SDXC_SYS_CTRL_SD_CLK_EN_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_SD_CLK_EN_MASK) >> SDXC_SYS_CTRL_SD_CLK_EN_SHIFT)
1088 
1089 /*
1090  * INTERNAL_CLK_STABLE (RW)
1091  *
1092  * Internal Clock Stable
1093  * This bit enables the Host Driver to check the clock stability twice after the Internal Clock Enable bit is set and after the PLL Enable bit is set.
1094  * This bit reflects the synchronized value of the intclk_stable signal after the Internal Clock Enable bit is set to 1,
1095  * and also reflects the synchronized value of the card_clk_stable signal after the PLL Enable bit is set to 1.
1096  * Values:
1097  * 0x0 (FALSE): Not Ready
1098  * 0x1 (TRUE): Ready
1099  */
1100 #define SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_MASK (0x2U)
1101 #define SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_SHIFT (1U)
1102 #define SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_SHIFT) & SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_MASK)
1103 #define SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_MASK) >> SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_SHIFT)
1104 
1105 /*
1106  * INTERNAL_CLK_EN (RW)
1107  *
1108  * Internal Clock Enable
1109  * This bit is set to 0 when the Host Driver is not using the Host Controller or the Host Controller awaits a wakeup interrupt.
1110  * The Host Controller must stop its internal clock to enter a very low power state.
1111  * However, registers can still be read and written to. The value is reflected on the intclk_en signal.
1112  * Note: If this bit is not used to control the internal clock (base clock and master clock), it is recommended to set this bit to '1' .
1113  * Values:
1114  * 0x0 (FALSE): Stop
1115  * 0x1 (TRUE): Oscillate
1116  */
1117 #define SDXC_SYS_CTRL_INTERNAL_CLK_EN_MASK (0x1U)
1118 #define SDXC_SYS_CTRL_INTERNAL_CLK_EN_SHIFT (0U)
1119 #define SDXC_SYS_CTRL_INTERNAL_CLK_EN_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_INTERNAL_CLK_EN_SHIFT) & SDXC_SYS_CTRL_INTERNAL_CLK_EN_MASK)
1120 #define SDXC_SYS_CTRL_INTERNAL_CLK_EN_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_INTERNAL_CLK_EN_MASK) >> SDXC_SYS_CTRL_INTERNAL_CLK_EN_SHIFT)
1121 
1122 /* Bitfield definition for register: INT_STAT */
1123 /*
1124  * BOOT_ACK_ERR (R/W1C)
1125  *
1126  * Boot Acknowledgment Error
1127  * This bit is set when there is a timeout for boot acknowledgement or when detecting boot ack status having a value other than 010. This is applicable only when boot acknowledgement is expected in eMMC mode.
1128  * In SD/UHS-II mode, this bit is irrelevant.
1129  */
1130 #define SDXC_INT_STAT_BOOT_ACK_ERR_MASK (0x10000000UL)
1131 #define SDXC_INT_STAT_BOOT_ACK_ERR_SHIFT (28U)
1132 #define SDXC_INT_STAT_BOOT_ACK_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_BOOT_ACK_ERR_SHIFT) & SDXC_INT_STAT_BOOT_ACK_ERR_MASK)
1133 #define SDXC_INT_STAT_BOOT_ACK_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_BOOT_ACK_ERR_MASK) >> SDXC_INT_STAT_BOOT_ACK_ERR_SHIFT)
1134 
1135 /*
1136  * RESP_ERR (R/W1C)
1137  *
1138  * Response Error
1139  * Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution.
1140  * If Response Error Check Enable is set to 1 in the Transfer Mode register, Host Controller Checks R1 or R5 response. If an error is detected in a response, this bit is set to 1.This is applicable in SD/eMMC mode.
1141  * Values:
1142  * 0x0 (FALSE): No error
1143  * 0x1 (TRUE): Error
1144  */
1145 #define SDXC_INT_STAT_RESP_ERR_MASK (0x8000000UL)
1146 #define SDXC_INT_STAT_RESP_ERR_SHIFT (27U)
1147 #define SDXC_INT_STAT_RESP_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_RESP_ERR_SHIFT) & SDXC_INT_STAT_RESP_ERR_MASK)
1148 #define SDXC_INT_STAT_RESP_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_RESP_ERR_MASK) >> SDXC_INT_STAT_RESP_ERR_SHIFT)
1149 
1150 /*
1151  * TUNING_ERR (R/W1C)
1152  *
1153  * Tuning Error
1154  * This bit is set when an unrecoverable error is detected in a tuning circuit except during the tuning procedure
1155  * (occurrence of an error during tuning procedure is indicated by Sampling Clock Select in the Host Control 2 register).
1156  * By detecting Tuning Error, Host Driver needs to abort a command executing and perform tuning.
1157  * To reset tuning circuit, Sampling Clock Select is set to 0 before executing tuning procedure.
1158  * The Tuning Error is higher priority than the other error interrupts generated during data transfer.
1159  * By detecting Tuning Error, the Host Driver must discard data transferred by a current read/write command and retry data transfer after the Host Controller retrieved from the tuning circuit error.
1160  * This is applicable in SD/eMMC mode.
1161  * Values:
1162  * 0x0 (FALSE): No error
1163  * 0x1 (TRUE): Error
1164  */
1165 #define SDXC_INT_STAT_TUNING_ERR_MASK (0x4000000UL)
1166 #define SDXC_INT_STAT_TUNING_ERR_SHIFT (26U)
1167 #define SDXC_INT_STAT_TUNING_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_TUNING_ERR_SHIFT) & SDXC_INT_STAT_TUNING_ERR_MASK)
1168 #define SDXC_INT_STAT_TUNING_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_TUNING_ERR_MASK) >> SDXC_INT_STAT_TUNING_ERR_SHIFT)
1169 
1170 /*
1171  * ADMA_ERR (R/W1C)
1172  *
1173  * ADMA Error
1174  * This bit is set when the Host Controller detects error during ADMA-based data transfer. The error could be due to following reasons:
1175  * Error response received from System bus (Master I/F)
1176  * ADMA3,ADMA2 Descriptors invalid
1177  * CQE Task or Transfer descriptors invalid
1178  * When the error occurs, the state of the ADMA is saved in the ADMA Error Status register.
1179  * In eMMC CQE mode:
1180  * The Host Controller generates this Interrupt when it detects an invalid descriptor data (Valid=0) at the ST_FDS state.
1181  * ADMA Error State in the ADMA Error Status indicates that an error has occurred in ST_FDS state.
1182  * The Host Driver may find that Valid bit is not set at the error descriptor.
1183  * Values:
1184  * 0x0 (FALSE): No error
1185  * 0x1 (TRUE): Error
1186  */
1187 #define SDXC_INT_STAT_ADMA_ERR_MASK (0x2000000UL)
1188 #define SDXC_INT_STAT_ADMA_ERR_SHIFT (25U)
1189 #define SDXC_INT_STAT_ADMA_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_ADMA_ERR_SHIFT) & SDXC_INT_STAT_ADMA_ERR_MASK)
1190 #define SDXC_INT_STAT_ADMA_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_ADMA_ERR_MASK) >> SDXC_INT_STAT_ADMA_ERR_SHIFT)
1191 
1192 /*
1193  * AUTO_CMD_ERR (R/W1C)
1194  *
1195  * Auto CMD Error
1196  * This error status is used by Auto CMD12 and Auto CMD23 in SD/eMMC mode.
1197  * This bit is set when detecting that any of the bits D00 to D05 in Auto CMD Error Status register has changed from 0 to 1.
1198  * D07 is effective in case of Auto CMD12. Auto CMD Error Status register is valid while this bit is set to 1 and may be cleared by clearing of this bit.
1199  * Values:
1200  * 0x0 (FALSE): No error
1201  * 0x1 (TRUE): Error
1202  */
1203 #define SDXC_INT_STAT_AUTO_CMD_ERR_MASK (0x1000000UL)
1204 #define SDXC_INT_STAT_AUTO_CMD_ERR_SHIFT (24U)
1205 #define SDXC_INT_STAT_AUTO_CMD_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_AUTO_CMD_ERR_SHIFT) & SDXC_INT_STAT_AUTO_CMD_ERR_MASK)
1206 #define SDXC_INT_STAT_AUTO_CMD_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_AUTO_CMD_ERR_MASK) >> SDXC_INT_STAT_AUTO_CMD_ERR_SHIFT)
1207 
1208 /*
1209  * CUR_LMT_ERR (R/W1C)
1210  *
1211  * Current Limit Error
1212  * By setting the SD Bus Power bit in the Power Control register, the Host Controller is requested to supply power for the SD Bus.
1213  * If the Host Controller supports the Current Limit function, it can be protected from an illegal card by stopping power supply to the card in which case this bit indicates a failure status.
1214  * A reading of 1 for this bit means that the Host Controller is not supplying power to the SD card due to some failure.
1215  * A reading of 0 for this bit means that the Host Controller is supplying power and no error has occurred.
1216  * The Host Controller may require some sampling time to detect the current limit.
1217  * SDXC Host Controller does not support this function, this bit is always set to 0.
1218  * Values:
1219  * 0x0 (FALSE): No error
1220  * 0x1 (TRUE): Power Fail
1221  */
1222 #define SDXC_INT_STAT_CUR_LMT_ERR_MASK (0x800000UL)
1223 #define SDXC_INT_STAT_CUR_LMT_ERR_SHIFT (23U)
1224 #define SDXC_INT_STAT_CUR_LMT_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CUR_LMT_ERR_SHIFT) & SDXC_INT_STAT_CUR_LMT_ERR_MASK)
1225 #define SDXC_INT_STAT_CUR_LMT_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CUR_LMT_ERR_MASK) >> SDXC_INT_STAT_CUR_LMT_ERR_SHIFT)
1226 
1227 /*
1228  * DATA_END_BIT_ERR (R/W1C)
1229  *
1230  * Data End Bit Error
1231  * This error occurs in SD/eMMC mode either when detecting 0 at the end bit position of read data that uses the DAT line or at the end bit position of the CRC status.
1232  * Values:
1233  * 0x0 (FALSE): No error
1234  * 0x1 (TRUE): Error
1235  */
1236 #define SDXC_INT_STAT_DATA_END_BIT_ERR_MASK (0x400000UL)
1237 #define SDXC_INT_STAT_DATA_END_BIT_ERR_SHIFT (22U)
1238 #define SDXC_INT_STAT_DATA_END_BIT_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_DATA_END_BIT_ERR_SHIFT) & SDXC_INT_STAT_DATA_END_BIT_ERR_MASK)
1239 #define SDXC_INT_STAT_DATA_END_BIT_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_DATA_END_BIT_ERR_MASK) >> SDXC_INT_STAT_DATA_END_BIT_ERR_SHIFT)
1240 
1241 /*
1242  * DATA_CRC_ERR (R/W1C)
1243  *
1244  * Data CRC Error
1245  * This error occurs in SD/eMMC mode when detecting CRC error when transferring read data which uses the DAT line,
1246  * when detecting the Write CRC status having a value of other than 010 or when write CRC status timeout.
1247  * Values:
1248  * 0x0 (FALSE): No error
1249  * 0x1 (TRUE): Error
1250  */
1251 #define SDXC_INT_STAT_DATA_CRC_ERR_MASK (0x200000UL)
1252 #define SDXC_INT_STAT_DATA_CRC_ERR_SHIFT (21U)
1253 #define SDXC_INT_STAT_DATA_CRC_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_DATA_CRC_ERR_SHIFT) & SDXC_INT_STAT_DATA_CRC_ERR_MASK)
1254 #define SDXC_INT_STAT_DATA_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_DATA_CRC_ERR_MASK) >> SDXC_INT_STAT_DATA_CRC_ERR_SHIFT)
1255 
1256 /*
1257  * DATA_TOUT_ERR (R/W1C)
1258  *
1259  * Data Timeout Error
1260  * This bit is set in SD/eMMC mode when detecting one of the following timeout conditions:
1261  * Busy timeout for R1b, R5b type
1262  * Busy timeout after Write CRC status
1263  * Write CRC Status timeout
1264  * Read Data timeout
1265  * Values:
1266  * 0x0 (FALSE): No error
1267  * 0x1 (TRUE): Time out
1268  */
1269 #define SDXC_INT_STAT_DATA_TOUT_ERR_MASK (0x100000UL)
1270 #define SDXC_INT_STAT_DATA_TOUT_ERR_SHIFT (20U)
1271 #define SDXC_INT_STAT_DATA_TOUT_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_DATA_TOUT_ERR_SHIFT) & SDXC_INT_STAT_DATA_TOUT_ERR_MASK)
1272 #define SDXC_INT_STAT_DATA_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_DATA_TOUT_ERR_MASK) >> SDXC_INT_STAT_DATA_TOUT_ERR_SHIFT)
1273 
1274 /*
1275  * CMD_IDX_ERR (R/W1C)
1276  *
1277  * Command Index Error
1278  * This bit is set if a Command Index error occurs in the command respons in SD/eMMC mode.
1279  * Values:
1280  * 0x0 (FALSE): No error
1281  * 0x1 (TRUE): Error
1282  */
1283 #define SDXC_INT_STAT_CMD_IDX_ERR_MASK (0x80000UL)
1284 #define SDXC_INT_STAT_CMD_IDX_ERR_SHIFT (19U)
1285 #define SDXC_INT_STAT_CMD_IDX_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CMD_IDX_ERR_SHIFT) & SDXC_INT_STAT_CMD_IDX_ERR_MASK)
1286 #define SDXC_INT_STAT_CMD_IDX_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CMD_IDX_ERR_MASK) >> SDXC_INT_STAT_CMD_IDX_ERR_SHIFT)
1287 
1288 /*
1289  * CMD_END_BIT_ERR (R/W1C)
1290  *
1291  * Command End Bit Error
1292  * This bit is set when detecting that the end bit of a command response is 0 in SD/eMMC mode.
1293  * Values:
1294  * 0x0 (FALSE): No error
1295  * 0x1 (TRUE): End Bit error generated
1296  */
1297 #define SDXC_INT_STAT_CMD_END_BIT_ERR_MASK (0x40000UL)
1298 #define SDXC_INT_STAT_CMD_END_BIT_ERR_SHIFT (18U)
1299 #define SDXC_INT_STAT_CMD_END_BIT_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CMD_END_BIT_ERR_SHIFT) & SDXC_INT_STAT_CMD_END_BIT_ERR_MASK)
1300 #define SDXC_INT_STAT_CMD_END_BIT_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CMD_END_BIT_ERR_MASK) >> SDXC_INT_STAT_CMD_END_BIT_ERR_SHIFT)
1301 
1302 /*
1303  * CMD_CRC_ERR (R/W1C)
1304  *
1305  * Command CRC Error
1306  * Command CRC Error is generated in SD/eMMC mode for following two cases.
1307  * If a response is returned and the Command Timeout Error is set to 0 (indicating no timeout), this bit is set to 1 when detecting a CRC error in the command response.
1308  * The Host Controller detects a CMD line conflict by monitoring the CMD line when a command is issued.
1309  * If the Host Controller drives the CMD line to 1 level,
1310  * but detects 0 level on the CMD line at the next SD clock edge, then the Host Controller aborts the command (stop driving CMD line) and set this bit to 1.
1311  * The Command Timeout Error is also set to 1 to distinguish a CMD line conflict.
1312  * Values:
1313  * 0x0 (FALSE): No error
1314  * 0x1 (TRUE): CRC error generated
1315  */
1316 #define SDXC_INT_STAT_CMD_CRC_ERR_MASK (0x20000UL)
1317 #define SDXC_INT_STAT_CMD_CRC_ERR_SHIFT (17U)
1318 #define SDXC_INT_STAT_CMD_CRC_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CMD_CRC_ERR_SHIFT) & SDXC_INT_STAT_CMD_CRC_ERR_MASK)
1319 #define SDXC_INT_STAT_CMD_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CMD_CRC_ERR_MASK) >> SDXC_INT_STAT_CMD_CRC_ERR_SHIFT)
1320 
1321 /*
1322  * CMD_TOUT_ERR (R/W1C)
1323  *
1324  * Command Timeout Error
1325  * In SD/eMMC Mode,this bit is set only if no response is returned within 64 SD clock cycles from the end bit of the command.
1326  * If the Host Controller detects a CMD line conflict, along with Command CRC Error bit, this bit is set to 1, without waiting for 64 SD/eMMC card clock cycles.
1327  * Values:
1328  * 0x0 (FALSE): No error
1329  * 0x1 (TRUE): Time out
1330  */
1331 #define SDXC_INT_STAT_CMD_TOUT_ERR_MASK (0x10000UL)
1332 #define SDXC_INT_STAT_CMD_TOUT_ERR_SHIFT (16U)
1333 #define SDXC_INT_STAT_CMD_TOUT_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CMD_TOUT_ERR_SHIFT) & SDXC_INT_STAT_CMD_TOUT_ERR_MASK)
1334 #define SDXC_INT_STAT_CMD_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CMD_TOUT_ERR_MASK) >> SDXC_INT_STAT_CMD_TOUT_ERR_SHIFT)
1335 
1336 /*
1337  * ERR_INTERRUPT (RO)
1338  *
1339  * Error Interrupt
1340  * If any of the bits in the Error Interrupt Status register are set, then this bit is set.
1341  * Values:
1342  * 0x0 (FALSE): No Error
1343  * 0x1 (TRUE): Error
1344  */
1345 #define SDXC_INT_STAT_ERR_INTERRUPT_MASK (0x8000U)
1346 #define SDXC_INT_STAT_ERR_INTERRUPT_SHIFT (15U)
1347 #define SDXC_INT_STAT_ERR_INTERRUPT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_ERR_INTERRUPT_MASK) >> SDXC_INT_STAT_ERR_INTERRUPT_SHIFT)
1348 
1349 /*
1350  * CQE_EVENT (R/W1C)
1351  *
1352  * Command Queuing Event
1353  * This status is set if Command Queuing/Crypto related event has occurred in eMMC/SD mode. Read CQHCI's CQIS/CRNQIS register for more details.
1354  * Values:
1355  * 0x0 (FALSE): No Event
1356  * 0x1 (TRUE): Command Queuing Event is detected
1357  */
1358 #define SDXC_INT_STAT_CQE_EVENT_MASK (0x4000U)
1359 #define SDXC_INT_STAT_CQE_EVENT_SHIFT (14U)
1360 #define SDXC_INT_STAT_CQE_EVENT_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CQE_EVENT_SHIFT) & SDXC_INT_STAT_CQE_EVENT_MASK)
1361 #define SDXC_INT_STAT_CQE_EVENT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CQE_EVENT_MASK) >> SDXC_INT_STAT_CQE_EVENT_SHIFT)
1362 
1363 /*
1364  * FX_EVENT (RO)
1365  *
1366  * FX Event
1367  * This status is set when R[14] of response register is set to 1 and Response Type R1/R5 is set to 0 in Transfer Mode register. This interrupt is used with response check function.
1368  * Values:
1369  * 0x0 (FALSE): No Event
1370  * 0x1 (TRUE): FX Event is detected
1371  */
1372 #define SDXC_INT_STAT_FX_EVENT_MASK (0x2000U)
1373 #define SDXC_INT_STAT_FX_EVENT_SHIFT (13U)
1374 #define SDXC_INT_STAT_FX_EVENT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_FX_EVENT_MASK) >> SDXC_INT_STAT_FX_EVENT_SHIFT)
1375 
1376 /*
1377  * RE_TUNE_EVENT (RO)
1378  *
1379  * Re-tuning Event
1380  * This bit is set if the Re-Tuning Request changes from 0 to 1. Re-Tuning request is not supported.
1381  */
1382 #define SDXC_INT_STAT_RE_TUNE_EVENT_MASK (0x1000U)
1383 #define SDXC_INT_STAT_RE_TUNE_EVENT_SHIFT (12U)
1384 #define SDXC_INT_STAT_RE_TUNE_EVENT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_RE_TUNE_EVENT_MASK) >> SDXC_INT_STAT_RE_TUNE_EVENT_SHIFT)
1385 
1386 /*
1387  * CARD_INTERRUPT (RO)
1388  *
1389  * Card Interrupt
1390  * This bit reflects the synchronized value of:
1391  * DAT[1] Interrupt Input for SD Mode
1392  * DAT[2] Interrupt Input for UHS-II Mode
1393  * Values:
1394  * 0x0 (FALSE): No Card Interrupt
1395  * 0x1 (TRUE): Generate Card Interrupt
1396  */
1397 #define SDXC_INT_STAT_CARD_INTERRUPT_MASK (0x100U)
1398 #define SDXC_INT_STAT_CARD_INTERRUPT_SHIFT (8U)
1399 #define SDXC_INT_STAT_CARD_INTERRUPT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CARD_INTERRUPT_MASK) >> SDXC_INT_STAT_CARD_INTERRUPT_SHIFT)
1400 
1401 /*
1402  * CARD_REMOVAL (R/W1C)
1403  *
1404  * Card Removal
1405  * This bit is set if the Card Inserted in the Present State register changes from 1 to 0.
1406  * Values:
1407  * 0x0 (FALSE): Card state stable or Debouncing
1408  * 0x1 (TRUE): Card Removed
1409  */
1410 #define SDXC_INT_STAT_CARD_REMOVAL_MASK (0x80U)
1411 #define SDXC_INT_STAT_CARD_REMOVAL_SHIFT (7U)
1412 #define SDXC_INT_STAT_CARD_REMOVAL_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CARD_REMOVAL_SHIFT) & SDXC_INT_STAT_CARD_REMOVAL_MASK)
1413 #define SDXC_INT_STAT_CARD_REMOVAL_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CARD_REMOVAL_MASK) >> SDXC_INT_STAT_CARD_REMOVAL_SHIFT)
1414 
1415 /*
1416  * CARD_INSERTION (R/W1C)
1417  *
1418  * Card Insertion
1419  * This bit is set if the Card Inserted in the Present State register changes from 0 to 1.
1420  * Values:
1421  * 0x0 (FALSE): Card state stable or Debouncing
1422  * 0x1 (TRUE): Card Inserted
1423  */
1424 #define SDXC_INT_STAT_CARD_INSERTION_MASK (0x40U)
1425 #define SDXC_INT_STAT_CARD_INSERTION_SHIFT (6U)
1426 #define SDXC_INT_STAT_CARD_INSERTION_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CARD_INSERTION_SHIFT) & SDXC_INT_STAT_CARD_INSERTION_MASK)
1427 #define SDXC_INT_STAT_CARD_INSERTION_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CARD_INSERTION_MASK) >> SDXC_INT_STAT_CARD_INSERTION_SHIFT)
1428 
1429 /*
1430  * BUF_RD_READY (R/W1C)
1431  *
1432  * Buffer Read Ready
1433  * This bit is set if the Buffer Read Enable changes from 0 to 1.
1434  * Values:
1435  * 0x0 (FALSE): Not ready to read buffer
1436  * 0x1 (TRUE): Ready to read buffer
1437  */
1438 #define SDXC_INT_STAT_BUF_RD_READY_MASK (0x20U)
1439 #define SDXC_INT_STAT_BUF_RD_READY_SHIFT (5U)
1440 #define SDXC_INT_STAT_BUF_RD_READY_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_BUF_RD_READY_SHIFT) & SDXC_INT_STAT_BUF_RD_READY_MASK)
1441 #define SDXC_INT_STAT_BUF_RD_READY_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_BUF_RD_READY_MASK) >> SDXC_INT_STAT_BUF_RD_READY_SHIFT)
1442 
1443 /*
1444  * BUF_WR_READY (R/W1C)
1445  *
1446  * Buffer Write Ready
1447  * This bit is set if the Buffer Write Enable changes from 0 to 1.
1448  * Values:
1449  * 0x0 (FALSE): Not ready to write buffer
1450  * 0x1 (TRUE): Ready to write buffer
1451  */
1452 #define SDXC_INT_STAT_BUF_WR_READY_MASK (0x10U)
1453 #define SDXC_INT_STAT_BUF_WR_READY_SHIFT (4U)
1454 #define SDXC_INT_STAT_BUF_WR_READY_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_BUF_WR_READY_SHIFT) & SDXC_INT_STAT_BUF_WR_READY_MASK)
1455 #define SDXC_INT_STAT_BUF_WR_READY_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_BUF_WR_READY_MASK) >> SDXC_INT_STAT_BUF_WR_READY_SHIFT)
1456 
1457 /*
1458  * DMA_INTERRUPT (R/W1C)
1459  *
1460  * DMA Interrupt
1461  * This bit is set if the Host Controller detects the SDMA Buffer Boundary during transfer.
1462  * In case of ADMA, by setting the Int field in the descriptor table, the Host controller generates this interrupt.
1463  * This interrupt is not generated after a Transfer Complete.
1464  * Values:
1465  * 0x0 (FALSE): No DMA Interrupt
1466  * 0x1 (TRUE): DMA Interrupt is generated
1467  */
1468 #define SDXC_INT_STAT_DMA_INTERRUPT_MASK (0x8U)
1469 #define SDXC_INT_STAT_DMA_INTERRUPT_SHIFT (3U)
1470 #define SDXC_INT_STAT_DMA_INTERRUPT_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_DMA_INTERRUPT_SHIFT) & SDXC_INT_STAT_DMA_INTERRUPT_MASK)
1471 #define SDXC_INT_STAT_DMA_INTERRUPT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_DMA_INTERRUPT_MASK) >> SDXC_INT_STAT_DMA_INTERRUPT_SHIFT)
1472 
1473 /*
1474  * BGAP_EVENT (R/W1C)
1475  *
1476  * Block Gap Event
1477  * This bit is set when both read/write transaction is stopped at block gap due to a Stop at Block Gap Request.
1478  * Values:
1479  * 0x0 (FALSE): No Block Gap Event
1480  * 0x1 (TRUE): Transaction stopped at block gap
1481  */
1482 #define SDXC_INT_STAT_BGAP_EVENT_MASK (0x4U)
1483 #define SDXC_INT_STAT_BGAP_EVENT_SHIFT (2U)
1484 #define SDXC_INT_STAT_BGAP_EVENT_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_BGAP_EVENT_SHIFT) & SDXC_INT_STAT_BGAP_EVENT_MASK)
1485 #define SDXC_INT_STAT_BGAP_EVENT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_BGAP_EVENT_MASK) >> SDXC_INT_STAT_BGAP_EVENT_SHIFT)
1486 
1487 /*
1488  * XFER_COMPLETE (R/W1C)
1489  *
1490  * Transfer Complete
1491  * This bit is set when a read/write transfer and a command with status busy is completed.
1492  * Values:
1493  * 0x0 (FALSE): Not complete
1494  * 0x1 (TRUE): Command execution is completed
1495  */
1496 #define SDXC_INT_STAT_XFER_COMPLETE_MASK (0x2U)
1497 #define SDXC_INT_STAT_XFER_COMPLETE_SHIFT (1U)
1498 #define SDXC_INT_STAT_XFER_COMPLETE_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_XFER_COMPLETE_SHIFT) & SDXC_INT_STAT_XFER_COMPLETE_MASK)
1499 #define SDXC_INT_STAT_XFER_COMPLETE_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_XFER_COMPLETE_MASK) >> SDXC_INT_STAT_XFER_COMPLETE_SHIFT)
1500 
1501 /*
1502  * CMD_COMPLETE (R/W1C)
1503  *
1504  * Command Complete
1505  * In an SD/eMMC Mode, this bit is set when the end bit of a response except for Auto CMD12 and Auto CMD23.
1506  * This interrupt is not generated when the Response Interrupt Disable in Transfer Mode Register is set to 1.
1507  * Values:
1508  * 0x0 (FALSE): No command complete
1509  * 0x1 (TRUE): Command Complete
1510  */
1511 #define SDXC_INT_STAT_CMD_COMPLETE_MASK (0x1U)
1512 #define SDXC_INT_STAT_CMD_COMPLETE_SHIFT (0U)
1513 #define SDXC_INT_STAT_CMD_COMPLETE_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CMD_COMPLETE_SHIFT) & SDXC_INT_STAT_CMD_COMPLETE_MASK)
1514 #define SDXC_INT_STAT_CMD_COMPLETE_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CMD_COMPLETE_MASK) >> SDXC_INT_STAT_CMD_COMPLETE_SHIFT)
1515 
1516 /* Bitfield definition for register: INT_STAT_EN */
1517 /*
1518  * BOOT_ACK_ERR_STAT_EN (RW)
1519  *
1520  * Boot Acknowledgment Error (eMMC Mode only)
1521  * Setting this bit to 1 enables setting of Boot Acknowledgment Error in Error Interrupt Status register (INT_STAT).
1522  * Values:
1523  * 0x0 (FALSE): Masked
1524  * 0x1 (TRUE): Enabled
1525  */
1526 #define SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_MASK (0x10000000UL)
1527 #define SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_SHIFT (28U)
1528 #define SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_MASK)
1529 #define SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_SHIFT)
1530 
1531 /*
1532  * RESP_ERR_STAT_EN (RW)
1533  *
1534  * Response Error Status Enable (SD Mode only)
1535  * Values:
1536  * 0x0 (FALSE): Masked
1537  * 0x1 (TRUE): Enabled
1538  */
1539 #define SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_MASK (0x8000000UL)
1540 #define SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_SHIFT (27U)
1541 #define SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_MASK)
1542 #define SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_SHIFT)
1543 
1544 /*
1545  * TUNING_ERR_STAT_EN (RW)
1546  *
1547  * Tuning Error Status Enable (UHS-I Mode only)
1548  * Values:
1549  * 0x0 (FALSE): Masked
1550  * 0x1 (TRUE): Enabled
1551  */
1552 #define SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_MASK (0x4000000UL)
1553 #define SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_SHIFT (26U)
1554 #define SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_MASK)
1555 #define SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_SHIFT)
1556 
1557 /*
1558  * ADMA_ERR_STAT_EN (RW)
1559  *
1560  * ADMA Error Status Enable
1561  * Values:
1562  * 0x0 (FALSE): Masked
1563  * 0x1 (TRUE): Enabled
1564  */
1565 #define SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_MASK (0x2000000UL)
1566 #define SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_SHIFT (25U)
1567 #define SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_MASK)
1568 #define SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_SHIFT)
1569 
1570 /*
1571  * AUTO_CMD_ERR_STAT_EN (RW)
1572  *
1573  * Auto CMD Error Status Enable (SD/eMMC Mode only).
1574  * Values:
1575  * 0x0 (FALSE): Masked
1576  * 0x1 (TRUE): Enabled
1577  */
1578 #define SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_MASK (0x1000000UL)
1579 #define SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_SHIFT (24U)
1580 #define SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_MASK)
1581 #define SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_SHIFT)
1582 
1583 /*
1584  * CUR_LMT_ERR_STAT_EN (RW)
1585  *
1586  * Current Limit Error Status Enable
1587  * Values:
1588  * 0x0 (FALSE): Masked
1589  * 0x1 (TRUE): Enabled
1590  */
1591 #define SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_MASK (0x800000UL)
1592 #define SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_SHIFT (23U)
1593 #define SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_MASK)
1594 #define SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_SHIFT)
1595 
1596 /*
1597  * DATA_END_BIT_ERR_STAT_EN (RW)
1598  *
1599  * Data End Bit Error Status Enable (SD/eMMC Mode only).
1600  * Values:
1601  * 0x0 (FALSE): Masked
1602  * 0x1 (TRUE): Enabled
1603  */
1604 #define SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_MASK (0x400000UL)
1605 #define SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_SHIFT (22U)
1606 #define SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_MASK)
1607 #define SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_SHIFT)
1608 
1609 /*
1610  * DATA_CRC_ERR_STAT_EN (RW)
1611  *
1612  * Data CRC Error Status Enable (SD/eMMC Mode only)
1613  * Values:
1614  * 0x0 (FALSE): Masked
1615  * 0x1 (TRUE): Enabled
1616  */
1617 #define SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_MASK (0x200000UL)
1618 #define SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_SHIFT (21U)
1619 #define SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_MASK)
1620 #define SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_SHIFT)
1621 
1622 /*
1623  * DATA_TOUT_ERR_STAT_EN (RW)
1624  *
1625  * Data Timeout Error Status Enable (SD/eMMC Mode only)
1626  * Values:
1627  * 0x0 (FALSE): Masked
1628  * 0x1 (TRUE): Enabled
1629  */
1630 #define SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_MASK (0x100000UL)
1631 #define SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_SHIFT (20U)
1632 #define SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_MASK)
1633 #define SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_SHIFT)
1634 
1635 /*
1636  * CMD_IDX_ERR_STAT_EN (RW)
1637  *
1638  * Command Index Error Status Enable (SD/eMMC Mode only)
1639  * Values:
1640  * 0x0 (FALSE): Masked
1641  * 0x1 (TRUE): Enabled
1642  */
1643 #define SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_MASK (0x80000UL)
1644 #define SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_SHIFT (19U)
1645 #define SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_MASK)
1646 #define SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_SHIFT)
1647 
1648 /*
1649  * CMD_END_BIT_ERR_STAT_EN (RW)
1650  *
1651  * Command End Bit Error Status Enable (SD/eMMC Mode only)
1652  * Values:
1653  * 0x0 (FALSE): Masked
1654  * 0x1 (TRUE): Enabled
1655  */
1656 #define SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_MASK (0x40000UL)
1657 #define SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_SHIFT (18U)
1658 #define SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_MASK)
1659 #define SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_SHIFT)
1660 
1661 /*
1662  * CMD_CRC_ERR_STAT_EN (RW)
1663  *
1664  * Command CRC Error Status Enable (SD/eMMC Mode only)
1665  * Values:
1666  * 0x0 (FALSE): Masked
1667  * 0x1 (TRUE): Enabled
1668  */
1669 #define SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_MASK (0x20000UL)
1670 #define SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_SHIFT (17U)
1671 #define SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_MASK)
1672 #define SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_SHIFT)
1673 
1674 /*
1675  * CMD_TOUT_ERR_STAT_EN (RW)
1676  *
1677  * Command Timeout Error Status Enable (SD/eMMC Mode only).
1678  * Values:
1679  * 0x0 (FALSE): Masked
1680  * 0x1 (TRUE): Enabled
1681  */
1682 #define SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_MASK (0x10000UL)
1683 #define SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_SHIFT (16U)
1684 #define SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_MASK)
1685 #define SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_SHIFT)
1686 
1687 /*
1688  * CQE_EVENT_STAT_EN (RW)
1689  *
1690  * CQE Event Status Enable
1691  * Values:
1692  * 0x0 (FALSE): Masked
1693  * 0x1 (TRUE): Enabled
1694  */
1695 #define SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_MASK (0x4000U)
1696 #define SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_SHIFT (14U)
1697 #define SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_MASK)
1698 #define SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_SHIFT)
1699 
1700 /*
1701  * FX_EVENT_STAT_EN (RW)
1702  *
1703  * FX Event Status Enable
1704  * This bit is added from Version 4.10.
1705  * Values:
1706  * 0x0 (FALSE): Masked
1707  * 0x1 (TRUE): Enabled
1708  */
1709 #define SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_MASK (0x2000U)
1710 #define SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_SHIFT (13U)
1711 #define SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_MASK)
1712 #define SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_SHIFT)
1713 
1714 /*
1715  * RE_TUNE_EVENT_STAT_EN (RW)
1716  *
1717  * Re-Tuning Event (UHS-I only) Status Enable
1718  * Values:
1719  * 0x0 (FALSE): Masked
1720  * 0x1 (TRUE): Enabled
1721  */
1722 #define SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_MASK (0x1000U)
1723 #define SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_SHIFT (12U)
1724 #define SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_MASK)
1725 #define SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_SHIFT)
1726 
1727 /*
1728  * CARD_INTERRUPT_STAT_EN (RW)
1729  *
1730  * Card Interrupt Status Enable
1731  * If this bit is set to 0, the Host Controller clears the interrupt request to the System.
1732  * The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1.
1733  * The Host Driver may clear the Card Interrupt Status Enable before servicing the Card Interrupt and may set this bit again after all interrupt requests from the card are cleared to prevent inadvertent interrupts.
1734  * By setting this bit to 0, interrupt input must be masked by implementation so that the interrupt input is not affected by external signal in any state (for example, floating).
1735  * Values:
1736  * 0x0 (FALSE): Masked
1737  * 0x1 (TRUE): Enabled
1738  */
1739 #define SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_MASK (0x100U)
1740 #define SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_SHIFT (8U)
1741 #define SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_MASK)
1742 #define SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_SHIFT)
1743 
1744 /*
1745  * CARD_REMOVAL_STAT_EN (RW)
1746  *
1747  * Card Removal Status Enable
1748  * Values:
1749  * 0x0 (FALSE): Masked
1750  * 0x1 (TRUE): Enabled
1751  */
1752 #define SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_MASK (0x80U)
1753 #define SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_SHIFT (7U)
1754 #define SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_MASK)
1755 #define SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_SHIFT)
1756 
1757 /*
1758  * CARD_INSERTION_STAT_EN (RW)
1759  *
1760  * Card Insertion Status Enable
1761  * Values:
1762  * 0x0 (FALSE): Masked
1763  * 0x1 (TRUE): Enabled
1764  */
1765 #define SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_MASK (0x40U)
1766 #define SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_SHIFT (6U)
1767 #define SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_MASK)
1768 #define SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_SHIFT)
1769 
1770 /*
1771  * BUF_RD_READY_STAT_EN (RW)
1772  *
1773  * Buffer Read Ready Status Enable
1774  * Values:
1775  * 0x0 (FALSE): Masked
1776  * 0x1 (TRUE): Enabled
1777  */
1778 #define SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_MASK (0x20U)
1779 #define SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_SHIFT (5U)
1780 #define SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_MASK)
1781 #define SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_MASK) >> SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_SHIFT)
1782 
1783 /*
1784  * BUF_WR_READY_STAT_EN (RW)
1785  *
1786  * Buffer Write Ready Status Enable
1787  * Values:
1788  * 0x0 (FALSE): Masked
1789  * 0x1 (TRUE): Enabled
1790  */
1791 #define SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_MASK (0x10U)
1792 #define SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_SHIFT (4U)
1793 #define SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_MASK)
1794 #define SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_MASK) >> SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_SHIFT)
1795 
1796 /*
1797  * DMA_INTERRUPT_STAT_EN (RW)
1798  *
1799  * DMA Interrupt Status Enable
1800  * Values:
1801  * 0x0 (FALSE): Masked
1802  * 0x1 (TRUE): Enabled
1803  */
1804 #define SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_MASK (0x8U)
1805 #define SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_SHIFT (3U)
1806 #define SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_MASK)
1807 #define SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_SHIFT)
1808 
1809 /*
1810  * BGAP_EVENT_STAT_EN (RW)
1811  *
1812  * Block Gap Event Status Enable
1813  * Values:
1814  * 0x0 (FALSE): Masked
1815  * 0x1 (TRUE): Enabled
1816  */
1817 #define SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_MASK (0x4U)
1818 #define SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_SHIFT (2U)
1819 #define SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_MASK)
1820 #define SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_SHIFT)
1821 
1822 /*
1823  * XFER_COMPLETE_STAT_EN (RW)
1824  *
1825  * Transfer Complete Status Enable
1826  * Values:
1827  * 0x0 (FALSE): Masked
1828  * 0x1 (TRUE): Enabled
1829  */
1830 #define SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_MASK (0x2U)
1831 #define SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_SHIFT (1U)
1832 #define SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_MASK)
1833 #define SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_MASK) >> SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_SHIFT)
1834 
1835 /*
1836  * CMD_COMPLETE_STAT_EN (RW)
1837  *
1838  * Command Complete Status Enable
1839  * Values:
1840  * 0x0 (FALSE): Masked
1841  * 0x1 (TRUE): Enabled
1842  */
1843 #define SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_MASK (0x1U)
1844 #define SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_SHIFT (0U)
1845 #define SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_MASK)
1846 #define SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_SHIFT)
1847 
1848 /* Bitfield definition for register: INT_SIGNAL_EN */
1849 /*
1850  * BOOT_ACK_ERR_SIGNAL_EN (RW)
1851  *
1852  * Boot Acknowledgment Error (eMMC Mode only).
1853  * Setting this bit to 1 enables generating interrupt signal when Boot Acknowledgment Error in Error Interrupt Status register is set.
1854  * Values:
1855  * 0x0 (FALSE): Masked
1856  * 0x1 (TRUE): Enabled
1857  */
1858 #define SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_MASK (0x10000000UL)
1859 #define SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_SHIFT (28U)
1860 #define SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_MASK)
1861 #define SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_SHIFT)
1862 
1863 /*
1864  * RESP_ERR_SIGNAL_EN (RW)
1865  *
1866  * Response Error Signal Enable (SD Mode only)
1867  * Values:
1868  * 0x0 (FALSE): Masked
1869  * 0x1 (TRUE): Enabled
1870  */
1871 #define SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_MASK (0x8000000UL)
1872 #define SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_SHIFT (27U)
1873 #define SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_MASK)
1874 #define SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_SHIFT)
1875 
1876 /*
1877  * TUNING_ERR_SIGNAL_EN (RW)
1878  *
1879  * Tuning Error Signal Enable (UHS-I Mode only)
1880  * Values:
1881  * 0x0 (FALSE): Masked
1882  * 0x1 (TRUE): Enabled
1883  */
1884 #define SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_MASK (0x4000000UL)
1885 #define SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_SHIFT (26U)
1886 #define SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_MASK)
1887 #define SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_SHIFT)
1888 
1889 /*
1890  * ADMA_ERR_SIGNAL_EN (RW)
1891  *
1892  * ADMA Error Signal Enable
1893  * Values:
1894  * 0x0 (FALSE): Masked
1895  * 0x1 (TRUE): Enabled
1896  */
1897 #define SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_MASK (0x2000000UL)
1898 #define SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_SHIFT (25U)
1899 #define SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_MASK)
1900 #define SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_SHIFT)
1901 
1902 /*
1903  * AUTO_CMD_ERR_SIGNAL_EN (RW)
1904  *
1905  * Auto CMD Error Signal Enable (SD/eMMC Mode only)
1906  * Values:
1907  * 0x0 (FALSE): Masked
1908  * 0x1 (TRUE): Enabled
1909  */
1910 #define SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_MASK (0x1000000UL)
1911 #define SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_SHIFT (24U)
1912 #define SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_MASK)
1913 #define SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_SHIFT)
1914 
1915 /*
1916  * CUR_LMT_ERR_SIGNAL_EN (RW)
1917  *
1918  * Current Limit Error Signal Enable
1919  * Values:
1920  * 0x0 (FALSE): Masked
1921  * 0x1 (TRUE): Enabled
1922  */
1923 #define SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_MASK (0x800000UL)
1924 #define SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_SHIFT (23U)
1925 #define SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_MASK)
1926 #define SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_SHIFT)
1927 
1928 /*
1929  * DATA_END_BIT_ERR_SIGNAL_EN (RW)
1930  *
1931  * Data End Bit Error Signal Enable (SD/eMMC Mode only)
1932  * Values:
1933  * 0x0 (FALSE): Masked
1934  * 0x1 (TRUE): Enabled
1935  */
1936 #define SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_MASK (0x400000UL)
1937 #define SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_SHIFT (22U)
1938 #define SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_MASK)
1939 #define SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_SHIFT)
1940 
1941 /*
1942  * DATA_CRC_ERR_SIGNAL_EN (RW)
1943  *
1944  * Data CRC Error Signal Enable (SD/eMMC Mode only)
1945  * Values:
1946  * 0x0 (FALSE): Masked
1947  * 0x1 (TRUE): Enabled
1948  */
1949 #define SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_MASK (0x200000UL)
1950 #define SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_SHIFT (21U)
1951 #define SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_MASK)
1952 #define SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_SHIFT)
1953 
1954 /*
1955  * DATA_TOUT_ERR_SIGNAL_EN (RW)
1956  *
1957  * Data Timeout Error Signal Enable (SD/eMMC Mode only)
1958  * Values:
1959  * 0x0 (FALSE): Masked
1960  * 0x1 (TRUE): Enabled
1961  */
1962 #define SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_MASK (0x100000UL)
1963 #define SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_SHIFT (20U)
1964 #define SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_MASK)
1965 #define SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_SHIFT)
1966 
1967 /*
1968  * CMD_IDX_ERR_SIGNAL_EN (RW)
1969  *
1970  * Command Index Error Signal Enable (SD/eMMC Mode only)
1971  * Values:
1972  * 0x0 (FALSE): No error
1973  * 0x1 (TRUE): Error
1974  */
1975 #define SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_MASK (0x80000UL)
1976 #define SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_SHIFT (19U)
1977 #define SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_MASK)
1978 #define SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_SHIFT)
1979 
1980 /*
1981  * CMD_END_BIT_ERR_SIGNAL_EN (RW)
1982  *
1983  * Command End Bit Error Signal Enable (SD/eMMC Mode only)
1984  * Values:
1985  * 0x0 (FALSE): Masked
1986  * 0x1 (TRUE): Enabled
1987  */
1988 #define SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_MASK (0x40000UL)
1989 #define SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_SHIFT (18U)
1990 #define SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_MASK)
1991 #define SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_SHIFT)
1992 
1993 /*
1994  * CMD_CRC_ERR_SIGNAL_EN (RW)
1995  *
1996  * Command CRC Error Signal Enable (SD/eMMC Mode only)
1997  * Values:
1998  * 0x0 (FALSE): Masked
1999  * 0x1 (TRUE): Enabled
2000  */
2001 #define SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_MASK (0x20000UL)
2002 #define SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_SHIFT (17U)
2003 #define SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_MASK)
2004 #define SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_SHIFT)
2005 
2006 /*
2007  * CMD_TOUT_ERR_SIGNAL_EN (RW)
2008  *
2009  * Command Timeout Error Signal Enable (SD/eMMC Mode only)
2010  * Values:
2011  * 0x0 (FALSE): Masked
2012  * 0x1 (TRUE): Enabled
2013  */
2014 #define SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_MASK (0x10000UL)
2015 #define SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_SHIFT (16U)
2016 #define SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_MASK)
2017 #define SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_SHIFT)
2018 
2019 /*
2020  * CQE_EVENT_SIGNAL_EN (RW)
2021  *
2022  * Command Queuing Engine Event Signal Enable
2023  * Values:
2024  * 0x0 (FALSE): Masked
2025  * 0x1 (TRUE): Enabled
2026  */
2027 #define SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_MASK (0x4000U)
2028 #define SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_SHIFT (14U)
2029 #define SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_MASK)
2030 #define SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_SHIFT)
2031 
2032 /*
2033  * FX_EVENT_SIGNAL_EN (RW)
2034  *
2035  * FX Event Signal Enable
2036  * Values:
2037  * 0x0 (FALSE): Masked
2038  * 0x1 (TRUE): Enabled
2039  */
2040 #define SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_MASK (0x2000U)
2041 #define SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_SHIFT (13U)
2042 #define SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_MASK)
2043 #define SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_SHIFT)
2044 
2045 /*
2046  * RE_TUNE_EVENT_SIGNAL_EN (RW)
2047  *
2048  * Re-Tuning Event (UHS-I only) Signal Enable.
2049  * Values:
2050  * 0x0 (FALSE): Masked
2051  * 0x1 (TRUE): Enabled
2052  */
2053 #define SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_MASK (0x1000U)
2054 #define SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_SHIFT (12U)
2055 #define SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_MASK)
2056 #define SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_SHIFT)
2057 
2058 /*
2059  * CARD_INTERRUPT_SIGNAL_EN (RW)
2060  *
2061  * Card Interrupt Signal Enable
2062  * Values:
2063  * 0x0 (FALSE): Masked
2064  * 0x1 (TRUE): Enabled
2065  */
2066 #define SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_MASK (0x100U)
2067 #define SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_SHIFT (8U)
2068 #define SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_MASK)
2069 #define SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_SHIFT)
2070 
2071 /*
2072  * CARD_REMOVAL_SIGNAL_EN (RW)
2073  *
2074  * Card Removal Signal Enable
2075  * Values:
2076  * 0x0 (FALSE): Masked
2077  * 0x1 (TRUE): Enabled
2078  */
2079 #define SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_MASK (0x80U)
2080 #define SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_SHIFT (7U)
2081 #define SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_MASK)
2082 #define SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_SHIFT)
2083 
2084 /*
2085  * CARD_INSERTION_SIGNAL_EN (RW)
2086  *
2087  * Card Insertion Signal Enable
2088  * Values:
2089  * 0x0 (FALSE): Masked
2090  * 0x1 (TRUE): Enabled
2091  */
2092 #define SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_MASK (0x40U)
2093 #define SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_SHIFT (6U)
2094 #define SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_MASK)
2095 #define SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_SHIFT)
2096 
2097 /*
2098  * BUF_RD_READY_SIGNAL_EN (RW)
2099  *
2100  * Buffer Read Ready Signal Enable
2101  * Values:
2102  * 0x0 (FALSE): Masked
2103  * 0x1 (TRUE): Enabled
2104  */
2105 #define SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_MASK (0x20U)
2106 #define SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_SHIFT (5U)
2107 #define SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_MASK)
2108 #define SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_SHIFT)
2109 
2110 /*
2111  * BUF_WR_READY_SIGNAL_EN (RW)
2112  *
2113  * Buffer Write Ready Signal Enable
2114  * Values:
2115  * 0x0 (FALSE): Masked
2116  * 0x1 (TRUE): Enabled
2117  */
2118 #define SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_MASK (0x10U)
2119 #define SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_SHIFT (4U)
2120 #define SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_MASK)
2121 #define SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_SHIFT)
2122 
2123 /*
2124  * DMA_INTERRUPT_SIGNAL_EN (RW)
2125  *
2126  * DMA Interrupt Signal Enable
2127  * Values:
2128  * 0x0 (FALSE): Masked
2129  * 0x1 (TRUE): Enabled
2130  */
2131 #define SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_MASK (0x8U)
2132 #define SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_SHIFT (3U)
2133 #define SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_MASK)
2134 #define SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_SHIFT)
2135 
2136 /*
2137  * BGAP_EVENT_SIGNAL_EN (RW)
2138  *
2139  * Block Gap Event Signal Enable
2140  * Values:
2141  * 0x0 (FALSE): Masked
2142  * 0x1 (TRUE): Enabled
2143  */
2144 #define SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_MASK (0x4U)
2145 #define SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_SHIFT (2U)
2146 #define SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_MASK)
2147 #define SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_SHIFT)
2148 
2149 /*
2150  * XFER_COMPLETE_SIGNAL_EN (RW)
2151  *
2152  * Transfer Complete Signal Enable
2153  * Values:
2154  * 0x0 (FALSE): Masked
2155  * 0x1 (TRUE): Enabled
2156  */
2157 #define SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_MASK (0x2U)
2158 #define SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_SHIFT (1U)
2159 #define SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_MASK)
2160 #define SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_SHIFT)
2161 
2162 /*
2163  * CMD_COMPLETE_SIGNAL_EN (RW)
2164  *
2165  * Command Complete Signal Enable
2166  * Values:
2167  * 0x0 (FALSE): Masked
2168  * 0x1 (TRUE): Enabled
2169  */
2170 #define SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_MASK (0x1U)
2171 #define SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_SHIFT (0U)
2172 #define SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_MASK)
2173 #define SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_SHIFT)
2174 
2175 /* Bitfield definition for register: AC_HOST_CTRL */
2176 /*
2177  * PRESET_VAL_ENABLE (RW)
2178  *
2179  * Preset Value Enable
2180  * This bit enables automatic selection of SDCLK frequency and Driver strength Preset Value registers.
2181  * When Preset Value Enable is set, SDCLK frequency generation (Frequency Select and Clock Generator Select) and the driver strength selection are performed by the controller.
2182  * These values are selected from set of Preset Value registers based on selected speed mode.
2183  * Values:
2184  * 0x0 (FALSE): SDCLK and Driver Strength are controlled by Host Driver
2185  * 0x1 (TRUE): Automatic Selection by Preset Value are Enabled
2186  */
2187 #define SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_MASK (0x80000000UL)
2188 #define SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_SHIFT (31U)
2189 #define SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_SHIFT) & SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_MASK)
2190 #define SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_MASK) >> SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_SHIFT)
2191 
2192 /*
2193  * ASYNC_INT_ENABLE (RW)
2194  *
2195  * Asynchronous Interrupt Enable
2196  * This bit can be set if a card supports asynchronous interrupts and Asynchronous Interrupt Support is set to 1 in the Capabilities register.
2197  * Values:
2198  * 0x0 (FALSE): Disabled
2199  * 0x1 (TRUE): Enabled
2200  */
2201 #define SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_MASK (0x40000000UL)
2202 #define SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_SHIFT (30U)
2203 #define SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_SHIFT) & SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_MASK)
2204 #define SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_MASK) >> SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_SHIFT)
2205 
2206 /*
2207  * HOST_VER4_ENABLE (RW)
2208  *
2209  * Host Version 4 Enable
2210  * This bit selects either Version 3.00 compatible mode or Version 4 mode.
2211  * Functions of following fields are modified for Host Version 4 mode:
2212  * SDMA Address: SDMA uses ADMA System Address (05Fh-058h) instead of SDMA System Address register (003h-000h)
2213  * ADMA2/ADMA3 selection: ADMA3 is selected by DMA select in Host Control 1 register
2214  * 64-bit ADMA Descriptor Size: 128-bit descriptor is used instead of 96-bit descriptor when 64-bit Addressing is set to 1
2215  * Selection of 32-bit/64-bit System Addressing: Either 32-bit or 64-bit system addressing is selected by 64-bit Addressing bit in this register
2216  * 32-bit Block Count: SDMA System Address register (003h-000h) is modified to 32-bit Block Count register
2217  * Note: It is recommended not to program ADMA3 Integrated Descriptor Address registers,
2218  * UHS-II registers and Command Queuing registers (if applicable) while operating in Host version less than 4 mode (Host Version 4 Enable = 0).
2219  * Values:
2220  * 0x0 (FALSE): Version 3.00 compatible mode
2221  * 0x1 (TRUE): Version 4 mode
2222  */
2223 #define SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_MASK (0x10000000UL)
2224 #define SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_SHIFT (28U)
2225 #define SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_SHIFT) & SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_MASK)
2226 #define SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_MASK) >> SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_SHIFT)
2227 
2228 /*
2229  * CMD23_ENABLE (RW)
2230  *
2231  * CMD23 Enable
2232  * If the card supports CMD23, this bit is set to 1. This bit is used to select Auto CMD23 or Auto CMD12 for ADMA3 data transfer.
2233  * Values:
2234  * 0x0 (FALSE): Auto CMD23 is disabled
2235  * 0x1 (TRUE): Auto CMD23 is enabled
2236  */
2237 #define SDXC_AC_HOST_CTRL_CMD23_ENABLE_MASK (0x8000000UL)
2238 #define SDXC_AC_HOST_CTRL_CMD23_ENABLE_SHIFT (27U)
2239 #define SDXC_AC_HOST_CTRL_CMD23_ENABLE_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_CMD23_ENABLE_SHIFT) & SDXC_AC_HOST_CTRL_CMD23_ENABLE_MASK)
2240 #define SDXC_AC_HOST_CTRL_CMD23_ENABLE_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_CMD23_ENABLE_MASK) >> SDXC_AC_HOST_CTRL_CMD23_ENABLE_SHIFT)
2241 
2242 /*
2243  * ADMA2_LEN_MODE (RW)
2244  *
2245  * ADMA2 Length Mode
2246  * This bit selects ADMA2 Length mode to be either 16-bit or 26-bit.
2247  * Values:
2248  * 0x0 (FALSE): 16-bit Data Length Mode
2249  * 0x1 (TRUE): 26-bit Data Length Mode
2250  */
2251 #define SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_MASK (0x4000000UL)
2252 #define SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_SHIFT (26U)
2253 #define SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_SHIFT) & SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_MASK)
2254 #define SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_MASK) >> SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_SHIFT)
2255 
2256 /*
2257  * SAMPLE_CLK_SEL (RW)
2258  *
2259  * Sampling Clock Select
2260  * This bit is used by the Host Controller to select the sampling clock in SD/eMMC mode to receive CMD and DAT.
2261  * This bit is set by the tuning procedure and is valid after the completion of tuning (when Execute Tuning is cleared).
2262  * Setting this bit to 1 means that tuning is completed successfully and setting this bit to 0 means that tuning has failed.
2263  * The value is reflected on the sample_cclk_sel pin.
2264  * Values:
2265  * 0x0 (FALSE): Fixed clock is used to sample data
2266  * 0x1 (TRUE): Tuned clock is used to sample data
2267  */
2268 #define SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_MASK (0x800000UL)
2269 #define SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_SHIFT (23U)
2270 #define SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_SHIFT) & SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_MASK)
2271 #define SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_MASK) >> SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_SHIFT)
2272 
2273 /*
2274  * EXEC_TUNING (RW)
2275  *
2276  * Execute Tuning
2277  * This bit is set to 1 to start the tuning procedure in UHS-I/eMMC speed modes and this bit is automatically cleared when tuning procedure is completed.
2278  * Values:
2279  * 0x0 (FALSE): Not Tuned or Tuning completed
2280  * 0x1 (TRUE): Execute Tuning
2281  */
2282 #define SDXC_AC_HOST_CTRL_EXEC_TUNING_MASK (0x400000UL)
2283 #define SDXC_AC_HOST_CTRL_EXEC_TUNING_SHIFT (22U)
2284 #define SDXC_AC_HOST_CTRL_EXEC_TUNING_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_EXEC_TUNING_SHIFT) & SDXC_AC_HOST_CTRL_EXEC_TUNING_MASK)
2285 #define SDXC_AC_HOST_CTRL_EXEC_TUNING_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_EXEC_TUNING_MASK) >> SDXC_AC_HOST_CTRL_EXEC_TUNING_SHIFT)
2286 
2287 /*
2288  * SIGNALING_EN (RW)
2289  *
2290  * 1.8V Signaling Enable
2291  * This bit controls voltage regulator for I/O cell in UHS-I/eMMC speed modes.
2292  * Setting this bit from 0 to 1 starts changing the signal voltage from 3.3V to 1.8V.
2293  * Host Controller clears this bit if switching to 1.8 signaling fails. The value is reflected on the uhs1_swvolt_en pin.
2294  * Note: This bit must be set for all UHS-I speed modes (SDR12/SDR25/SDR50/SDR104/DDR50).
2295  * Values:
2296  * 0x0 (V_3_3): 3.3V Signalling
2297  * 0x1 (V_1_8): 1.8V Signalling
2298  */
2299 #define SDXC_AC_HOST_CTRL_SIGNALING_EN_MASK (0x80000UL)
2300 #define SDXC_AC_HOST_CTRL_SIGNALING_EN_SHIFT (19U)
2301 #define SDXC_AC_HOST_CTRL_SIGNALING_EN_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_SIGNALING_EN_SHIFT) & SDXC_AC_HOST_CTRL_SIGNALING_EN_MASK)
2302 #define SDXC_AC_HOST_CTRL_SIGNALING_EN_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_SIGNALING_EN_MASK) >> SDXC_AC_HOST_CTRL_SIGNALING_EN_SHIFT)
2303 
2304 /*
2305  * UHS_MODE_SEL (RW)
2306  *
2307  * UHS Mode/eMMC Speed Mode Select
2308  * These bits are used to select UHS mode in the SD mode of operation. In eMMC mode, these bits are used to select eMMC Speed mode.
2309  * UHS Mode (SD/UHS-II mode only):
2310  * 0x0 (SDR12): SDR12/Legacy
2311  * 0x1 (SDR25): SDR25/High Speed SDR
2312  * 0x2 (SDR50): SDR50
2313  * 0x3 (SDR104): SDR104/HS200
2314  * 0x4 (DDR50): DDR50/High Speed DDR
2315  * 0x5 (RSVD5): Reserved
2316  * 0x6 (RSVD6): Reserved
2317  * 0x7 (UHS2): UHS-II/HS400
2318  * eMMC Speed Mode (eMMC mode only):
2319  * 0x0: Legacy
2320  * 0x1: High Speed SDR
2321  * 0x2: Reserved
2322  * 0x3: HS200
2323  * 0x4: High Speed DDR
2324  * 0x5: Reserved
2325  * 0x6: Reserved
2326  * 0x7: HS400
2327  */
2328 #define SDXC_AC_HOST_CTRL_UHS_MODE_SEL_MASK (0x70000UL)
2329 #define SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SHIFT (16U)
2330 #define SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SHIFT) & SDXC_AC_HOST_CTRL_UHS_MODE_SEL_MASK)
2331 #define SDXC_AC_HOST_CTRL_UHS_MODE_SEL_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_UHS_MODE_SEL_MASK) >> SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SHIFT)
2332 
2333 /*
2334  * CMD_NOT_ISSUED_AUTO_CMD12 (RO)
2335  *
2336  * Command Not Issued By Auto CMD12 Error
2337  * If this bit is set to 1, CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register.
2338  * This bit is set to 0 when Auto CMD Error is generated by Auto CMD23.
2339  * Values:
2340  * 0x1 (TRUE): Not Issued
2341  * 0x0 (FALSE): No Error
2342  */
2343 #define SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_MASK (0x80U)
2344 #define SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT (7U)
2345 #define SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_MASK) >> SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT)
2346 
2347 /*
2348  * AUTO_CMD_RESP_ERR (RO)
2349  *
2350  * Auto CMD Response Error
2351  * This bit is set when Response Error Check Enable in the Transfer Mode register is set to 1 and an error is detected in R1 response of either Auto CMD12 or CMD13.
2352  * This status is ignored if any bit between D00 to D04 is set to 1.
2353  * Values:
2354  * 0x1 (TRUE): Error
2355  * 0x0 (FALSE): No Error
2356  */
2357 #define SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_MASK (0x20U)
2358 #define SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_SHIFT (5U)
2359 #define SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_SHIFT)
2360 
2361 /*
2362  * AUTO_CMD_IDX_ERR (RO)
2363  *
2364  * Auto CMD Index Error
2365  * This bit is set if the command index error occurs in response to a command.
2366  * Values:
2367  * 0x1 (TRUE): Error
2368  * 0x0 (FALSE): No Error
2369  */
2370 #define SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_MASK (0x10U)
2371 #define SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_SHIFT (4U)
2372 #define SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_SHIFT)
2373 
2374 /*
2375  * AUTO_CMD_EBIT_ERR (RO)
2376  *
2377  * Auto CMD End Bit Error
2378  * This bit is set when detecting that the end bit of command response is 0.
2379  * Values:
2380  * 0x1 (TRUE): End Bit Error Generated
2381  * 0x0 (FALSE): No Error
2382  */
2383 #define SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_MASK (0x8U)
2384 #define SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_SHIFT (3U)
2385 #define SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_SHIFT)
2386 
2387 /*
2388  * AUTO_CMD_CRC_ERR (RO)
2389  *
2390  * Auto CMD CRC Error
2391  * This bit is set when detecting a CRC error in the command response.
2392  * Values:
2393  * 0x1 (TRUE): CRC Error Generated
2394  * 0x0 (FALSE): No Error
2395  */
2396 #define SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_MASK (0x4U)
2397 #define SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_SHIFT (2U)
2398 #define SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_SHIFT)
2399 
2400 /*
2401  * AUTO_CMD_TOUT_ERR (RO)
2402  *
2403  * Auto CMD Timeout Error
2404  * This bit is set if no response is returned with 64 SDCLK cycles from the end bit of the command.
2405  * If this bit is set to 1, error status bits (D04-D01) are meaningless.
2406  * Values:
2407  * 0x1 (TRUE): Time out
2408  * 0x0 (FALSE): No Error
2409  */
2410 #define SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_MASK (0x2U)
2411 #define SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_SHIFT (1U)
2412 #define SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_SHIFT)
2413 
2414 /*
2415  * AUTO_CMD12_NOT_EXEC (RO)
2416  *
2417  * Auto CMD12 Not Executed
2418  * If multiple memory block data transfer is not started due to a command error, this bit is not set because it is not necessary to issue an Auto CMD12.
2419  * Setting this bit to 1 means that the Host Controller cannot issue Auto CMD12 to stop multiple memory block data transfer, due to some error.
2420  * If this bit is set to 1, error status bits (D04-D01) is meaningless.
2421  * This bit is set to 0 when Auto CMD Error is generated by Auto CMD23.
2422  * Values:
2423  * 0x1 (TRUE): Not Executed
2424  * 0x0 (FALSE): Executed
2425  */
2426 #define SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_MASK (0x1U)
2427 #define SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_SHIFT (0U)
2428 #define SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_SHIFT)
2429 
2430 /* Bitfield definition for register: CAPABILITIES1 */
2431 /*
2432  * SLOT_TYPE_R (RO)
2433  *
2434  * Slot Type
2435  * These bits indicate usage of a slot by a specific Host System.
2436  * Values:
2437  * 0x0 (REMOVABLE_SLOT): Removable Card Slot
2438  * 0x1 (EMBEDDED_SLOT): Embedded Slot for one Device
2439  * 0x2 (SHARED_SLOT): Shared Bus Slot (SD mode)
2440  * 0x3 (UHS2_EMBEDDED_SLOT): UHS-II Multiple Embedded Devices
2441  */
2442 #define SDXC_CAPABILITIES1_SLOT_TYPE_R_MASK (0xC0000000UL)
2443 #define SDXC_CAPABILITIES1_SLOT_TYPE_R_SHIFT (30U)
2444 #define SDXC_CAPABILITIES1_SLOT_TYPE_R_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_SLOT_TYPE_R_MASK) >> SDXC_CAPABILITIES1_SLOT_TYPE_R_SHIFT)
2445 
2446 /*
2447  * ASYNC_INT_SUPPORT (RO)
2448  *
2449  * Asynchronous Interrupt Support (SD Mode only)
2450  * Values:
2451  * 0x0 (FALSE): Asynchronous Interrupt Not Supported
2452  * 0x1 (TRUE): Asynchronous Interrupt Supported
2453  */
2454 #define SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_MASK (0x20000000UL)
2455 #define SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_SHIFT (29U)
2456 #define SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_MASK) >> SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_SHIFT)
2457 
2458 /*
2459  * VOLT_18 (RO)
2460  *
2461  * Voltage Support for 1.8V
2462  * Values:
2463  * 0x0 (FALSE): 1.8V Not Supported
2464  * 0x1 (TRUE): 1.8V Supported
2465  */
2466 #define SDXC_CAPABILITIES1_VOLT_18_MASK (0x4000000UL)
2467 #define SDXC_CAPABILITIES1_VOLT_18_SHIFT (26U)
2468 #define SDXC_CAPABILITIES1_VOLT_18_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_VOLT_18_MASK) >> SDXC_CAPABILITIES1_VOLT_18_SHIFT)
2469 
2470 /*
2471  * VOLT_30 (RO)
2472  *
2473  * Voltage Support for SD 3.0V or Embedded 1.2V
2474  * Values:
2475  * 0x0 (FALSE): SD 3.0V or Embedded 1.2V Not Supported
2476  * 0x1 (TRUE): SD 3.0V or Embedded Supported
2477  */
2478 #define SDXC_CAPABILITIES1_VOLT_30_MASK (0x2000000UL)
2479 #define SDXC_CAPABILITIES1_VOLT_30_SHIFT (25U)
2480 #define SDXC_CAPABILITIES1_VOLT_30_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_VOLT_30_MASK) >> SDXC_CAPABILITIES1_VOLT_30_SHIFT)
2481 
2482 /*
2483  * VOLT_33 (RO)
2484  *
2485  * Voltage Support for 3.3V
2486  * Values:
2487  * 0x0 (FALSE): 3.3V Not Supported
2488  * 0x1 (TRUE): 3.3V Supported
2489  */
2490 #define SDXC_CAPABILITIES1_VOLT_33_MASK (0x1000000UL)
2491 #define SDXC_CAPABILITIES1_VOLT_33_SHIFT (24U)
2492 #define SDXC_CAPABILITIES1_VOLT_33_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_VOLT_33_MASK) >> SDXC_CAPABILITIES1_VOLT_33_SHIFT)
2493 
2494 /*
2495  * SUS_RES_SUPPORT (RO)
2496  *
2497  * Suspense/Resume Support
2498  * This bit indicates whether the Host Controller supports Suspend/Resume functionality.
2499  * If this bit is 0, the Host Driver does not issue either Suspend or Resume commands because the Suspend and Resume mechanism is not supported.
2500  * Values:
2501  * 0x0 (FALSE): Not Supported
2502  * 0x1 (TRUE): Supported
2503  */
2504 #define SDXC_CAPABILITIES1_SUS_RES_SUPPORT_MASK (0x800000UL)
2505 #define SDXC_CAPABILITIES1_SUS_RES_SUPPORT_SHIFT (23U)
2506 #define SDXC_CAPABILITIES1_SUS_RES_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_SUS_RES_SUPPORT_MASK) >> SDXC_CAPABILITIES1_SUS_RES_SUPPORT_SHIFT)
2507 
2508 /*
2509  * SDMA_SUPPORT (RO)
2510  *
2511  * SDMA Support
2512  * This bit indicates whether the Host Controller is capable of using SDMA to transfer data between the system memory and the Host Controller directly.
2513  * Values:
2514  * 0x0 (FALSE): SDMA not Supported
2515  * 0x1 (TRUE): SDMA Supported
2516  */
2517 #define SDXC_CAPABILITIES1_SDMA_SUPPORT_MASK (0x400000UL)
2518 #define SDXC_CAPABILITIES1_SDMA_SUPPORT_SHIFT (22U)
2519 #define SDXC_CAPABILITIES1_SDMA_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_SDMA_SUPPORT_MASK) >> SDXC_CAPABILITIES1_SDMA_SUPPORT_SHIFT)
2520 
2521 /*
2522  * HIGH_SPEED_SUPPORT (RO)
2523  *
2524  * High Speed Support
2525  * This bit indicates whether the Host Controller and the Host System supports High Speed mode and they can supply the SD Clock frequency from 25 MHz to 50 MHz.
2526  * Values:
2527  * 0x0 (FALSE): High Speed not Supported
2528  * 0x1 (TRUE): High Speed Supported
2529  */
2530 #define SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_MASK (0x200000UL)
2531 #define SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_SHIFT (21U)
2532 #define SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_MASK) >> SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_SHIFT)
2533 
2534 /*
2535  * ADMA2_SUPPORT (RO)
2536  *
2537  * ADMA2 Support
2538  * This bit indicates whether the Host Controller is capable of using ADMA2.
2539  * Values:
2540  * 0x0 (FALSE): ADMA2 not Supported
2541  * 0x1 (TRUE): ADMA2 Supported
2542  */
2543 #define SDXC_CAPABILITIES1_ADMA2_SUPPORT_MASK (0x80000UL)
2544 #define SDXC_CAPABILITIES1_ADMA2_SUPPORT_SHIFT (19U)
2545 #define SDXC_CAPABILITIES1_ADMA2_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_ADMA2_SUPPORT_MASK) >> SDXC_CAPABILITIES1_ADMA2_SUPPORT_SHIFT)
2546 
2547 /*
2548  * EMBEDDED_8_BIT (RO)
2549  *
2550  * 8-bit Support for Embedded Device
2551  * This bit indicates whether the Host Controller is capable of using an 8-bit bus width mode. This bit is not effective when the Slot Type is set to 10b.
2552  * Values:
2553  * 0x0 (FALSE): 8-bit Bus Width not Supported
2554  * 0x1 (TRUE): 8-bit Bus Width Supported
2555  */
2556 #define SDXC_CAPABILITIES1_EMBEDDED_8_BIT_MASK (0x40000UL)
2557 #define SDXC_CAPABILITIES1_EMBEDDED_8_BIT_SHIFT (18U)
2558 #define SDXC_CAPABILITIES1_EMBEDDED_8_BIT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_EMBEDDED_8_BIT_MASK) >> SDXC_CAPABILITIES1_EMBEDDED_8_BIT_SHIFT)
2559 
2560 /*
2561  * MAX_BLK_LEN (RO)
2562  *
2563  * Maximum Block Length
2564  * This bit indicates the maximum block size that the Host driver can read and write to the buffer in the Host Controller.
2565  * The buffer transfers this block size without wait cycles. The transfer block length is always 512 bytes for the SD Memory irrespective of this bit
2566  * Values:
2567  * 0x0 (ZERO): 512 Byte
2568  * 0x1 (ONE): 1024 Byte
2569  * 0x2 (TWO): 2048 Byte
2570  * 0x3 (THREE): Reserved
2571  */
2572 #define SDXC_CAPABILITIES1_MAX_BLK_LEN_MASK (0x30000UL)
2573 #define SDXC_CAPABILITIES1_MAX_BLK_LEN_SHIFT (16U)
2574 #define SDXC_CAPABILITIES1_MAX_BLK_LEN_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_MAX_BLK_LEN_MASK) >> SDXC_CAPABILITIES1_MAX_BLK_LEN_SHIFT)
2575 
2576 /*
2577  * BASE_CLK_FREQ (RO)
2578  *
2579  * Base Clock Frequency for SD clock
2580  * These bits indicate the base (maximum) clock frequency for the SD Clock. The definition of these bits depend on the Host Controller Version.
2581  * 6-Bit Base Clock Frequency: This mode is supported by the Host Controller version 1.00 and 2.00.
2582  * The upper 2 bits are not effective and are always 0. The unit values are 1 MHz. The supported clock range is 10 MHz to 63 MHz.
2583  * -0x00 : Get information through another method
2584  * -0x01 : 1 MHz
2585  * -0x02 : 2 MHz
2586  * -.............
2587  * -0x3F : 63 MHz
2588  * -0x40-0xFF : Not Supported
2589  * 8-Bit Base Clock Frequency: This mode is supported by the Host Controller version 3.00. The unit values are 1 MHz. The supported clock range is 10 MHz to 255 MHz.
2590  * -0x00 : Get information through another method
2591  * -0x01 : 1 MHz
2592  * -0x02 : 2 MHz
2593  * -............
2594  * -0xFF : 255 MHz
2595  * If the frequency is 16.5 MHz, the larger value is set to 0001001b (17 MHz) because the Host Driver uses this value to calculate the clock divider value and it does not exceed the upper limit of the SD Clock frequency.
2596  * If these bits are all 0, the Host system has to get information using a different method.
2597  */
2598 #define SDXC_CAPABILITIES1_BASE_CLK_FREQ_MASK (0xFF00U)
2599 #define SDXC_CAPABILITIES1_BASE_CLK_FREQ_SHIFT (8U)
2600 #define SDXC_CAPABILITIES1_BASE_CLK_FREQ_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_BASE_CLK_FREQ_MASK) >> SDXC_CAPABILITIES1_BASE_CLK_FREQ_SHIFT)
2601 
2602 /*
2603  * TOUT_CLK_UNIT (RO)
2604  *
2605  * Timeout Clock Unit
2606  * This bit shows the unit of base clock frequency used to detect Data TImeout Error.
2607  * Values:
2608  * 0x0 (KHZ): KHz
2609  * 0x1 (MHZ): MHz
2610  */
2611 #define SDXC_CAPABILITIES1_TOUT_CLK_UNIT_MASK (0x80U)
2612 #define SDXC_CAPABILITIES1_TOUT_CLK_UNIT_SHIFT (7U)
2613 #define SDXC_CAPABILITIES1_TOUT_CLK_UNIT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_TOUT_CLK_UNIT_MASK) >> SDXC_CAPABILITIES1_TOUT_CLK_UNIT_SHIFT)
2614 
2615 /*
2616  * TOUT_CLK_FREQ (RO)
2617  *
2618  * Timeout Clock Frequency
2619  * This bit shows the base clock frequency used to detect Data Timeout Error. The Timeout Clock unit defines the unit of timeout clock frequency. It can be KHz or MHz.
2620  * 0x00 : Get information through another method
2621  * 0x01 : 1KHz / 1MHz
2622  * 0x02 : 2KHz / 2MHz
2623  * 0x03 : 3KHz / 3MHz
2624  * ...........
2625  * 0x3F : 63KHz / 63MHz
2626  */
2627 #define SDXC_CAPABILITIES1_TOUT_CLK_FREQ_MASK (0x3FU)
2628 #define SDXC_CAPABILITIES1_TOUT_CLK_FREQ_SHIFT (0U)
2629 #define SDXC_CAPABILITIES1_TOUT_CLK_FREQ_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_TOUT_CLK_FREQ_MASK) >> SDXC_CAPABILITIES1_TOUT_CLK_FREQ_SHIFT)
2630 
2631 /* Bitfield definition for register: CAPABILITIES2 */
2632 /*
2633  * VDD2_18V_SUPPORT (RO)
2634  *
2635  * 1.8V VDD2 Support
2636  * This bit indicates support of VDD2 for the Host System.
2637  * 0x0 (FALSE): 1.8V VDD2 is not Supported
2638  * 0x1 (TRUE): 1.8V VDD2 is Supported
2639  */
2640 #define SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_MASK (0x10000000UL)
2641 #define SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_SHIFT (28U)
2642 #define SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_MASK) >> SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_SHIFT)
2643 
2644 /*
2645  * ADMA3_SUPPORT (RO)
2646  *
2647  * ADMA3 Support
2648  * This bit indicates whether the Host Controller is capable of using ADMA3.
2649  * Values:
2650  * 0x0 (FALSE): ADMA3 not Supported
2651  * 0x1 (TRUE): ADMA3 Supported
2652  */
2653 #define SDXC_CAPABILITIES2_ADMA3_SUPPORT_MASK (0x8000000UL)
2654 #define SDXC_CAPABILITIES2_ADMA3_SUPPORT_SHIFT (27U)
2655 #define SDXC_CAPABILITIES2_ADMA3_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_ADMA3_SUPPORT_MASK) >> SDXC_CAPABILITIES2_ADMA3_SUPPORT_SHIFT)
2656 
2657 /*
2658  * CLK_MUL (RO)
2659  *
2660  * Clock Multiplier
2661  * These bits indicate the clock multiplier of the programmable clock generator. Setting these bits to 0 means that the Host Controller does not support a programmable clock generator.
2662  * 0x0: Clock Multiplier is not Supported
2663  * 0x1: Clock Multiplier M = 2
2664  * 0x2: Clock Multiplier M = 3
2665  * .........
2666  * 0xFF: Clock Multiplier M = 256
2667  */
2668 #define SDXC_CAPABILITIES2_CLK_MUL_MASK (0xFF0000UL)
2669 #define SDXC_CAPABILITIES2_CLK_MUL_SHIFT (16U)
2670 #define SDXC_CAPABILITIES2_CLK_MUL_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_CLK_MUL_MASK) >> SDXC_CAPABILITIES2_CLK_MUL_SHIFT)
2671 
2672 /*
2673  * RE_TUNING_MODES (RO)
2674  *
2675  * Re-Tuning Modes (UHS-I only)
2676  * These bits select the re-tuning method and limit the maximum data length.
2677  * Values:
2678  * 0x0 (MODE1): Timer
2679  * 0x1 (MODE2): Timer and Re-Tuning Request (Not supported)
2680  * 0x2 (MODE3): Auto Re-Tuning (for transfer)
2681  * 0x3 (RSVD_MODE): Reserved
2682  */
2683 #define SDXC_CAPABILITIES2_RE_TUNING_MODES_MASK (0xC000U)
2684 #define SDXC_CAPABILITIES2_RE_TUNING_MODES_SHIFT (14U)
2685 #define SDXC_CAPABILITIES2_RE_TUNING_MODES_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_RE_TUNING_MODES_MASK) >> SDXC_CAPABILITIES2_RE_TUNING_MODES_SHIFT)
2686 
2687 /*
2688  * USE_TUNING_SDR50 (RO)
2689  *
2690  * Use Tuning for SDR50 (UHS-I only)
2691  * Values:
2692  * 0x0 (ZERO): SDR50 does not require tuning
2693  * 0x1 (ONE): SDR50 requires tuning
2694  */
2695 #define SDXC_CAPABILITIES2_USE_TUNING_SDR50_MASK (0x2000U)
2696 #define SDXC_CAPABILITIES2_USE_TUNING_SDR50_SHIFT (13U)
2697 #define SDXC_CAPABILITIES2_USE_TUNING_SDR50_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_USE_TUNING_SDR50_MASK) >> SDXC_CAPABILITIES2_USE_TUNING_SDR50_SHIFT)
2698 
2699 /*
2700  * RETUNE_CNT (RO)
2701  *
2702  * Timer Count for Re-Tuning (UHS-I only)
2703  * 0x0: Re-Tuning Timer disabled
2704  * 0x1: 1 seconds
2705  * 0x2: 2 seconds
2706  * 0x3: 4 seconds
2707  * ........
2708  * 0xB: 1024 seconds
2709  * 0xC: Reserved
2710  * 0xD: Reserved
2711  * 0xE: Reserved
2712  * 0xF: Get information from other source
2713  */
2714 #define SDXC_CAPABILITIES2_RETUNE_CNT_MASK (0xF00U)
2715 #define SDXC_CAPABILITIES2_RETUNE_CNT_SHIFT (8U)
2716 #define SDXC_CAPABILITIES2_RETUNE_CNT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_RETUNE_CNT_MASK) >> SDXC_CAPABILITIES2_RETUNE_CNT_SHIFT)
2717 
2718 /*
2719  * DRV_TYPED (RO)
2720  *
2721  * Driver Type D Support (UHS-I only)
2722  * This bit indicates support of Driver Type D for 1.8 Signaling.
2723  * Values:
2724  * 0x0 (FALSE): Driver Type D is not supported
2725  * 0x1 (TRUE): Driver Type D is supported
2726  */
2727 #define SDXC_CAPABILITIES2_DRV_TYPED_MASK (0x40U)
2728 #define SDXC_CAPABILITIES2_DRV_TYPED_SHIFT (6U)
2729 #define SDXC_CAPABILITIES2_DRV_TYPED_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_DRV_TYPED_MASK) >> SDXC_CAPABILITIES2_DRV_TYPED_SHIFT)
2730 
2731 /*
2732  * DRV_TYPEC (RO)
2733  *
2734  * Driver Type C Support (UHS-I only)
2735  * This bit indicates support of Driver Type C for 1.8 Signaling.
2736  * Values:
2737  * 0x0 (FALSE): Driver Type C is not supported
2738  * 0x1 (TRUE): Driver Type C is supported
2739  */
2740 #define SDXC_CAPABILITIES2_DRV_TYPEC_MASK (0x20U)
2741 #define SDXC_CAPABILITIES2_DRV_TYPEC_SHIFT (5U)
2742 #define SDXC_CAPABILITIES2_DRV_TYPEC_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_DRV_TYPEC_MASK) >> SDXC_CAPABILITIES2_DRV_TYPEC_SHIFT)
2743 
2744 /*
2745  * DRV_TYPEA (RO)
2746  *
2747  * Driver Type A Support (UHS-I only)
2748  * This bit indicates support of Driver Type A for 1.8 Signaling.
2749  * Values:
2750  * 0x0 (FALSE): Driver Type A is not supported
2751  * 0x1 (TRUE): Driver Type A is supported
2752  */
2753 #define SDXC_CAPABILITIES2_DRV_TYPEA_MASK (0x10U)
2754 #define SDXC_CAPABILITIES2_DRV_TYPEA_SHIFT (4U)
2755 #define SDXC_CAPABILITIES2_DRV_TYPEA_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_DRV_TYPEA_MASK) >> SDXC_CAPABILITIES2_DRV_TYPEA_SHIFT)
2756 
2757 /*
2758  * UHS2_SUPPORT (RO)
2759  *
2760  * UHS-II Support (UHS-II only)
2761  * This bit indicates whether Host Controller supports UHS-II.
2762  * Values:
2763  * 0x0 (FALSE): UHS-II is not supported
2764  * 0x1 (TRUE): UHS-II is supported
2765  */
2766 #define SDXC_CAPABILITIES2_UHS2_SUPPORT_MASK (0x8U)
2767 #define SDXC_CAPABILITIES2_UHS2_SUPPORT_SHIFT (3U)
2768 #define SDXC_CAPABILITIES2_UHS2_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_UHS2_SUPPORT_MASK) >> SDXC_CAPABILITIES2_UHS2_SUPPORT_SHIFT)
2769 
2770 /*
2771  * DDR50_SUPPORT (RO)
2772  *
2773  * DDR50 Support (UHS-I only)
2774  * Values:
2775  * 0x0 (FALSE): DDR50 is not supported
2776  * 0x1 (TRUE): DDR50 is supported
2777  */
2778 #define SDXC_CAPABILITIES2_DDR50_SUPPORT_MASK (0x4U)
2779 #define SDXC_CAPABILITIES2_DDR50_SUPPORT_SHIFT (2U)
2780 #define SDXC_CAPABILITIES2_DDR50_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_DDR50_SUPPORT_MASK) >> SDXC_CAPABILITIES2_DDR50_SUPPORT_SHIFT)
2781 
2782 /*
2783  * SDR104_SUPPORT (RO)
2784  *
2785  * SDR104 Support (UHS-I only)
2786  * This bit mentions that SDR104 requires tuning.
2787  * Values:
2788  * 0x0 (FALSE): SDR104 is not supported
2789  * 0x1 (TRUE): SDR104 is supported
2790  */
2791 #define SDXC_CAPABILITIES2_SDR104_SUPPORT_MASK (0x2U)
2792 #define SDXC_CAPABILITIES2_SDR104_SUPPORT_SHIFT (1U)
2793 #define SDXC_CAPABILITIES2_SDR104_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_SDR104_SUPPORT_MASK) >> SDXC_CAPABILITIES2_SDR104_SUPPORT_SHIFT)
2794 
2795 /*
2796  * SDR50_SUPPORT (RO)
2797  *
2798  * SDR50 Support (UHS-I only)
2799  * This bit indicates that SDR50 is supported. The bit 13 (USE_TUNING_SDR50) indicates whether SDR50 requires tuning or not.
2800  * Values:
2801  * 0x0 (FALSE): SDR50 is not supported
2802  * 0x1 (TRUE): SDR50 is supported
2803  */
2804 #define SDXC_CAPABILITIES2_SDR50_SUPPORT_MASK (0x1U)
2805 #define SDXC_CAPABILITIES2_SDR50_SUPPORT_SHIFT (0U)
2806 #define SDXC_CAPABILITIES2_SDR50_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_SDR50_SUPPORT_MASK) >> SDXC_CAPABILITIES2_SDR50_SUPPORT_SHIFT)
2807 
2808 /* Bitfield definition for register: CURR_CAPABILITIES1 */
2809 /*
2810  * MAX_CUR_18V (RO)
2811  *
2812  * Maximum Current for 1.8V
2813  * This bit specifies the Maximum Current for 1.8V VDD1 power supply for the card.
2814  * 0: Get information through another method
2815  * 1: 4mA
2816  * 2: 8mA
2817  * 3: 13mA
2818  * .......
2819  * 255: 1020mA
2820  */
2821 #define SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_MASK (0xFF0000UL)
2822 #define SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_SHIFT (16U)
2823 #define SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_GET(x) (((uint32_t)(x) & SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_MASK) >> SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_SHIFT)
2824 
2825 /*
2826  * MAX_CUR_30V (RO)
2827  *
2828  * Maximum Current for 3.0V
2829  * This bit specifies the Maximum Current for 3.0V VDD1 power supply for the card.
2830  * 0: Get information through another method
2831  * 1: 4mA
2832  * 2: 8mA
2833  * 3: 13mA
2834  * .......
2835  * 255: 1020mA
2836  */
2837 #define SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_MASK (0xFF00U)
2838 #define SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_SHIFT (8U)
2839 #define SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_GET(x) (((uint32_t)(x) & SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_MASK) >> SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_SHIFT)
2840 
2841 /*
2842  * MAX_CUR_33V (RO)
2843  *
2844  * Maximum Current for 3.3V
2845  * This bit specifies the Maximum Current for 3.3V VDD1 power supply for the card.
2846  * 0: Get information through another method
2847  * 1: 4mA
2848  * 2: 8mA
2849  * 3: 13mA
2850  * .......
2851  * 255: 1020mA
2852  */
2853 #define SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_MASK (0xFFU)
2854 #define SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_SHIFT (0U)
2855 #define SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_GET(x) (((uint32_t)(x) & SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_MASK) >> SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_SHIFT)
2856 
2857 /* Bitfield definition for register: CURR_CAPABILITIES2 */
2858 /*
2859  * MAX_CUR_VDD2_18V (RO)
2860  *
2861  * Maximum Current for 1.8V VDD2
2862  * This bit specifies the Maximum Current for 1.8V VDD2 power supply for the UHS-II card.
2863  * 0: Get information through another method
2864  * 1: 4mA
2865  * 2: 8mA
2866  * 3: 13mA
2867  * .......
2868  * 255: 1020mA
2869  */
2870 #define SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_MASK (0xFFU)
2871 #define SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_SHIFT (0U)
2872 #define SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_GET(x) (((uint32_t)(x) & SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_MASK) >> SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_SHIFT)
2873 
2874 /* Bitfield definition for register: FORCE_EVENT */
2875 /*
2876  * FORCE_BOOT_ACK_ERR (WO)
2877  *
2878  * Force Event for Boot Ack error
2879  * Values:
2880  * 0x0 (FALSE): Not Affected
2881  * 0x1 (TRUE): Boot ack Error Status is set
2882  */
2883 #define SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_MASK (0x10000000UL)
2884 #define SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_SHIFT (28U)
2885 #define SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_MASK)
2886 #define SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_SHIFT)
2887 
2888 /*
2889  * FORCE_RESP_ERR (WO)
2890  *
2891  * Force Event for Response Error (SD Mode only)
2892  * Values:
2893  * 0x0 (FALSE): Not Affected
2894  * 0x1 (TRUE): Response Error Status is set
2895  */
2896 #define SDXC_FORCE_EVENT_FORCE_RESP_ERR_MASK (0x8000000UL)
2897 #define SDXC_FORCE_EVENT_FORCE_RESP_ERR_SHIFT (27U)
2898 #define SDXC_FORCE_EVENT_FORCE_RESP_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_RESP_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_RESP_ERR_MASK)
2899 #define SDXC_FORCE_EVENT_FORCE_RESP_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_RESP_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_RESP_ERR_SHIFT)
2900 
2901 /*
2902  * FORCE_TUNING_ERR (WO)
2903  *
2904  * Force Event for Tuning Error (UHS-I Mode only)
2905  * Values:
2906  * 0x0 (FALSE): Not Affected
2907  * 0x1 (TRUE): Tuning Error Status is set
2908  */
2909 #define SDXC_FORCE_EVENT_FORCE_TUNING_ERR_MASK (0x4000000UL)
2910 #define SDXC_FORCE_EVENT_FORCE_TUNING_ERR_SHIFT (26U)
2911 #define SDXC_FORCE_EVENT_FORCE_TUNING_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_TUNING_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_TUNING_ERR_MASK)
2912 #define SDXC_FORCE_EVENT_FORCE_TUNING_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_TUNING_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_TUNING_ERR_SHIFT)
2913 
2914 /*
2915  * FORCE_ADMA_ERR (WO)
2916  *
2917  * Force Event for ADMA Error
2918  * Values:
2919  * 0x0 (FALSE): Not Affected
2920  * 0x1 (TRUE): ADMA Error Status is set
2921  */
2922 #define SDXC_FORCE_EVENT_FORCE_ADMA_ERR_MASK (0x2000000UL)
2923 #define SDXC_FORCE_EVENT_FORCE_ADMA_ERR_SHIFT (25U)
2924 #define SDXC_FORCE_EVENT_FORCE_ADMA_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_ADMA_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_ADMA_ERR_MASK)
2925 #define SDXC_FORCE_EVENT_FORCE_ADMA_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_ADMA_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_ADMA_ERR_SHIFT)
2926 
2927 /*
2928  * FORCE_AUTO_CMD_ERR (WO)
2929  *
2930  * Force Event for Auto CMD Error (SD/eMMC Mode only)
2931  * Values:
2932  * 0x0 (FALSE): Not Affected
2933  * 0x1 (TRUE): Auto CMD Error Status is set
2934  */
2935 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_MASK (0x1000000UL)
2936 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_SHIFT (24U)
2937 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_MASK)
2938 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_SHIFT)
2939 
2940 /*
2941  * FORCE_CUR_LMT_ERR (WO)
2942  *
2943  * Force Event for Current Limit Error
2944  * Values:
2945  * 0x0 (FALSE): Not Affected
2946  * 0x1 (TRUE): Current Limit Error Status is set
2947  */
2948 #define SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_MASK (0x800000UL)
2949 #define SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_SHIFT (23U)
2950 #define SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_MASK)
2951 #define SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_SHIFT)
2952 
2953 /*
2954  * FORCE_DATA_END_BIT_ERR (WO)
2955  *
2956  * Force Event for Data End Bit Error (SD/eMMC Mode only)
2957  * Values:
2958  * 0x0 (FALSE): Not Affected
2959  * 0x1 (TRUE): Data End Bit Error Status is set
2960  */
2961 #define SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_MASK (0x400000UL)
2962 #define SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_SHIFT (22U)
2963 #define SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_MASK)
2964 #define SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_SHIFT)
2965 
2966 /*
2967  * FORCE_DATA_CRC_ERR (WO)
2968  *
2969  * Force Event for Data CRC Error (SD/eMMC Mode only)
2970  * Values:
2971  * 0x0 (FALSE): Not Affected
2972  * 0x1 (TRUE): Data CRC Error Status is set
2973  */
2974 #define SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_MASK (0x200000UL)
2975 #define SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_SHIFT (21U)
2976 #define SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_MASK)
2977 #define SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_SHIFT)
2978 
2979 /*
2980  * FORCE_DATA_TOUT_ERR (WO)
2981  *
2982  * Force Event for Data Timeout Error (SD/eMMC Mode only)
2983  * Values:
2984  * 0x0 (FALSE): Not Affected
2985  * 0x1 (TRUE): Data Timeout Error Status is set
2986  */
2987 #define SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_MASK (0x100000UL)
2988 #define SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_SHIFT (20U)
2989 #define SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_MASK)
2990 #define SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_SHIFT)
2991 
2992 /*
2993  * FORCE_CMD_IDX_ERR (WO)
2994  *
2995  * Force Event for Command Index Error (SD/eMMC Mode only)
2996  * Values:
2997  * 0x0 (FALSE): Not Affected
2998  * 0x1 (TRUE): Command Index Error Status is set
2999  */
3000 #define SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_MASK (0x80000UL)
3001 #define SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_SHIFT (19U)
3002 #define SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_MASK)
3003 #define SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_SHIFT)
3004 
3005 /*
3006  * FORCE_CMD_END_BIT_ERR (WO)
3007  *
3008  * Force Event for Command End Bit Error (SD/eMMC Mode only)
3009  * Values:
3010  * 0x0 (FALSE): Not Affected
3011  * 0x1 (TRUE): Command End Bit Error Status is set
3012  */
3013 #define SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_MASK (0x40000UL)
3014 #define SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_SHIFT (18U)
3015 #define SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_MASK)
3016 #define SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_SHIFT)
3017 
3018 /*
3019  * FORCE_CMD_CRC_ERR (WO)
3020  *
3021  * Force Event for Command CRC Error (SD/eMMC Mode only)
3022  * Values:
3023  * 0x0 (FALSE): Not Affected
3024  * 0x1 (TRUE): Command CRC Error Status is set
3025  */
3026 #define SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_MASK (0x20000UL)
3027 #define SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_SHIFT (17U)
3028 #define SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_MASK)
3029 #define SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_SHIFT)
3030 
3031 /*
3032  * FORCE_CMD_TOUT_ERR (WO)
3033  *
3034  * Force Event for Command Timeout Error (SD/eMMC Mode only)
3035  * Values:
3036  * 0x0 (FALSE): Not Affected
3037  * 0x1 (TRUE): Command Timeout Error Status is set
3038  */
3039 #define SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_MASK (0x10000UL)
3040 #define SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_SHIFT (16U)
3041 #define SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_MASK)
3042 #define SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_SHIFT)
3043 
3044 /*
3045  * FORCE_CMD_NOT_ISSUED_AUTO_CMD12 (WO)
3046  *
3047  * Force Event for Command Not Issued By Auto CMD12 Error
3048  * Values:
3049  * 0x1 (TRUE): Command Not Issued By Auto CMD12 Error Status is set
3050  * 0x0 (FALSE): Not Affected
3051  */
3052 #define SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_MASK (0x80U)
3053 #define SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT (7U)
3054 #define SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_MASK)
3055 #define SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT)
3056 
3057 /*
3058  * FORCE_AUTO_CMD_RESP_ERR (WO)
3059  *
3060  * Force Event for Auto CMD Response Error
3061  * Values:
3062  * 0x1 (TRUE): Auto CMD Response Error Status is set
3063  * 0x0 (FALSE): Not Affected
3064  */
3065 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_MASK (0x20U)
3066 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_SHIFT (5U)
3067 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_MASK)
3068 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_SHIFT)
3069 
3070 /*
3071  * FORCE_AUTO_CMD_IDX_ERR (WO)
3072  *
3073  * Force Event for Auto CMD Index Error
3074  * Values:
3075  * 0x1 (TRUE): Auto CMD Index Error Status is set
3076  * 0x0 (FALSE): Not Affected
3077  */
3078 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_MASK (0x10U)
3079 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_SHIFT (4U)
3080 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_MASK)
3081 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_SHIFT)
3082 
3083 /*
3084  * FORCE_AUTO_CMD_EBIT_ERR (WO)
3085  *
3086  * Force Event for Auto CMD End Bit Error
3087  * Values:
3088  * 0x1 (TRUE): Auto CMD End Bit Error Status is set
3089  * 0x0 (FALSE): Not Affected
3090  */
3091 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_MASK (0x8U)
3092 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_SHIFT (3U)
3093 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_MASK)
3094 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_SHIFT)
3095 
3096 /*
3097  * FORCE_AUTO_CMD_CRC_ERR (WO)
3098  *
3099  * Force Event for Auto CMD CRC Error
3100  * Values:
3101  * 0x1 (TRUE): Auto CMD CRC Error Status is set
3102  * 0x0 (FALSE): Not Affected
3103  */
3104 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_MASK (0x4U)
3105 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_SHIFT (2U)
3106 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_MASK)
3107 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_SHIFT)
3108 
3109 /*
3110  * FORCE_AUTO_CMD_TOUT_ERR (WO)
3111  *
3112  * Force Event for Auto CMD Timeout Error
3113  * Values:
3114  * 0x1 (TRUE): Auto CMD Timeout Error Status is set
3115  * 0x0 (FALSE): Not Affected
3116  */
3117 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_MASK (0x2U)
3118 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_SHIFT (1U)
3119 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_MASK)
3120 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_SHIFT)
3121 
3122 /*
3123  * FORCE_AUTO_CMD12_NOT_EXEC (WO)
3124  *
3125  * Force Event for Auto CMD12 Not Executed
3126  * Values:
3127  * 0x1 (TRUE): Auto CMD12 Not Executed Status is set
3128  * 0x0 (FALSE): Not Affected
3129  */
3130 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_MASK (0x1U)
3131 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_SHIFT (0U)
3132 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_MASK)
3133 #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_SHIFT)
3134 
3135 /* Bitfield definition for register: ADMA_ERR_STAT */
3136 /*
3137  * ADMA_LEN_ERR (RO)
3138  *
3139  * ADMA Length Mismatch Error States
3140  * This error occurs in the following instances:
3141  * While the Block Count Enable is being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length
3142  * When the total data length cannot be divided by the block length
3143  * Values:
3144  * 0x0 (NO_ERR): No Error
3145  * 0x1 (ERROR): Error
3146  */
3147 #define SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_MASK (0x4U)
3148 #define SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_SHIFT (2U)
3149 #define SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_GET(x) (((uint32_t)(x) & SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_MASK) >> SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_SHIFT)
3150 
3151 /*
3152  * ADMA_ERR_STATES (RO)
3153  *
3154  * ADMA Error States
3155  * These bits indicate the state of ADMA when an error occurs during ADMA data transfer.
3156  * Values:
3157  * 0x0 (ST_STOP): Stop DMA - SYS_ADR register points to a location next to the error descriptor
3158  * 0x1 (ST_FDS): Fetch Descriptor - SYS_ADR register points to the error descriptor
3159  * 0x2 (UNUSED): Never set this state
3160  * 0x3 (ST_TFR): Transfer Data - SYS_ADR register points to a location next to the error descriptor
3161  */
3162 #define SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_MASK (0x3U)
3163 #define SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_SHIFT (0U)
3164 #define SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_GET(x) (((uint32_t)(x) & SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_MASK) >> SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_SHIFT)
3165 
3166 /* Bitfield definition for register: ADMA_SYS_ADDR */
3167 /*
3168  * ADMA_SA (RW)
3169  *
3170  * ADMA System Address
3171  * These bits indicate the lower 32 bits of the ADMA system address.
3172  * SDMA: If Host Version 4 Enable is set to 1, this register stores the system address of the data location
3173  * ADMA2: This register stores the byte address of the executing command of the descriptor table
3174  * ADMA3: This register is set by ADMA3. ADMA2 increments the address of this register that points to the next line, every time a Descriptor line is fetched.
3175  */
3176 #define SDXC_ADMA_SYS_ADDR_ADMA_SA_MASK (0xFFFFFFFFUL)
3177 #define SDXC_ADMA_SYS_ADDR_ADMA_SA_SHIFT (0U)
3178 #define SDXC_ADMA_SYS_ADDR_ADMA_SA_SET(x) (((uint32_t)(x) << SDXC_ADMA_SYS_ADDR_ADMA_SA_SHIFT) & SDXC_ADMA_SYS_ADDR_ADMA_SA_MASK)
3179 #define SDXC_ADMA_SYS_ADDR_ADMA_SA_GET(x) (((uint32_t)(x) & SDXC_ADMA_SYS_ADDR_ADMA_SA_MASK) >> SDXC_ADMA_SYS_ADDR_ADMA_SA_SHIFT)
3180 
3181 /* Bitfield definition for register array: PRESET */
3182 /*
3183  * CLK_GEN_SEL_VAL (RO)
3184  *
3185  * Clock Generator Select Value
3186  * This bit is effective when the Host Controller supports a programmable clock generator.
3187  * Values:
3188  * 0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator
3189  * 0x1 (PROG): Programmable Clock Generator
3190  */
3191 #define SDXC_PRESET_CLK_GEN_SEL_VAL_MASK (0x400U)
3192 #define SDXC_PRESET_CLK_GEN_SEL_VAL_SHIFT (10U)
3193 #define SDXC_PRESET_CLK_GEN_SEL_VAL_GET(x) (((uint16_t)(x) & SDXC_PRESET_CLK_GEN_SEL_VAL_MASK) >> SDXC_PRESET_CLK_GEN_SEL_VAL_SHIFT)
3194 
3195 /*
3196  * FREQ_SEL_VAL (RO)
3197  *
3198  * SDCLK/RCLK Frequency Select Value
3199  * 10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System.
3200  */
3201 #define SDXC_PRESET_FREQ_SEL_VAL_MASK (0x3FFU)
3202 #define SDXC_PRESET_FREQ_SEL_VAL_SHIFT (0U)
3203 #define SDXC_PRESET_FREQ_SEL_VAL_GET(x) (((uint16_t)(x) & SDXC_PRESET_FREQ_SEL_VAL_MASK) >> SDXC_PRESET_FREQ_SEL_VAL_SHIFT)
3204 
3205 /* Bitfield definition for register: ADMA_ID_ADDR */
3206 /*
3207  * ADMA_ID_ADDR (RW)
3208  *
3209  * ADMA Integrated Descriptor Address
3210  * These bits indicate the lower 32-bit of the ADMA Integrated Descriptor address.
3211  * The start address of Integrated Descriptor is set to these register bits.
3212  * The ADMA3 fetches one Descriptor Address and increments these bits to indicate the next Descriptor address.
3213  */
3214 #define SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_MASK (0xFFFFFFFFUL)
3215 #define SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_SHIFT (0U)
3216 #define SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_SET(x) (((uint32_t)(x) << SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_SHIFT) & SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_MASK)
3217 #define SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_GET(x) (((uint32_t)(x) & SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_MASK) >> SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_SHIFT)
3218 
3219 /* Bitfield definition for register: P_EMBEDDED_CNTRL */
3220 /*
3221  * REG_OFFSET_ADDR (RO)
3222  *
3223  * Offset Address of Embedded Control register.
3224  */
3225 #define SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_MASK (0xFFFU)
3226 #define SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_SHIFT (0U)
3227 #define SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_GET(x) (((uint16_t)(x) & SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_MASK) >> SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_SHIFT)
3228 
3229 /* Bitfield definition for register: P_VENDOR_SPECIFIC_AREA */
3230 /*
3231  * REG_OFFSET_ADDR (RO)
3232  *
3233  * Base offset Address for Vendor-Specific registers.
3234  */
3235 #define SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_MASK (0xFFFU)
3236 #define SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_SHIFT (0U)
3237 #define SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_GET(x) (((uint16_t)(x) & SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_MASK) >> SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_SHIFT)
3238 
3239 /* Bitfield definition for register: P_VENDOR2_SPECIFIC_AREA */
3240 /*
3241  * REG_OFFSET_ADDR (RO)
3242  *
3243  * Base offset Address for Command Queuing registers.
3244  */
3245 #define SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_MASK (0xFFFFU)
3246 #define SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_SHIFT (0U)
3247 #define SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_GET(x) (((uint16_t)(x) & SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_MASK) >> SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_SHIFT)
3248 
3249 /* Bitfield definition for register: SLOT_INTR_STATUS */
3250 /*
3251  * INTR_SLOT (RO)
3252  *
3253  * Interrupt signal for each Slot
3254  * These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot.
3255  * A maximum of 8 slots can be defined. If one interrupt signal is associated with multiple slots, the Host Driver can identify the interrupt that is generated by reading these bits.
3256  * By a power on reset or by setting Software Reset For All bit, the interrupt signals are de-asserted and this status reads 00h.
3257  * Bit 00: Slot 1
3258  * Bit 01: Slot 2
3259  * Bit 02: Slot 3
3260  * ..........
3261  * ..........
3262  * Bit 07: Slot 8
3263  * Note: MSHC Host Controller support single card slot. This register shall always return 0.
3264  */
3265 #define SDXC_SLOT_INTR_STATUS_INTR_SLOT_MASK (0xFFU)
3266 #define SDXC_SLOT_INTR_STATUS_INTR_SLOT_SHIFT (0U)
3267 #define SDXC_SLOT_INTR_STATUS_INTR_SLOT_GET(x) (((uint16_t)(x) & SDXC_SLOT_INTR_STATUS_INTR_SLOT_MASK) >> SDXC_SLOT_INTR_STATUS_INTR_SLOT_SHIFT)
3268 
3269 /* Bitfield definition for register: CQVER */
3270 /*
3271  * EMMC_VER_MAHOR (RO)
3272  *
3273  * This bit indicates the eMMC major version (1st digit left of decimal point) in BCD format.
3274  */
3275 #define SDXC_CQVER_EMMC_VER_MAHOR_MASK (0xF00U)
3276 #define SDXC_CQVER_EMMC_VER_MAHOR_SHIFT (8U)
3277 #define SDXC_CQVER_EMMC_VER_MAHOR_GET(x) (((uint32_t)(x) & SDXC_CQVER_EMMC_VER_MAHOR_MASK) >> SDXC_CQVER_EMMC_VER_MAHOR_SHIFT)
3278 
3279 /*
3280  * EMMC_VER_MINOR (RO)
3281  *
3282  * This bit indicates the eMMC minor version (1st digit right of decimal point) in BCD format.
3283  */
3284 #define SDXC_CQVER_EMMC_VER_MINOR_MASK (0xF0U)
3285 #define SDXC_CQVER_EMMC_VER_MINOR_SHIFT (4U)
3286 #define SDXC_CQVER_EMMC_VER_MINOR_GET(x) (((uint32_t)(x) & SDXC_CQVER_EMMC_VER_MINOR_MASK) >> SDXC_CQVER_EMMC_VER_MINOR_SHIFT)
3287 
3288 /*
3289  * EMMC_VER_SUFFIX (RO)
3290  *
3291  * This bit indicates the eMMC version suffix (2nd digit right of decimal point) in BCD format.
3292  */
3293 #define SDXC_CQVER_EMMC_VER_SUFFIX_MASK (0xFU)
3294 #define SDXC_CQVER_EMMC_VER_SUFFIX_SHIFT (0U)
3295 #define SDXC_CQVER_EMMC_VER_SUFFIX_GET(x) (((uint32_t)(x) & SDXC_CQVER_EMMC_VER_SUFFIX_MASK) >> SDXC_CQVER_EMMC_VER_SUFFIX_SHIFT)
3296 
3297 /* Bitfield definition for register: CQCAP */
3298 /*
3299  * CRYPTO_SUPPORT (RO)
3300  *
3301  * Crypto Support
3302  * This bit indicates whether the Host Controller supports cryptographic operations.
3303  * Values:
3304  * 0x0 (FALSE): Crypto not Supported
3305  * 0x1 (TRUE): Crypto Supported
3306  */
3307 #define SDXC_CQCAP_CRYPTO_SUPPORT_MASK (0x10000000UL)
3308 #define SDXC_CQCAP_CRYPTO_SUPPORT_SHIFT (28U)
3309 #define SDXC_CQCAP_CRYPTO_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CQCAP_CRYPTO_SUPPORT_MASK) >> SDXC_CQCAP_CRYPTO_SUPPORT_SHIFT)
3310 
3311 /*
3312  * ITCFMUL (RO)
3313  *
3314  * Internal Timer Clock Frequency Multiplier (ITCFMUL)
3315  * This field indicates the frequency of the clock used for interrupt coalescing timer and for determining the SQS
3316  * polling period. See ITCFVAL definition for details. Values 0x5 to 0xF are reserved.
3317  * Values:
3318  * 0x0 (CLK_1KHz): 1KHz clock
3319  * 0x1 (CLK_10KHz): 10KHz clock
3320  * 0x2 (CLK_100KHz): 100KHz clock
3321  * 0x3 (CLK_1MHz): 1MHz clock
3322  * 0x4 (CLK_10MHz): 10MHz clock
3323  */
3324 #define SDXC_CQCAP_ITCFMUL_MASK (0xF000U)
3325 #define SDXC_CQCAP_ITCFMUL_SHIFT (12U)
3326 #define SDXC_CQCAP_ITCFMUL_GET(x) (((uint32_t)(x) & SDXC_CQCAP_ITCFMUL_MASK) >> SDXC_CQCAP_ITCFMUL_SHIFT)
3327 
3328 /*
3329  * ITCFVAL (RO)
3330  *
3331  * Internal Timer Clock Frequency Value (ITCFVAL)
3332  * This field scales the frequency of the timer clock provided by ITCFMUL. The Final clock frequency of actual timer clock is calculated as ITCFVAL* ITCFMUL.
3333  */
3334 #define SDXC_CQCAP_ITCFVAL_MASK (0x3FFU)
3335 #define SDXC_CQCAP_ITCFVAL_SHIFT (0U)
3336 #define SDXC_CQCAP_ITCFVAL_GET(x) (((uint32_t)(x) & SDXC_CQCAP_ITCFVAL_MASK) >> SDXC_CQCAP_ITCFVAL_SHIFT)
3337 
3338 /* Bitfield definition for register: CQCFG */
3339 /*
3340  * DCMD_EN (RW)
3341  *
3342  * This bit indicates to the hardware whether the Task
3343  * Descriptor in slot #31 of the TDL is a data transfer descriptor or a direct-command descriptor. CQE uses this bit when a task is issued in slot #31, to determine how to decode the Task Descriptor.
3344  * Values:
3345  * 0x1 (SLOT31_DCMD_ENABLE): Task descriptor in slot #31 is a DCMD Task Descriptor
3346  * 0x0 (SLOT31_DCMD_DISABLE): Task descriptor in slot #31 is a data Transfer Task Descriptor
3347  */
3348 #define SDXC_CQCFG_DCMD_EN_MASK (0x1000U)
3349 #define SDXC_CQCFG_DCMD_EN_SHIFT (12U)
3350 #define SDXC_CQCFG_DCMD_EN_SET(x) (((uint32_t)(x) << SDXC_CQCFG_DCMD_EN_SHIFT) & SDXC_CQCFG_DCMD_EN_MASK)
3351 #define SDXC_CQCFG_DCMD_EN_GET(x) (((uint32_t)(x) & SDXC_CQCFG_DCMD_EN_MASK) >> SDXC_CQCFG_DCMD_EN_SHIFT)
3352 
3353 /*
3354  * TASK_DESC_SIZE (RW)
3355  *
3356  * Bit Value Description
3357  * This bit indicates the size of task descriptor used in host memory. This bit can only be configured when Command Queuing Enable bit is 0 (command queuing is disabled).
3358  * Values:
3359  * 0x1 (TASK_DESC_128b): Task descriptor size is 128 bits
3360  * 0x0 (TASK_DESC_64b): Task descriptor size is 64 bit
3361  */
3362 #define SDXC_CQCFG_TASK_DESC_SIZE_MASK (0x100U)
3363 #define SDXC_CQCFG_TASK_DESC_SIZE_SHIFT (8U)
3364 #define SDXC_CQCFG_TASK_DESC_SIZE_SET(x) (((uint32_t)(x) << SDXC_CQCFG_TASK_DESC_SIZE_SHIFT) & SDXC_CQCFG_TASK_DESC_SIZE_MASK)
3365 #define SDXC_CQCFG_TASK_DESC_SIZE_GET(x) (((uint32_t)(x) & SDXC_CQCFG_TASK_DESC_SIZE_MASK) >> SDXC_CQCFG_TASK_DESC_SIZE_SHIFT)
3366 
3367 /*
3368  * CQ_EN (RW)
3369  *
3370  */
3371 #define SDXC_CQCFG_CQ_EN_MASK (0x1U)
3372 #define SDXC_CQCFG_CQ_EN_SHIFT (0U)
3373 #define SDXC_CQCFG_CQ_EN_SET(x) (((uint32_t)(x) << SDXC_CQCFG_CQ_EN_SHIFT) & SDXC_CQCFG_CQ_EN_MASK)
3374 #define SDXC_CQCFG_CQ_EN_GET(x) (((uint32_t)(x) & SDXC_CQCFG_CQ_EN_MASK) >> SDXC_CQCFG_CQ_EN_SHIFT)
3375 
3376 /* Bitfield definition for register: CQCTL */
3377 /*
3378  * CLR_ALL_TASKS (RW)
3379  *
3380  * Clear all tasks
3381  * This bit can only be written when the controller is halted. This bit does not clear tasks in the device. The software has to use the CMDQ_TASK_MGMT command to clear device's queue.
3382  * Values:
3383  * 0x1 (CLEAR_ALL_TASKS): Clears all the tasks in the controller
3384  * 0x0 (NO_EFFECT): Programming 0 has no effect
3385  */
3386 #define SDXC_CQCTL_CLR_ALL_TASKS_MASK (0x100U)
3387 #define SDXC_CQCTL_CLR_ALL_TASKS_SHIFT (8U)
3388 #define SDXC_CQCTL_CLR_ALL_TASKS_SET(x) (((uint32_t)(x) << SDXC_CQCTL_CLR_ALL_TASKS_SHIFT) & SDXC_CQCTL_CLR_ALL_TASKS_MASK)
3389 #define SDXC_CQCTL_CLR_ALL_TASKS_GET(x) (((uint32_t)(x) & SDXC_CQCTL_CLR_ALL_TASKS_MASK) >> SDXC_CQCTL_CLR_ALL_TASKS_SHIFT)
3390 
3391 /*
3392  * HALT (RW)
3393  *
3394  * Halt request and resume
3395  * Values:
3396  * 0x1 (HALT_CQE): Software writes 1 to this bit when it wants to acquire software control over the eMMC bus and to disable CQE from issuing command on the bus.
3397  * For example, issuing a Discard Task command (CMDQ_TASK_MGMT).
3398  * When the software writes 1, CQE completes the ongoing task (if any in progress).
3399  * After the task is completed and the CQE is in idle state, CQE does not issue new commands and indicates to the software by setting this bit to 1.
3400  * The software can poll on this bit until it is set to 1 and only then send commands on the eMMC bus.
3401  * 0x0 (RESUME_CQE): Software writes 0 to this bit to exit from the halt state and resume CQE activity
3402  */
3403 #define SDXC_CQCTL_HALT_MASK (0x1U)
3404 #define SDXC_CQCTL_HALT_SHIFT (0U)
3405 #define SDXC_CQCTL_HALT_SET(x) (((uint32_t)(x) << SDXC_CQCTL_HALT_SHIFT) & SDXC_CQCTL_HALT_MASK)
3406 #define SDXC_CQCTL_HALT_GET(x) (((uint32_t)(x) & SDXC_CQCTL_HALT_MASK) >> SDXC_CQCTL_HALT_SHIFT)
3407 
3408 /* Bitfield definition for register: CQIS */
3409 /*
3410  * TCL (RW)
3411  *
3412  * Task cleared interrupt
3413  * This status bit is asserted (if CQISE.TCL_STE=1) when a task clear operation is completed by CQE.
3414  * The completed task clear operation is either an individual task clear (by writing CQTCLR) or clearing of all tasks (by writing CQCTL).
3415  * A value of 1 clears this status bit.
3416  * Values:
3417  * 0x1 (SET): TCL Interrupt is set
3418  * 0x0 (NOTSET): TCL Interrupt is not set
3419  */
3420 #define SDXC_CQIS_TCL_MASK (0x8U)
3421 #define SDXC_CQIS_TCL_SHIFT (3U)
3422 #define SDXC_CQIS_TCL_SET(x) (((uint32_t)(x) << SDXC_CQIS_TCL_SHIFT) & SDXC_CQIS_TCL_MASK)
3423 #define SDXC_CQIS_TCL_GET(x) (((uint32_t)(x) & SDXC_CQIS_TCL_MASK) >> SDXC_CQIS_TCL_SHIFT)
3424 
3425 /*
3426  * RED (RW)
3427  *
3428  * Response error detected interrupt
3429  * This status bit is asserted (if CQISE.RED_STE=1) when a response is received with an error bit set in the device status
3430  * field. Configure the CQRMEM register to identify device status bit fields that may trigger an interrupt and that are masked.
3431  * A value of 1 clears this status bit.
3432  * Values:
3433  * 0x1 (SET): RED Interrupt is set
3434  * 0x0 (NOTSET): RED Interrupt is not set
3435  */
3436 #define SDXC_CQIS_RED_MASK (0x4U)
3437 #define SDXC_CQIS_RED_SHIFT (2U)
3438 #define SDXC_CQIS_RED_SET(x) (((uint32_t)(x) << SDXC_CQIS_RED_SHIFT) & SDXC_CQIS_RED_MASK)
3439 #define SDXC_CQIS_RED_GET(x) (((uint32_t)(x) & SDXC_CQIS_RED_MASK) >> SDXC_CQIS_RED_SHIFT)
3440 
3441 /*
3442  * TCC (RW)
3443  *
3444  * Task complete interrupt
3445  * This status bit is asserted (if CQISE.TCC_STE=1) when at least one of the following conditions are met:
3446  * A task is completed and the INT bit is set in its Task Descriptor
3447  * Interrupt caused by Interrupt Coalescing logic due to timeout
3448  * Interrupt Coalescing logic reached the configured threshold
3449  * A value of 1 clears this status bit
3450  */
3451 #define SDXC_CQIS_TCC_MASK (0x2U)
3452 #define SDXC_CQIS_TCC_SHIFT (1U)
3453 #define SDXC_CQIS_TCC_SET(x) (((uint32_t)(x) << SDXC_CQIS_TCC_SHIFT) & SDXC_CQIS_TCC_MASK)
3454 #define SDXC_CQIS_TCC_GET(x) (((uint32_t)(x) & SDXC_CQIS_TCC_MASK) >> SDXC_CQIS_TCC_SHIFT)
3455 
3456 /*
3457  * HAC (RW)
3458  *
3459  * Halt complete interrupt
3460  * This status bit is asserted (only if CQISE.HAC_STE=1) when halt bit in the CQCTL register transitions from 0 to 1 indicating that the host controller has completed its current ongoing task and has entered halt state.
3461  * A value of 1 clears this status bit.
3462  * Values:
3463  * 0x1 (SET): HAC Interrupt is set
3464  * 0x0 (NOTSET): HAC Interrupt is not set
3465  */
3466 #define SDXC_CQIS_HAC_MASK (0x1U)
3467 #define SDXC_CQIS_HAC_SHIFT (0U)
3468 #define SDXC_CQIS_HAC_SET(x) (((uint32_t)(x) << SDXC_CQIS_HAC_SHIFT) & SDXC_CQIS_HAC_MASK)
3469 #define SDXC_CQIS_HAC_GET(x) (((uint32_t)(x) & SDXC_CQIS_HAC_MASK) >> SDXC_CQIS_HAC_SHIFT)
3470 
3471 /* Bitfield definition for register: CQISE */
3472 /*
3473  * TCL_STE (RW)
3474  *
3475  * Task cleared interrupt status enable
3476  * Values:
3477  * 0x1 (INT_STS_ENABLE): CQIS.TCL is set when its interrupt condition is active
3478  * 0x0 (INT_STS_DISABLE): CQIS.TCL is disabled
3479  */
3480 #define SDXC_CQISE_TCL_STE_MASK (0x8U)
3481 #define SDXC_CQISE_TCL_STE_SHIFT (3U)
3482 #define SDXC_CQISE_TCL_STE_SET(x) (((uint32_t)(x) << SDXC_CQISE_TCL_STE_SHIFT) & SDXC_CQISE_TCL_STE_MASK)
3483 #define SDXC_CQISE_TCL_STE_GET(x) (((uint32_t)(x) & SDXC_CQISE_TCL_STE_MASK) >> SDXC_CQISE_TCL_STE_SHIFT)
3484 
3485 /*
3486  * RED_STE (RW)
3487  *
3488  * Response error detected interrupt status enable
3489  * Values:
3490  * 0x1 (INT_STS_ENABLE): CQIS.RED is set when its interrupt condition is active
3491  * 0x0 (INT_STS_DISABLE): CQIS.RED is disabled
3492  */
3493 #define SDXC_CQISE_RED_STE_MASK (0x4U)
3494 #define SDXC_CQISE_RED_STE_SHIFT (2U)
3495 #define SDXC_CQISE_RED_STE_SET(x) (((uint32_t)(x) << SDXC_CQISE_RED_STE_SHIFT) & SDXC_CQISE_RED_STE_MASK)
3496 #define SDXC_CQISE_RED_STE_GET(x) (((uint32_t)(x) & SDXC_CQISE_RED_STE_MASK) >> SDXC_CQISE_RED_STE_SHIFT)
3497 
3498 /*
3499  * TCC_STE (RW)
3500  *
3501  * Task complete interrupt status enable
3502  * Values:
3503  * 0x1 (INT_STS_ENABLE): CQIS.TCC is set when its interrupt condition is active
3504  * 0x0 (INT_STS_DISABLE): CQIS.TCC is disabled
3505  */
3506 #define SDXC_CQISE_TCC_STE_MASK (0x2U)
3507 #define SDXC_CQISE_TCC_STE_SHIFT (1U)
3508 #define SDXC_CQISE_TCC_STE_SET(x) (((uint32_t)(x) << SDXC_CQISE_TCC_STE_SHIFT) & SDXC_CQISE_TCC_STE_MASK)
3509 #define SDXC_CQISE_TCC_STE_GET(x) (((uint32_t)(x) & SDXC_CQISE_TCC_STE_MASK) >> SDXC_CQISE_TCC_STE_SHIFT)
3510 
3511 /*
3512  * HAC_STE (RW)
3513  *
3514  * Halt complete interrupt status enable
3515  * Values:
3516  * 0x1 (INT_STS_ENABLE): CQIS.HAC is set when its interrupt condition is active
3517  * 0x0 (INT_STS_DISABLE): CQIS.HAC is disabled
3518  */
3519 #define SDXC_CQISE_HAC_STE_MASK (0x1U)
3520 #define SDXC_CQISE_HAC_STE_SHIFT (0U)
3521 #define SDXC_CQISE_HAC_STE_SET(x) (((uint32_t)(x) << SDXC_CQISE_HAC_STE_SHIFT) & SDXC_CQISE_HAC_STE_MASK)
3522 #define SDXC_CQISE_HAC_STE_GET(x) (((uint32_t)(x) & SDXC_CQISE_HAC_STE_MASK) >> SDXC_CQISE_HAC_STE_SHIFT)
3523 
3524 /* Bitfield definition for register: CQISGE */
3525 /*
3526  * TCL_SGE (RW)
3527  *
3528  * Task cleared interrupt signal enable
3529  * Values:
3530  * 0x1 (INT_SIG_ENABLE): CQIS.TCL interrupt signal generation is active
3531  * 0x0 (INT_SIG_DISABLE): CQIS.TCL interrupt signal generation is disabled
3532  */
3533 #define SDXC_CQISGE_TCL_SGE_MASK (0x8U)
3534 #define SDXC_CQISGE_TCL_SGE_SHIFT (3U)
3535 #define SDXC_CQISGE_TCL_SGE_SET(x) (((uint32_t)(x) << SDXC_CQISGE_TCL_SGE_SHIFT) & SDXC_CQISGE_TCL_SGE_MASK)
3536 #define SDXC_CQISGE_TCL_SGE_GET(x) (((uint32_t)(x) & SDXC_CQISGE_TCL_SGE_MASK) >> SDXC_CQISGE_TCL_SGE_SHIFT)
3537 
3538 /*
3539  * RED_SGE (RW)
3540  *
3541  * Response error detected interrupt signal enable
3542  * Values:
3543  * 0x1 (INT_SIG_ENABLE): CQIS.RED interrupt signal generation is active
3544  * 0x0 (INT_SIG_DISABLE): CQIS.RED interrupt signal generation is disabled
3545  */
3546 #define SDXC_CQISGE_RED_SGE_MASK (0x4U)
3547 #define SDXC_CQISGE_RED_SGE_SHIFT (2U)
3548 #define SDXC_CQISGE_RED_SGE_SET(x) (((uint32_t)(x) << SDXC_CQISGE_RED_SGE_SHIFT) & SDXC_CQISGE_RED_SGE_MASK)
3549 #define SDXC_CQISGE_RED_SGE_GET(x) (((uint32_t)(x) & SDXC_CQISGE_RED_SGE_MASK) >> SDXC_CQISGE_RED_SGE_SHIFT)
3550 
3551 /*
3552  * TCC_SGE (RW)
3553  *
3554  * Task complete interrupt signal enable
3555  * Values:
3556  * 0x1 (INT_SIG_ENABLE): CQIS.TCC interrupt signal generation is active
3557  * 0x0 (INT_SIG_DISABLE): CQIS.TCC interrupt signal generation is disabled
3558  */
3559 #define SDXC_CQISGE_TCC_SGE_MASK (0x2U)
3560 #define SDXC_CQISGE_TCC_SGE_SHIFT (1U)
3561 #define SDXC_CQISGE_TCC_SGE_SET(x) (((uint32_t)(x) << SDXC_CQISGE_TCC_SGE_SHIFT) & SDXC_CQISGE_TCC_SGE_MASK)
3562 #define SDXC_CQISGE_TCC_SGE_GET(x) (((uint32_t)(x) & SDXC_CQISGE_TCC_SGE_MASK) >> SDXC_CQISGE_TCC_SGE_SHIFT)
3563 
3564 /*
3565  * HAC_SGE (RW)
3566  *
3567  * Halt complete interrupt signal enable
3568  * Values:
3569  * 0x1 (INT_SIG_ENABLE): CQIS.HAC interrupt signal generation is active
3570  * 0x0 (INT_SIG_DISABLE): CQIS.HAC interrupt signal generation is disabled
3571  */
3572 #define SDXC_CQISGE_HAC_SGE_MASK (0x1U)
3573 #define SDXC_CQISGE_HAC_SGE_SHIFT (0U)
3574 #define SDXC_CQISGE_HAC_SGE_SET(x) (((uint32_t)(x) << SDXC_CQISGE_HAC_SGE_SHIFT) & SDXC_CQISGE_HAC_SGE_MASK)
3575 #define SDXC_CQISGE_HAC_SGE_GET(x) (((uint32_t)(x) & SDXC_CQISGE_HAC_SGE_MASK) >> SDXC_CQISGE_HAC_SGE_SHIFT)
3576 
3577 /* Bitfield definition for register: CQIC */
3578 /*
3579  * INTC_EN (RW)
3580  *
3581  * Interrupt Coalescing Enable Bit
3582  * Values:
3583  * 0x1 (ENABLE_INT_COALESCING): Interrupt coalescing mechanism is active. Interrupts are counted and timed, and coalesced interrupts are generated
3584  * 0x0 (DISABLE_INT_COALESCING): Interrupt coalescing mechanism is disabled (Default)
3585  */
3586 #define SDXC_CQIC_INTC_EN_MASK (0x80000000UL)
3587 #define SDXC_CQIC_INTC_EN_SHIFT (31U)
3588 #define SDXC_CQIC_INTC_EN_SET(x) (((uint32_t)(x) << SDXC_CQIC_INTC_EN_SHIFT) & SDXC_CQIC_INTC_EN_MASK)
3589 #define SDXC_CQIC_INTC_EN_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_EN_MASK) >> SDXC_CQIC_INTC_EN_SHIFT)
3590 
3591 /*
3592  * INTC_STAT (RO)
3593  *
3594  * Interrupt Coalescing Status Bit
3595  * This bit indicates to the software whether any tasks (with INT=0) have completed and counted towards interrupt
3596  * coalescing (that is, this is set if and only if INTC counter > 0).
3597  * Values:
3598  * 0x1 (INTC_ATLEAST1_COMP): At least one INT0 task completion has been counted (INTC counter > 0)
3599  * 0x0 (INTC_NO_TASK_COMP): INT0 Task completions have not occurred since last counter reset (INTC counter == 0)
3600  */
3601 #define SDXC_CQIC_INTC_STAT_MASK (0x100000UL)
3602 #define SDXC_CQIC_INTC_STAT_SHIFT (20U)
3603 #define SDXC_CQIC_INTC_STAT_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_STAT_MASK) >> SDXC_CQIC_INTC_STAT_SHIFT)
3604 
3605 /*
3606  * INTC_RST (WO)
3607  *
3608  * Counter and Timer Reset
3609  * When host driver writes 1, the interrupt coalescing timer and counter are reset.
3610  * Values:
3611  * 0x1 (ASSERT_INTC_RESET): Interrupt coalescing timer and counter are reset
3612  * 0x0 (NO_EFFECT): No Effect
3613  */
3614 #define SDXC_CQIC_INTC_RST_MASK (0x10000UL)
3615 #define SDXC_CQIC_INTC_RST_SHIFT (16U)
3616 #define SDXC_CQIC_INTC_RST_SET(x) (((uint32_t)(x) << SDXC_CQIC_INTC_RST_SHIFT) & SDXC_CQIC_INTC_RST_MASK)
3617 #define SDXC_CQIC_INTC_RST_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_RST_MASK) >> SDXC_CQIC_INTC_RST_SHIFT)
3618 
3619 /*
3620  * INTC_TH_WEN (WO)
3621  *
3622  * Interrupt Coalescing Counter Threshold Write Enable
3623  * When software writes 1 to this bit, the value INTC_TH is updated with the contents written on the same cycle.
3624  * Values:
3625  * 0x1 (WEN_SET): Sets INTC_TH_WEN
3626  * 0x0 (WEN_CLR): Clears INTC_TH_WEN
3627  */
3628 #define SDXC_CQIC_INTC_TH_WEN_MASK (0x8000U)
3629 #define SDXC_CQIC_INTC_TH_WEN_SHIFT (15U)
3630 #define SDXC_CQIC_INTC_TH_WEN_SET(x) (((uint32_t)(x) << SDXC_CQIC_INTC_TH_WEN_SHIFT) & SDXC_CQIC_INTC_TH_WEN_MASK)
3631 #define SDXC_CQIC_INTC_TH_WEN_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_TH_WEN_MASK) >> SDXC_CQIC_INTC_TH_WEN_SHIFT)
3632 
3633 /*
3634  * INTC_TH (WO)
3635  *
3636  * Interrupt Coalescing Counter Threshold filed
3637  * Software uses this field to configure the number of task completions (only tasks with INT=0 in the Task Descriptor), which are required in order to generate an interrupt.
3638  * Counter Operation: As data transfer tasks with INT=0 complete, they are counted by CQE.
3639  * The counter is reset by software during the interrupt service routine.
3640  * The counter stops counting when it reaches the value configured in INTC_TH, and generates interrupt.
3641  * 0x0: Interrupt coalescing feature disabled
3642  * 0x1: Interrupt coalescing interrupt generated after 1 task when INT=0 completes
3643  * 0x2: Interrupt coalescing interrupt generated after 2 tasks when INT=0 completes
3644  * ........
3645  * 0x1f: Interrupt coalescing interrupt generated after 31 tasks when INT=0 completes
3646  * To write to this field, the INTC_TH_WEN bit must be set during the same write operation.
3647  */
3648 #define SDXC_CQIC_INTC_TH_MASK (0x1F00U)
3649 #define SDXC_CQIC_INTC_TH_SHIFT (8U)
3650 #define SDXC_CQIC_INTC_TH_SET(x) (((uint32_t)(x) << SDXC_CQIC_INTC_TH_SHIFT) & SDXC_CQIC_INTC_TH_MASK)
3651 #define SDXC_CQIC_INTC_TH_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_TH_MASK) >> SDXC_CQIC_INTC_TH_SHIFT)
3652 
3653 /*
3654  * TOUT_VAL_WEN (WO)
3655  *
3656  * When software writes 1 to this bit, the value TOUT_VAL is updated with the contents written on the same cycle.
3657  * Values:
3658  * 0x1 (WEN_SET): Sets TOUT_VAL_WEN
3659  * 0x0 (WEN_CLR): clears TOUT_VAL_WEN
3660  */
3661 #define SDXC_CQIC_TOUT_VAL_WEN_MASK (0x80U)
3662 #define SDXC_CQIC_TOUT_VAL_WEN_SHIFT (7U)
3663 #define SDXC_CQIC_TOUT_VAL_WEN_SET(x) (((uint32_t)(x) << SDXC_CQIC_TOUT_VAL_WEN_SHIFT) & SDXC_CQIC_TOUT_VAL_WEN_MASK)
3664 #define SDXC_CQIC_TOUT_VAL_WEN_GET(x) (((uint32_t)(x) & SDXC_CQIC_TOUT_VAL_WEN_MASK) >> SDXC_CQIC_TOUT_VAL_WEN_SHIFT)
3665 
3666 /*
3667  * TOUT_VAL (RW)
3668  *
3669  * Interrupt Coalescing Timeout Value
3670  * Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt.
3671  * Timer Operation: The timer is reset by software during the interrupt service routine.
3672  * It starts running when the first data transfer task with INT=0 is completed, after the timer was reset.
3673  * When the timer reaches the value configured in ICTOVAL field, it generates an interrupt and stops.
3674  * The timer's unit is equal to 1024 clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register.
3675  * 0x0: Timer is disabled. Timeout-based interrupt is not generated
3676  * 0x1: Timeout on 01x1024 cycles of timer clock frequency
3677  * 0x2: Timeout on 02x1024 cycles of timer clock frequency
3678  * ........
3679  * 0x7f: Timeout on 127x1024 cycles of timer clock frequency
3680  * In order to write to this field, the TOUT_VAL_WEN bit must
3681  * be set at the same write operation.
3682  */
3683 #define SDXC_CQIC_TOUT_VAL_MASK (0x7FU)
3684 #define SDXC_CQIC_TOUT_VAL_SHIFT (0U)
3685 #define SDXC_CQIC_TOUT_VAL_SET(x) (((uint32_t)(x) << SDXC_CQIC_TOUT_VAL_SHIFT) & SDXC_CQIC_TOUT_VAL_MASK)
3686 #define SDXC_CQIC_TOUT_VAL_GET(x) (((uint32_t)(x) & SDXC_CQIC_TOUT_VAL_MASK) >> SDXC_CQIC_TOUT_VAL_SHIFT)
3687 
3688 /* Bitfield definition for register: CQTDLBA */
3689 /*
3690  * TDLBA (RW)
3691  *
3692  * This register stores the LSB bits (31:0) of the byte address of the head of the Task Descriptor List in system memory.
3693  * The size of the task descriptor list is 32 * (Task Descriptor size + Transfer Descriptor size) as configured by the host driver.
3694  * This address is set on 1 KB boundary. The lower 10 bits of this register are set to 0 by the software and are ignored by CQE
3695  */
3696 #define SDXC_CQTDLBA_TDLBA_MASK (0xFFFFFFFFUL)
3697 #define SDXC_CQTDLBA_TDLBA_SHIFT (0U)
3698 #define SDXC_CQTDLBA_TDLBA_SET(x) (((uint32_t)(x) << SDXC_CQTDLBA_TDLBA_SHIFT) & SDXC_CQTDLBA_TDLBA_MASK)
3699 #define SDXC_CQTDLBA_TDLBA_GET(x) (((uint32_t)(x) & SDXC_CQTDLBA_TDLBA_MASK) >> SDXC_CQTDLBA_TDLBA_SHIFT)
3700 
3701 /* Bitfield definition for register: CQTDBR */
3702 /*
3703  * DBR (RW)
3704  *
3705  * The software configures TDLBA and TDLBAU, and enable
3706  * CQE in CQCFG before using this register.
3707  * Writing 1 to bit n of this register triggers CQE to start processing the task encoded in slot n of the TDL.
3708  * Writing 0 by the software does not have any impact on the hardware, and does not change the value of the register bit.
3709  * CQE always processes tasks according to the order submitted to the list by CQTDBR write transactions.
3710  * CQE processes Data Transfer tasks by reading the Task Descriptor and sending QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) commands to
3711  * the device. CQE processes DCMD tasks (in slot #31, when enabled) by reading the Task Descriptor, and generating the command encoded by its index and argument.
3712  * The corresponding bit is cleared to 0 by CQE in one of the following events:
3713  * A task execution is completed (with success or error).
3714  * The task is cleared using CQTCLR register.
3715  * All tasks are cleared using CQCTL register.
3716  * CQE is disabled using CQCFG register.
3717  * Software may initiate multiple tasks at the same time (batch submission) by writing 1 to multiple bits of this register in the same transaction.
3718  * In the case of batch submission, CQE processes the tasks in order of the task index, starting with the lowest index.
3719  * If one or more tasks in the batch are marked with QBR, the ordering of execution is based on said processing order.
3720  */
3721 #define SDXC_CQTDBR_DBR_MASK (0xFFFFFFFFUL)
3722 #define SDXC_CQTDBR_DBR_SHIFT (0U)
3723 #define SDXC_CQTDBR_DBR_SET(x) (((uint32_t)(x) << SDXC_CQTDBR_DBR_SHIFT) & SDXC_CQTDBR_DBR_MASK)
3724 #define SDXC_CQTDBR_DBR_GET(x) (((uint32_t)(x) & SDXC_CQTDBR_DBR_MASK) >> SDXC_CQTDBR_DBR_SHIFT)
3725 
3726 /* Bitfield definition for register: CQTCN */
3727 /*
3728  * TCN (RW)
3729  *
3730  * Task Completion Notification
3731  * Each of the 32 bits are bit mapped to the 32 tasks.
3732  * Bit-N(1): Task-N has completed execution (with success or errors)
3733  * Bit-N(0): Task-N has not completed, could be pending or not submitted.
3734  * On task completion, software may read this register to know tasks that have completed. After reading this register,
3735  * software may clear the relevant bit fields by writing 1 to the corresponding bits.
3736  */
3737 #define SDXC_CQTCN_TCN_MASK (0xFFFFFFFFUL)
3738 #define SDXC_CQTCN_TCN_SHIFT (0U)
3739 #define SDXC_CQTCN_TCN_SET(x) (((uint32_t)(x) << SDXC_CQTCN_TCN_SHIFT) & SDXC_CQTCN_TCN_MASK)
3740 #define SDXC_CQTCN_TCN_GET(x) (((uint32_t)(x) & SDXC_CQTCN_TCN_MASK) >> SDXC_CQTCN_TCN_SHIFT)
3741 
3742 /* Bitfield definition for register: CQDQS */
3743 /*
3744  * DQS (RW)
3745  *
3746  * Device Queue Status
3747  * Each of the 32 bits are bit mapped to the 32 tasks.
3748  * Bit-N(1): Device has marked task N as ready for execution
3749  * Bit-N(0): Task-N is not ready for execution. This task could be pending in device or not submitted.
3750  * Host controller updates this register with response of the Device Queue Status command.
3751  */
3752 #define SDXC_CQDQS_DQS_MASK (0xFFFFFFFFUL)
3753 #define SDXC_CQDQS_DQS_SHIFT (0U)
3754 #define SDXC_CQDQS_DQS_SET(x) (((uint32_t)(x) << SDXC_CQDQS_DQS_SHIFT) & SDXC_CQDQS_DQS_MASK)
3755 #define SDXC_CQDQS_DQS_GET(x) (((uint32_t)(x) & SDXC_CQDQS_DQS_MASK) >> SDXC_CQDQS_DQS_SHIFT)
3756 
3757 /* Bitfield definition for register: CQDPT */
3758 /*
3759  * DPT (RW)
3760  *
3761  * Device-Pending Tasks
3762  * Each of the 32 bits are bit mapped to the 32 tasks.
3763  * Bit-N(1): Task-N has been successfully queued into the device and is awaiting execution
3764  * Bit-N(0): Task-N is not yet queued.
3765  * Bit n of this register is set if and only if QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) were sent for this specific task and if this task has not been executed.
3766  * The controller sets this bit after receiving a successful response for CMD45. CQE clears this bit after the task has completed execution.
3767  * Software reads this register in the task-discard procedure to determine if the task is queued in the device
3768  */
3769 #define SDXC_CQDPT_DPT_MASK (0xFFFFFFFFUL)
3770 #define SDXC_CQDPT_DPT_SHIFT (0U)
3771 #define SDXC_CQDPT_DPT_SET(x) (((uint32_t)(x) << SDXC_CQDPT_DPT_SHIFT) & SDXC_CQDPT_DPT_MASK)
3772 #define SDXC_CQDPT_DPT_GET(x) (((uint32_t)(x) & SDXC_CQDPT_DPT_MASK) >> SDXC_CQDPT_DPT_SHIFT)
3773 
3774 /* Bitfield definition for register: CQTCLR */
3775 /*
3776  * TCLR (RW)
3777  *
3778  * Writing 1 to bit n of this register orders CQE to clear a task that the software has previously issued.
3779  * This bit can only be written when CQE is in Halt state as indicated in CQCFG register Halt bit.
3780  * When software writes 1 to a bit in this register, CQE updates the value to 1, and starts clearing the data structures related to the task.
3781  * CQE clears the bit fields (sets a value of 0) in CQTCLR and in CQTDBR once the clear operation is complete.
3782  * Software must poll on the CQTCLR until it is leared to verify that a clear operation was done.
3783  */
3784 #define SDXC_CQTCLR_TCLR_MASK (0xFFFFFFFFUL)
3785 #define SDXC_CQTCLR_TCLR_SHIFT (0U)
3786 #define SDXC_CQTCLR_TCLR_SET(x) (((uint32_t)(x) << SDXC_CQTCLR_TCLR_SHIFT) & SDXC_CQTCLR_TCLR_MASK)
3787 #define SDXC_CQTCLR_TCLR_GET(x) (((uint32_t)(x) & SDXC_CQTCLR_TCLR_MASK) >> SDXC_CQTCLR_TCLR_SHIFT)
3788 
3789 /* Bitfield definition for register: CQSSC1 */
3790 /*
3791  * SQSCMD_BLK_CNT (RW)
3792  *
3793  * This field indicates when SQS CMD is sent while data transfer is in progress.
3794  * A value of 'n' indicates that CQE sends status command on the CMD line, during the transfer of data block BLOCK_CNTn, on the data lines, where BLOCK_CNT is the number of blocks in the current transaction.
3795  * 0x0: SEND_QUEUE_STATUS (CMD13) command is not sent during the transaction. Instead, it is sent only when the data lines are idle.
3796  * 0x1: SEND_QUEUE_STATUS command is to be sent during the last block of the transaction.
3797  * 0x2: SEND_QUEUE_STATUS command when last 2 blocks are pending.
3798  * 0x3: SEND_QUEUE_STATUS command when last 3 blocks are pending.
3799  * ........
3800  * 0xf: SEND_QUEUE_STATUS command when last 15 blocks are pending.
3801  * Should be programmed only when CQCFG.CQ_EN is 0
3802  */
3803 #define SDXC_CQSSC1_SQSCMD_BLK_CNT_MASK (0xF0000UL)
3804 #define SDXC_CQSSC1_SQSCMD_BLK_CNT_SHIFT (16U)
3805 #define SDXC_CQSSC1_SQSCMD_BLK_CNT_SET(x) (((uint32_t)(x) << SDXC_CQSSC1_SQSCMD_BLK_CNT_SHIFT) & SDXC_CQSSC1_SQSCMD_BLK_CNT_MASK)
3806 #define SDXC_CQSSC1_SQSCMD_BLK_CNT_GET(x) (((uint32_t)(x) & SDXC_CQSSC1_SQSCMD_BLK_CNT_MASK) >> SDXC_CQSSC1_SQSCMD_BLK_CNT_SHIFT)
3807 
3808 /*
3809  * SQSCMD_IDLE_TMR (RW)
3810  *
3811  * This field configures the polling period to be used when using periodic SEND_QUEUE_STATUS (CMD13) polling.
3812  * Periodic polling is used when tasks are pending in the device, but no data transfer is in progress.
3813  * When a SEND_QUEUE_STATUS response indicates that no task is ready for execution, CQE counts the configured time until it issues the next SEND_QUEUE_STATUS.
3814  * Timer units are clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register.
3815  * The minimum value is 0001h (1 clock period) and the maximum value is FFFFh (65535 clock periods).
3816  * For example, a CQCAP field value of 0 indicates a 19.2 MHz clock frequency (period = 52.08 ns).
3817  * If the setting in CQSSC1.CIT is 1000h, the calculated polling period is 4096*52.08 ns= 213.33 us.
3818  * Should be programmed only when CQCFG.CQ_EN is '0'
3819  */
3820 #define SDXC_CQSSC1_SQSCMD_IDLE_TMR_MASK (0xFFFFU)
3821 #define SDXC_CQSSC1_SQSCMD_IDLE_TMR_SHIFT (0U)
3822 #define SDXC_CQSSC1_SQSCMD_IDLE_TMR_SET(x) (((uint32_t)(x) << SDXC_CQSSC1_SQSCMD_IDLE_TMR_SHIFT) & SDXC_CQSSC1_SQSCMD_IDLE_TMR_MASK)
3823 #define SDXC_CQSSC1_SQSCMD_IDLE_TMR_GET(x) (((uint32_t)(x) & SDXC_CQSSC1_SQSCMD_IDLE_TMR_MASK) >> SDXC_CQSSC1_SQSCMD_IDLE_TMR_SHIFT)
3824 
3825 /* Bitfield definition for register: CQSSC2 */
3826 /*
3827  * SQSCMD_RCA (RW)
3828  *
3829  * This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_STATUS (CMD13) command argument.
3830  * CQE copies this field to bits 31:16 of the argument when transmitting SEND_ QUEUE_STATUS (CMD13) command.
3831  */
3832 #define SDXC_CQSSC2_SQSCMD_RCA_MASK (0xFFFFU)
3833 #define SDXC_CQSSC2_SQSCMD_RCA_SHIFT (0U)
3834 #define SDXC_CQSSC2_SQSCMD_RCA_SET(x) (((uint32_t)(x) << SDXC_CQSSC2_SQSCMD_RCA_SHIFT) & SDXC_CQSSC2_SQSCMD_RCA_MASK)
3835 #define SDXC_CQSSC2_SQSCMD_RCA_GET(x) (((uint32_t)(x) & SDXC_CQSSC2_SQSCMD_RCA_MASK) >> SDXC_CQSSC2_SQSCMD_RCA_SHIFT)
3836 
3837 /* Bitfield definition for register: CQCRDCT */
3838 /*
3839  * DCMD_RESP (RO)
3840  *
3841  * This register contains the response of the command generated by the last direct command (DCMD) task that was sent.
3842  * Contents of this register are valid only after bit 31 of CQTDBR register is cleared by the controller.
3843  */
3844 #define SDXC_CQCRDCT_DCMD_RESP_MASK (0xFFFFFFFFUL)
3845 #define SDXC_CQCRDCT_DCMD_RESP_SHIFT (0U)
3846 #define SDXC_CQCRDCT_DCMD_RESP_GET(x) (((uint32_t)(x) & SDXC_CQCRDCT_DCMD_RESP_MASK) >> SDXC_CQCRDCT_DCMD_RESP_SHIFT)
3847 
3848 /* Bitfield definition for register: CQRMEM */
3849 /*
3850  * RESP_ERR_MASK (RW)
3851  *
3852  * The bits of this field are bit mapped to the device response.
3853  * This bit is used as an interrupt mask on the device status filed that is received in R1/R1b responses.
3854  * 1: When a R1/R1b response is received, with a bit i in the device status set, a RED interrupt is generated.
3855  * 0: When a R1/R1b response is received, bit i in the device status is ignored.
3856  * The reset value of this register is set to trigger an interrupt on all "Error" type bits in the device status.
3857  * Note: Responses to CMD13 (SQS) encode the QSR so that they are ignored by this logic.
3858  */
3859 #define SDXC_CQRMEM_RESP_ERR_MASK_MASK (0xFFFFFFFFUL)
3860 #define SDXC_CQRMEM_RESP_ERR_MASK_SHIFT (0U)
3861 #define SDXC_CQRMEM_RESP_ERR_MASK_SET(x) (((uint32_t)(x) << SDXC_CQRMEM_RESP_ERR_MASK_SHIFT) & SDXC_CQRMEM_RESP_ERR_MASK_MASK)
3862 #define SDXC_CQRMEM_RESP_ERR_MASK_GET(x) (((uint32_t)(x) & SDXC_CQRMEM_RESP_ERR_MASK_MASK) >> SDXC_CQRMEM_RESP_ERR_MASK_SHIFT)
3863 
3864 /* Bitfield definition for register: CQTERRI */
3865 /*
3866  * TRANS_ERR_TASKID (RO)
3867  *
3868  * This field captures the ID of the task that was executed and whose data transfer has errors.
3869  */
3870 #define SDXC_CQTERRI_TRANS_ERR_TASKID_MASK (0x1F000000UL)
3871 #define SDXC_CQTERRI_TRANS_ERR_TASKID_SHIFT (24U)
3872 #define SDXC_CQTERRI_TRANS_ERR_TASKID_GET(x) (((uint32_t)(x) & SDXC_CQTERRI_TRANS_ERR_TASKID_MASK) >> SDXC_CQTERRI_TRANS_ERR_TASKID_SHIFT)
3873 
3874 /*
3875  * TRANS_ERR_CMD_INDX (RO)
3876  *
3877  * This field captures the index of the command that was executed and whose data transfer has errors.
3878  */
3879 #define SDXC_CQTERRI_TRANS_ERR_CMD_INDX_MASK (0x3F0000UL)
3880 #define SDXC_CQTERRI_TRANS_ERR_CMD_INDX_SHIFT (16U)
3881 #define SDXC_CQTERRI_TRANS_ERR_CMD_INDX_GET(x) (((uint32_t)(x) & SDXC_CQTERRI_TRANS_ERR_CMD_INDX_MASK) >> SDXC_CQTERRI_TRANS_ERR_CMD_INDX_SHIFT)
3882 
3883 /*
3884  * RESP_ERR_FIELDS_VALID (RO)
3885  *
3886  * This bit is updated when an error is detected while a command transaction was in progress.
3887  * Values:
3888  * 0x1 (SET): Response-related error is detected. Check contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX fields
3889  * 0x0 (NOT_SET): Ignore contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX
3890  */
3891 #define SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_MASK (0x8000U)
3892 #define SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_SHIFT (15U)
3893 #define SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_GET(x) (((uint32_t)(x) & SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_MASK) >> SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_SHIFT)
3894 
3895 /*
3896  * RESP_ERR_TASKID (RO)
3897  *
3898  * This field captures the ID of the task which was executed on the command line when the error occurred.
3899  */
3900 #define SDXC_CQTERRI_RESP_ERR_TASKID_MASK (0x1F00U)
3901 #define SDXC_CQTERRI_RESP_ERR_TASKID_SHIFT (8U)
3902 #define SDXC_CQTERRI_RESP_ERR_TASKID_GET(x) (((uint32_t)(x) & SDXC_CQTERRI_RESP_ERR_TASKID_MASK) >> SDXC_CQTERRI_RESP_ERR_TASKID_SHIFT)
3903 
3904 /*
3905  * RESP_ERR_CMD_INDX (RO)
3906  *
3907  * This field captures the index of the command that was executed on the command line when the error occurred
3908  */
3909 #define SDXC_CQTERRI_RESP_ERR_CMD_INDX_MASK (0x3FU)
3910 #define SDXC_CQTERRI_RESP_ERR_CMD_INDX_SHIFT (0U)
3911 #define SDXC_CQTERRI_RESP_ERR_CMD_INDX_GET(x) (((uint32_t)(x) & SDXC_CQTERRI_RESP_ERR_CMD_INDX_MASK) >> SDXC_CQTERRI_RESP_ERR_CMD_INDX_SHIFT)
3912 
3913 /* Bitfield definition for register: CQCRI */
3914 /*
3915  * CMD_RESP_INDX (RO)
3916  *
3917  * Last Command Response index
3918  * This field stores the index of the last received command response. Controller updates the value every time a command response is received
3919  */
3920 #define SDXC_CQCRI_CMD_RESP_INDX_MASK (0x3FU)
3921 #define SDXC_CQCRI_CMD_RESP_INDX_SHIFT (0U)
3922 #define SDXC_CQCRI_CMD_RESP_INDX_GET(x) (((uint32_t)(x) & SDXC_CQCRI_CMD_RESP_INDX_MASK) >> SDXC_CQCRI_CMD_RESP_INDX_SHIFT)
3923 
3924 /* Bitfield definition for register: CQCRA */
3925 /*
3926  * CMD_RESP_ARG (RO)
3927  *
3928  * Last Command Response argument
3929  * This field stores the argument of the last received command response. Controller updates the value every time a command response is received.
3930  */
3931 #define SDXC_CQCRA_CMD_RESP_ARG_MASK (0xFFFFFFFFUL)
3932 #define SDXC_CQCRA_CMD_RESP_ARG_SHIFT (0U)
3933 #define SDXC_CQCRA_CMD_RESP_ARG_GET(x) (((uint32_t)(x) & SDXC_CQCRA_CMD_RESP_ARG_MASK) >> SDXC_CQCRA_CMD_RESP_ARG_SHIFT)
3934 
3935 /* Bitfield definition for register: MSHC_VER_ID */
3936 /*
3937  * VER_ID (RO)
3938  *
3939  */
3940 #define SDXC_MSHC_VER_ID_VER_ID_MASK (0xFFFFFFFFUL)
3941 #define SDXC_MSHC_VER_ID_VER_ID_SHIFT (0U)
3942 #define SDXC_MSHC_VER_ID_VER_ID_GET(x) (((uint32_t)(x) & SDXC_MSHC_VER_ID_VER_ID_MASK) >> SDXC_MSHC_VER_ID_VER_ID_SHIFT)
3943 
3944 /* Bitfield definition for register: MSHC_VER_TYPE */
3945 /*
3946  * VER_TYPE (RO)
3947  *
3948  */
3949 #define SDXC_MSHC_VER_TYPE_VER_TYPE_MASK (0xFFFFFFFFUL)
3950 #define SDXC_MSHC_VER_TYPE_VER_TYPE_SHIFT (0U)
3951 #define SDXC_MSHC_VER_TYPE_VER_TYPE_GET(x) (((uint32_t)(x) & SDXC_MSHC_VER_TYPE_VER_TYPE_MASK) >> SDXC_MSHC_VER_TYPE_VER_TYPE_SHIFT)
3952 
3953 /* Bitfield definition for register: EMMC_BOOT_CTRL */
3954 /*
3955  * BOOT_TOUT_CNT (RW)
3956  *
3957  * Boot Ack Timeout Counter Value.
3958  * This value determines the interval by which boot ack timeout (50 ms) is detected when boot ack is expected during boot operation.
3959  * 0xF : Reserved
3960  * 0xE : TMCLK x 2^27
3961  * ............
3962  * 0x1 : TMCLK x 2^14
3963  * 0x0 : TMCLK x 2^13
3964  */
3965 #define SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_MASK (0xF0000000UL)
3966 #define SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_SHIFT (28U)
3967 #define SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_SHIFT) & SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_MASK)
3968 #define SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_MASK) >> SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_SHIFT)
3969 
3970 /*
3971  * BOOT_ACK_ENABLE (RW)
3972  *
3973  * Boot Acknowledge Enable
3974  * When this bit set, SDXC checks for boot acknowledge start pattern of 0-1-0 during boot operation. This bit is applicable for both mandatory and alternate boot mode.
3975  * Values:
3976  * 0x1 (TRUE): Boot Ack enable
3977  * 0x0 (FALSE): Boot Ack disable
3978  */
3979 #define SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_MASK (0x1000000UL)
3980 #define SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_SHIFT (24U)
3981 #define SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_SHIFT) & SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_MASK)
3982 #define SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_MASK) >> SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_SHIFT)
3983 
3984 /*
3985  * VALIDATE_BOOT (WO)
3986  *
3987  * Validate Mandatory Boot Enable bit
3988  * This bit is used to validate the MAN_BOOT_EN bit.
3989  * Values:
3990  * 0x1 (TRUE): Validate Mandatory boot enable bit
3991  * 0x0 (FALSE): Ignore Mandatory boot Enable bit
3992  */
3993 #define SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_MASK (0x800000UL)
3994 #define SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_SHIFT (23U)
3995 #define SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_SHIFT) & SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_MASK)
3996 #define SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_MASK) >> SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_SHIFT)
3997 
3998 /*
3999  * MAN_BOOT_EN (RW)
4000  *
4001  * Mandatory Boot Enable
4002  * This bit is used to initiate the mandatory boot operation. The application sets this bit along with VALIDATE_BOOT bit.
4003  * Writing 0 is ignored. The SDXC clears this bit after the boot transfer is completed or terminated.
4004  * Values:
4005  * 0x1 (MAN_BOOT_EN): Mandatory boot enable
4006  * 0x0 (MAN_BOOT_DIS): Mandatory boot disable
4007  */
4008 #define SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_MASK (0x10000UL)
4009 #define SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_SHIFT (16U)
4010 #define SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_SHIFT) & SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_MASK)
4011 #define SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_MASK) >> SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_SHIFT)
4012 
4013 /*
4014  * CQE_PREFETCH_DISABLE (RW)
4015  *
4016  * Enable or Disable CQE's PREFETCH feature
4017  * This field allows Software to disable CQE's data prefetch feature when set to 1.
4018  * Values:
4019  * 0x0 (PREFETCH_ENABLE): CQE can Prefetch data for sucessive WRITE transfers and pipeline sucessive READ transfers
4020  * 0x1 (PREFETCH_DISABLE): Prefetch for WRITE and Pipeline for READ are disabled
4021  */
4022 #define SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_MASK (0x400U)
4023 #define SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_SHIFT (10U)
4024 #define SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_SHIFT) & SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_MASK)
4025 #define SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_MASK) >> SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_SHIFT)
4026 
4027 /*
4028  * CQE_ALGO_SEL (RW)
4029  *
4030  * Scheduler algorithm selected for execution
4031  * This bit selects the Algorithm used for selecting one of the many ready tasks for execution.
4032  * Values:
4033  * 0x0 (PRI_REORDER_PLUS_FCFS): Priority based reordering with FCFS to resolve equal priority tasks
4034  * 0x1 (FCFS_ONLY): First come First serve, in the order of DBR rings
4035  */
4036 #define SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_MASK (0x200U)
4037 #define SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_SHIFT (9U)
4038 #define SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_SHIFT) & SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_MASK)
4039 #define SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_MASK) >> SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_SHIFT)
4040 
4041 /*
4042  * ENH_STROBE_ENABLE (RW)
4043  *
4044  * Enhanced Strobe Enable
4045  * This bit instructs SDXC to sample the CMD line using data strobe for HS400 mode.
4046  * Values:
4047  * 0x1 (ENH_STB_FOR_CMD): CMD line is sampled using data strobe for HS400 mode
4048  * 0x0 (NO_STB_FOR_CMD): CMD line is sampled using cclk_rx for HS400 mode
4049  */
4050 #define SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_MASK (0x100U)
4051 #define SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_SHIFT (8U)
4052 #define SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_SHIFT) & SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_MASK)
4053 #define SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_MASK) >> SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_SHIFT)
4054 
4055 /*
4056  * EMMC_RST_N_OE (RW)
4057  *
4058  * Output Enable control for EMMC Device Reset signal PAD
4059  * control.
4060  * This field drived sd_rst_n_oe output of SDXC
4061  * Values:
4062  * 0x1 (ENABLE): sd_rst_n_oe is 1
4063  * 0x0 (DISABLE): sd_rst_n_oe is 0
4064  */
4065 #define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_MASK (0x8U)
4066 #define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_SHIFT (3U)
4067 #define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_SHIFT) & SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_MASK)
4068 #define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_MASK) >> SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_SHIFT)
4069 
4070 /*
4071  * EMMC_RST_N (RW)
4072  *
4073  * EMMC Device Reset signal control.
4074  * This register field controls the sd_rst_n output of SDXC
4075  * Values:
4076  * 0x1 (RST_DEASSERT): Reset to eMMC device is deasserted
4077  * 0x0 (RST_ASSERT): Reset to eMMC device asserted (active low)
4078  */
4079 #define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_MASK (0x4U)
4080 #define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_SHIFT (2U)
4081 #define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_SHIFT) & SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_MASK)
4082 #define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_MASK) >> SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_SHIFT)
4083 
4084 /*
4085  * DISABLE_DATA_CRC_CHK (RW)
4086  *
4087  * Disable Data CRC Check
4088  * This bit controls masking of CRC16 error for Card Write in eMMC mode.
4089  * This is useful in bus testing (CMD19) for an eMMC device. In bus testing, an eMMC card does not send CRC status for a block,
4090  * which may generate CRC error. This CRC error can be masked using this bit during bus testing.
4091  * Values:
4092  * 0x1 (DISABLE): DATA CRC check is disabled
4093  * 0x0 (ENABLE): DATA CRC check is enabled
4094  */
4095 #define SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_MASK (0x2U)
4096 #define SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_SHIFT (1U)
4097 #define SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_SHIFT) & SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_MASK)
4098 #define SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_MASK) >> SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_SHIFT)
4099 
4100 /*
4101  * CARD_IS_EMMC (RW)
4102  *
4103  * eMMC Card present
4104  * This bit indicates the type of card connected. An application program this bit based on the card connected to SDXC.
4105  * Values:
4106  * 0x1 (EMMC_CARD): Card connected to SDXC is an eMMC card
4107  * 0x0 (NON_EMMC_CARD): Card connected to SDXCis a non-eMMC card
4108  */
4109 #define SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_MASK (0x1U)
4110 #define SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_SHIFT (0U)
4111 #define SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_SHIFT) & SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_MASK)
4112 #define SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_MASK) >> SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_SHIFT)
4113 
4114 /* Bitfield definition for register: AUTO_TUNING_CTRL */
4115 /*
4116  * SWIN_TH_VAL (RW)
4117  *
4118  * Sampling window threshold value setting
4119  * The maximum value that can be set here depends on the length of delayline used for tuning. A delayLine with 32 taps
4120  * can use values from 0x0 to 0x1F.
4121  * This field is valid only when SWIN_TH_EN is '1'. Should be programmed only when SAMPLE_CLK_SEL is '0'
4122  * 0x0 : Threshold values is 0x1, windows of length 1 tap and above can be selected as sampling window.
4123  * 0x1 : Threshold values is 0x2, windows of length 2 taps and above can be selected as sampling window.
4124  * 0x2 : Threshold values is 0x1, windows of length 3 taps and above can be selected as sampling window.
4125  * ........
4126  * 0x1F : Threshold values is 0x1, windows of length 32 taps and above can be selected as sampling window.
4127  */
4128 #define SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_MASK (0x7F000000UL)
4129 #define SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_SHIFT (24U)
4130 #define SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_SHIFT) & SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_MASK)
4131 #define SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_MASK) >> SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_SHIFT)
4132 
4133 /*
4134  * POST_CHANGE_DLY (RW)
4135  *
4136  * Time taken for phase switching and stable clock output.
4137  * Specifies the maximum time (in terms of cclk cycles) that the delay line can take to switch its output phase after a change in tuning_cclk_sel or autotuning_cclk_sel.
4138  * Values:
4139  * 0x0 (LATENCY_LT_1): Less than 1-cycle latency
4140  * 0x1 (LATENCY_LT_2): Less than 2-cycle latency
4141  * 0x2 (LATENCY_LT_3): Less than 3-cycle latency
4142  * 0x3 (LATENCY_LT_4): Less than 4-cycle latency
4143  */
4144 #define SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_MASK (0x180000UL)
4145 #define SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_SHIFT (19U)
4146 #define SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_SHIFT) & SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_MASK)
4147 #define SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_MASK) >> SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_SHIFT)
4148 
4149 /*
4150  * PRE_CHANGE_DLY (RW)
4151  *
4152  * Maximum Latency specification between cclk_tx and cclk_rx.
4153  * Values:
4154  * 0x0 (LATENCY_LT_1): Less than 1-cycle latency
4155  * 0x1 (LATENCY_LT_2): Less than 2-cycle latency
4156  * 0x2 (LATENCY_LT_3): Less than 3-cycle latency
4157  * 0x3 (LATENCY_LT_4): Less than 4-cycle latency
4158  */
4159 #define SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_MASK (0x60000UL)
4160 #define SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_SHIFT (17U)
4161 #define SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_SHIFT) & SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_MASK)
4162 #define SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_MASK) >> SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_SHIFT)
4163 
4164 /*
4165  * TUNE_CLK_STOP_EN (RW)
4166  *
4167  * Clock stopping control for Tuning and auto-tuning circuit.
4168  * When enabled, clock gate control output of SDXC (clk2card_on) is pulled low before changing phase select codes on tuning_cclk_sel and autotuning_cclk_sel.
4169  * This effectively stops the Device/Card clock, cclk_rx and also drift_cclk_rx. Changing phase code when clocks are stopped ensures glitch free phase switching.
4170  * Set this bit to 0 if the PHY or delayline can guarantee glitch free switching.
4171  * Values:
4172  * 0x1 (ENABLE_CLK_STOPPING): Clocks stopped during phase code change
4173  * 0x0 (DISABLE_CLK_STOPPING): Clocks not stopped. PHY ensures glitch free phase switching
4174  */
4175 #define SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_MASK (0x10000UL)
4176 #define SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_SHIFT (16U)
4177 #define SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_SHIFT) & SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_MASK)
4178 #define SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_MASK) >> SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_SHIFT)
4179 
4180 /*
4181  * WIN_EDGE_SEL (RW)
4182  *
4183  * This field sets the phase for Left and Right edges for drift monitoring. [Left edge offset + Right edge offset] must not be less than total taps of delayLine.
4184  * 0x0: User selection disabled. Tuning calculated edges are used.
4185  * 0x1: Right edge Phase is center + 2 stages, Left edge Phase is center - 2 stages.
4186  * 0x2: Right edge Phase is center + 3 stages, Left edge Phase is center - 3 stagess
4187  * ...
4188  * 0xF: Right edge Phase is center + 16 stages, Left edge Phase is center - 16 stages.
4189  */
4190 #define SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_MASK (0xF00U)
4191 #define SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_SHIFT (8U)
4192 #define SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_SHIFT) & SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_MASK)
4193 #define SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_MASK) >> SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_SHIFT)
4194 
4195 /*
4196  * SW_TUNE_EN (RW)
4197  *
4198  * This fields enables software-managed tuning flow.
4199  * Values:
4200  * 0x1 (SW_TUNING_ENABLE): Software-managed tuning enabled. AUTO_TUNING_STAT.CENTER_PH_CODE Field is now writable.
4201  * 0x0 (SW_TUNING_DISABLE): Software-managed tuning disabled
4202  */
4203 #define SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_MASK (0x10U)
4204 #define SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_SHIFT (4U)
4205 #define SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_SHIFT) & SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_MASK)
4206 #define SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_MASK) >> SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_SHIFT)
4207 
4208 /*
4209  * RPT_TUNE_ERR (RW)
4210  *
4211  * Framing errors are not generated when executing tuning.
4212  * This debug bit allows users to report these errors.
4213  * Values:
4214  * 0x1 (DEBUG_ERRORS): Debug mode for reporting framing errors
4215  * 0x0 (ERRORS_DISABLED): Default mode where as per SDXC no errors are reported.
4216  */
4217 #define SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_MASK (0x8U)
4218 #define SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_SHIFT (3U)
4219 #define SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_SHIFT) & SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_MASK)
4220 #define SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_MASK) >> SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_SHIFT)
4221 
4222 /*
4223  * SWIN_TH_EN (RW)
4224  *
4225  * Sampling window Threshold enable
4226  * Selects the tuning mode
4227  * Field should be programmed only when SAMPLE_CLK_SEL is '0'
4228  * Values:
4229  * 0x1 (THRESHOLD_MODE): Tuning engine selects the first complete sampling window that meets the threshold
4230  * set by SWIN_TH_VAL field
4231  * 0x0 (LARGEST_WIN_MODE): Tuning engine sweeps all taps and settles at the largest window
4232  */
4233 #define SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_MASK (0x4U)
4234 #define SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_SHIFT (2U)
4235 #define SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_SHIFT) & SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_MASK)
4236 #define SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_MASK) >> SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_SHIFT)
4237 
4238 /*
4239  * CI_SEL (RW)
4240  *
4241  * Selects the interval when the corrected center phase select code can be driven on tuning_cclk_sel output.
4242  * Values:
4243  * 0x0 (WHEN_IN_BLK_GAP): Driven in block gap interval
4244  * 0x1 (WHEN_IN_IDLE): Driven at the end of the transfer
4245  */
4246 #define SDXC_AUTO_TUNING_CTRL_CI_SEL_MASK (0x2U)
4247 #define SDXC_AUTO_TUNING_CTRL_CI_SEL_SHIFT (1U)
4248 #define SDXC_AUTO_TUNING_CTRL_CI_SEL_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_CI_SEL_SHIFT) & SDXC_AUTO_TUNING_CTRL_CI_SEL_MASK)
4249 #define SDXC_AUTO_TUNING_CTRL_CI_SEL_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_CI_SEL_MASK) >> SDXC_AUTO_TUNING_CTRL_CI_SEL_SHIFT)
4250 
4251 /*
4252  * AT_EN (RW)
4253  *
4254  * Setting this bit enables Auto tuning engine. This bit is enabled by default when core is configured with mode3 retuning support.
4255  * Clear this bit to 0 when core is configured to have Mode3 re-tuning but SW wishes to disable mode3 retuning.
4256  * This field should be programmed only when SYS_CTRL.SD_CLK_EN is 0.
4257  * Values:
4258  * 0x1 (AT_ENABLE): AutoTuning is enabled
4259  * 0x0 (AT_DISABLE): AutoTuning is disabled
4260  */
4261 #define SDXC_AUTO_TUNING_CTRL_AT_EN_MASK (0x1U)
4262 #define SDXC_AUTO_TUNING_CTRL_AT_EN_SHIFT (0U)
4263 #define SDXC_AUTO_TUNING_CTRL_AT_EN_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_AT_EN_SHIFT) & SDXC_AUTO_TUNING_CTRL_AT_EN_MASK)
4264 #define SDXC_AUTO_TUNING_CTRL_AT_EN_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_AT_EN_MASK) >> SDXC_AUTO_TUNING_CTRL_AT_EN_SHIFT)
4265 
4266 /* Bitfield definition for register: AUTO_TUNING_STAT */
4267 /*
4268  * L_EDGE_PH_CODE (RO)
4269  *
4270  * Left Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Left edge of sampling window.
4271  */
4272 #define SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_MASK (0xFF0000UL)
4273 #define SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_SHIFT (16U)
4274 #define SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_MASK) >> SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_SHIFT)
4275 
4276 /*
4277  * R_EDGE_PH_CODE (RO)
4278  *
4279  * Right Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Right edge of sampling window.
4280  */
4281 #define SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_MASK (0xFF00U)
4282 #define SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_SHIFT (8U)
4283 #define SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_MASK) >> SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_SHIFT)
4284 
4285 /*
4286  * CENTER_PH_CODE (RW)
4287  *
4288  * Centered Phase code. Reading this field returns the current value on tuning_cclk_sel output. Setting AUTO_TUNING_CTRL.SW_TUNE_EN enables software to write to this field and its contents are reflected on tuning_cclk_sel
4289  */
4290 #define SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_MASK (0xFFU)
4291 #define SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_SHIFT (0U)
4292 #define SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_SHIFT) & SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_MASK)
4293 #define SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_MASK) >> SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_SHIFT)
4294 
4295 
4296 
4297 /* RESP register group index macro definition */
4298 #define SDXC_RESP_RESP01 (0UL)
4299 #define SDXC_RESP_RESP23 (1UL)
4300 #define SDXC_RESP_RESP45 (2UL)
4301 #define SDXC_RESP_RESP67 (3UL)
4302 
4303 /* PRESET register group index macro definition */
4304 #define SDXC_PRESET_INIT (0UL)
4305 #define SDXC_PRESET_DS (1UL)
4306 #define SDXC_PRESET_HS (2UL)
4307 #define SDXC_PRESET_SDR12 (3UL)
4308 #define SDXC_PRESET_SDR25 (4UL)
4309 #define SDXC_PRESET_SDR50 (5UL)
4310 #define SDXC_PRESET_SDR104 (6UL)
4311 #define SDXC_PRESET_DDR50 (7UL)
4312 #define SDXC_PRESET_UHS2 (10UL)
4313 
4314 
4315 #endif /* HPM_SDXC_H */
SDXC_Type
Definition: hpm_sdxc_regs.h:12