HPM SDK
HPMicro Software Development Kit
hpm_sysctl_regs.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_SYSCTL_H
10 #define HPM_SYSCTL_H
11 
12 typedef struct {
13  __RW uint32_t RESOURCE[350]; /* 0x0 - 0x574: Resource control register for cpu0 */
14  __R uint8_t RESERVED0[648]; /* 0x578 - 0x7FF: Reserved */
15  struct {
16  __RW uint32_t VALUE; /* 0x800: Goup setting */
17  __RW uint32_t SET; /* 0x804: Goup setting */
18  __RW uint32_t CLEAR; /* 0x808: Goup setting */
19  __RW uint32_t TOGGLE; /* 0x80C: Goup setting */
20  } GROUP0[3];
21  __R uint8_t RESERVED1[16]; /* 0x830 - 0x83F: Reserved */
22  struct {
23  __RW uint32_t VALUE; /* 0x840: Goup setting */
24  __RW uint32_t SET; /* 0x844: Goup setting */
25  __RW uint32_t CLEAR; /* 0x848: Goup setting */
26  __RW uint32_t TOGGLE; /* 0x84C: Goup setting */
27  } GROUP1[3];
28  __R uint8_t RESERVED2[144]; /* 0x870 - 0x8FF: Reserved */
29  struct {
30  __RW uint32_t VALUE; /* 0x900: Affiliate of Group */
31  __RW uint32_t SET; /* 0x904: Affiliate of Group */
32  __RW uint32_t CLEAR; /* 0x908: Affiliate of Group */
33  __RW uint32_t TOGGLE; /* 0x90C: Affiliate of Group */
34  } AFFILIATE[2];
35  struct {
36  __RW uint32_t VALUE; /* 0x920: Retention Control */
37  __RW uint32_t SET; /* 0x924: Retention Control */
38  __RW uint32_t CLEAR; /* 0x928: Retention Control */
39  __RW uint32_t TOGGLE; /* 0x92C: Retention Control */
40  } RETENTION[2];
41  __R uint8_t RESERVED3[1728]; /* 0x940 - 0xFFF: Reserved */
42  struct {
43  __RW uint32_t STATUS; /* 0x1000: Power Setting */
44  __RW uint32_t LF_WAIT; /* 0x1004: Power Setting */
45  __R uint8_t RESERVED0[4]; /* 0x1008 - 0x100B: Reserved */
46  __RW uint32_t OFF_WAIT; /* 0x100C: Power Setting */
47  } POWER[4];
48  __R uint8_t RESERVED4[960]; /* 0x1040 - 0x13FF: Reserved */
49  struct {
50  __RW uint32_t CONTROL; /* 0x1400: Reset Setting */
51  __RW uint32_t CONFIG; /* 0x1404: Reset Setting */
52  __R uint8_t RESERVED0[4]; /* 0x1408 - 0x140B: Reserved */
53  __RW uint32_t COUNTER; /* 0x140C: Reset Setting */
54  } RESET[5];
55  __R uint8_t RESERVED5[944]; /* 0x1450 - 0x17FF: Reserved */
56  __RW uint32_t CLOCK[67]; /* 0x1800 - 0x1908: Clock setting */
57  __R uint8_t RESERVED6[756]; /* 0x190C - 0x1BFF: Reserved */
58  __RW uint32_t ADCCLK[4]; /* 0x1C00 - 0x1C0C: Clock setting */
59  __RW uint32_t I2SCLK[4]; /* 0x1C10 - 0x1C1C: Clock setting */
60  __R uint8_t RESERVED7[992]; /* 0x1C20 - 0x1FFF: Reserved */
61  __RW uint32_t GLOBAL00; /* 0x2000: Clock senario */
62  __R uint8_t RESERVED8[1020]; /* 0x2004 - 0x23FF: Reserved */
63  struct {
64  __RW uint32_t CONTROL; /* 0x2400: Clock measure and monitor control */
65  __R uint32_t CURRENT; /* 0x2404: Clock measure result */
66  __RW uint32_t LOW_LIMIT; /* 0x2408: Clock lower limit */
67  __RW uint32_t HIGH_LIMIT; /* 0x240C: Clock upper limit */
68  __R uint8_t RESERVED0[16]; /* 0x2410 - 0x241F: Reserved */
69  } MONITOR[4];
70  __R uint8_t RESERVED9[896]; /* 0x2480 - 0x27FF: Reserved */
71  struct {
72  __RW uint32_t LP; /* 0x2800: */
73  __RW uint32_t LOCK; /* 0x2804: */
74  __RW uint32_t GPR[14]; /* 0x2808 - 0x283C: */
75  __R uint32_t WAKEUP_STATUS[8]; /* 0x2840 - 0x285C: */
76  __R uint8_t RESERVED0[32]; /* 0x2860 - 0x287F: Reserved */
77  __RW uint32_t WAKEUP_ENABLE[8]; /* 0x2880 - 0x289C: */
78  __R uint8_t RESERVED1[864]; /* 0x28A0 - 0x2BFF: Reserved */
79  } CPU[2];
80 } SYSCTL_Type;
81 
82 
83 /* Bitfield definition for register array: RESOURCE */
84 /*
85  * GLB_BUSY (RO)
86  *
87  * global busy
88  * 0: no changes pending to any nodes
89  * 1: any of nodes is changing status
90  */
91 #define SYSCTL_RESOURCE_GLB_BUSY_MASK (0x80000000UL)
92 #define SYSCTL_RESOURCE_GLB_BUSY_SHIFT (31U)
93 #define SYSCTL_RESOURCE_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_GLB_BUSY_MASK) >> SYSCTL_RESOURCE_GLB_BUSY_SHIFT)
94 
95 /*
96  * LOC_BUSY (RO)
97  *
98  * local busy
99  * 0: no change is pending for current node
100  * 1: current node is changing status
101  */
102 #define SYSCTL_RESOURCE_LOC_BUSY_MASK (0x40000000UL)
103 #define SYSCTL_RESOURCE_LOC_BUSY_SHIFT (30U)
104 #define SYSCTL_RESOURCE_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_LOC_BUSY_MASK) >> SYSCTL_RESOURCE_LOC_BUSY_SHIFT)
105 
106 /*
107  * MODE (RW)
108  *
109  * resource work mode
110  * 0:auto turn on and off as system required(recommended)
111  * 1:always on
112  * 2:always off
113  * 3:reserved
114  */
115 #define SYSCTL_RESOURCE_MODE_MASK (0x3U)
116 #define SYSCTL_RESOURCE_MODE_SHIFT (0U)
117 #define SYSCTL_RESOURCE_MODE_SET(x) (((uint32_t)(x) << SYSCTL_RESOURCE_MODE_SHIFT) & SYSCTL_RESOURCE_MODE_MASK)
118 #define SYSCTL_RESOURCE_MODE_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_MODE_MASK) >> SYSCTL_RESOURCE_MODE_SHIFT)
119 
120 /* Bitfield definition for register of struct array GROUP0: VALUE */
121 /*
122  * LINK (RW)
123  *
124  * denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral
125  * 0: peripheral is not needed
126  * 1: periphera is needed
127  */
128 #define SYSCTL_GROUP0_VALUE_LINK_MASK (0xFFFFFFFFUL)
129 #define SYSCTL_GROUP0_VALUE_LINK_SHIFT (0U)
130 #define SYSCTL_GROUP0_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_VALUE_LINK_SHIFT) & SYSCTL_GROUP0_VALUE_LINK_MASK)
131 #define SYSCTL_GROUP0_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_VALUE_LINK_MASK) >> SYSCTL_GROUP0_VALUE_LINK_SHIFT)
132 
133 /* Bitfield definition for register of struct array GROUP0: SET */
134 /*
135  * LINK (RW)
136  *
137  * denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral
138  * 0: peripheral is not needed
139  * 1: periphera is needed
140  */
141 #define SYSCTL_GROUP0_SET_LINK_MASK (0xFFFFFFFFUL)
142 #define SYSCTL_GROUP0_SET_LINK_SHIFT (0U)
143 #define SYSCTL_GROUP0_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_SET_LINK_SHIFT) & SYSCTL_GROUP0_SET_LINK_MASK)
144 #define SYSCTL_GROUP0_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_SET_LINK_MASK) >> SYSCTL_GROUP0_SET_LINK_SHIFT)
145 
146 /* Bitfield definition for register of struct array GROUP0: CLEAR */
147 /*
148  * LINK (RW)
149  *
150  * denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral
151  * 0: peripheral is not needed
152  * 1: periphera is needed
153  */
154 #define SYSCTL_GROUP0_CLEAR_LINK_MASK (0xFFFFFFFFUL)
155 #define SYSCTL_GROUP0_CLEAR_LINK_SHIFT (0U)
156 #define SYSCTL_GROUP0_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_CLEAR_LINK_SHIFT) & SYSCTL_GROUP0_CLEAR_LINK_MASK)
157 #define SYSCTL_GROUP0_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_CLEAR_LINK_MASK) >> SYSCTL_GROUP0_CLEAR_LINK_SHIFT)
158 
159 /* Bitfield definition for register of struct array GROUP0: TOGGLE */
160 /*
161  * LINK (RW)
162  *
163  * denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral
164  * 0: peripheral is not needed
165  * 1: periphera is needed
166  */
167 #define SYSCTL_GROUP0_TOGGLE_LINK_MASK (0xFFFFFFFFUL)
168 #define SYSCTL_GROUP0_TOGGLE_LINK_SHIFT (0U)
169 #define SYSCTL_GROUP0_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_TOGGLE_LINK_SHIFT) & SYSCTL_GROUP0_TOGGLE_LINK_MASK)
170 #define SYSCTL_GROUP0_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_TOGGLE_LINK_MASK) >> SYSCTL_GROUP0_TOGGLE_LINK_SHIFT)
171 
172 /* Bitfield definition for register of struct array GROUP1: VALUE */
173 /*
174  * LINK (RW)
175  *
176  * denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral
177  * 0: peripheral is not needed
178  * 1: periphera is needed
179  */
180 #define SYSCTL_GROUP1_VALUE_LINK_MASK (0xFFFFFFFFUL)
181 #define SYSCTL_GROUP1_VALUE_LINK_SHIFT (0U)
182 #define SYSCTL_GROUP1_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_VALUE_LINK_SHIFT) & SYSCTL_GROUP1_VALUE_LINK_MASK)
183 #define SYSCTL_GROUP1_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_VALUE_LINK_MASK) >> SYSCTL_GROUP1_VALUE_LINK_SHIFT)
184 
185 /* Bitfield definition for register of struct array GROUP1: SET */
186 /*
187  * LINK (RW)
188  *
189  * denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral
190  * 0: peripheral is not needed
191  * 1: periphera is needed
192  */
193 #define SYSCTL_GROUP1_SET_LINK_MASK (0xFFFFFFFFUL)
194 #define SYSCTL_GROUP1_SET_LINK_SHIFT (0U)
195 #define SYSCTL_GROUP1_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_SET_LINK_SHIFT) & SYSCTL_GROUP1_SET_LINK_MASK)
196 #define SYSCTL_GROUP1_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_SET_LINK_MASK) >> SYSCTL_GROUP1_SET_LINK_SHIFT)
197 
198 /* Bitfield definition for register of struct array GROUP1: CLEAR */
199 /*
200  * LINK (RW)
201  *
202  * denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral
203  * 0: peripheral is not needed
204  * 1: periphera is needed
205  */
206 #define SYSCTL_GROUP1_CLEAR_LINK_MASK (0xFFFFFFFFUL)
207 #define SYSCTL_GROUP1_CLEAR_LINK_SHIFT (0U)
208 #define SYSCTL_GROUP1_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_CLEAR_LINK_SHIFT) & SYSCTL_GROUP1_CLEAR_LINK_MASK)
209 #define SYSCTL_GROUP1_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_CLEAR_LINK_MASK) >> SYSCTL_GROUP1_CLEAR_LINK_SHIFT)
210 
211 /* Bitfield definition for register of struct array GROUP1: TOGGLE */
212 /*
213  * LINK (RW)
214  *
215  * denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral
216  * 0: peripheral is not needed
217  * 1: periphera is needed
218  */
219 #define SYSCTL_GROUP1_TOGGLE_LINK_MASK (0xFFFFFFFFUL)
220 #define SYSCTL_GROUP1_TOGGLE_LINK_SHIFT (0U)
221 #define SYSCTL_GROUP1_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_TOGGLE_LINK_SHIFT) & SYSCTL_GROUP1_TOGGLE_LINK_MASK)
222 #define SYSCTL_GROUP1_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_TOGGLE_LINK_MASK) >> SYSCTL_GROUP1_TOGGLE_LINK_SHIFT)
223 
224 /* Bitfield definition for register of struct array AFFILIATE: VALUE */
225 /*
226  * LINK (RW)
227  *
228  * Affiliate groups of cpu0
229  * bit0: cpu0 depends on logic node0
230  * bit1: cpu0 depends on logic node1
231  * bit2: cpu0 depends on logic node2
232  * bit3: cpu0 depends on logic node3
233  */
234 #define SYSCTL_AFFILIATE_VALUE_LINK_MASK (0xFU)
235 #define SYSCTL_AFFILIATE_VALUE_LINK_SHIFT (0U)
236 #define SYSCTL_AFFILIATE_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_VALUE_LINK_SHIFT) & SYSCTL_AFFILIATE_VALUE_LINK_MASK)
237 #define SYSCTL_AFFILIATE_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_VALUE_LINK_MASK) >> SYSCTL_AFFILIATE_VALUE_LINK_SHIFT)
238 
239 /* Bitfield definition for register of struct array AFFILIATE: SET */
240 /*
241  * LINK (RW)
242  *
243  * Affiliate groups of cpu0
244  * bit0: cpu0 depends on logic node0
245  * bit1: cpu0 depends on logic node1
246  * bit2: cpu0 depends on logic node2
247  * bit3: cpu0 depends on logic node3
248  */
249 #define SYSCTL_AFFILIATE_SET_LINK_MASK (0xFU)
250 #define SYSCTL_AFFILIATE_SET_LINK_SHIFT (0U)
251 #define SYSCTL_AFFILIATE_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_SET_LINK_SHIFT) & SYSCTL_AFFILIATE_SET_LINK_MASK)
252 #define SYSCTL_AFFILIATE_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_SET_LINK_MASK) >> SYSCTL_AFFILIATE_SET_LINK_SHIFT)
253 
254 /* Bitfield definition for register of struct array AFFILIATE: CLEAR */
255 /*
256  * LINK (RW)
257  *
258  * Affiliate groups of cpu0
259  * bit0: cpu0 depends on logic node0
260  * bit1: cpu0 depends on logic node1
261  * bit2: cpu0 depends on logic node2
262  * bit3: cpu0 depends on logic node3
263  */
264 #define SYSCTL_AFFILIATE_CLEAR_LINK_MASK (0xFU)
265 #define SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT (0U)
266 #define SYSCTL_AFFILIATE_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK)
267 #define SYSCTL_AFFILIATE_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK) >> SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT)
268 
269 /* Bitfield definition for register of struct array AFFILIATE: TOGGLE */
270 /*
271  * LINK (RW)
272  *
273  * Affiliate groups of cpu0
274  * bit0: cpu0 depends on logic node0
275  * bit1: cpu0 depends on logic node1
276  * bit2: cpu0 depends on logic node2
277  * bit3: cpu0 depends on logic node3
278  */
279 #define SYSCTL_AFFILIATE_TOGGLE_LINK_MASK (0xFU)
280 #define SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT (0U)
281 #define SYSCTL_AFFILIATE_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK)
282 #define SYSCTL_AFFILIATE_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK) >> SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT)
283 
284 /* Bitfield definition for register of struct array RETENTION: VALUE */
285 /*
286  * LINK (RW)
287  *
288  * retention setting while system sleep, each bit represents a resource
289  * bit0: soc_pow
290  * bit1: soc_rst
291  * bit2: cpu0_pow
292  * bit3: cpu0_rst
293  * bit4: cpu1_pow
294  * bit5: cpu1_rst
295  * bit6: con_pow
296  * bit7: con_rst
297  * bit8: vis_pow
298  * bit9: vis_rst
299  * bit10: xtal
300  * bit11: pll0
301  * bit12: pll1
302  * bit13: pll2
303  * bit14: pll3
304  * bit15: pll4
305  */
306 #define SYSCTL_RETENTION_VALUE_LINK_MASK (0x3FFFFUL)
307 #define SYSCTL_RETENTION_VALUE_LINK_SHIFT (0U)
308 #define SYSCTL_RETENTION_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_VALUE_LINK_SHIFT) & SYSCTL_RETENTION_VALUE_LINK_MASK)
309 #define SYSCTL_RETENTION_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_VALUE_LINK_MASK) >> SYSCTL_RETENTION_VALUE_LINK_SHIFT)
310 
311 /* Bitfield definition for register of struct array RETENTION: SET */
312 /*
313  * LINK (RW)
314  *
315  * retention setting while system sleep
316  */
317 #define SYSCTL_RETENTION_SET_LINK_MASK (0x3FFFFUL)
318 #define SYSCTL_RETENTION_SET_LINK_SHIFT (0U)
319 #define SYSCTL_RETENTION_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_SET_LINK_SHIFT) & SYSCTL_RETENTION_SET_LINK_MASK)
320 #define SYSCTL_RETENTION_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_SET_LINK_MASK) >> SYSCTL_RETENTION_SET_LINK_SHIFT)
321 
322 /* Bitfield definition for register of struct array RETENTION: CLEAR */
323 /*
324  * LINK (RW)
325  *
326  * retention setting while system sleep
327  */
328 #define SYSCTL_RETENTION_CLEAR_LINK_MASK (0x3FFFFUL)
329 #define SYSCTL_RETENTION_CLEAR_LINK_SHIFT (0U)
330 #define SYSCTL_RETENTION_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_CLEAR_LINK_SHIFT) & SYSCTL_RETENTION_CLEAR_LINK_MASK)
331 #define SYSCTL_RETENTION_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_CLEAR_LINK_MASK) >> SYSCTL_RETENTION_CLEAR_LINK_SHIFT)
332 
333 /* Bitfield definition for register of struct array RETENTION: TOGGLE */
334 /*
335  * LINK (RW)
336  *
337  * retention setting while system sleep
338  */
339 #define SYSCTL_RETENTION_TOGGLE_LINK_MASK (0x3FFFFUL)
340 #define SYSCTL_RETENTION_TOGGLE_LINK_SHIFT (0U)
341 #define SYSCTL_RETENTION_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_TOGGLE_LINK_SHIFT) & SYSCTL_RETENTION_TOGGLE_LINK_MASK)
342 #define SYSCTL_RETENTION_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_TOGGLE_LINK_MASK) >> SYSCTL_RETENTION_TOGGLE_LINK_SHIFT)
343 
344 /* Bitfield definition for register of struct array POWER: STATUS */
345 /*
346  * FLAG (RW)
347  *
348  * flag represents power cycle happened from last clear of this bit
349  * 0: power domain did not edurance power cycle since last clear of this bit
350  * 1: power domain enduranced power cycle since last clear of this bit
351  */
352 #define SYSCTL_POWER_STATUS_FLAG_MASK (0x80000000UL)
353 #define SYSCTL_POWER_STATUS_FLAG_SHIFT (31U)
354 #define SYSCTL_POWER_STATUS_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_SHIFT) & SYSCTL_POWER_STATUS_FLAG_MASK)
355 #define SYSCTL_POWER_STATUS_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_MASK) >> SYSCTL_POWER_STATUS_FLAG_SHIFT)
356 
357 /*
358  * FLAG_WAKE (RW)
359  *
360  * flag represents wakeup power cycle happened from last clear of this bit
361  * 0: power domain did not edurance wakeup power cycle since last clear of this bit
362  * 1: power domain enduranced wakeup power cycle since last clear of this bit
363  */
364 #define SYSCTL_POWER_STATUS_FLAG_WAKE_MASK (0x40000000UL)
365 #define SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT (30U)
366 #define SYSCTL_POWER_STATUS_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK)
367 #define SYSCTL_POWER_STATUS_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK) >> SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT)
368 
369 /*
370  * LF_DISABLE (RO)
371  *
372  * low fanout power switch disable
373  * 0: low fanout power switches are turned on
374  * 1: low fanout power switches are truned off
375  */
376 #define SYSCTL_POWER_STATUS_LF_DISABLE_MASK (0x1000U)
377 #define SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT (12U)
378 #define SYSCTL_POWER_STATUS_LF_DISABLE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_DISABLE_MASK) >> SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT)
379 
380 /*
381  * LF_ACK (RO)
382  *
383  * low fanout power switch feedback
384  * 0: low fanout power switches are turned on
385  * 1: low fanout power switches are truned off
386  */
387 #define SYSCTL_POWER_STATUS_LF_ACK_MASK (0x100U)
388 #define SYSCTL_POWER_STATUS_LF_ACK_SHIFT (8U)
389 #define SYSCTL_POWER_STATUS_LF_ACK_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_ACK_MASK) >> SYSCTL_POWER_STATUS_LF_ACK_SHIFT)
390 
391 /* Bitfield definition for register of struct array POWER: LF_WAIT */
392 /*
393  * WAIT (RW)
394  *
395  * wait time for low fan out power switch turn on, default value is 255
396  * 0: 0 clock cycle
397  * 1: 1 clock cycles
398  * . . .
399  * clock cycles count on 24MHz
400  */
401 #define SYSCTL_POWER_LF_WAIT_WAIT_MASK (0xFFFFFUL)
402 #define SYSCTL_POWER_LF_WAIT_WAIT_SHIFT (0U)
403 #define SYSCTL_POWER_LF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_LF_WAIT_WAIT_MASK)
404 #define SYSCTL_POWER_LF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_LF_WAIT_WAIT_MASK) >> SYSCTL_POWER_LF_WAIT_WAIT_SHIFT)
405 
406 /* Bitfield definition for register of struct array POWER: OFF_WAIT */
407 /*
408  * WAIT (RW)
409  *
410  * wait time for power switch turn off, default value is 15
411  * 0: 0 clock cycle
412  * 1: 1 clock cycles
413  * . . .
414  * clock cycles count on 24MHz
415  */
416 #define SYSCTL_POWER_OFF_WAIT_WAIT_MASK (0xFFFFFUL)
417 #define SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT (0U)
418 #define SYSCTL_POWER_OFF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK)
419 #define SYSCTL_POWER_OFF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK) >> SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT)
420 
421 /* Bitfield definition for register of struct array RESET: CONTROL */
422 /*
423  * FLAG (RW)
424  *
425  * flag represents reset happened from last clear of this bit
426  * 0: domain did not edurance reset cycle since last clear of this bit
427  * 1: domain enduranced reset cycle since last clear of this bit
428  */
429 #define SYSCTL_RESET_CONTROL_FLAG_MASK (0x80000000UL)
430 #define SYSCTL_RESET_CONTROL_FLAG_SHIFT (31U)
431 #define SYSCTL_RESET_CONTROL_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_MASK)
432 #define SYSCTL_RESET_CONTROL_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_MASK) >> SYSCTL_RESET_CONTROL_FLAG_SHIFT)
433 
434 /*
435  * FLAG_WAKE (RW)
436  *
437  * flag represents wakeup reset happened from last clear of this bit
438  * 0: domain did not edurance wakeup reset cycle since last clear of this bit
439  * 1: domain enduranced wakeup reset cycle since last clear of this bit
440  */
441 #define SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK (0x40000000UL)
442 #define SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT (30U)
443 #define SYSCTL_RESET_CONTROL_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK)
444 #define SYSCTL_RESET_CONTROL_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK) >> SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT)
445 
446 /*
447  * HOLD (RW)
448  *
449  * perform reset and hold in reset, until ths bit cleared by software
450  * 0: reset is released for function
451  * 1: reset is assert and hold
452  */
453 #define SYSCTL_RESET_CONTROL_HOLD_MASK (0x10U)
454 #define SYSCTL_RESET_CONTROL_HOLD_SHIFT (4U)
455 #define SYSCTL_RESET_CONTROL_HOLD_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_HOLD_SHIFT) & SYSCTL_RESET_CONTROL_HOLD_MASK)
456 #define SYSCTL_RESET_CONTROL_HOLD_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_HOLD_MASK) >> SYSCTL_RESET_CONTROL_HOLD_SHIFT)
457 
458 /*
459  * RESET (RW)
460  *
461  * perform reset and release imediately
462  * 0: reset is released
463  * 1 reset is asserted and will release automatically
464  */
465 #define SYSCTL_RESET_CONTROL_RESET_MASK (0x1U)
466 #define SYSCTL_RESET_CONTROL_RESET_SHIFT (0U)
467 #define SYSCTL_RESET_CONTROL_RESET_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_RESET_SHIFT) & SYSCTL_RESET_CONTROL_RESET_MASK)
468 #define SYSCTL_RESET_CONTROL_RESET_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_RESET_MASK) >> SYSCTL_RESET_CONTROL_RESET_SHIFT)
469 
470 /* Bitfield definition for register of struct array RESET: CONFIG */
471 /*
472  * PRE_WAIT (RW)
473  *
474  * wait cycle numbers before assert reset
475  * 0: wait 0 cycle
476  * 1: wait 1 cycles
477  * . . .
478  * Note, clock cycle is base on 24M
479  */
480 #define SYSCTL_RESET_CONFIG_PRE_WAIT_MASK (0xFF0000UL)
481 #define SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT (16U)
482 #define SYSCTL_RESET_CONFIG_PRE_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK)
483 #define SYSCTL_RESET_CONFIG_PRE_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK) >> SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT)
484 
485 /*
486  * RSTCLK_NUM (RW)
487  *
488  * reset clock number(must be even number)
489  * 0: 0 cycle
490  * 1: 0 cycles
491  * 2: 2 cycles
492  * 3: 2 cycles
493  * . . .
494  * Note, clock cycle is base on 24M
495  */
496 #define SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK (0xFF00U)
497 #define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT (8U)
498 #define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK)
499 #define SYSCTL_RESET_CONFIG_RSTCLK_NUM_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK) >> SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT)
500 
501 /*
502  * POST_WAIT (RW)
503  *
504  * time guard band for reset release
505  * 0: wait 0 cycle
506  * 1: wait 1 cycles
507  * . . .
508  * Note, clock cycle is base on 24M
509  */
510 #define SYSCTL_RESET_CONFIG_POST_WAIT_MASK (0xFFU)
511 #define SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT (0U)
512 #define SYSCTL_RESET_CONFIG_POST_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK)
513 #define SYSCTL_RESET_CONFIG_POST_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK) >> SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT)
514 
515 /* Bitfield definition for register of struct array RESET: COUNTER */
516 /*
517  * COUNTER (RW)
518  *
519  * self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset
520  * 0: wait 0 cycle
521  * 1: wait 1 cycles
522  * . . .
523  * Note, clock cycle is base on 24M
524  */
525 #define SYSCTL_RESET_COUNTER_COUNTER_MASK (0xFFFFFUL)
526 #define SYSCTL_RESET_COUNTER_COUNTER_SHIFT (0U)
527 #define SYSCTL_RESET_COUNTER_COUNTER_SET(x) (((uint32_t)(x) << SYSCTL_RESET_COUNTER_COUNTER_SHIFT) & SYSCTL_RESET_COUNTER_COUNTER_MASK)
528 #define SYSCTL_RESET_COUNTER_COUNTER_GET(x) (((uint32_t)(x) & SYSCTL_RESET_COUNTER_COUNTER_MASK) >> SYSCTL_RESET_COUNTER_COUNTER_SHIFT)
529 
530 /* Bitfield definition for register array: CLOCK */
531 /*
532  * GLB_BUSY (RO)
533  *
534  * global busy
535  * 0: no changes pending to any clock
536  * 1: any of nodes is changing status
537  */
538 #define SYSCTL_CLOCK_GLB_BUSY_MASK (0x80000000UL)
539 #define SYSCTL_CLOCK_GLB_BUSY_SHIFT (31U)
540 #define SYSCTL_CLOCK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_GLB_BUSY_MASK) >> SYSCTL_CLOCK_GLB_BUSY_SHIFT)
541 
542 /*
543  * LOC_BUSY (RO)
544  *
545  * local busy
546  * 0: a change is pending for current node
547  * 1: current node is changing status
548  */
549 #define SYSCTL_CLOCK_LOC_BUSY_MASK (0x40000000UL)
550 #define SYSCTL_CLOCK_LOC_BUSY_SHIFT (30U)
551 #define SYSCTL_CLOCK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_LOC_BUSY_MASK) >> SYSCTL_CLOCK_LOC_BUSY_SHIFT)
552 
553 /*
554  * MUX (RW)
555  *
556  * clock source selection
557  * 0:osc0_clk0
558  * 1:pll0_clk0
559  * 2:pll1_clk0
560  * 3:pll1_clk1
561  * 4:pll2_clk0
562  * 5:pll2_clk1
563  * 6:pll3_clk0
564  * 7:pll4_clk0
565  */
566 #define SYSCTL_CLOCK_MUX_MASK (0xF00U)
567 #define SYSCTL_CLOCK_MUX_SHIFT (8U)
568 #define SYSCTL_CLOCK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_MUX_SHIFT) & SYSCTL_CLOCK_MUX_MASK)
569 #define SYSCTL_CLOCK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_MUX_MASK) >> SYSCTL_CLOCK_MUX_SHIFT)
570 
571 /*
572  * DIV (RW)
573  *
574  * clock divider
575  * 0: divider by1
576  * 1: divider by 2
577  * 2 divider by 3
578  * . . .
579  * 255: divider by 256
580  */
581 #define SYSCTL_CLOCK_DIV_MASK (0xFFU)
582 #define SYSCTL_CLOCK_DIV_SHIFT (0U)
583 #define SYSCTL_CLOCK_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_DIV_SHIFT) & SYSCTL_CLOCK_DIV_MASK)
584 #define SYSCTL_CLOCK_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_DIV_MASK) >> SYSCTL_CLOCK_DIV_SHIFT)
585 
586 /* Bitfield definition for register array: ADCCLK */
587 /*
588  * GLB_BUSY (RO)
589  *
590  * global busy
591  * 0: no changes pending to any clock
592  * 1: any of nodes is changing status
593  */
594 #define SYSCTL_ADCCLK_GLB_BUSY_MASK (0x80000000UL)
595 #define SYSCTL_ADCCLK_GLB_BUSY_SHIFT (31U)
596 #define SYSCTL_ADCCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_GLB_BUSY_MASK) >> SYSCTL_ADCCLK_GLB_BUSY_SHIFT)
597 
598 /*
599  * LOC_BUSY (RO)
600  *
601  * local busy
602  * 0: a change is pending for current node
603  * 1: current node is changing status
604  */
605 #define SYSCTL_ADCCLK_LOC_BUSY_MASK (0x40000000UL)
606 #define SYSCTL_ADCCLK_LOC_BUSY_SHIFT (30U)
607 #define SYSCTL_ADCCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_LOC_BUSY_MASK) >> SYSCTL_ADCCLK_LOC_BUSY_SHIFT)
608 
609 /*
610  * MUX (RW)
611  *
612  * clock source selection
613  * 0: ahb clock
614  * 1: adc clock 0
615  * 2: adc clock 1
616  * 3: adc clock 2
617  */
618 #define SYSCTL_ADCCLK_MUX_MASK (0x700U)
619 #define SYSCTL_ADCCLK_MUX_SHIFT (8U)
620 #define SYSCTL_ADCCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_MUX_SHIFT) & SYSCTL_ADCCLK_MUX_MASK)
621 #define SYSCTL_ADCCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_MUX_MASK) >> SYSCTL_ADCCLK_MUX_SHIFT)
622 
623 /* Bitfield definition for register array: I2SCLK */
624 /*
625  * GLB_BUSY (RO)
626  *
627  * global busy
628  * 0: no changes pending to any clock
629  * 1: any of nodes is changing status
630  */
631 #define SYSCTL_I2SCLK_GLB_BUSY_MASK (0x80000000UL)
632 #define SYSCTL_I2SCLK_GLB_BUSY_SHIFT (31U)
633 #define SYSCTL_I2SCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_GLB_BUSY_MASK) >> SYSCTL_I2SCLK_GLB_BUSY_SHIFT)
634 
635 /*
636  * LOC_BUSY (RO)
637  *
638  * local busy
639  * 0: a change is pending for current node
640  * 1: current node is changing status
641  */
642 #define SYSCTL_I2SCLK_LOC_BUSY_MASK (0x40000000UL)
643 #define SYSCTL_I2SCLK_LOC_BUSY_SHIFT (30U)
644 #define SYSCTL_I2SCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_LOC_BUSY_MASK) >> SYSCTL_I2SCLK_LOC_BUSY_SHIFT)
645 
646 /*
647  * MUX (RW)
648  *
649  * clock source selection
650  * 0: ahb clock
651  * 1: i2s clock 0
652  * 2: i2s clock 1
653  * 3: i2s clock 2
654  */
655 #define SYSCTL_I2SCLK_MUX_MASK (0x700U)
656 #define SYSCTL_I2SCLK_MUX_SHIFT (8U)
657 #define SYSCTL_I2SCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_I2SCLK_MUX_SHIFT) & SYSCTL_I2SCLK_MUX_MASK)
658 #define SYSCTL_I2SCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_MUX_MASK) >> SYSCTL_I2SCLK_MUX_SHIFT)
659 
660 /* Bitfield definition for register: GLOBAL00 */
661 /*
662  * PRESET (RW)
663  *
664  * global clock override request
665  * bit0: override to preset0
666  * bit1: override to preset1
667  * bit2: override to preset2
668  * bit3: override to preset3
669  */
670 #define SYSCTL_GLOBAL00_PRESET_MASK (0xFU)
671 #define SYSCTL_GLOBAL00_PRESET_SHIFT (0U)
672 #define SYSCTL_GLOBAL00_PRESET_SET(x) (((uint32_t)(x) << SYSCTL_GLOBAL00_PRESET_SHIFT) & SYSCTL_GLOBAL00_PRESET_MASK)
673 #define SYSCTL_GLOBAL00_PRESET_GET(x) (((uint32_t)(x) & SYSCTL_GLOBAL00_PRESET_MASK) >> SYSCTL_GLOBAL00_PRESET_SHIFT)
674 
675 /* Bitfield definition for register of struct array MONITOR: CONTROL */
676 /*
677  * VALID (RW)
678  *
679  * result is ready for read
680  * 0: not ready
681  * 1: result is ready
682  */
683 #define SYSCTL_MONITOR_CONTROL_VALID_MASK (0x80000000UL)
684 #define SYSCTL_MONITOR_CONTROL_VALID_SHIFT (31U)
685 #define SYSCTL_MONITOR_CONTROL_VALID_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_VALID_SHIFT) & SYSCTL_MONITOR_CONTROL_VALID_MASK)
686 #define SYSCTL_MONITOR_CONTROL_VALID_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_VALID_MASK) >> SYSCTL_MONITOR_CONTROL_VALID_SHIFT)
687 
688 /*
689  * DIV_BUSY (RO)
690  *
691  * divider is applying new setting
692  */
693 #define SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK (0x8000000UL)
694 #define SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT (27U)
695 #define SYSCTL_MONITOR_CONTROL_DIV_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT)
696 
697 /*
698  * OUTEN (RW)
699  *
700  * enable clock output
701  */
702 #define SYSCTL_MONITOR_CONTROL_OUTEN_MASK (0x1000000UL)
703 #define SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT (24U)
704 #define SYSCTL_MONITOR_CONTROL_OUTEN_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK)
705 #define SYSCTL_MONITOR_CONTROL_OUTEN_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK) >> SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT)
706 
707 /*
708  * DIV (RW)
709  *
710  * output divider
711  */
712 #define SYSCTL_MONITOR_CONTROL_DIV_MASK (0xFF0000UL)
713 #define SYSCTL_MONITOR_CONTROL_DIV_SHIFT (16U)
714 #define SYSCTL_MONITOR_CONTROL_DIV_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_DIV_SHIFT) & SYSCTL_MONITOR_CONTROL_DIV_MASK)
715 #define SYSCTL_MONITOR_CONTROL_DIV_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_SHIFT)
716 
717 /*
718  * HIGH (RW)
719  *
720  * clock frequency higher than upper limit
721  */
722 #define SYSCTL_MONITOR_CONTROL_HIGH_MASK (0x8000U)
723 #define SYSCTL_MONITOR_CONTROL_HIGH_SHIFT (15U)
724 #define SYSCTL_MONITOR_CONTROL_HIGH_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_HIGH_SHIFT) & SYSCTL_MONITOR_CONTROL_HIGH_MASK)
725 #define SYSCTL_MONITOR_CONTROL_HIGH_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_HIGH_MASK) >> SYSCTL_MONITOR_CONTROL_HIGH_SHIFT)
726 
727 /*
728  * LOW (RW)
729  *
730  * clock frequency lower than lower limit
731  */
732 #define SYSCTL_MONITOR_CONTROL_LOW_MASK (0x4000U)
733 #define SYSCTL_MONITOR_CONTROL_LOW_SHIFT (14U)
734 #define SYSCTL_MONITOR_CONTROL_LOW_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_LOW_SHIFT) & SYSCTL_MONITOR_CONTROL_LOW_MASK)
735 #define SYSCTL_MONITOR_CONTROL_LOW_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_LOW_MASK) >> SYSCTL_MONITOR_CONTROL_LOW_SHIFT)
736 
737 /*
738  * START (RW)
739  *
740  * start measurement
741  */
742 #define SYSCTL_MONITOR_CONTROL_START_MASK (0x1000U)
743 #define SYSCTL_MONITOR_CONTROL_START_SHIFT (12U)
744 #define SYSCTL_MONITOR_CONTROL_START_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_START_SHIFT) & SYSCTL_MONITOR_CONTROL_START_MASK)
745 #define SYSCTL_MONITOR_CONTROL_START_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_START_MASK) >> SYSCTL_MONITOR_CONTROL_START_SHIFT)
746 
747 /*
748  * MODE (RW)
749  *
750  * work mode,
751  * 0: register value will be compared to measurement
752  * 1: upper and lower value will be recordered in register
753  */
754 #define SYSCTL_MONITOR_CONTROL_MODE_MASK (0x400U)
755 #define SYSCTL_MONITOR_CONTROL_MODE_SHIFT (10U)
756 #define SYSCTL_MONITOR_CONTROL_MODE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_MODE_SHIFT) & SYSCTL_MONITOR_CONTROL_MODE_MASK)
757 #define SYSCTL_MONITOR_CONTROL_MODE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_MODE_MASK) >> SYSCTL_MONITOR_CONTROL_MODE_SHIFT)
758 
759 /*
760  * ACCURACY (RW)
761  *
762  * measurement accuracy,
763  * 0: resolution is 1kHz
764  * 1: resolution is 1Hz
765  */
766 #define SYSCTL_MONITOR_CONTROL_ACCURACY_MASK (0x200U)
767 #define SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT (9U)
768 #define SYSCTL_MONITOR_CONTROL_ACCURACY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK)
769 #define SYSCTL_MONITOR_CONTROL_ACCURACY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK) >> SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT)
770 
771 /*
772  * REFERENCE (RW)
773  *
774  * reference clock selection,
775  * 0: 32k
776  * 1: 24M
777  */
778 #define SYSCTL_MONITOR_CONTROL_REFERENCE_MASK (0x100U)
779 #define SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT (8U)
780 #define SYSCTL_MONITOR_CONTROL_REFERENCE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK)
781 #define SYSCTL_MONITOR_CONTROL_REFERENCE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK) >> SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT)
782 
783 /*
784  * SELECTION (RW)
785  *
786  * clock measurement selection
787  */
788 #define SYSCTL_MONITOR_CONTROL_SELECTION_MASK (0xFFU)
789 #define SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT (0U)
790 #define SYSCTL_MONITOR_CONTROL_SELECTION_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK)
791 #define SYSCTL_MONITOR_CONTROL_SELECTION_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK) >> SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT)
792 
793 /* Bitfield definition for register of struct array MONITOR: CURRENT */
794 /*
795  * FREQUENCY (RO)
796  *
797  * self updating measure result
798  */
799 #define SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK (0xFFFFFFFFUL)
800 #define SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT (0U)
801 #define SYSCTL_MONITOR_CURRENT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK) >> SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT)
802 
803 /* Bitfield definition for register of struct array MONITOR: LOW_LIMIT */
804 /*
805  * FREQUENCY (RW)
806  *
807  * lower frequency
808  */
809 #define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL)
810 #define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT (0U)
811 #define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK)
812 #define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT)
813 
814 /* Bitfield definition for register of struct array MONITOR: HIGH_LIMIT */
815 /*
816  * FREQUENCY (RW)
817  *
818  * upper frequency
819  */
820 #define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL)
821 #define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT (0U)
822 #define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK)
823 #define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT)
824 
825 /* Bitfield definition for register of struct array CPU: LP */
826 /*
827  * WAKE_CNT (RW)
828  *
829  * CPU0 wake up counter, counter saturated at 255, write 0x00 to clear
830  */
831 #define SYSCTL_CPU_LP_WAKE_CNT_MASK (0xFF000000UL)
832 #define SYSCTL_CPU_LP_WAKE_CNT_SHIFT (24U)
833 #define SYSCTL_CPU_LP_WAKE_CNT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_CNT_SHIFT) & SYSCTL_CPU_LP_WAKE_CNT_MASK)
834 #define SYSCTL_CPU_LP_WAKE_CNT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_CNT_MASK) >> SYSCTL_CPU_LP_WAKE_CNT_SHIFT)
835 
836 /*
837  * HALT (RW)
838  *
839  * halt request for CPU0,
840  * 0: CPU0 will start to execute after reset or receive wakeup request
841  * 1: CPU0 will not start after reset, or wakeup after WFI
842  */
843 #define SYSCTL_CPU_LP_HALT_MASK (0x10000UL)
844 #define SYSCTL_CPU_LP_HALT_SHIFT (16U)
845 #define SYSCTL_CPU_LP_HALT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_HALT_SHIFT) & SYSCTL_CPU_LP_HALT_MASK)
846 #define SYSCTL_CPU_LP_HALT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_HALT_MASK) >> SYSCTL_CPU_LP_HALT_SHIFT)
847 
848 /*
849  * WAKE (RO)
850  *
851  * CPU0 is waking up
852  * 0: CPU0 wake up not asserted
853  * 1: CPU0 wake up asserted
854  */
855 #define SYSCTL_CPU_LP_WAKE_MASK (0x2000U)
856 #define SYSCTL_CPU_LP_WAKE_SHIFT (13U)
857 #define SYSCTL_CPU_LP_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_MASK) >> SYSCTL_CPU_LP_WAKE_SHIFT)
858 
859 /*
860  * EXEC (RO)
861  *
862  * CPU0 is executing
863  * 0: CPU0 is not executing
864  * 1: CPU0 is executing
865  */
866 #define SYSCTL_CPU_LP_EXEC_MASK (0x1000U)
867 #define SYSCTL_CPU_LP_EXEC_SHIFT (12U)
868 #define SYSCTL_CPU_LP_EXEC_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_EXEC_MASK) >> SYSCTL_CPU_LP_EXEC_SHIFT)
869 
870 /*
871  * WAKE_FLAG (RW)
872  *
873  * CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit
874  * 0: CPU0 wakeup not happened
875  * 1: CPU0 wakeup happened
876  */
877 #define SYSCTL_CPU_LP_WAKE_FLAG_MASK (0x400U)
878 #define SYSCTL_CPU_LP_WAKE_FLAG_SHIFT (10U)
879 #define SYSCTL_CPU_LP_WAKE_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_FLAG_SHIFT) & SYSCTL_CPU_LP_WAKE_FLAG_MASK)
880 #define SYSCTL_CPU_LP_WAKE_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_FLAG_MASK) >> SYSCTL_CPU_LP_WAKE_FLAG_SHIFT)
881 
882 /*
883  * SLEEP_FLAG (RW)
884  *
885  * CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit
886  * 0: CPU0 sleep not happened
887  * 1: CPU0 sleep happened
888  */
889 #define SYSCTL_CPU_LP_SLEEP_FLAG_MASK (0x200U)
890 #define SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT (9U)
891 #define SYSCTL_CPU_LP_SLEEP_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK)
892 #define SYSCTL_CPU_LP_SLEEP_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK) >> SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT)
893 
894 /*
895  * RESET_FLAG (RW)
896  *
897  * CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit
898  * 0: CPU0 sleep not happened
899  * 1: CPU0 sleep happened
900  */
901 #define SYSCTL_CPU_LP_RESET_FLAG_MASK (0x100U)
902 #define SYSCTL_CPU_LP_RESET_FLAG_SHIFT (8U)
903 #define SYSCTL_CPU_LP_RESET_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_RESET_FLAG_SHIFT) & SYSCTL_CPU_LP_RESET_FLAG_MASK)
904 #define SYSCTL_CPU_LP_RESET_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_RESET_FLAG_MASK) >> SYSCTL_CPU_LP_RESET_FLAG_SHIFT)
905 
906 /*
907  * MODE (RW)
908  *
909  * Low power mode, system behavior after WFI
910  * 00: CPU clock stop after WFI
911  * 01: System enter low power mode after WFI
912  * 10: Keep running after WFI
913  * 11: reserved
914  */
915 #define SYSCTL_CPU_LP_MODE_MASK (0x3U)
916 #define SYSCTL_CPU_LP_MODE_SHIFT (0U)
917 #define SYSCTL_CPU_LP_MODE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_MODE_SHIFT) & SYSCTL_CPU_LP_MODE_MASK)
918 #define SYSCTL_CPU_LP_MODE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_MODE_MASK) >> SYSCTL_CPU_LP_MODE_SHIFT)
919 
920 /* Bitfield definition for register of struct array CPU: LOCK */
921 /*
922  * GPR (RW)
923  *
924  * Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset
925  */
926 #define SYSCTL_CPU_LOCK_GPR_MASK (0xFFFCU)
927 #define SYSCTL_CPU_LOCK_GPR_SHIFT (2U)
928 #define SYSCTL_CPU_LOCK_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_GPR_SHIFT) & SYSCTL_CPU_LOCK_GPR_MASK)
929 #define SYSCTL_CPU_LOCK_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_GPR_MASK) >> SYSCTL_CPU_LOCK_GPR_SHIFT)
930 
931 /*
932  * LOCK (RW)
933  *
934  * Lock bit for CPU_LOCK
935  */
936 #define SYSCTL_CPU_LOCK_LOCK_MASK (0x2U)
937 #define SYSCTL_CPU_LOCK_LOCK_SHIFT (1U)
938 #define SYSCTL_CPU_LOCK_LOCK_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_LOCK_SHIFT) & SYSCTL_CPU_LOCK_LOCK_MASK)
939 #define SYSCTL_CPU_LOCK_LOCK_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_LOCK_MASK) >> SYSCTL_CPU_LOCK_LOCK_SHIFT)
940 
941 /* Bitfield definition for register of struct array CPU: GPR0 */
942 /*
943  * GPR (RW)
944  *
945  * register for software to handle resume, can save resume address or status
946  */
947 #define SYSCTL_CPU_GPR_GPR_MASK (0xFFFFFFFFUL)
948 #define SYSCTL_CPU_GPR_GPR_SHIFT (0U)
949 #define SYSCTL_CPU_GPR_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_GPR_GPR_SHIFT) & SYSCTL_CPU_GPR_GPR_MASK)
950 #define SYSCTL_CPU_GPR_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_GPR_GPR_MASK) >> SYSCTL_CPU_GPR_GPR_SHIFT)
951 
952 /* Bitfield definition for register of struct array CPU: STATUS0 */
953 /*
954  * STATUS (RO)
955  *
956  * IRQ values
957  */
958 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK (0xFFFFFFFFUL)
959 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT (0U)
960 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK) >> SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT)
961 
962 /* Bitfield definition for register of struct array CPU: ENABLE0 */
963 /*
964  * ENABLE (RW)
965  *
966  * IRQ wakeup enable
967  */
968 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK (0xFFFFFFFFUL)
969 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT (0U)
970 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK)
971 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK) >> SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT)
972 
973 
974 
975 /* RESOURCE register group index macro definition */
976 #define SYSCTL_RESOURCE_CPU0_CORE (0UL)
977 #define SYSCTL_RESOURCE_CPU0_SUBSYS (1UL)
978 #define SYSCTL_RESOURCE_CPU1_CORE (8UL)
979 #define SYSCTL_RESOURCE_CPX1_SUBSYS (9UL)
980 #define SYSCTL_RESOURCE_POW_CON (21UL)
981 #define SYSCTL_RESOURCE_POW_VIS (22UL)
982 #define SYSCTL_RESOURCE_POW_CPU0 (23UL)
983 #define SYSCTL_RESOURCE_POW_CPU1 (24UL)
984 #define SYSCTL_RESOURCE_RST_SOC (25UL)
985 #define SYSCTL_RESOURCE_RST_CON (26UL)
986 #define SYSCTL_RESOURCE_RST_VIS (27UL)
987 #define SYSCTL_RESOURCE_RST_CPU0 (28UL)
988 #define SYSCTL_RESOURCE_RST_CPU1 (29UL)
989 #define SYSCTL_RESOURCE_CLK_SRC_XTAL (32UL)
990 #define SYSCTL_RESOURCE_CLK_SRC_PLL0 (33UL)
991 #define SYSCTL_RESOURCE_CLK_SRC_PLL0CLK0 (34UL)
992 #define SYSCTL_RESOURCE_CLK_SRC_PLL1 (35UL)
993 #define SYSCTL_RESOURCE_CLK_SRC_PLL1CLK0 (36UL)
994 #define SYSCTL_RESOURCE_CLK_SRC_PLL1CLK1 (37UL)
995 #define SYSCTL_RESOURCE_CLK_SRC_PLL2 (38UL)
996 #define SYSCTL_RESOURCE_CLK_SRC_PLL2CLK0 (39UL)
997 #define SYSCTL_RESOURCE_CLK_SRC_PLL2CLK1 (40UL)
998 #define SYSCTL_RESOURCE_CLK_SRC_PLL3 (41UL)
999 #define SYSCTL_RESOURCE_CLK_SRC_PLL3CLK0 (42UL)
1000 #define SYSCTL_RESOURCE_CLK_SRC_PLL4 (43UL)
1001 #define SYSCTL_RESOURCE_CLK_SRC_PLL4CLK0 (44UL)
1002 #define SYSCTL_RESOURCE_CLK_TOP_CPU0 (64UL)
1003 #define SYSCTL_RESOURCE_CLK_TOP_MCHTMR0 (65UL)
1004 #define SYSCTL_RESOURCE_CLK_TOP_CPU1 (66UL)
1005 #define SYSCTL_RESOURCE_CLK_TOP_MCHTMR1 (67UL)
1006 #define SYSCTL_RESOURCE_CLK_TOP_AXI (68UL)
1007 #define SYSCTL_RESOURCE_CLK_TOP_CONN (69UL)
1008 #define SYSCTL_RESOURCE_CLK_TOP_VIS (70UL)
1009 #define SYSCTL_RESOURCE_CLK_TOP_AHB (71UL)
1010 #define SYSCTL_RESOURCE_CLK_TOP_FEMC (72UL)
1011 #define SYSCTL_RESOURCE_CLK_TOP_XPI0 (73UL)
1012 #define SYSCTL_RESOURCE_CLK_TOP_XPI1 (74UL)
1013 #define SYSCTL_RESOURCE_CLK_TOP_GPTMR0 (75UL)
1014 #define SYSCTL_RESOURCE_CLK_TOP_GPTMR1 (76UL)
1015 #define SYSCTL_RESOURCE_CLK_TOP_GPTMR2 (77UL)
1016 #define SYSCTL_RESOURCE_CLK_TOP_GPTMR3 (78UL)
1017 #define SYSCTL_RESOURCE_CLK_TOP_GPTMR4 (79UL)
1018 #define SYSCTL_RESOURCE_CLK_TOP_GPTMR5 (80UL)
1019 #define SYSCTL_RESOURCE_CLK_TOP_GPTMR6 (81UL)
1020 #define SYSCTL_RESOURCE_CLK_TOP_GPTMR7 (82UL)
1021 #define SYSCTL_RESOURCE_CLK_TOP_UART0 (83UL)
1022 #define SYSCTL_RESOURCE_CLK_TOP_UART1 (84UL)
1023 #define SYSCTL_RESOURCE_CLK_TOP_UART2 (85UL)
1024 #define SYSCTL_RESOURCE_CLK_TOP_UART3 (86UL)
1025 #define SYSCTL_RESOURCE_CLK_TOP_UART4 (87UL)
1026 #define SYSCTL_RESOURCE_CLK_TOP_UART5 (88UL)
1027 #define SYSCTL_RESOURCE_CLK_TOP_UART6 (89UL)
1028 #define SYSCTL_RESOURCE_CLK_TOP_UART7 (90UL)
1029 #define SYSCTL_RESOURCE_CLK_TOP_UART8 (91UL)
1030 #define SYSCTL_RESOURCE_CLK_TOP_UART9 (92UL)
1031 #define SYSCTL_RESOURCE_CLK_TOP_UART10 (93UL)
1032 #define SYSCTL_RESOURCE_CLK_TOP_UART11 (94UL)
1033 #define SYSCTL_RESOURCE_CLK_TOP_UART12 (95UL)
1034 #define SYSCTL_RESOURCE_CLK_TOP_UART13 (96UL)
1035 #define SYSCTL_RESOURCE_CLK_TOP_UART14 (97UL)
1036 #define SYSCTL_RESOURCE_CLK_TOP_UART15 (98UL)
1037 #define SYSCTL_RESOURCE_CLK_TOP_I2C0 (99UL)
1038 #define SYSCTL_RESOURCE_CLK_TOP_I2C1 (100UL)
1039 #define SYSCTL_RESOURCE_CLK_TOP_I2C2 (101UL)
1040 #define SYSCTL_RESOURCE_CLK_TOP_I2C3 (102UL)
1041 #define SYSCTL_RESOURCE_CLK_TOP_SPI0 (103UL)
1042 #define SYSCTL_RESOURCE_CLK_TOP_SPI1 (104UL)
1043 #define SYSCTL_RESOURCE_CLK_TOP_SPI2 (105UL)
1044 #define SYSCTL_RESOURCE_CLK_TOP_SPI3 (106UL)
1045 #define SYSCTL_RESOURCE_CLK_TOP_CAN0 (107UL)
1046 #define SYSCTL_RESOURCE_CLK_TOP_CAN1 (108UL)
1047 #define SYSCTL_RESOURCE_CLK_TOP_CAN2 (109UL)
1048 #define SYSCTL_RESOURCE_CLK_TOP_CAN3 (110UL)
1049 #define SYSCTL_RESOURCE_CLK_TOP_PTPC (111UL)
1050 #define SYSCTL_RESOURCE_CLK_TOP_ANA0 (112UL)
1051 #define SYSCTL_RESOURCE_CLK_TOP_ANA1 (113UL)
1052 #define SYSCTL_RESOURCE_CLK_TOP_ANA2 (114UL)
1053 #define SYSCTL_RESOURCE_CLK_TOP_AUD0 (115UL)
1054 #define SYSCTL_RESOURCE_CLK_TOP_AUD1 (116UL)
1055 #define SYSCTL_RESOURCE_CLK_TOP_AUD2 (117UL)
1056 #define SYSCTL_RESOURCE_CLK_TOP_LCDC (118UL)
1057 #define SYSCTL_RESOURCE_CLK_TOP_CAM0 (119UL)
1058 #define SYSCTL_RESOURCE_CLK_TOP_CAM1 (120UL)
1059 #define SYSCTL_RESOURCE_CLK_TOP_ENET0 (121UL)
1060 #define SYSCTL_RESOURCE_CLK_TOP_ENET1 (122UL)
1061 #define SYSCTL_RESOURCE_CLK_TOP_PTP0 (123UL)
1062 #define SYSCTL_RESOURCE_CLK_TOP_PTP1 (124UL)
1063 #define SYSCTL_RESOURCE_CLK_TOP_REF0 (125UL)
1064 #define SYSCTL_RESOURCE_CLK_TOP_REF1 (126UL)
1065 #define SYSCTL_RESOURCE_CLK_TOP_NTMR0 (127UL)
1066 #define SYSCTL_RESOURCE_CLK_TOP_NTMR1 (128UL)
1067 #define SYSCTL_RESOURCE_CLK_TOP_SDXC0 (129UL)
1068 #define SYSCTL_RESOURCE_CLK_TOP_SDXC1 (130UL)
1069 #define SYSCTL_RESOURCE_CLK_TOP_ADC0 (192UL)
1070 #define SYSCTL_RESOURCE_CLK_TOP_ADC1 (193UL)
1071 #define SYSCTL_RESOURCE_CLK_TOP_ADC2 (194UL)
1072 #define SYSCTL_RESOURCE_CLK_TOP_ADC3 (195UL)
1073 #define SYSCTL_RESOURCE_CLK_TOP_I2S0 (196UL)
1074 #define SYSCTL_RESOURCE_CLK_TOP_I2S1 (197UL)
1075 #define SYSCTL_RESOURCE_CLK_TOP_I2S2 (198UL)
1076 #define SYSCTL_RESOURCE_CLK_TOP_I2S3 (199UL)
1077 #define SYSCTL_RESOURCE_AHBAPB_BUS (256UL)
1078 #define SYSCTL_RESOURCE_AXI_BUS (257UL)
1079 #define SYSCTL_RESOURCE_CONN_BUS (258UL)
1080 #define SYSCTL_RESOURCE_VIS_BUS (259UL)
1081 #define SYSCTL_RESOURCE_FEMC (260UL)
1082 #define SYSCTL_RESOURCE_ROM (261UL)
1083 #define SYSCTL_RESOURCE_LMM0 (262UL)
1084 #define SYSCTL_RESOURCE_LMM1 (263UL)
1085 #define SYSCTL_RESOURCE_MCHTMR0 (264UL)
1086 #define SYSCTL_RESOURCE_MCHTMR1 (265UL)
1087 #define SYSCTL_RESOURCE_AXI_SRAM0 (266UL)
1088 #define SYSCTL_RESOURCE_AXI_SRAM1 (267UL)
1089 #define SYSCTL_RESOURCE_XPI0 (268UL)
1090 #define SYSCTL_RESOURCE_XPI1 (269UL)
1091 #define SYSCTL_RESOURCE_SDP (270UL)
1092 #define SYSCTL_RESOURCE_RNG (271UL)
1093 #define SYSCTL_RESOURCE_KEYM (272UL)
1094 #define SYSCTL_RESOURCE_HDMA (273UL)
1095 #define SYSCTL_RESOURCE_XDMA (274UL)
1096 #define SYSCTL_RESOURCE_GPIO (275UL)
1097 #define SYSCTL_RESOURCE_MBX0 (276UL)
1098 #define SYSCTL_RESOURCE_MBX1 (277UL)
1099 #define SYSCTL_RESOURCE_WDG0 (278UL)
1100 #define SYSCTL_RESOURCE_WDG1 (279UL)
1101 #define SYSCTL_RESOURCE_WDG2 (280UL)
1102 #define SYSCTL_RESOURCE_WDG3 (281UL)
1103 #define SYSCTL_RESOURCE_GPTMR0 (282UL)
1104 #define SYSCTL_RESOURCE_GPTMR1 (283UL)
1105 #define SYSCTL_RESOURCE_GPTMR2 (284UL)
1106 #define SYSCTL_RESOURCE_GPTMR3 (285UL)
1107 #define SYSCTL_RESOURCE_GPTMR4 (286UL)
1108 #define SYSCTL_RESOURCE_GPTMR5 (287UL)
1109 #define SYSCTL_RESOURCE_GPTMR6 (288UL)
1110 #define SYSCTL_RESOURCE_GPTMR7 (289UL)
1111 #define SYSCTL_RESOURCE_UART0 (290UL)
1112 #define SYSCTL_RESOURCE_UART1 (291UL)
1113 #define SYSCTL_RESOURCE_UART2 (292UL)
1114 #define SYSCTL_RESOURCE_UART3 (293UL)
1115 #define SYSCTL_RESOURCE_UART4 (294UL)
1116 #define SYSCTL_RESOURCE_UART5 (295UL)
1117 #define SYSCTL_RESOURCE_UART6 (296UL)
1118 #define SYSCTL_RESOURCE_UART7 (297UL)
1119 #define SYSCTL_RESOURCE_UART8 (298UL)
1120 #define SYSCTL_RESOURCE_UART9 (299UL)
1121 #define SYSCTL_RESOURCE_UART10 (300UL)
1122 #define SYSCTL_RESOURCE_UART11 (301UL)
1123 #define SYSCTL_RESOURCE_UART12 (302UL)
1124 #define SYSCTL_RESOURCE_UART13 (303UL)
1125 #define SYSCTL_RESOURCE_UART14 (304UL)
1126 #define SYSCTL_RESOURCE_UART15 (305UL)
1127 #define SYSCTL_RESOURCE_I2C0 (306UL)
1128 #define SYSCTL_RESOURCE_I2C1 (307UL)
1129 #define SYSCTL_RESOURCE_I2C2 (308UL)
1130 #define SYSCTL_RESOURCE_I2C3 (309UL)
1131 #define SYSCTL_RESOURCE_SPI0 (310UL)
1132 #define SYSCTL_RESOURCE_SPI1 (311UL)
1133 #define SYSCTL_RESOURCE_SPI2 (312UL)
1134 #define SYSCTL_RESOURCE_SPI3 (313UL)
1135 #define SYSCTL_RESOURCE_CAN0 (314UL)
1136 #define SYSCTL_RESOURCE_CAN1 (315UL)
1137 #define SYSCTL_RESOURCE_CAN2 (316UL)
1138 #define SYSCTL_RESOURCE_CAN3 (317UL)
1139 #define SYSCTL_RESOURCE_PTPC (318UL)
1140 #define SYSCTL_RESOURCE_ADC0 (319UL)
1141 #define SYSCTL_RESOURCE_ADC1 (320UL)
1142 #define SYSCTL_RESOURCE_ADC2 (321UL)
1143 #define SYSCTL_RESOURCE_ADC3 (322UL)
1144 #define SYSCTL_RESOURCE_ACMP (323UL)
1145 #define SYSCTL_RESOURCE_I2S0 (324UL)
1146 #define SYSCTL_RESOURCE_I2S1 (325UL)
1147 #define SYSCTL_RESOURCE_I2S2 (326UL)
1148 #define SYSCTL_RESOURCE_I2S3 (327UL)
1149 #define SYSCTL_RESOURCE_PDM (328UL)
1150 #define SYSCTL_RESOURCE_DAO (329UL)
1151 #define SYSCTL_RESOURCE_SYNT (330UL)
1152 #define SYSCTL_RESOURCE_MOT0 (331UL)
1153 #define SYSCTL_RESOURCE_MOT1 (332UL)
1154 #define SYSCTL_RESOURCE_MOT2 (333UL)
1155 #define SYSCTL_RESOURCE_MOT3 (334UL)
1156 #define SYSCTL_RESOURCE_LCDC (335UL)
1157 #define SYSCTL_RESOURCE_CAM0 (336UL)
1158 #define SYSCTL_RESOURCE_CAM1 (337UL)
1159 #define SYSCTL_RESOURCE_JPEG (338UL)
1160 #define SYSCTL_RESOURCE_PDMA (339UL)
1161 #define SYSCTL_RESOURCE_ENET0 (340UL)
1162 #define SYSCTL_RESOURCE_ENET1 (341UL)
1163 #define SYSCTL_RESOURCE_NTMR0 (342UL)
1164 #define SYSCTL_RESOURCE_NTMR1 (343UL)
1165 #define SYSCTL_RESOURCE_SDXC0 (344UL)
1166 #define SYSCTL_RESOURCE_SDXC1 (345UL)
1167 #define SYSCTL_RESOURCE_USB0 (346UL)
1168 #define SYSCTL_RESOURCE_USB1 (347UL)
1169 #define SYSCTL_RESOURCE_REF0 (348UL)
1170 #define SYSCTL_RESOURCE_REF1 (349UL)
1171 
1172 /* GROUP0 register group index macro definition */
1173 #define SYSCTL_GROUP0_0 (0UL)
1174 #define SYSCTL_GROUP0_1 (1UL)
1175 #define SYSCTL_GROUP0_2 (2UL)
1176 
1177 /* GROUP1 register group index macro definition */
1178 #define SYSCTL_GROUP1_0 (0UL)
1179 #define SYSCTL_GROUP1_1 (1UL)
1180 #define SYSCTL_GROUP1_2 (2UL)
1181 
1182 /* AFFILIATE register group index macro definition */
1183 #define SYSCTL_AFFILIATE_CPU0 (0UL)
1184 #define SYSCTL_AFFILIATE_CPU1 (1UL)
1185 
1186 /* RETENTION register group index macro definition */
1187 #define SYSCTL_RETENTION_CPU0 (0UL)
1188 #define SYSCTL_RETENTION_CPU1 (1UL)
1189 
1190 /* POWER register group index macro definition */
1191 #define SYSCTL_POWER_CPU0 (0UL)
1192 #define SYSCTL_POWER_CPU1 (1UL)
1193 #define SYSCTL_POWER_CON (2UL)
1194 #define SYSCTL_POWER_VIS (3UL)
1195 
1196 /* RESET register group index macro definition */
1197 #define SYSCTL_RESET_SOC (0UL)
1198 #define SYSCTL_RESET_CON (1UL)
1199 #define SYSCTL_RESET_VIS (2UL)
1200 #define SYSCTL_RESET_CPU0 (3UL)
1201 #define SYSCTL_RESET_CPU1 (4UL)
1202 
1203 /* CLOCK register group index macro definition */
1204 #define SYSCTL_CLOCK_CLK_TOP_CPU0 (0UL)
1205 #define SYSCTL_CLOCK_CLK_TOP_MCHTMR0 (1UL)
1206 #define SYSCTL_CLOCK_CLK_TOP_CPU1 (2UL)
1207 #define SYSCTL_CLOCK_CLK_TOP_MCHTMR (3UL)
1208 #define SYSCTL_CLOCK_CLK_TOP_AXI (4UL)
1209 #define SYSCTL_CLOCK_CLK_TOP_CONN (5UL)
1210 #define SYSCTL_CLOCK_CLK_TOP_VIS (6UL)
1211 #define SYSCTL_CLOCK_CLK_TOP_AHB (7UL)
1212 #define SYSCTL_CLOCK_CLK_TOP_FEMC (8UL)
1213 #define SYSCTL_CLOCK_CLK_TOP_XPI0 (9UL)
1214 #define SYSCTL_CLOCK_CLK_TOP_XPI1 (10UL)
1215 #define SYSCTL_CLOCK_CLK_TOP_GPTMR0 (11UL)
1216 #define SYSCTL_CLOCK_CLK_TOP_GPTMR1 (12UL)
1217 #define SYSCTL_CLOCK_CLK_TOP_GPTMR2 (13UL)
1218 #define SYSCTL_CLOCK_CLK_TOP_GPTMR3 (14UL)
1219 #define SYSCTL_CLOCK_CLK_TOP_GPTMR4 (15UL)
1220 #define SYSCTL_CLOCK_CLK_TOP_GPTMR5 (16UL)
1221 #define SYSCTL_CLOCK_CLK_TOP_GPTMR6 (17UL)
1222 #define SYSCTL_CLOCK_CLK_TOP_GPTMR7 (18UL)
1223 #define SYSCTL_CLOCK_CLK_TOP_UART0 (19UL)
1224 #define SYSCTL_CLOCK_CLK_TOP_UART1 (20UL)
1225 #define SYSCTL_CLOCK_CLK_TOP_UART2 (21UL)
1226 #define SYSCTL_CLOCK_CLK_TOP_UART3 (22UL)
1227 #define SYSCTL_CLOCK_CLK_TOP_UART4 (23UL)
1228 #define SYSCTL_CLOCK_CLK_TOP_UART5 (24UL)
1229 #define SYSCTL_CLOCK_CLK_TOP_UART6 (25UL)
1230 #define SYSCTL_CLOCK_CLK_TOP_UART7 (26UL)
1231 #define SYSCTL_CLOCK_CLK_TOP_UART8 (27UL)
1232 #define SYSCTL_CLOCK_CLK_TOP_UART9 (28UL)
1233 #define SYSCTL_CLOCK_CLK_TOP_UART10 (29UL)
1234 #define SYSCTL_CLOCK_CLK_TOP_UART11 (30UL)
1235 #define SYSCTL_CLOCK_CLK_TOP_UART12 (31UL)
1236 #define SYSCTL_CLOCK_CLK_TOP_UART13 (32UL)
1237 #define SYSCTL_CLOCK_CLK_TOP_UART14 (33UL)
1238 #define SYSCTL_CLOCK_CLK_TOP_UART15 (34UL)
1239 #define SYSCTL_CLOCK_CLK_TOP_I2C0 (35UL)
1240 #define SYSCTL_CLOCK_CLK_TOP_I2C1 (36UL)
1241 #define SYSCTL_CLOCK_CLK_TOP_I2C2 (37UL)
1242 #define SYSCTL_CLOCK_CLK_TOP_I2C3 (38UL)
1243 #define SYSCTL_CLOCK_CLK_TOP_SPI0 (39UL)
1244 #define SYSCTL_CLOCK_CLK_TOP_SPI1 (40UL)
1245 #define SYSCTL_CLOCK_CLK_TOP_SPI2 (41UL)
1246 #define SYSCTL_CLOCK_CLK_TOP_SPI3 (42UL)
1247 #define SYSCTL_CLOCK_CLK_TOP_CAN0 (43UL)
1248 #define SYSCTL_CLOCK_CLK_TOP_CAN1 (44UL)
1249 #define SYSCTL_CLOCK_CLK_TOP_CAN2 (45UL)
1250 #define SYSCTL_CLOCK_CLK_TOP_CAN3 (46UL)
1251 #define SYSCTL_CLOCK_CLK_TOP_PTPC (47UL)
1252 #define SYSCTL_CLOCK_CLK_TOP_ANA0 (48UL)
1253 #define SYSCTL_CLOCK_CLK_TOP_ANA1 (49UL)
1254 #define SYSCTL_CLOCK_CLK_TOP_ANA2 (50UL)
1255 #define SYSCTL_CLOCK_CLK_TOP_AUD0 (51UL)
1256 #define SYSCTL_CLOCK_CLK_TOP_AUD1 (52UL)
1257 #define SYSCTL_CLOCK_CLK_TOP_AUD2 (53UL)
1258 #define SYSCTL_CLOCK_CLK_TOP_LCDC (54UL)
1259 #define SYSCTL_CLOCK_CLK_TOP_CAM0 (55UL)
1260 #define SYSCTL_CLOCK_CLK_TOP_CAM1 (56UL)
1261 #define SYSCTL_CLOCK_CLK_TOP_ENET0 (57UL)
1262 #define SYSCTL_CLOCK_CLK_TOP_ENET1 (58UL)
1263 #define SYSCTL_CLOCK_CLK_TOP_PTP0 (59UL)
1264 #define SYSCTL_CLOCK_CLK_TOP_PTP1 (60UL)
1265 #define SYSCTL_CLOCK_CLK_TOP_REF0 (61UL)
1266 #define SYSCTL_CLOCK_CLK_TOP_REF1 (62UL)
1267 #define SYSCTL_CLOCK_CLK_TOP_NTMR0 (63UL)
1268 #define SYSCTL_CLOCK_CLK_TOP_NTMR1 (64UL)
1269 #define SYSCTL_CLOCK_CLK_TOP_SDXC0 (65UL)
1270 #define SYSCTL_CLOCK_CLK_TOP_SDXC1 (66UL)
1271 
1272 /* ADCCLK register group index macro definition */
1273 #define SYSCTL_ADCCLK_CLK_TOP_ADC0 (0UL)
1274 #define SYSCTL_ADCCLK_CLK_TOP_ADC1 (1UL)
1275 #define SYSCTL_ADCCLK_CLK_TOP_ADC2 (2UL)
1276 #define SYSCTL_ADCCLK_CLK_TOP_ADC3 (3UL)
1277 
1278 /* I2SCLK register group index macro definition */
1279 #define SYSCTL_I2SCLK_CLK_TOP_I2S0 (0UL)
1280 #define SYSCTL_I2SCLK_CLK_TOP_I2S1 (1UL)
1281 #define SYSCTL_I2SCLK_CLK_TOP_I2S2 (2UL)
1282 #define SYSCTL_I2SCLK_CLK_TOP_I2S3 (3UL)
1283 
1284 /* MONITOR register group index macro definition */
1285 #define SYSCTL_MONITOR_SLICE0 (0UL)
1286 #define SYSCTL_MONITOR_SLICE1 (1UL)
1287 #define SYSCTL_MONITOR_SLICE2 (2UL)
1288 #define SYSCTL_MONITOR_SLICE3 (3UL)
1289 
1290 /* GPR register group index macro definition */
1291 #define SYSCTL_CPU_GPR_GPR0 (0UL)
1292 #define SYSCTL_CPU_GPR_GPR1 (1UL)
1293 #define SYSCTL_CPU_GPR_GPR2 (2UL)
1294 #define SYSCTL_CPU_GPR_GPR3 (3UL)
1295 #define SYSCTL_CPU_GPR_GPR4 (4UL)
1296 #define SYSCTL_CPU_GPR_GPR5 (5UL)
1297 #define SYSCTL_CPU_GPR_GPR6 (6UL)
1298 #define SYSCTL_CPU_GPR_GPR7 (7UL)
1299 #define SYSCTL_CPU_GPR_GPR8 (8UL)
1300 #define SYSCTL_CPU_GPR_GPR9 (9UL)
1301 #define SYSCTL_CPU_GPR_GPR10 (10UL)
1302 #define SYSCTL_CPU_GPR_GPR11 (11UL)
1303 #define SYSCTL_CPU_GPR_GPR12 (12UL)
1304 #define SYSCTL_CPU_GPR_GPR13 (13UL)
1305 
1306 /* WAKEUP_STATUS register group index macro definition */
1307 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS0 (0UL)
1308 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS1 (1UL)
1309 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS2 (2UL)
1310 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS3 (3UL)
1311 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS4 (4UL)
1312 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS5 (5UL)
1313 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS6 (6UL)
1314 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS7 (7UL)
1315 
1316 /* WAKEUP_ENABLE register group index macro definition */
1317 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE0 (0UL)
1318 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE1 (1UL)
1319 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE2 (2UL)
1320 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE3 (3UL)
1321 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE4 (4UL)
1322 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE5 (5UL)
1323 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE6 (6UL)
1324 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE7 (7UL)
1325 
1326 /* CPU register group index macro definition */
1327 #define SYSCTL_CPU_CPU0 (0UL)
1328 #define SYSCTL_CPU_CPU1 (1UL)
1329 
1330 
1331 #endif /* HPM_SYSCTL_H */
SYSCTL_Type
Definition: hpm_sysctl_regs.h:12