HPM SDK
HPMicro Software Development Kit
hpm_bcfg_regs.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_BCFG_H
10 #define HPM_BCFG_H
11 
12 typedef struct {
13  __RW uint32_t VBG_CFG; /* 0x0: Bandgap config */
14  __R uint8_t RESERVED0[4]; /* 0x4 - 0x7: Reserved */
15  __RW uint32_t IRC32K_CFG; /* 0x8: On-chip 32k oscillator config */
16  __RW uint32_t XTAL32K_CFG; /* 0xC: XTAL 32K config */
17  __RW uint32_t CLK_CFG; /* 0x10: Clock config */
18 } BCFG_Type;
19 
20 
21 /* Bitfield definition for register: VBG_CFG */
22 /*
23  * VBG_TRIMMED (RW)
24  *
25  * Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value
26  * 0: bandgap is not trimmed
27  * 1: bandgap is trimmed
28  */
29 #define BCFG_VBG_CFG_VBG_TRIMMED_MASK (0x80000000UL)
30 #define BCFG_VBG_CFG_VBG_TRIMMED_SHIFT (31U)
31 #define BCFG_VBG_CFG_VBG_TRIMMED_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_TRIMMED_SHIFT) & BCFG_VBG_CFG_VBG_TRIMMED_MASK)
32 #define BCFG_VBG_CFG_VBG_TRIMMED_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_TRIMMED_MASK) >> BCFG_VBG_CFG_VBG_TRIMMED_SHIFT)
33 
34 /*
35  * POWER_SAVE (RW)
36  *
37  * Bandgap works in power save mode
38  * 0: not in power save mode
39  * 1: bandgap work in power save mode
40  */
41 #define BCFG_VBG_CFG_POWER_SAVE_MASK (0x1000000UL)
42 #define BCFG_VBG_CFG_POWER_SAVE_SHIFT (24U)
43 #define BCFG_VBG_CFG_POWER_SAVE_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_POWER_SAVE_SHIFT) & BCFG_VBG_CFG_POWER_SAVE_MASK)
44 #define BCFG_VBG_CFG_POWER_SAVE_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_POWER_SAVE_MASK) >> BCFG_VBG_CFG_POWER_SAVE_SHIFT)
45 
46 /*
47  * VBG_1P0 (RW)
48  *
49  * Bandgap 1.0V output trim
50  */
51 #define BCFG_VBG_CFG_VBG_1P0_MASK (0x1F0000UL)
52 #define BCFG_VBG_CFG_VBG_1P0_SHIFT (16U)
53 #define BCFG_VBG_CFG_VBG_1P0_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_1P0_SHIFT) & BCFG_VBG_CFG_VBG_1P0_MASK)
54 #define BCFG_VBG_CFG_VBG_1P0_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_1P0_MASK) >> BCFG_VBG_CFG_VBG_1P0_SHIFT)
55 
56 /*
57  * VBG_P65 (RW)
58  *
59  * Bandgap 0.65V output trim
60  */
61 #define BCFG_VBG_CFG_VBG_P65_MASK (0x1F00U)
62 #define BCFG_VBG_CFG_VBG_P65_SHIFT (8U)
63 #define BCFG_VBG_CFG_VBG_P65_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_P65_SHIFT) & BCFG_VBG_CFG_VBG_P65_MASK)
64 #define BCFG_VBG_CFG_VBG_P65_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_P65_MASK) >> BCFG_VBG_CFG_VBG_P65_SHIFT)
65 
66 /*
67  * VBG_P50 (RW)
68  *
69  * Bandgap 0.50V output trim
70  */
71 #define BCFG_VBG_CFG_VBG_P50_MASK (0x1FU)
72 #define BCFG_VBG_CFG_VBG_P50_SHIFT (0U)
73 #define BCFG_VBG_CFG_VBG_P50_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_P50_SHIFT) & BCFG_VBG_CFG_VBG_P50_MASK)
74 #define BCFG_VBG_CFG_VBG_P50_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_P50_MASK) >> BCFG_VBG_CFG_VBG_P50_SHIFT)
75 
76 /* Bitfield definition for register: IRC32K_CFG */
77 /*
78  * IRC_TRIMMED (RW)
79  *
80  * IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value
81  * 0: irc is not trimmed
82  * 1: irc is trimmed
83  */
84 #define BCFG_IRC32K_CFG_IRC_TRIMMED_MASK (0x80000000UL)
85 #define BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT (31U)
86 #define BCFG_IRC32K_CFG_IRC_TRIMMED_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT) & BCFG_IRC32K_CFG_IRC_TRIMMED_MASK)
87 #define BCFG_IRC32K_CFG_IRC_TRIMMED_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_IRC_TRIMMED_MASK) >> BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT)
88 
89 /*
90  * CAPEX7_TRIM (RW)
91  *
92  * IRC32K bit 7
93  */
94 #define BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK (0x800000UL)
95 #define BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT (23U)
96 #define BCFG_IRC32K_CFG_CAPEX7_TRIM_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK)
97 #define BCFG_IRC32K_CFG_CAPEX7_TRIM_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK) >> BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT)
98 
99 /*
100  * CAPEX6_TRIM (RW)
101  *
102  * IRC32K bit 6
103  */
104 #define BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK (0x400000UL)
105 #define BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT (22U)
106 #define BCFG_IRC32K_CFG_CAPEX6_TRIM_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK)
107 #define BCFG_IRC32K_CFG_CAPEX6_TRIM_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK) >> BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT)
108 
109 /*
110  * CAP_TRIM (RW)
111  *
112  * capacitor trim bits
113  */
114 #define BCFG_IRC32K_CFG_CAP_TRIM_MASK (0x1FFU)
115 #define BCFG_IRC32K_CFG_CAP_TRIM_SHIFT (0U)
116 #define BCFG_IRC32K_CFG_CAP_TRIM_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_CAP_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAP_TRIM_MASK)
117 #define BCFG_IRC32K_CFG_CAP_TRIM_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_CAP_TRIM_MASK) >> BCFG_IRC32K_CFG_CAP_TRIM_SHIFT)
118 
119 /* Bitfield definition for register: XTAL32K_CFG */
120 /*
121  * HYST_EN (RW)
122  *
123  * crystal 32k hysteres enable
124  */
125 #define BCFG_XTAL32K_CFG_HYST_EN_MASK (0x1000U)
126 #define BCFG_XTAL32K_CFG_HYST_EN_SHIFT (12U)
127 #define BCFG_XTAL32K_CFG_HYST_EN_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_HYST_EN_SHIFT) & BCFG_XTAL32K_CFG_HYST_EN_MASK)
128 #define BCFG_XTAL32K_CFG_HYST_EN_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_HYST_EN_MASK) >> BCFG_XTAL32K_CFG_HYST_EN_SHIFT)
129 
130 /*
131  * GMSEL (RW)
132  *
133  * crystal 32k gm selection
134  */
135 #define BCFG_XTAL32K_CFG_GMSEL_MASK (0x300U)
136 #define BCFG_XTAL32K_CFG_GMSEL_SHIFT (8U)
137 #define BCFG_XTAL32K_CFG_GMSEL_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_GMSEL_SHIFT) & BCFG_XTAL32K_CFG_GMSEL_MASK)
138 #define BCFG_XTAL32K_CFG_GMSEL_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_GMSEL_MASK) >> BCFG_XTAL32K_CFG_GMSEL_SHIFT)
139 
140 /*
141  * CFG (RW)
142  *
143  * crystal 32k config
144  */
145 #define BCFG_XTAL32K_CFG_CFG_MASK (0x10U)
146 #define BCFG_XTAL32K_CFG_CFG_SHIFT (4U)
147 #define BCFG_XTAL32K_CFG_CFG_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_CFG_SHIFT) & BCFG_XTAL32K_CFG_CFG_MASK)
148 #define BCFG_XTAL32K_CFG_CFG_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_CFG_MASK) >> BCFG_XTAL32K_CFG_CFG_SHIFT)
149 
150 /*
151  * AMP (RW)
152  *
153  * crystal 32k amplifier
154  */
155 #define BCFG_XTAL32K_CFG_AMP_MASK (0x3U)
156 #define BCFG_XTAL32K_CFG_AMP_SHIFT (0U)
157 #define BCFG_XTAL32K_CFG_AMP_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_AMP_SHIFT) & BCFG_XTAL32K_CFG_AMP_MASK)
158 #define BCFG_XTAL32K_CFG_AMP_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_AMP_MASK) >> BCFG_XTAL32K_CFG_AMP_SHIFT)
159 
160 /* Bitfield definition for register: CLK_CFG */
161 /*
162  * XTAL_SEL (RO)
163  *
164  * crystal selected
165  */
166 #define BCFG_CLK_CFG_XTAL_SEL_MASK (0x10000000UL)
167 #define BCFG_CLK_CFG_XTAL_SEL_SHIFT (28U)
168 #define BCFG_CLK_CFG_XTAL_SEL_GET(x) (((uint32_t)(x) & BCFG_CLK_CFG_XTAL_SEL_MASK) >> BCFG_CLK_CFG_XTAL_SEL_SHIFT)
169 
170 /*
171  * KEEP_IRC (RW)
172  *
173  * force irc32k run
174  */
175 #define BCFG_CLK_CFG_KEEP_IRC_MASK (0x10000UL)
176 #define BCFG_CLK_CFG_KEEP_IRC_SHIFT (16U)
177 #define BCFG_CLK_CFG_KEEP_IRC_SET(x) (((uint32_t)(x) << BCFG_CLK_CFG_KEEP_IRC_SHIFT) & BCFG_CLK_CFG_KEEP_IRC_MASK)
178 #define BCFG_CLK_CFG_KEEP_IRC_GET(x) (((uint32_t)(x) & BCFG_CLK_CFG_KEEP_IRC_MASK) >> BCFG_CLK_CFG_KEEP_IRC_SHIFT)
179 
180 /*
181  * FORCE_XTAL (RW)
182  *
183  * force switch to crystal
184  */
185 #define BCFG_CLK_CFG_FORCE_XTAL_MASK (0x10U)
186 #define BCFG_CLK_CFG_FORCE_XTAL_SHIFT (4U)
187 #define BCFG_CLK_CFG_FORCE_XTAL_SET(x) (((uint32_t)(x) << BCFG_CLK_CFG_FORCE_XTAL_SHIFT) & BCFG_CLK_CFG_FORCE_XTAL_MASK)
188 #define BCFG_CLK_CFG_FORCE_XTAL_GET(x) (((uint32_t)(x) & BCFG_CLK_CFG_FORCE_XTAL_MASK) >> BCFG_CLK_CFG_FORCE_XTAL_SHIFT)
189 
190 
191 
192 
193 #endif /* HPM_BCFG_H */
BCFG_Type
Definition: hpm_bcfg_regs.h:12