HPM SDK
HPMicro Software Development Kit
hpm_pwmv2_regs.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_PWMV2_H
10 #define HPM_PWMV2_H
11 
12 typedef struct {
13  __RW uint32_t WORK_CTRL0; /* 0x0: */
14  __RW uint32_t UNLOCK; /* 0x4: */
15  __RW uint32_t SHADOW_VAL[28]; /* 0x8 - 0x74: */
16  __RW uint32_t FORCE_MODE; /* 0x78: */
17  __RW uint32_t WORK_CTRL1; /* 0x7C: */
18  __R uint8_t RESERVED0[128]; /* 0x80 - 0xFF: Reserved */
19  struct {
20  __RW uint32_t CFG0; /* 0x100: */
21  __RW uint32_t CFG1; /* 0x104: */
22  __RW uint32_t DEAD_AREA; /* 0x108: */
23  __R uint8_t RESERVED0[4]; /* 0x10C - 0x10F: Reserved */
24  } PWM[8];
25  __RW uint32_t TRIGGER_CFG[8]; /* 0x180 - 0x19C: */
26  __R uint8_t RESERVED1[80]; /* 0x1A0 - 0x1EF: Reserved */
27  __RW uint32_t GLB_CTRL; /* 0x1F0: */
28  __RW uint32_t GLB_CTRL2; /* 0x1F4: */
29  __R uint8_t RESERVED2[8]; /* 0x1F8 - 0x1FF: Reserved */
30  __R uint32_t CNT_RELOAD_WORK[4]; /* 0x200 - 0x20C: */
31  __R uint32_t CMP_VAL_WORK[24]; /* 0x210 - 0x26C: */
32  __R uint8_t RESERVED3[12]; /* 0x270 - 0x27B: Reserved */
33  __R uint32_t FORCE_WORK; /* 0x27C: */
34  __R uint8_t RESERVED4[32]; /* 0x280 - 0x29F: Reserved */
35  __R uint32_t CNT_VAL[4]; /* 0x2A0 - 0x2AC: */
36  __RW uint32_t DAC_VALUE_SV[4]; /* 0x2B0 - 0x2BC: */
37  __R uint8_t RESERVED5[64]; /* 0x2C0 - 0x2FF: Reserved */
38  __RW uint32_t CAPTURE_POS[8]; /* 0x300 - 0x31C: */
39  __R uint8_t RESERVED6[96]; /* 0x320 - 0x37F: Reserved */
40  __R uint32_t CAPTURE_NEG[8]; /* 0x380 - 0x39C: */
41  __R uint8_t RESERVED7[96]; /* 0x3A0 - 0x3FF: Reserved */
42  __RW uint32_t IRQ_STS; /* 0x400: */
43  __RW uint32_t IRQ_EN; /* 0x404: */
44  __R uint8_t RESERVED8[8]; /* 0x408 - 0x40F: Reserved */
45  __W uint32_t IRQ_STS_CMP; /* 0x410: */
46  __W uint32_t IRQ_STS_RELOAD; /* 0x414: */
47  __W uint32_t IRQ_STS_CAP_POS; /* 0x418: */
48  __W uint32_t IRQ_STS_CAP_NEG; /* 0x41C: */
49  __W uint32_t IRQ_STS_FAULT; /* 0x420: */
50  __W uint32_t IRQ_STS_BURSTEND; /* 0x424: */
51  __R uint8_t RESERVED9[8]; /* 0x428 - 0x42F: Reserved */
52  __RW uint32_t IRQ_EN_CMP; /* 0x430: */
53  __RW uint32_t IRQ_EN_RELOAD; /* 0x434: */
54  __RW uint32_t IRQ_EN_CAP_POS; /* 0x438: */
55  __RW uint32_t IRQ_EN_CAP_NEG; /* 0x43C: */
56  __RW uint32_t IRQ_EN_FAULT; /* 0x440: */
57  __RW uint32_t IRQ_EN_BURSTEND; /* 0x444: */
58  __R uint8_t RESERVED10[56]; /* 0x448 - 0x47F: Reserved */
59  __RW uint32_t DMA_EN; /* 0x480: */
60  __R uint8_t RESERVED11[124]; /* 0x484 - 0x4FF: Reserved */
61  struct {
62  __RW uint32_t CFG0; /* 0x500: */
63  __RW uint32_t CFG1; /* 0x504: */
64  __RW uint32_t CFG2; /* 0x508: */
65  __RW uint32_t CFG3; /* 0x50C: */
66  } CNT[4];
67  __RW uint32_t CNT_GLBCFG; /* 0x540: */
68  __R uint8_t RESERVED12[188]; /* 0x544 - 0x5FF: Reserved */
69  struct {
70  __RW uint32_t CFG0; /* 0x600: */
71  __RW uint32_t CFG1; /* 0x604: */
72  __R uint8_t RESERVED0[8]; /* 0x608 - 0x60F: Reserved */
73  } CAL[16];
74  __R uint8_t RESERVED13[256]; /* 0x700 - 0x7FF: Reserved */
75  struct {
76  __RW uint32_t CFG; /* 0x800: */
77  __R uint8_t RESERVED0[12]; /* 0x804 - 0x80F: Reserved */
78  } CMP[24];
79 } PWMV2_Type;
80 
81 
82 /* Bitfield definition for register: WORK_CTRL0 */
83 /*
84  * SHADOW_UNLOCK (RW)
85  *
86  * write 0x… first to unlock, then set related bits in unlock_sel to unlock following shadow registers(from 0x04 to 0x78),
87  * otherwise the shadow registers can not be written.
88  * The shadow registers will be loaded to work registers only when shadow_lock is 1 or lock is not enabled
89  * This bit can be cleared by set shadow_lock bit in work_ctrl1
90  */
91 #define PWMV2_WORK_CTRL0_SHADOW_UNLOCK_MASK (0x80000000UL)
92 #define PWMV2_WORK_CTRL0_SHADOW_UNLOCK_SHIFT (31U)
93 #define PWMV2_WORK_CTRL0_SHADOW_UNLOCK_SET(x) (((uint32_t)(x) << PWMV2_WORK_CTRL0_SHADOW_UNLOCK_SHIFT) & PWMV2_WORK_CTRL0_SHADOW_UNLOCK_MASK)
94 #define PWMV2_WORK_CTRL0_SHADOW_UNLOCK_GET(x) (((uint32_t)(x) & PWMV2_WORK_CTRL0_SHADOW_UNLOCK_MASK) >> PWMV2_WORK_CTRL0_SHADOW_UNLOCK_SHIFT)
95 
96 /* Bitfield definition for register: UNLOCK */
97 /*
98  * UNLOCK_BIT (RW)
99  *
100  * bit2 to bit 29 for value_shadow, bit30 for force_mode
101  * the shadow registers can be updated only when related unlock_bit is set;
102  * this register can only be updated after unlock
103  */
104 #define PWMV2_UNLOCK_UNLOCK_BIT_MASK (0xFFFFFFFFUL)
105 #define PWMV2_UNLOCK_UNLOCK_BIT_SHIFT (0U)
106 #define PWMV2_UNLOCK_UNLOCK_BIT_SET(x) (((uint32_t)(x) << PWMV2_UNLOCK_UNLOCK_BIT_SHIFT) & PWMV2_UNLOCK_UNLOCK_BIT_MASK)
107 #define PWMV2_UNLOCK_UNLOCK_BIT_GET(x) (((uint32_t)(x) & PWMV2_UNLOCK_UNLOCK_BIT_MASK) >> PWMV2_UNLOCK_UNLOCK_BIT_SHIFT)
108 
109 /* Bitfield definition for register array: SHADOW_VAL */
110 /*
111  * VALUE (RW)
112  *
113  * shadow registers, if used as reload or compare point, shall be 24bit clock cycles plus 1bit half cycle and 7bit high-resolution delay
114  */
115 #define PWMV2_SHADOW_VAL_VALUE_MASK (0xFFFFFFFFUL)
116 #define PWMV2_SHADOW_VAL_VALUE_SHIFT (0U)
117 #define PWMV2_SHADOW_VAL_VALUE_SET(x) (((uint32_t)(x) << PWMV2_SHADOW_VAL_VALUE_SHIFT) & PWMV2_SHADOW_VAL_VALUE_MASK)
118 #define PWMV2_SHADOW_VAL_VALUE_GET(x) (((uint32_t)(x) & PWMV2_SHADOW_VAL_VALUE_MASK) >> PWMV2_SHADOW_VAL_VALUE_SHIFT)
119 
120 /* Bitfield definition for register: FORCE_MODE */
121 /*
122  * POLARITY (RW)
123  *
124  * one bit for one pwm channel, it's used as shadow register when pwm_cfg0.polarity_opt0 is set.
125  * output polarity, set to 1 will invert the output
126  */
127 #define PWMV2_FORCE_MODE_POLARITY_MASK (0xFF0000UL)
128 #define PWMV2_FORCE_MODE_POLARITY_SHIFT (16U)
129 #define PWMV2_FORCE_MODE_POLARITY_SET(x) (((uint32_t)(x) << PWMV2_FORCE_MODE_POLARITY_SHIFT) & PWMV2_FORCE_MODE_POLARITY_MASK)
130 #define PWMV2_FORCE_MODE_POLARITY_GET(x) (((uint32_t)(x) & PWMV2_FORCE_MODE_POLARITY_MASK) >> PWMV2_FORCE_MODE_POLARITY_SHIFT)
131 
132 /*
133  * FORCE_MODE (RW)
134  *
135  * 2bit for each PWM channel(0~7);
136  * 00: force output 0
137  * 01: force output 1
138  * 10: output highz(pad_oe_*=0)
139  * 11: no force
140  * this field may be changed by software as shadow register , the update time should be defined by chan_cfg.load, only for PWM channels.
141  */
142 #define PWMV2_FORCE_MODE_FORCE_MODE_MASK (0xFFFFU)
143 #define PWMV2_FORCE_MODE_FORCE_MODE_SHIFT (0U)
144 #define PWMV2_FORCE_MODE_FORCE_MODE_SET(x) (((uint32_t)(x) << PWMV2_FORCE_MODE_FORCE_MODE_SHIFT) & PWMV2_FORCE_MODE_FORCE_MODE_MASK)
145 #define PWMV2_FORCE_MODE_FORCE_MODE_GET(x) (((uint32_t)(x) & PWMV2_FORCE_MODE_FORCE_MODE_MASK) >> PWMV2_FORCE_MODE_FORCE_MODE_SHIFT)
146 
147 /* Bitfield definition for register: WORK_CTRL1 */
148 /*
149  * SHADOW_LOCK (RW)
150  *
151  * one to lock, sofware can't write any shadow registers
152  * Software have to write 0x…. to work_ctrl0 to clear this bit.
153  */
154 #define PWMV2_WORK_CTRL1_SHADOW_LOCK_MASK (0x80000000UL)
155 #define PWMV2_WORK_CTRL1_SHADOW_LOCK_SHIFT (31U)
156 #define PWMV2_WORK_CTRL1_SHADOW_LOCK_SET(x) (((uint32_t)(x) << PWMV2_WORK_CTRL1_SHADOW_LOCK_SHIFT) & PWMV2_WORK_CTRL1_SHADOW_LOCK_MASK)
157 #define PWMV2_WORK_CTRL1_SHADOW_LOCK_GET(x) (((uint32_t)(x) & PWMV2_WORK_CTRL1_SHADOW_LOCK_MASK) >> PWMV2_WORK_CTRL1_SHADOW_LOCK_SHIFT)
158 
159 /* Bitfield definition for register of struct array PWM: CFG0 */
160 /*
161  * TRIG_SEL4 (RW)
162  *
163  * for N=0/2/4/6, clear to select 2 compare point(N*2~N*2+1);
164  * set to select 4 compare point(N*2~N*2+3);
165  * or use 2 compare point(N*2+2~N*2+3);
166  * for N=1/3/5/7, this bit is no means, it can work on pair mode, or use 2 compare point (N*2+2~N*2+3);
167  * assume select ab or abcd, abcd can between 0 and 2T.
168  * output will be 1 when counter value between a and b;
169  * if b<=a then output all 0; if b>=(T+a), then output all 1;
170  */
171 #define PWMV2_PWM_CFG0_TRIG_SEL4_MASK (0x1000000UL)
172 #define PWMV2_PWM_CFG0_TRIG_SEL4_SHIFT (24U)
173 #define PWMV2_PWM_CFG0_TRIG_SEL4_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG0_TRIG_SEL4_SHIFT) & PWMV2_PWM_CFG0_TRIG_SEL4_MASK)
174 #define PWMV2_PWM_CFG0_TRIG_SEL4_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG0_TRIG_SEL4_MASK) >> PWMV2_PWM_CFG0_TRIG_SEL4_SHIFT)
175 
176 /*
177  * FAULT_SEL_ASYNC (RW)
178  *
179  * select from 16bit async fault from pad
180  */
181 #define PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_MASK (0xF00U)
182 #define PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_SHIFT (8U)
183 #define PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_SHIFT) & PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_MASK)
184 #define PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_MASK) >> PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_SHIFT)
185 
186 /*
187  * FAULT_POL_ASYNC (RW)
188  *
189  * fault polarity for input fault from pad, 1-active low; 0-active high;
190  */
191 #define PWMV2_PWM_CFG0_FAULT_POL_ASYNC_MASK (0x40U)
192 #define PWMV2_PWM_CFG0_FAULT_POL_ASYNC_SHIFT (6U)
193 #define PWMV2_PWM_CFG0_FAULT_POL_ASYNC_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG0_FAULT_POL_ASYNC_SHIFT) & PWMV2_PWM_CFG0_FAULT_POL_ASYNC_MASK)
194 #define PWMV2_PWM_CFG0_FAULT_POL_ASYNC_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG0_FAULT_POL_ASYNC_MASK) >> PWMV2_PWM_CFG0_FAULT_POL_ASYNC_SHIFT)
195 
196 /*
197  * FAULT_EN_ASYNC (RW)
198  *
199  * set to enable the input async faults from pad directly
200  */
201 #define PWMV2_PWM_CFG0_FAULT_EN_ASYNC_MASK (0x20U)
202 #define PWMV2_PWM_CFG0_FAULT_EN_ASYNC_SHIFT (5U)
203 #define PWMV2_PWM_CFG0_FAULT_EN_ASYNC_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG0_FAULT_EN_ASYNC_SHIFT) & PWMV2_PWM_CFG0_FAULT_EN_ASYNC_MASK)
204 #define PWMV2_PWM_CFG0_FAULT_EN_ASYNC_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG0_FAULT_EN_ASYNC_MASK) >> PWMV2_PWM_CFG0_FAULT_EN_ASYNC_SHIFT)
205 
206 /*
207  * FAULT_EN_SYNC (RW)
208  *
209  * set to enable the input faults from trig_mux(trigger_in[0] for channel0/1, 1 for 23, 2 for 45, 3 for 67)
210  */
211 #define PWMV2_PWM_CFG0_FAULT_EN_SYNC_MASK (0x10U)
212 #define PWMV2_PWM_CFG0_FAULT_EN_SYNC_SHIFT (4U)
213 #define PWMV2_PWM_CFG0_FAULT_EN_SYNC_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG0_FAULT_EN_SYNC_SHIFT) & PWMV2_PWM_CFG0_FAULT_EN_SYNC_MASK)
214 #define PWMV2_PWM_CFG0_FAULT_EN_SYNC_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG0_FAULT_EN_SYNC_MASK) >> PWMV2_PWM_CFG0_FAULT_EN_SYNC_SHIFT)
215 
216 /*
217  * POL_UPDATE_SEL (RW)
218  *
219  * used when polarity_opt0 is set, define when to update polarity working register.
220  * 0: software set work_ctrl1.shadow_lock bit
221  * 1: update at reload point;
222  */
223 #define PWMV2_PWM_CFG0_POL_UPDATE_SEL_MASK (0x4U)
224 #define PWMV2_PWM_CFG0_POL_UPDATE_SEL_SHIFT (2U)
225 #define PWMV2_PWM_CFG0_POL_UPDATE_SEL_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG0_POL_UPDATE_SEL_SHIFT) & PWMV2_PWM_CFG0_POL_UPDATE_SEL_MASK)
226 #define PWMV2_PWM_CFG0_POL_UPDATE_SEL_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG0_POL_UPDATE_SEL_MASK) >> PWMV2_PWM_CFG0_POL_UPDATE_SEL_SHIFT)
227 
228 /*
229  * OUT_POLARITY (RW)
230  *
231  * output polarity, set to 1 will invert the output.
232  * when polarity_opt0 is set, this bit is controlled by shadow register, can't be writable; read as working register
233  * use compare channel settings(in cmp_cfg) as shadow register update
234  */
235 #define PWMV2_PWM_CFG0_OUT_POLARITY_MASK (0x2U)
236 #define PWMV2_PWM_CFG0_OUT_POLARITY_SHIFT (1U)
237 #define PWMV2_PWM_CFG0_OUT_POLARITY_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG0_OUT_POLARITY_SHIFT) & PWMV2_PWM_CFG0_OUT_POLARITY_MASK)
238 #define PWMV2_PWM_CFG0_OUT_POLARITY_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG0_OUT_POLARITY_MASK) >> PWMV2_PWM_CFG0_OUT_POLARITY_SHIFT)
239 
240 /*
241  * POLARITY_OPT0 (RW)
242  *
243  * set to use shadow polarity
244  */
245 #define PWMV2_PWM_CFG0_POLARITY_OPT0_MASK (0x1U)
246 #define PWMV2_PWM_CFG0_POLARITY_OPT0_SHIFT (0U)
247 #define PWMV2_PWM_CFG0_POLARITY_OPT0_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG0_POLARITY_OPT0_SHIFT) & PWMV2_PWM_CFG0_POLARITY_OPT0_MASK)
248 #define PWMV2_PWM_CFG0_POLARITY_OPT0_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG0_POLARITY_OPT0_MASK) >> PWMV2_PWM_CFG0_POLARITY_OPT0_SHIFT)
249 
250 /* Bitfield definition for register of struct array PWM: CFG1 */
251 /*
252  * HIGHZ_EN_N (RW)
253  *
254  * 0 to highz pwm outputs(pad_oe*=0), software need set this bit to 1 to enable pwm output
255  */
256 #define PWMV2_PWM_CFG1_HIGHZ_EN_N_MASK (0x10000000UL)
257 #define PWMV2_PWM_CFG1_HIGHZ_EN_N_SHIFT (28U)
258 #define PWMV2_PWM_CFG1_HIGHZ_EN_N_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG1_HIGHZ_EN_N_SHIFT) & PWMV2_PWM_CFG1_HIGHZ_EN_N_MASK)
259 #define PWMV2_PWM_CFG1_HIGHZ_EN_N_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG1_HIGHZ_EN_N_MASK) >> PWMV2_PWM_CFG1_HIGHZ_EN_N_SHIFT)
260 
261 /*
262  * FORCE_UPDATE_TIME (RW)
263  *
264  * define when to use the shadow register value for working register(force_mode)
265  * 00: software set work_ctrl1.shadow_lock bit
266  * 01: use the related counter rld_cmp_sel0 and rld_cmp_sel1, to select one compare point
267  * 10: related counter reload time(selected by pwm_cnt)
268  * 11: use force_trig_sel to select one of the input trigger
269  * NOTE: 00/01 are not recommended since the update time is not controllable, may cause error in complex application.
270  * 00 is used for initialization or debug, not suggest for real time update
271  */
272 #define PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_MASK (0xC000000UL)
273 #define PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_SHIFT (26U)
274 #define PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_SHIFT) & PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_MASK)
275 #define PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_MASK) >> PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_SHIFT)
276 
277 /*
278  * FAULT_MODE (RW)
279  *
280  * 00: force output 0
281  * 01: force output 1
282  * 1x: output highz(pad_oe_*=0)
283  */
284 #define PWMV2_PWM_CFG1_FAULT_MODE_MASK (0x3000000UL)
285 #define PWMV2_PWM_CFG1_FAULT_MODE_SHIFT (24U)
286 #define PWMV2_PWM_CFG1_FAULT_MODE_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG1_FAULT_MODE_SHIFT) & PWMV2_PWM_CFG1_FAULT_MODE_MASK)
287 #define PWMV2_PWM_CFG1_FAULT_MODE_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG1_FAULT_MODE_MASK) >> PWMV2_PWM_CFG1_FAULT_MODE_SHIFT)
288 
289 /*
290  * FAULT_REC_TIME (RW)
291  *
292  * 00: immediately
293  * 01: after main counter reload time
294  * 10: use fault_rec_sel to select one of the input trigger
295  * 11: software write fault_clear in glb_ctrl2, no effort if pwm_fault is still assert
296  */
297 #define PWMV2_PWM_CFG1_FAULT_REC_TIME_MASK (0xC00000UL)
298 #define PWMV2_PWM_CFG1_FAULT_REC_TIME_SHIFT (22U)
299 #define PWMV2_PWM_CFG1_FAULT_REC_TIME_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG1_FAULT_REC_TIME_SHIFT) & PWMV2_PWM_CFG1_FAULT_REC_TIME_MASK)
300 #define PWMV2_PWM_CFG1_FAULT_REC_TIME_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG1_FAULT_REC_TIME_MASK) >> PWMV2_PWM_CFG1_FAULT_REC_TIME_SHIFT)
301 
302 /*
303  * SW_FORCE_EN (RW)
304  *
305  * 0 for hardware force, from trig_mux selected by pwm_force_sel
306  * 1 for software force, from glb_ctrl.sw_force
307  */
308 #define PWMV2_PWM_CFG1_SW_FORCE_EN_MASK (0x200000UL)
309 #define PWMV2_PWM_CFG1_SW_FORCE_EN_SHIFT (21U)
310 #define PWMV2_PWM_CFG1_SW_FORCE_EN_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG1_SW_FORCE_EN_SHIFT) & PWMV2_PWM_CFG1_SW_FORCE_EN_MASK)
311 #define PWMV2_PWM_CFG1_SW_FORCE_EN_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG1_SW_FORCE_EN_MASK) >> PWMV2_PWM_CFG1_SW_FORCE_EN_SHIFT)
312 
313 /*
314  * PAIR_MODE (RW)
315  *
316  * if set to 1, PWM work at pair mode,
317  * pwm_cfg for channel 2m is used for channel 2m+1(m=0,1,2,3),
318  * except the dead area, which is separate for each channel even in pair mode
319  * software need set this bit for both channel of one pair, otherwise result unknown.
320  */
321 #define PWMV2_PWM_CFG1_PAIR_MODE_MASK (0x100000UL)
322 #define PWMV2_PWM_CFG1_PAIR_MODE_SHIFT (20U)
323 #define PWMV2_PWM_CFG1_PAIR_MODE_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG1_PAIR_MODE_SHIFT) & PWMV2_PWM_CFG1_PAIR_MODE_MASK)
324 #define PWMV2_PWM_CFG1_PAIR_MODE_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG1_PAIR_MODE_MASK) >> PWMV2_PWM_CFG1_PAIR_MODE_SHIFT)
325 
326 /*
327  * PWM_LOGIC (RW)
328  *
329  * valid only for pwm0/2/4/6 when trig_sel4 is set
330  * 00: ab OR cd;
331  * 01: ab AND cd;
332  * 10: ab XOR cd;
333  * 11: cd
334  */
335 #define PWMV2_PWM_CFG1_PWM_LOGIC_MASK (0xC0000UL)
336 #define PWMV2_PWM_CFG1_PWM_LOGIC_SHIFT (18U)
337 #define PWMV2_PWM_CFG1_PWM_LOGIC_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG1_PWM_LOGIC_SHIFT) & PWMV2_PWM_CFG1_PWM_LOGIC_MASK)
338 #define PWMV2_PWM_CFG1_PWM_LOGIC_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG1_PWM_LOGIC_MASK) >> PWMV2_PWM_CFG1_PWM_LOGIC_SHIFT)
339 
340 /*
341  * FORCE_TIME (RW)
342  *
343  * 00: force immediately
344  * 01: force at main counter reload time
345  * 10: force at trig signal selected by force_act_sel
346  * 11: no force
347  * the force assert/deassert will happen at the force_time;
348  * qeo force and value also latched at this time
349  */
350 #define PWMV2_PWM_CFG1_FORCE_TIME_MASK (0x30000UL)
351 #define PWMV2_PWM_CFG1_FORCE_TIME_SHIFT (16U)
352 #define PWMV2_PWM_CFG1_FORCE_TIME_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG1_FORCE_TIME_SHIFT) & PWMV2_PWM_CFG1_FORCE_TIME_MASK)
353 #define PWMV2_PWM_CFG1_FORCE_TIME_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG1_FORCE_TIME_MASK) >> PWMV2_PWM_CFG1_FORCE_TIME_SHIFT)
354 
355 /*
356  * FORCE_TRIG_SEL (RW)
357  *
358  * select one trigger from 8, should set to pulse in trig_mux, will load shadow register(force)mode) to force_mode_work at this time
359  */
360 #define PWMV2_PWM_CFG1_FORCE_TRIG_SEL_MASK (0x7000U)
361 #define PWMV2_PWM_CFG1_FORCE_TRIG_SEL_SHIFT (12U)
362 #define PWMV2_PWM_CFG1_FORCE_TRIG_SEL_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG1_FORCE_TRIG_SEL_SHIFT) & PWMV2_PWM_CFG1_FORCE_TRIG_SEL_MASK)
363 #define PWMV2_PWM_CFG1_FORCE_TRIG_SEL_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG1_FORCE_TRIG_SEL_MASK) >> PWMV2_PWM_CFG1_FORCE_TRIG_SEL_SHIFT)
364 
365 /*
366  * FORCE_ACT_SEL (RW)
367  *
368  * select one trigger from 8, should set to pulse in trig_mux, will load hw/sw force at this time
369  */
370 #define PWMV2_PWM_CFG1_FORCE_ACT_SEL_MASK (0x700U)
371 #define PWMV2_PWM_CFG1_FORCE_ACT_SEL_SHIFT (8U)
372 #define PWMV2_PWM_CFG1_FORCE_ACT_SEL_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG1_FORCE_ACT_SEL_SHIFT) & PWMV2_PWM_CFG1_FORCE_ACT_SEL_MASK)
373 #define PWMV2_PWM_CFG1_FORCE_ACT_SEL_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG1_FORCE_ACT_SEL_MASK) >> PWMV2_PWM_CFG1_FORCE_ACT_SEL_SHIFT)
374 
375 /*
376  * PWM_FORCE_SEL (RW)
377  *
378  * select one trigger from 8 as force signal, should be level signal, 1 for force active, 0 for no force
379  */
380 #define PWMV2_PWM_CFG1_PWM_FORCE_SEL_MASK (0x70U)
381 #define PWMV2_PWM_CFG1_PWM_FORCE_SEL_SHIFT (4U)
382 #define PWMV2_PWM_CFG1_PWM_FORCE_SEL_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG1_PWM_FORCE_SEL_SHIFT) & PWMV2_PWM_CFG1_PWM_FORCE_SEL_MASK)
383 #define PWMV2_PWM_CFG1_PWM_FORCE_SEL_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG1_PWM_FORCE_SEL_MASK) >> PWMV2_PWM_CFG1_PWM_FORCE_SEL_SHIFT)
384 
385 /*
386  * FAULT_REC_SEL (RW)
387  *
388  * select one trigger from 8, should set to pulse in trig_mux, used for fault recovery if fault_rec_time is set to 2'b10
389  */
390 #define PWMV2_PWM_CFG1_FAULT_REC_SEL_MASK (0x7U)
391 #define PWMV2_PWM_CFG1_FAULT_REC_SEL_SHIFT (0U)
392 #define PWMV2_PWM_CFG1_FAULT_REC_SEL_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG1_FAULT_REC_SEL_SHIFT) & PWMV2_PWM_CFG1_FAULT_REC_SEL_MASK)
393 #define PWMV2_PWM_CFG1_FAULT_REC_SEL_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG1_FAULT_REC_SEL_MASK) >> PWMV2_PWM_CFG1_FAULT_REC_SEL_SHIFT)
394 
395 /* Bitfield definition for register of struct array PWM: DEAD_AREA */
396 /*
397  * DEAD_AREA (RW)
398  *
399  * 16bit cycle delay plus 8bit hr_delay
400  * min value is 2 cycles, less than 0x200 will be treated as no dead area;
401  * NOTE: dead insertion must be configured with pair, that is, for pwm 01/23/45/67.
402  * otherwise the result maybe UNKNOWN!!!
403  */
404 #define PWMV2_PWM_DEAD_AREA_DEAD_AREA_MASK (0xFFFFFFUL)
405 #define PWMV2_PWM_DEAD_AREA_DEAD_AREA_SHIFT (0U)
406 #define PWMV2_PWM_DEAD_AREA_DEAD_AREA_SET(x) (((uint32_t)(x) << PWMV2_PWM_DEAD_AREA_DEAD_AREA_SHIFT) & PWMV2_PWM_DEAD_AREA_DEAD_AREA_MASK)
407 #define PWMV2_PWM_DEAD_AREA_DEAD_AREA_GET(x) (((uint32_t)(x) & PWMV2_PWM_DEAD_AREA_DEAD_AREA_MASK) >> PWMV2_PWM_DEAD_AREA_DEAD_AREA_SHIFT)
408 
409 /* Bitfield definition for register array: TRIGGER_CFG */
410 /*
411  * TRIGGER_OUT_SEL (RW)
412  *
413  * select one from 24 compare result as trigger out, set at compare point, clear at reload point.
414  */
415 #define PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_MASK (0x1FU)
416 #define PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_SHIFT (0U)
417 #define PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_SET(x) (((uint32_t)(x) << PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_SHIFT) & PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_MASK)
418 #define PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_GET(x) (((uint32_t)(x) & PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_MASK) >> PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_SHIFT)
419 
420 /* Bitfield definition for register: GLB_CTRL */
421 /*
422  * SW_FORCE (RW)
423  *
424  * software write 1 to start software force, if the pwm_cfg<n>.sw_force_en is set, force will take effort
425  */
426 #define PWMV2_GLB_CTRL_SW_FORCE_MASK (0xFF0000UL)
427 #define PWMV2_GLB_CTRL_SW_FORCE_SHIFT (16U)
428 #define PWMV2_GLB_CTRL_SW_FORCE_SET(x) (((uint32_t)(x) << PWMV2_GLB_CTRL_SW_FORCE_SHIFT) & PWMV2_GLB_CTRL_SW_FORCE_MASK)
429 #define PWMV2_GLB_CTRL_SW_FORCE_GET(x) (((uint32_t)(x) & PWMV2_GLB_CTRL_SW_FORCE_MASK) >> PWMV2_GLB_CTRL_SW_FORCE_SHIFT)
430 
431 /*
432  * OUTPUT_DELAY (RW)
433  *
434  * add delay after dead_area insertiong logic, for hr_pwm
435  */
436 #define PWMV2_GLB_CTRL_OUTPUT_DELAY_MASK (0x300U)
437 #define PWMV2_GLB_CTRL_OUTPUT_DELAY_SHIFT (8U)
438 #define PWMV2_GLB_CTRL_OUTPUT_DELAY_SET(x) (((uint32_t)(x) << PWMV2_GLB_CTRL_OUTPUT_DELAY_SHIFT) & PWMV2_GLB_CTRL_OUTPUT_DELAY_MASK)
439 #define PWMV2_GLB_CTRL_OUTPUT_DELAY_GET(x) (((uint32_t)(x) & PWMV2_GLB_CTRL_OUTPUT_DELAY_MASK) >> PWMV2_GLB_CTRL_OUTPUT_DELAY_SHIFT)
440 
441 /*
442  * HR_PWM_EN (RW)
443  *
444  * set to enable hr pwm, clear to bypass delay chain.
445  */
446 #define PWMV2_GLB_CTRL_HR_PWM_EN_MASK (0x10U)
447 #define PWMV2_GLB_CTRL_HR_PWM_EN_SHIFT (4U)
448 #define PWMV2_GLB_CTRL_HR_PWM_EN_SET(x) (((uint32_t)(x) << PWMV2_GLB_CTRL_HR_PWM_EN_SHIFT) & PWMV2_GLB_CTRL_HR_PWM_EN_MASK)
449 #define PWMV2_GLB_CTRL_HR_PWM_EN_GET(x) (((uint32_t)(x) & PWMV2_GLB_CTRL_HR_PWM_EN_MASK) >> PWMV2_GLB_CTRL_HR_PWM_EN_SHIFT)
450 
451 /*
452  * FRAC_DISABLE (RW)
453  *
454  * set to disable bit[7:0] in DAC value when Calculation Unit use it.
455  */
456 #define PWMV2_GLB_CTRL_FRAC_DISABLE_MASK (0x8U)
457 #define PWMV2_GLB_CTRL_FRAC_DISABLE_SHIFT (3U)
458 #define PWMV2_GLB_CTRL_FRAC_DISABLE_SET(x) (((uint32_t)(x) << PWMV2_GLB_CTRL_FRAC_DISABLE_SHIFT) & PWMV2_GLB_CTRL_FRAC_DISABLE_MASK)
459 #define PWMV2_GLB_CTRL_FRAC_DISABLE_GET(x) (((uint32_t)(x) & PWMV2_GLB_CTRL_FRAC_DISABLE_MASK) >> PWMV2_GLB_CTRL_FRAC_DISABLE_SHIFT)
460 
461 /* Bitfield definition for register: GLB_CTRL2 */
462 /*
463  * DAC_SW_MODE (RW)
464  *
465  * set for software DAC mode, software can write dac_value*_sv directly, and dac_valid from moto system is ignored
466  */
467 #define PWMV2_GLB_CTRL2_DAC_SW_MODE_MASK (0xF000000UL)
468 #define PWMV2_GLB_CTRL2_DAC_SW_MODE_SHIFT (24U)
469 #define PWMV2_GLB_CTRL2_DAC_SW_MODE_SET(x) (((uint32_t)(x) << PWMV2_GLB_CTRL2_DAC_SW_MODE_SHIFT) & PWMV2_GLB_CTRL2_DAC_SW_MODE_MASK)
470 #define PWMV2_GLB_CTRL2_DAC_SW_MODE_GET(x) (((uint32_t)(x) & PWMV2_GLB_CTRL2_DAC_SW_MODE_MASK) >> PWMV2_GLB_CTRL2_DAC_SW_MODE_SHIFT)
471 
472 /*
473  * DEBUG_IN_EN (RW)
474  *
475  * set to enable debug_in signal as fault signal, generally disable pwm output
476  */
477 #define PWMV2_GLB_CTRL2_DEBUG_IN_EN_MASK (0x200000UL)
478 #define PWMV2_GLB_CTRL2_DEBUG_IN_EN_SHIFT (21U)
479 #define PWMV2_GLB_CTRL2_DEBUG_IN_EN_SET(x) (((uint32_t)(x) << PWMV2_GLB_CTRL2_DEBUG_IN_EN_SHIFT) & PWMV2_GLB_CTRL2_DEBUG_IN_EN_MASK)
480 #define PWMV2_GLB_CTRL2_DEBUG_IN_EN_GET(x) (((uint32_t)(x) & PWMV2_GLB_CTRL2_DEBUG_IN_EN_MASK) >> PWMV2_GLB_CTRL2_DEBUG_IN_EN_SHIFT)
481 
482 /*
483  * FAULT_CLEAR (RW)
484  *
485  * software write 1 to clear fault event if pwm_cfg.fault_rec_time is 2'b11.
486  * software need to clear it after the fault signal is de-assert and before next fault
487  * one bit for one pwm channel
488  */
489 #define PWMV2_GLB_CTRL2_FAULT_CLEAR_MASK (0xFF00U)
490 #define PWMV2_GLB_CTRL2_FAULT_CLEAR_SHIFT (8U)
491 #define PWMV2_GLB_CTRL2_FAULT_CLEAR_SET(x) (((uint32_t)(x) << PWMV2_GLB_CTRL2_FAULT_CLEAR_SHIFT) & PWMV2_GLB_CTRL2_FAULT_CLEAR_MASK)
492 #define PWMV2_GLB_CTRL2_FAULT_CLEAR_GET(x) (((uint32_t)(x) & PWMV2_GLB_CTRL2_FAULT_CLEAR_MASK) >> PWMV2_GLB_CTRL2_FAULT_CLEAR_SHIFT)
493 
494 /*
495  * SHADOW_LOCK_EN (RW)
496  *
497  * enable shadow_lock feature, if cleared, shadow_lock will be always 0
498  */
499 #define PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_MASK (0x1U)
500 #define PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_SHIFT (0U)
501 #define PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_SET(x) (((uint32_t)(x) << PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_SHIFT) & PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_MASK)
502 #define PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_GET(x) (((uint32_t)(x) & PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_MASK) >> PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_SHIFT)
503 
504 /* Bitfield definition for register array: CNT_RELOAD_WORK */
505 /*
506  * VALUE (RO)
507  *
508  * counter0 reload working register
509  */
510 #define PWMV2_CNT_RELOAD_WORK_VALUE_MASK (0xFFFFFFFFUL)
511 #define PWMV2_CNT_RELOAD_WORK_VALUE_SHIFT (0U)
512 #define PWMV2_CNT_RELOAD_WORK_VALUE_GET(x) (((uint32_t)(x) & PWMV2_CNT_RELOAD_WORK_VALUE_MASK) >> PWMV2_CNT_RELOAD_WORK_VALUE_SHIFT)
513 
514 /* Bitfield definition for register array: CMP_VAL_WORK */
515 /*
516  * VALUE (RO)
517  *
518  * compare point working register
519  */
520 #define PWMV2_CMP_VAL_WORK_VALUE_MASK (0xFFFFFFFFUL)
521 #define PWMV2_CMP_VAL_WORK_VALUE_SHIFT (0U)
522 #define PWMV2_CMP_VAL_WORK_VALUE_GET(x) (((uint32_t)(x) & PWMV2_CMP_VAL_WORK_VALUE_MASK) >> PWMV2_CMP_VAL_WORK_VALUE_SHIFT)
523 
524 /* Bitfield definition for register: FORCE_WORK */
525 /*
526  * OUT_POLARITY (RO)
527  *
528  * force working register
529  */
530 #define PWMV2_FORCE_WORK_OUT_POLARITY_MASK (0xFF0000UL)
531 #define PWMV2_FORCE_WORK_OUT_POLARITY_SHIFT (16U)
532 #define PWMV2_FORCE_WORK_OUT_POLARITY_GET(x) (((uint32_t)(x) & PWMV2_FORCE_WORK_OUT_POLARITY_MASK) >> PWMV2_FORCE_WORK_OUT_POLARITY_SHIFT)
533 
534 /*
535  * FORCE_MODE (RO)
536  *
537  * force_mode work register
538  */
539 #define PWMV2_FORCE_WORK_FORCE_MODE_MASK (0xFFFFU)
540 #define PWMV2_FORCE_WORK_FORCE_MODE_SHIFT (0U)
541 #define PWMV2_FORCE_WORK_FORCE_MODE_GET(x) (((uint32_t)(x) & PWMV2_FORCE_WORK_FORCE_MODE_MASK) >> PWMV2_FORCE_WORK_FORCE_MODE_SHIFT)
542 
543 /* Bitfield definition for register array: CNT_VAL */
544 /*
545  * VALUE (RO)
546  *
547  * main counter value
548  */
549 #define PWMV2_CNT_VAL_VALUE_MASK (0xFFFFFFFFUL)
550 #define PWMV2_CNT_VAL_VALUE_SHIFT (0U)
551 #define PWMV2_CNT_VAL_VALUE_GET(x) (((uint32_t)(x) & PWMV2_CNT_VAL_VALUE_MASK) >> PWMV2_CNT_VAL_VALUE_SHIFT)
552 
553 /* Bitfield definition for register array: DAC_VALUE_SV */
554 /*
555  * VALUE (RW)
556  *
557  * save dac0_value when dac0_valid if dac_sw_mode is 0;
558  * software write dac_value directly if dac_sw_mode is 1
559  */
560 #define PWMV2_DAC_VALUE_SV_VALUE_MASK (0xFFFFFFFFUL)
561 #define PWMV2_DAC_VALUE_SV_VALUE_SHIFT (0U)
562 #define PWMV2_DAC_VALUE_SV_VALUE_SET(x) (((uint32_t)(x) << PWMV2_DAC_VALUE_SV_VALUE_SHIFT) & PWMV2_DAC_VALUE_SV_VALUE_MASK)
563 #define PWMV2_DAC_VALUE_SV_VALUE_GET(x) (((uint32_t)(x) & PWMV2_DAC_VALUE_SV_VALUE_MASK) >> PWMV2_DAC_VALUE_SV_VALUE_SHIFT)
564 
565 /* Bitfield definition for register array: CAPTURE_POS */
566 /*
567  * CAPTURE_POS (RO)
568  *
569  * related counter value captured at input negedge
570  */
571 #define PWMV2_CAPTURE_POS_CAPTURE_POS_MASK (0xFFFFFF00UL)
572 #define PWMV2_CAPTURE_POS_CAPTURE_POS_SHIFT (8U)
573 #define PWMV2_CAPTURE_POS_CAPTURE_POS_GET(x) (((uint32_t)(x) & PWMV2_CAPTURE_POS_CAPTURE_POS_MASK) >> PWMV2_CAPTURE_POS_CAPTURE_POS_SHIFT)
574 
575 /*
576  * CAPTURE_SELGPIO (RW)
577  *
578  * 0: result from CAP[ 7:0], from trgm
579  * 1: result from CAP[15:8], from gpio
580  */
581 #define PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_MASK (0x10U)
582 #define PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_SHIFT (4U)
583 #define PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_SET(x) (((uint32_t)(x) << PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_SHIFT) & PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_MASK)
584 #define PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_GET(x) (((uint32_t)(x) & PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_MASK) >> PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_SHIFT)
585 
586 /*
587  * CNT_INDEX (RW)
588  *
589  * related counter
590  */
591 #define PWMV2_CAPTURE_POS_CNT_INDEX_MASK (0x3U)
592 #define PWMV2_CAPTURE_POS_CNT_INDEX_SHIFT (0U)
593 #define PWMV2_CAPTURE_POS_CNT_INDEX_SET(x) (((uint32_t)(x) << PWMV2_CAPTURE_POS_CNT_INDEX_SHIFT) & PWMV2_CAPTURE_POS_CNT_INDEX_MASK)
594 #define PWMV2_CAPTURE_POS_CNT_INDEX_GET(x) (((uint32_t)(x) & PWMV2_CAPTURE_POS_CNT_INDEX_MASK) >> PWMV2_CAPTURE_POS_CNT_INDEX_SHIFT)
595 
596 /* Bitfield definition for register array: CAPTURE_NEG */
597 /*
598  * CAPTURE_NEG (RO)
599  *
600  * counter value captured at input negedge
601  */
602 #define PWMV2_CAPTURE_NEG_CAPTURE_NEG_MASK (0xFFFFFF00UL)
603 #define PWMV2_CAPTURE_NEG_CAPTURE_NEG_SHIFT (8U)
604 #define PWMV2_CAPTURE_NEG_CAPTURE_NEG_GET(x) (((uint32_t)(x) & PWMV2_CAPTURE_NEG_CAPTURE_NEG_MASK) >> PWMV2_CAPTURE_NEG_CAPTURE_NEG_SHIFT)
605 
606 /* Bitfield definition for register: IRQ_STS */
607 /*
608  * IRQ_CAL_OVERFLOW (W1C)
609  *
610  * end of output burst
611  */
612 #define PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_MASK (0x80000000UL)
613 #define PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_SHIFT (31U)
614 #define PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_SET(x) (((uint32_t)(x) << PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_SHIFT) & PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_MASK)
615 #define PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_GET(x) (((uint32_t)(x) & PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_MASK) >> PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_SHIFT)
616 
617 /*
618  * IRQ_BURSTEND (RO)
619  *
620  * end of output burst
621  */
622 #define PWMV2_IRQ_STS_IRQ_BURSTEND_MASK (0x20U)
623 #define PWMV2_IRQ_STS_IRQ_BURSTEND_SHIFT (5U)
624 #define PWMV2_IRQ_STS_IRQ_BURSTEND_GET(x) (((uint32_t)(x) & PWMV2_IRQ_STS_IRQ_BURSTEND_MASK) >> PWMV2_IRQ_STS_IRQ_BURSTEND_SHIFT)
625 
626 /*
627  * IRQ_FAULT (RO)
628  *
629  * for external fault event
630  */
631 #define PWMV2_IRQ_STS_IRQ_FAULT_MASK (0x10U)
632 #define PWMV2_IRQ_STS_IRQ_FAULT_SHIFT (4U)
633 #define PWMV2_IRQ_STS_IRQ_FAULT_GET(x) (((uint32_t)(x) & PWMV2_IRQ_STS_IRQ_FAULT_MASK) >> PWMV2_IRQ_STS_IRQ_FAULT_SHIFT)
634 
635 /*
636  * IRQ_CAPTURE_NEG (RO)
637  *
638  * capture negedge status
639  */
640 #define PWMV2_IRQ_STS_IRQ_CAPTURE_NEG_MASK (0x8U)
641 #define PWMV2_IRQ_STS_IRQ_CAPTURE_NEG_SHIFT (3U)
642 #define PWMV2_IRQ_STS_IRQ_CAPTURE_NEG_GET(x) (((uint32_t)(x) & PWMV2_IRQ_STS_IRQ_CAPTURE_NEG_MASK) >> PWMV2_IRQ_STS_IRQ_CAPTURE_NEG_SHIFT)
643 
644 /*
645  * IRQ_CAPTURE_POS (RO)
646  *
647  * capture posedge status
648  */
649 #define PWMV2_IRQ_STS_IRQ_CAPTURE_POS_MASK (0x4U)
650 #define PWMV2_IRQ_STS_IRQ_CAPTURE_POS_SHIFT (2U)
651 #define PWMV2_IRQ_STS_IRQ_CAPTURE_POS_GET(x) (((uint32_t)(x) & PWMV2_IRQ_STS_IRQ_CAPTURE_POS_MASK) >> PWMV2_IRQ_STS_IRQ_CAPTURE_POS_SHIFT)
652 
653 /*
654  * IRQ_RELOAD (RO)
655  *
656  * when clock counter reach the reload time
657  */
658 #define PWMV2_IRQ_STS_IRQ_RELOAD_MASK (0x2U)
659 #define PWMV2_IRQ_STS_IRQ_RELOAD_SHIFT (1U)
660 #define PWMV2_IRQ_STS_IRQ_RELOAD_GET(x) (((uint32_t)(x) & PWMV2_IRQ_STS_IRQ_RELOAD_MASK) >> PWMV2_IRQ_STS_IRQ_RELOAD_SHIFT)
661 
662 /*
663  * IRQ_CMP (RO)
664  *
665  * for 24 channel, compare event
666  */
667 #define PWMV2_IRQ_STS_IRQ_CMP_MASK (0x1U)
668 #define PWMV2_IRQ_STS_IRQ_CMP_SHIFT (0U)
669 #define PWMV2_IRQ_STS_IRQ_CMP_GET(x) (((uint32_t)(x) & PWMV2_IRQ_STS_IRQ_CMP_MASK) >> PWMV2_IRQ_STS_IRQ_CMP_SHIFT)
670 
671 /* Bitfield definition for register: IRQ_EN */
672 /*
673  * IRQ_EN_OVERFLOW (RW)
674  *
675  * enable interrupt when calculation unit overflow
676  */
677 #define PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_MASK (0x80000000UL)
678 #define PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_SHIFT (31U)
679 #define PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_SET(x) (((uint32_t)(x) << PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_SHIFT) & PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_MASK)
680 #define PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_GET(x) (((uint32_t)(x) & PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_MASK) >> PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_SHIFT)
681 
682 /* Bitfield definition for register: IRQ_STS_CMP */
683 /*
684  * IRQ_STS_CMP (W1C)
685  *
686  * interrupt flag for compare point match event, and each bit means one compare point.
687  */
688 #define PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_MASK (0xFFFFFFUL)
689 #define PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_SHIFT (0U)
690 #define PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_SET(x) (((uint32_t)(x) << PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_SHIFT) & PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_MASK)
691 #define PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_GET(x) (((uint32_t)(x) & PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_MASK) >> PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_SHIFT)
692 
693 /* Bitfield definition for register: IRQ_STS_RELOAD */
694 /*
695  * IRQ_STS_RELOAD (W1C)
696  *
697  * interrupt flag for reload event , and each bit means one main counter.
698  */
699 #define PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_MASK (0xFU)
700 #define PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_SHIFT (0U)
701 #define PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_SET(x) (((uint32_t)(x) << PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_SHIFT) & PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_MASK)
702 #define PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_GET(x) (((uint32_t)(x) & PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_MASK) >> PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_SHIFT)
703 
704 /* Bitfield definition for register: IRQ_STS_CAP_POS */
705 /*
706  * IRQ_STS_CAP_POS (W1C)
707  *
708  * interrupt flag for posedge capture event , and each bit means one capture channel.
709  */
710 #define PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_MASK (0xFFU)
711 #define PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_SHIFT (0U)
712 #define PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_SET(x) (((uint32_t)(x) << PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_SHIFT) & PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_MASK)
713 #define PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_GET(x) (((uint32_t)(x) & PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_MASK) >> PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_SHIFT)
714 
715 /* Bitfield definition for register: IRQ_STS_CAP_NEG */
716 /*
717  * IRQ_STS_CAP_NEG (W1C)
718  *
719  * interrupt flag for negedge capture event , and each bit means one capture channel.
720  */
721 #define PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_MASK (0xFFU)
722 #define PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_SHIFT (0U)
723 #define PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_SET(x) (((uint32_t)(x) << PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_SHIFT) & PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_MASK)
724 #define PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_GET(x) (((uint32_t)(x) & PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_MASK) >> PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_SHIFT)
725 
726 /* Bitfield definition for register: IRQ_STS_FAULT */
727 /*
728  * IRQ_STS_FAULT (W1C)
729  *
730  * interrupt flag for external fault event , and each bit means one external fault channel.
731  */
732 #define PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_MASK (0xFFU)
733 #define PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_SHIFT (0U)
734 #define PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_SET(x) (((uint32_t)(x) << PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_SHIFT) & PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_MASK)
735 #define PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_GET(x) (((uint32_t)(x) & PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_MASK) >> PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_SHIFT)
736 
737 /* Bitfield definition for register: IRQ_STS_BURSTEND */
738 /*
739  * IRQ_STS_BURSTEND (W1C)
740  *
741  * interrupt flag for output burst done event , and each bit means one main counter.
742  */
743 #define PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_MASK (0xFU)
744 #define PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_SHIFT (0U)
745 #define PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_SET(x) (((uint32_t)(x) << PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_SHIFT) & PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_MASK)
746 #define PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_GET(x) (((uint32_t)(x) & PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_MASK) >> PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_SHIFT)
747 
748 /* Bitfield definition for register: IRQ_EN_CMP */
749 /*
750  * IRQ_EN_CMP (RW)
751  *
752  * interrupt enable field for compare point match event, and each bit means one compare point.
753  */
754 #define PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_MASK (0xFFFFFFUL)
755 #define PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_SHIFT (0U)
756 #define PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_SET(x) (((uint32_t)(x) << PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_SHIFT) & PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_MASK)
757 #define PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_GET(x) (((uint32_t)(x) & PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_MASK) >> PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_SHIFT)
758 
759 /* Bitfield definition for register: IRQ_EN_RELOAD */
760 /*
761  * IRQ_EN_RELOAD (RW)
762  *
763  * interrupt enable field for reload event , and each bit means one main counter.
764  */
765 #define PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_MASK (0xFU)
766 #define PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_SHIFT (0U)
767 #define PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_SET(x) (((uint32_t)(x) << PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_SHIFT) & PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_MASK)
768 #define PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_GET(x) (((uint32_t)(x) & PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_MASK) >> PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_SHIFT)
769 
770 /* Bitfield definition for register: IRQ_EN_CAP_POS */
771 /*
772  * IRQ_EN_CAP_POS (RW)
773  *
774  * interrupt enable field for posedge capture event , and each bit means one capture channel.
775  */
776 #define PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_MASK (0xFFU)
777 #define PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_SHIFT (0U)
778 #define PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_SET(x) (((uint32_t)(x) << PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_SHIFT) & PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_MASK)
779 #define PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_GET(x) (((uint32_t)(x) & PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_MASK) >> PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_SHIFT)
780 
781 /* Bitfield definition for register: IRQ_EN_CAP_NEG */
782 /*
783  * IRQ_EN_CAP_NEG (RW)
784  *
785  * interrupt enable field for negedge capture event , and each bit means one capture channel.
786  */
787 #define PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_MASK (0xFFU)
788 #define PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_SHIFT (0U)
789 #define PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_SET(x) (((uint32_t)(x) << PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_SHIFT) & PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_MASK)
790 #define PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_GET(x) (((uint32_t)(x) & PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_MASK) >> PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_SHIFT)
791 
792 /* Bitfield definition for register: IRQ_EN_FAULT */
793 /*
794  * IRQ_EN_FAULT (RW)
795  *
796  * interrupt enable field for external fault event , and each bit means one external fault channel.
797  */
798 #define PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_MASK (0xFFU)
799 #define PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_SHIFT (0U)
800 #define PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_SET(x) (((uint32_t)(x) << PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_SHIFT) & PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_MASK)
801 #define PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_GET(x) (((uint32_t)(x) & PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_MASK) >> PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_SHIFT)
802 
803 /* Bitfield definition for register: IRQ_EN_BURSTEND */
804 /*
805  * IRQ_EN_BURSTEND (RW)
806  *
807  * interrupt enable field for output burst done event , and each bit means one main counter.
808  */
809 #define PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_MASK (0xFU)
810 #define PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_SHIFT (0U)
811 #define PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_SET(x) (((uint32_t)(x) << PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_SHIFT) & PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_MASK)
812 #define PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_GET(x) (((uint32_t)(x) & PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_MASK) >> PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_SHIFT)
813 
814 /* Bitfield definition for register: DMA_EN */
815 /*
816  * DMA3_EN (RW)
817  *
818  * enable dma3
819  */
820 #define PWMV2_DMA_EN_DMA3_EN_MASK (0x80000000UL)
821 #define PWMV2_DMA_EN_DMA3_EN_SHIFT (31U)
822 #define PWMV2_DMA_EN_DMA3_EN_SET(x) (((uint32_t)(x) << PWMV2_DMA_EN_DMA3_EN_SHIFT) & PWMV2_DMA_EN_DMA3_EN_MASK)
823 #define PWMV2_DMA_EN_DMA3_EN_GET(x) (((uint32_t)(x) & PWMV2_DMA_EN_DMA3_EN_MASK) >> PWMV2_DMA_EN_DMA3_EN_SHIFT)
824 
825 /*
826  * DMA3_SEL (RW)
827  *
828  * selelct one of compare point(0~23) or one reload point(24~27) as dma0
829  */
830 #define PWMV2_DMA_EN_DMA3_SEL_MASK (0x1F000000UL)
831 #define PWMV2_DMA_EN_DMA3_SEL_SHIFT (24U)
832 #define PWMV2_DMA_EN_DMA3_SEL_SET(x) (((uint32_t)(x) << PWMV2_DMA_EN_DMA3_SEL_SHIFT) & PWMV2_DMA_EN_DMA3_SEL_MASK)
833 #define PWMV2_DMA_EN_DMA3_SEL_GET(x) (((uint32_t)(x) & PWMV2_DMA_EN_DMA3_SEL_MASK) >> PWMV2_DMA_EN_DMA3_SEL_SHIFT)
834 
835 /*
836  * DMA2_EN (RW)
837  *
838  * enable dma2
839  */
840 #define PWMV2_DMA_EN_DMA2_EN_MASK (0x800000UL)
841 #define PWMV2_DMA_EN_DMA2_EN_SHIFT (23U)
842 #define PWMV2_DMA_EN_DMA2_EN_SET(x) (((uint32_t)(x) << PWMV2_DMA_EN_DMA2_EN_SHIFT) & PWMV2_DMA_EN_DMA2_EN_MASK)
843 #define PWMV2_DMA_EN_DMA2_EN_GET(x) (((uint32_t)(x) & PWMV2_DMA_EN_DMA2_EN_MASK) >> PWMV2_DMA_EN_DMA2_EN_SHIFT)
844 
845 /*
846  * DMA2_SEL (RW)
847  *
848  * selelct one of compare point(0~23) or one reload point(24~27) as dma0
849  */
850 #define PWMV2_DMA_EN_DMA2_SEL_MASK (0x1F0000UL)
851 #define PWMV2_DMA_EN_DMA2_SEL_SHIFT (16U)
852 #define PWMV2_DMA_EN_DMA2_SEL_SET(x) (((uint32_t)(x) << PWMV2_DMA_EN_DMA2_SEL_SHIFT) & PWMV2_DMA_EN_DMA2_SEL_MASK)
853 #define PWMV2_DMA_EN_DMA2_SEL_GET(x) (((uint32_t)(x) & PWMV2_DMA_EN_DMA2_SEL_MASK) >> PWMV2_DMA_EN_DMA2_SEL_SHIFT)
854 
855 /*
856  * DMA1_EN (RW)
857  *
858  * enable dma1
859  */
860 #define PWMV2_DMA_EN_DMA1_EN_MASK (0x8000U)
861 #define PWMV2_DMA_EN_DMA1_EN_SHIFT (15U)
862 #define PWMV2_DMA_EN_DMA1_EN_SET(x) (((uint32_t)(x) << PWMV2_DMA_EN_DMA1_EN_SHIFT) & PWMV2_DMA_EN_DMA1_EN_MASK)
863 #define PWMV2_DMA_EN_DMA1_EN_GET(x) (((uint32_t)(x) & PWMV2_DMA_EN_DMA1_EN_MASK) >> PWMV2_DMA_EN_DMA1_EN_SHIFT)
864 
865 /*
866  * DMA1_SEL (RW)
867  *
868  * selelct one of compare point(0~23) or one reload point(24~27) as dma0
869  */
870 #define PWMV2_DMA_EN_DMA1_SEL_MASK (0x1F00U)
871 #define PWMV2_DMA_EN_DMA1_SEL_SHIFT (8U)
872 #define PWMV2_DMA_EN_DMA1_SEL_SET(x) (((uint32_t)(x) << PWMV2_DMA_EN_DMA1_SEL_SHIFT) & PWMV2_DMA_EN_DMA1_SEL_MASK)
873 #define PWMV2_DMA_EN_DMA1_SEL_GET(x) (((uint32_t)(x) & PWMV2_DMA_EN_DMA1_SEL_MASK) >> PWMV2_DMA_EN_DMA1_SEL_SHIFT)
874 
875 /*
876  * DMA0_EN (RW)
877  *
878  * enable dma0
879  */
880 #define PWMV2_DMA_EN_DMA0_EN_MASK (0x80U)
881 #define PWMV2_DMA_EN_DMA0_EN_SHIFT (7U)
882 #define PWMV2_DMA_EN_DMA0_EN_SET(x) (((uint32_t)(x) << PWMV2_DMA_EN_DMA0_EN_SHIFT) & PWMV2_DMA_EN_DMA0_EN_MASK)
883 #define PWMV2_DMA_EN_DMA0_EN_GET(x) (((uint32_t)(x) & PWMV2_DMA_EN_DMA0_EN_MASK) >> PWMV2_DMA_EN_DMA0_EN_SHIFT)
884 
885 /*
886  * DMA0_SEL (RW)
887  *
888  * selelct one of compare point(0~23) or one reload point(24~27) as dma0
889  */
890 #define PWMV2_DMA_EN_DMA0_SEL_MASK (0x1FU)
891 #define PWMV2_DMA_EN_DMA0_SEL_SHIFT (0U)
892 #define PWMV2_DMA_EN_DMA0_SEL_SET(x) (((uint32_t)(x) << PWMV2_DMA_EN_DMA0_SEL_SHIFT) & PWMV2_DMA_EN_DMA0_SEL_MASK)
893 #define PWMV2_DMA_EN_DMA0_SEL_GET(x) (((uint32_t)(x) & PWMV2_DMA_EN_DMA0_SEL_MASK) >> PWMV2_DMA_EN_DMA0_SEL_SHIFT)
894 
895 /* Bitfield definition for register of struct array CNT: CFG0 */
896 /*
897  * RLD_CMP_SEL1 (RW)
898  *
899  * select one compare point from 24, set to 0x1F to disable current selection, used for reload value, compare value, force value update
900  */
901 #define PWMV2_CNT_CFG0_RLD_CMP_SEL1_MASK (0x1F000000UL)
902 #define PWMV2_CNT_CFG0_RLD_CMP_SEL1_SHIFT (24U)
903 #define PWMV2_CNT_CFG0_RLD_CMP_SEL1_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG0_RLD_CMP_SEL1_SHIFT) & PWMV2_CNT_CFG0_RLD_CMP_SEL1_MASK)
904 #define PWMV2_CNT_CFG0_RLD_CMP_SEL1_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG0_RLD_CMP_SEL1_MASK) >> PWMV2_CNT_CFG0_RLD_CMP_SEL1_SHIFT)
905 
906 /*
907  * RLD_CMP_SEL0 (RW)
908  *
909  * select one compare point from 24, set to 0x1F to disable current selection
910  */
911 #define PWMV2_CNT_CFG0_RLD_CMP_SEL0_MASK (0x1F0000UL)
912 #define PWMV2_CNT_CFG0_RLD_CMP_SEL0_SHIFT (16U)
913 #define PWMV2_CNT_CFG0_RLD_CMP_SEL0_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG0_RLD_CMP_SEL0_SHIFT) & PWMV2_CNT_CFG0_RLD_CMP_SEL0_MASK)
914 #define PWMV2_CNT_CFG0_RLD_CMP_SEL0_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG0_RLD_CMP_SEL0_MASK) >> PWMV2_CNT_CFG0_RLD_CMP_SEL0_SHIFT)
915 
916 /*
917  * RLD_TRIG_SEL (RW)
918  *
919  * select one trigger from 8, should set to pulse in trig_mux
920  */
921 #define PWMV2_CNT_CFG0_RLD_TRIG_SEL_MASK (0x7000U)
922 #define PWMV2_CNT_CFG0_RLD_TRIG_SEL_SHIFT (12U)
923 #define PWMV2_CNT_CFG0_RLD_TRIG_SEL_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG0_RLD_TRIG_SEL_SHIFT) & PWMV2_CNT_CFG0_RLD_TRIG_SEL_MASK)
924 #define PWMV2_CNT_CFG0_RLD_TRIG_SEL_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG0_RLD_TRIG_SEL_MASK) >> PWMV2_CNT_CFG0_RLD_TRIG_SEL_SHIFT)
925 
926 /*
927  * RLD_UPDATE_TIME (RW)
928  *
929  * define when to use the calculation output value as reload time
930  * 00: software set work_ctrl1.shadow_lock bit
931  * 01: use compare point selected by rld_cmp_sel0 or rld_cmp_sel1
932  * 10: counter reload time
933  * 11: use rld_trig_sel to select one of the input trigger
934  * NOTE: 00 is not recommended since the update time is not controllable, may cause error in complex application.
935  */
936 #define PWMV2_CNT_CFG0_RLD_UPDATE_TIME_MASK (0x300U)
937 #define PWMV2_CNT_CFG0_RLD_UPDATE_TIME_SHIFT (8U)
938 #define PWMV2_CNT_CFG0_RLD_UPDATE_TIME_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG0_RLD_UPDATE_TIME_SHIFT) & PWMV2_CNT_CFG0_RLD_UPDATE_TIME_MASK)
939 #define PWMV2_CNT_CFG0_RLD_UPDATE_TIME_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG0_RLD_UPDATE_TIME_MASK) >> PWMV2_CNT_CFG0_RLD_UPDATE_TIME_SHIFT)
940 
941 /*
942  * CNT_D_PARAM (RW)
943  *
944  * input dac data parameter
945  */
946 #define PWMV2_CNT_CFG0_CNT_D_PARAM_MASK (0x1FU)
947 #define PWMV2_CNT_CFG0_CNT_D_PARAM_SHIFT (0U)
948 #define PWMV2_CNT_CFG0_CNT_D_PARAM_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG0_CNT_D_PARAM_SHIFT) & PWMV2_CNT_CFG0_CNT_D_PARAM_MASK)
949 #define PWMV2_CNT_CFG0_CNT_D_PARAM_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG0_CNT_D_PARAM_MASK) >> PWMV2_CNT_CFG0_CNT_D_PARAM_SHIFT)
950 
951 /* Bitfield definition for register of struct array CNT: CFG1 */
952 /*
953  * CNT_DAC_INDEX (RW)
954  *
955  * select one of the dac value
956  */
957 #define PWMV2_CNT_CFG1_CNT_DAC_INDEX_MASK (0x3000000UL)
958 #define PWMV2_CNT_CFG1_CNT_DAC_INDEX_SHIFT (24U)
959 #define PWMV2_CNT_CFG1_CNT_DAC_INDEX_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG1_CNT_DAC_INDEX_SHIFT) & PWMV2_CNT_CFG1_CNT_DAC_INDEX_MASK)
960 #define PWMV2_CNT_CFG1_CNT_DAC_INDEX_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG1_CNT_DAC_INDEX_MASK) >> PWMV2_CNT_CFG1_CNT_DAC_INDEX_SHIFT)
961 
962 /*
963  * CNT_LU_EN (RW)
964  *
965  * set to enable up limit, use cnt_lu_off to select one of the shadow register value as limitation
966  */
967 #define PWMV2_CNT_CFG1_CNT_LU_EN_MASK (0x800000UL)
968 #define PWMV2_CNT_CFG1_CNT_LU_EN_SHIFT (23U)
969 #define PWMV2_CNT_CFG1_CNT_LU_EN_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG1_CNT_LU_EN_SHIFT) & PWMV2_CNT_CFG1_CNT_LU_EN_MASK)
970 #define PWMV2_CNT_CFG1_CNT_LU_EN_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG1_CNT_LU_EN_MASK) >> PWMV2_CNT_CFG1_CNT_LU_EN_SHIFT)
971 
972 /*
973  * CNT_LIM_UP (RW)
974  *
975  * up limit offset selection, from one of the shadow_val
976  */
977 #define PWMV2_CNT_CFG1_CNT_LIM_UP_MASK (0x1F0000UL)
978 #define PWMV2_CNT_CFG1_CNT_LIM_UP_SHIFT (16U)
979 #define PWMV2_CNT_CFG1_CNT_LIM_UP_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG1_CNT_LIM_UP_SHIFT) & PWMV2_CNT_CFG1_CNT_LIM_UP_MASK)
980 #define PWMV2_CNT_CFG1_CNT_LIM_UP_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG1_CNT_LIM_UP_MASK) >> PWMV2_CNT_CFG1_CNT_LIM_UP_SHIFT)
981 
982 /*
983  * CNT_LL_EN (RW)
984  *
985  * set to enable low limit
986  */
987 #define PWMV2_CNT_CFG1_CNT_LL_EN_MASK (0x8000U)
988 #define PWMV2_CNT_CFG1_CNT_LL_EN_SHIFT (15U)
989 #define PWMV2_CNT_CFG1_CNT_LL_EN_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG1_CNT_LL_EN_SHIFT) & PWMV2_CNT_CFG1_CNT_LL_EN_MASK)
990 #define PWMV2_CNT_CFG1_CNT_LL_EN_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG1_CNT_LL_EN_MASK) >> PWMV2_CNT_CFG1_CNT_LL_EN_SHIFT)
991 
992 /*
993  * CNT_LIM_LO (RW)
994  *
995  * low limit offset selection, from one of the shadow_val
996  */
997 #define PWMV2_CNT_CFG1_CNT_LIM_LO_MASK (0x1F00U)
998 #define PWMV2_CNT_CFG1_CNT_LIM_LO_SHIFT (8U)
999 #define PWMV2_CNT_CFG1_CNT_LIM_LO_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG1_CNT_LIM_LO_SHIFT) & PWMV2_CNT_CFG1_CNT_LIM_LO_MASK)
1000 #define PWMV2_CNT_CFG1_CNT_LIM_LO_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG1_CNT_LIM_LO_MASK) >> PWMV2_CNT_CFG1_CNT_LIM_LO_SHIFT)
1001 
1002 /*
1003  * CNT_IN_OFF (RW)
1004  *
1005  * input data offset selection, from one of the shadow_val, default just shadow reload time
1006  */
1007 #define PWMV2_CNT_CFG1_CNT_IN_OFF_MASK (0x1FU)
1008 #define PWMV2_CNT_CFG1_CNT_IN_OFF_SHIFT (0U)
1009 #define PWMV2_CNT_CFG1_CNT_IN_OFF_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG1_CNT_IN_OFF_SHIFT) & PWMV2_CNT_CFG1_CNT_IN_OFF_MASK)
1010 #define PWMV2_CNT_CFG1_CNT_IN_OFF_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG1_CNT_IN_OFF_MASK) >> PWMV2_CNT_CFG1_CNT_IN_OFF_SHIFT)
1011 
1012 /* Bitfield definition for register of struct array CNT: CFG2 */
1013 /*
1014  * CNT_RELOAD_EN (RW)
1015  *
1016  * set to use input signal(selected by cnt_reload_trig) to reload timer
1017  */
1018 #define PWMV2_CNT_CFG2_CNT_RELOAD_EN_MASK (0x80000000UL)
1019 #define PWMV2_CNT_CFG2_CNT_RELOAD_EN_SHIFT (31U)
1020 #define PWMV2_CNT_CFG2_CNT_RELOAD_EN_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_RELOAD_EN_SHIFT) & PWMV2_CNT_CFG2_CNT_RELOAD_EN_MASK)
1021 #define PWMV2_CNT_CFG2_CNT_RELOAD_EN_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_RELOAD_EN_MASK) >> PWMV2_CNT_CFG2_CNT_RELOAD_EN_SHIFT)
1022 
1023 /*
1024  * CNT_RELOAD_TRIG (RW)
1025  *
1026  * select one trigger from 8, should set to pulse in trig_mux
1027  */
1028 #define PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_MASK (0x7000000UL)
1029 #define PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_SHIFT (24U)
1030 #define PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_SHIFT) & PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_MASK)
1031 #define PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_MASK) >> PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_SHIFT)
1032 
1033 /*
1034  * CNT_UPDATE_TRIG1 (RW)
1035  *
1036  * select one trigger from 8, should set to pulse in trig_mux
1037  */
1038 #define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_MASK (0x700000UL)
1039 #define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_SHIFT (20U)
1040 #define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_SHIFT) & PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_MASK)
1041 #define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_MASK) >> PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_SHIFT)
1042 
1043 /*
1044  * CNT_UPDATE_EN1 (RW)
1045  *
1046  * set to enable using trig1 to load calculation cell output to counter
1047  */
1048 #define PWMV2_CNT_CFG2_CNT_UPDATE_EN1_MASK (0x80000UL)
1049 #define PWMV2_CNT_CFG2_CNT_UPDATE_EN1_SHIFT (19U)
1050 #define PWMV2_CNT_CFG2_CNT_UPDATE_EN1_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_UPDATE_EN1_SHIFT) & PWMV2_CNT_CFG2_CNT_UPDATE_EN1_MASK)
1051 #define PWMV2_CNT_CFG2_CNT_UPDATE_EN1_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_UPDATE_EN1_MASK) >> PWMV2_CNT_CFG2_CNT_UPDATE_EN1_SHIFT)
1052 
1053 /*
1054  * CNT_TRIG1 (RW)
1055  *
1056  * change counter value to one of the calculation cell output when cnt_update_triger1 issued
1057  */
1058 #define PWMV2_CNT_CFG2_CNT_TRIG1_MASK (0xF000U)
1059 #define PWMV2_CNT_CFG2_CNT_TRIG1_SHIFT (12U)
1060 #define PWMV2_CNT_CFG2_CNT_TRIG1_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_TRIG1_SHIFT) & PWMV2_CNT_CFG2_CNT_TRIG1_MASK)
1061 #define PWMV2_CNT_CFG2_CNT_TRIG1_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_TRIG1_MASK) >> PWMV2_CNT_CFG2_CNT_TRIG1_SHIFT)
1062 
1063 /*
1064  * CNT_UPDATE_TRIG0 (RW)
1065  *
1066  * select one trigger from 8, should set to pulse in trig_mux
1067  */
1068 #define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_MASK (0x700U)
1069 #define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_SHIFT (8U)
1070 #define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_SHIFT) & PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_MASK)
1071 #define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_MASK) >> PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_SHIFT)
1072 
1073 /*
1074  * CNT_UPDATE_EN0 (RW)
1075  *
1076  * set to enable using trig0 to load calculation cell output to counter
1077  */
1078 #define PWMV2_CNT_CFG2_CNT_UPDATE_EN0_MASK (0x80U)
1079 #define PWMV2_CNT_CFG2_CNT_UPDATE_EN0_SHIFT (7U)
1080 #define PWMV2_CNT_CFG2_CNT_UPDATE_EN0_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_UPDATE_EN0_SHIFT) & PWMV2_CNT_CFG2_CNT_UPDATE_EN0_MASK)
1081 #define PWMV2_CNT_CFG2_CNT_UPDATE_EN0_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_UPDATE_EN0_MASK) >> PWMV2_CNT_CFG2_CNT_UPDATE_EN0_SHIFT)
1082 
1083 /*
1084  * CNT_TRIG0 (RW)
1085  *
1086  * change counter value to one of the calculation cell output when cnt_update_triger0 issued
1087  */
1088 #define PWMV2_CNT_CFG2_CNT_TRIG0_MASK (0xFU)
1089 #define PWMV2_CNT_CFG2_CNT_TRIG0_SHIFT (0U)
1090 #define PWMV2_CNT_CFG2_CNT_TRIG0_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_TRIG0_SHIFT) & PWMV2_CNT_CFG2_CNT_TRIG0_MASK)
1091 #define PWMV2_CNT_CFG2_CNT_TRIG0_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_TRIG0_MASK) >> PWMV2_CNT_CFG2_CNT_TRIG0_SHIFT)
1092 
1093 /* Bitfield definition for register of struct array CNT: CFG3 */
1094 /*
1095  * CNT_START_SEL (RW)
1096  *
1097  * select one trigger from 8, should set to pulse in trig_mux
1098  */
1099 #define PWMV2_CNT_CFG3_CNT_START_SEL_MASK (0x700000UL)
1100 #define PWMV2_CNT_CFG3_CNT_START_SEL_SHIFT (20U)
1101 #define PWMV2_CNT_CFG3_CNT_START_SEL_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG3_CNT_START_SEL_SHIFT) & PWMV2_CNT_CFG3_CNT_START_SEL_MASK)
1102 #define PWMV2_CNT_CFG3_CNT_START_SEL_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG3_CNT_START_SEL_MASK) >> PWMV2_CNT_CFG3_CNT_START_SEL_SHIFT)
1103 
1104 /*
1105  * CNT_HW_START_EN (RW)
1106  *
1107  * enable use trigger to start pwm output(at next reload point), by cnt_start_sel
1108  */
1109 #define PWMV2_CNT_CFG3_CNT_HW_START_EN_MASK (0x20000UL)
1110 #define PWMV2_CNT_CFG3_CNT_HW_START_EN_SHIFT (17U)
1111 #define PWMV2_CNT_CFG3_CNT_HW_START_EN_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG3_CNT_HW_START_EN_SHIFT) & PWMV2_CNT_CFG3_CNT_HW_START_EN_MASK)
1112 #define PWMV2_CNT_CFG3_CNT_HW_START_EN_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG3_CNT_HW_START_EN_MASK) >> PWMV2_CNT_CFG3_CNT_HW_START_EN_SHIFT)
1113 
1114 /*
1115  * CNT_BURST (RW)
1116  *
1117  * output pwm wave for configured burst(timer period),
1118  * 0 for one burst; 1 for two burst.
1119  * set to 0xFFFF for always output pwm wave
1120  * bit's only used when setting cnt_sw_start or trigger selected by cnt_start_sel
1121  */
1122 #define PWMV2_CNT_CFG3_CNT_BURST_MASK (0xFFFFU)
1123 #define PWMV2_CNT_CFG3_CNT_BURST_SHIFT (0U)
1124 #define PWMV2_CNT_CFG3_CNT_BURST_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG3_CNT_BURST_SHIFT) & PWMV2_CNT_CFG3_CNT_BURST_MASK)
1125 #define PWMV2_CNT_CFG3_CNT_BURST_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG3_CNT_BURST_MASK) >> PWMV2_CNT_CFG3_CNT_BURST_SHIFT)
1126 
1127 /* Bitfield definition for register: CNT_GLBCFG */
1128 /*
1129  * CNT_SW_START (WO)
1130  *
1131  * set to start pwm output(at next reload point), write only, Auto clear.
1132  * User can disable pwm output before burst end by start again with cnt_burst=0
1133  */
1134 #define PWMV2_CNT_GLBCFG_CNT_SW_START_MASK (0xF0000UL)
1135 #define PWMV2_CNT_GLBCFG_CNT_SW_START_SHIFT (16U)
1136 #define PWMV2_CNT_GLBCFG_CNT_SW_START_SET(x) (((uint32_t)(x) << PWMV2_CNT_GLBCFG_CNT_SW_START_SHIFT) & PWMV2_CNT_GLBCFG_CNT_SW_START_MASK)
1137 #define PWMV2_CNT_GLBCFG_CNT_SW_START_GET(x) (((uint32_t)(x) & PWMV2_CNT_GLBCFG_CNT_SW_START_MASK) >> PWMV2_CNT_GLBCFG_CNT_SW_START_SHIFT)
1138 
1139 /*
1140  * TIMER_RESET (WO)
1141  *
1142  * set to clear current timer. Auto clear
1143  */
1144 #define PWMV2_CNT_GLBCFG_TIMER_RESET_MASK (0xF00U)
1145 #define PWMV2_CNT_GLBCFG_TIMER_RESET_SHIFT (8U)
1146 #define PWMV2_CNT_GLBCFG_TIMER_RESET_SET(x) (((uint32_t)(x) << PWMV2_CNT_GLBCFG_TIMER_RESET_SHIFT) & PWMV2_CNT_GLBCFG_TIMER_RESET_MASK)
1147 #define PWMV2_CNT_GLBCFG_TIMER_RESET_GET(x) (((uint32_t)(x) & PWMV2_CNT_GLBCFG_TIMER_RESET_MASK) >> PWMV2_CNT_GLBCFG_TIMER_RESET_SHIFT)
1148 
1149 /*
1150  * TIMER_ENABLE (RW)
1151  *
1152  * 1 to enable the main cycle counter; 0 to stop the counter;
1153  * NOTE: when counter stopped, the related trigger_out will be cleared to 0, the related pwm output will keep value not changed.
1154  */
1155 #define PWMV2_CNT_GLBCFG_TIMER_ENABLE_MASK (0xFU)
1156 #define PWMV2_CNT_GLBCFG_TIMER_ENABLE_SHIFT (0U)
1157 #define PWMV2_CNT_GLBCFG_TIMER_ENABLE_SET(x) (((uint32_t)(x) << PWMV2_CNT_GLBCFG_TIMER_ENABLE_SHIFT) & PWMV2_CNT_GLBCFG_TIMER_ENABLE_MASK)
1158 #define PWMV2_CNT_GLBCFG_TIMER_ENABLE_GET(x) (((uint32_t)(x) & PWMV2_CNT_GLBCFG_TIMER_ENABLE_MASK) >> PWMV2_CNT_GLBCFG_TIMER_ENABLE_SHIFT)
1159 
1160 /* Bitfield definition for register of struct array CAL: CFG0 */
1161 /*
1162  * CAL_LU_PARAM (RW)
1163  *
1164  * up limit parameter
1165  */
1166 #define PWMV2_CAL_CFG0_CAL_LU_PARAM_MASK (0x1F000000UL)
1167 #define PWMV2_CAL_CFG0_CAL_LU_PARAM_SHIFT (24U)
1168 #define PWMV2_CAL_CFG0_CAL_LU_PARAM_SET(x) (((uint32_t)(x) << PWMV2_CAL_CFG0_CAL_LU_PARAM_SHIFT) & PWMV2_CAL_CFG0_CAL_LU_PARAM_MASK)
1169 #define PWMV2_CAL_CFG0_CAL_LU_PARAM_GET(x) (((uint32_t)(x) & PWMV2_CAL_CFG0_CAL_LU_PARAM_MASK) >> PWMV2_CAL_CFG0_CAL_LU_PARAM_SHIFT)
1170 
1171 /*
1172  * CAL_LL_PARAM (RW)
1173  *
1174  * low limit parameter
1175  */
1176 #define PWMV2_CAL_CFG0_CAL_LL_PARAM_MASK (0x1F0000UL)
1177 #define PWMV2_CAL_CFG0_CAL_LL_PARAM_SHIFT (16U)
1178 #define PWMV2_CAL_CFG0_CAL_LL_PARAM_SET(x) (((uint32_t)(x) << PWMV2_CAL_CFG0_CAL_LL_PARAM_SHIFT) & PWMV2_CAL_CFG0_CAL_LL_PARAM_MASK)
1179 #define PWMV2_CAL_CFG0_CAL_LL_PARAM_GET(x) (((uint32_t)(x) & PWMV2_CAL_CFG0_CAL_LL_PARAM_MASK) >> PWMV2_CAL_CFG0_CAL_LL_PARAM_SHIFT)
1180 
1181 /*
1182  * CAL_T_PARAM (RW)
1183  *
1184  * period parameter
1185  */
1186 #define PWMV2_CAL_CFG0_CAL_T_PARAM_MASK (0x1F00U)
1187 #define PWMV2_CAL_CFG0_CAL_T_PARAM_SHIFT (8U)
1188 #define PWMV2_CAL_CFG0_CAL_T_PARAM_SET(x) (((uint32_t)(x) << PWMV2_CAL_CFG0_CAL_T_PARAM_SHIFT) & PWMV2_CAL_CFG0_CAL_T_PARAM_MASK)
1189 #define PWMV2_CAL_CFG0_CAL_T_PARAM_GET(x) (((uint32_t)(x) & PWMV2_CAL_CFG0_CAL_T_PARAM_MASK) >> PWMV2_CAL_CFG0_CAL_T_PARAM_SHIFT)
1190 
1191 /*
1192  * CAL_D_PARAM (RW)
1193  *
1194  * dac/counter value parameter
1195  */
1196 #define PWMV2_CAL_CFG0_CAL_D_PARAM_MASK (0x1FU)
1197 #define PWMV2_CAL_CFG0_CAL_D_PARAM_SHIFT (0U)
1198 #define PWMV2_CAL_CFG0_CAL_D_PARAM_SET(x) (((uint32_t)(x) << PWMV2_CAL_CFG0_CAL_D_PARAM_SHIFT) & PWMV2_CAL_CFG0_CAL_D_PARAM_MASK)
1199 #define PWMV2_CAL_CFG0_CAL_D_PARAM_GET(x) (((uint32_t)(x) & PWMV2_CAL_CFG0_CAL_D_PARAM_MASK) >> PWMV2_CAL_CFG0_CAL_D_PARAM_SHIFT)
1200 
1201 /* Bitfield definition for register of struct array CAL: CFG1 */
1202 /*
1203  * CAL_T_INDEX (RW)
1204  *
1205  * select one of 4 counter reload time
1206  */
1207 #define PWMV2_CAL_CFG1_CAL_T_INDEX_MASK (0x30000000UL)
1208 #define PWMV2_CAL_CFG1_CAL_T_INDEX_SHIFT (28U)
1209 #define PWMV2_CAL_CFG1_CAL_T_INDEX_SET(x) (((uint32_t)(x) << PWMV2_CAL_CFG1_CAL_T_INDEX_SHIFT) & PWMV2_CAL_CFG1_CAL_T_INDEX_MASK)
1210 #define PWMV2_CAL_CFG1_CAL_T_INDEX_GET(x) (((uint32_t)(x) & PWMV2_CAL_CFG1_CAL_T_INDEX_MASK) >> PWMV2_CAL_CFG1_CAL_T_INDEX_SHIFT)
1211 
1212 /*
1213  * CAL_IN_INDEX (RW)
1214  *
1215  * 0~3 to select one of the dac input value; 4~7 to select one of the current counter value
1216  */
1217 #define PWMV2_CAL_CFG1_CAL_IN_INDEX_MASK (0x7000000UL)
1218 #define PWMV2_CAL_CFG1_CAL_IN_INDEX_SHIFT (24U)
1219 #define PWMV2_CAL_CFG1_CAL_IN_INDEX_SET(x) (((uint32_t)(x) << PWMV2_CAL_CFG1_CAL_IN_INDEX_SHIFT) & PWMV2_CAL_CFG1_CAL_IN_INDEX_MASK)
1220 #define PWMV2_CAL_CFG1_CAL_IN_INDEX_GET(x) (((uint32_t)(x) & PWMV2_CAL_CFG1_CAL_IN_INDEX_MASK) >> PWMV2_CAL_CFG1_CAL_IN_INDEX_SHIFT)
1221 
1222 /*
1223  * CAL_LU_EN (RW)
1224  *
1225  * set to enable up limit
1226  */
1227 #define PWMV2_CAL_CFG1_CAL_LU_EN_MASK (0x800000UL)
1228 #define PWMV2_CAL_CFG1_CAL_LU_EN_SHIFT (23U)
1229 #define PWMV2_CAL_CFG1_CAL_LU_EN_SET(x) (((uint32_t)(x) << PWMV2_CAL_CFG1_CAL_LU_EN_SHIFT) & PWMV2_CAL_CFG1_CAL_LU_EN_MASK)
1230 #define PWMV2_CAL_CFG1_CAL_LU_EN_GET(x) (((uint32_t)(x) & PWMV2_CAL_CFG1_CAL_LU_EN_MASK) >> PWMV2_CAL_CFG1_CAL_LU_EN_SHIFT)
1231 
1232 /*
1233  * CAL_LIM_UP (RW)
1234  *
1235  * up limit offset selection, select from one of the shadow_val
1236  */
1237 #define PWMV2_CAL_CFG1_CAL_LIM_UP_MASK (0x1F0000UL)
1238 #define PWMV2_CAL_CFG1_CAL_LIM_UP_SHIFT (16U)
1239 #define PWMV2_CAL_CFG1_CAL_LIM_UP_SET(x) (((uint32_t)(x) << PWMV2_CAL_CFG1_CAL_LIM_UP_SHIFT) & PWMV2_CAL_CFG1_CAL_LIM_UP_MASK)
1240 #define PWMV2_CAL_CFG1_CAL_LIM_UP_GET(x) (((uint32_t)(x) & PWMV2_CAL_CFG1_CAL_LIM_UP_MASK) >> PWMV2_CAL_CFG1_CAL_LIM_UP_SHIFT)
1241 
1242 /*
1243  * CAL_LL_EN (RW)
1244  *
1245  * set to enable low limit
1246  */
1247 #define PWMV2_CAL_CFG1_CAL_LL_EN_MASK (0x8000U)
1248 #define PWMV2_CAL_CFG1_CAL_LL_EN_SHIFT (15U)
1249 #define PWMV2_CAL_CFG1_CAL_LL_EN_SET(x) (((uint32_t)(x) << PWMV2_CAL_CFG1_CAL_LL_EN_SHIFT) & PWMV2_CAL_CFG1_CAL_LL_EN_MASK)
1250 #define PWMV2_CAL_CFG1_CAL_LL_EN_GET(x) (((uint32_t)(x) & PWMV2_CAL_CFG1_CAL_LL_EN_MASK) >> PWMV2_CAL_CFG1_CAL_LL_EN_SHIFT)
1251 
1252 /*
1253  * CAL_LIM_LO (RW)
1254  *
1255  * low limit offset selection, select from one of the shadow_val
1256  */
1257 #define PWMV2_CAL_CFG1_CAL_LIM_LO_MASK (0x1F00U)
1258 #define PWMV2_CAL_CFG1_CAL_LIM_LO_SHIFT (8U)
1259 #define PWMV2_CAL_CFG1_CAL_LIM_LO_SET(x) (((uint32_t)(x) << PWMV2_CAL_CFG1_CAL_LIM_LO_SHIFT) & PWMV2_CAL_CFG1_CAL_LIM_LO_MASK)
1260 #define PWMV2_CAL_CFG1_CAL_LIM_LO_GET(x) (((uint32_t)(x) & PWMV2_CAL_CFG1_CAL_LIM_LO_MASK) >> PWMV2_CAL_CFG1_CAL_LIM_LO_SHIFT)
1261 
1262 /*
1263  * CAL_IN_OFF (RW)
1264  *
1265  * offset for calculation unit, select from one of the shadow_val.
1266  */
1267 #define PWMV2_CAL_CFG1_CAL_IN_OFF_MASK (0x1FU)
1268 #define PWMV2_CAL_CFG1_CAL_IN_OFF_SHIFT (0U)
1269 #define PWMV2_CAL_CFG1_CAL_IN_OFF_SET(x) (((uint32_t)(x) << PWMV2_CAL_CFG1_CAL_IN_OFF_SHIFT) & PWMV2_CAL_CFG1_CAL_IN_OFF_MASK)
1270 #define PWMV2_CAL_CFG1_CAL_IN_OFF_GET(x) (((uint32_t)(x) & PWMV2_CAL_CFG1_CAL_IN_OFF_MASK) >> PWMV2_CAL_CFG1_CAL_IN_OFF_SHIFT)
1271 
1272 /* Bitfield definition for register of struct array CMP: CFG */
1273 /*
1274  * CMP_TRIG_SEL (RW)
1275  *
1276  * select one trigger from 8, should set to pulse in trig_mux
1277  */
1278 #define PWMV2_CMP_CFG_CMP_TRIG_SEL_MASK (0x70000000UL)
1279 #define PWMV2_CMP_CFG_CMP_TRIG_SEL_SHIFT (28U)
1280 #define PWMV2_CMP_CFG_CMP_TRIG_SEL_SET(x) (((uint32_t)(x) << PWMV2_CMP_CFG_CMP_TRIG_SEL_SHIFT) & PWMV2_CMP_CFG_CMP_TRIG_SEL_MASK)
1281 #define PWMV2_CMP_CFG_CMP_TRIG_SEL_GET(x) (((uint32_t)(x) & PWMV2_CMP_CFG_CMP_TRIG_SEL_MASK) >> PWMV2_CMP_CFG_CMP_TRIG_SEL_SHIFT)
1282 
1283 /*
1284  * CMP_UPDATE_TIME (RW)
1285  *
1286  * define when to use the shadow register value for working register(trig_cmp)
1287  * 000: software set work_ctrl1.shadow_lock bit
1288  * 001: update immediately(at next cycle)
1289  * 010: related counter reload time
1290  * 011: use cmp_update_trigger(from trig_mux, selected by cmp_trig_sel)
1291  * 100: use the related counter rld_cmp_sel0 to select one compare point
1292  * 101: use the related counter rld_cmp_sel1, to select one compare point
1293  * 11x: reserved, no update.
1294  */
1295 #define PWMV2_CMP_CFG_CMP_UPDATE_TIME_MASK (0x7000000UL)
1296 #define PWMV2_CMP_CFG_CMP_UPDATE_TIME_SHIFT (24U)
1297 #define PWMV2_CMP_CFG_CMP_UPDATE_TIME_SET(x) (((uint32_t)(x) << PWMV2_CMP_CFG_CMP_UPDATE_TIME_SHIFT) & PWMV2_CMP_CFG_CMP_UPDATE_TIME_MASK)
1298 #define PWMV2_CMP_CFG_CMP_UPDATE_TIME_GET(x) (((uint32_t)(x) & PWMV2_CMP_CFG_CMP_UPDATE_TIME_MASK) >> PWMV2_CMP_CFG_CMP_UPDATE_TIME_SHIFT)
1299 
1300 /*
1301  * CMP_IN_SEL (RW)
1302  *
1303  * 0x00~0x1B select one of the shadow_val directly
1304  * 0x20~0x2F select one of the calculation cell output
1305  * 0x30~0x37 select one of capture_pos value(low 8bit are 0)
1306  * 0x38+k select T/4
1307  * 0x3E select 0xFFFFF000
1308  * 0x3F select 0xFFFFFF00
1309  * others select 0
1310  */
1311 #define PWMV2_CMP_CFG_CMP_IN_SEL_MASK (0x3F0000UL)
1312 #define PWMV2_CMP_CFG_CMP_IN_SEL_SHIFT (16U)
1313 #define PWMV2_CMP_CFG_CMP_IN_SEL_SET(x) (((uint32_t)(x) << PWMV2_CMP_CFG_CMP_IN_SEL_SHIFT) & PWMV2_CMP_CFG_CMP_IN_SEL_MASK)
1314 #define PWMV2_CMP_CFG_CMP_IN_SEL_GET(x) (((uint32_t)(x) & PWMV2_CMP_CFG_CMP_IN_SEL_MASK) >> PWMV2_CMP_CFG_CMP_IN_SEL_SHIFT)
1315 
1316 /*
1317  * CMP_CNT (RW)
1318  *
1319  * select one from 4 counters, only for N>=16.
1320  * for N<16, this field is0, every 4 compare point related to one counter(0123 for counter0, 4567 for counter1….)
1321  */
1322 #define PWMV2_CMP_CFG_CMP_CNT_MASK (0xC000U)
1323 #define PWMV2_CMP_CFG_CMP_CNT_SHIFT (14U)
1324 #define PWMV2_CMP_CFG_CMP_CNT_SET(x) (((uint32_t)(x) << PWMV2_CMP_CFG_CMP_CNT_SHIFT) & PWMV2_CMP_CFG_CMP_CNT_MASK)
1325 #define PWMV2_CMP_CFG_CMP_CNT_GET(x) (((uint32_t)(x) & PWMV2_CMP_CFG_CMP_CNT_MASK) >> PWMV2_CMP_CFG_CMP_CNT_SHIFT)
1326 
1327 
1328 
1329 /* SHADOW_VAL register group index macro definition */
1330 #define PWMV2_SHADOW_VAL_0 (0UL)
1331 #define PWMV2_SHADOW_VAL_1 (1UL)
1332 #define PWMV2_SHADOW_VAL_2 (2UL)
1333 #define PWMV2_SHADOW_VAL_3 (3UL)
1334 #define PWMV2_SHADOW_VAL_4 (4UL)
1335 #define PWMV2_SHADOW_VAL_5 (5UL)
1336 #define PWMV2_SHADOW_VAL_6 (6UL)
1337 #define PWMV2_SHADOW_VAL_7 (7UL)
1338 #define PWMV2_SHADOW_VAL_8 (8UL)
1339 #define PWMV2_SHADOW_VAL_9 (9UL)
1340 #define PWMV2_SHADOW_VAL_10 (10UL)
1341 #define PWMV2_SHADOW_VAL_11 (11UL)
1342 #define PWMV2_SHADOW_VAL_12 (12UL)
1343 #define PWMV2_SHADOW_VAL_13 (13UL)
1344 #define PWMV2_SHADOW_VAL_14 (14UL)
1345 #define PWMV2_SHADOW_VAL_15 (15UL)
1346 #define PWMV2_SHADOW_VAL_16 (16UL)
1347 #define PWMV2_SHADOW_VAL_17 (17UL)
1348 #define PWMV2_SHADOW_VAL_18 (18UL)
1349 #define PWMV2_SHADOW_VAL_19 (19UL)
1350 #define PWMV2_SHADOW_VAL_20 (20UL)
1351 #define PWMV2_SHADOW_VAL_21 (21UL)
1352 #define PWMV2_SHADOW_VAL_22 (22UL)
1353 #define PWMV2_SHADOW_VAL_23 (23UL)
1354 #define PWMV2_SHADOW_VAL_24 (24UL)
1355 #define PWMV2_SHADOW_VAL_25 (25UL)
1356 #define PWMV2_SHADOW_VAL_26 (26UL)
1357 #define PWMV2_SHADOW_VAL_27 (27UL)
1358 
1359 /* PWM register group index macro definition */
1360 #define PWMV2_PWM_0 (0UL)
1361 #define PWMV2_PWM_1 (1UL)
1362 #define PWMV2_PWM_2 (2UL)
1363 #define PWMV2_PWM_3 (3UL)
1364 #define PWMV2_PWM_4 (4UL)
1365 #define PWMV2_PWM_5 (5UL)
1366 #define PWMV2_PWM_6 (6UL)
1367 #define PWMV2_PWM_7 (7UL)
1368 
1369 /* TRIGGER_CFG register group index macro definition */
1370 #define PWMV2_TRIGGER_CFG_0 (0UL)
1371 #define PWMV2_TRIGGER_CFG_1 (1UL)
1372 #define PWMV2_TRIGGER_CFG_2 (2UL)
1373 #define PWMV2_TRIGGER_CFG_3 (3UL)
1374 #define PWMV2_TRIGGER_CFG_4 (4UL)
1375 #define PWMV2_TRIGGER_CFG_5 (5UL)
1376 #define PWMV2_TRIGGER_CFG_6 (6UL)
1377 #define PWMV2_TRIGGER_CFG_7 (7UL)
1378 
1379 /* CNT_RELOAD_WORK register group index macro definition */
1380 #define PWMV2_CNT_RELOAD_WORK_0 (0UL)
1381 #define PWMV2_CNT_RELOAD_WORK_1 (1UL)
1382 #define PWMV2_CNT_RELOAD_WORK_2 (2UL)
1383 #define PWMV2_CNT_RELOAD_WORK_3 (3UL)
1384 
1385 /* CMP_VAL_WORK register group index macro definition */
1386 #define PWMV2_CMP_VAL_WORK_0 (0UL)
1387 #define PWMV2_CMP_VAL_WORK_1 (1UL)
1388 #define PWMV2_CMP_VAL_WORK_2 (2UL)
1389 #define PWMV2_CMP_VAL_WORK_3 (3UL)
1390 #define PWMV2_CMP_VAL_WORK_4 (4UL)
1391 #define PWMV2_CMP_VAL_WORK_5 (5UL)
1392 #define PWMV2_CMP_VAL_WORK_6 (6UL)
1393 #define PWMV2_CMP_VAL_WORK_7 (7UL)
1394 #define PWMV2_CMP_VAL_WORK_8 (8UL)
1395 #define PWMV2_CMP_VAL_WORK_9 (9UL)
1396 #define PWMV2_CMP_VAL_WORK_10 (10UL)
1397 #define PWMV2_CMP_VAL_WORK_11 (11UL)
1398 #define PWMV2_CMP_VAL_WORK_12 (12UL)
1399 #define PWMV2_CMP_VAL_WORK_13 (13UL)
1400 #define PWMV2_CMP_VAL_WORK_14 (14UL)
1401 #define PWMV2_CMP_VAL_WORK_15 (15UL)
1402 #define PWMV2_CMP_VAL_WORK_16 (16UL)
1403 #define PWMV2_CMP_VAL_WORK_17 (17UL)
1404 #define PWMV2_CMP_VAL_WORK_18 (18UL)
1405 #define PWMV2_CMP_VAL_WORK_19 (19UL)
1406 #define PWMV2_CMP_VAL_WORK_20 (20UL)
1407 #define PWMV2_CMP_VAL_WORK_21 (21UL)
1408 #define PWMV2_CMP_VAL_WORK_22 (22UL)
1409 #define PWMV2_CMP_VAL_WORK_23 (23UL)
1410 
1411 /* CNT_VAL register group index macro definition */
1412 #define PWMV2_CNT_VAL_0 (0UL)
1413 #define PWMV2_CNT_VAL_1 (1UL)
1414 #define PWMV2_CNT_VAL_2 (2UL)
1415 #define PWMV2_CNT_VAL_3 (3UL)
1416 
1417 /* DAC_VALUE_SV register group index macro definition */
1418 #define PWMV2_DAC_VALUE_SV_0 (0UL)
1419 #define PWMV2_DAC_VALUE_SV_1 (1UL)
1420 #define PWMV2_DAC_VALUE_SV_2 (2UL)
1421 #define PWMV2_DAC_VALUE_SV_3 (3UL)
1422 
1423 /* CAPTURE_POS register group index macro definition */
1424 #define PWMV2_CAPTURE_POS_0 (0UL)
1425 #define PWMV2_CAPTURE_POS_1 (1UL)
1426 #define PWMV2_CAPTURE_POS_2 (2UL)
1427 #define PWMV2_CAPTURE_POS_3 (3UL)
1428 #define PWMV2_CAPTURE_POS_4 (4UL)
1429 #define PWMV2_CAPTURE_POS_5 (5UL)
1430 #define PWMV2_CAPTURE_POS_6 (6UL)
1431 #define PWMV2_CAPTURE_POS_7 (7UL)
1432 
1433 /* CAPTURE_NEG register group index macro definition */
1434 #define PWMV2_CAPTURE_NEG_0 (0UL)
1435 #define PWMV2_CAPTURE_NEG_1 (1UL)
1436 #define PWMV2_CAPTURE_NEG_2 (2UL)
1437 #define PWMV2_CAPTURE_NEG_3 (3UL)
1438 #define PWMV2_CAPTURE_NEG_4 (4UL)
1439 #define PWMV2_CAPTURE_NEG_5 (5UL)
1440 #define PWMV2_CAPTURE_NEG_6 (6UL)
1441 #define PWMV2_CAPTURE_NEG_7 (7UL)
1442 
1443 /* CNT register group index macro definition */
1444 #define PWMV2_CNT_0 (0UL)
1445 #define PWMV2_CNT_1 (1UL)
1446 #define PWMV2_CNT_2 (2UL)
1447 #define PWMV2_CNT_3 (3UL)
1448 
1449 /* CAL register group index macro definition */
1450 #define PWMV2_CAL_0 (0UL)
1451 #define PWMV2_CAL_1 (1UL)
1452 #define PWMV2_CAL_2 (2UL)
1453 #define PWMV2_CAL_3 (3UL)
1454 #define PWMV2_CAL_4 (4UL)
1455 #define PWMV2_CAL_5 (5UL)
1456 #define PWMV2_CAL_6 (6UL)
1457 #define PWMV2_CAL_7 (7UL)
1458 #define PWMV2_CAL_8 (8UL)
1459 #define PWMV2_CAL_9 (9UL)
1460 #define PWMV2_CAL_10 (10UL)
1461 #define PWMV2_CAL_11 (11UL)
1462 #define PWMV2_CAL_12 (12UL)
1463 #define PWMV2_CAL_13 (13UL)
1464 #define PWMV2_CAL_14 (14UL)
1465 #define PWMV2_CAL_15 (15UL)
1466 
1467 /* CMP register group index macro definition */
1468 #define PWMV2_CMP_0 (0UL)
1469 #define PWMV2_CMP_1 (1UL)
1470 #define PWMV2_CMP_2 (2UL)
1471 #define PWMV2_CMP_3 (3UL)
1472 #define PWMV2_CMP_4 (4UL)
1473 #define PWMV2_CMP_5 (5UL)
1474 #define PWMV2_CMP_6 (6UL)
1475 #define PWMV2_CMP_7 (7UL)
1476 #define PWMV2_CMP_8 (8UL)
1477 #define PWMV2_CMP_9 (9UL)
1478 #define PWMV2_CMP_10 (10UL)
1479 #define PWMV2_CMP_11 (11UL)
1480 #define PWMV2_CMP_12 (12UL)
1481 #define PWMV2_CMP_13 (13UL)
1482 #define PWMV2_CMP_14 (14UL)
1483 #define PWMV2_CMP_15 (15UL)
1484 #define PWMV2_CMP_16 (16UL)
1485 #define PWMV2_CMP_17 (17UL)
1486 #define PWMV2_CMP_18 (18UL)
1487 #define PWMV2_CMP_19 (19UL)
1488 #define PWMV2_CMP_20 (20UL)
1489 #define PWMV2_CMP_21 (21UL)
1490 #define PWMV2_CMP_22 (22UL)
1491 #define PWMV2_CMP_23 (23UL)
1492 
1493 
1494 #endif /* HPM_PWMV2_H */
PWMV2_Type
Definition: hpm_pwmv2_regs.h:12