HPM SDK
HPMicro Software Development Kit
hpm_sei_regs.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_SEI_H
10 #define HPM_SEI_H
11 
12 typedef struct {
13  struct {
14  struct {
15  __RW uint32_t CTRL; /* 0x0: Engine control register */
16  __RW uint32_t PTR_CFG; /* 0x4: Pointer configuration register */
17  __RW uint32_t WDG_CFG; /* 0x8: Watch dog configuration register */
18  __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */
19  __R uint32_t EXE_STA; /* 0x10: Execution status */
20  __R uint32_t EXE_PTR; /* 0x14: Execution pointer */
21  __R uint32_t EXE_INST; /* 0x18: Execution instruction */
22  __R uint32_t WDG_STA; /* 0x1C: Watch dog status */
23  } ENGINE;
24  struct {
25  __RW uint32_t CTRL; /* 0x20: Transceiver control register */
26  __RW uint32_t TYPE_CFG; /* 0x24: Transceiver configuration register */
27  __RW uint32_t BAUD_CFG; /* 0x28: Transceiver baud rate register */
28  __RW uint32_t DATA_CFG; /* 0x2C: Transceiver data timing configuration */
29  __RW uint32_t CLK_CFG; /* 0x30: Transceiver clock timing configuration */
30  __R uint8_t RESERVED0[4]; /* 0x34 - 0x37: Reserved */
31  __R uint32_t PIN; /* 0x38: Transceiver pin status */
32  __R uint32_t STATE; /* 0x3C: FSM of asynchronous */
33  } XCVR;
34  struct {
35  __RW uint32_t IN_CFG; /* 0x40: Trigger input configuration */
36  __W uint32_t SW; /* 0x44: Software trigger */
37  __RW uint32_t PRD_CFG; /* 0x48: Period trigger configuration */
38  __RW uint32_t PRD; /* 0x4C: Trigger period */
39  __RW uint32_t OUT_CFG; /* 0x50: Trigger output configuration */
40  __R uint8_t RESERVED0[12]; /* 0x54 - 0x5F: Reserved */
41  __R uint32_t PRD_STS; /* 0x60: Period trigger status */
42  __R uint32_t PRD_CNT; /* 0x64: Period trigger counter */
43  __R uint8_t RESERVED1[24]; /* 0x68 - 0x7F: Reserved */
44  } TRG;
45  struct {
46  __RW uint32_t CMD[4]; /* 0x80 - 0x8C: Trigger command */
47  __R uint8_t RESERVED0[16]; /* 0x90 - 0x9F: Reserved */
48  __R uint32_t TIME[4]; /* 0xA0 - 0xAC: Trigger Time */
49  __R uint8_t RESERVED1[16]; /* 0xB0 - 0xBF: Reserved */
50  } TRG_TABLE;
51  struct {
52  __RW uint32_t MODE; /* 0xC0: command register mode */
53  __RW uint32_t IDX; /* 0xC4: command register configuration */
54  __R uint8_t RESERVED0[24]; /* 0xC8 - 0xDF: Reserved */
55  __RW uint32_t CMD; /* 0xE0: command */
56  __RW uint32_t SET; /* 0xE4: command bit set register */
57  __RW uint32_t CLR; /* 0xE8: command bit clear register */
58  __RW uint32_t INV; /* 0xEC: command bit invert register */
59  __R uint32_t IN; /* 0xF0: Commad input */
60  __R uint32_t OUT; /* 0xF4: Command output */
61  __RW uint32_t STS; /* 0xF8: Command status */
62  __R uint8_t RESERVED1[4]; /* 0xFC - 0xFF: Reserved */
63  } CMD;
64  struct {
65  __RW uint32_t MIN; /* 0x100: command start value */
66  __RW uint32_t MAX; /* 0x104: command end value */
67  __RW uint32_t MSK; /* 0x108: command compare bit enable */
68  __R uint8_t RESERVED0[4]; /* 0x10C - 0x10F: Reserved */
69  __RW uint32_t PTA; /* 0x110: command pointer 0 - 3 */
70  __RW uint32_t PTB; /* 0x114: command pointer 4 - 7 */
71  __RW uint32_t PTC; /* 0x118: command pointer 8 - 11 */
72  __RW uint32_t PTD; /* 0x11C: command pointer 12 - 15 */
73  } CMD_TABLE[8];
74  struct {
75  __RW uint32_t TRAN[4]; /* 0x200 - 0x20C: Latch state transition configuration */
76  __RW uint32_t CFG; /* 0x210: Latch configuration */
77  __R uint8_t RESERVED0[4]; /* 0x214 - 0x217: Reserved */
78  __R uint32_t TIME; /* 0x218: Latch time */
79  __R uint32_t STS; /* 0x21C: Latch status */
80  } LATCH[4];
81  struct {
82  __RW uint32_t SMP_EN; /* 0x280: Sample selection register */
83  __RW uint32_t SMP_CFG; /* 0x284: Sample configuration */
84  __RW uint32_t SMP_DAT; /* 0x288: Sample data */
85  __R uint8_t RESERVED0[4]; /* 0x28C - 0x28F: Reserved */
86  __RW uint32_t SMP_POS; /* 0x290: Sample override position */
87  __RW uint32_t SMP_REV; /* 0x294: Sample override revolution */
88  __RW uint32_t SMP_SPD; /* 0x298: Sample override speed */
89  __RW uint32_t SMP_ACC; /* 0x29C: Sample override accelerate */
90  __RW uint32_t UPD_EN; /* 0x2A0: Update configuration */
91  __RW uint32_t UPD_CFG; /* 0x2A4: Update configuration */
92  __RW uint32_t UPD_DAT; /* 0x2A8: Update data */
93  __RW uint32_t UPD_TIME; /* 0x2AC: Update overide time */
94  __RW uint32_t UPD_POS; /* 0x2B0: Update override position */
95  __RW uint32_t UPD_REV; /* 0x2B4: Update override revolution */
96  __RW uint32_t UPD_SPD; /* 0x2B8: Update override speed */
97  __RW uint32_t UPD_ACC; /* 0x2BC: Update override accelerate */
98  __R uint32_t SMP_VAL; /* 0x2C0: Sample valid */
99  __R uint32_t SMP_STS; /* 0x2C4: Sample status */
100  __R uint8_t RESERVED1[4]; /* 0x2C8 - 0x2CB: Reserved */
101  __R uint32_t TIME_IN; /* 0x2CC: input time */
102  __R uint32_t POS_IN; /* 0x2D0: Input position */
103  __R uint32_t REV_IN; /* 0x2D4: Input revolution */
104  __R uint32_t SPD_IN; /* 0x2D8: Input speed */
105  __R uint32_t ACC_IN; /* 0x2DC: Input accelerate */
106  __R uint8_t RESERVED2[4]; /* 0x2E0 - 0x2E3: Reserved */
107  __R uint32_t UPD_STS; /* 0x2E4: Update status */
108  __R uint8_t RESERVED3[24]; /* 0x2E8 - 0x2FF: Reserved */
109  } POS;
110  struct {
111  __RW uint32_t INT_EN; /* 0x300: Interrupt Enable */
112  __W uint32_t INT_FLAG; /* 0x304: Interrupt flag */
113  __R uint32_t INT_STS; /* 0x308: Interrupt status */
114  __R uint8_t RESERVED0[4]; /* 0x30C - 0x30F: Reserved */
115  __RW uint32_t POINTER0; /* 0x310: Match pointer 0 */
116  __RW uint32_t POINTER1; /* 0x314: Match pointer 1 */
117  __RW uint32_t INSTR0; /* 0x318: Match instruction 0 */
118  __RW uint32_t INSTR1; /* 0x31C: Match instruction 1 */
119  } IRQ;
120  __RW uint32_t DMA_EN; /* 0x320: DMA Enable */
121  __R uint8_t RESERVED0[220]; /* 0x324 - 0x3FF: Reserved */
122  } CTRL[13];
123  __RW uint32_t INSTR[256]; /* 0x3400 - 0x37FC: Instructions */
124  struct {
125  __RW uint32_t MODE; /* 0x3800: */
126  __RW uint32_t IDX; /* 0x3804: Data register bit index */
127  __RW uint32_t GOLD; /* 0x3808: Gold data for data check */
128  __RW uint32_t CRCINIT; /* 0x380C: CRC calculation initial vector */
129  __RW uint32_t CRCPOLY; /* 0x3810: CRC calculation polynomial */
130  __R uint8_t RESERVED0[12]; /* 0x3814 - 0x381F: Reserved */
131  __RW uint32_t DATA; /* 0x3820: Data value */
132  __RW uint32_t SET; /* 0x3824: Data bit set */
133  __RW uint32_t CLR; /* 0x3828: Data bit clear */
134  __RW uint32_t INV; /* 0x382C: Data bit invert */
135  __R uint32_t IN; /* 0x3830: Data input */
136  __R uint32_t OUT; /* 0x3834: Data output */
137  __RW uint32_t STS; /* 0x3838: Data status */
138  __R uint8_t RESERVED1[4]; /* 0x383C - 0x383F: Reserved */
139  } DAT[32];
140 } SEI_Type;
141 
142 
143 /* Bitfield definition for register of struct array CTRL: CTRL */
144 /*
145  * WATCH (RW)
146  *
147  * Enable watch dog
148  * 0: Watch dog disabled
149  * 1: Watch dog enabled
150  */
151 #define SEI_CTRL_ENGINE_CTRL_WATCH_MASK (0x1000000UL)
152 #define SEI_CTRL_ENGINE_CTRL_WATCH_SHIFT (24U)
153 #define SEI_CTRL_ENGINE_CTRL_WATCH_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_WATCH_SHIFT) & SEI_CTRL_ENGINE_CTRL_WATCH_MASK)
154 #define SEI_CTRL_ENGINE_CTRL_WATCH_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_WATCH_MASK) >> SEI_CTRL_ENGINE_CTRL_WATCH_SHIFT)
155 
156 /*
157  * ARMING (RW)
158  *
159  * Wait for trigger before excuting
160  * 0: Execute on enable
161  * 1: Wait trigger before exection after enabled
162  */
163 #define SEI_CTRL_ENGINE_CTRL_ARMING_MASK (0x10000UL)
164 #define SEI_CTRL_ENGINE_CTRL_ARMING_SHIFT (16U)
165 #define SEI_CTRL_ENGINE_CTRL_ARMING_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_ARMING_SHIFT) & SEI_CTRL_ENGINE_CTRL_ARMING_MASK)
166 #define SEI_CTRL_ENGINE_CTRL_ARMING_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_ARMING_MASK) >> SEI_CTRL_ENGINE_CTRL_ARMING_SHIFT)
167 
168 /*
169  * EXCEPT (RW)
170  *
171  * Explain timout as exception
172  * 0: when timeout, pointer move to next instruction
173  * 1: when timeout, pointer jump to timeout vector
174  */
175 #define SEI_CTRL_ENGINE_CTRL_EXCEPT_MASK (0x100U)
176 #define SEI_CTRL_ENGINE_CTRL_EXCEPT_SHIFT (8U)
177 #define SEI_CTRL_ENGINE_CTRL_EXCEPT_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_EXCEPT_SHIFT) & SEI_CTRL_ENGINE_CTRL_EXCEPT_MASK)
178 #define SEI_CTRL_ENGINE_CTRL_EXCEPT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_EXCEPT_MASK) >> SEI_CTRL_ENGINE_CTRL_EXCEPT_SHIFT)
179 
180 /*
181  * REWIND (RW)
182  *
183  * Rewind execution pointer
184  * 0: run
185  * 1: clean status and rewind
186  */
187 #define SEI_CTRL_ENGINE_CTRL_REWIND_MASK (0x10U)
188 #define SEI_CTRL_ENGINE_CTRL_REWIND_SHIFT (4U)
189 #define SEI_CTRL_ENGINE_CTRL_REWIND_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_REWIND_SHIFT) & SEI_CTRL_ENGINE_CTRL_REWIND_MASK)
190 #define SEI_CTRL_ENGINE_CTRL_REWIND_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_REWIND_MASK) >> SEI_CTRL_ENGINE_CTRL_REWIND_SHIFT)
191 
192 /*
193  * ENABLE (RW)
194  *
195  * Enable
196  * 0: disable
197  * 1: enable
198  */
199 #define SEI_CTRL_ENGINE_CTRL_ENABLE_MASK (0x1U)
200 #define SEI_CTRL_ENGINE_CTRL_ENABLE_SHIFT (0U)
201 #define SEI_CTRL_ENGINE_CTRL_ENABLE_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_ENABLE_SHIFT) & SEI_CTRL_ENGINE_CTRL_ENABLE_MASK)
202 #define SEI_CTRL_ENGINE_CTRL_ENABLE_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_ENABLE_MASK) >> SEI_CTRL_ENGINE_CTRL_ENABLE_SHIFT)
203 
204 /* Bitfield definition for register of struct array CTRL: PTR_CFG */
205 /*
206  * DAT_CDM (RW)
207  *
208  * Select DATA register to receive CDM bit in BiSSC slave mode
209  * 0: ignore
210  * 1: command
211  * 2: data register 2
212  * 3: data register 3
213  * ...
214  * 29:data register 29
215  * 30: value 0 when send, ignore in receive
216  * 31: value1 when send, ignore in receive
217  */
218 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_MASK (0x1F000000UL)
219 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SHIFT (24U)
220 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_MASK)
221 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SHIFT)
222 
223 /*
224  * DAT_BASE (RW)
225  *
226  * Bias for data register access, if calculated index bigger than 32, index will wrap around
227  * 0: real data index
228  * 1: access index is 1 greater than instruction address
229  * 2: access index is 2 greater than instruction address
230  * ...
231  * 31: access index is 31 greater than instruction address
232  */
233 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_MASK (0x1F0000UL)
234 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SHIFT (16U)
235 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_MASK)
236 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SHIFT)
237 
238 /*
239  * POINTER_WDOG (RW)
240  *
241  * Pointer to the instruction that the program starts executing after the instruction timeout. The timeout is WDOG_TIME
242  */
243 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_MASK (0xFF00U)
244 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SHIFT (8U)
245 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_MASK)
246 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SHIFT)
247 
248 /*
249  * POINTER_INIT (RW)
250  *
251  * Initial execute pointer
252  */
253 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_MASK (0xFFU)
254 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SHIFT (0U)
255 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_MASK)
256 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SHIFT)
257 
258 /* Bitfield definition for register of struct array CTRL: WDG_CFG */
259 /*
260  * WDOG_TIME (RW)
261  *
262  * Time out count for each instruction, counter in bit time.
263  */
264 #define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_MASK (0xFFFFU)
265 #define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SHIFT (0U)
266 #define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SHIFT) & SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_MASK)
267 #define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_MASK) >> SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SHIFT)
268 
269 /* Bitfield definition for register of struct array CTRL: EXE_STA */
270 /*
271  * TRIGERED (RO)
272  *
273  * Execution has been triggered
274  * 0: Execution not triggered
275  * 1: Execution triggered
276  */
277 #define SEI_CTRL_ENGINE_EXE_STA_TRIGERED_MASK (0x100000UL)
278 #define SEI_CTRL_ENGINE_EXE_STA_TRIGERED_SHIFT (20U)
279 #define SEI_CTRL_ENGINE_EXE_STA_TRIGERED_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_TRIGERED_MASK) >> SEI_CTRL_ENGINE_EXE_STA_TRIGERED_SHIFT)
280 
281 /*
282  * ARMED (RO)
283  *
284  * Waiting for trigger for execution
285  * 0: Not in waiting status
286  * 1: In waiting status
287  */
288 #define SEI_CTRL_ENGINE_EXE_STA_ARMED_MASK (0x10000UL)
289 #define SEI_CTRL_ENGINE_EXE_STA_ARMED_SHIFT (16U)
290 #define SEI_CTRL_ENGINE_EXE_STA_ARMED_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_ARMED_MASK) >> SEI_CTRL_ENGINE_EXE_STA_ARMED_SHIFT)
291 
292 /*
293  * EXPIRE (RO)
294  *
295  * Watchdog timer expired
296  * 0: Not expired
297  * 1: Expired
298  */
299 #define SEI_CTRL_ENGINE_EXE_STA_EXPIRE_MASK (0x100U)
300 #define SEI_CTRL_ENGINE_EXE_STA_EXPIRE_SHIFT (8U)
301 #define SEI_CTRL_ENGINE_EXE_STA_EXPIRE_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_EXPIRE_MASK) >> SEI_CTRL_ENGINE_EXE_STA_EXPIRE_SHIFT)
302 
303 /*
304  * STALL (RO)
305  *
306  * Program finished
307  * 0: Program is executing
308  * 1: Program finished
309  */
310 #define SEI_CTRL_ENGINE_EXE_STA_STALL_MASK (0x1U)
311 #define SEI_CTRL_ENGINE_EXE_STA_STALL_SHIFT (0U)
312 #define SEI_CTRL_ENGINE_EXE_STA_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_STALL_MASK) >> SEI_CTRL_ENGINE_EXE_STA_STALL_SHIFT)
313 
314 /* Bitfield definition for register of struct array CTRL: EXE_PTR */
315 /*
316  * HALT_CNT (RO)
317  *
318  * Halt count in halt instrution
319  */
320 #define SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_MASK (0x1F000000UL)
321 #define SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_SHIFT (24U)
322 #define SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_MASK) >> SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_SHIFT)
323 
324 /*
325  * BIT_CNT (RO)
326  *
327  * Bit count in send and receive instruction execution
328  */
329 #define SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_MASK (0x1F0000UL)
330 #define SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_SHIFT (16U)
331 #define SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_MASK) >> SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_SHIFT)
332 
333 /*
334  * POINTER (RO)
335  *
336  * Current program pointer
337  */
338 #define SEI_CTRL_ENGINE_EXE_PTR_POINTER_MASK (0xFFU)
339 #define SEI_CTRL_ENGINE_EXE_PTR_POINTER_SHIFT (0U)
340 #define SEI_CTRL_ENGINE_EXE_PTR_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_PTR_POINTER_MASK) >> SEI_CTRL_ENGINE_EXE_PTR_POINTER_SHIFT)
341 
342 /* Bitfield definition for register of struct array CTRL: EXE_INST */
343 /*
344  * INST (RO)
345  *
346  * Current instruction
347  */
348 #define SEI_CTRL_ENGINE_EXE_INST_INST_MASK (0xFFFFFFFFUL)
349 #define SEI_CTRL_ENGINE_EXE_INST_INST_SHIFT (0U)
350 #define SEI_CTRL_ENGINE_EXE_INST_INST_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_INST_INST_MASK) >> SEI_CTRL_ENGINE_EXE_INST_INST_SHIFT)
351 
352 /* Bitfield definition for register of struct array CTRL: WDG_STA */
353 /*
354  * WDOG_CNT (RO)
355  *
356  * Current watch dog counter value
357  */
358 #define SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_MASK (0xFFFFU)
359 #define SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_SHIFT (0U)
360 #define SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_MASK) >> SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_SHIFT)
361 
362 /* Bitfield definition for register of struct array CTRL: CTRL */
363 /*
364  * TRISMP (RW)
365  *
366  * Tipple sampe
367  * 0: sample 1 time for data transition
368  * 1: sample 3 times in receive and result in 2oo3
369  */
370 #define SEI_CTRL_XCVR_CTRL_TRISMP_MASK (0x1000U)
371 #define SEI_CTRL_XCVR_CTRL_TRISMP_SHIFT (12U)
372 #define SEI_CTRL_XCVR_CTRL_TRISMP_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_TRISMP_SHIFT) & SEI_CTRL_XCVR_CTRL_TRISMP_MASK)
373 #define SEI_CTRL_XCVR_CTRL_TRISMP_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_TRISMP_MASK) >> SEI_CTRL_XCVR_CTRL_TRISMP_SHIFT)
374 
375 /*
376  * PAR_CLR (WC)
377  *
378  * Clear parity error, this is a self clear bit
379  * 0: no effect
380  * 1: clear parity error
381  */
382 #define SEI_CTRL_XCVR_CTRL_PAR_CLR_MASK (0x100U)
383 #define SEI_CTRL_XCVR_CTRL_PAR_CLR_SHIFT (8U)
384 #define SEI_CTRL_XCVR_CTRL_PAR_CLR_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_PAR_CLR_SHIFT) & SEI_CTRL_XCVR_CTRL_PAR_CLR_MASK)
385 #define SEI_CTRL_XCVR_CTRL_PAR_CLR_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_PAR_CLR_MASK) >> SEI_CTRL_XCVR_CTRL_PAR_CLR_SHIFT)
386 
387 /*
388  * RESTART (WC)
389  *
390  * Restart transceiver, this is a self clear bit
391  * 0: no effect
392  * 1: reset transceiver
393  */
394 #define SEI_CTRL_XCVR_CTRL_RESTART_MASK (0x10U)
395 #define SEI_CTRL_XCVR_CTRL_RESTART_SHIFT (4U)
396 #define SEI_CTRL_XCVR_CTRL_RESTART_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_RESTART_SHIFT) & SEI_CTRL_XCVR_CTRL_RESTART_MASK)
397 #define SEI_CTRL_XCVR_CTRL_RESTART_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_RESTART_MASK) >> SEI_CTRL_XCVR_CTRL_RESTART_SHIFT)
398 
399 /*
400  * MODE (RW)
401  *
402  * Transceiver mode
403  * 0: synchronous maaster
404  * 1: synchronous slave
405  * 2: asynchronous mode
406  * 3: asynchronous mode
407  */
408 #define SEI_CTRL_XCVR_CTRL_MODE_MASK (0x3U)
409 #define SEI_CTRL_XCVR_CTRL_MODE_SHIFT (0U)
410 #define SEI_CTRL_XCVR_CTRL_MODE_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_MODE_SHIFT) & SEI_CTRL_XCVR_CTRL_MODE_MASK)
411 #define SEI_CTRL_XCVR_CTRL_MODE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_MODE_MASK) >> SEI_CTRL_XCVR_CTRL_MODE_SHIFT)
412 
413 /* Bitfield definition for register of struct array CTRL: TYPE_CFG */
414 /*
415  * WAIT_LEN (RW)
416  *
417  * Number of extra stop bit for asynchronous mode
418  * 0: 1 bit
419  * 1: 2 bit
420  * ...
421  * 255: 256 bit
422  */
423 #define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_MASK (0xFF000000UL)
424 #define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SHIFT (24U)
425 #define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_MASK)
426 #define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SHIFT)
427 
428 /*
429  * DATA_LEN (RW)
430  *
431  * Number of data bit for asynchronous mode
432  * 0: 1 bit
433  * 1: 2 bit
434  * ...
435  * 31: 32 bit
436  */
437 #define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_MASK (0x1F0000UL)
438 #define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SHIFT (16U)
439 #define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_MASK)
440 #define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SHIFT)
441 
442 /*
443  * PAR_POL (RW)
444  *
445  * Polarity of parity for asynchronous mode
446  * 0: even
447  * 1: odd
448  */
449 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_MASK (0x200U)
450 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SHIFT (9U)
451 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_MASK)
452 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SHIFT)
453 
454 /*
455  * PAR_EN (RW)
456  *
457  * enable parity check for asynchronous mode
458  * 0: disable
459  * 1: enable
460  */
461 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_MASK (0x100U)
462 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SHIFT (8U)
463 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_MASK)
464 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SHIFT)
465 
466 /*
467  * DA_IDLEZ (RW)
468  *
469  * Idle state driver of data line
470  * 0: output
471  * 1: high-Z
472  */
473 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_MASK (0x8U)
474 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SHIFT (3U)
475 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_MASK)
476 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SHIFT)
477 
478 /*
479  * CK_IDLEZ (RW)
480  *
481  * Idle state driver of clock line
482  * 0: output
483  * 1: high-Z
484  */
485 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_MASK (0x4U)
486 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SHIFT (2U)
487 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_MASK)
488 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SHIFT)
489 
490 /*
491  * DA_IDLEV (RW)
492  *
493  * Idle state value of data line
494  * 0: data'0'
495  * 1: data'1'
496  */
497 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_MASK (0x2U)
498 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SHIFT (1U)
499 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_MASK)
500 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SHIFT)
501 
502 /*
503  * CK_IDLEV (RW)
504  *
505  * Idle state value of clock line
506  * 0: data'0'
507  * 1: data'1'
508  */
509 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_MASK (0x1U)
510 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SHIFT (0U)
511 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_MASK)
512 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SHIFT)
513 
514 /* Bitfield definition for register of struct array CTRL: BAUD_CFG */
515 /*
516  * SYNC_POINT (RW)
517  *
518  * Baud synchronous time, minmum bit time
519  */
520 #define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_MASK (0xFFFF0000UL)
521 #define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SHIFT (16U)
522 #define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SHIFT) & SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_MASK)
523 #define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_MASK) >> SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SHIFT)
524 
525 /*
526  * BAUD_DIV (RW)
527  *
528  * Baud rate, bit time in system clock cycle
529  */
530 #define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_MASK (0xFFFFU)
531 #define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SHIFT (0U)
532 #define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SHIFT) & SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_MASK)
533 #define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_MASK) >> SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SHIFT)
534 
535 /* Bitfield definition for register of struct array CTRL: DATA_CFG */
536 /*
537  * TXD_POINT (RW)
538  *
539  * data transmit point in system clcok cycle
540  */
541 #define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_MASK (0xFFFF0000UL)
542 #define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SHIFT (16U)
543 #define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SHIFT) & SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_MASK)
544 #define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_MASK) >> SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SHIFT)
545 
546 /*
547  * RXD_POINT (RW)
548  *
549  * data receive point in system clcok cycle
550  */
551 #define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_MASK (0xFFFFU)
552 #define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SHIFT (0U)
553 #define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SHIFT) & SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_MASK)
554 #define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_MASK) >> SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SHIFT)
555 
556 /* Bitfield definition for register of struct array CTRL: CLK_CFG */
557 /*
558  * CK1_POINT (RW)
559  *
560  * clock point 1 in system clcok cycle
561  */
562 #define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_MASK (0xFFFF0000UL)
563 #define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SHIFT (16U)
564 #define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SHIFT) & SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_MASK)
565 #define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_MASK) >> SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SHIFT)
566 
567 /*
568  * CK0_POINT (RW)
569  *
570  * clock point 0 in system clcok cycle
571  */
572 #define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_MASK (0xFFFFU)
573 #define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SHIFT (0U)
574 #define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SHIFT) & SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_MASK)
575 #define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_MASK) >> SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SHIFT)
576 
577 /* Bitfield definition for register of struct array CTRL: PIN */
578 /*
579  * OE_CK (RO)
580  *
581  * CK drive state
582  * 0: input
583  * 1: output
584  */
585 #define SEI_CTRL_XCVR_PIN_OE_CK_MASK (0x4000000UL)
586 #define SEI_CTRL_XCVR_PIN_OE_CK_SHIFT (26U)
587 #define SEI_CTRL_XCVR_PIN_OE_CK_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_CK_MASK) >> SEI_CTRL_XCVR_PIN_OE_CK_SHIFT)
588 
589 /*
590  * DI_CK (RO)
591  *
592  * CK state
593  * 0: data 0
594  * 1: data 1
595  */
596 #define SEI_CTRL_XCVR_PIN_DI_CK_MASK (0x2000000UL)
597 #define SEI_CTRL_XCVR_PIN_DI_CK_SHIFT (25U)
598 #define SEI_CTRL_XCVR_PIN_DI_CK_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_CK_MASK) >> SEI_CTRL_XCVR_PIN_DI_CK_SHIFT)
599 
600 /*
601  * DO_CK (RO)
602  *
603  * CK output
604  * 0: data 0
605  * 1: data 1
606  */
607 #define SEI_CTRL_XCVR_PIN_DO_CK_MASK (0x1000000UL)
608 #define SEI_CTRL_XCVR_PIN_DO_CK_SHIFT (24U)
609 #define SEI_CTRL_XCVR_PIN_DO_CK_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_CK_MASK) >> SEI_CTRL_XCVR_PIN_DO_CK_SHIFT)
610 
611 /*
612  * OE_RX (RO)
613  *
614  * RX drive state
615  * 0: input
616  * 1: output
617  */
618 #define SEI_CTRL_XCVR_PIN_OE_RX_MASK (0x40000UL)
619 #define SEI_CTRL_XCVR_PIN_OE_RX_SHIFT (18U)
620 #define SEI_CTRL_XCVR_PIN_OE_RX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_RX_MASK) >> SEI_CTRL_XCVR_PIN_OE_RX_SHIFT)
621 
622 /*
623  * DI_RX (RO)
624  *
625  * RX state
626  * 0: data 0
627  * 1: data 1
628  */
629 #define SEI_CTRL_XCVR_PIN_DI_RX_MASK (0x20000UL)
630 #define SEI_CTRL_XCVR_PIN_DI_RX_SHIFT (17U)
631 #define SEI_CTRL_XCVR_PIN_DI_RX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_RX_MASK) >> SEI_CTRL_XCVR_PIN_DI_RX_SHIFT)
632 
633 /*
634  * DO_RX (RO)
635  *
636  * RX output
637  * 0: data 0
638  * 1: data 1
639  */
640 #define SEI_CTRL_XCVR_PIN_DO_RX_MASK (0x10000UL)
641 #define SEI_CTRL_XCVR_PIN_DO_RX_SHIFT (16U)
642 #define SEI_CTRL_XCVR_PIN_DO_RX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_RX_MASK) >> SEI_CTRL_XCVR_PIN_DO_RX_SHIFT)
643 
644 /*
645  * OE_DE (RO)
646  *
647  * DE drive state
648  * 0: input
649  * 1: output
650  */
651 #define SEI_CTRL_XCVR_PIN_OE_DE_MASK (0x400U)
652 #define SEI_CTRL_XCVR_PIN_OE_DE_SHIFT (10U)
653 #define SEI_CTRL_XCVR_PIN_OE_DE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_DE_MASK) >> SEI_CTRL_XCVR_PIN_OE_DE_SHIFT)
654 
655 /*
656  * DI_DE (RO)
657  *
658  * DE state
659  * 0: data 0
660  * 1: data 1
661  */
662 #define SEI_CTRL_XCVR_PIN_DI_DE_MASK (0x200U)
663 #define SEI_CTRL_XCVR_PIN_DI_DE_SHIFT (9U)
664 #define SEI_CTRL_XCVR_PIN_DI_DE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_DE_MASK) >> SEI_CTRL_XCVR_PIN_DI_DE_SHIFT)
665 
666 /*
667  * DO_DE (RO)
668  *
669  * DE output
670  * 0: data 0
671  * 1: data 1
672  */
673 #define SEI_CTRL_XCVR_PIN_DO_DE_MASK (0x100U)
674 #define SEI_CTRL_XCVR_PIN_DO_DE_SHIFT (8U)
675 #define SEI_CTRL_XCVR_PIN_DO_DE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_DE_MASK) >> SEI_CTRL_XCVR_PIN_DO_DE_SHIFT)
676 
677 /*
678  * OE_TX (RO)
679  *
680  * TX drive state
681  * 0: input
682  * 1: output
683  */
684 #define SEI_CTRL_XCVR_PIN_OE_TX_MASK (0x4U)
685 #define SEI_CTRL_XCVR_PIN_OE_TX_SHIFT (2U)
686 #define SEI_CTRL_XCVR_PIN_OE_TX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_TX_MASK) >> SEI_CTRL_XCVR_PIN_OE_TX_SHIFT)
687 
688 /*
689  * DI_TX (RO)
690  *
691  * TX state
692  * 0: data 0
693  * 1: data 1
694  */
695 #define SEI_CTRL_XCVR_PIN_DI_TX_MASK (0x2U)
696 #define SEI_CTRL_XCVR_PIN_DI_TX_SHIFT (1U)
697 #define SEI_CTRL_XCVR_PIN_DI_TX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_TX_MASK) >> SEI_CTRL_XCVR_PIN_DI_TX_SHIFT)
698 
699 /*
700  * DO_TX (RO)
701  *
702  * TX output
703  * 0: data 0
704  * 1: data 1
705  */
706 #define SEI_CTRL_XCVR_PIN_DO_TX_MASK (0x1U)
707 #define SEI_CTRL_XCVR_PIN_DO_TX_SHIFT (0U)
708 #define SEI_CTRL_XCVR_PIN_DO_TX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_TX_MASK) >> SEI_CTRL_XCVR_PIN_DO_TX_SHIFT)
709 
710 /* Bitfield definition for register of struct array CTRL: STATE */
711 /*
712  * RECV_STATE (RO)
713  *
714  * FSM of asynchronous receive
715  */
716 #define SEI_CTRL_XCVR_STATE_RECV_STATE_MASK (0x7000000UL)
717 #define SEI_CTRL_XCVR_STATE_RECV_STATE_SHIFT (24U)
718 #define SEI_CTRL_XCVR_STATE_RECV_STATE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_STATE_RECV_STATE_MASK) >> SEI_CTRL_XCVR_STATE_RECV_STATE_SHIFT)
719 
720 /*
721  * SEND_STATE (RO)
722  *
723  * FSM of asynchronous transmit
724  */
725 #define SEI_CTRL_XCVR_STATE_SEND_STATE_MASK (0x70000UL)
726 #define SEI_CTRL_XCVR_STATE_SEND_STATE_SHIFT (16U)
727 #define SEI_CTRL_XCVR_STATE_SEND_STATE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_STATE_SEND_STATE_MASK) >> SEI_CTRL_XCVR_STATE_SEND_STATE_SHIFT)
728 
729 /* Bitfield definition for register of struct array CTRL: IN_CFG */
730 /*
731  * REWIND_EN (RW)
732  *
733  * enable rewind cmd register by LATCH
734  */
735 #define SEI_CTRL_TRG_IN_CFG_REWIND_EN_MASK (0x80000000UL)
736 #define SEI_CTRL_TRG_IN_CFG_REWIND_EN_SHIFT (31U)
737 #define SEI_CTRL_TRG_IN_CFG_REWIND_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_REWIND_EN_SHIFT) & SEI_CTRL_TRG_IN_CFG_REWIND_EN_MASK)
738 #define SEI_CTRL_TRG_IN_CFG_REWIND_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_REWIND_EN_MASK) >> SEI_CTRL_TRG_IN_CFG_REWIND_EN_SHIFT)
739 
740 /*
741  * REWIND_SEL (RW)
742  *
743  * select one LATCH to rewind CMD register
744  * 0:LATCH[0]
745  * 1:LATCH[1]
746  * 2:LATCH[2]
747  * 3:LATCH[3]
748  */
749 #define SEI_CTRL_TRG_IN_CFG_REWIND_SEL_MASK (0x3000000UL)
750 #define SEI_CTRL_TRG_IN_CFG_REWIND_SEL_SHIFT (24U)
751 #define SEI_CTRL_TRG_IN_CFG_REWIND_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_REWIND_SEL_SHIFT) & SEI_CTRL_TRG_IN_CFG_REWIND_SEL_MASK)
752 #define SEI_CTRL_TRG_IN_CFG_REWIND_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_REWIND_SEL_MASK) >> SEI_CTRL_TRG_IN_CFG_REWIND_SEL_SHIFT)
753 
754 /*
755  * PRD_EN (RW)
756  *
757  * Enable period trigger (tigger 2)
758  * 0: periodical trigger disabled
759  * 1: periodical trigger enabled
760  */
761 #define SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK (0x800000UL)
762 #define SEI_CTRL_TRG_IN_CFG_PRD_EN_SHIFT (23U)
763 #define SEI_CTRL_TRG_IN_CFG_PRD_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_PRD_EN_SHIFT) & SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK)
764 #define SEI_CTRL_TRG_IN_CFG_PRD_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK) >> SEI_CTRL_TRG_IN_CFG_PRD_EN_SHIFT)
765 
766 /*
767  * SYNC_SEL (RW)
768  *
769  * Synchronize sigal selection (tigger 2)
770  * 0: trigger in 0
771  * 1: trigger in 1
772  * ...
773  * 7: trigger in 7
774  */
775 #define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_MASK (0x70000UL)
776 #define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SHIFT (16U)
777 #define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SHIFT) & SEI_CTRL_TRG_IN_CFG_SYNC_SEL_MASK)
778 #define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_SYNC_SEL_MASK) >> SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SHIFT)
779 
780 /*
781  * IN1_EN (RW)
782  *
783  * Enable trigger 1
784  * 0: disable trigger 1
785  * 1: enable trigger 1
786  */
787 #define SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK (0x8000U)
788 #define SEI_CTRL_TRG_IN_CFG_IN1_EN_SHIFT (15U)
789 #define SEI_CTRL_TRG_IN_CFG_IN1_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN1_EN_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK)
790 #define SEI_CTRL_TRG_IN_CFG_IN1_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK) >> SEI_CTRL_TRG_IN_CFG_IN1_EN_SHIFT)
791 
792 /*
793  * IN1_SEL (RW)
794  *
795  * Trigger 1 sigal selection
796  * 0: trigger in 0
797  * 1: trigger in 1
798  * ...
799  * 7: trigger in 7
800  */
801 #define SEI_CTRL_TRG_IN_CFG_IN1_SEL_MASK (0x700U)
802 #define SEI_CTRL_TRG_IN_CFG_IN1_SEL_SHIFT (8U)
803 #define SEI_CTRL_TRG_IN_CFG_IN1_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN1_SEL_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN1_SEL_MASK)
804 #define SEI_CTRL_TRG_IN_CFG_IN1_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN1_SEL_MASK) >> SEI_CTRL_TRG_IN_CFG_IN1_SEL_SHIFT)
805 
806 /*
807  * IN0_EN (RW)
808  *
809  * Enable trigger 0
810  * 0: disable trigger 1
811  * 1: enable trigger 1
812  */
813 #define SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK (0x80U)
814 #define SEI_CTRL_TRG_IN_CFG_IN0_EN_SHIFT (7U)
815 #define SEI_CTRL_TRG_IN_CFG_IN0_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN0_EN_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK)
816 #define SEI_CTRL_TRG_IN_CFG_IN0_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK) >> SEI_CTRL_TRG_IN_CFG_IN0_EN_SHIFT)
817 
818 /*
819  * IN0_SEL (RW)
820  *
821  * Trigger 0 sigal selection
822  * 0: trigger in 0
823  * 1: trigger in 1
824  * ...
825  * 7: trigger in 7
826  */
827 #define SEI_CTRL_TRG_IN_CFG_IN0_SEL_MASK (0x7U)
828 #define SEI_CTRL_TRG_IN_CFG_IN0_SEL_SHIFT (0U)
829 #define SEI_CTRL_TRG_IN_CFG_IN0_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN0_SEL_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN0_SEL_MASK)
830 #define SEI_CTRL_TRG_IN_CFG_IN0_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN0_SEL_MASK) >> SEI_CTRL_TRG_IN_CFG_IN0_SEL_SHIFT)
831 
832 /* Bitfield definition for register of struct array CTRL: SW */
833 /*
834  * SOFT (WC)
835  *
836  * Software trigger (tigger 3). this bit is self-clear
837  * 0: trigger source disabled
838  * 1: trigger source enabled
839  */
840 #define SEI_CTRL_TRG_SW_SOFT_MASK (0x1U)
841 #define SEI_CTRL_TRG_SW_SOFT_SHIFT (0U)
842 #define SEI_CTRL_TRG_SW_SOFT_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_SW_SOFT_SHIFT) & SEI_CTRL_TRG_SW_SOFT_MASK)
843 #define SEI_CTRL_TRG_SW_SOFT_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_SW_SOFT_MASK) >> SEI_CTRL_TRG_SW_SOFT_SHIFT)
844 
845 /* Bitfield definition for register of struct array CTRL: PRD_CFG */
846 /*
847  * ARMING (RW)
848  *
849  * Wait for trigger synchronous before trigger
850  * 0: Trigger directly
851  * 1: Wait trigger source before period trigger
852  */
853 #define SEI_CTRL_TRG_PRD_CFG_ARMING_MASK (0x10000UL)
854 #define SEI_CTRL_TRG_PRD_CFG_ARMING_SHIFT (16U)
855 #define SEI_CTRL_TRG_PRD_CFG_ARMING_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_PRD_CFG_ARMING_SHIFT) & SEI_CTRL_TRG_PRD_CFG_ARMING_MASK)
856 #define SEI_CTRL_TRG_PRD_CFG_ARMING_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_CFG_ARMING_MASK) >> SEI_CTRL_TRG_PRD_CFG_ARMING_SHIFT)
857 
858 /*
859  * SYNC (RW)
860  *
861  * Synchronous
862  * 0: Not synchronous
863  * 1: Synchronous every trigger source
864  */
865 #define SEI_CTRL_TRG_PRD_CFG_SYNC_MASK (0x1U)
866 #define SEI_CTRL_TRG_PRD_CFG_SYNC_SHIFT (0U)
867 #define SEI_CTRL_TRG_PRD_CFG_SYNC_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_PRD_CFG_SYNC_SHIFT) & SEI_CTRL_TRG_PRD_CFG_SYNC_MASK)
868 #define SEI_CTRL_TRG_PRD_CFG_SYNC_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_CFG_SYNC_MASK) >> SEI_CTRL_TRG_PRD_CFG_SYNC_SHIFT)
869 
870 /* Bitfield definition for register of struct array CTRL: PRD */
871 /*
872  * PERIOD (RW)
873  *
874  * Trigger period
875  */
876 #define SEI_CTRL_TRG_PRD_PERIOD_MASK (0xFFFFFFFFUL)
877 #define SEI_CTRL_TRG_PRD_PERIOD_SHIFT (0U)
878 #define SEI_CTRL_TRG_PRD_PERIOD_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_PRD_PERIOD_SHIFT) & SEI_CTRL_TRG_PRD_PERIOD_MASK)
879 #define SEI_CTRL_TRG_PRD_PERIOD_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_PERIOD_MASK) >> SEI_CTRL_TRG_PRD_PERIOD_SHIFT)
880 
881 /* Bitfield definition for register of struct array CTRL: OUT_CFG */
882 /*
883  * OUT3_EN (RW)
884  *
885  * Enable trigger 3
886  * 0: disable trigger 3
887  * 1: enable trigger 3
888  */
889 #define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_MASK (0x80000000UL)
890 #define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SHIFT (31U)
891 #define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT3_EN_MASK)
892 #define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT3_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SHIFT)
893 
894 /*
895  * OUT3_SEL (RW)
896  *
897  * Trigger 3 sigal selection
898  * 0: trigger out 0
899  * 1: trigger out 1
900  * ...
901  * 7: trigger out 7
902  */
903 #define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_MASK (0x7000000UL)
904 #define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SHIFT (24U)
905 #define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_MASK)
906 #define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SHIFT)
907 
908 /*
909  * OUT2_EN (RW)
910  *
911  * Enable trigger 2
912  * 0: disable trigger 2
913  * 1: enable trigger 2
914  */
915 #define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_MASK (0x800000UL)
916 #define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SHIFT (23U)
917 #define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT2_EN_MASK)
918 #define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT2_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SHIFT)
919 
920 /*
921  * OUT2_SEL (RW)
922  *
923  * Trigger 2 sigal selection
924  * 0: trigger out 0
925  * 1: trigger out 1
926  * ...
927  * 7: trigger out 7
928  */
929 #define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_MASK (0x70000UL)
930 #define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SHIFT (16U)
931 #define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_MASK)
932 #define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SHIFT)
933 
934 /*
935  * OUT1_EN (RW)
936  *
937  * Enable trigger 1
938  * 0: disable trigger 1
939  * 1: enable trigger 1
940  */
941 #define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_MASK (0x8000U)
942 #define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SHIFT (15U)
943 #define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT1_EN_MASK)
944 #define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT1_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SHIFT)
945 
946 /*
947  * OUT1_SEL (RW)
948  *
949  * Trigger 1 sigal selection
950  * 0: trigger out 0
951  * 1: trigger out 1
952  * ...
953  * 7: trigger out 7
954  */
955 #define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_MASK (0x700U)
956 #define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SHIFT (8U)
957 #define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_MASK)
958 #define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SHIFT)
959 
960 /*
961  * OUT0_EN (RW)
962  *
963  * Enable trigger 0
964  * 0: disable trigger 1
965  * 1: enable trigger 1
966  */
967 #define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_MASK (0x80U)
968 #define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SHIFT (7U)
969 #define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT0_EN_MASK)
970 #define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT0_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SHIFT)
971 
972 /*
973  * OUT0_SEL (RW)
974  *
975  * Trigger 0 sigal selection
976  * 0: trigger out 0
977  * 1: trigger out 1
978  * ...
979  * 7: trigger out 7
980  */
981 #define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_MASK (0x7U)
982 #define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SHIFT (0U)
983 #define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_MASK)
984 #define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SHIFT)
985 
986 /* Bitfield definition for register of struct array CTRL: PRD_STS */
987 /*
988  * TRIGERED (RO)
989  *
990  * Period has been triggered
991  * 0: Not triggered
992  * 1: Triggered
993  */
994 #define SEI_CTRL_TRG_PRD_STS_TRIGERED_MASK (0x100000UL)
995 #define SEI_CTRL_TRG_PRD_STS_TRIGERED_SHIFT (20U)
996 #define SEI_CTRL_TRG_PRD_STS_TRIGERED_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_STS_TRIGERED_MASK) >> SEI_CTRL_TRG_PRD_STS_TRIGERED_SHIFT)
997 
998 /*
999  * ARMED (RO)
1000  *
1001  * Waiting for trigger
1002  * 0: Not in waiting status
1003  * 1: In waiting status
1004  */
1005 #define SEI_CTRL_TRG_PRD_STS_ARMED_MASK (0x10000UL)
1006 #define SEI_CTRL_TRG_PRD_STS_ARMED_SHIFT (16U)
1007 #define SEI_CTRL_TRG_PRD_STS_ARMED_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_STS_ARMED_MASK) >> SEI_CTRL_TRG_PRD_STS_ARMED_SHIFT)
1008 
1009 /* Bitfield definition for register of struct array CTRL: PRD_CNT */
1010 /*
1011  * PERIOD_CNT (RO)
1012  *
1013  * Trigger period counter
1014  */
1015 #define SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_MASK (0xFFFFFFFFUL)
1016 #define SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_SHIFT (0U)
1017 #define SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_MASK) >> SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_SHIFT)
1018 
1019 /* Bitfield definition for register of struct array CTRL: 0 */
1020 /*
1021  * CMD_TRIGGER0 (RW)
1022  *
1023  * Trigger command
1024  */
1025 #define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_MASK (0xFFFFFFFFUL)
1026 #define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SHIFT (0U)
1027 #define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SHIFT) & SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_MASK)
1028 #define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_MASK) >> SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SHIFT)
1029 
1030 /* Bitfield definition for register of struct array CTRL: 0 */
1031 /*
1032  * TRIGGER0_TIME (RO)
1033  *
1034  * Trigger time
1035  */
1036 #define SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_MASK (0xFFFFFFFFUL)
1037 #define SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_SHIFT (0U)
1038 #define SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_MASK) >> SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_SHIFT)
1039 
1040 /* Bitfield definition for register of struct array CTRL: MODE */
1041 /*
1042  * WLEN (RW)
1043  *
1044  * word length
1045  * 0: 1 bit
1046  * 1: 2 bit
1047  * ...
1048  * 31: 32 bit
1049  */
1050 #define SEI_CTRL_CMD_MODE_WLEN_MASK (0x1F0000UL)
1051 #define SEI_CTRL_CMD_MODE_WLEN_SHIFT (16U)
1052 #define SEI_CTRL_CMD_MODE_WLEN_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_WLEN_SHIFT) & SEI_CTRL_CMD_MODE_WLEN_MASK)
1053 #define SEI_CTRL_CMD_MODE_WLEN_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_WLEN_MASK) >> SEI_CTRL_CMD_MODE_WLEN_SHIFT)
1054 
1055 /*
1056  * WORDER (RW)
1057  *
1058  * word order
1059  * 0: sample as bit order
1060  * 1: different from bit order
1061  */
1062 #define SEI_CTRL_CMD_MODE_WORDER_MASK (0x800U)
1063 #define SEI_CTRL_CMD_MODE_WORDER_SHIFT (11U)
1064 #define SEI_CTRL_CMD_MODE_WORDER_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_WORDER_SHIFT) & SEI_CTRL_CMD_MODE_WORDER_MASK)
1065 #define SEI_CTRL_CMD_MODE_WORDER_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_WORDER_MASK) >> SEI_CTRL_CMD_MODE_WORDER_SHIFT)
1066 
1067 /*
1068  * BORDER (RW)
1069  *
1070  * bit order
1071  * 0: LSB first
1072  * 1: MSB first
1073  */
1074 #define SEI_CTRL_CMD_MODE_BORDER_MASK (0x400U)
1075 #define SEI_CTRL_CMD_MODE_BORDER_SHIFT (10U)
1076 #define SEI_CTRL_CMD_MODE_BORDER_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_BORDER_SHIFT) & SEI_CTRL_CMD_MODE_BORDER_MASK)
1077 #define SEI_CTRL_CMD_MODE_BORDER_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_BORDER_MASK) >> SEI_CTRL_CMD_MODE_BORDER_SHIFT)
1078 
1079 /*
1080  * SIGNED (RW)
1081  *
1082  * Signed
1083  * 0: unsigned value
1084  * 1: signed value
1085  */
1086 #define SEI_CTRL_CMD_MODE_SIGNED_MASK (0x200U)
1087 #define SEI_CTRL_CMD_MODE_SIGNED_SHIFT (9U)
1088 #define SEI_CTRL_CMD_MODE_SIGNED_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_SIGNED_SHIFT) & SEI_CTRL_CMD_MODE_SIGNED_MASK)
1089 #define SEI_CTRL_CMD_MODE_SIGNED_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_SIGNED_MASK) >> SEI_CTRL_CMD_MODE_SIGNED_SHIFT)
1090 
1091 /*
1092  * REWIND (WC)
1093  *
1094  * Write 1 to rewind read/write pointer, this is a self clear bit
1095  */
1096 #define SEI_CTRL_CMD_MODE_REWIND_MASK (0x100U)
1097 #define SEI_CTRL_CMD_MODE_REWIND_SHIFT (8U)
1098 #define SEI_CTRL_CMD_MODE_REWIND_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_REWIND_SHIFT) & SEI_CTRL_CMD_MODE_REWIND_MASK)
1099 #define SEI_CTRL_CMD_MODE_REWIND_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_REWIND_MASK) >> SEI_CTRL_CMD_MODE_REWIND_SHIFT)
1100 
1101 /*
1102  * MODE (RW)
1103  *
1104  * Data mode(CMD register only support data mode)
1105  * 0: data mode
1106  * 1: check mode
1107  * 2: CRC mode
1108  */
1109 #define SEI_CTRL_CMD_MODE_MODE_MASK (0x3U)
1110 #define SEI_CTRL_CMD_MODE_MODE_SHIFT (0U)
1111 #define SEI_CTRL_CMD_MODE_MODE_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_MODE_SHIFT) & SEI_CTRL_CMD_MODE_MODE_MASK)
1112 #define SEI_CTRL_CMD_MODE_MODE_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_MODE_MASK) >> SEI_CTRL_CMD_MODE_MODE_SHIFT)
1113 
1114 /* Bitfield definition for register of struct array CTRL: IDX */
1115 /*
1116  * LAST_BIT (RW)
1117  *
1118  * Last bit index for tranceive
1119  */
1120 #define SEI_CTRL_CMD_IDX_LAST_BIT_MASK (0x1F000000UL)
1121 #define SEI_CTRL_CMD_IDX_LAST_BIT_SHIFT (24U)
1122 #define SEI_CTRL_CMD_IDX_LAST_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_LAST_BIT_SHIFT) & SEI_CTRL_CMD_IDX_LAST_BIT_MASK)
1123 #define SEI_CTRL_CMD_IDX_LAST_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_LAST_BIT_MASK) >> SEI_CTRL_CMD_IDX_LAST_BIT_SHIFT)
1124 
1125 /*
1126  * FIRST_BIT (RW)
1127  *
1128  * First bit index for tranceive
1129  */
1130 #define SEI_CTRL_CMD_IDX_FIRST_BIT_MASK (0x1F0000UL)
1131 #define SEI_CTRL_CMD_IDX_FIRST_BIT_SHIFT (16U)
1132 #define SEI_CTRL_CMD_IDX_FIRST_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_FIRST_BIT_SHIFT) & SEI_CTRL_CMD_IDX_FIRST_BIT_MASK)
1133 #define SEI_CTRL_CMD_IDX_FIRST_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_FIRST_BIT_MASK) >> SEI_CTRL_CMD_IDX_FIRST_BIT_SHIFT)
1134 
1135 /*
1136  * MAX_BIT (RW)
1137  *
1138  * Highest bit index
1139  */
1140 #define SEI_CTRL_CMD_IDX_MAX_BIT_MASK (0x1F00U)
1141 #define SEI_CTRL_CMD_IDX_MAX_BIT_SHIFT (8U)
1142 #define SEI_CTRL_CMD_IDX_MAX_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_MAX_BIT_SHIFT) & SEI_CTRL_CMD_IDX_MAX_BIT_MASK)
1143 #define SEI_CTRL_CMD_IDX_MAX_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_MAX_BIT_MASK) >> SEI_CTRL_CMD_IDX_MAX_BIT_SHIFT)
1144 
1145 /*
1146  * MIN_BIT (RW)
1147  *
1148  * Lowest bit index
1149  */
1150 #define SEI_CTRL_CMD_IDX_MIN_BIT_MASK (0x1FU)
1151 #define SEI_CTRL_CMD_IDX_MIN_BIT_SHIFT (0U)
1152 #define SEI_CTRL_CMD_IDX_MIN_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_MIN_BIT_SHIFT) & SEI_CTRL_CMD_IDX_MIN_BIT_MASK)
1153 #define SEI_CTRL_CMD_IDX_MIN_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_MIN_BIT_MASK) >> SEI_CTRL_CMD_IDX_MIN_BIT_SHIFT)
1154 
1155 /* Bitfield definition for register of struct array CTRL: CMD */
1156 /*
1157  * DATA (RW)
1158  *
1159  * DATA
1160  */
1161 #define SEI_CTRL_CMD_CMD_DATA_MASK (0xFFFFFFFFUL)
1162 #define SEI_CTRL_CMD_CMD_DATA_SHIFT (0U)
1163 #define SEI_CTRL_CMD_CMD_DATA_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_CMD_DATA_SHIFT) & SEI_CTRL_CMD_CMD_DATA_MASK)
1164 #define SEI_CTRL_CMD_CMD_DATA_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_CMD_DATA_MASK) >> SEI_CTRL_CMD_CMD_DATA_SHIFT)
1165 
1166 /* Bitfield definition for register of struct array CTRL: SET */
1167 /*
1168  * DATA_SET (RW)
1169  *
1170  * DATA bit set
1171  */
1172 #define SEI_CTRL_CMD_SET_DATA_SET_MASK (0xFFFFFFFFUL)
1173 #define SEI_CTRL_CMD_SET_DATA_SET_SHIFT (0U)
1174 #define SEI_CTRL_CMD_SET_DATA_SET_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_SET_DATA_SET_SHIFT) & SEI_CTRL_CMD_SET_DATA_SET_MASK)
1175 #define SEI_CTRL_CMD_SET_DATA_SET_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_SET_DATA_SET_MASK) >> SEI_CTRL_CMD_SET_DATA_SET_SHIFT)
1176 
1177 /* Bitfield definition for register of struct array CTRL: CLR */
1178 /*
1179  * DATA_CLR (RW)
1180  *
1181  * DATA bit clear
1182  */
1183 #define SEI_CTRL_CMD_CLR_DATA_CLR_MASK (0xFFFFFFFFUL)
1184 #define SEI_CTRL_CMD_CLR_DATA_CLR_SHIFT (0U)
1185 #define SEI_CTRL_CMD_CLR_DATA_CLR_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_CLR_DATA_CLR_SHIFT) & SEI_CTRL_CMD_CLR_DATA_CLR_MASK)
1186 #define SEI_CTRL_CMD_CLR_DATA_CLR_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_CLR_DATA_CLR_MASK) >> SEI_CTRL_CMD_CLR_DATA_CLR_SHIFT)
1187 
1188 /* Bitfield definition for register of struct array CTRL: INV */
1189 /*
1190  * DATA_TGL (RW)
1191  *
1192  * DATA bit toggle
1193  */
1194 #define SEI_CTRL_CMD_INV_DATA_TGL_MASK (0xFFFFFFFFUL)
1195 #define SEI_CTRL_CMD_INV_DATA_TGL_SHIFT (0U)
1196 #define SEI_CTRL_CMD_INV_DATA_TGL_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_INV_DATA_TGL_SHIFT) & SEI_CTRL_CMD_INV_DATA_TGL_MASK)
1197 #define SEI_CTRL_CMD_INV_DATA_TGL_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_INV_DATA_TGL_MASK) >> SEI_CTRL_CMD_INV_DATA_TGL_SHIFT)
1198 
1199 /* Bitfield definition for register of struct array CTRL: IN */
1200 /*
1201  * DATA_IN (RO)
1202  *
1203  * Commad input
1204  */
1205 #define SEI_CTRL_CMD_IN_DATA_IN_MASK (0xFFFFFFFFUL)
1206 #define SEI_CTRL_CMD_IN_DATA_IN_SHIFT (0U)
1207 #define SEI_CTRL_CMD_IN_DATA_IN_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IN_DATA_IN_MASK) >> SEI_CTRL_CMD_IN_DATA_IN_SHIFT)
1208 
1209 /* Bitfield definition for register of struct array CTRL: OUT */
1210 /*
1211  * DATA_OUT (RO)
1212  *
1213  * Command output
1214  */
1215 #define SEI_CTRL_CMD_OUT_DATA_OUT_MASK (0xFFFFFFFFUL)
1216 #define SEI_CTRL_CMD_OUT_DATA_OUT_SHIFT (0U)
1217 #define SEI_CTRL_CMD_OUT_DATA_OUT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_OUT_DATA_OUT_MASK) >> SEI_CTRL_CMD_OUT_DATA_OUT_SHIFT)
1218 
1219 /* Bitfield definition for register of struct array CTRL: STS */
1220 /*
1221  * WORD_IDX (RO)
1222  *
1223  * Word index
1224  */
1225 #define SEI_CTRL_CMD_STS_WORD_IDX_MASK (0x1F0000UL)
1226 #define SEI_CTRL_CMD_STS_WORD_IDX_SHIFT (16U)
1227 #define SEI_CTRL_CMD_STS_WORD_IDX_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_STS_WORD_IDX_MASK) >> SEI_CTRL_CMD_STS_WORD_IDX_SHIFT)
1228 
1229 /*
1230  * WORD_CNT (RO)
1231  *
1232  * Word counter
1233  */
1234 #define SEI_CTRL_CMD_STS_WORD_CNT_MASK (0x1F00U)
1235 #define SEI_CTRL_CMD_STS_WORD_CNT_SHIFT (8U)
1236 #define SEI_CTRL_CMD_STS_WORD_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_STS_WORD_CNT_MASK) >> SEI_CTRL_CMD_STS_WORD_CNT_SHIFT)
1237 
1238 /*
1239  * BIT_IDX (RO)
1240  *
1241  * Bit index
1242  */
1243 #define SEI_CTRL_CMD_STS_BIT_IDX_MASK (0x1FU)
1244 #define SEI_CTRL_CMD_STS_BIT_IDX_SHIFT (0U)
1245 #define SEI_CTRL_CMD_STS_BIT_IDX_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_STS_BIT_IDX_MASK) >> SEI_CTRL_CMD_STS_BIT_IDX_SHIFT)
1246 
1247 /* Bitfield definition for register of struct array CTRL: MIN */
1248 /*
1249  * CMD_MIN (RW)
1250  *
1251  * minimum command value
1252  */
1253 #define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_MASK (0xFFFFFFFFUL)
1254 #define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SHIFT (0U)
1255 #define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SHIFT) & SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_MASK)
1256 #define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_MASK) >> SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SHIFT)
1257 
1258 /* Bitfield definition for register of struct array CTRL: MAX */
1259 /*
1260  * CMD_MAX (RW)
1261  *
1262  * maximum command value
1263  */
1264 #define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_MASK (0xFFFFFFFFUL)
1265 #define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SHIFT (0U)
1266 #define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SHIFT) & SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_MASK)
1267 #define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_MASK) >> SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SHIFT)
1268 
1269 /* Bitfield definition for register of struct array CTRL: MSK */
1270 /*
1271  * CMD_MASK (RW)
1272  *
1273  * compare mask
1274  */
1275 #define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_MASK (0xFFFFFFFFUL)
1276 #define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SHIFT (0U)
1277 #define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SHIFT) & SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_MASK)
1278 #define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_MASK) >> SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SHIFT)
1279 
1280 /* Bitfield definition for register of struct array CTRL: PTA */
1281 /*
1282  * PTR3 (RW)
1283  *
1284  * pointer3
1285  */
1286 #define SEI_CTRL_CMD_TABLE_PTA_PTR3_MASK (0xFF000000UL)
1287 #define SEI_CTRL_CMD_TABLE_PTA_PTR3_SHIFT (24U)
1288 #define SEI_CTRL_CMD_TABLE_PTA_PTR3_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR3_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR3_MASK)
1289 #define SEI_CTRL_CMD_TABLE_PTA_PTR3_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR3_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR3_SHIFT)
1290 
1291 /*
1292  * PTR2 (RW)
1293  *
1294  * pointer2
1295  */
1296 #define SEI_CTRL_CMD_TABLE_PTA_PTR2_MASK (0xFF0000UL)
1297 #define SEI_CTRL_CMD_TABLE_PTA_PTR2_SHIFT (16U)
1298 #define SEI_CTRL_CMD_TABLE_PTA_PTR2_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR2_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR2_MASK)
1299 #define SEI_CTRL_CMD_TABLE_PTA_PTR2_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR2_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR2_SHIFT)
1300 
1301 /*
1302  * PTR1 (RW)
1303  *
1304  * pointer1
1305  */
1306 #define SEI_CTRL_CMD_TABLE_PTA_PTR1_MASK (0xFF00U)
1307 #define SEI_CTRL_CMD_TABLE_PTA_PTR1_SHIFT (8U)
1308 #define SEI_CTRL_CMD_TABLE_PTA_PTR1_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR1_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR1_MASK)
1309 #define SEI_CTRL_CMD_TABLE_PTA_PTR1_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR1_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR1_SHIFT)
1310 
1311 /*
1312  * PTR0 (RW)
1313  *
1314  * pointer0
1315  */
1316 #define SEI_CTRL_CMD_TABLE_PTA_PTR0_MASK (0xFFU)
1317 #define SEI_CTRL_CMD_TABLE_PTA_PTR0_SHIFT (0U)
1318 #define SEI_CTRL_CMD_TABLE_PTA_PTR0_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR0_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR0_MASK)
1319 #define SEI_CTRL_CMD_TABLE_PTA_PTR0_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR0_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR0_SHIFT)
1320 
1321 /* Bitfield definition for register of struct array CTRL: PTB */
1322 /*
1323  * PTR7 (RW)
1324  *
1325  * pointer7
1326  */
1327 #define SEI_CTRL_CMD_TABLE_PTB_PTR7_MASK (0xFF000000UL)
1328 #define SEI_CTRL_CMD_TABLE_PTB_PTR7_SHIFT (24U)
1329 #define SEI_CTRL_CMD_TABLE_PTB_PTR7_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR7_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR7_MASK)
1330 #define SEI_CTRL_CMD_TABLE_PTB_PTR7_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR7_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR7_SHIFT)
1331 
1332 /*
1333  * PTR6 (RW)
1334  *
1335  * pointer6
1336  */
1337 #define SEI_CTRL_CMD_TABLE_PTB_PTR6_MASK (0xFF0000UL)
1338 #define SEI_CTRL_CMD_TABLE_PTB_PTR6_SHIFT (16U)
1339 #define SEI_CTRL_CMD_TABLE_PTB_PTR6_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR6_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR6_MASK)
1340 #define SEI_CTRL_CMD_TABLE_PTB_PTR6_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR6_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR6_SHIFT)
1341 
1342 /*
1343  * PTR5 (RW)
1344  *
1345  * pointer5
1346  */
1347 #define SEI_CTRL_CMD_TABLE_PTB_PTR5_MASK (0xFF00U)
1348 #define SEI_CTRL_CMD_TABLE_PTB_PTR5_SHIFT (8U)
1349 #define SEI_CTRL_CMD_TABLE_PTB_PTR5_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR5_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR5_MASK)
1350 #define SEI_CTRL_CMD_TABLE_PTB_PTR5_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR5_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR5_SHIFT)
1351 
1352 /*
1353  * PTR4 (RW)
1354  *
1355  * pointer4
1356  */
1357 #define SEI_CTRL_CMD_TABLE_PTB_PTR4_MASK (0xFFU)
1358 #define SEI_CTRL_CMD_TABLE_PTB_PTR4_SHIFT (0U)
1359 #define SEI_CTRL_CMD_TABLE_PTB_PTR4_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR4_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR4_MASK)
1360 #define SEI_CTRL_CMD_TABLE_PTB_PTR4_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR4_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR4_SHIFT)
1361 
1362 /* Bitfield definition for register of struct array CTRL: PTC */
1363 /*
1364  * PTR11 (RW)
1365  *
1366  * pointer11
1367  */
1368 #define SEI_CTRL_CMD_TABLE_PTC_PTR11_MASK (0xFF000000UL)
1369 #define SEI_CTRL_CMD_TABLE_PTC_PTR11_SHIFT (24U)
1370 #define SEI_CTRL_CMD_TABLE_PTC_PTR11_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTC_PTR11_SHIFT) & SEI_CTRL_CMD_TABLE_PTC_PTR11_MASK)
1371 #define SEI_CTRL_CMD_TABLE_PTC_PTR11_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTC_PTR11_MASK) >> SEI_CTRL_CMD_TABLE_PTC_PTR11_SHIFT)
1372 
1373 /*
1374  * PTR10 (RW)
1375  *
1376  * pointer10
1377  */
1378 #define SEI_CTRL_CMD_TABLE_PTC_PTR10_MASK (0xFF0000UL)
1379 #define SEI_CTRL_CMD_TABLE_PTC_PTR10_SHIFT (16U)
1380 #define SEI_CTRL_CMD_TABLE_PTC_PTR10_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTC_PTR10_SHIFT) & SEI_CTRL_CMD_TABLE_PTC_PTR10_MASK)
1381 #define SEI_CTRL_CMD_TABLE_PTC_PTR10_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTC_PTR10_MASK) >> SEI_CTRL_CMD_TABLE_PTC_PTR10_SHIFT)
1382 
1383 /*
1384  * PTR9 (RW)
1385  *
1386  * pointer9
1387  */
1388 #define SEI_CTRL_CMD_TABLE_PTC_PTR9_MASK (0xFF00U)
1389 #define SEI_CTRL_CMD_TABLE_PTC_PTR9_SHIFT (8U)
1390 #define SEI_CTRL_CMD_TABLE_PTC_PTR9_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTC_PTR9_SHIFT) & SEI_CTRL_CMD_TABLE_PTC_PTR9_MASK)
1391 #define SEI_CTRL_CMD_TABLE_PTC_PTR9_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTC_PTR9_MASK) >> SEI_CTRL_CMD_TABLE_PTC_PTR9_SHIFT)
1392 
1393 /*
1394  * PTR8 (RW)
1395  *
1396  * pointer8
1397  */
1398 #define SEI_CTRL_CMD_TABLE_PTC_PTR8_MASK (0xFFU)
1399 #define SEI_CTRL_CMD_TABLE_PTC_PTR8_SHIFT (0U)
1400 #define SEI_CTRL_CMD_TABLE_PTC_PTR8_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTC_PTR8_SHIFT) & SEI_CTRL_CMD_TABLE_PTC_PTR8_MASK)
1401 #define SEI_CTRL_CMD_TABLE_PTC_PTR8_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTC_PTR8_MASK) >> SEI_CTRL_CMD_TABLE_PTC_PTR8_SHIFT)
1402 
1403 /* Bitfield definition for register of struct array CTRL: PTD */
1404 /*
1405  * PTR15 (RW)
1406  *
1407  * pointer15
1408  */
1409 #define SEI_CTRL_CMD_TABLE_PTD_PTR15_MASK (0xFF000000UL)
1410 #define SEI_CTRL_CMD_TABLE_PTD_PTR15_SHIFT (24U)
1411 #define SEI_CTRL_CMD_TABLE_PTD_PTR15_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTD_PTR15_SHIFT) & SEI_CTRL_CMD_TABLE_PTD_PTR15_MASK)
1412 #define SEI_CTRL_CMD_TABLE_PTD_PTR15_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTD_PTR15_MASK) >> SEI_CTRL_CMD_TABLE_PTD_PTR15_SHIFT)
1413 
1414 /*
1415  * PTR14 (RW)
1416  *
1417  * pointer14
1418  */
1419 #define SEI_CTRL_CMD_TABLE_PTD_PTR14_MASK (0xFF0000UL)
1420 #define SEI_CTRL_CMD_TABLE_PTD_PTR14_SHIFT (16U)
1421 #define SEI_CTRL_CMD_TABLE_PTD_PTR14_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTD_PTR14_SHIFT) & SEI_CTRL_CMD_TABLE_PTD_PTR14_MASK)
1422 #define SEI_CTRL_CMD_TABLE_PTD_PTR14_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTD_PTR14_MASK) >> SEI_CTRL_CMD_TABLE_PTD_PTR14_SHIFT)
1423 
1424 /*
1425  * PTR13 (RW)
1426  *
1427  * pointer13
1428  */
1429 #define SEI_CTRL_CMD_TABLE_PTD_PTR13_MASK (0xFF00U)
1430 #define SEI_CTRL_CMD_TABLE_PTD_PTR13_SHIFT (8U)
1431 #define SEI_CTRL_CMD_TABLE_PTD_PTR13_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTD_PTR13_SHIFT) & SEI_CTRL_CMD_TABLE_PTD_PTR13_MASK)
1432 #define SEI_CTRL_CMD_TABLE_PTD_PTR13_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTD_PTR13_MASK) >> SEI_CTRL_CMD_TABLE_PTD_PTR13_SHIFT)
1433 
1434 /*
1435  * PTR12 (RW)
1436  *
1437  * pointer12
1438  */
1439 #define SEI_CTRL_CMD_TABLE_PTD_PTR12_MASK (0xFFU)
1440 #define SEI_CTRL_CMD_TABLE_PTD_PTR12_SHIFT (0U)
1441 #define SEI_CTRL_CMD_TABLE_PTD_PTR12_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTD_PTR12_SHIFT) & SEI_CTRL_CMD_TABLE_PTD_PTR12_MASK)
1442 #define SEI_CTRL_CMD_TABLE_PTD_PTR12_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTD_PTR12_MASK) >> SEI_CTRL_CMD_TABLE_PTD_PTR12_SHIFT)
1443 
1444 /* Bitfield definition for register of struct array CTRL: 0_1 */
1445 /*
1446  * POINTER (RW)
1447  *
1448  * pointer
1449  */
1450 #define SEI_CTRL_LATCH_TRAN_POINTER_MASK (0xFF000000UL)
1451 #define SEI_CTRL_LATCH_TRAN_POINTER_SHIFT (24U)
1452 #define SEI_CTRL_LATCH_TRAN_POINTER_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_POINTER_SHIFT) & SEI_CTRL_LATCH_TRAN_POINTER_MASK)
1453 #define SEI_CTRL_LATCH_TRAN_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_POINTER_MASK) >> SEI_CTRL_LATCH_TRAN_POINTER_SHIFT)
1454 
1455 /*
1456  * CFG_TM (RW)
1457  *
1458  * timeout
1459  * 0: high
1460  * 1: low
1461  * 2: rise
1462  * 3: fall
1463  */
1464 #define SEI_CTRL_LATCH_TRAN_CFG_TM_MASK (0x30000UL)
1465 #define SEI_CTRL_LATCH_TRAN_CFG_TM_SHIFT (16U)
1466 #define SEI_CTRL_LATCH_TRAN_CFG_TM_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_TM_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_TM_MASK)
1467 #define SEI_CTRL_LATCH_TRAN_CFG_TM_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_TM_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_TM_SHIFT)
1468 
1469 /*
1470  * CFG_RXD (RW)
1471  *
1472  * data received
1473  * 0: high
1474  * 1: low
1475  * 2: rise
1476  * 3: fall
1477  */
1478 #define SEI_CTRL_LATCH_TRAN_CFG_RXD_MASK (0xC000U)
1479 #define SEI_CTRL_LATCH_TRAN_CFG_RXD_SHIFT (14U)
1480 #define SEI_CTRL_LATCH_TRAN_CFG_RXD_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_RXD_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_RXD_MASK)
1481 #define SEI_CTRL_LATCH_TRAN_CFG_RXD_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_RXD_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_RXD_SHIFT)
1482 
1483 /*
1484  * CFG_TXD (RW)
1485  *
1486  * data send
1487  * 0: high
1488  * 1: low
1489  * 2: rise
1490  * 3: fall
1491  */
1492 #define SEI_CTRL_LATCH_TRAN_CFG_TXD_MASK (0x3000U)
1493 #define SEI_CTRL_LATCH_TRAN_CFG_TXD_SHIFT (12U)
1494 #define SEI_CTRL_LATCH_TRAN_CFG_TXD_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_TXD_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_TXD_MASK)
1495 #define SEI_CTRL_LATCH_TRAN_CFG_TXD_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_TXD_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_TXD_SHIFT)
1496 
1497 /*
1498  * CFG_CLK (RW)
1499  *
1500  * clock
1501  * 0: high
1502  * 1: low
1503  * 2: rise
1504  * 3: fall
1505  */
1506 #define SEI_CTRL_LATCH_TRAN_CFG_CLK_MASK (0xC00U)
1507 #define SEI_CTRL_LATCH_TRAN_CFG_CLK_SHIFT (10U)
1508 #define SEI_CTRL_LATCH_TRAN_CFG_CLK_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_CLK_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_CLK_MASK)
1509 #define SEI_CTRL_LATCH_TRAN_CFG_CLK_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_CLK_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_CLK_SHIFT)
1510 
1511 /*
1512  * CFG_PTR (RW)
1513  *
1514  * pointer
1515  * 0: match
1516  * 1: not match
1517  * 2:entry
1518  * 3:leave
1519  */
1520 #define SEI_CTRL_LATCH_TRAN_CFG_PTR_MASK (0x300U)
1521 #define SEI_CTRL_LATCH_TRAN_CFG_PTR_SHIFT (8U)
1522 #define SEI_CTRL_LATCH_TRAN_CFG_PTR_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_PTR_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_PTR_MASK)
1523 #define SEI_CTRL_LATCH_TRAN_CFG_PTR_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_PTR_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_PTR_SHIFT)
1524 
1525 /*
1526  * OV_TM (RW)
1527  *
1528  * override timeout check
1529  */
1530 #define SEI_CTRL_LATCH_TRAN_OV_TM_MASK (0x10U)
1531 #define SEI_CTRL_LATCH_TRAN_OV_TM_SHIFT (4U)
1532 #define SEI_CTRL_LATCH_TRAN_OV_TM_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_TM_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_TM_MASK)
1533 #define SEI_CTRL_LATCH_TRAN_OV_TM_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_TM_MASK) >> SEI_CTRL_LATCH_TRAN_OV_TM_SHIFT)
1534 
1535 /*
1536  * OV_RXD (RW)
1537  *
1538  * override RX data check
1539  */
1540 #define SEI_CTRL_LATCH_TRAN_OV_RXD_MASK (0x8U)
1541 #define SEI_CTRL_LATCH_TRAN_OV_RXD_SHIFT (3U)
1542 #define SEI_CTRL_LATCH_TRAN_OV_RXD_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_RXD_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_RXD_MASK)
1543 #define SEI_CTRL_LATCH_TRAN_OV_RXD_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_RXD_MASK) >> SEI_CTRL_LATCH_TRAN_OV_RXD_SHIFT)
1544 
1545 /*
1546  * OV_TXD (RW)
1547  *
1548  * override TX data check
1549  */
1550 #define SEI_CTRL_LATCH_TRAN_OV_TXD_MASK (0x4U)
1551 #define SEI_CTRL_LATCH_TRAN_OV_TXD_SHIFT (2U)
1552 #define SEI_CTRL_LATCH_TRAN_OV_TXD_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_TXD_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_TXD_MASK)
1553 #define SEI_CTRL_LATCH_TRAN_OV_TXD_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_TXD_MASK) >> SEI_CTRL_LATCH_TRAN_OV_TXD_SHIFT)
1554 
1555 /*
1556  * OV_CLK (RW)
1557  *
1558  * override clock check
1559  */
1560 #define SEI_CTRL_LATCH_TRAN_OV_CLK_MASK (0x2U)
1561 #define SEI_CTRL_LATCH_TRAN_OV_CLK_SHIFT (1U)
1562 #define SEI_CTRL_LATCH_TRAN_OV_CLK_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_CLK_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_CLK_MASK)
1563 #define SEI_CTRL_LATCH_TRAN_OV_CLK_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_CLK_MASK) >> SEI_CTRL_LATCH_TRAN_OV_CLK_SHIFT)
1564 
1565 /*
1566  * OV_PTR (RW)
1567  *
1568  * override pointer check
1569  */
1570 #define SEI_CTRL_LATCH_TRAN_OV_PTR_MASK (0x1U)
1571 #define SEI_CTRL_LATCH_TRAN_OV_PTR_SHIFT (0U)
1572 #define SEI_CTRL_LATCH_TRAN_OV_PTR_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_PTR_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_PTR_MASK)
1573 #define SEI_CTRL_LATCH_TRAN_OV_PTR_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_PTR_MASK) >> SEI_CTRL_LATCH_TRAN_OV_PTR_SHIFT)
1574 
1575 /* Bitfield definition for register of struct array CTRL: CFG */
1576 /*
1577  * EN (RW)
1578  *
1579  * Enable latch
1580  * 0: disable
1581  * 1: enable
1582  */
1583 #define SEI_CTRL_LATCH_CFG_EN_MASK (0x80000000UL)
1584 #define SEI_CTRL_LATCH_CFG_EN_SHIFT (31U)
1585 #define SEI_CTRL_LATCH_CFG_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_CFG_EN_SHIFT) & SEI_CTRL_LATCH_CFG_EN_MASK)
1586 #define SEI_CTRL_LATCH_CFG_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_CFG_EN_MASK) >> SEI_CTRL_LATCH_CFG_EN_SHIFT)
1587 
1588 /*
1589  * SELECT (RW)
1590  *
1591  * Output select
1592  * 0: state0-state1
1593  * 1: state1-state2
1594  * 2: state2-state3
1595  * 3: state3-state0
1596  */
1597 #define SEI_CTRL_LATCH_CFG_SELECT_MASK (0x7000000UL)
1598 #define SEI_CTRL_LATCH_CFG_SELECT_SHIFT (24U)
1599 #define SEI_CTRL_LATCH_CFG_SELECT_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_CFG_SELECT_SHIFT) & SEI_CTRL_LATCH_CFG_SELECT_MASK)
1600 #define SEI_CTRL_LATCH_CFG_SELECT_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_CFG_SELECT_MASK) >> SEI_CTRL_LATCH_CFG_SELECT_SHIFT)
1601 
1602 /*
1603  * DELAY (RW)
1604  *
1605  * Delay in system clock cycle, for state transition
1606  */
1607 #define SEI_CTRL_LATCH_CFG_DELAY_MASK (0xFFFFU)
1608 #define SEI_CTRL_LATCH_CFG_DELAY_SHIFT (0U)
1609 #define SEI_CTRL_LATCH_CFG_DELAY_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_CFG_DELAY_SHIFT) & SEI_CTRL_LATCH_CFG_DELAY_MASK)
1610 #define SEI_CTRL_LATCH_CFG_DELAY_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_CFG_DELAY_MASK) >> SEI_CTRL_LATCH_CFG_DELAY_SHIFT)
1611 
1612 /* Bitfield definition for register of struct array CTRL: TIME */
1613 /*
1614  * LAT_TIME (RO)
1615  *
1616  * Latch time
1617  */
1618 #define SEI_CTRL_LATCH_TIME_LAT_TIME_MASK (0xFFFFFFFFUL)
1619 #define SEI_CTRL_LATCH_TIME_LAT_TIME_SHIFT (0U)
1620 #define SEI_CTRL_LATCH_TIME_LAT_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TIME_LAT_TIME_MASK) >> SEI_CTRL_LATCH_TIME_LAT_TIME_SHIFT)
1621 
1622 /* Bitfield definition for register of struct array CTRL: STS */
1623 /*
1624  * STATE (RO)
1625  *
1626  * State
1627  */
1628 #define SEI_CTRL_LATCH_STS_STATE_MASK (0x7000000UL)
1629 #define SEI_CTRL_LATCH_STS_STATE_SHIFT (24U)
1630 #define SEI_CTRL_LATCH_STS_STATE_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_STS_STATE_MASK) >> SEI_CTRL_LATCH_STS_STATE_SHIFT)
1631 
1632 /*
1633  * LAT_CNT (RO)
1634  *
1635  * Latch counter
1636  */
1637 #define SEI_CTRL_LATCH_STS_LAT_CNT_MASK (0xFFFFU)
1638 #define SEI_CTRL_LATCH_STS_LAT_CNT_SHIFT (0U)
1639 #define SEI_CTRL_LATCH_STS_LAT_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_STS_LAT_CNT_MASK) >> SEI_CTRL_LATCH_STS_LAT_CNT_SHIFT)
1640 
1641 /* Bitfield definition for register of struct array CTRL: SMP_EN */
1642 /*
1643  * ACC_EN (RW)
1644  *
1645  * Position include acceleration
1646  * 0: use acceleration from sample override acceleration register
1647  * 1: use acceleration from motor group
1648  */
1649 #define SEI_CTRL_POS_SMP_EN_ACC_EN_MASK (0x80000000UL)
1650 #define SEI_CTRL_POS_SMP_EN_ACC_EN_SHIFT (31U)
1651 #define SEI_CTRL_POS_SMP_EN_ACC_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_ACC_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_ACC_EN_MASK)
1652 #define SEI_CTRL_POS_SMP_EN_ACC_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_ACC_EN_MASK) >> SEI_CTRL_POS_SMP_EN_ACC_EN_SHIFT)
1653 
1654 /*
1655  * ACC_SEL (RW)
1656  *
1657  * Data register for acceleration transfer
1658  */
1659 #define SEI_CTRL_POS_SMP_EN_ACC_SEL_MASK (0x1F000000UL)
1660 #define SEI_CTRL_POS_SMP_EN_ACC_SEL_SHIFT (24U)
1661 #define SEI_CTRL_POS_SMP_EN_ACC_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_ACC_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_ACC_SEL_MASK)
1662 #define SEI_CTRL_POS_SMP_EN_ACC_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_ACC_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_ACC_SEL_SHIFT)
1663 
1664 /*
1665  * SPD_EN (RW)
1666  *
1667  * Position include speed
1668  * 0: use speed from sample override speed register
1669  * 1: use speed from motor group
1670  */
1671 #define SEI_CTRL_POS_SMP_EN_SPD_EN_MASK (0x800000UL)
1672 #define SEI_CTRL_POS_SMP_EN_SPD_EN_SHIFT (23U)
1673 #define SEI_CTRL_POS_SMP_EN_SPD_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_SPD_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_SPD_EN_MASK)
1674 #define SEI_CTRL_POS_SMP_EN_SPD_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_SPD_EN_MASK) >> SEI_CTRL_POS_SMP_EN_SPD_EN_SHIFT)
1675 
1676 /*
1677  * SPD_SEL (RW)
1678  *
1679  * Data register for speed transfer
1680  */
1681 #define SEI_CTRL_POS_SMP_EN_SPD_SEL_MASK (0x1F0000UL)
1682 #define SEI_CTRL_POS_SMP_EN_SPD_SEL_SHIFT (16U)
1683 #define SEI_CTRL_POS_SMP_EN_SPD_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_SPD_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_SPD_SEL_MASK)
1684 #define SEI_CTRL_POS_SMP_EN_SPD_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_SPD_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_SPD_SEL_SHIFT)
1685 
1686 /*
1687  * REV_EN (RW)
1688  *
1689  * Position include revolution
1690  * 0: use revolution from sample override revolution register
1691  * 1: use revolution from motor group
1692  */
1693 #define SEI_CTRL_POS_SMP_EN_REV_EN_MASK (0x8000U)
1694 #define SEI_CTRL_POS_SMP_EN_REV_EN_SHIFT (15U)
1695 #define SEI_CTRL_POS_SMP_EN_REV_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_REV_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_REV_EN_MASK)
1696 #define SEI_CTRL_POS_SMP_EN_REV_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_REV_EN_MASK) >> SEI_CTRL_POS_SMP_EN_REV_EN_SHIFT)
1697 
1698 /*
1699  * REV_SEL (RW)
1700  *
1701  * Data register for revolution transfer
1702  */
1703 #define SEI_CTRL_POS_SMP_EN_REV_SEL_MASK (0x1F00U)
1704 #define SEI_CTRL_POS_SMP_EN_REV_SEL_SHIFT (8U)
1705 #define SEI_CTRL_POS_SMP_EN_REV_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_REV_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_REV_SEL_MASK)
1706 #define SEI_CTRL_POS_SMP_EN_REV_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_REV_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_REV_SEL_SHIFT)
1707 
1708 /*
1709  * POS_EN (RW)
1710  *
1711  * Position include position
1712  * 0: use position from sample override position register
1713  * 1: use position from motor group
1714  */
1715 #define SEI_CTRL_POS_SMP_EN_POS_EN_MASK (0x80U)
1716 #define SEI_CTRL_POS_SMP_EN_POS_EN_SHIFT (7U)
1717 #define SEI_CTRL_POS_SMP_EN_POS_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_POS_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_POS_EN_MASK)
1718 #define SEI_CTRL_POS_SMP_EN_POS_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_POS_EN_MASK) >> SEI_CTRL_POS_SMP_EN_POS_EN_SHIFT)
1719 
1720 /*
1721  * POS_SEL (RW)
1722  *
1723  * Data register for position transfer
1724  */
1725 #define SEI_CTRL_POS_SMP_EN_POS_SEL_MASK (0x1FU)
1726 #define SEI_CTRL_POS_SMP_EN_POS_SEL_SHIFT (0U)
1727 #define SEI_CTRL_POS_SMP_EN_POS_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_POS_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_POS_SEL_MASK)
1728 #define SEI_CTRL_POS_SMP_EN_POS_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_POS_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_POS_SEL_SHIFT)
1729 
1730 /* Bitfield definition for register of struct array CTRL: SMP_CFG */
1731 /*
1732  * ONCE (RW)
1733  *
1734  * Sample one time
1735  * 0: Sample during windows time
1736  * 1: Close sample window after first sample
1737  */
1738 #define SEI_CTRL_POS_SMP_CFG_ONCE_MASK (0x1000000UL)
1739 #define SEI_CTRL_POS_SMP_CFG_ONCE_SHIFT (24U)
1740 #define SEI_CTRL_POS_SMP_CFG_ONCE_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_CFG_ONCE_SHIFT) & SEI_CTRL_POS_SMP_CFG_ONCE_MASK)
1741 #define SEI_CTRL_POS_SMP_CFG_ONCE_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_CFG_ONCE_MASK) >> SEI_CTRL_POS_SMP_CFG_ONCE_SHIFT)
1742 
1743 /*
1744  * LAT_SEL (RW)
1745  *
1746  * Latch selection
1747  * 0: latch 0
1748  * 1: latch 1
1749  * 2: latch 2
1750  * 3: latch 3
1751  */
1752 #define SEI_CTRL_POS_SMP_CFG_LAT_SEL_MASK (0x30000UL)
1753 #define SEI_CTRL_POS_SMP_CFG_LAT_SEL_SHIFT (16U)
1754 #define SEI_CTRL_POS_SMP_CFG_LAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_CFG_LAT_SEL_SHIFT) & SEI_CTRL_POS_SMP_CFG_LAT_SEL_MASK)
1755 #define SEI_CTRL_POS_SMP_CFG_LAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_CFG_LAT_SEL_MASK) >> SEI_CTRL_POS_SMP_CFG_LAT_SEL_SHIFT)
1756 
1757 /*
1758  * WINDOW (RW)
1759  *
1760  * Sample window, in clock cycle
1761  */
1762 #define SEI_CTRL_POS_SMP_CFG_WINDOW_MASK (0xFFFFU)
1763 #define SEI_CTRL_POS_SMP_CFG_WINDOW_SHIFT (0U)
1764 #define SEI_CTRL_POS_SMP_CFG_WINDOW_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_CFG_WINDOW_SHIFT) & SEI_CTRL_POS_SMP_CFG_WINDOW_MASK)
1765 #define SEI_CTRL_POS_SMP_CFG_WINDOW_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_CFG_WINDOW_MASK) >> SEI_CTRL_POS_SMP_CFG_WINDOW_SHIFT)
1766 
1767 /* Bitfield definition for register of struct array CTRL: SMP_DAT */
1768 /*
1769  * DAT_SEL (RW)
1770  *
1771  * Data register sampled, each bit represent a data register, select the DATA registers need to be updated when SAMPLE happens.
1772  * Note: CRC register will be cleared automatically by SAMPLE if select the DATA register used for CRC.
1773  */
1774 #define SEI_CTRL_POS_SMP_DAT_DAT_SEL_MASK (0xFFFFFFFFUL)
1775 #define SEI_CTRL_POS_SMP_DAT_DAT_SEL_SHIFT (0U)
1776 #define SEI_CTRL_POS_SMP_DAT_DAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_DAT_DAT_SEL_SHIFT) & SEI_CTRL_POS_SMP_DAT_DAT_SEL_MASK)
1777 #define SEI_CTRL_POS_SMP_DAT_DAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_DAT_DAT_SEL_MASK) >> SEI_CTRL_POS_SMP_DAT_DAT_SEL_SHIFT)
1778 
1779 /* Bitfield definition for register of struct array CTRL: SMP_POS */
1780 /*
1781  * POS (RW)
1782  *
1783  * Sample override position
1784  */
1785 #define SEI_CTRL_POS_SMP_POS_POS_MASK (0xFFFFFFFFUL)
1786 #define SEI_CTRL_POS_SMP_POS_POS_SHIFT (0U)
1787 #define SEI_CTRL_POS_SMP_POS_POS_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_POS_POS_SHIFT) & SEI_CTRL_POS_SMP_POS_POS_MASK)
1788 #define SEI_CTRL_POS_SMP_POS_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_POS_POS_MASK) >> SEI_CTRL_POS_SMP_POS_POS_SHIFT)
1789 
1790 /* Bitfield definition for register of struct array CTRL: SMP_REV */
1791 /*
1792  * REV (RW)
1793  *
1794  * Sample override revolution
1795  */
1796 #define SEI_CTRL_POS_SMP_REV_REV_MASK (0xFFFFFFFFUL)
1797 #define SEI_CTRL_POS_SMP_REV_REV_SHIFT (0U)
1798 #define SEI_CTRL_POS_SMP_REV_REV_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_REV_REV_SHIFT) & SEI_CTRL_POS_SMP_REV_REV_MASK)
1799 #define SEI_CTRL_POS_SMP_REV_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_REV_REV_MASK) >> SEI_CTRL_POS_SMP_REV_REV_SHIFT)
1800 
1801 /* Bitfield definition for register of struct array CTRL: SMP_SPD */
1802 /*
1803  * SPD (RW)
1804  *
1805  * Sample override speed
1806  */
1807 #define SEI_CTRL_POS_SMP_SPD_SPD_MASK (0xFFFFFFFFUL)
1808 #define SEI_CTRL_POS_SMP_SPD_SPD_SHIFT (0U)
1809 #define SEI_CTRL_POS_SMP_SPD_SPD_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_SPD_SPD_SHIFT) & SEI_CTRL_POS_SMP_SPD_SPD_MASK)
1810 #define SEI_CTRL_POS_SMP_SPD_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_SPD_SPD_MASK) >> SEI_CTRL_POS_SMP_SPD_SPD_SHIFT)
1811 
1812 /* Bitfield definition for register of struct array CTRL: SMP_ACC */
1813 /*
1814  * ACC (RW)
1815  *
1816  * Sample override accelerate
1817  */
1818 #define SEI_CTRL_POS_SMP_ACC_ACC_MASK (0xFFFFFFFFUL)
1819 #define SEI_CTRL_POS_SMP_ACC_ACC_SHIFT (0U)
1820 #define SEI_CTRL_POS_SMP_ACC_ACC_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_ACC_ACC_SHIFT) & SEI_CTRL_POS_SMP_ACC_ACC_MASK)
1821 #define SEI_CTRL_POS_SMP_ACC_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_ACC_ACC_MASK) >> SEI_CTRL_POS_SMP_ACC_ACC_SHIFT)
1822 
1823 /* Bitfield definition for register of struct array CTRL: UPD_EN */
1824 /*
1825  * ACC_EN (RW)
1826  *
1827  * Position include acceleration
1828  * 0: use acceleration from update override acceleration register
1829  * 1: use acceleration from data register
1830  */
1831 #define SEI_CTRL_POS_UPD_EN_ACC_EN_MASK (0x80000000UL)
1832 #define SEI_CTRL_POS_UPD_EN_ACC_EN_SHIFT (31U)
1833 #define SEI_CTRL_POS_UPD_EN_ACC_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_ACC_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_ACC_EN_MASK)
1834 #define SEI_CTRL_POS_UPD_EN_ACC_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_ACC_EN_MASK) >> SEI_CTRL_POS_UPD_EN_ACC_EN_SHIFT)
1835 
1836 /*
1837  * ACC_SEL (RW)
1838  *
1839  * Data register for acceleration transfer
1840  */
1841 #define SEI_CTRL_POS_UPD_EN_ACC_SEL_MASK (0x1F000000UL)
1842 #define SEI_CTRL_POS_UPD_EN_ACC_SEL_SHIFT (24U)
1843 #define SEI_CTRL_POS_UPD_EN_ACC_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_ACC_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_ACC_SEL_MASK)
1844 #define SEI_CTRL_POS_UPD_EN_ACC_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_ACC_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_ACC_SEL_SHIFT)
1845 
1846 /*
1847  * SPD_EN (RW)
1848  *
1849  * Position include speed
1850  * 0: use speed from update override speed register
1851  * 1: use speed from data register
1852  */
1853 #define SEI_CTRL_POS_UPD_EN_SPD_EN_MASK (0x800000UL)
1854 #define SEI_CTRL_POS_UPD_EN_SPD_EN_SHIFT (23U)
1855 #define SEI_CTRL_POS_UPD_EN_SPD_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_SPD_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_SPD_EN_MASK)
1856 #define SEI_CTRL_POS_UPD_EN_SPD_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_SPD_EN_MASK) >> SEI_CTRL_POS_UPD_EN_SPD_EN_SHIFT)
1857 
1858 /*
1859  * SPD_SEL (RW)
1860  *
1861  * Data register for speed transfer
1862  */
1863 #define SEI_CTRL_POS_UPD_EN_SPD_SEL_MASK (0x1F0000UL)
1864 #define SEI_CTRL_POS_UPD_EN_SPD_SEL_SHIFT (16U)
1865 #define SEI_CTRL_POS_UPD_EN_SPD_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_SPD_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_SPD_SEL_MASK)
1866 #define SEI_CTRL_POS_UPD_EN_SPD_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_SPD_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_SPD_SEL_SHIFT)
1867 
1868 /*
1869  * REV_EN (RW)
1870  *
1871  * Position include revolution
1872  * 0: use revolution from update override revolution register
1873  * 1: use revolution from data register
1874  */
1875 #define SEI_CTRL_POS_UPD_EN_REV_EN_MASK (0x8000U)
1876 #define SEI_CTRL_POS_UPD_EN_REV_EN_SHIFT (15U)
1877 #define SEI_CTRL_POS_UPD_EN_REV_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_REV_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_REV_EN_MASK)
1878 #define SEI_CTRL_POS_UPD_EN_REV_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_REV_EN_MASK) >> SEI_CTRL_POS_UPD_EN_REV_EN_SHIFT)
1879 
1880 /*
1881  * REV_SEL (RW)
1882  *
1883  * Data register for revolution transfer
1884  */
1885 #define SEI_CTRL_POS_UPD_EN_REV_SEL_MASK (0x1F00U)
1886 #define SEI_CTRL_POS_UPD_EN_REV_SEL_SHIFT (8U)
1887 #define SEI_CTRL_POS_UPD_EN_REV_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_REV_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_REV_SEL_MASK)
1888 #define SEI_CTRL_POS_UPD_EN_REV_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_REV_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_REV_SEL_SHIFT)
1889 
1890 /*
1891  * POS_EN (RW)
1892  *
1893  * Position include position
1894  * 0: use position from update override position register
1895  * 1: use position from data register
1896  */
1897 #define SEI_CTRL_POS_UPD_EN_POS_EN_MASK (0x80U)
1898 #define SEI_CTRL_POS_UPD_EN_POS_EN_SHIFT (7U)
1899 #define SEI_CTRL_POS_UPD_EN_POS_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_POS_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_POS_EN_MASK)
1900 #define SEI_CTRL_POS_UPD_EN_POS_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_POS_EN_MASK) >> SEI_CTRL_POS_UPD_EN_POS_EN_SHIFT)
1901 
1902 /*
1903  * POS_SEL (RW)
1904  *
1905  * Data register for position transfer
1906  */
1907 #define SEI_CTRL_POS_UPD_EN_POS_SEL_MASK (0x1FU)
1908 #define SEI_CTRL_POS_UPD_EN_POS_SEL_SHIFT (0U)
1909 #define SEI_CTRL_POS_UPD_EN_POS_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_POS_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_POS_SEL_MASK)
1910 #define SEI_CTRL_POS_UPD_EN_POS_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_POS_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_POS_SEL_SHIFT)
1911 
1912 /* Bitfield definition for register of struct array CTRL: UPD_CFG */
1913 /*
1914  * TIME_OVRD (RW)
1915  *
1916  * Use override time
1917  * 0: use time sample from motor group
1918  * 1: use override time
1919  */
1920 #define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_MASK (0x80000000UL)
1921 #define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SHIFT (31U)
1922 #define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SHIFT) & SEI_CTRL_POS_UPD_CFG_TIME_OVRD_MASK)
1923 #define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_CFG_TIME_OVRD_MASK) >> SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SHIFT)
1924 
1925 /*
1926  * ONERR (RW)
1927  *
1928  * Sample one time
1929  * 0: Sample during windows time
1930  * 1: Close sample window after first sample
1931  */
1932 #define SEI_CTRL_POS_UPD_CFG_ONERR_MASK (0x1000000UL)
1933 #define SEI_CTRL_POS_UPD_CFG_ONERR_SHIFT (24U)
1934 #define SEI_CTRL_POS_UPD_CFG_ONERR_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_CFG_ONERR_SHIFT) & SEI_CTRL_POS_UPD_CFG_ONERR_MASK)
1935 #define SEI_CTRL_POS_UPD_CFG_ONERR_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_CFG_ONERR_MASK) >> SEI_CTRL_POS_UPD_CFG_ONERR_SHIFT)
1936 
1937 /*
1938  * LAT_SEL (RW)
1939  *
1940  * Latch selection
1941  * 0: latch 0
1942  * 1: latch 1
1943  * 2: latch 2
1944  * 3: latch 3
1945  */
1946 #define SEI_CTRL_POS_UPD_CFG_LAT_SEL_MASK (0x30000UL)
1947 #define SEI_CTRL_POS_UPD_CFG_LAT_SEL_SHIFT (16U)
1948 #define SEI_CTRL_POS_UPD_CFG_LAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_CFG_LAT_SEL_SHIFT) & SEI_CTRL_POS_UPD_CFG_LAT_SEL_MASK)
1949 #define SEI_CTRL_POS_UPD_CFG_LAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_CFG_LAT_SEL_MASK) >> SEI_CTRL_POS_UPD_CFG_LAT_SEL_SHIFT)
1950 
1951 /* Bitfield definition for register of struct array CTRL: UPD_DAT */
1952 /*
1953  * DAT_SEL (RW)
1954  *
1955  * Data register sampled, each bit represent a data register, select the DATA registers need to be updated when UPDATE happen.
1956  * Note: CRC register will be cleared automatically by UPDATE if select the DATA register used for CRC.
1957  */
1958 #define SEI_CTRL_POS_UPD_DAT_DAT_SEL_MASK (0xFFFFFFFFUL)
1959 #define SEI_CTRL_POS_UPD_DAT_DAT_SEL_SHIFT (0U)
1960 #define SEI_CTRL_POS_UPD_DAT_DAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_DAT_DAT_SEL_SHIFT) & SEI_CTRL_POS_UPD_DAT_DAT_SEL_MASK)
1961 #define SEI_CTRL_POS_UPD_DAT_DAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_DAT_DAT_SEL_MASK) >> SEI_CTRL_POS_UPD_DAT_DAT_SEL_SHIFT)
1962 
1963 /* Bitfield definition for register of struct array CTRL: UPD_TIME */
1964 /*
1965  * TIME (RW)
1966  *
1967  * Update override time
1968  */
1969 #define SEI_CTRL_POS_UPD_TIME_TIME_MASK (0xFFFFFFFFUL)
1970 #define SEI_CTRL_POS_UPD_TIME_TIME_SHIFT (0U)
1971 #define SEI_CTRL_POS_UPD_TIME_TIME_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_TIME_TIME_SHIFT) & SEI_CTRL_POS_UPD_TIME_TIME_MASK)
1972 #define SEI_CTRL_POS_UPD_TIME_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_TIME_TIME_MASK) >> SEI_CTRL_POS_UPD_TIME_TIME_SHIFT)
1973 
1974 /* Bitfield definition for register of struct array CTRL: UPD_POS */
1975 /*
1976  * POS (RW)
1977  *
1978  * Update override position
1979  */
1980 #define SEI_CTRL_POS_UPD_POS_POS_MASK (0xFFFFFFFFUL)
1981 #define SEI_CTRL_POS_UPD_POS_POS_SHIFT (0U)
1982 #define SEI_CTRL_POS_UPD_POS_POS_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_POS_POS_SHIFT) & SEI_CTRL_POS_UPD_POS_POS_MASK)
1983 #define SEI_CTRL_POS_UPD_POS_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_POS_POS_MASK) >> SEI_CTRL_POS_UPD_POS_POS_SHIFT)
1984 
1985 /* Bitfield definition for register of struct array CTRL: UPD_REV */
1986 /*
1987  * REV (RW)
1988  *
1989  * Update override revolution
1990  */
1991 #define SEI_CTRL_POS_UPD_REV_REV_MASK (0xFFFFFFFFUL)
1992 #define SEI_CTRL_POS_UPD_REV_REV_SHIFT (0U)
1993 #define SEI_CTRL_POS_UPD_REV_REV_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_REV_REV_SHIFT) & SEI_CTRL_POS_UPD_REV_REV_MASK)
1994 #define SEI_CTRL_POS_UPD_REV_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_REV_REV_MASK) >> SEI_CTRL_POS_UPD_REV_REV_SHIFT)
1995 
1996 /* Bitfield definition for register of struct array CTRL: UPD_SPD */
1997 /*
1998  * SPD (RW)
1999  *
2000  * Update override speed
2001  */
2002 #define SEI_CTRL_POS_UPD_SPD_SPD_MASK (0xFFFFFFFFUL)
2003 #define SEI_CTRL_POS_UPD_SPD_SPD_SHIFT (0U)
2004 #define SEI_CTRL_POS_UPD_SPD_SPD_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_SPD_SPD_SHIFT) & SEI_CTRL_POS_UPD_SPD_SPD_MASK)
2005 #define SEI_CTRL_POS_UPD_SPD_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_SPD_SPD_MASK) >> SEI_CTRL_POS_UPD_SPD_SPD_SHIFT)
2006 
2007 /* Bitfield definition for register of struct array CTRL: UPD_ACC */
2008 /*
2009  * ACC (RW)
2010  *
2011  * Update override accelerate
2012  */
2013 #define SEI_CTRL_POS_UPD_ACC_ACC_MASK (0xFFFFFFFFUL)
2014 #define SEI_CTRL_POS_UPD_ACC_ACC_SHIFT (0U)
2015 #define SEI_CTRL_POS_UPD_ACC_ACC_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_ACC_ACC_SHIFT) & SEI_CTRL_POS_UPD_ACC_ACC_MASK)
2016 #define SEI_CTRL_POS_UPD_ACC_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_ACC_ACC_MASK) >> SEI_CTRL_POS_UPD_ACC_ACC_SHIFT)
2017 
2018 /* Bitfield definition for register of struct array CTRL: SMP_VAL */
2019 /*
2020  * ACC (RO)
2021  *
2022  * Position include acceleration
2023  */
2024 #define SEI_CTRL_POS_SMP_VAL_ACC_MASK (0x80000000UL)
2025 #define SEI_CTRL_POS_SMP_VAL_ACC_SHIFT (31U)
2026 #define SEI_CTRL_POS_SMP_VAL_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_ACC_MASK) >> SEI_CTRL_POS_SMP_VAL_ACC_SHIFT)
2027 
2028 /*
2029  * SPD (RO)
2030  *
2031  * Position include speed
2032  */
2033 #define SEI_CTRL_POS_SMP_VAL_SPD_MASK (0x800000UL)
2034 #define SEI_CTRL_POS_SMP_VAL_SPD_SHIFT (23U)
2035 #define SEI_CTRL_POS_SMP_VAL_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_SPD_MASK) >> SEI_CTRL_POS_SMP_VAL_SPD_SHIFT)
2036 
2037 /*
2038  * REV (RO)
2039  *
2040  * Position include revolution
2041  */
2042 #define SEI_CTRL_POS_SMP_VAL_REV_MASK (0x8000U)
2043 #define SEI_CTRL_POS_SMP_VAL_REV_SHIFT (15U)
2044 #define SEI_CTRL_POS_SMP_VAL_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_REV_MASK) >> SEI_CTRL_POS_SMP_VAL_REV_SHIFT)
2045 
2046 /*
2047  * POS (RO)
2048  *
2049  * Position include position
2050  */
2051 #define SEI_CTRL_POS_SMP_VAL_POS_MASK (0x80U)
2052 #define SEI_CTRL_POS_SMP_VAL_POS_SHIFT (7U)
2053 #define SEI_CTRL_POS_SMP_VAL_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_POS_MASK) >> SEI_CTRL_POS_SMP_VAL_POS_SHIFT)
2054 
2055 /* Bitfield definition for register of struct array CTRL: SMP_STS */
2056 /*
2057  * OCCUR (RO)
2058  *
2059  * Sample occured
2060  * 0: Sample not happened
2061  * 1: Sample occured
2062  */
2063 #define SEI_CTRL_POS_SMP_STS_OCCUR_MASK (0x1000000UL)
2064 #define SEI_CTRL_POS_SMP_STS_OCCUR_SHIFT (24U)
2065 #define SEI_CTRL_POS_SMP_STS_OCCUR_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_STS_OCCUR_MASK) >> SEI_CTRL_POS_SMP_STS_OCCUR_SHIFT)
2066 
2067 /*
2068  * WIN_CNT (RO)
2069  *
2070  * Sample window counter
2071  */
2072 #define SEI_CTRL_POS_SMP_STS_WIN_CNT_MASK (0xFFFFU)
2073 #define SEI_CTRL_POS_SMP_STS_WIN_CNT_SHIFT (0U)
2074 #define SEI_CTRL_POS_SMP_STS_WIN_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_STS_WIN_CNT_MASK) >> SEI_CTRL_POS_SMP_STS_WIN_CNT_SHIFT)
2075 
2076 /* Bitfield definition for register of struct array CTRL: TIME_IN */
2077 /*
2078  * TIME (RO)
2079  *
2080  * input time
2081  */
2082 #define SEI_CTRL_POS_TIME_IN_TIME_MASK (0xFFFFFFFFUL)
2083 #define SEI_CTRL_POS_TIME_IN_TIME_SHIFT (0U)
2084 #define SEI_CTRL_POS_TIME_IN_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_TIME_IN_TIME_MASK) >> SEI_CTRL_POS_TIME_IN_TIME_SHIFT)
2085 
2086 /* Bitfield definition for register of struct array CTRL: POS_IN */
2087 /*
2088  * POS (RO)
2089  *
2090  * Input position
2091  */
2092 #define SEI_CTRL_POS_POS_IN_POS_MASK (0xFFFFFFFFUL)
2093 #define SEI_CTRL_POS_POS_IN_POS_SHIFT (0U)
2094 #define SEI_CTRL_POS_POS_IN_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_POS_IN_POS_MASK) >> SEI_CTRL_POS_POS_IN_POS_SHIFT)
2095 
2096 /* Bitfield definition for register of struct array CTRL: REV_IN */
2097 /*
2098  * REV (RO)
2099  *
2100  * Input revolution
2101  */
2102 #define SEI_CTRL_POS_REV_IN_REV_MASK (0xFFFFFFFFUL)
2103 #define SEI_CTRL_POS_REV_IN_REV_SHIFT (0U)
2104 #define SEI_CTRL_POS_REV_IN_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_REV_IN_REV_MASK) >> SEI_CTRL_POS_REV_IN_REV_SHIFT)
2105 
2106 /* Bitfield definition for register of struct array CTRL: SPD_IN */
2107 /*
2108  * SPD (RO)
2109  *
2110  * Input speed
2111  */
2112 #define SEI_CTRL_POS_SPD_IN_SPD_MASK (0xFFFFFFFFUL)
2113 #define SEI_CTRL_POS_SPD_IN_SPD_SHIFT (0U)
2114 #define SEI_CTRL_POS_SPD_IN_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SPD_IN_SPD_MASK) >> SEI_CTRL_POS_SPD_IN_SPD_SHIFT)
2115 
2116 /* Bitfield definition for register of struct array CTRL: ACC_IN */
2117 /*
2118  * ACC (RO)
2119  *
2120  * Input accelerate
2121  */
2122 #define SEI_CTRL_POS_ACC_IN_ACC_MASK (0xFFFFFFFFUL)
2123 #define SEI_CTRL_POS_ACC_IN_ACC_SHIFT (0U)
2124 #define SEI_CTRL_POS_ACC_IN_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_ACC_IN_ACC_MASK) >> SEI_CTRL_POS_ACC_IN_ACC_SHIFT)
2125 
2126 /* Bitfield definition for register of struct array CTRL: UPD_STS */
2127 /*
2128  * UPD_ERR (RO)
2129  *
2130  * Update error
2131  * 0: data receive normally
2132  * 1: data receive error
2133  */
2134 #define SEI_CTRL_POS_UPD_STS_UPD_ERR_MASK (0x1000000UL)
2135 #define SEI_CTRL_POS_UPD_STS_UPD_ERR_SHIFT (24U)
2136 #define SEI_CTRL_POS_UPD_STS_UPD_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_STS_UPD_ERR_MASK) >> SEI_CTRL_POS_UPD_STS_UPD_ERR_SHIFT)
2137 
2138 /* Bitfield definition for register of struct array CTRL: INT_EN */
2139 /*
2140  * TRG_ERR3 (RW)
2141  *
2142  * Trigger3 failed
2143  */
2144 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_MASK (0x80000000UL)
2145 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SHIFT (31U)
2146 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR3_MASK)
2147 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR3_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SHIFT)
2148 
2149 /*
2150  * TRG_ERR2 (RW)
2151  *
2152  * Trigger2 failed
2153  */
2154 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_MASK (0x40000000UL)
2155 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SHIFT (30U)
2156 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR2_MASK)
2157 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR2_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SHIFT)
2158 
2159 /*
2160  * TRG_ERR1 (RW)
2161  *
2162  * Trigger1 failed
2163  */
2164 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_MASK (0x20000000UL)
2165 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SHIFT (29U)
2166 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR1_MASK)
2167 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR1_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SHIFT)
2168 
2169 /*
2170  * TRG_ERR0 (RW)
2171  *
2172  * Trigger0 failed
2173  */
2174 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_MASK (0x10000000UL)
2175 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SHIFT (28U)
2176 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR0_MASK)
2177 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR0_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SHIFT)
2178 
2179 /*
2180  * TRIGER3 (RW)
2181  *
2182  * Trigger3
2183  */
2184 #define SEI_CTRL_IRQ_INT_EN_TRIGER3_MASK (0x8000000UL)
2185 #define SEI_CTRL_IRQ_INT_EN_TRIGER3_SHIFT (27U)
2186 #define SEI_CTRL_IRQ_INT_EN_TRIGER3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER3_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER3_MASK)
2187 #define SEI_CTRL_IRQ_INT_EN_TRIGER3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER3_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER3_SHIFT)
2188 
2189 /*
2190  * TRIGER2 (RW)
2191  *
2192  * Trigger2
2193  */
2194 #define SEI_CTRL_IRQ_INT_EN_TRIGER2_MASK (0x4000000UL)
2195 #define SEI_CTRL_IRQ_INT_EN_TRIGER2_SHIFT (26U)
2196 #define SEI_CTRL_IRQ_INT_EN_TRIGER2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER2_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER2_MASK)
2197 #define SEI_CTRL_IRQ_INT_EN_TRIGER2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER2_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER2_SHIFT)
2198 
2199 /*
2200  * TRIGER1 (RW)
2201  *
2202  * Trigger1
2203  */
2204 #define SEI_CTRL_IRQ_INT_EN_TRIGER1_MASK (0x2000000UL)
2205 #define SEI_CTRL_IRQ_INT_EN_TRIGER1_SHIFT (25U)
2206 #define SEI_CTRL_IRQ_INT_EN_TRIGER1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER1_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER1_MASK)
2207 #define SEI_CTRL_IRQ_INT_EN_TRIGER1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER1_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER1_SHIFT)
2208 
2209 /*
2210  * TRIGER0 (RW)
2211  *
2212  * Trigger0
2213  */
2214 #define SEI_CTRL_IRQ_INT_EN_TRIGER0_MASK (0x1000000UL)
2215 #define SEI_CTRL_IRQ_INT_EN_TRIGER0_SHIFT (24U)
2216 #define SEI_CTRL_IRQ_INT_EN_TRIGER0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER0_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER0_MASK)
2217 #define SEI_CTRL_IRQ_INT_EN_TRIGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER0_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER0_SHIFT)
2218 
2219 /*
2220  * SMP_ERR (RW)
2221  *
2222  * Sample error
2223  */
2224 #define SEI_CTRL_IRQ_INT_EN_SMP_ERR_MASK (0x100000UL)
2225 #define SEI_CTRL_IRQ_INT_EN_SMP_ERR_SHIFT (20U)
2226 #define SEI_CTRL_IRQ_INT_EN_SMP_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_SMP_ERR_SHIFT) & SEI_CTRL_IRQ_INT_EN_SMP_ERR_MASK)
2227 #define SEI_CTRL_IRQ_INT_EN_SMP_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_SMP_ERR_MASK) >> SEI_CTRL_IRQ_INT_EN_SMP_ERR_SHIFT)
2228 
2229 /*
2230  * LATCH3 (RW)
2231  *
2232  * Latch3
2233  */
2234 #define SEI_CTRL_IRQ_INT_EN_LATCH3_MASK (0x80000UL)
2235 #define SEI_CTRL_IRQ_INT_EN_LATCH3_SHIFT (19U)
2236 #define SEI_CTRL_IRQ_INT_EN_LATCH3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH3_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH3_MASK)
2237 #define SEI_CTRL_IRQ_INT_EN_LATCH3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH3_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH3_SHIFT)
2238 
2239 /*
2240  * LATCH2 (RW)
2241  *
2242  * Latch2
2243  */
2244 #define SEI_CTRL_IRQ_INT_EN_LATCH2_MASK (0x40000UL)
2245 #define SEI_CTRL_IRQ_INT_EN_LATCH2_SHIFT (18U)
2246 #define SEI_CTRL_IRQ_INT_EN_LATCH2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH2_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH2_MASK)
2247 #define SEI_CTRL_IRQ_INT_EN_LATCH2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH2_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH2_SHIFT)
2248 
2249 /*
2250  * LATCH1 (RW)
2251  *
2252  * Latch1
2253  */
2254 #define SEI_CTRL_IRQ_INT_EN_LATCH1_MASK (0x20000UL)
2255 #define SEI_CTRL_IRQ_INT_EN_LATCH1_SHIFT (17U)
2256 #define SEI_CTRL_IRQ_INT_EN_LATCH1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH1_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH1_MASK)
2257 #define SEI_CTRL_IRQ_INT_EN_LATCH1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH1_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH1_SHIFT)
2258 
2259 /*
2260  * LATCH0 (RW)
2261  *
2262  * Latch0
2263  */
2264 #define SEI_CTRL_IRQ_INT_EN_LATCH0_MASK (0x10000UL)
2265 #define SEI_CTRL_IRQ_INT_EN_LATCH0_SHIFT (16U)
2266 #define SEI_CTRL_IRQ_INT_EN_LATCH0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH0_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH0_MASK)
2267 #define SEI_CTRL_IRQ_INT_EN_LATCH0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH0_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH0_SHIFT)
2268 
2269 /*
2270  * TIMEOUT (RW)
2271  *
2272  * Timeout
2273  */
2274 #define SEI_CTRL_IRQ_INT_EN_TIMEOUT_MASK (0x2000U)
2275 #define SEI_CTRL_IRQ_INT_EN_TIMEOUT_SHIFT (13U)
2276 #define SEI_CTRL_IRQ_INT_EN_TIMEOUT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TIMEOUT_SHIFT) & SEI_CTRL_IRQ_INT_EN_TIMEOUT_MASK)
2277 #define SEI_CTRL_IRQ_INT_EN_TIMEOUT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TIMEOUT_MASK) >> SEI_CTRL_IRQ_INT_EN_TIMEOUT_SHIFT)
2278 
2279 /*
2280  * TRX_ERR (RW)
2281  *
2282  * Transfer error
2283  */
2284 #define SEI_CTRL_IRQ_INT_EN_TRX_ERR_MASK (0x1000U)
2285 #define SEI_CTRL_IRQ_INT_EN_TRX_ERR_SHIFT (12U)
2286 #define SEI_CTRL_IRQ_INT_EN_TRX_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRX_ERR_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRX_ERR_MASK)
2287 #define SEI_CTRL_IRQ_INT_EN_TRX_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRX_ERR_MASK) >> SEI_CTRL_IRQ_INT_EN_TRX_ERR_SHIFT)
2288 
2289 /*
2290  * INSTR1_END (RW)
2291  *
2292  * Instruction 1 end
2293  */
2294 #define SEI_CTRL_IRQ_INT_EN_INSTR1_END_MASK (0x800U)
2295 #define SEI_CTRL_IRQ_INT_EN_INSTR1_END_SHIFT (11U)
2296 #define SEI_CTRL_IRQ_INT_EN_INSTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR1_END_MASK)
2297 #define SEI_CTRL_IRQ_INT_EN_INSTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR1_END_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR1_END_SHIFT)
2298 
2299 /*
2300  * INSTR0_END (RW)
2301  *
2302  * Instruction 0 end
2303  */
2304 #define SEI_CTRL_IRQ_INT_EN_INSTR0_END_MASK (0x400U)
2305 #define SEI_CTRL_IRQ_INT_EN_INSTR0_END_SHIFT (10U)
2306 #define SEI_CTRL_IRQ_INT_EN_INSTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR0_END_MASK)
2307 #define SEI_CTRL_IRQ_INT_EN_INSTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR0_END_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR0_END_SHIFT)
2308 
2309 /*
2310  * PTR1_END (RW)
2311  *
2312  * Pointer 1 end
2313  */
2314 #define SEI_CTRL_IRQ_INT_EN_PTR1_END_MASK (0x200U)
2315 #define SEI_CTRL_IRQ_INT_EN_PTR1_END_SHIFT (9U)
2316 #define SEI_CTRL_IRQ_INT_EN_PTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR1_END_MASK)
2317 #define SEI_CTRL_IRQ_INT_EN_PTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR1_END_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR1_END_SHIFT)
2318 
2319 /*
2320  * PTR0_END (RW)
2321  *
2322  * Pointer 0 end
2323  */
2324 #define SEI_CTRL_IRQ_INT_EN_PTR0_END_MASK (0x100U)
2325 #define SEI_CTRL_IRQ_INT_EN_PTR0_END_SHIFT (8U)
2326 #define SEI_CTRL_IRQ_INT_EN_PTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR0_END_MASK)
2327 #define SEI_CTRL_IRQ_INT_EN_PTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR0_END_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR0_END_SHIFT)
2328 
2329 /*
2330  * INSTR1_ST (RW)
2331  *
2332  * Instruction 1 start
2333  */
2334 #define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_MASK (0x80U)
2335 #define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SHIFT (7U)
2336 #define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR1_ST_MASK)
2337 #define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SHIFT)
2338 
2339 /*
2340  * INSTR0_ST (RW)
2341  *
2342  * Instruction 0 start
2343  */
2344 #define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_MASK (0x40U)
2345 #define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SHIFT (6U)
2346 #define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR0_ST_MASK)
2347 #define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SHIFT)
2348 
2349 /*
2350  * PTR1_ST (RW)
2351  *
2352  * Pointer 1 start
2353  */
2354 #define SEI_CTRL_IRQ_INT_EN_PTR1_ST_MASK (0x20U)
2355 #define SEI_CTRL_IRQ_INT_EN_PTR1_ST_SHIFT (5U)
2356 #define SEI_CTRL_IRQ_INT_EN_PTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR1_ST_MASK)
2357 #define SEI_CTRL_IRQ_INT_EN_PTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR1_ST_SHIFT)
2358 
2359 /*
2360  * PTR0_ST (RW)
2361  *
2362  * Pointer 0 start
2363  */
2364 #define SEI_CTRL_IRQ_INT_EN_PTR0_ST_MASK (0x10U)
2365 #define SEI_CTRL_IRQ_INT_EN_PTR0_ST_SHIFT (4U)
2366 #define SEI_CTRL_IRQ_INT_EN_PTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR0_ST_MASK)
2367 #define SEI_CTRL_IRQ_INT_EN_PTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR0_ST_SHIFT)
2368 
2369 /*
2370  * WDOG (RW)
2371  *
2372  * Watch dog
2373  */
2374 #define SEI_CTRL_IRQ_INT_EN_WDOG_MASK (0x4U)
2375 #define SEI_CTRL_IRQ_INT_EN_WDOG_SHIFT (2U)
2376 #define SEI_CTRL_IRQ_INT_EN_WDOG_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_WDOG_SHIFT) & SEI_CTRL_IRQ_INT_EN_WDOG_MASK)
2377 #define SEI_CTRL_IRQ_INT_EN_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_WDOG_MASK) >> SEI_CTRL_IRQ_INT_EN_WDOG_SHIFT)
2378 
2379 /*
2380  * EXCEPT (RW)
2381  *
2382  * Exception
2383  */
2384 #define SEI_CTRL_IRQ_INT_EN_EXCEPT_MASK (0x2U)
2385 #define SEI_CTRL_IRQ_INT_EN_EXCEPT_SHIFT (1U)
2386 #define SEI_CTRL_IRQ_INT_EN_EXCEPT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_EXCEPT_SHIFT) & SEI_CTRL_IRQ_INT_EN_EXCEPT_MASK)
2387 #define SEI_CTRL_IRQ_INT_EN_EXCEPT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_EXCEPT_MASK) >> SEI_CTRL_IRQ_INT_EN_EXCEPT_SHIFT)
2388 
2389 /*
2390  * STALL (RW)
2391  *
2392  * Stall
2393  */
2394 #define SEI_CTRL_IRQ_INT_EN_STALL_MASK (0x1U)
2395 #define SEI_CTRL_IRQ_INT_EN_STALL_SHIFT (0U)
2396 #define SEI_CTRL_IRQ_INT_EN_STALL_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_STALL_SHIFT) & SEI_CTRL_IRQ_INT_EN_STALL_MASK)
2397 #define SEI_CTRL_IRQ_INT_EN_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_STALL_MASK) >> SEI_CTRL_IRQ_INT_EN_STALL_SHIFT)
2398 
2399 /* Bitfield definition for register of struct array CTRL: INT_FLAG */
2400 /*
2401  * TRG_ERR3 (W1C)
2402  *
2403  * Trigger3 failed
2404  */
2405 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_MASK (0x80000000UL)
2406 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SHIFT (31U)
2407 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_MASK)
2408 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SHIFT)
2409 
2410 /*
2411  * TRG_ERR2 (W1C)
2412  *
2413  * Trigger2 failed
2414  */
2415 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_MASK (0x40000000UL)
2416 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SHIFT (30U)
2417 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_MASK)
2418 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SHIFT)
2419 
2420 /*
2421  * TRG_ERR1 (W1C)
2422  *
2423  * Trigger1 failed
2424  */
2425 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_MASK (0x20000000UL)
2426 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SHIFT (29U)
2427 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_MASK)
2428 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SHIFT)
2429 
2430 /*
2431  * TRG_ERR0 (W1C)
2432  *
2433  * Trigger0 failed
2434  */
2435 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_MASK (0x10000000UL)
2436 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SHIFT (28U)
2437 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_MASK)
2438 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SHIFT)
2439 
2440 /*
2441  * TRIGER3 (W1C)
2442  *
2443  * Trigger3
2444  */
2445 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_MASK (0x8000000UL)
2446 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SHIFT (27U)
2447 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER3_MASK)
2448 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER3_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SHIFT)
2449 
2450 /*
2451  * TRIGER2 (W1C)
2452  *
2453  * Trigger2
2454  */
2455 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_MASK (0x4000000UL)
2456 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SHIFT (26U)
2457 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER2_MASK)
2458 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER2_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SHIFT)
2459 
2460 /*
2461  * TRIGER1 (W1C)
2462  *
2463  * Trigger1
2464  */
2465 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_MASK (0x2000000UL)
2466 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SHIFT (25U)
2467 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER1_MASK)
2468 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER1_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SHIFT)
2469 
2470 /*
2471  * TRIGER0 (W1C)
2472  *
2473  * Trigger0
2474  */
2475 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_MASK (0x1000000UL)
2476 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SHIFT (24U)
2477 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER0_MASK)
2478 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER0_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SHIFT)
2479 
2480 /*
2481  * SMP_ERR (W1C)
2482  *
2483  * Sample error
2484  */
2485 #define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_MASK (0x100000UL)
2486 #define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SHIFT (20U)
2487 #define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_MASK)
2488 #define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_MASK) >> SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SHIFT)
2489 
2490 /*
2491  * LATCH3 (W1C)
2492  *
2493  * Latch3
2494  */
2495 #define SEI_CTRL_IRQ_INT_FLAG_LATCH3_MASK (0x80000UL)
2496 #define SEI_CTRL_IRQ_INT_FLAG_LATCH3_SHIFT (19U)
2497 #define SEI_CTRL_IRQ_INT_FLAG_LATCH3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH3_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH3_MASK)
2498 #define SEI_CTRL_IRQ_INT_FLAG_LATCH3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH3_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH3_SHIFT)
2499 
2500 /*
2501  * LATCH2 (W1C)
2502  *
2503  * Latch2
2504  */
2505 #define SEI_CTRL_IRQ_INT_FLAG_LATCH2_MASK (0x40000UL)
2506 #define SEI_CTRL_IRQ_INT_FLAG_LATCH2_SHIFT (18U)
2507 #define SEI_CTRL_IRQ_INT_FLAG_LATCH2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH2_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH2_MASK)
2508 #define SEI_CTRL_IRQ_INT_FLAG_LATCH2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH2_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH2_SHIFT)
2509 
2510 /*
2511  * LATCH1 (W1C)
2512  *
2513  * Latch1
2514  */
2515 #define SEI_CTRL_IRQ_INT_FLAG_LATCH1_MASK (0x20000UL)
2516 #define SEI_CTRL_IRQ_INT_FLAG_LATCH1_SHIFT (17U)
2517 #define SEI_CTRL_IRQ_INT_FLAG_LATCH1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH1_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH1_MASK)
2518 #define SEI_CTRL_IRQ_INT_FLAG_LATCH1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH1_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH1_SHIFT)
2519 
2520 /*
2521  * LATCH0 (W1C)
2522  *
2523  * Latch0
2524  */
2525 #define SEI_CTRL_IRQ_INT_FLAG_LATCH0_MASK (0x10000UL)
2526 #define SEI_CTRL_IRQ_INT_FLAG_LATCH0_SHIFT (16U)
2527 #define SEI_CTRL_IRQ_INT_FLAG_LATCH0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH0_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH0_MASK)
2528 #define SEI_CTRL_IRQ_INT_FLAG_LATCH0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH0_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH0_SHIFT)
2529 
2530 /*
2531  * TIMEOUT (W1C)
2532  *
2533  * Timeout
2534  */
2535 #define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_MASK (0x2000U)
2536 #define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SHIFT (13U)
2537 #define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_MASK)
2538 #define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SHIFT)
2539 
2540 /*
2541  * TRX_ERR (W1C)
2542  *
2543  * Transfer error
2544  */
2545 #define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_MASK (0x1000U)
2546 #define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SHIFT (12U)
2547 #define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_MASK)
2548 #define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SHIFT)
2549 
2550 /*
2551  * INSTR1_END (W1C)
2552  *
2553  * Instruction 1 end
2554  */
2555 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_MASK (0x800U)
2556 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SHIFT (11U)
2557 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_MASK)
2558 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SHIFT)
2559 
2560 /*
2561  * INSTR0_END (W1C)
2562  *
2563  * Instruction 0 end
2564  */
2565 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_MASK (0x400U)
2566 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SHIFT (10U)
2567 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_MASK)
2568 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SHIFT)
2569 
2570 /*
2571  * PTR1_END (W1C)
2572  *
2573  * Pointer 1 end
2574  */
2575 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_MASK (0x200U)
2576 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SHIFT (9U)
2577 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR1_END_MASK)
2578 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR1_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SHIFT)
2579 
2580 /*
2581  * PTR0_END (W1C)
2582  *
2583  * Pointer 0 end
2584  */
2585 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_MASK (0x100U)
2586 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SHIFT (8U)
2587 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR0_END_MASK)
2588 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR0_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SHIFT)
2589 
2590 /*
2591  * INSTR1_ST (W1C)
2592  *
2593  * Instruction 1 start
2594  */
2595 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_MASK (0x80U)
2596 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SHIFT (7U)
2597 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_MASK)
2598 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SHIFT)
2599 
2600 /*
2601  * INSTR0_ST (W1C)
2602  *
2603  * Instruction 0 start
2604  */
2605 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_MASK (0x40U)
2606 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SHIFT (6U)
2607 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_MASK)
2608 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SHIFT)
2609 
2610 /*
2611  * PTR1_ST (W1C)
2612  *
2613  * Pointer 1 start
2614  */
2615 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_MASK (0x20U)
2616 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SHIFT (5U)
2617 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_MASK)
2618 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SHIFT)
2619 
2620 /*
2621  * PTR0_ST (W1C)
2622  *
2623  * Pointer 0 start
2624  */
2625 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_MASK (0x10U)
2626 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SHIFT (4U)
2627 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_MASK)
2628 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SHIFT)
2629 
2630 /*
2631  * WDOG (W1C)
2632  *
2633  * Watch dog
2634  */
2635 #define SEI_CTRL_IRQ_INT_FLAG_WDOG_MASK (0x4U)
2636 #define SEI_CTRL_IRQ_INT_FLAG_WDOG_SHIFT (2U)
2637 #define SEI_CTRL_IRQ_INT_FLAG_WDOG_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_WDOG_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_WDOG_MASK)
2638 #define SEI_CTRL_IRQ_INT_FLAG_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_WDOG_MASK) >> SEI_CTRL_IRQ_INT_FLAG_WDOG_SHIFT)
2639 
2640 /*
2641  * EXCEPT (W1C)
2642  *
2643  * Exception
2644  */
2645 #define SEI_CTRL_IRQ_INT_FLAG_EXCEPT_MASK (0x2U)
2646 #define SEI_CTRL_IRQ_INT_FLAG_EXCEPT_SHIFT (1U)
2647 #define SEI_CTRL_IRQ_INT_FLAG_EXCEPT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_EXCEPT_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_EXCEPT_MASK)
2648 #define SEI_CTRL_IRQ_INT_FLAG_EXCEPT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_EXCEPT_MASK) >> SEI_CTRL_IRQ_INT_FLAG_EXCEPT_SHIFT)
2649 
2650 /*
2651  * STALL (W1C)
2652  *
2653  * Stall
2654  */
2655 #define SEI_CTRL_IRQ_INT_FLAG_STALL_MASK (0x1U)
2656 #define SEI_CTRL_IRQ_INT_FLAG_STALL_SHIFT (0U)
2657 #define SEI_CTRL_IRQ_INT_FLAG_STALL_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_STALL_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_STALL_MASK)
2658 #define SEI_CTRL_IRQ_INT_FLAG_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_STALL_MASK) >> SEI_CTRL_IRQ_INT_FLAG_STALL_SHIFT)
2659 
2660 /* Bitfield definition for register of struct array CTRL: INT_STS */
2661 /*
2662  * TRG_ERR3 (RO)
2663  *
2664  * Trigger3 failed
2665  */
2666 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR3_MASK (0x80000000UL)
2667 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR3_SHIFT (31U)
2668 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR3_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR3_SHIFT)
2669 
2670 /*
2671  * TRG_ERR2 (RO)
2672  *
2673  * Trigger2 failed
2674  */
2675 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR2_MASK (0x40000000UL)
2676 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR2_SHIFT (30U)
2677 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR2_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR2_SHIFT)
2678 
2679 /*
2680  * TRG_ERR1 (RO)
2681  *
2682  * Trigger1 failed
2683  */
2684 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR1_MASK (0x20000000UL)
2685 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR1_SHIFT (29U)
2686 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR1_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR1_SHIFT)
2687 
2688 /*
2689  * TRG_ERR0 (RO)
2690  *
2691  * Trigger0 failed
2692  */
2693 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR0_MASK (0x10000000UL)
2694 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR0_SHIFT (28U)
2695 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR0_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR0_SHIFT)
2696 
2697 /*
2698  * TRIGER3 (RO)
2699  *
2700  * Trigger3
2701  */
2702 #define SEI_CTRL_IRQ_INT_STS_TRIGER3_MASK (0x8000000UL)
2703 #define SEI_CTRL_IRQ_INT_STS_TRIGER3_SHIFT (27U)
2704 #define SEI_CTRL_IRQ_INT_STS_TRIGER3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER3_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER3_SHIFT)
2705 
2706 /*
2707  * TRIGER2 (RO)
2708  *
2709  * Trigger2
2710  */
2711 #define SEI_CTRL_IRQ_INT_STS_TRIGER2_MASK (0x4000000UL)
2712 #define SEI_CTRL_IRQ_INT_STS_TRIGER2_SHIFT (26U)
2713 #define SEI_CTRL_IRQ_INT_STS_TRIGER2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER2_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER2_SHIFT)
2714 
2715 /*
2716  * TRIGER1 (RO)
2717  *
2718  * Trigger1
2719  */
2720 #define SEI_CTRL_IRQ_INT_STS_TRIGER1_MASK (0x2000000UL)
2721 #define SEI_CTRL_IRQ_INT_STS_TRIGER1_SHIFT (25U)
2722 #define SEI_CTRL_IRQ_INT_STS_TRIGER1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER1_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER1_SHIFT)
2723 
2724 /*
2725  * TRIGER0 (RO)
2726  *
2727  * Trigger0
2728  */
2729 #define SEI_CTRL_IRQ_INT_STS_TRIGER0_MASK (0x1000000UL)
2730 #define SEI_CTRL_IRQ_INT_STS_TRIGER0_SHIFT (24U)
2731 #define SEI_CTRL_IRQ_INT_STS_TRIGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER0_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER0_SHIFT)
2732 
2733 /*
2734  * SMP_ERR (RO)
2735  *
2736  * Sample error
2737  */
2738 #define SEI_CTRL_IRQ_INT_STS_SMP_ERR_MASK (0x100000UL)
2739 #define SEI_CTRL_IRQ_INT_STS_SMP_ERR_SHIFT (20U)
2740 #define SEI_CTRL_IRQ_INT_STS_SMP_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_SMP_ERR_MASK) >> SEI_CTRL_IRQ_INT_STS_SMP_ERR_SHIFT)
2741 
2742 /*
2743  * LATCH3 (RO)
2744  *
2745  * Latch3
2746  */
2747 #define SEI_CTRL_IRQ_INT_STS_LATCH3_MASK (0x80000UL)
2748 #define SEI_CTRL_IRQ_INT_STS_LATCH3_SHIFT (19U)
2749 #define SEI_CTRL_IRQ_INT_STS_LATCH3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH3_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH3_SHIFT)
2750 
2751 /*
2752  * LATCH2 (RO)
2753  *
2754  * Latch2
2755  */
2756 #define SEI_CTRL_IRQ_INT_STS_LATCH2_MASK (0x40000UL)
2757 #define SEI_CTRL_IRQ_INT_STS_LATCH2_SHIFT (18U)
2758 #define SEI_CTRL_IRQ_INT_STS_LATCH2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH2_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH2_SHIFT)
2759 
2760 /*
2761  * LATCH1 (RO)
2762  *
2763  * Latch1
2764  */
2765 #define SEI_CTRL_IRQ_INT_STS_LATCH1_MASK (0x20000UL)
2766 #define SEI_CTRL_IRQ_INT_STS_LATCH1_SHIFT (17U)
2767 #define SEI_CTRL_IRQ_INT_STS_LATCH1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH1_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH1_SHIFT)
2768 
2769 /*
2770  * LATCH0 (RO)
2771  *
2772  * Latch0
2773  */
2774 #define SEI_CTRL_IRQ_INT_STS_LATCH0_MASK (0x10000UL)
2775 #define SEI_CTRL_IRQ_INT_STS_LATCH0_SHIFT (16U)
2776 #define SEI_CTRL_IRQ_INT_STS_LATCH0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH0_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH0_SHIFT)
2777 
2778 /*
2779  * TIMEOUT (RO)
2780  *
2781  * Timeout
2782  */
2783 #define SEI_CTRL_IRQ_INT_STS_TIMEOUT_MASK (0x2000U)
2784 #define SEI_CTRL_IRQ_INT_STS_TIMEOUT_SHIFT (13U)
2785 #define SEI_CTRL_IRQ_INT_STS_TIMEOUT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TIMEOUT_MASK) >> SEI_CTRL_IRQ_INT_STS_TIMEOUT_SHIFT)
2786 
2787 /*
2788  * TRX_ERR (RO)
2789  *
2790  * Transfer error
2791  */
2792 #define SEI_CTRL_IRQ_INT_STS_TRX_ERR_MASK (0x1000U)
2793 #define SEI_CTRL_IRQ_INT_STS_TRX_ERR_SHIFT (12U)
2794 #define SEI_CTRL_IRQ_INT_STS_TRX_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRX_ERR_MASK) >> SEI_CTRL_IRQ_INT_STS_TRX_ERR_SHIFT)
2795 
2796 /*
2797  * INSTR1_END (RO)
2798  *
2799  * Instruction 1 end
2800  */
2801 #define SEI_CTRL_IRQ_INT_STS_INSTR1_END_MASK (0x800U)
2802 #define SEI_CTRL_IRQ_INT_STS_INSTR1_END_SHIFT (11U)
2803 #define SEI_CTRL_IRQ_INT_STS_INSTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR1_END_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR1_END_SHIFT)
2804 
2805 /*
2806  * INSTR0_END (RO)
2807  *
2808  * Instruction 0 end
2809  */
2810 #define SEI_CTRL_IRQ_INT_STS_INSTR0_END_MASK (0x400U)
2811 #define SEI_CTRL_IRQ_INT_STS_INSTR0_END_SHIFT (10U)
2812 #define SEI_CTRL_IRQ_INT_STS_INSTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR0_END_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR0_END_SHIFT)
2813 
2814 /*
2815  * PTR1_END (RO)
2816  *
2817  * Pointer 1 end
2818  */
2819 #define SEI_CTRL_IRQ_INT_STS_PTR1_END_MASK (0x200U)
2820 #define SEI_CTRL_IRQ_INT_STS_PTR1_END_SHIFT (9U)
2821 #define SEI_CTRL_IRQ_INT_STS_PTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR1_END_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR1_END_SHIFT)
2822 
2823 /*
2824  * PTR0_END (RO)
2825  *
2826  * Pointer 0 end
2827  */
2828 #define SEI_CTRL_IRQ_INT_STS_PTR0_END_MASK (0x100U)
2829 #define SEI_CTRL_IRQ_INT_STS_PTR0_END_SHIFT (8U)
2830 #define SEI_CTRL_IRQ_INT_STS_PTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR0_END_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR0_END_SHIFT)
2831 
2832 /*
2833  * INSTR1_ST (RO)
2834  *
2835  * Instruction 1 start
2836  */
2837 #define SEI_CTRL_IRQ_INT_STS_INSTR1_ST_MASK (0x80U)
2838 #define SEI_CTRL_IRQ_INT_STS_INSTR1_ST_SHIFT (7U)
2839 #define SEI_CTRL_IRQ_INT_STS_INSTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR1_ST_SHIFT)
2840 
2841 /*
2842  * INSTR0_ST (RO)
2843  *
2844  * Instruction 0 start
2845  */
2846 #define SEI_CTRL_IRQ_INT_STS_INSTR0_ST_MASK (0x40U)
2847 #define SEI_CTRL_IRQ_INT_STS_INSTR0_ST_SHIFT (6U)
2848 #define SEI_CTRL_IRQ_INT_STS_INSTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR0_ST_SHIFT)
2849 
2850 /*
2851  * PTR1_ST (RO)
2852  *
2853  * Pointer 1 start
2854  */
2855 #define SEI_CTRL_IRQ_INT_STS_PTR1_ST_MASK (0x20U)
2856 #define SEI_CTRL_IRQ_INT_STS_PTR1_ST_SHIFT (5U)
2857 #define SEI_CTRL_IRQ_INT_STS_PTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR1_ST_SHIFT)
2858 
2859 /*
2860  * PTR0_ST (RO)
2861  *
2862  * Pointer 0 start
2863  */
2864 #define SEI_CTRL_IRQ_INT_STS_PTR0_ST_MASK (0x10U)
2865 #define SEI_CTRL_IRQ_INT_STS_PTR0_ST_SHIFT (4U)
2866 #define SEI_CTRL_IRQ_INT_STS_PTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR0_ST_SHIFT)
2867 
2868 /*
2869  * WDOG (RO)
2870  *
2871  * Watch dog
2872  */
2873 #define SEI_CTRL_IRQ_INT_STS_WDOG_MASK (0x4U)
2874 #define SEI_CTRL_IRQ_INT_STS_WDOG_SHIFT (2U)
2875 #define SEI_CTRL_IRQ_INT_STS_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_WDOG_MASK) >> SEI_CTRL_IRQ_INT_STS_WDOG_SHIFT)
2876 
2877 /*
2878  * EXCEPT (RO)
2879  *
2880  * Exception
2881  */
2882 #define SEI_CTRL_IRQ_INT_STS_EXCEPT_MASK (0x2U)
2883 #define SEI_CTRL_IRQ_INT_STS_EXCEPT_SHIFT (1U)
2884 #define SEI_CTRL_IRQ_INT_STS_EXCEPT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_EXCEPT_MASK) >> SEI_CTRL_IRQ_INT_STS_EXCEPT_SHIFT)
2885 
2886 /*
2887  * STALL (RO)
2888  *
2889  * Stall
2890  */
2891 #define SEI_CTRL_IRQ_INT_STS_STALL_MASK (0x1U)
2892 #define SEI_CTRL_IRQ_INT_STS_STALL_SHIFT (0U)
2893 #define SEI_CTRL_IRQ_INT_STS_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_STALL_MASK) >> SEI_CTRL_IRQ_INT_STS_STALL_SHIFT)
2894 
2895 /* Bitfield definition for register of struct array CTRL: POINTER0 */
2896 /*
2897  * POINTER (RW)
2898  *
2899  * Match pointer 0
2900  */
2901 #define SEI_CTRL_IRQ_POINTER0_POINTER_MASK (0xFFU)
2902 #define SEI_CTRL_IRQ_POINTER0_POINTER_SHIFT (0U)
2903 #define SEI_CTRL_IRQ_POINTER0_POINTER_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_POINTER0_POINTER_SHIFT) & SEI_CTRL_IRQ_POINTER0_POINTER_MASK)
2904 #define SEI_CTRL_IRQ_POINTER0_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_POINTER0_POINTER_MASK) >> SEI_CTRL_IRQ_POINTER0_POINTER_SHIFT)
2905 
2906 /* Bitfield definition for register of struct array CTRL: POINTER1 */
2907 /*
2908  * POINTER (RW)
2909  *
2910  * Match pointer 1
2911  */
2912 #define SEI_CTRL_IRQ_POINTER1_POINTER_MASK (0xFFU)
2913 #define SEI_CTRL_IRQ_POINTER1_POINTER_SHIFT (0U)
2914 #define SEI_CTRL_IRQ_POINTER1_POINTER_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_POINTER1_POINTER_SHIFT) & SEI_CTRL_IRQ_POINTER1_POINTER_MASK)
2915 #define SEI_CTRL_IRQ_POINTER1_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_POINTER1_POINTER_MASK) >> SEI_CTRL_IRQ_POINTER1_POINTER_SHIFT)
2916 
2917 /* Bitfield definition for register of struct array CTRL: INSTR0 */
2918 /*
2919  * INSTR (RW)
2920  *
2921  * Match instruction 0
2922  */
2923 #define SEI_CTRL_IRQ_INSTR0_INSTR_MASK (0xFFFFFFFFUL)
2924 #define SEI_CTRL_IRQ_INSTR0_INSTR_SHIFT (0U)
2925 #define SEI_CTRL_IRQ_INSTR0_INSTR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INSTR0_INSTR_SHIFT) & SEI_CTRL_IRQ_INSTR0_INSTR_MASK)
2926 #define SEI_CTRL_IRQ_INSTR0_INSTR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INSTR0_INSTR_MASK) >> SEI_CTRL_IRQ_INSTR0_INSTR_SHIFT)
2927 
2928 /* Bitfield definition for register of struct array CTRL: INSTR1 */
2929 /*
2930  * INSTR (RW)
2931  *
2932  * Match instruction 1
2933  */
2934 #define SEI_CTRL_IRQ_INSTR1_INSTR_MASK (0xFFFFFFFFUL)
2935 #define SEI_CTRL_IRQ_INSTR1_INSTR_SHIFT (0U)
2936 #define SEI_CTRL_IRQ_INSTR1_INSTR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INSTR1_INSTR_SHIFT) & SEI_CTRL_IRQ_INSTR1_INSTR_MASK)
2937 #define SEI_CTRL_IRQ_INSTR1_INSTR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INSTR1_INSTR_MASK) >> SEI_CTRL_IRQ_INSTR1_INSTR_SHIFT)
2938 
2939 /* Bitfield definition for register of struct array CTRL: DMA_EN */
2940 /*
2941  * TRG_ERR3 (RW)
2942  *
2943  * Trigger3 failed
2944  */
2945 #define SEI_CTRL_DMA_EN_TRG_ERR3_MASK (0x80000000UL)
2946 #define SEI_CTRL_DMA_EN_TRG_ERR3_SHIFT (31U)
2947 #define SEI_CTRL_DMA_EN_TRG_ERR3_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRG_ERR3_SHIFT) & SEI_CTRL_DMA_EN_TRG_ERR3_MASK)
2948 #define SEI_CTRL_DMA_EN_TRG_ERR3_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRG_ERR3_MASK) >> SEI_CTRL_DMA_EN_TRG_ERR3_SHIFT)
2949 
2950 /*
2951  * TRG_ERR2 (RW)
2952  *
2953  * Trigger2 failed
2954  */
2955 #define SEI_CTRL_DMA_EN_TRG_ERR2_MASK (0x40000000UL)
2956 #define SEI_CTRL_DMA_EN_TRG_ERR2_SHIFT (30U)
2957 #define SEI_CTRL_DMA_EN_TRG_ERR2_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRG_ERR2_SHIFT) & SEI_CTRL_DMA_EN_TRG_ERR2_MASK)
2958 #define SEI_CTRL_DMA_EN_TRG_ERR2_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRG_ERR2_MASK) >> SEI_CTRL_DMA_EN_TRG_ERR2_SHIFT)
2959 
2960 /*
2961  * TRG_ERR1 (RW)
2962  *
2963  * Trigger1 failed
2964  */
2965 #define SEI_CTRL_DMA_EN_TRG_ERR1_MASK (0x20000000UL)
2966 #define SEI_CTRL_DMA_EN_TRG_ERR1_SHIFT (29U)
2967 #define SEI_CTRL_DMA_EN_TRG_ERR1_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRG_ERR1_SHIFT) & SEI_CTRL_DMA_EN_TRG_ERR1_MASK)
2968 #define SEI_CTRL_DMA_EN_TRG_ERR1_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRG_ERR1_MASK) >> SEI_CTRL_DMA_EN_TRG_ERR1_SHIFT)
2969 
2970 /*
2971  * TRG_ERR0 (RW)
2972  *
2973  * Trigger0 failed
2974  */
2975 #define SEI_CTRL_DMA_EN_TRG_ERR0_MASK (0x10000000UL)
2976 #define SEI_CTRL_DMA_EN_TRG_ERR0_SHIFT (28U)
2977 #define SEI_CTRL_DMA_EN_TRG_ERR0_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRG_ERR0_SHIFT) & SEI_CTRL_DMA_EN_TRG_ERR0_MASK)
2978 #define SEI_CTRL_DMA_EN_TRG_ERR0_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRG_ERR0_MASK) >> SEI_CTRL_DMA_EN_TRG_ERR0_SHIFT)
2979 
2980 /*
2981  * TRIGER3 (RW)
2982  *
2983  * Trigger3
2984  */
2985 #define SEI_CTRL_DMA_EN_TRIGER3_MASK (0x8000000UL)
2986 #define SEI_CTRL_DMA_EN_TRIGER3_SHIFT (27U)
2987 #define SEI_CTRL_DMA_EN_TRIGER3_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRIGER3_SHIFT) & SEI_CTRL_DMA_EN_TRIGER3_MASK)
2988 #define SEI_CTRL_DMA_EN_TRIGER3_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRIGER3_MASK) >> SEI_CTRL_DMA_EN_TRIGER3_SHIFT)
2989 
2990 /*
2991  * TRIGER2 (RW)
2992  *
2993  * Trigger2
2994  */
2995 #define SEI_CTRL_DMA_EN_TRIGER2_MASK (0x4000000UL)
2996 #define SEI_CTRL_DMA_EN_TRIGER2_SHIFT (26U)
2997 #define SEI_CTRL_DMA_EN_TRIGER2_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRIGER2_SHIFT) & SEI_CTRL_DMA_EN_TRIGER2_MASK)
2998 #define SEI_CTRL_DMA_EN_TRIGER2_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRIGER2_MASK) >> SEI_CTRL_DMA_EN_TRIGER2_SHIFT)
2999 
3000 /*
3001  * TRIGER1 (RW)
3002  *
3003  * Trigger1
3004  */
3005 #define SEI_CTRL_DMA_EN_TRIGER1_MASK (0x2000000UL)
3006 #define SEI_CTRL_DMA_EN_TRIGER1_SHIFT (25U)
3007 #define SEI_CTRL_DMA_EN_TRIGER1_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRIGER1_SHIFT) & SEI_CTRL_DMA_EN_TRIGER1_MASK)
3008 #define SEI_CTRL_DMA_EN_TRIGER1_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRIGER1_MASK) >> SEI_CTRL_DMA_EN_TRIGER1_SHIFT)
3009 
3010 /*
3011  * TRIGER0 (RW)
3012  *
3013  * Trigger0
3014  */
3015 #define SEI_CTRL_DMA_EN_TRIGER0_MASK (0x1000000UL)
3016 #define SEI_CTRL_DMA_EN_TRIGER0_SHIFT (24U)
3017 #define SEI_CTRL_DMA_EN_TRIGER0_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRIGER0_SHIFT) & SEI_CTRL_DMA_EN_TRIGER0_MASK)
3018 #define SEI_CTRL_DMA_EN_TRIGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRIGER0_MASK) >> SEI_CTRL_DMA_EN_TRIGER0_SHIFT)
3019 
3020 /*
3021  * SMP_ERR (RW)
3022  *
3023  * Sample error
3024  */
3025 #define SEI_CTRL_DMA_EN_SMP_ERR_MASK (0x100000UL)
3026 #define SEI_CTRL_DMA_EN_SMP_ERR_SHIFT (20U)
3027 #define SEI_CTRL_DMA_EN_SMP_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_SMP_ERR_SHIFT) & SEI_CTRL_DMA_EN_SMP_ERR_MASK)
3028 #define SEI_CTRL_DMA_EN_SMP_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_SMP_ERR_MASK) >> SEI_CTRL_DMA_EN_SMP_ERR_SHIFT)
3029 
3030 /*
3031  * LATCH3 (RW)
3032  *
3033  * Latch3
3034  */
3035 #define SEI_CTRL_DMA_EN_LATCH3_MASK (0x80000UL)
3036 #define SEI_CTRL_DMA_EN_LATCH3_SHIFT (19U)
3037 #define SEI_CTRL_DMA_EN_LATCH3_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_LATCH3_SHIFT) & SEI_CTRL_DMA_EN_LATCH3_MASK)
3038 #define SEI_CTRL_DMA_EN_LATCH3_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_LATCH3_MASK) >> SEI_CTRL_DMA_EN_LATCH3_SHIFT)
3039 
3040 /*
3041  * LATCH2 (RW)
3042  *
3043  * Latch2
3044  */
3045 #define SEI_CTRL_DMA_EN_LATCH2_MASK (0x40000UL)
3046 #define SEI_CTRL_DMA_EN_LATCH2_SHIFT (18U)
3047 #define SEI_CTRL_DMA_EN_LATCH2_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_LATCH2_SHIFT) & SEI_CTRL_DMA_EN_LATCH2_MASK)
3048 #define SEI_CTRL_DMA_EN_LATCH2_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_LATCH2_MASK) >> SEI_CTRL_DMA_EN_LATCH2_SHIFT)
3049 
3050 /*
3051  * LATCH1 (RW)
3052  *
3053  * Latch1
3054  */
3055 #define SEI_CTRL_DMA_EN_LATCH1_MASK (0x20000UL)
3056 #define SEI_CTRL_DMA_EN_LATCH1_SHIFT (17U)
3057 #define SEI_CTRL_DMA_EN_LATCH1_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_LATCH1_SHIFT) & SEI_CTRL_DMA_EN_LATCH1_MASK)
3058 #define SEI_CTRL_DMA_EN_LATCH1_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_LATCH1_MASK) >> SEI_CTRL_DMA_EN_LATCH1_SHIFT)
3059 
3060 /*
3061  * LATCH0 (RW)
3062  *
3063  * Latch0
3064  */
3065 #define SEI_CTRL_DMA_EN_LATCH0_MASK (0x10000UL)
3066 #define SEI_CTRL_DMA_EN_LATCH0_SHIFT (16U)
3067 #define SEI_CTRL_DMA_EN_LATCH0_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_LATCH0_SHIFT) & SEI_CTRL_DMA_EN_LATCH0_MASK)
3068 #define SEI_CTRL_DMA_EN_LATCH0_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_LATCH0_MASK) >> SEI_CTRL_DMA_EN_LATCH0_SHIFT)
3069 
3070 /*
3071  * TIMEOUT (RW)
3072  *
3073  * Timeout
3074  */
3075 #define SEI_CTRL_DMA_EN_TIMEOUT_MASK (0x2000U)
3076 #define SEI_CTRL_DMA_EN_TIMEOUT_SHIFT (13U)
3077 #define SEI_CTRL_DMA_EN_TIMEOUT_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TIMEOUT_SHIFT) & SEI_CTRL_DMA_EN_TIMEOUT_MASK)
3078 #define SEI_CTRL_DMA_EN_TIMEOUT_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TIMEOUT_MASK) >> SEI_CTRL_DMA_EN_TIMEOUT_SHIFT)
3079 
3080 /*
3081  * TRX_ERR (RW)
3082  *
3083  * Transfer error
3084  */
3085 #define SEI_CTRL_DMA_EN_TRX_ERR_MASK (0x1000U)
3086 #define SEI_CTRL_DMA_EN_TRX_ERR_SHIFT (12U)
3087 #define SEI_CTRL_DMA_EN_TRX_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRX_ERR_SHIFT) & SEI_CTRL_DMA_EN_TRX_ERR_MASK)
3088 #define SEI_CTRL_DMA_EN_TRX_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRX_ERR_MASK) >> SEI_CTRL_DMA_EN_TRX_ERR_SHIFT)
3089 
3090 /*
3091  * INSTR1_END (RW)
3092  *
3093  * Instruction 1 end
3094  */
3095 #define SEI_CTRL_DMA_EN_INSTR1_END_MASK (0x800U)
3096 #define SEI_CTRL_DMA_EN_INSTR1_END_SHIFT (11U)
3097 #define SEI_CTRL_DMA_EN_INSTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_INSTR1_END_SHIFT) & SEI_CTRL_DMA_EN_INSTR1_END_MASK)
3098 #define SEI_CTRL_DMA_EN_INSTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_INSTR1_END_MASK) >> SEI_CTRL_DMA_EN_INSTR1_END_SHIFT)
3099 
3100 /*
3101  * INSTR0_END (RW)
3102  *
3103  * Instruction 0 end
3104  */
3105 #define SEI_CTRL_DMA_EN_INSTR0_END_MASK (0x400U)
3106 #define SEI_CTRL_DMA_EN_INSTR0_END_SHIFT (10U)
3107 #define SEI_CTRL_DMA_EN_INSTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_INSTR0_END_SHIFT) & SEI_CTRL_DMA_EN_INSTR0_END_MASK)
3108 #define SEI_CTRL_DMA_EN_INSTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_INSTR0_END_MASK) >> SEI_CTRL_DMA_EN_INSTR0_END_SHIFT)
3109 
3110 /*
3111  * PTR1_END (RW)
3112  *
3113  * Pointer 1 end
3114  */
3115 #define SEI_CTRL_DMA_EN_PTR1_END_MASK (0x200U)
3116 #define SEI_CTRL_DMA_EN_PTR1_END_SHIFT (9U)
3117 #define SEI_CTRL_DMA_EN_PTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_PTR1_END_SHIFT) & SEI_CTRL_DMA_EN_PTR1_END_MASK)
3118 #define SEI_CTRL_DMA_EN_PTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_PTR1_END_MASK) >> SEI_CTRL_DMA_EN_PTR1_END_SHIFT)
3119 
3120 /*
3121  * PTR0_END (RW)
3122  *
3123  * Pointer 0 end
3124  */
3125 #define SEI_CTRL_DMA_EN_PTR0_END_MASK (0x100U)
3126 #define SEI_CTRL_DMA_EN_PTR0_END_SHIFT (8U)
3127 #define SEI_CTRL_DMA_EN_PTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_PTR0_END_SHIFT) & SEI_CTRL_DMA_EN_PTR0_END_MASK)
3128 #define SEI_CTRL_DMA_EN_PTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_PTR0_END_MASK) >> SEI_CTRL_DMA_EN_PTR0_END_SHIFT)
3129 
3130 /*
3131  * INSTR1_ST (RW)
3132  *
3133  * Instruction 1 start
3134  */
3135 #define SEI_CTRL_DMA_EN_INSTR1_ST_MASK (0x80U)
3136 #define SEI_CTRL_DMA_EN_INSTR1_ST_SHIFT (7U)
3137 #define SEI_CTRL_DMA_EN_INSTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_INSTR1_ST_SHIFT) & SEI_CTRL_DMA_EN_INSTR1_ST_MASK)
3138 #define SEI_CTRL_DMA_EN_INSTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_INSTR1_ST_MASK) >> SEI_CTRL_DMA_EN_INSTR1_ST_SHIFT)
3139 
3140 /*
3141  * INSTR0_ST (RW)
3142  *
3143  * Instruction 0 start
3144  */
3145 #define SEI_CTRL_DMA_EN_INSTR0_ST_MASK (0x40U)
3146 #define SEI_CTRL_DMA_EN_INSTR0_ST_SHIFT (6U)
3147 #define SEI_CTRL_DMA_EN_INSTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_INSTR0_ST_SHIFT) & SEI_CTRL_DMA_EN_INSTR0_ST_MASK)
3148 #define SEI_CTRL_DMA_EN_INSTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_INSTR0_ST_MASK) >> SEI_CTRL_DMA_EN_INSTR0_ST_SHIFT)
3149 
3150 /*
3151  * PTR1_ST (RW)
3152  *
3153  * Pointer 1 start
3154  */
3155 #define SEI_CTRL_DMA_EN_PTR1_ST_MASK (0x20U)
3156 #define SEI_CTRL_DMA_EN_PTR1_ST_SHIFT (5U)
3157 #define SEI_CTRL_DMA_EN_PTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_PTR1_ST_SHIFT) & SEI_CTRL_DMA_EN_PTR1_ST_MASK)
3158 #define SEI_CTRL_DMA_EN_PTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_PTR1_ST_MASK) >> SEI_CTRL_DMA_EN_PTR1_ST_SHIFT)
3159 
3160 /*
3161  * PTR0_ST (RW)
3162  *
3163  * Pointer 0 start
3164  */
3165 #define SEI_CTRL_DMA_EN_PTR0_ST_MASK (0x10U)
3166 #define SEI_CTRL_DMA_EN_PTR0_ST_SHIFT (4U)
3167 #define SEI_CTRL_DMA_EN_PTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_PTR0_ST_SHIFT) & SEI_CTRL_DMA_EN_PTR0_ST_MASK)
3168 #define SEI_CTRL_DMA_EN_PTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_PTR0_ST_MASK) >> SEI_CTRL_DMA_EN_PTR0_ST_SHIFT)
3169 
3170 /*
3171  * WDOG (RW)
3172  *
3173  * Watch dog
3174  */
3175 #define SEI_CTRL_DMA_EN_WDOG_MASK (0x4U)
3176 #define SEI_CTRL_DMA_EN_WDOG_SHIFT (2U)
3177 #define SEI_CTRL_DMA_EN_WDOG_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_WDOG_SHIFT) & SEI_CTRL_DMA_EN_WDOG_MASK)
3178 #define SEI_CTRL_DMA_EN_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_WDOG_MASK) >> SEI_CTRL_DMA_EN_WDOG_SHIFT)
3179 
3180 /*
3181  * EXCEPT (RW)
3182  *
3183  * Exception
3184  */
3185 #define SEI_CTRL_DMA_EN_EXCEPT_MASK (0x2U)
3186 #define SEI_CTRL_DMA_EN_EXCEPT_SHIFT (1U)
3187 #define SEI_CTRL_DMA_EN_EXCEPT_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_EXCEPT_SHIFT) & SEI_CTRL_DMA_EN_EXCEPT_MASK)
3188 #define SEI_CTRL_DMA_EN_EXCEPT_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_EXCEPT_MASK) >> SEI_CTRL_DMA_EN_EXCEPT_SHIFT)
3189 
3190 /*
3191  * STALL (RW)
3192  *
3193  * Stall
3194  */
3195 #define SEI_CTRL_DMA_EN_STALL_MASK (0x1U)
3196 #define SEI_CTRL_DMA_EN_STALL_SHIFT (0U)
3197 #define SEI_CTRL_DMA_EN_STALL_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_STALL_SHIFT) & SEI_CTRL_DMA_EN_STALL_MASK)
3198 #define SEI_CTRL_DMA_EN_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_STALL_MASK) >> SEI_CTRL_DMA_EN_STALL_SHIFT)
3199 
3200 /* Bitfield definition for register array: INSTR */
3201 /*
3202  * OP (RW)
3203  *
3204  * operation
3205  * 0: halt
3206  * 1: jump
3207  * 2: send with timeout check
3208  * 3: send without timout check
3209  * 4: wait with timeout check
3210  * 5: wait without timout check
3211  * 6: receive with timeout check
3212  * 7: receive without timout check
3213  */
3214 #define SEI_INSTR_OP_MASK (0x1C000000UL)
3215 #define SEI_INSTR_OP_SHIFT (26U)
3216 #define SEI_INSTR_OP_SET(x) (((uint32_t)(x) << SEI_INSTR_OP_SHIFT) & SEI_INSTR_OP_MASK)
3217 #define SEI_INSTR_OP_GET(x) (((uint32_t)(x) & SEI_INSTR_OP_MASK) >> SEI_INSTR_OP_SHIFT)
3218 
3219 /*
3220  * CK (RW)
3221  *
3222  * clock
3223  * 0: low
3224  * 1: rise-fall
3225  * 2: fall-rise
3226  * 3: high
3227  */
3228 #define SEI_INSTR_CK_MASK (0x3000000UL)
3229 #define SEI_INSTR_CK_SHIFT (24U)
3230 #define SEI_INSTR_CK_SET(x) (((uint32_t)(x) << SEI_INSTR_CK_SHIFT) & SEI_INSTR_CK_MASK)
3231 #define SEI_INSTR_CK_GET(x) (((uint32_t)(x) & SEI_INSTR_CK_MASK) >> SEI_INSTR_CK_SHIFT)
3232 
3233 /*
3234  * CRC (RW)
3235  *
3236  * CRC register
3237  * 0: don't calculate CRC
3238  * 1: do not set this value
3239  * 2: data register 2
3240  * 3: data register 3
3241  * ...
3242  * 29: data register 29
3243  * 30: value 0 when send, wait 0 in receive
3244  * 31: value1 when send, wait 1 in receive
3245  */
3246 #define SEI_INSTR_CRC_MASK (0x1F0000UL)
3247 #define SEI_INSTR_CRC_SHIFT (16U)
3248 #define SEI_INSTR_CRC_SET(x) (((uint32_t)(x) << SEI_INSTR_CRC_SHIFT) & SEI_INSTR_CRC_MASK)
3249 #define SEI_INSTR_CRC_GET(x) (((uint32_t)(x) & SEI_INSTR_CRC_MASK) >> SEI_INSTR_CRC_SHIFT)
3250 
3251 /*
3252  * DAT (RW)
3253  *
3254  * DATA register
3255  * 0: ignore data
3256  * 1: command
3257  * 2: data register 2
3258  * 3: data register 3
3259  * ...
3260  * 29: data register 29
3261  * 30: value 0 when send, wait 0 in receive
3262  * 31: value1 when send, wait 1 in receive
3263  */
3264 #define SEI_INSTR_DAT_MASK (0x1F00U)
3265 #define SEI_INSTR_DAT_SHIFT (8U)
3266 #define SEI_INSTR_DAT_SET(x) (((uint32_t)(x) << SEI_INSTR_DAT_SHIFT) & SEI_INSTR_DAT_MASK)
3267 #define SEI_INSTR_DAT_GET(x) (((uint32_t)(x) & SEI_INSTR_DAT_MASK) >> SEI_INSTR_DAT_SHIFT)
3268 
3269 /*
3270  * OPR (RW)
3271  *
3272  * a. When OP is 0, this area is the halt time in baudrate, 0 represents infinite time.
3273  * b. When OP is 1, this area is the the pointer to the command table.
3274  * OPR[4]=1, OPR[3:0] value is CMD_TABLE instruct pointer;
3275  * OPR[4]=0, OPR[3:0]=0 is INIT_POINTER;
3276  * OPR[4]=0, OPR[3:0]=1 is WDG_POINTER.
3277  * c. When OP is 2-7, this area is the data length as fellow:
3278  * 0: 1 bit
3279  * 1: 2 bit
3280  * ...
3281  * 31: 32 bit
3282  */
3283 #define SEI_INSTR_OPR_MASK (0x1FU)
3284 #define SEI_INSTR_OPR_SHIFT (0U)
3285 #define SEI_INSTR_OPR_SET(x) (((uint32_t)(x) << SEI_INSTR_OPR_SHIFT) & SEI_INSTR_OPR_MASK)
3286 #define SEI_INSTR_OPR_GET(x) (((uint32_t)(x) & SEI_INSTR_OPR_MASK) >> SEI_INSTR_OPR_SHIFT)
3287 
3288 /* Bitfield definition for register of struct array DAT: MODE */
3289 /*
3290  * CRC_LEN (RW)
3291  *
3292  * CRC length
3293  * 0: 1 bit
3294  * 1: 2 bit
3295  * ...
3296  * 31: 32 bit
3297  */
3298 #define SEI_DAT_MODE_CRC_LEN_MASK (0x1F000000UL)
3299 #define SEI_DAT_MODE_CRC_LEN_SHIFT (24U)
3300 #define SEI_DAT_MODE_CRC_LEN_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_CRC_LEN_SHIFT) & SEI_DAT_MODE_CRC_LEN_MASK)
3301 #define SEI_DAT_MODE_CRC_LEN_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_CRC_LEN_MASK) >> SEI_DAT_MODE_CRC_LEN_SHIFT)
3302 
3303 /*
3304  * WLEN (RW)
3305  *
3306  * word length
3307  * 0: 1 bit
3308  * 1: 2 bit
3309  * ...
3310  * 31: 32 bit
3311  */
3312 #define SEI_DAT_MODE_WLEN_MASK (0x1F0000UL)
3313 #define SEI_DAT_MODE_WLEN_SHIFT (16U)
3314 #define SEI_DAT_MODE_WLEN_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_WLEN_SHIFT) & SEI_DAT_MODE_WLEN_MASK)
3315 #define SEI_DAT_MODE_WLEN_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_WLEN_MASK) >> SEI_DAT_MODE_WLEN_SHIFT)
3316 
3317 /*
3318  * CRC_SHIFT (RW)
3319  *
3320  * CRC shift mode, this mode is used to perform repeat code check
3321  * 0: CRC
3322  * 1: shift mode
3323  */
3324 #define SEI_DAT_MODE_CRC_SHIFT_MASK (0x2000U)
3325 #define SEI_DAT_MODE_CRC_SHIFT_SHIFT (13U)
3326 #define SEI_DAT_MODE_CRC_SHIFT_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_CRC_SHIFT_SHIFT) & SEI_DAT_MODE_CRC_SHIFT_MASK)
3327 #define SEI_DAT_MODE_CRC_SHIFT_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_CRC_SHIFT_MASK) >> SEI_DAT_MODE_CRC_SHIFT_SHIFT)
3328 
3329 /*
3330  * CRC_INV (RW)
3331  *
3332  * CRC invert
3333  * 0: use CRC
3334  * 1: use inverted CRC
3335  */
3336 #define SEI_DAT_MODE_CRC_INV_MASK (0x1000U)
3337 #define SEI_DAT_MODE_CRC_INV_SHIFT (12U)
3338 #define SEI_DAT_MODE_CRC_INV_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_CRC_INV_SHIFT) & SEI_DAT_MODE_CRC_INV_MASK)
3339 #define SEI_DAT_MODE_CRC_INV_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_CRC_INV_MASK) >> SEI_DAT_MODE_CRC_INV_SHIFT)
3340 
3341 /*
3342  * WORDER (RW)
3343  *
3344  * word order
3345  * 0: sample as bit order
3346  * 1: different from bit order
3347  */
3348 #define SEI_DAT_MODE_WORDER_MASK (0x800U)
3349 #define SEI_DAT_MODE_WORDER_SHIFT (11U)
3350 #define SEI_DAT_MODE_WORDER_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_WORDER_SHIFT) & SEI_DAT_MODE_WORDER_MASK)
3351 #define SEI_DAT_MODE_WORDER_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_WORDER_MASK) >> SEI_DAT_MODE_WORDER_SHIFT)
3352 
3353 /*
3354  * BORDER (RW)
3355  *
3356  * bit order
3357  * 0: LSB first
3358  * 1: MSB first
3359  */
3360 #define SEI_DAT_MODE_BORDER_MASK (0x400U)
3361 #define SEI_DAT_MODE_BORDER_SHIFT (10U)
3362 #define SEI_DAT_MODE_BORDER_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_BORDER_SHIFT) & SEI_DAT_MODE_BORDER_MASK)
3363 #define SEI_DAT_MODE_BORDER_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_BORDER_MASK) >> SEI_DAT_MODE_BORDER_SHIFT)
3364 
3365 /*
3366  * SIGNED (RW)
3367  *
3368  * Signed
3369  * 0: unsigned value
3370  * 1: signed value
3371  */
3372 #define SEI_DAT_MODE_SIGNED_MASK (0x200U)
3373 #define SEI_DAT_MODE_SIGNED_SHIFT (9U)
3374 #define SEI_DAT_MODE_SIGNED_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_SIGNED_SHIFT) & SEI_DAT_MODE_SIGNED_MASK)
3375 #define SEI_DAT_MODE_SIGNED_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_SIGNED_MASK) >> SEI_DAT_MODE_SIGNED_SHIFT)
3376 
3377 /*
3378  * REWIND (RW)
3379  *
3380  * Write 1 to rewind read/write pointer, this is a self clear bit
3381  */
3382 #define SEI_DAT_MODE_REWIND_MASK (0x100U)
3383 #define SEI_DAT_MODE_REWIND_SHIFT (8U)
3384 #define SEI_DAT_MODE_REWIND_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_REWIND_SHIFT) & SEI_DAT_MODE_REWIND_MASK)
3385 #define SEI_DAT_MODE_REWIND_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_REWIND_MASK) >> SEI_DAT_MODE_REWIND_SHIFT)
3386 
3387 /*
3388  * MODE (RW)
3389  *
3390  * Data mode
3391  * 0: data mode
3392  * 1: check mode
3393  * 2: CRC mode
3394  */
3395 #define SEI_DAT_MODE_MODE_MASK (0x3U)
3396 #define SEI_DAT_MODE_MODE_SHIFT (0U)
3397 #define SEI_DAT_MODE_MODE_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_MODE_SHIFT) & SEI_DAT_MODE_MODE_MASK)
3398 #define SEI_DAT_MODE_MODE_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_MODE_MASK) >> SEI_DAT_MODE_MODE_SHIFT)
3399 
3400 /* Bitfield definition for register of struct array DAT: IDX */
3401 /*
3402  * LAST_BIT (RW)
3403  *
3404  * Last bit index for tranceive
3405  */
3406 #define SEI_DAT_IDX_LAST_BIT_MASK (0x1F000000UL)
3407 #define SEI_DAT_IDX_LAST_BIT_SHIFT (24U)
3408 #define SEI_DAT_IDX_LAST_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_LAST_BIT_SHIFT) & SEI_DAT_IDX_LAST_BIT_MASK)
3409 #define SEI_DAT_IDX_LAST_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_LAST_BIT_MASK) >> SEI_DAT_IDX_LAST_BIT_SHIFT)
3410 
3411 /*
3412  * FIRST_BIT (RW)
3413  *
3414  * First bit index for tranceive
3415  */
3416 #define SEI_DAT_IDX_FIRST_BIT_MASK (0x1F0000UL)
3417 #define SEI_DAT_IDX_FIRST_BIT_SHIFT (16U)
3418 #define SEI_DAT_IDX_FIRST_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_FIRST_BIT_SHIFT) & SEI_DAT_IDX_FIRST_BIT_MASK)
3419 #define SEI_DAT_IDX_FIRST_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_FIRST_BIT_MASK) >> SEI_DAT_IDX_FIRST_BIT_SHIFT)
3420 
3421 /*
3422  * MAX_BIT (RW)
3423  *
3424  * Highest bit index
3425  */
3426 #define SEI_DAT_IDX_MAX_BIT_MASK (0x1F00U)
3427 #define SEI_DAT_IDX_MAX_BIT_SHIFT (8U)
3428 #define SEI_DAT_IDX_MAX_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_MAX_BIT_SHIFT) & SEI_DAT_IDX_MAX_BIT_MASK)
3429 #define SEI_DAT_IDX_MAX_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_MAX_BIT_MASK) >> SEI_DAT_IDX_MAX_BIT_SHIFT)
3430 
3431 /*
3432  * MIN_BIT (RW)
3433  *
3434  * Lowest bit index
3435  */
3436 #define SEI_DAT_IDX_MIN_BIT_MASK (0x1FU)
3437 #define SEI_DAT_IDX_MIN_BIT_SHIFT (0U)
3438 #define SEI_DAT_IDX_MIN_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_MIN_BIT_SHIFT) & SEI_DAT_IDX_MIN_BIT_MASK)
3439 #define SEI_DAT_IDX_MIN_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_MIN_BIT_MASK) >> SEI_DAT_IDX_MIN_BIT_SHIFT)
3440 
3441 /* Bitfield definition for register of struct array DAT: GOLD */
3442 /*
3443  * GOLD_VALUE (RW)
3444  *
3445  * Gold value for check mode
3446  */
3447 #define SEI_DAT_GOLD_GOLD_VALUE_MASK (0xFFFFFFFFUL)
3448 #define SEI_DAT_GOLD_GOLD_VALUE_SHIFT (0U)
3449 #define SEI_DAT_GOLD_GOLD_VALUE_SET(x) (((uint32_t)(x) << SEI_DAT_GOLD_GOLD_VALUE_SHIFT) & SEI_DAT_GOLD_GOLD_VALUE_MASK)
3450 #define SEI_DAT_GOLD_GOLD_VALUE_GET(x) (((uint32_t)(x) & SEI_DAT_GOLD_GOLD_VALUE_MASK) >> SEI_DAT_GOLD_GOLD_VALUE_SHIFT)
3451 
3452 /* Bitfield definition for register of struct array DAT: CRCINIT */
3453 /*
3454  * CRC_INIT (RW)
3455  *
3456  * CRC initial value
3457  */
3458 #define SEI_DAT_CRCINIT_CRC_INIT_MASK (0xFFFFFFFFUL)
3459 #define SEI_DAT_CRCINIT_CRC_INIT_SHIFT (0U)
3460 #define SEI_DAT_CRCINIT_CRC_INIT_SET(x) (((uint32_t)(x) << SEI_DAT_CRCINIT_CRC_INIT_SHIFT) & SEI_DAT_CRCINIT_CRC_INIT_MASK)
3461 #define SEI_DAT_CRCINIT_CRC_INIT_GET(x) (((uint32_t)(x) & SEI_DAT_CRCINIT_CRC_INIT_MASK) >> SEI_DAT_CRCINIT_CRC_INIT_SHIFT)
3462 
3463 /* Bitfield definition for register of struct array DAT: CRCPOLY */
3464 /*
3465  * CRC_POLY (RW)
3466  *
3467  * CRC polymonial
3468  */
3469 #define SEI_DAT_CRCPOLY_CRC_POLY_MASK (0xFFFFFFFFUL)
3470 #define SEI_DAT_CRCPOLY_CRC_POLY_SHIFT (0U)
3471 #define SEI_DAT_CRCPOLY_CRC_POLY_SET(x) (((uint32_t)(x) << SEI_DAT_CRCPOLY_CRC_POLY_SHIFT) & SEI_DAT_CRCPOLY_CRC_POLY_MASK)
3472 #define SEI_DAT_CRCPOLY_CRC_POLY_GET(x) (((uint32_t)(x) & SEI_DAT_CRCPOLY_CRC_POLY_MASK) >> SEI_DAT_CRCPOLY_CRC_POLY_SHIFT)
3473 
3474 /* Bitfield definition for register of struct array DAT: DATA */
3475 /*
3476  * DATA (RW)
3477  *
3478  * DATA
3479  */
3480 #define SEI_DAT_DATA_DATA_MASK (0xFFFFFFFFUL)
3481 #define SEI_DAT_DATA_DATA_SHIFT (0U)
3482 #define SEI_DAT_DATA_DATA_SET(x) (((uint32_t)(x) << SEI_DAT_DATA_DATA_SHIFT) & SEI_DAT_DATA_DATA_MASK)
3483 #define SEI_DAT_DATA_DATA_GET(x) (((uint32_t)(x) & SEI_DAT_DATA_DATA_MASK) >> SEI_DAT_DATA_DATA_SHIFT)
3484 
3485 /* Bitfield definition for register of struct array DAT: SET */
3486 /*
3487  * DATA_SET (RW)
3488  *
3489  * DATA bit set
3490  */
3491 #define SEI_DAT_SET_DATA_SET_MASK (0xFFFFFFFFUL)
3492 #define SEI_DAT_SET_DATA_SET_SHIFT (0U)
3493 #define SEI_DAT_SET_DATA_SET_SET(x) (((uint32_t)(x) << SEI_DAT_SET_DATA_SET_SHIFT) & SEI_DAT_SET_DATA_SET_MASK)
3494 #define SEI_DAT_SET_DATA_SET_GET(x) (((uint32_t)(x) & SEI_DAT_SET_DATA_SET_MASK) >> SEI_DAT_SET_DATA_SET_SHIFT)
3495 
3496 /* Bitfield definition for register of struct array DAT: CLR */
3497 /*
3498  * DATA_CLR (RW)
3499  *
3500  * DATA bit clear
3501  */
3502 #define SEI_DAT_CLR_DATA_CLR_MASK (0xFFFFFFFFUL)
3503 #define SEI_DAT_CLR_DATA_CLR_SHIFT (0U)
3504 #define SEI_DAT_CLR_DATA_CLR_SET(x) (((uint32_t)(x) << SEI_DAT_CLR_DATA_CLR_SHIFT) & SEI_DAT_CLR_DATA_CLR_MASK)
3505 #define SEI_DAT_CLR_DATA_CLR_GET(x) (((uint32_t)(x) & SEI_DAT_CLR_DATA_CLR_MASK) >> SEI_DAT_CLR_DATA_CLR_SHIFT)
3506 
3507 /* Bitfield definition for register of struct array DAT: INV */
3508 /*
3509  * DATA_INV (RW)
3510  *
3511  * DATA bit toggle
3512  */
3513 #define SEI_DAT_INV_DATA_INV_MASK (0xFFFFFFFFUL)
3514 #define SEI_DAT_INV_DATA_INV_SHIFT (0U)
3515 #define SEI_DAT_INV_DATA_INV_SET(x) (((uint32_t)(x) << SEI_DAT_INV_DATA_INV_SHIFT) & SEI_DAT_INV_DATA_INV_MASK)
3516 #define SEI_DAT_INV_DATA_INV_GET(x) (((uint32_t)(x) & SEI_DAT_INV_DATA_INV_MASK) >> SEI_DAT_INV_DATA_INV_SHIFT)
3517 
3518 /* Bitfield definition for register of struct array DAT: IN */
3519 /*
3520  * DATA_IN (RO)
3521  *
3522  * Data input
3523  */
3524 #define SEI_DAT_IN_DATA_IN_MASK (0xFFFFFFFFUL)
3525 #define SEI_DAT_IN_DATA_IN_SHIFT (0U)
3526 #define SEI_DAT_IN_DATA_IN_GET(x) (((uint32_t)(x) & SEI_DAT_IN_DATA_IN_MASK) >> SEI_DAT_IN_DATA_IN_SHIFT)
3527 
3528 /* Bitfield definition for register of struct array DAT: OUT */
3529 /*
3530  * DATA_OUT (RO)
3531  *
3532  * Data output
3533  */
3534 #define SEI_DAT_OUT_DATA_OUT_MASK (0xFFFFFFFFUL)
3535 #define SEI_DAT_OUT_DATA_OUT_SHIFT (0U)
3536 #define SEI_DAT_OUT_DATA_OUT_GET(x) (((uint32_t)(x) & SEI_DAT_OUT_DATA_OUT_MASK) >> SEI_DAT_OUT_DATA_OUT_SHIFT)
3537 
3538 /* Bitfield definition for register of struct array DAT: STS */
3539 /*
3540  * CRC_IDX (RO)
3541  *
3542  * CRC index
3543  */
3544 #define SEI_DAT_STS_CRC_IDX_MASK (0x1F000000UL)
3545 #define SEI_DAT_STS_CRC_IDX_SHIFT (24U)
3546 #define SEI_DAT_STS_CRC_IDX_GET(x) (((uint32_t)(x) & SEI_DAT_STS_CRC_IDX_MASK) >> SEI_DAT_STS_CRC_IDX_SHIFT)
3547 
3548 /*
3549  * WORD_IDX (RO)
3550  *
3551  * Word index
3552  */
3553 #define SEI_DAT_STS_WORD_IDX_MASK (0x1F0000UL)
3554 #define SEI_DAT_STS_WORD_IDX_SHIFT (16U)
3555 #define SEI_DAT_STS_WORD_IDX_GET(x) (((uint32_t)(x) & SEI_DAT_STS_WORD_IDX_MASK) >> SEI_DAT_STS_WORD_IDX_SHIFT)
3556 
3557 /*
3558  * WORD_CNT (RO)
3559  *
3560  * Word counter
3561  */
3562 #define SEI_DAT_STS_WORD_CNT_MASK (0x1F00U)
3563 #define SEI_DAT_STS_WORD_CNT_SHIFT (8U)
3564 #define SEI_DAT_STS_WORD_CNT_GET(x) (((uint32_t)(x) & SEI_DAT_STS_WORD_CNT_MASK) >> SEI_DAT_STS_WORD_CNT_SHIFT)
3565 
3566 /*
3567  * BIT_IDX (RO)
3568  *
3569  * Bit index
3570  */
3571 #define SEI_DAT_STS_BIT_IDX_MASK (0x1FU)
3572 #define SEI_DAT_STS_BIT_IDX_SHIFT (0U)
3573 #define SEI_DAT_STS_BIT_IDX_GET(x) (((uint32_t)(x) & SEI_DAT_STS_BIT_IDX_MASK) >> SEI_DAT_STS_BIT_IDX_SHIFT)
3574 
3575 
3576 
3577 /* CMD register group index macro definition */
3578 #define SEI_CTRL_TRG_TABLE_CMD_0 (0UL)
3579 #define SEI_CTRL_TRG_TABLE_CMD_1 (1UL)
3580 #define SEI_CTRL_TRG_TABLE_CMD_2 (2UL)
3581 #define SEI_CTRL_TRG_TABLE_CMD_3 (3UL)
3582 
3583 /* TIME register group index macro definition */
3584 #define SEI_CTRL_TRG_TABLE_TIME_0 (0UL)
3585 #define SEI_CTRL_TRG_TABLE_TIME_1 (1UL)
3586 #define SEI_CTRL_TRG_TABLE_TIME_2 (2UL)
3587 #define SEI_CTRL_TRG_TABLE_TIME_3 (3UL)
3588 
3589 /* CMD_TABLE register group index macro definition */
3590 #define SEI_CMD_TABLE_0 (0UL)
3591 #define SEI_CMD_TABLE_1 (1UL)
3592 #define SEI_CMD_TABLE_2 (2UL)
3593 #define SEI_CMD_TABLE_3 (3UL)
3594 #define SEI_CMD_TABLE_4 (4UL)
3595 #define SEI_CMD_TABLE_5 (5UL)
3596 #define SEI_CMD_TABLE_6 (6UL)
3597 #define SEI_CMD_TABLE_7 (7UL)
3598 
3599 /* TRAN register group index macro definition */
3600 #define SEI_CTRL_LATCH_TRAN_0_1 (0UL)
3601 #define SEI_CTRL_LATCH_TRAN_1_2 (1UL)
3602 #define SEI_CTRL_LATCH_TRAN_2_3 (2UL)
3603 #define SEI_CTRL_LATCH_TRAN_3_0 (3UL)
3604 
3605 /* LATCH register group index macro definition */
3606 #define SEI_LATCH_0 (0UL)
3607 #define SEI_LATCH_1 (1UL)
3608 #define SEI_LATCH_2 (2UL)
3609 #define SEI_LATCH_3 (3UL)
3610 
3611 /* CTRL register group index macro definition */
3612 #define SEI_CTRL_0 (0UL)
3613 #define SEI_CTRL_1 (1UL)
3614 #define SEI_CTRL_2 (2UL)
3615 #define SEI_CTRL_3 (3UL)
3616 #define SEI_CTRL_4 (4UL)
3617 #define SEI_CTRL_5 (5UL)
3618 #define SEI_CTRL_6 (6UL)
3619 #define SEI_CTRL_7 (7UL)
3620 #define SEI_CTRL_8 (8UL)
3621 #define SEI_CTRL_9 (9UL)
3622 #define SEI_CTRL_10 (10UL)
3623 #define SEI_CTRL_11 (11UL)
3624 #define SEI_CTRL_12 (12UL)
3625 
3626 /* INSTR register group index macro definition */
3627 #define SEI_INSTR_0 (0UL)
3628 #define SEI_INSTR_1 (1UL)
3629 #define SEI_INSTR_2 (2UL)
3630 #define SEI_INSTR_3 (3UL)
3631 #define SEI_INSTR_4 (4UL)
3632 #define SEI_INSTR_5 (5UL)
3633 #define SEI_INSTR_6 (6UL)
3634 #define SEI_INSTR_7 (7UL)
3635 #define SEI_INSTR_8 (8UL)
3636 #define SEI_INSTR_9 (9UL)
3637 #define SEI_INSTR_10 (10UL)
3638 #define SEI_INSTR_11 (11UL)
3639 #define SEI_INSTR_12 (12UL)
3640 #define SEI_INSTR_13 (13UL)
3641 #define SEI_INSTR_14 (14UL)
3642 #define SEI_INSTR_15 (15UL)
3643 #define SEI_INSTR_16 (16UL)
3644 #define SEI_INSTR_17 (17UL)
3645 #define SEI_INSTR_18 (18UL)
3646 #define SEI_INSTR_19 (19UL)
3647 #define SEI_INSTR_20 (20UL)
3648 #define SEI_INSTR_21 (21UL)
3649 #define SEI_INSTR_22 (22UL)
3650 #define SEI_INSTR_23 (23UL)
3651 #define SEI_INSTR_24 (24UL)
3652 #define SEI_INSTR_25 (25UL)
3653 #define SEI_INSTR_26 (26UL)
3654 #define SEI_INSTR_27 (27UL)
3655 #define SEI_INSTR_28 (28UL)
3656 #define SEI_INSTR_29 (29UL)
3657 #define SEI_INSTR_30 (30UL)
3658 #define SEI_INSTR_31 (31UL)
3659 #define SEI_INSTR_32 (32UL)
3660 #define SEI_INSTR_33 (33UL)
3661 #define SEI_INSTR_34 (34UL)
3662 #define SEI_INSTR_35 (35UL)
3663 #define SEI_INSTR_36 (36UL)
3664 #define SEI_INSTR_37 (37UL)
3665 #define SEI_INSTR_38 (38UL)
3666 #define SEI_INSTR_39 (39UL)
3667 #define SEI_INSTR_40 (40UL)
3668 #define SEI_INSTR_41 (41UL)
3669 #define SEI_INSTR_42 (42UL)
3670 #define SEI_INSTR_43 (43UL)
3671 #define SEI_INSTR_44 (44UL)
3672 #define SEI_INSTR_45 (45UL)
3673 #define SEI_INSTR_46 (46UL)
3674 #define SEI_INSTR_47 (47UL)
3675 #define SEI_INSTR_48 (48UL)
3676 #define SEI_INSTR_49 (49UL)
3677 #define SEI_INSTR_50 (50UL)
3678 #define SEI_INSTR_51 (51UL)
3679 #define SEI_INSTR_52 (52UL)
3680 #define SEI_INSTR_53 (53UL)
3681 #define SEI_INSTR_54 (54UL)
3682 #define SEI_INSTR_55 (55UL)
3683 #define SEI_INSTR_56 (56UL)
3684 #define SEI_INSTR_57 (57UL)
3685 #define SEI_INSTR_58 (58UL)
3686 #define SEI_INSTR_59 (59UL)
3687 #define SEI_INSTR_60 (60UL)
3688 #define SEI_INSTR_61 (61UL)
3689 #define SEI_INSTR_62 (62UL)
3690 #define SEI_INSTR_63 (63UL)
3691 #define SEI_INSTR_64 (64UL)
3692 #define SEI_INSTR_65 (65UL)
3693 #define SEI_INSTR_66 (66UL)
3694 #define SEI_INSTR_67 (67UL)
3695 #define SEI_INSTR_68 (68UL)
3696 #define SEI_INSTR_69 (69UL)
3697 #define SEI_INSTR_70 (70UL)
3698 #define SEI_INSTR_71 (71UL)
3699 #define SEI_INSTR_72 (72UL)
3700 #define SEI_INSTR_73 (73UL)
3701 #define SEI_INSTR_74 (74UL)
3702 #define SEI_INSTR_75 (75UL)
3703 #define SEI_INSTR_76 (76UL)
3704 #define SEI_INSTR_77 (77UL)
3705 #define SEI_INSTR_78 (78UL)
3706 #define SEI_INSTR_79 (79UL)
3707 #define SEI_INSTR_80 (80UL)
3708 #define SEI_INSTR_81 (81UL)
3709 #define SEI_INSTR_82 (82UL)
3710 #define SEI_INSTR_83 (83UL)
3711 #define SEI_INSTR_84 (84UL)
3712 #define SEI_INSTR_85 (85UL)
3713 #define SEI_INSTR_86 (86UL)
3714 #define SEI_INSTR_87 (87UL)
3715 #define SEI_INSTR_88 (88UL)
3716 #define SEI_INSTR_89 (89UL)
3717 #define SEI_INSTR_90 (90UL)
3718 #define SEI_INSTR_91 (91UL)
3719 #define SEI_INSTR_92 (92UL)
3720 #define SEI_INSTR_93 (93UL)
3721 #define SEI_INSTR_94 (94UL)
3722 #define SEI_INSTR_95 (95UL)
3723 #define SEI_INSTR_96 (96UL)
3724 #define SEI_INSTR_97 (97UL)
3725 #define SEI_INSTR_98 (98UL)
3726 #define SEI_INSTR_99 (99UL)
3727 #define SEI_INSTR_100 (100UL)
3728 #define SEI_INSTR_101 (101UL)
3729 #define SEI_INSTR_102 (102UL)
3730 #define SEI_INSTR_103 (103UL)
3731 #define SEI_INSTR_104 (104UL)
3732 #define SEI_INSTR_105 (105UL)
3733 #define SEI_INSTR_106 (106UL)
3734 #define SEI_INSTR_107 (107UL)
3735 #define SEI_INSTR_108 (108UL)
3736 #define SEI_INSTR_109 (109UL)
3737 #define SEI_INSTR_110 (110UL)
3738 #define SEI_INSTR_111 (111UL)
3739 #define SEI_INSTR_112 (112UL)
3740 #define SEI_INSTR_113 (113UL)
3741 #define SEI_INSTR_114 (114UL)
3742 #define SEI_INSTR_115 (115UL)
3743 #define SEI_INSTR_116 (116UL)
3744 #define SEI_INSTR_117 (117UL)
3745 #define SEI_INSTR_118 (118UL)
3746 #define SEI_INSTR_119 (119UL)
3747 #define SEI_INSTR_120 (120UL)
3748 #define SEI_INSTR_121 (121UL)
3749 #define SEI_INSTR_122 (122UL)
3750 #define SEI_INSTR_123 (123UL)
3751 #define SEI_INSTR_124 (124UL)
3752 #define SEI_INSTR_125 (125UL)
3753 #define SEI_INSTR_126 (126UL)
3754 #define SEI_INSTR_127 (127UL)
3755 #define SEI_INSTR_128 (128UL)
3756 #define SEI_INSTR_129 (129UL)
3757 #define SEI_INSTR_130 (130UL)
3758 #define SEI_INSTR_131 (131UL)
3759 #define SEI_INSTR_132 (132UL)
3760 #define SEI_INSTR_133 (133UL)
3761 #define SEI_INSTR_134 (134UL)
3762 #define SEI_INSTR_135 (135UL)
3763 #define SEI_INSTR_136 (136UL)
3764 #define SEI_INSTR_137 (137UL)
3765 #define SEI_INSTR_138 (138UL)
3766 #define SEI_INSTR_139 (139UL)
3767 #define SEI_INSTR_140 (140UL)
3768 #define SEI_INSTR_141 (141UL)
3769 #define SEI_INSTR_142 (142UL)
3770 #define SEI_INSTR_143 (143UL)
3771 #define SEI_INSTR_144 (144UL)
3772 #define SEI_INSTR_145 (145UL)
3773 #define SEI_INSTR_146 (146UL)
3774 #define SEI_INSTR_147 (147UL)
3775 #define SEI_INSTR_148 (148UL)
3776 #define SEI_INSTR_149 (149UL)
3777 #define SEI_INSTR_150 (150UL)
3778 #define SEI_INSTR_151 (151UL)
3779 #define SEI_INSTR_152 (152UL)
3780 #define SEI_INSTR_153 (153UL)
3781 #define SEI_INSTR_154 (154UL)
3782 #define SEI_INSTR_155 (155UL)
3783 #define SEI_INSTR_156 (156UL)
3784 #define SEI_INSTR_157 (157UL)
3785 #define SEI_INSTR_158 (158UL)
3786 #define SEI_INSTR_159 (159UL)
3787 #define SEI_INSTR_160 (160UL)
3788 #define SEI_INSTR_161 (161UL)
3789 #define SEI_INSTR_162 (162UL)
3790 #define SEI_INSTR_163 (163UL)
3791 #define SEI_INSTR_164 (164UL)
3792 #define SEI_INSTR_165 (165UL)
3793 #define SEI_INSTR_166 (166UL)
3794 #define SEI_INSTR_167 (167UL)
3795 #define SEI_INSTR_168 (168UL)
3796 #define SEI_INSTR_169 (169UL)
3797 #define SEI_INSTR_170 (170UL)
3798 #define SEI_INSTR_171 (171UL)
3799 #define SEI_INSTR_172 (172UL)
3800 #define SEI_INSTR_173 (173UL)
3801 #define SEI_INSTR_174 (174UL)
3802 #define SEI_INSTR_175 (175UL)
3803 #define SEI_INSTR_176 (176UL)
3804 #define SEI_INSTR_177 (177UL)
3805 #define SEI_INSTR_178 (178UL)
3806 #define SEI_INSTR_179 (179UL)
3807 #define SEI_INSTR_180 (180UL)
3808 #define SEI_INSTR_181 (181UL)
3809 #define SEI_INSTR_182 (182UL)
3810 #define SEI_INSTR_183 (183UL)
3811 #define SEI_INSTR_184 (184UL)
3812 #define SEI_INSTR_185 (185UL)
3813 #define SEI_INSTR_186 (186UL)
3814 #define SEI_INSTR_187 (187UL)
3815 #define SEI_INSTR_188 (188UL)
3816 #define SEI_INSTR_189 (189UL)
3817 #define SEI_INSTR_190 (190UL)
3818 #define SEI_INSTR_191 (191UL)
3819 #define SEI_INSTR_192 (192UL)
3820 #define SEI_INSTR_193 (193UL)
3821 #define SEI_INSTR_194 (194UL)
3822 #define SEI_INSTR_195 (195UL)
3823 #define SEI_INSTR_196 (196UL)
3824 #define SEI_INSTR_197 (197UL)
3825 #define SEI_INSTR_198 (198UL)
3826 #define SEI_INSTR_199 (199UL)
3827 #define SEI_INSTR_200 (200UL)
3828 #define SEI_INSTR_201 (201UL)
3829 #define SEI_INSTR_202 (202UL)
3830 #define SEI_INSTR_203 (203UL)
3831 #define SEI_INSTR_204 (204UL)
3832 #define SEI_INSTR_205 (205UL)
3833 #define SEI_INSTR_206 (206UL)
3834 #define SEI_INSTR_207 (207UL)
3835 #define SEI_INSTR_208 (208UL)
3836 #define SEI_INSTR_209 (209UL)
3837 #define SEI_INSTR_210 (210UL)
3838 #define SEI_INSTR_211 (211UL)
3839 #define SEI_INSTR_212 (212UL)
3840 #define SEI_INSTR_213 (213UL)
3841 #define SEI_INSTR_214 (214UL)
3842 #define SEI_INSTR_215 (215UL)
3843 #define SEI_INSTR_216 (216UL)
3844 #define SEI_INSTR_217 (217UL)
3845 #define SEI_INSTR_218 (218UL)
3846 #define SEI_INSTR_219 (219UL)
3847 #define SEI_INSTR_220 (220UL)
3848 #define SEI_INSTR_221 (221UL)
3849 #define SEI_INSTR_222 (222UL)
3850 #define SEI_INSTR_223 (223UL)
3851 #define SEI_INSTR_224 (224UL)
3852 #define SEI_INSTR_225 (225UL)
3853 #define SEI_INSTR_226 (226UL)
3854 #define SEI_INSTR_227 (227UL)
3855 #define SEI_INSTR_228 (228UL)
3856 #define SEI_INSTR_229 (229UL)
3857 #define SEI_INSTR_230 (230UL)
3858 #define SEI_INSTR_231 (231UL)
3859 #define SEI_INSTR_232 (232UL)
3860 #define SEI_INSTR_233 (233UL)
3861 #define SEI_INSTR_234 (234UL)
3862 #define SEI_INSTR_235 (235UL)
3863 #define SEI_INSTR_236 (236UL)
3864 #define SEI_INSTR_237 (237UL)
3865 #define SEI_INSTR_238 (238UL)
3866 #define SEI_INSTR_239 (239UL)
3867 #define SEI_INSTR_240 (240UL)
3868 #define SEI_INSTR_241 (241UL)
3869 #define SEI_INSTR_242 (242UL)
3870 #define SEI_INSTR_243 (243UL)
3871 #define SEI_INSTR_244 (244UL)
3872 #define SEI_INSTR_245 (245UL)
3873 #define SEI_INSTR_246 (246UL)
3874 #define SEI_INSTR_247 (247UL)
3875 #define SEI_INSTR_248 (248UL)
3876 #define SEI_INSTR_249 (249UL)
3877 #define SEI_INSTR_250 (250UL)
3878 #define SEI_INSTR_251 (251UL)
3879 #define SEI_INSTR_252 (252UL)
3880 #define SEI_INSTR_253 (253UL)
3881 #define SEI_INSTR_254 (254UL)
3882 #define SEI_INSTR_255 (255UL)
3883 
3884 /* DAT register group index macro definition */
3885 #define SEI_DAT_0 (0UL)
3886 #define SEI_DAT_1 (1UL)
3887 #define SEI_DAT_2 (2UL)
3888 #define SEI_DAT_3 (3UL)
3889 #define SEI_DAT_4 (4UL)
3890 #define SEI_DAT_5 (5UL)
3891 #define SEI_DAT_6 (6UL)
3892 #define SEI_DAT_7 (7UL)
3893 #define SEI_DAT_8 (8UL)
3894 #define SEI_DAT_9 (9UL)
3895 #define SEI_DAT_10 (10UL)
3896 #define SEI_DAT_11 (11UL)
3897 #define SEI_DAT_12 (12UL)
3898 #define SEI_DAT_13 (13UL)
3899 #define SEI_DAT_14 (14UL)
3900 #define SEI_DAT_15 (15UL)
3901 #define SEI_DAT_16 (16UL)
3902 #define SEI_DAT_17 (17UL)
3903 #define SEI_DAT_18 (18UL)
3904 #define SEI_DAT_19 (19UL)
3905 #define SEI_DAT_20 (20UL)
3906 #define SEI_DAT_21 (21UL)
3907 #define SEI_DAT_22 (22UL)
3908 #define SEI_DAT_23 (23UL)
3909 #define SEI_DAT_24 (24UL)
3910 #define SEI_DAT_25 (25UL)
3911 #define SEI_DAT_26 (26UL)
3912 #define SEI_DAT_27 (27UL)
3913 #define SEI_DAT_28 (28UL)
3914 #define SEI_DAT_29 (29UL)
3915 #define SEI_DAT_30 (30UL)
3916 #define SEI_DAT_31 (31UL)
3917 
3918 
3919 #endif /* HPM_SEI_H */
MIN
#define MIN(a, b)
Definition: hpm_common.h:49
MAX
#define MAX(a, b)
Definition: hpm_common.h:46
SEI_Type
Definition: hpm_sei_regs.h:12