HPM SDK
HPMicro Software Development Kit
hpm_synt_regs.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_SYNT_H
10 #define HPM_SYNT_H
11 
12 typedef struct {
13  __RW uint32_t GCR; /* 0x0: Global control register */
14  __RW uint32_t RLD; /* 0x4: Counter reload register */
15  __RW uint32_t TIMESTAMP_NEW; /* 0x8: timestamp new value register */
16  __R uint32_t CNT; /* 0xC: Counter */
17  __R uint32_t TIMESTAMP_SAV; /* 0x10: timestamp trig save value */
18  __R uint32_t TIMESTAMP_CUR; /* 0x14: timestamp read value */
19  __R uint8_t RESERVED0[8]; /* 0x18 - 0x1F: Reserved */
20  __RW uint32_t CMP[16]; /* 0x20 - 0x5C: Comparator */
21 } SYNT_Type;
22 
23 
24 /* Bitfield definition for register: GCR */
25 /*
26  * TIMESTAMP_INC_NEW (WO)
27  *
28  * set to increase the timesamp with new value, auto clr
29  */
30 #define SYNT_GCR_TIMESTAMP_INC_NEW_MASK (0x80000000UL)
31 #define SYNT_GCR_TIMESTAMP_INC_NEW_SHIFT (31U)
32 #define SYNT_GCR_TIMESTAMP_INC_NEW_SET(x) (((uint32_t)(x) << SYNT_GCR_TIMESTAMP_INC_NEW_SHIFT) & SYNT_GCR_TIMESTAMP_INC_NEW_MASK)
33 #define SYNT_GCR_TIMESTAMP_INC_NEW_GET(x) (((uint32_t)(x) & SYNT_GCR_TIMESTAMP_INC_NEW_MASK) >> SYNT_GCR_TIMESTAMP_INC_NEW_SHIFT)
34 
35 /*
36  * TIMESTAMP_DEC_NEW (WO)
37  *
38  * set to decrease the timesamp with new value, auto clr
39  */
40 #define SYNT_GCR_TIMESTAMP_DEC_NEW_MASK (0x40000000UL)
41 #define SYNT_GCR_TIMESTAMP_DEC_NEW_SHIFT (30U)
42 #define SYNT_GCR_TIMESTAMP_DEC_NEW_SET(x) (((uint32_t)(x) << SYNT_GCR_TIMESTAMP_DEC_NEW_SHIFT) & SYNT_GCR_TIMESTAMP_DEC_NEW_MASK)
43 #define SYNT_GCR_TIMESTAMP_DEC_NEW_GET(x) (((uint32_t)(x) & SYNT_GCR_TIMESTAMP_DEC_NEW_MASK) >> SYNT_GCR_TIMESTAMP_DEC_NEW_SHIFT)
44 
45 /*
46  * TIMESTAMP_SET_NEW (WO)
47  *
48  * set the timesamp to new value, auto clr
49  */
50 #define SYNT_GCR_TIMESTAMP_SET_NEW_MASK (0x20000000UL)
51 #define SYNT_GCR_TIMESTAMP_SET_NEW_SHIFT (29U)
52 #define SYNT_GCR_TIMESTAMP_SET_NEW_SET(x) (((uint32_t)(x) << SYNT_GCR_TIMESTAMP_SET_NEW_SHIFT) & SYNT_GCR_TIMESTAMP_SET_NEW_MASK)
53 #define SYNT_GCR_TIMESTAMP_SET_NEW_GET(x) (((uint32_t)(x) & SYNT_GCR_TIMESTAMP_SET_NEW_MASK) >> SYNT_GCR_TIMESTAMP_SET_NEW_SHIFT)
54 
55 /*
56  * TIMESTAMP_RESET (WO)
57  *
58  * reset timesamp to 0, auto clr
59  */
60 #define SYNT_GCR_TIMESTAMP_RESET_MASK (0x10000000UL)
61 #define SYNT_GCR_TIMESTAMP_RESET_SHIFT (28U)
62 #define SYNT_GCR_TIMESTAMP_RESET_SET(x) (((uint32_t)(x) << SYNT_GCR_TIMESTAMP_RESET_SHIFT) & SYNT_GCR_TIMESTAMP_RESET_MASK)
63 #define SYNT_GCR_TIMESTAMP_RESET_GET(x) (((uint32_t)(x) & SYNT_GCR_TIMESTAMP_RESET_MASK) >> SYNT_GCR_TIMESTAMP_RESET_SHIFT)
64 
65 /*
66  * TIMESTAMP_DEBUG_EN (RW)
67  *
68  * set to enable cpu_debug_mode to stop the timesamp
69  */
70 #define SYNT_GCR_TIMESTAMP_DEBUG_EN_MASK (0x20U)
71 #define SYNT_GCR_TIMESTAMP_DEBUG_EN_SHIFT (5U)
72 #define SYNT_GCR_TIMESTAMP_DEBUG_EN_SET(x) (((uint32_t)(x) << SYNT_GCR_TIMESTAMP_DEBUG_EN_SHIFT) & SYNT_GCR_TIMESTAMP_DEBUG_EN_MASK)
73 #define SYNT_GCR_TIMESTAMP_DEBUG_EN_GET(x) (((uint32_t)(x) & SYNT_GCR_TIMESTAMP_DEBUG_EN_MASK) >> SYNT_GCR_TIMESTAMP_DEBUG_EN_SHIFT)
74 
75 /*
76  * TIMESTAMP_ENABLE (RW)
77  *
78  * set to enable the timesamp , clr to stop
79  */
80 #define SYNT_GCR_TIMESTAMP_ENABLE_MASK (0x10U)
81 #define SYNT_GCR_TIMESTAMP_ENABLE_SHIFT (4U)
82 #define SYNT_GCR_TIMESTAMP_ENABLE_SET(x) (((uint32_t)(x) << SYNT_GCR_TIMESTAMP_ENABLE_SHIFT) & SYNT_GCR_TIMESTAMP_ENABLE_MASK)
83 #define SYNT_GCR_TIMESTAMP_ENABLE_GET(x) (((uint32_t)(x) & SYNT_GCR_TIMESTAMP_ENABLE_MASK) >> SYNT_GCR_TIMESTAMP_ENABLE_SHIFT)
84 
85 /*
86  * TIMER_ONESHOT (RW)
87  *
88  * set for one shot mode, timer will run only once.
89  * Software need reset timer first to start another one shot
90  */
91 #define SYNT_GCR_TIMER_ONESHOT_MASK (0x8U)
92 #define SYNT_GCR_TIMER_ONESHOT_SHIFT (3U)
93 #define SYNT_GCR_TIMER_ONESHOT_SET(x) (((uint32_t)(x) << SYNT_GCR_TIMER_ONESHOT_SHIFT) & SYNT_GCR_TIMER_ONESHOT_MASK)
94 #define SYNT_GCR_TIMER_ONESHOT_GET(x) (((uint32_t)(x) & SYNT_GCR_TIMER_ONESHOT_MASK) >> SYNT_GCR_TIMER_ONESHOT_SHIFT)
95 
96 /*
97  * COUNTER_DEBUG_EN (RW)
98  *
99  * set to enable cpu_debug_mode to stop the counter
100  */
101 #define SYNT_GCR_COUNTER_DEBUG_EN_MASK (0x4U)
102 #define SYNT_GCR_COUNTER_DEBUG_EN_SHIFT (2U)
103 #define SYNT_GCR_COUNTER_DEBUG_EN_SET(x) (((uint32_t)(x) << SYNT_GCR_COUNTER_DEBUG_EN_SHIFT) & SYNT_GCR_COUNTER_DEBUG_EN_MASK)
104 #define SYNT_GCR_COUNTER_DEBUG_EN_GET(x) (((uint32_t)(x) & SYNT_GCR_COUNTER_DEBUG_EN_MASK) >> SYNT_GCR_COUNTER_DEBUG_EN_SHIFT)
105 
106 /*
107  * CRST (RW)
108  *
109  * 1- Reset counter
110  */
111 #define SYNT_GCR_CRST_MASK (0x2U)
112 #define SYNT_GCR_CRST_SHIFT (1U)
113 #define SYNT_GCR_CRST_SET(x) (((uint32_t)(x) << SYNT_GCR_CRST_SHIFT) & SYNT_GCR_CRST_MASK)
114 #define SYNT_GCR_CRST_GET(x) (((uint32_t)(x) & SYNT_GCR_CRST_MASK) >> SYNT_GCR_CRST_SHIFT)
115 
116 /*
117  * CEN (RW)
118  *
119  * 1- Enable counter
120  */
121 #define SYNT_GCR_CEN_MASK (0x1U)
122 #define SYNT_GCR_CEN_SHIFT (0U)
123 #define SYNT_GCR_CEN_SET(x) (((uint32_t)(x) << SYNT_GCR_CEN_SHIFT) & SYNT_GCR_CEN_MASK)
124 #define SYNT_GCR_CEN_GET(x) (((uint32_t)(x) & SYNT_GCR_CEN_MASK) >> SYNT_GCR_CEN_SHIFT)
125 
126 /* Bitfield definition for register: RLD */
127 /*
128  * RLD (RW)
129  *
130  * counter reload value
131  */
132 #define SYNT_RLD_RLD_MASK (0xFFFFFFFFUL)
133 #define SYNT_RLD_RLD_SHIFT (0U)
134 #define SYNT_RLD_RLD_SET(x) (((uint32_t)(x) << SYNT_RLD_RLD_SHIFT) & SYNT_RLD_RLD_MASK)
135 #define SYNT_RLD_RLD_GET(x) (((uint32_t)(x) & SYNT_RLD_RLD_MASK) >> SYNT_RLD_RLD_SHIFT)
136 
137 /* Bitfield definition for register: TIMESTAMP_NEW */
138 /*
139  * VALUE (RW)
140  *
141  * new value for timesamp , can be used as set/inc/dec
142  */
143 #define SYNT_TIMESTAMP_NEW_VALUE_MASK (0xFFFFFFFFUL)
144 #define SYNT_TIMESTAMP_NEW_VALUE_SHIFT (0U)
145 #define SYNT_TIMESTAMP_NEW_VALUE_SET(x) (((uint32_t)(x) << SYNT_TIMESTAMP_NEW_VALUE_SHIFT) & SYNT_TIMESTAMP_NEW_VALUE_MASK)
146 #define SYNT_TIMESTAMP_NEW_VALUE_GET(x) (((uint32_t)(x) & SYNT_TIMESTAMP_NEW_VALUE_MASK) >> SYNT_TIMESTAMP_NEW_VALUE_SHIFT)
147 
148 /* Bitfield definition for register: CNT */
149 /*
150  * CNT (RO)
151  *
152  * counter
153  */
154 #define SYNT_CNT_CNT_MASK (0xFFFFFFFFUL)
155 #define SYNT_CNT_CNT_SHIFT (0U)
156 #define SYNT_CNT_CNT_GET(x) (((uint32_t)(x) & SYNT_CNT_CNT_MASK) >> SYNT_CNT_CNT_SHIFT)
157 
158 /* Bitfield definition for register: TIMESTAMP_SAV */
159 /*
160  * VALUE (RO)
161  *
162  * use the trigger to save timesamp here
163  */
164 #define SYNT_TIMESTAMP_SAV_VALUE_MASK (0xFFFFFFFFUL)
165 #define SYNT_TIMESTAMP_SAV_VALUE_SHIFT (0U)
166 #define SYNT_TIMESTAMP_SAV_VALUE_GET(x) (((uint32_t)(x) & SYNT_TIMESTAMP_SAV_VALUE_MASK) >> SYNT_TIMESTAMP_SAV_VALUE_SHIFT)
167 
168 /* Bitfield definition for register: TIMESTAMP_CUR */
169 /*
170  * VALUE (RO)
171  *
172  * current timesamp value
173  */
174 #define SYNT_TIMESTAMP_CUR_VALUE_MASK (0xFFFFFFFFUL)
175 #define SYNT_TIMESTAMP_CUR_VALUE_SHIFT (0U)
176 #define SYNT_TIMESTAMP_CUR_VALUE_GET(x) (((uint32_t)(x) & SYNT_TIMESTAMP_CUR_VALUE_MASK) >> SYNT_TIMESTAMP_CUR_VALUE_SHIFT)
177 
178 /* Bitfield definition for register array: CMP */
179 /*
180  * CMP (RW)
181  *
182  * comparator value, the output will assert when counter count to this value
183  */
184 #define SYNT_CMP_CMP_MASK (0xFFFFFFFFUL)
185 #define SYNT_CMP_CMP_SHIFT (0U)
186 #define SYNT_CMP_CMP_SET(x) (((uint32_t)(x) << SYNT_CMP_CMP_SHIFT) & SYNT_CMP_CMP_MASK)
187 #define SYNT_CMP_CMP_GET(x) (((uint32_t)(x) & SYNT_CMP_CMP_MASK) >> SYNT_CMP_CMP_SHIFT)
188 
189 
190 
191 /* CMP register group index macro definition */
192 #define SYNT_CMP_0 (0UL)
193 #define SYNT_CMP_1 (1UL)
194 #define SYNT_CMP_2 (2UL)
195 #define SYNT_CMP_3 (3UL)
196 #define SYNT_CMP_4 (4UL)
197 #define SYNT_CMP_5 (5UL)
198 #define SYNT_CMP_6 (6UL)
199 #define SYNT_CMP_7 (7UL)
200 #define SYNT_CMP_8 (8UL)
201 #define SYNT_CMP_9 (9UL)
202 #define SYNT_CMP_10 (10UL)
203 #define SYNT_CMP_11 (11UL)
204 #define SYNT_CMP_12 (12UL)
205 #define SYNT_CMP_13 (13UL)
206 #define SYNT_CMP_14 (14UL)
207 #define SYNT_CMP_15 (15UL)
208 
209 
210 #endif /* HPM_SYNT_H */
Definition: hpm_synt_regs.h:12