HPM SDK
HPMicro Software Development Kit
hpm_tamp_regs.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_TAMP_H
10 #define HPM_TAMP_H
11 
12 typedef struct {
13  struct {
14  __RW uint32_t CONTROL; /* 0x0: Tamper n control */
15  __RW uint32_t POLY; /* 0x4: Tamper n Polynomial of LFSR */
16  __W uint32_t LFSR; /* 0x8: Tamper n LFSR shift register */
17  __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */
18  } TAMP[4];
19  __R uint8_t RESERVED0[64]; /* 0x40 - 0x7F: Reserved */
20  __RW uint32_t TAMP_FLAG; /* 0x80: Tamper flag */
21  __RW uint32_t IRQ_EN; /* 0x84: Tamper interrupt enable */
22 } TAMP_Type;
23 
24 
25 /* Bitfield definition for register of struct array TAMP: CONTROL */
26 /*
27  * LOCK (RW)
28  *
29  * lock tamper setting
30  * 0: tamper setting can be changed
31  * 1: tamper setting will last to next battery domain power cycle
32  */
33 #define TAMP_TAMP_CONTROL_LOCK_MASK (0x80000000UL)
34 #define TAMP_TAMP_CONTROL_LOCK_SHIFT (31U)
35 #define TAMP_TAMP_CONTROL_LOCK_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_LOCK_SHIFT) & TAMP_TAMP_CONTROL_LOCK_MASK)
36 #define TAMP_TAMP_CONTROL_LOCK_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_LOCK_MASK) >> TAMP_TAMP_CONTROL_LOCK_SHIFT)
37 
38 /*
39  * BYPASS (RW)
40  *
41  * bypass tamper violation filter
42  * 0: filter applied
43  * 1: filter not used
44  */
45 #define TAMP_TAMP_CONTROL_BYPASS_MASK (0x100000UL)
46 #define TAMP_TAMP_CONTROL_BYPASS_SHIFT (20U)
47 #define TAMP_TAMP_CONTROL_BYPASS_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_BYPASS_SHIFT) & TAMP_TAMP_CONTROL_BYPASS_MASK)
48 #define TAMP_TAMP_CONTROL_BYPASS_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_BYPASS_MASK) >> TAMP_TAMP_CONTROL_BYPASS_SHIFT)
49 
50 /*
51  * FILTER (RW)
52  *
53  * filter length
54  * 0: 1 cycle
55  * 1: 2 cycle
56  * 15: 65526 cycle
57  */
58 #define TAMP_TAMP_CONTROL_FILTER_MASK (0xF0000UL)
59 #define TAMP_TAMP_CONTROL_FILTER_SHIFT (16U)
60 #define TAMP_TAMP_CONTROL_FILTER_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_FILTER_SHIFT) & TAMP_TAMP_CONTROL_FILTER_MASK)
61 #define TAMP_TAMP_CONTROL_FILTER_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_FILTER_MASK) >> TAMP_TAMP_CONTROL_FILTER_SHIFT)
62 
63 /*
64  * VALUE (RW)
65  *
66  * pin value for passive tamper
67  */
68 #define TAMP_TAMP_CONTROL_VALUE_MASK (0x300U)
69 #define TAMP_TAMP_CONTROL_VALUE_SHIFT (8U)
70 #define TAMP_TAMP_CONTROL_VALUE_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_VALUE_SHIFT) & TAMP_TAMP_CONTROL_VALUE_MASK)
71 #define TAMP_TAMP_CONTROL_VALUE_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_VALUE_MASK) >> TAMP_TAMP_CONTROL_VALUE_SHIFT)
72 
73 /*
74  * SPEED (RW)
75  *
76  * tamper speed selection, (2^SPEED) changes per second
77  * 0: 1 shift per second
78  * 1: 2 shifts per second
79  * . . .
80  * 15: 32768 shifts per second
81  */
82 #define TAMP_TAMP_CONTROL_SPEED_MASK (0xF0U)
83 #define TAMP_TAMP_CONTROL_SPEED_SHIFT (4U)
84 #define TAMP_TAMP_CONTROL_SPEED_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_SPEED_SHIFT) & TAMP_TAMP_CONTROL_SPEED_MASK)
85 #define TAMP_TAMP_CONTROL_SPEED_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_SPEED_MASK) >> TAMP_TAMP_CONTROL_SPEED_SHIFT)
86 
87 /*
88  * RECOVER (RW)
89  *
90  * tamper will recover itself if tamper LFSR goes wrong
91  * 0: tamper will not recover
92  * 1: tamper will recover
93  */
94 #define TAMP_TAMP_CONTROL_RECOVER_MASK (0x4U)
95 #define TAMP_TAMP_CONTROL_RECOVER_SHIFT (2U)
96 #define TAMP_TAMP_CONTROL_RECOVER_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_RECOVER_SHIFT) & TAMP_TAMP_CONTROL_RECOVER_MASK)
97 #define TAMP_TAMP_CONTROL_RECOVER_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_RECOVER_MASK) >> TAMP_TAMP_CONTROL_RECOVER_SHIFT)
98 
99 /*
100  * ACTIVE (RW)
101  *
102  * select active or passive tamper
103  * 0: passive tamper
104  * 1: active tamper
105  */
106 #define TAMP_TAMP_CONTROL_ACTIVE_MASK (0x2U)
107 #define TAMP_TAMP_CONTROL_ACTIVE_SHIFT (1U)
108 #define TAMP_TAMP_CONTROL_ACTIVE_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_ACTIVE_SHIFT) & TAMP_TAMP_CONTROL_ACTIVE_MASK)
109 #define TAMP_TAMP_CONTROL_ACTIVE_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_ACTIVE_MASK) >> TAMP_TAMP_CONTROL_ACTIVE_SHIFT)
110 
111 /*
112  * ENABLE (RW)
113  *
114  * enable tamper
115  * 0: tamper disableed
116  * 1: tamper enabled
117  */
118 #define TAMP_TAMP_CONTROL_ENABLE_MASK (0x1U)
119 #define TAMP_TAMP_CONTROL_ENABLE_SHIFT (0U)
120 #define TAMP_TAMP_CONTROL_ENABLE_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_ENABLE_SHIFT) & TAMP_TAMP_CONTROL_ENABLE_MASK)
121 #define TAMP_TAMP_CONTROL_ENABLE_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_ENABLE_MASK) >> TAMP_TAMP_CONTROL_ENABLE_SHIFT)
122 
123 /* Bitfield definition for register of struct array TAMP: POLY */
124 /*
125  * POLY (RW)
126  *
127  * tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1"
128  */
129 #define TAMP_TAMP_POLY_POLY_MASK (0xFFFFFFFFUL)
130 #define TAMP_TAMP_POLY_POLY_SHIFT (0U)
131 #define TAMP_TAMP_POLY_POLY_SET(x) (((uint32_t)(x) << TAMP_TAMP_POLY_POLY_SHIFT) & TAMP_TAMP_POLY_POLY_MASK)
132 #define TAMP_TAMP_POLY_POLY_GET(x) (((uint32_t)(x) & TAMP_TAMP_POLY_POLY_MASK) >> TAMP_TAMP_POLY_POLY_SHIFT)
133 
134 /* Bitfield definition for register of struct array TAMP: LFSR */
135 /*
136  * LFSR (WO)
137  *
138  * LFSR for active tamper, write only register, always read 0
139  */
140 #define TAMP_TAMP_LFSR_LFSR_MASK (0xFFFFFFFFUL)
141 #define TAMP_TAMP_LFSR_LFSR_SHIFT (0U)
142 #define TAMP_TAMP_LFSR_LFSR_SET(x) (((uint32_t)(x) << TAMP_TAMP_LFSR_LFSR_SHIFT) & TAMP_TAMP_LFSR_LFSR_MASK)
143 #define TAMP_TAMP_LFSR_LFSR_GET(x) (((uint32_t)(x) & TAMP_TAMP_LFSR_LFSR_MASK) >> TAMP_TAMP_LFSR_LFSR_SHIFT)
144 
145 /* Bitfield definition for register: TAMP_FLAG */
146 /*
147  * FLAG (RW)
148  *
149  * tamper flag, each bit represents one tamper pin, write 1 to clear the flag
150  * Note, clear can only be cleared when tamper disappeared
151  */
152 #define TAMP_TAMP_FLAG_FLAG_MASK (0xFFFU)
153 #define TAMP_TAMP_FLAG_FLAG_SHIFT (0U)
154 #define TAMP_TAMP_FLAG_FLAG_SET(x) (((uint32_t)(x) << TAMP_TAMP_FLAG_FLAG_SHIFT) & TAMP_TAMP_FLAG_FLAG_MASK)
155 #define TAMP_TAMP_FLAG_FLAG_GET(x) (((uint32_t)(x) & TAMP_TAMP_FLAG_FLAG_MASK) >> TAMP_TAMP_FLAG_FLAG_SHIFT)
156 
157 /* Bitfield definition for register: IRQ_EN */
158 /*
159  * LOCK (RW)
160  *
161  * lock bit for IRQ enable
162  * 0: enable bits can be changed
163  * 1: enable bits hold until next battery domain power cycle
164  */
165 #define TAMP_IRQ_EN_LOCK_MASK (0x80000000UL)
166 #define TAMP_IRQ_EN_LOCK_SHIFT (31U)
167 #define TAMP_IRQ_EN_LOCK_SET(x) (((uint32_t)(x) << TAMP_IRQ_EN_LOCK_SHIFT) & TAMP_IRQ_EN_LOCK_MASK)
168 #define TAMP_IRQ_EN_LOCK_GET(x) (((uint32_t)(x) & TAMP_IRQ_EN_LOCK_MASK) >> TAMP_IRQ_EN_LOCK_SHIFT)
169 
170 /*
171  * IRQ_EN (RW)
172  *
173  * interrupt enable, each bit represents one tamper pin
174  * 0: interrupt disabled
175  * 1: interrupt enabled
176  */
177 #define TAMP_IRQ_EN_IRQ_EN_MASK (0xFFFU)
178 #define TAMP_IRQ_EN_IRQ_EN_SHIFT (0U)
179 #define TAMP_IRQ_EN_IRQ_EN_SET(x) (((uint32_t)(x) << TAMP_IRQ_EN_IRQ_EN_SHIFT) & TAMP_IRQ_EN_IRQ_EN_MASK)
180 #define TAMP_IRQ_EN_IRQ_EN_GET(x) (((uint32_t)(x) & TAMP_IRQ_EN_IRQ_EN_MASK) >> TAMP_IRQ_EN_IRQ_EN_SHIFT)
181 
182 
183 
184 /* TAMP register group index macro definition */
185 #define TAMP_TAMP_TAMP0 (0UL)
186 #define TAMP_TAMP_TAMP1 (1UL)
187 #define TAMP_TAMP_TAMP2 (2UL)
188 #define TAMP_TAMP_TAMP3 (3UL)
189 
190 
191 #endif /* HPM_TAMP_H */
TAMP_Type
Definition: hpm_tamp_regs.h:12