HPM SDK
HPMicro Software Development Kit
hpm_dmamux_src.h
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_DMAMUX_SRC_H
10 #define HPM_DMAMUX_SRC_H
11 
12 /* dma mux definitions */
13 #define HPM_DMA_SRC_SPI0_RX (0x0UL) /* SPI0 Receive */
14 #define HPM_DMA_SRC_SPI0_TX (0x1UL) /* SPI0 Transmit */
15 #define HPM_DMA_SRC_SPI1_RX (0x2UL) /* SPI1 Receive */
16 #define HPM_DMA_SRC_SPI1_TX (0x3UL) /* SPI1 Transmit */
17 #define HPM_DMA_SRC_SPI2_RX (0x4UL) /* SPI2 Receive */
18 #define HPM_DMA_SRC_SPI2_TX (0x5UL) /* SPI2 Transmit */
19 #define HPM_DMA_SRC_UART0_RX (0x8UL) /* UART0 Receive */
20 #define HPM_DMA_SRC_UART0_TX (0x9UL) /* UART0 Transmit */
21 #define HPM_DMA_SRC_UART1_RX (0xAUL) /* UART1 Receive */
22 #define HPM_DMA_SRC_UART1_TX (0xBUL) /* UART1 Transmit */
23 #define HPM_DMA_SRC_UART2_RX (0xCUL) /* UART2 Receive */
24 #define HPM_DMA_SRC_UART2_TX (0xDUL) /* UART2 Transmit */
25 #define HPM_DMA_SRC_UART3_RX (0xEUL) /* UART3 Receive */
26 #define HPM_DMA_SRC_UART3_TX (0xFUL) /* UART3 Transmit */
27 #define HPM_DMA_SRC_I2C0 (0x18UL) /* I2C0 */
28 #define HPM_DMA_SRC_I2C1 (0x19UL) /* I2C1 */
29 #define HPM_DMA_SRC_I2C2 (0x1AUL) /* I2C2 */
30 #define HPM_DMA_SRC_MCAN0 (0x1CUL) /* CAN0 */
31 #define HPM_DMA_SRC_MCAN1 (0x1DUL) /* CAN1 */
32 #define HPM_DMA_SRC_GPTMR0_0 (0x30UL) /* GPTMR0 Channel 0 */
33 #define HPM_DMA_SRC_GPTMR0_1 (0x31UL) /* GPTMR0 Channel 1 */
34 #define HPM_DMA_SRC_GPTMR0_2 (0x32UL) /* GPTMR0 Channel 2 */
35 #define HPM_DMA_SRC_GPTMR0_3 (0x33UL) /* GPTMR0 Channel 3 */
36 #define HPM_DMA_SRC_GPTMR1_0 (0x34UL) /* GPTMR1 Channel 0 */
37 #define HPM_DMA_SRC_GPTMR1_1 (0x35UL) /* GPTMR1 Channel 1 */
38 #define HPM_DMA_SRC_GPTMR1_2 (0x36UL) /* GPTMR1 Channel 2 */
39 #define HPM_DMA_SRC_GPTMR1_3 (0x37UL) /* GPTMR1 Channel 3 */
40 #define HPM_DMA_SRC_GPTMR2_0 (0x38UL) /* GPTMR2 channel 0 */
41 #define HPM_DMA_SRC_GPTMR2_1 (0x39UL) /* GPTMR2 Channel 1 */
42 #define HPM_DMA_SRC_GPTMR2_2 (0x3AUL) /* GPTMR2 Channel 2 */
43 #define HPM_DMA_SRC_GPTMR2_3 (0x3BUL) /* GPTMR2 Channel 3 */
44 #define HPM_DMA_SRC_GPTMR3_0 (0x3CUL) /* GPTMR3 channel 0 */
45 #define HPM_DMA_SRC_GPTMR3_1 (0x3DUL) /* GPTMR3 Channel 1 */
46 #define HPM_DMA_SRC_GPTMR3_2 (0x3EUL) /* GPTMR3 Channel 2 */
47 #define HPM_DMA_SRC_GPTMR3_3 (0x3FUL) /* GPTMR3 Channel 3 */
48 #define HPM_DMA_SRC_MOT_0 (0x40UL) /* TRGM0 DMA request 0 (contains DMA requests for PWM0, PWM1, PWM2, PWM3, QEI0, QEI1, SEI0, SEI1) */
49 #define HPM_DMA_SRC_MOT_1 (0x41UL) /* TRGM0 DMA request 1 (contains DMA requests for PWM0, PWM1, PWM2, PWM3, QEI0, QEI1, SEI0, SEI1) */
50 #define HPM_DMA_SRC_MOT_2 (0x42UL) /* TRGM0 DMA request 2 (contains DMA requests for PWM0, PWM1, PWM2, PWM3, QEI0, QEI1, SEI0, SEI1) */
51 #define HPM_DMA_SRC_MOT_3 (0x43UL) /* TRGM0 DMA request 3 (contains DMA requests for PWM0, PWM1, PWM2, PWM3, QEI0, QEI1, SEI0, SEI1) */
52 #define HPM_DMA_SRC_MOT_4 (0x44UL) /* TRGM0 DMA request 4 (contains DMA requests for PWM0, PWM1, PWM2, PWM3, QEI0, QEI1, SEI0, SEI1) */
53 #define HPM_DMA_SRC_MOT_5 (0x45UL) /* TRGM0 DMA request 5 (contains DMA requests for PWM0, PWM1, PWM2, PWM3, QEI0, QEI1, SEI0, SEI1) */
54 #define HPM_DMA_SRC_MOT_6 (0x46UL) /* TRGM0 DMA request 6 (contains DMA requests for PWM0, PWM1, PWM2, PWM3, QEI0, QEI1, SEI0, SEI1) */
55 #define HPM_DMA_SRC_MOT_7 (0x47UL) /* TRGM0 DMA request 7 (contains DMA requests for PWM0, PWM1, PWM2, PWM3, QEI0, QEI1, SEI0, SEI1) */
56 #define HPM_DMA_SRC_ACMP0_0 (0x48UL) /* ACMP0 Channel 0 */
57 #define HPM_DMA_SRC_ACMP0_1 (0x49UL) /* ACMP0 Channel 1 */
58 #define HPM_DMA_SRC_ACMP1_0 (0x4AUL) /* ACMP1 Channel 0 */
59 #define HPM_DMA_SRC_ACMP1_1 (0x4BUL) /* ACMP1 Channel 1 */
60 #define HPM_DMA_SRC_ACMP2_0 (0x4CUL) /* ACMP2 Channel 0 */
61 #define HPM_DMA_SRC_ACMP2_1 (0x4DUL) /* ACMP2 Channel 1 */
62 #define HPM_DMA_SRC_ACMP3_0 (0x4EUL) /* ACMP3 Channel 0 */
63 #define HPM_DMA_SRC_ACMP3_1 (0x4FUL) /* ACMP3 Channel 1 */
64 #define HPM_DMA_SRC_DAC0 (0x50UL) /* DAC0 */
65 #define HPM_DMA_SRC_DAC1 (0x51UL) /* DAC1 */
66 #define HPM_DMA_SRC_XPI0_RX (0x52UL) /* XPI0 Receive */
67 #define HPM_DMA_SRC_XPI0_TX (0x53UL) /* XPI0 Transmit */
68 
69 
70 
71 #endif /* HPM_DMAMUX_SRC_H */