HPM SDK
HPMicro Software Development Kit
hpm_pdgo_regs.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_PDGO_H
10 #define HPM_PDGO_H
11 
12 typedef struct {
13  __W uint32_t DGO_TURNOFF; /* 0x0: trunoff control */
14  __RW uint32_t DGO_RC32K_CFG; /* 0x4: RC32K CLOCK */
15  __R uint8_t RESERVED0[1528]; /* 0x8 - 0x5FF: Reserved */
16  __RW uint32_t DGO_GPR00; /* 0x600: Generic control 0 */
17  __RW uint32_t DGO_GPR01; /* 0x604: Generic control 1 */
18  __RW uint32_t DGO_GPR02; /* 0x608: Generic control 2 */
19  __RW uint32_t DGO_GPR03; /* 0x60C: Generic control 3 */
20  __R uint8_t RESERVED1[240]; /* 0x610 - 0x6FF: Reserved */
21  __RW uint32_t DGO_CTR0; /* 0x700: control register 0 */
22  __RW uint32_t DGO_CTR1; /* 0x704: control register 1 */
23  __RW uint32_t DGO_CTR2; /* 0x708: control register 2 */
24  __RW uint32_t DGO_CTR3; /* 0x70C: control register 3 */
25  __RW uint32_t DGO_CTR4; /* 0x710: control register 4 */
26 } PDGO_Type;
27 
28 
29 /* Bitfield definition for register: DGO_TURNOFF */
30 /*
31  * COUNTER (WO)
32  *
33  * trunoff counter, counter stops when it counts down to 0, the trunoff occurs when the counter value is 1.
34  */
35 #define PDGO_DGO_TURNOFF_COUNTER_MASK (0xFFFFFFFFUL)
36 #define PDGO_DGO_TURNOFF_COUNTER_SHIFT (0U)
37 #define PDGO_DGO_TURNOFF_COUNTER_SET(x) (((uint32_t)(x) << PDGO_DGO_TURNOFF_COUNTER_SHIFT) & PDGO_DGO_TURNOFF_COUNTER_MASK)
38 #define PDGO_DGO_TURNOFF_COUNTER_GET(x) (((uint32_t)(x) & PDGO_DGO_TURNOFF_COUNTER_MASK) >> PDGO_DGO_TURNOFF_COUNTER_SHIFT)
39 
40 /* Bitfield definition for register: DGO_RC32K_CFG */
41 /*
42  * IRC_TRIMMED (RW)
43  *
44  * IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value
45  * 0: irc is not trimmed
46  * 1: irc is trimmed
47  */
48 #define PDGO_DGO_RC32K_CFG_IRC_TRIMMED_MASK (0x80000000UL)
49 #define PDGO_DGO_RC32K_CFG_IRC_TRIMMED_SHIFT (31U)
50 #define PDGO_DGO_RC32K_CFG_IRC_TRIMMED_SET(x) (((uint32_t)(x) << PDGO_DGO_RC32K_CFG_IRC_TRIMMED_SHIFT) & PDGO_DGO_RC32K_CFG_IRC_TRIMMED_MASK)
51 #define PDGO_DGO_RC32K_CFG_IRC_TRIMMED_GET(x) (((uint32_t)(x) & PDGO_DGO_RC32K_CFG_IRC_TRIMMED_MASK) >> PDGO_DGO_RC32K_CFG_IRC_TRIMMED_SHIFT)
52 
53 /*
54  * CAPEX7_TRIM (RW)
55  *
56  * IRC32K bit 7
57  */
58 #define PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_MASK (0x800000UL)
59 #define PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_SHIFT (23U)
60 #define PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_SET(x) (((uint32_t)(x) << PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_SHIFT) & PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_MASK)
61 #define PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_GET(x) (((uint32_t)(x) & PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_MASK) >> PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_SHIFT)
62 
63 /*
64  * CAPEX6_TRIM (RW)
65  *
66  * IRC32K bit 6
67  */
68 #define PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_MASK (0x400000UL)
69 #define PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_SHIFT (22U)
70 #define PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_SET(x) (((uint32_t)(x) << PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_SHIFT) & PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_MASK)
71 #define PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_GET(x) (((uint32_t)(x) & PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_MASK) >> PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_SHIFT)
72 
73 /*
74  * CAP_TRIM (RW)
75  *
76  * capacitor trim bits
77  */
78 #define PDGO_DGO_RC32K_CFG_CAP_TRIM_MASK (0x1FFU)
79 #define PDGO_DGO_RC32K_CFG_CAP_TRIM_SHIFT (0U)
80 #define PDGO_DGO_RC32K_CFG_CAP_TRIM_SET(x) (((uint32_t)(x) << PDGO_DGO_RC32K_CFG_CAP_TRIM_SHIFT) & PDGO_DGO_RC32K_CFG_CAP_TRIM_MASK)
81 #define PDGO_DGO_RC32K_CFG_CAP_TRIM_GET(x) (((uint32_t)(x) & PDGO_DGO_RC32K_CFG_CAP_TRIM_MASK) >> PDGO_DGO_RC32K_CFG_CAP_TRIM_SHIFT)
82 
83 /* Bitfield definition for register: DGO_GPR00 */
84 /*
85  * GPR (RW)
86  *
87  * Generic control
88  */
89 #define PDGO_DGO_GPR00_GPR_MASK (0xFFFFFFFFUL)
90 #define PDGO_DGO_GPR00_GPR_SHIFT (0U)
91 #define PDGO_DGO_GPR00_GPR_SET(x) (((uint32_t)(x) << PDGO_DGO_GPR00_GPR_SHIFT) & PDGO_DGO_GPR00_GPR_MASK)
92 #define PDGO_DGO_GPR00_GPR_GET(x) (((uint32_t)(x) & PDGO_DGO_GPR00_GPR_MASK) >> PDGO_DGO_GPR00_GPR_SHIFT)
93 
94 /* Bitfield definition for register: DGO_GPR01 */
95 /*
96  * GPR (RW)
97  *
98  * Generic control
99  */
100 #define PDGO_DGO_GPR01_GPR_MASK (0xFFFFFFFFUL)
101 #define PDGO_DGO_GPR01_GPR_SHIFT (0U)
102 #define PDGO_DGO_GPR01_GPR_SET(x) (((uint32_t)(x) << PDGO_DGO_GPR01_GPR_SHIFT) & PDGO_DGO_GPR01_GPR_MASK)
103 #define PDGO_DGO_GPR01_GPR_GET(x) (((uint32_t)(x) & PDGO_DGO_GPR01_GPR_MASK) >> PDGO_DGO_GPR01_GPR_SHIFT)
104 
105 /* Bitfield definition for register: DGO_GPR02 */
106 /*
107  * GPR (RW)
108  *
109  * Generic control
110  */
111 #define PDGO_DGO_GPR02_GPR_MASK (0xFFFFFFFFUL)
112 #define PDGO_DGO_GPR02_GPR_SHIFT (0U)
113 #define PDGO_DGO_GPR02_GPR_SET(x) (((uint32_t)(x) << PDGO_DGO_GPR02_GPR_SHIFT) & PDGO_DGO_GPR02_GPR_MASK)
114 #define PDGO_DGO_GPR02_GPR_GET(x) (((uint32_t)(x) & PDGO_DGO_GPR02_GPR_MASK) >> PDGO_DGO_GPR02_GPR_SHIFT)
115 
116 /* Bitfield definition for register: DGO_GPR03 */
117 /*
118  * GPR (RW)
119  *
120  * Generic control
121  */
122 #define PDGO_DGO_GPR03_GPR_MASK (0xFFFFFFFFUL)
123 #define PDGO_DGO_GPR03_GPR_SHIFT (0U)
124 #define PDGO_DGO_GPR03_GPR_SET(x) (((uint32_t)(x) << PDGO_DGO_GPR03_GPR_SHIFT) & PDGO_DGO_GPR03_GPR_MASK)
125 #define PDGO_DGO_GPR03_GPR_GET(x) (((uint32_t)(x) & PDGO_DGO_GPR03_GPR_MASK) >> PDGO_DGO_GPR03_GPR_SHIFT)
126 
127 /* Bitfield definition for register: DGO_CTR0 */
128 /*
129  * RETENTION (RW)
130  *
131  * dgo register status retenion
132  */
133 #define PDGO_DGO_CTR0_RETENTION_MASK (0x10000UL)
134 #define PDGO_DGO_CTR0_RETENTION_SHIFT (16U)
135 #define PDGO_DGO_CTR0_RETENTION_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR0_RETENTION_SHIFT) & PDGO_DGO_CTR0_RETENTION_MASK)
136 #define PDGO_DGO_CTR0_RETENTION_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR0_RETENTION_MASK) >> PDGO_DGO_CTR0_RETENTION_SHIFT)
137 
138 /* Bitfield definition for register: DGO_CTR1 */
139 /*
140  * AOTO_SYS_WAKEUP (RW)
141  *
142  * software wakeup： 0 : wakeup once； 1：auto wakeup Continuously
143  */
144 #define PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_MASK (0x80000000UL)
145 #define PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_SHIFT (31U)
146 #define PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_SHIFT) & PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_MASK)
147 #define PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_MASK) >> PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_SHIFT)
148 
149 /*
150  * WAKEUP_EN (RW)
151  *
152  * permit wakeup pin or software wakeup
153  */
154 #define PDGO_DGO_CTR1_WAKEUP_EN_MASK (0x10000UL)
155 #define PDGO_DGO_CTR1_WAKEUP_EN_SHIFT (16U)
156 #define PDGO_DGO_CTR1_WAKEUP_EN_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR1_WAKEUP_EN_SHIFT) & PDGO_DGO_CTR1_WAKEUP_EN_MASK)
157 #define PDGO_DGO_CTR1_WAKEUP_EN_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR1_WAKEUP_EN_MASK) >> PDGO_DGO_CTR1_WAKEUP_EN_SHIFT)
158 
159 /*
160  * PIN_WAKEUP_STATUS (RO)
161  *
162  * wakeup pin status
163  */
164 #define PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_MASK (0x1U)
165 #define PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_SHIFT (0U)
166 #define PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_MASK) >> PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_SHIFT)
167 
168 /* Bitfield definition for register: DGO_CTR2 */
169 /*
170  * RESETN_PULLUP_DISABLE (RW)
171  *
172  * resetn pin pull up disable
173  */
174 #define PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_MASK (0x1000000UL)
175 #define PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_SHIFT (24U)
176 #define PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_SHIFT) & PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_MASK)
177 #define PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_MASK) >> PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_SHIFT)
178 
179 /*
180  * WAKEUP_PULLDN_DISABLE (RW)
181  *
182  * wakeup pin pull down disable
183  */
184 #define PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_MASK (0x10000UL)
185 #define PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_SHIFT (16U)
186 #define PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_SHIFT) & PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_MASK)
187 #define PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_MASK) >> PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_SHIFT)
188 
189 /* Bitfield definition for register: DGO_CTR3 */
190 /*
191  * WAKEUP_COUNTER (RW)
192  *
193  * software wakeup counter
194  */
195 #define PDGO_DGO_CTR3_WAKEUP_COUNTER_MASK (0xFFFFFFFFUL)
196 #define PDGO_DGO_CTR3_WAKEUP_COUNTER_SHIFT (0U)
197 #define PDGO_DGO_CTR3_WAKEUP_COUNTER_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR3_WAKEUP_COUNTER_SHIFT) & PDGO_DGO_CTR3_WAKEUP_COUNTER_MASK)
198 #define PDGO_DGO_CTR3_WAKEUP_COUNTER_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR3_WAKEUP_COUNTER_MASK) >> PDGO_DGO_CTR3_WAKEUP_COUNTER_SHIFT)
199 
200 /* Bitfield definition for register: DGO_CTR4 */
201 /*
202  * BANDGAP_LESS_POWER (RW)
203  *
204  * Banggap work in power save mode, banggap function normally
205  * 0: banggap works in high performance mode
206  * 1: banggap works in power saving mode
207  */
208 #define PDGO_DGO_CTR4_BANDGAP_LESS_POWER_MASK (0x2U)
209 #define PDGO_DGO_CTR4_BANDGAP_LESS_POWER_SHIFT (1U)
210 #define PDGO_DGO_CTR4_BANDGAP_LESS_POWER_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR4_BANDGAP_LESS_POWER_SHIFT) & PDGO_DGO_CTR4_BANDGAP_LESS_POWER_MASK)
211 #define PDGO_DGO_CTR4_BANDGAP_LESS_POWER_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR4_BANDGAP_LESS_POWER_MASK) >> PDGO_DGO_CTR4_BANDGAP_LESS_POWER_SHIFT)
212 
213 /*
214  * BANDGAP_LP_MODE (RW)
215  *
216  * Banggap work in low power mode, banggap function limited
217  * 0: banggap works in normal mode
218  * 1: banggap works in low power mode
219  */
220 #define PDGO_DGO_CTR4_BANDGAP_LP_MODE_MASK (0x1U)
221 #define PDGO_DGO_CTR4_BANDGAP_LP_MODE_SHIFT (0U)
222 #define PDGO_DGO_CTR4_BANDGAP_LP_MODE_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR4_BANDGAP_LP_MODE_SHIFT) & PDGO_DGO_CTR4_BANDGAP_LP_MODE_MASK)
223 #define PDGO_DGO_CTR4_BANDGAP_LP_MODE_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR4_BANDGAP_LP_MODE_MASK) >> PDGO_DGO_CTR4_BANDGAP_LP_MODE_SHIFT)
224 
225 
226 
227 
228 #endif /* HPM_PDGO_H */
PDGO_Type
Definition: hpm_pdgo_regs.h:12