HPM SDK
HPMicro Software Development Kit
hpm_plb_regs.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_PLB_H
10 #define HPM_PLB_H
11 
12 typedef struct {
13  struct {
14  __RW uint32_t LOOKUP_TABLE[4]; /* 0x0 - 0xC: TYPE A CHN lookup_table 0 */
15  __RW uint32_t SW_INJECT; /* 0x10: TYPE A CHN software inject */
16  __R uint8_t RESERVED0[12]; /* 0x14 - 0x1F: Reserved */
17  } TYPE_A[8];
18  __R uint8_t RESERVED0[768]; /* 0x100 - 0x3FF: Reserved */
19  struct {
20  __RW uint32_t LUT[2]; /* 0x400 - 0x404: TYPE B CHN lookup table 0 */
21  __RW uint32_t CMP[4]; /* 0x408 - 0x414: TYPE B CHN data unit cmp0 */
22  __RW uint32_t MODE; /* 0x418: TYPE B CHN mode ctrl */
23  __RW uint32_t SW_INJECT; /* 0x41C: TYPE B CHN software inject */
24  __RW uint32_t LUT_CMP[4]; /* 0x420 - 0x42C: TYPE B CHN cmp0 lut */
25  __R uint8_t RESERVED0[80]; /* 0x430 - 0x47F: Reserved */
26  } TYPE_B[8];
27 } PLB_Type;
28 
29 
30 /* Bitfield definition for register of struct array TYPE_A: 0 */
31 /*
32  * LOOKUP_TABLE (RW)
33  *
34  * using 4 bit trig_in as lookup index. software can program this register as trig_in's true table.
35  */
36 #define PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_MASK (0xFFFFU)
37 #define PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_SHIFT (0U)
38 #define PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_SET(x) (((uint32_t)(x) << PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_SHIFT) & PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_MASK)
39 #define PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_GET(x) (((uint32_t)(x) & PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_MASK) >> PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_SHIFT)
40 
41 /* Bitfield definition for register of struct array TYPE_A: SW_INJECT */
42 /*
43  * SW_INJECT (RW)
44  *
45  * software can inject value to TYPEA's output
46  */
47 #define PLB_TYPE_A_SW_INJECT_SW_INJECT_MASK (0xFU)
48 #define PLB_TYPE_A_SW_INJECT_SW_INJECT_SHIFT (0U)
49 #define PLB_TYPE_A_SW_INJECT_SW_INJECT_SET(x) (((uint32_t)(x) << PLB_TYPE_A_SW_INJECT_SW_INJECT_SHIFT) & PLB_TYPE_A_SW_INJECT_SW_INJECT_MASK)
50 #define PLB_TYPE_A_SW_INJECT_SW_INJECT_GET(x) (((uint32_t)(x) & PLB_TYPE_A_SW_INJECT_SW_INJECT_MASK) >> PLB_TYPE_A_SW_INJECT_SW_INJECT_SHIFT)
51 
52 /* Bitfield definition for register of struct array TYPE_B: 0 */
53 /*
54  * LOOKUP_TABLE (RW)
55  *
56  * lut0 and lut1 union as 64bit, consider each 4bit as one slice. then, total 16 slice. slice0 as bit3:0, slice1 as bit7:4...etc. using 4bit trig in as index of slice. the operate sel in data unit of type B channle is decided by which slice value choosed by trig_in
57  */
58 #define PLB_TYPE_B_LUT_LOOKUP_TABLE_MASK (0xFFFFFFFFUL)
59 #define PLB_TYPE_B_LUT_LOOKUP_TABLE_SHIFT (0U)
60 #define PLB_TYPE_B_LUT_LOOKUP_TABLE_SET(x) (((uint32_t)(x) << PLB_TYPE_B_LUT_LOOKUP_TABLE_SHIFT) & PLB_TYPE_B_LUT_LOOKUP_TABLE_MASK)
61 #define PLB_TYPE_B_LUT_LOOKUP_TABLE_GET(x) (((uint32_t)(x) & PLB_TYPE_B_LUT_LOOKUP_TABLE_MASK) >> PLB_TYPE_B_LUT_LOOKUP_TABLE_SHIFT)
62 
63 /* Bitfield definition for register of struct array TYPE_B: 0 */
64 /*
65  * CMP_VALUE (RW)
66  *
67  * cmp value, using as data unit operation
68  */
69 #define PLB_TYPE_B_CMP_CMP_VALUE_MASK (0xFFFFFFFFUL)
70 #define PLB_TYPE_B_CMP_CMP_VALUE_SHIFT (0U)
71 #define PLB_TYPE_B_CMP_CMP_VALUE_SET(x) (((uint32_t)(x) << PLB_TYPE_B_CMP_CMP_VALUE_SHIFT) & PLB_TYPE_B_CMP_CMP_VALUE_MASK)
72 #define PLB_TYPE_B_CMP_CMP_VALUE_GET(x) (((uint32_t)(x) & PLB_TYPE_B_CMP_CMP_VALUE_MASK) >> PLB_TYPE_B_CMP_CMP_VALUE_SHIFT)
73 
74 /* Bitfield definition for register of struct array TYPE_B: MODE */
75 /*
76  * OPT_SEL (RW)
77  *
78  * operation selection in data unit.
79  */
80 #define PLB_TYPE_B_MODE_OPT_SEL_MASK (0x10000UL)
81 #define PLB_TYPE_B_MODE_OPT_SEL_SHIFT (16U)
82 #define PLB_TYPE_B_MODE_OPT_SEL_SET(x) (((uint32_t)(x) << PLB_TYPE_B_MODE_OPT_SEL_SHIFT) & PLB_TYPE_B_MODE_OPT_SEL_MASK)
83 #define PLB_TYPE_B_MODE_OPT_SEL_GET(x) (((uint32_t)(x) & PLB_TYPE_B_MODE_OPT_SEL_MASK) >> PLB_TYPE_B_MODE_OPT_SEL_SHIFT)
84 
85 /*
86  * OUT3_SEL (RW)
87  *
88  * trig out 3 output type in current channel
89  */
90 #define PLB_TYPE_B_MODE_OUT3_SEL_MASK (0xF000U)
91 #define PLB_TYPE_B_MODE_OUT3_SEL_SHIFT (12U)
92 #define PLB_TYPE_B_MODE_OUT3_SEL_SET(x) (((uint32_t)(x) << PLB_TYPE_B_MODE_OUT3_SEL_SHIFT) & PLB_TYPE_B_MODE_OUT3_SEL_MASK)
93 #define PLB_TYPE_B_MODE_OUT3_SEL_GET(x) (((uint32_t)(x) & PLB_TYPE_B_MODE_OUT3_SEL_MASK) >> PLB_TYPE_B_MODE_OUT3_SEL_SHIFT)
94 
95 /*
96  * OUT2_SEL (RW)
97  *
98  * trig out 2 output type in current channel
99  */
100 #define PLB_TYPE_B_MODE_OUT2_SEL_MASK (0xF00U)
101 #define PLB_TYPE_B_MODE_OUT2_SEL_SHIFT (8U)
102 #define PLB_TYPE_B_MODE_OUT2_SEL_SET(x) (((uint32_t)(x) << PLB_TYPE_B_MODE_OUT2_SEL_SHIFT) & PLB_TYPE_B_MODE_OUT2_SEL_MASK)
103 #define PLB_TYPE_B_MODE_OUT2_SEL_GET(x) (((uint32_t)(x) & PLB_TYPE_B_MODE_OUT2_SEL_MASK) >> PLB_TYPE_B_MODE_OUT2_SEL_SHIFT)
104 
105 /*
106  * OUT1_SEL (RW)
107  *
108  * trig out 1 output type in current channel
109  */
110 #define PLB_TYPE_B_MODE_OUT1_SEL_MASK (0xF0U)
111 #define PLB_TYPE_B_MODE_OUT1_SEL_SHIFT (4U)
112 #define PLB_TYPE_B_MODE_OUT1_SEL_SET(x) (((uint32_t)(x) << PLB_TYPE_B_MODE_OUT1_SEL_SHIFT) & PLB_TYPE_B_MODE_OUT1_SEL_MASK)
113 #define PLB_TYPE_B_MODE_OUT1_SEL_GET(x) (((uint32_t)(x) & PLB_TYPE_B_MODE_OUT1_SEL_MASK) >> PLB_TYPE_B_MODE_OUT1_SEL_SHIFT)
114 
115 /*
116  * OUT0_SEL (RW)
117  *
118  * trig out 0 output type in current channel
119  */
120 #define PLB_TYPE_B_MODE_OUT0_SEL_MASK (0xFU)
121 #define PLB_TYPE_B_MODE_OUT0_SEL_SHIFT (0U)
122 #define PLB_TYPE_B_MODE_OUT0_SEL_SET(x) (((uint32_t)(x) << PLB_TYPE_B_MODE_OUT0_SEL_SHIFT) & PLB_TYPE_B_MODE_OUT0_SEL_MASK)
123 #define PLB_TYPE_B_MODE_OUT0_SEL_GET(x) (((uint32_t)(x) & PLB_TYPE_B_MODE_OUT0_SEL_MASK) >> PLB_TYPE_B_MODE_OUT0_SEL_SHIFT)
124 
125 /* Bitfield definition for register of struct array TYPE_B: SW_INJECT */
126 /*
127  * SOFTWARE_INJECT (RW)
128  *
129  * data unit value can be changed if program this register
130  */
131 #define PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_MASK (0xFFFFFFFFUL)
132 #define PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_SHIFT (0U)
133 #define PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_SET(x) (((uint32_t)(x) << PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_SHIFT) & PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_MASK)
134 #define PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_GET(x) (((uint32_t)(x) & PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_MASK) >> PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_SHIFT)
135 
136 /* Bitfield definition for register of struct array TYPE_B: 0 */
137 /*
138  * LUT_CMP (RW)
139  *
140  * using 4 bit trig_in as lookup index. software can program this register as cmp load control's true table.
141  */
142 #define PLB_TYPE_B_LUT_CMP_LUT_CMP_MASK (0xFFFFU)
143 #define PLB_TYPE_B_LUT_CMP_LUT_CMP_SHIFT (0U)
144 #define PLB_TYPE_B_LUT_CMP_LUT_CMP_SET(x) (((uint32_t)(x) << PLB_TYPE_B_LUT_CMP_LUT_CMP_SHIFT) & PLB_TYPE_B_LUT_CMP_LUT_CMP_MASK)
145 #define PLB_TYPE_B_LUT_CMP_LUT_CMP_GET(x) (((uint32_t)(x) & PLB_TYPE_B_LUT_CMP_LUT_CMP_MASK) >> PLB_TYPE_B_LUT_CMP_LUT_CMP_SHIFT)
146 
147 
148 
149 /* LOOKUP_TABLE register group index macro definition */
150 #define PLB_TYPE_A_LOOKUP_TABLE_0 (0UL)
151 #define PLB_TYPE_A_LOOKUP_TABLE_1 (1UL)
152 #define PLB_TYPE_A_LOOKUP_TABLE_2 (2UL)
153 #define PLB_TYPE_A_LOOKUP_TABLE_3 (3UL)
154 
155 /* TYPE_A register group index macro definition */
156 #define PLB_TYPE_A_0 (0UL)
157 #define PLB_TYPE_A_1 (1UL)
158 #define PLB_TYPE_A_2 (2UL)
159 #define PLB_TYPE_A_3 (3UL)
160 #define PLB_TYPE_A_4 (4UL)
161 #define PLB_TYPE_A_5 (5UL)
162 #define PLB_TYPE_A_6 (6UL)
163 #define PLB_TYPE_A_7 (7UL)
164 
165 /* LUT register group index macro definition */
166 #define PLB_TYPE_B_LUT_0 (0UL)
167 #define PLB_TYPE_B_LUT_1 (1UL)
168 
169 /* CMP register group index macro definition */
170 #define PLB_TYPE_B_CMP_0 (0UL)
171 #define PLB_TYPE_B_CMP_1 (1UL)
172 #define PLB_TYPE_B_CMP_2 (2UL)
173 #define PLB_TYPE_B_CMP_3 (3UL)
174 
175 /* LUT_CMP register group index macro definition */
176 #define PLB_TYPE_B_LUT_CMP_0 (0UL)
177 #define PLB_TYPE_B_LUT_CMP_1 (1UL)
178 #define PLB_TYPE_B_LUT_CMP_2 (2UL)
179 #define PLB_TYPE_B_LUT_CMP_3 (3UL)
180 
181 /* TYPE_B register group index macro definition */
182 #define PLB_TYPE_B_0 (0UL)
183 #define PLB_TYPE_B_1 (1UL)
184 #define PLB_TYPE_B_2 (2UL)
185 #define PLB_TYPE_B_3 (3UL)
186 #define PLB_TYPE_B_4 (4UL)
187 #define PLB_TYPE_B_5 (5UL)
188 #define PLB_TYPE_B_6 (6UL)
189 #define PLB_TYPE_B_7 (7UL)
190 
191 
192 #endif /* HPM_PLB_H */
PLB_Type
Definition: hpm_plb_regs.h:12