HPM SDK
HPMicro Software Development Kit
hpm_pwmv2_regs.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_PWMV2_H
10 #define HPM_PWMV2_H
11 
12 typedef struct {
13  __RW uint32_t WORK_CTRL0; /* 0x0: */
14  __RW uint32_t UNLOCK; /* 0x4: */
15  __RW uint32_t SHADOW_VAL[28]; /* 0x8 - 0x74: */
16  __RW uint32_t FORCE_MODE; /* 0x78: */
17  __RW uint32_t WORK_CTRL1; /* 0x7C: */
18  __R uint8_t RESERVED0[128]; /* 0x80 - 0xFF: Reserved */
19  struct {
20  __RW uint32_t CFG0; /* 0x100: */
21  __RW uint32_t CFG1; /* 0x104: */
22  __RW uint32_t DEAD_AREA; /* 0x108: */
23  __RW uint32_t CFG3; /* 0x10C: */
24  } PWM[8];
25  __RW uint32_t TRIGGER_CFG[8]; /* 0x180 - 0x19C: */
26  __R uint8_t RESERVED1[80]; /* 0x1A0 - 0x1EF: Reserved */
27  __RW uint32_t GLB_CTRL; /* 0x1F0: */
28  __RW uint32_t GLB_CTRL2; /* 0x1F4: */
29  __RW uint32_t GLB_CTRL3; /* 0x1F8: */
30  __R uint8_t RESERVED2[4]; /* 0x1FC - 0x1FF: Reserved */
31  __R uint32_t CNT_RELOAD_WORK[4]; /* 0x200 - 0x20C: */
32  __R uint32_t CMP_VAL_WORK[24]; /* 0x210 - 0x26C: */
33  __R uint8_t RESERVED3[12]; /* 0x270 - 0x27B: Reserved */
34  __R uint32_t FORCE_WORK; /* 0x27C: */
35  __R uint8_t RESERVED4[32]; /* 0x280 - 0x29F: Reserved */
36  __R uint32_t CNT_VAL[4]; /* 0x2A0 - 0x2AC: */
37  __RW uint32_t DAC_VALUE_SV[4]; /* 0x2B0 - 0x2BC: */
38  __R uint8_t RESERVED5[64]; /* 0x2C0 - 0x2FF: Reserved */
39  __RW uint32_t CAPTURE_POS[8]; /* 0x300 - 0x31C: */
40  __R uint8_t RESERVED6[96]; /* 0x320 - 0x37F: Reserved */
41  __R uint32_t CAPTURE_NEG[8]; /* 0x380 - 0x39C: */
42  __R uint8_t RESERVED7[96]; /* 0x3A0 - 0x3FF: Reserved */
43  __RW uint32_t IRQ_STS; /* 0x400: */
44  __RW uint32_t IRQ_EN; /* 0x404: */
45  __R uint8_t RESERVED8[8]; /* 0x408 - 0x40F: Reserved */
46  __W uint32_t IRQ_STS_CMP; /* 0x410: */
47  __W uint32_t IRQ_STS_RELOAD; /* 0x414: */
48  __W uint32_t IRQ_STS_CAP_POS; /* 0x418: */
49  __W uint32_t IRQ_STS_CAP_NEG; /* 0x41C: */
50  __W uint32_t IRQ_STS_FAULT; /* 0x420: */
51  __W uint32_t IRQ_STS_BURSTEND; /* 0x424: */
52  __R uint8_t RESERVED9[8]; /* 0x428 - 0x42F: Reserved */
53  __RW uint32_t IRQ_EN_CMP; /* 0x430: */
54  __RW uint32_t IRQ_EN_RELOAD; /* 0x434: */
55  __RW uint32_t IRQ_EN_CAP_POS; /* 0x438: */
56  __RW uint32_t IRQ_EN_CAP_NEG; /* 0x43C: */
57  __RW uint32_t IRQ_EN_FAULT; /* 0x440: */
58  __RW uint32_t IRQ_EN_BURSTEND; /* 0x444: */
59  __R uint8_t RESERVED10[56]; /* 0x448 - 0x47F: Reserved */
60  __RW uint32_t DMA_EN; /* 0x480: */
61  __R uint8_t RESERVED11[124]; /* 0x484 - 0x4FF: Reserved */
62  struct {
63  __RW uint32_t CFG0; /* 0x500: */
64  __RW uint32_t CFG1; /* 0x504: */
65  __RW uint32_t CFG2; /* 0x508: */
66  __RW uint32_t CFG3; /* 0x50C: */
67  } CNT[4];
68  __RW uint32_t CNT_GLBCFG; /* 0x540: */
69  __R uint8_t RESERVED12[188]; /* 0x544 - 0x5FF: Reserved */
70  struct {
71  __RW uint32_t CFG0; /* 0x600: */
72  __RW uint32_t CFG1; /* 0x604: */
73  __R uint8_t RESERVED0[8]; /* 0x608 - 0x60F: Reserved */
74  } CAL[16];
75  __R uint8_t RESERVED13[256]; /* 0x700 - 0x7FF: Reserved */
76  struct {
77  __RW uint32_t CFG; /* 0x800: */
78  __R uint8_t RESERVED0[12]; /* 0x804 - 0x80F: Reserved */
79  } CMP[24];
80 } PWMV2_Type;
81 
82 
83 /* Bitfield definition for register: WORK_CTRL0 */
84 /*
85  * SHADOW_UNLOCK (RW)
86  *
87  * write 0x… first to unlock, then set related bits in unlock_sel to unlock following shadow registers(from 0x04 to 0x78),
88  * otherwise the shadow registers can not be written.
89  * The shadow registers will be loaded to work registers only when shadow_lock is 1 or lock is not enabled
90  * This bit can be cleared by set shadow_lock bit in work_ctrl1
91  */
92 #define PWMV2_WORK_CTRL0_SHADOW_UNLOCK_MASK (0x80000000UL)
93 #define PWMV2_WORK_CTRL0_SHADOW_UNLOCK_SHIFT (31U)
94 #define PWMV2_WORK_CTRL0_SHADOW_UNLOCK_SET(x) (((uint32_t)(x) << PWMV2_WORK_CTRL0_SHADOW_UNLOCK_SHIFT) & PWMV2_WORK_CTRL0_SHADOW_UNLOCK_MASK)
95 #define PWMV2_WORK_CTRL0_SHADOW_UNLOCK_GET(x) (((uint32_t)(x) & PWMV2_WORK_CTRL0_SHADOW_UNLOCK_MASK) >> PWMV2_WORK_CTRL0_SHADOW_UNLOCK_SHIFT)
96 
97 /* Bitfield definition for register: UNLOCK */
98 /*
99  * UNLOCK_BIT (RW)
100  *
101  * bit2 to bit 29 for value_shadow, bit30 for force_mode
102  * the shadow registers can be updated only when related unlock_bit is set;
103  * this register can only be updated after unlock
104  */
105 #define PWMV2_UNLOCK_UNLOCK_BIT_MASK (0xFFFFFFFFUL)
106 #define PWMV2_UNLOCK_UNLOCK_BIT_SHIFT (0U)
107 #define PWMV2_UNLOCK_UNLOCK_BIT_SET(x) (((uint32_t)(x) << PWMV2_UNLOCK_UNLOCK_BIT_SHIFT) & PWMV2_UNLOCK_UNLOCK_BIT_MASK)
108 #define PWMV2_UNLOCK_UNLOCK_BIT_GET(x) (((uint32_t)(x) & PWMV2_UNLOCK_UNLOCK_BIT_MASK) >> PWMV2_UNLOCK_UNLOCK_BIT_SHIFT)
109 
110 /* Bitfield definition for register array: SHADOW_VAL */
111 /*
112  * VALUE (RW)
113  *
114  * shadow registers, if used as reload or compare point, shall be 24bit clock cycles plus 1bit half cycle and 7bit high-resolution delay
115  */
116 #define PWMV2_SHADOW_VAL_VALUE_MASK (0xFFFFFFFFUL)
117 #define PWMV2_SHADOW_VAL_VALUE_SHIFT (0U)
118 #define PWMV2_SHADOW_VAL_VALUE_SET(x) (((uint32_t)(x) << PWMV2_SHADOW_VAL_VALUE_SHIFT) & PWMV2_SHADOW_VAL_VALUE_MASK)
119 #define PWMV2_SHADOW_VAL_VALUE_GET(x) (((uint32_t)(x) & PWMV2_SHADOW_VAL_VALUE_MASK) >> PWMV2_SHADOW_VAL_VALUE_SHIFT)
120 
121 /* Bitfield definition for register: FORCE_MODE */
122 /*
123  * POLARITY (RW)
124  *
125  * one bit for one pwm channel, it's used as shadow register when pwm_cfg0.polarity_opt0 is set.
126  * output polarity, set to 1 will invert the output
127  */
128 #define PWMV2_FORCE_MODE_POLARITY_MASK (0xFF0000UL)
129 #define PWMV2_FORCE_MODE_POLARITY_SHIFT (16U)
130 #define PWMV2_FORCE_MODE_POLARITY_SET(x) (((uint32_t)(x) << PWMV2_FORCE_MODE_POLARITY_SHIFT) & PWMV2_FORCE_MODE_POLARITY_MASK)
131 #define PWMV2_FORCE_MODE_POLARITY_GET(x) (((uint32_t)(x) & PWMV2_FORCE_MODE_POLARITY_MASK) >> PWMV2_FORCE_MODE_POLARITY_SHIFT)
132 
133 /*
134  * FORCE_MODE (RW)
135  *
136  * 2bit for each PWM channel(0~7);
137  * 00: force output 0
138  * 01: force output 1
139  * 10: output highz(pad_oe_*=0)
140  * 11: no force
141  * this field may be changed by software as shadow register , the update time should be defined by chan_cfg.load, only for PWM channels.
142  */
143 #define PWMV2_FORCE_MODE_FORCE_MODE_MASK (0xFFFFU)
144 #define PWMV2_FORCE_MODE_FORCE_MODE_SHIFT (0U)
145 #define PWMV2_FORCE_MODE_FORCE_MODE_SET(x) (((uint32_t)(x) << PWMV2_FORCE_MODE_FORCE_MODE_SHIFT) & PWMV2_FORCE_MODE_FORCE_MODE_MASK)
146 #define PWMV2_FORCE_MODE_FORCE_MODE_GET(x) (((uint32_t)(x) & PWMV2_FORCE_MODE_FORCE_MODE_MASK) >> PWMV2_FORCE_MODE_FORCE_MODE_SHIFT)
147 
148 /* Bitfield definition for register: WORK_CTRL1 */
149 /*
150  * SHADOW_LOCK (RW)
151  *
152  * one to lock, sofware can't write any shadow registers
153  * Software have to write 0x…. to work_ctrl0 to clear this bit.
154  */
155 #define PWMV2_WORK_CTRL1_SHADOW_LOCK_MASK (0x80000000UL)
156 #define PWMV2_WORK_CTRL1_SHADOW_LOCK_SHIFT (31U)
157 #define PWMV2_WORK_CTRL1_SHADOW_LOCK_SET(x) (((uint32_t)(x) << PWMV2_WORK_CTRL1_SHADOW_LOCK_SHIFT) & PWMV2_WORK_CTRL1_SHADOW_LOCK_MASK)
158 #define PWMV2_WORK_CTRL1_SHADOW_LOCK_GET(x) (((uint32_t)(x) & PWMV2_WORK_CTRL1_SHADOW_LOCK_MASK) >> PWMV2_WORK_CTRL1_SHADOW_LOCK_SHIFT)
159 
160 /* Bitfield definition for register of struct array PWM: CFG0 */
161 /*
162  * TRIG_SEL4 (RW)
163  *
164  * for N=0/2/4/6, clear to select 2 compare point(N*2~N*2+1);
165  * set to select 4 compare point(N*2~N*2+3);
166  * or use 2 compare point(N*2+2~N*2+3);
167  * for N=1/3/5/7, this bit is no means, it can work on pair mode, or use 2 compare point (N*2+2~N*2+3);
168  * assume select ab or abcd, abcd can between 0 and 2T.
169  * output will be 1 when counter value between a and b;
170  * if b<=a then output all 0; if b>=(T+a), then output all 1;
171  */
172 #define PWMV2_PWM_CFG0_TRIG_SEL4_MASK (0x1000000UL)
173 #define PWMV2_PWM_CFG0_TRIG_SEL4_SHIFT (24U)
174 #define PWMV2_PWM_CFG0_TRIG_SEL4_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG0_TRIG_SEL4_SHIFT) & PWMV2_PWM_CFG0_TRIG_SEL4_MASK)
175 #define PWMV2_PWM_CFG0_TRIG_SEL4_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG0_TRIG_SEL4_MASK) >> PWMV2_PWM_CFG0_TRIG_SEL4_SHIFT)
176 
177 /*
178  * FAULT_SEL_ASYNC (RW)
179  *
180  * select from 16bit async fault from pad
181  */
182 #define PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_MASK (0xF00U)
183 #define PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_SHIFT (8U)
184 #define PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_SHIFT) & PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_MASK)
185 #define PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_MASK) >> PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_SHIFT)
186 
187 /*
188  * FAULT_POL_ASYNC (RW)
189  *
190  * fault polarity for input fault from pad, 1-active low; 0-active high;
191  */
192 #define PWMV2_PWM_CFG0_FAULT_POL_ASYNC_MASK (0x40U)
193 #define PWMV2_PWM_CFG0_FAULT_POL_ASYNC_SHIFT (6U)
194 #define PWMV2_PWM_CFG0_FAULT_POL_ASYNC_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG0_FAULT_POL_ASYNC_SHIFT) & PWMV2_PWM_CFG0_FAULT_POL_ASYNC_MASK)
195 #define PWMV2_PWM_CFG0_FAULT_POL_ASYNC_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG0_FAULT_POL_ASYNC_MASK) >> PWMV2_PWM_CFG0_FAULT_POL_ASYNC_SHIFT)
196 
197 /*
198  * FAULT_EN_ASYNC (RW)
199  *
200  * set to enable the input async faults from pad directly
201  */
202 #define PWMV2_PWM_CFG0_FAULT_EN_ASYNC_MASK (0x20U)
203 #define PWMV2_PWM_CFG0_FAULT_EN_ASYNC_SHIFT (5U)
204 #define PWMV2_PWM_CFG0_FAULT_EN_ASYNC_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG0_FAULT_EN_ASYNC_SHIFT) & PWMV2_PWM_CFG0_FAULT_EN_ASYNC_MASK)
205 #define PWMV2_PWM_CFG0_FAULT_EN_ASYNC_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG0_FAULT_EN_ASYNC_MASK) >> PWMV2_PWM_CFG0_FAULT_EN_ASYNC_SHIFT)
206 
207 /*
208  * FAULT_EN_SYNC (RW)
209  *
210  * set to enable the input faults from trig_mux(trigger_in[0] for channel0/1, 1 for 23, 2 for 45, 3 for 67)
211  */
212 #define PWMV2_PWM_CFG0_FAULT_EN_SYNC_MASK (0x10U)
213 #define PWMV2_PWM_CFG0_FAULT_EN_SYNC_SHIFT (4U)
214 #define PWMV2_PWM_CFG0_FAULT_EN_SYNC_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG0_FAULT_EN_SYNC_SHIFT) & PWMV2_PWM_CFG0_FAULT_EN_SYNC_MASK)
215 #define PWMV2_PWM_CFG0_FAULT_EN_SYNC_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG0_FAULT_EN_SYNC_MASK) >> PWMV2_PWM_CFG0_FAULT_EN_SYNC_SHIFT)
216 
217 /*
218  * POL_UPDATE_SEL (RW)
219  *
220  * used when polarity_opt0 is set, define when to update polarity working register.
221  * 0: software set work_ctrl1.shadow_lock bit
222  * 1: update at reload point;
223  */
224 #define PWMV2_PWM_CFG0_POL_UPDATE_SEL_MASK (0x4U)
225 #define PWMV2_PWM_CFG0_POL_UPDATE_SEL_SHIFT (2U)
226 #define PWMV2_PWM_CFG0_POL_UPDATE_SEL_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG0_POL_UPDATE_SEL_SHIFT) & PWMV2_PWM_CFG0_POL_UPDATE_SEL_MASK)
227 #define PWMV2_PWM_CFG0_POL_UPDATE_SEL_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG0_POL_UPDATE_SEL_MASK) >> PWMV2_PWM_CFG0_POL_UPDATE_SEL_SHIFT)
228 
229 /*
230  * OUT_POLARITY (RW)
231  *
232  * output polarity, set to 1 will invert the output.
233  * when polarity_opt0 is set, this bit is controlled by shadow register, can't be writable; read as working register
234  * use compare channel settings(in cmp_cfg) as shadow register update
235  */
236 #define PWMV2_PWM_CFG0_OUT_POLARITY_MASK (0x2U)
237 #define PWMV2_PWM_CFG0_OUT_POLARITY_SHIFT (1U)
238 #define PWMV2_PWM_CFG0_OUT_POLARITY_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG0_OUT_POLARITY_SHIFT) & PWMV2_PWM_CFG0_OUT_POLARITY_MASK)
239 #define PWMV2_PWM_CFG0_OUT_POLARITY_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG0_OUT_POLARITY_MASK) >> PWMV2_PWM_CFG0_OUT_POLARITY_SHIFT)
240 
241 /*
242  * POLARITY_OPT0 (RW)
243  *
244  * set to use shadow polarity
245  */
246 #define PWMV2_PWM_CFG0_POLARITY_OPT0_MASK (0x1U)
247 #define PWMV2_PWM_CFG0_POLARITY_OPT0_SHIFT (0U)
248 #define PWMV2_PWM_CFG0_POLARITY_OPT0_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG0_POLARITY_OPT0_SHIFT) & PWMV2_PWM_CFG0_POLARITY_OPT0_MASK)
249 #define PWMV2_PWM_CFG0_POLARITY_OPT0_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG0_POLARITY_OPT0_MASK) >> PWMV2_PWM_CFG0_POLARITY_OPT0_SHIFT)
250 
251 /* Bitfield definition for register of struct array PWM: CFG1 */
252 /*
253  * HIGHZ_EN_N (RW)
254  *
255  * 0 to highz pwm outputs(pad_oe*=0), software need set this bit to 1 to enable pwm output
256  */
257 #define PWMV2_PWM_CFG1_HIGHZ_EN_N_MASK (0x10000000UL)
258 #define PWMV2_PWM_CFG1_HIGHZ_EN_N_SHIFT (28U)
259 #define PWMV2_PWM_CFG1_HIGHZ_EN_N_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG1_HIGHZ_EN_N_SHIFT) & PWMV2_PWM_CFG1_HIGHZ_EN_N_MASK)
260 #define PWMV2_PWM_CFG1_HIGHZ_EN_N_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG1_HIGHZ_EN_N_MASK) >> PWMV2_PWM_CFG1_HIGHZ_EN_N_SHIFT)
261 
262 /*
263  * FORCE_UPDATE_TIME (RW)
264  *
265  * define when to use the shadow register value for working register(force_mode)
266  * 00: software set work_ctrl1.shadow_lock bit
267  * 01: use the related counter rld_cmp_sel0 and rld_cmp_sel1, to select one compare point
268  * 10: related counter reload time(selected by pwm_cnt)
269  * 11: use force_trig_sel to select one of the input trigger
270  * NOTE: 00/01 are not recommended since the update time is not controllable, may cause error in complex application.
271  * 00 is used for initialization or debug, not suggest for real time update
272  */
273 #define PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_MASK (0xC000000UL)
274 #define PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_SHIFT (26U)
275 #define PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_SHIFT) & PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_MASK)
276 #define PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_MASK) >> PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_SHIFT)
277 
278 /*
279  * FAULT_MODE (RW)
280  *
281  * 00: force output 0
282  * 01: force output 1
283  * 1x: output highz(pad_oe_*=0)
284  */
285 #define PWMV2_PWM_CFG1_FAULT_MODE_MASK (0x3000000UL)
286 #define PWMV2_PWM_CFG1_FAULT_MODE_SHIFT (24U)
287 #define PWMV2_PWM_CFG1_FAULT_MODE_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG1_FAULT_MODE_SHIFT) & PWMV2_PWM_CFG1_FAULT_MODE_MASK)
288 #define PWMV2_PWM_CFG1_FAULT_MODE_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG1_FAULT_MODE_MASK) >> PWMV2_PWM_CFG1_FAULT_MODE_SHIFT)
289 
290 /*
291  * FAULT_REC_TIME (RW)
292  *
293  * 00: immediately
294  * 01: after main counter reload time
295  * 10: use fault_rec_sel to select one of the input trigger
296  * 11: software write fault_clear in glb_ctrl2, no effort if pwm_fault is still assert
297  */
298 #define PWMV2_PWM_CFG1_FAULT_REC_TIME_MASK (0xC00000UL)
299 #define PWMV2_PWM_CFG1_FAULT_REC_TIME_SHIFT (22U)
300 #define PWMV2_PWM_CFG1_FAULT_REC_TIME_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG1_FAULT_REC_TIME_SHIFT) & PWMV2_PWM_CFG1_FAULT_REC_TIME_MASK)
301 #define PWMV2_PWM_CFG1_FAULT_REC_TIME_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG1_FAULT_REC_TIME_MASK) >> PWMV2_PWM_CFG1_FAULT_REC_TIME_SHIFT)
302 
303 /*
304  * SW_FORCE_EN (RW)
305  *
306  * 0 for hardware force, from trig_mux selected by pwm_force_sel
307  * 1 for software force, from glb_ctrl.sw_force
308  */
309 #define PWMV2_PWM_CFG1_SW_FORCE_EN_MASK (0x200000UL)
310 #define PWMV2_PWM_CFG1_SW_FORCE_EN_SHIFT (21U)
311 #define PWMV2_PWM_CFG1_SW_FORCE_EN_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG1_SW_FORCE_EN_SHIFT) & PWMV2_PWM_CFG1_SW_FORCE_EN_MASK)
312 #define PWMV2_PWM_CFG1_SW_FORCE_EN_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG1_SW_FORCE_EN_MASK) >> PWMV2_PWM_CFG1_SW_FORCE_EN_SHIFT)
313 
314 /*
315  * PAIR_MODE (RW)
316  *
317  * if set to 1, PWM work at pair mode,
318  * pwm_cfg for channel 2m is used for channel 2m+1(m=0,1,2,3),
319  * except the dead area, which is separate for each channel even in pair mode
320  * software need set this bit for both channel of one pair, otherwise result unknown.
321  */
322 #define PWMV2_PWM_CFG1_PAIR_MODE_MASK (0x100000UL)
323 #define PWMV2_PWM_CFG1_PAIR_MODE_SHIFT (20U)
324 #define PWMV2_PWM_CFG1_PAIR_MODE_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG1_PAIR_MODE_SHIFT) & PWMV2_PWM_CFG1_PAIR_MODE_MASK)
325 #define PWMV2_PWM_CFG1_PAIR_MODE_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG1_PAIR_MODE_MASK) >> PWMV2_PWM_CFG1_PAIR_MODE_SHIFT)
326 
327 /*
328  * PWM_LOGIC (RW)
329  *
330  * valid only for pwm0/2/4/6 when trig_sel4 is set
331  * 00: ab OR cd;
332  * 01: ab AND cd;
333  * 10: ab XOR cd;
334  * 11: cd
335  */
336 #define PWMV2_PWM_CFG1_PWM_LOGIC_MASK (0xC0000UL)
337 #define PWMV2_PWM_CFG1_PWM_LOGIC_SHIFT (18U)
338 #define PWMV2_PWM_CFG1_PWM_LOGIC_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG1_PWM_LOGIC_SHIFT) & PWMV2_PWM_CFG1_PWM_LOGIC_MASK)
339 #define PWMV2_PWM_CFG1_PWM_LOGIC_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG1_PWM_LOGIC_MASK) >> PWMV2_PWM_CFG1_PWM_LOGIC_SHIFT)
340 
341 /*
342  * FORCE_TIME (RW)
343  *
344  * 00: force immediately
345  * 01: force at main counter reload time
346  * 10: force at trig signal selected by force_act_sel
347  * 11: no force
348  * the force assert/deassert will happen at the force_time;
349  * qeo force and value also latched at this time
350  */
351 #define PWMV2_PWM_CFG1_FORCE_TIME_MASK (0x30000UL)
352 #define PWMV2_PWM_CFG1_FORCE_TIME_SHIFT (16U)
353 #define PWMV2_PWM_CFG1_FORCE_TIME_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG1_FORCE_TIME_SHIFT) & PWMV2_PWM_CFG1_FORCE_TIME_MASK)
354 #define PWMV2_PWM_CFG1_FORCE_TIME_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG1_FORCE_TIME_MASK) >> PWMV2_PWM_CFG1_FORCE_TIME_SHIFT)
355 
356 /*
357  * FORCE_TRIG_SEL (RW)
358  *
359  * select one trigger from 8, should set to pulse in trig_mux, will load shadow register(force)mode) to force_mode_work at this time
360  */
361 #define PWMV2_PWM_CFG1_FORCE_TRIG_SEL_MASK (0x7000U)
362 #define PWMV2_PWM_CFG1_FORCE_TRIG_SEL_SHIFT (12U)
363 #define PWMV2_PWM_CFG1_FORCE_TRIG_SEL_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG1_FORCE_TRIG_SEL_SHIFT) & PWMV2_PWM_CFG1_FORCE_TRIG_SEL_MASK)
364 #define PWMV2_PWM_CFG1_FORCE_TRIG_SEL_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG1_FORCE_TRIG_SEL_MASK) >> PWMV2_PWM_CFG1_FORCE_TRIG_SEL_SHIFT)
365 
366 /*
367  * FORCE_ACT_SEL (RW)
368  *
369  * select one trigger from 8, should set to pulse in trig_mux, will load hw/sw force at this time
370  */
371 #define PWMV2_PWM_CFG1_FORCE_ACT_SEL_MASK (0x700U)
372 #define PWMV2_PWM_CFG1_FORCE_ACT_SEL_SHIFT (8U)
373 #define PWMV2_PWM_CFG1_FORCE_ACT_SEL_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG1_FORCE_ACT_SEL_SHIFT) & PWMV2_PWM_CFG1_FORCE_ACT_SEL_MASK)
374 #define PWMV2_PWM_CFG1_FORCE_ACT_SEL_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG1_FORCE_ACT_SEL_MASK) >> PWMV2_PWM_CFG1_FORCE_ACT_SEL_SHIFT)
375 
376 /*
377  * PWM_FORCE_SEL (RW)
378  *
379  * select one trigger from 8 as force signal, should be level signal, 1 for force active, 0 for no force
380  */
381 #define PWMV2_PWM_CFG1_PWM_FORCE_SEL_MASK (0x70U)
382 #define PWMV2_PWM_CFG1_PWM_FORCE_SEL_SHIFT (4U)
383 #define PWMV2_PWM_CFG1_PWM_FORCE_SEL_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG1_PWM_FORCE_SEL_SHIFT) & PWMV2_PWM_CFG1_PWM_FORCE_SEL_MASK)
384 #define PWMV2_PWM_CFG1_PWM_FORCE_SEL_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG1_PWM_FORCE_SEL_MASK) >> PWMV2_PWM_CFG1_PWM_FORCE_SEL_SHIFT)
385 
386 /*
387  * FAULT_REC_SEL (RW)
388  *
389  * select one trigger from 8, should set to pulse in trig_mux, used for fault recovery if fault_rec_time is set to 2'b10
390  */
391 #define PWMV2_PWM_CFG1_FAULT_REC_SEL_MASK (0x7U)
392 #define PWMV2_PWM_CFG1_FAULT_REC_SEL_SHIFT (0U)
393 #define PWMV2_PWM_CFG1_FAULT_REC_SEL_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG1_FAULT_REC_SEL_SHIFT) & PWMV2_PWM_CFG1_FAULT_REC_SEL_MASK)
394 #define PWMV2_PWM_CFG1_FAULT_REC_SEL_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG1_FAULT_REC_SEL_MASK) >> PWMV2_PWM_CFG1_FAULT_REC_SEL_SHIFT)
395 
396 /* Bitfield definition for register of struct array PWM: DEAD_AREA */
397 /*
398  * DEAD_AREA (RW)
399  *
400  * 16bit cycle delay plus 8bit hr_delay
401  * min value is 2 cycles, less than 0x200 will be treated as no dead area;
402  * NOTE: dead insertion must be configured with pair, that is, for pwm 01/23/45/67.
403  * otherwise the result maybe UNKNOWN!!!
404  */
405 #define PWMV2_PWM_DEAD_AREA_DEAD_AREA_MASK (0xFFFFFFUL)
406 #define PWMV2_PWM_DEAD_AREA_DEAD_AREA_SHIFT (0U)
407 #define PWMV2_PWM_DEAD_AREA_DEAD_AREA_SET(x) (((uint32_t)(x) << PWMV2_PWM_DEAD_AREA_DEAD_AREA_SHIFT) & PWMV2_PWM_DEAD_AREA_DEAD_AREA_MASK)
408 #define PWMV2_PWM_DEAD_AREA_DEAD_AREA_GET(x) (((uint32_t)(x) & PWMV2_PWM_DEAD_AREA_DEAD_AREA_MASK) >> PWMV2_PWM_DEAD_AREA_DEAD_AREA_SHIFT)
409 
410 /* Bitfield definition for register of struct array PWM: CFG3 */
411 /*
412  * ASYNC_FAULT_SEL (RW)
413  *
414  * one bit select to enable one async fault from pad, all enabled fault will be OR together with the old async fault logic.
415  * (in old version, user can select one async fault by pwm_cfg0.fault_sel_async, and enabled by pwm_cfg0.fault_en_async)
416  * each async fault has dedicaate polarity definition in glb_ctrl3.async_fault_pol
417  */
418 #define PWMV2_PWM_CFG3_ASYNC_FAULT_SEL_MASK (0xFFFFU)
419 #define PWMV2_PWM_CFG3_ASYNC_FAULT_SEL_SHIFT (0U)
420 #define PWMV2_PWM_CFG3_ASYNC_FAULT_SEL_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG3_ASYNC_FAULT_SEL_SHIFT) & PWMV2_PWM_CFG3_ASYNC_FAULT_SEL_MASK)
421 #define PWMV2_PWM_CFG3_ASYNC_FAULT_SEL_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG3_ASYNC_FAULT_SEL_MASK) >> PWMV2_PWM_CFG3_ASYNC_FAULT_SEL_SHIFT)
422 
423 /* Bitfield definition for register array: TRIGGER_CFG */
424 /*
425  * TRIGGER_OUT_SEL (RW)
426  *
427  * select one from 24 compare result as trigger out, set at compare point, clear at reload point.
428  */
429 #define PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_MASK (0x1FU)
430 #define PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_SHIFT (0U)
431 #define PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_SET(x) (((uint32_t)(x) << PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_SHIFT) & PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_MASK)
432 #define PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_GET(x) (((uint32_t)(x) & PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_MASK) >> PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_SHIFT)
433 
434 /* Bitfield definition for register: GLB_CTRL */
435 /*
436  * SW_FORCE (RW)
437  *
438  * software write 1 to start software force, if the pwm_cfg<n>.sw_force_en is set, force will take effort
439  */
440 #define PWMV2_GLB_CTRL_SW_FORCE_MASK (0xFF0000UL)
441 #define PWMV2_GLB_CTRL_SW_FORCE_SHIFT (16U)
442 #define PWMV2_GLB_CTRL_SW_FORCE_SET(x) (((uint32_t)(x) << PWMV2_GLB_CTRL_SW_FORCE_SHIFT) & PWMV2_GLB_CTRL_SW_FORCE_MASK)
443 #define PWMV2_GLB_CTRL_SW_FORCE_GET(x) (((uint32_t)(x) & PWMV2_GLB_CTRL_SW_FORCE_MASK) >> PWMV2_GLB_CTRL_SW_FORCE_SHIFT)
444 
445 /*
446  * OUTPUT_DELAY (RW)
447  *
448  * add delay after dead_area insertiong logic, for hr_pwm
449  */
450 #define PWMV2_GLB_CTRL_OUTPUT_DELAY_MASK (0x300U)
451 #define PWMV2_GLB_CTRL_OUTPUT_DELAY_SHIFT (8U)
452 #define PWMV2_GLB_CTRL_OUTPUT_DELAY_SET(x) (((uint32_t)(x) << PWMV2_GLB_CTRL_OUTPUT_DELAY_SHIFT) & PWMV2_GLB_CTRL_OUTPUT_DELAY_MASK)
453 #define PWMV2_GLB_CTRL_OUTPUT_DELAY_GET(x) (((uint32_t)(x) & PWMV2_GLB_CTRL_OUTPUT_DELAY_MASK) >> PWMV2_GLB_CTRL_OUTPUT_DELAY_SHIFT)
454 
455 /*
456  * HR_PWM_EN (RW)
457  *
458  * set to enable hr pwm, clear to bypass delay chain.
459  */
460 #define PWMV2_GLB_CTRL_HR_PWM_EN_MASK (0x10U)
461 #define PWMV2_GLB_CTRL_HR_PWM_EN_SHIFT (4U)
462 #define PWMV2_GLB_CTRL_HR_PWM_EN_SET(x) (((uint32_t)(x) << PWMV2_GLB_CTRL_HR_PWM_EN_SHIFT) & PWMV2_GLB_CTRL_HR_PWM_EN_MASK)
463 #define PWMV2_GLB_CTRL_HR_PWM_EN_GET(x) (((uint32_t)(x) & PWMV2_GLB_CTRL_HR_PWM_EN_MASK) >> PWMV2_GLB_CTRL_HR_PWM_EN_SHIFT)
464 
465 /*
466  * FRAC_DISABLE (RW)
467  *
468  * set to disable bit[7:0] in DAC value when Calculation Unit use it.
469  */
470 #define PWMV2_GLB_CTRL_FRAC_DISABLE_MASK (0x8U)
471 #define PWMV2_GLB_CTRL_FRAC_DISABLE_SHIFT (3U)
472 #define PWMV2_GLB_CTRL_FRAC_DISABLE_SET(x) (((uint32_t)(x) << PWMV2_GLB_CTRL_FRAC_DISABLE_SHIFT) & PWMV2_GLB_CTRL_FRAC_DISABLE_MASK)
473 #define PWMV2_GLB_CTRL_FRAC_DISABLE_GET(x) (((uint32_t)(x) & PWMV2_GLB_CTRL_FRAC_DISABLE_MASK) >> PWMV2_GLB_CTRL_FRAC_DISABLE_SHIFT)
474 
475 /* Bitfield definition for register: GLB_CTRL2 */
476 /*
477  * DAC_SW_MODE (RW)
478  *
479  * set for software DAC mode, software can write dac_value*_sv directly, and dac_valid from moto system is ignored
480  */
481 #define PWMV2_GLB_CTRL2_DAC_SW_MODE_MASK (0xF000000UL)
482 #define PWMV2_GLB_CTRL2_DAC_SW_MODE_SHIFT (24U)
483 #define PWMV2_GLB_CTRL2_DAC_SW_MODE_SET(x) (((uint32_t)(x) << PWMV2_GLB_CTRL2_DAC_SW_MODE_SHIFT) & PWMV2_GLB_CTRL2_DAC_SW_MODE_MASK)
484 #define PWMV2_GLB_CTRL2_DAC_SW_MODE_GET(x) (((uint32_t)(x) & PWMV2_GLB_CTRL2_DAC_SW_MODE_MASK) >> PWMV2_GLB_CTRL2_DAC_SW_MODE_SHIFT)
485 
486 /*
487  * DEBUG_OPT (RW)
488  *
489  * set to disable debug fault immediately when exit debug mode
490  */
491 #define PWMV2_GLB_CTRL2_DEBUG_OPT_MASK (0x400000UL)
492 #define PWMV2_GLB_CTRL2_DEBUG_OPT_SHIFT (22U)
493 #define PWMV2_GLB_CTRL2_DEBUG_OPT_SET(x) (((uint32_t)(x) << PWMV2_GLB_CTRL2_DEBUG_OPT_SHIFT) & PWMV2_GLB_CTRL2_DEBUG_OPT_MASK)
494 #define PWMV2_GLB_CTRL2_DEBUG_OPT_GET(x) (((uint32_t)(x) & PWMV2_GLB_CTRL2_DEBUG_OPT_MASK) >> PWMV2_GLB_CTRL2_DEBUG_OPT_SHIFT)
495 
496 /*
497  * DEBUG_IN_EN (RW)
498  *
499  * set to enable debug_in signal as fault signal, generally disable pwm output
500  */
501 #define PWMV2_GLB_CTRL2_DEBUG_IN_EN_MASK (0x200000UL)
502 #define PWMV2_GLB_CTRL2_DEBUG_IN_EN_SHIFT (21U)
503 #define PWMV2_GLB_CTRL2_DEBUG_IN_EN_SET(x) (((uint32_t)(x) << PWMV2_GLB_CTRL2_DEBUG_IN_EN_SHIFT) & PWMV2_GLB_CTRL2_DEBUG_IN_EN_MASK)
504 #define PWMV2_GLB_CTRL2_DEBUG_IN_EN_GET(x) (((uint32_t)(x) & PWMV2_GLB_CTRL2_DEBUG_IN_EN_MASK) >> PWMV2_GLB_CTRL2_DEBUG_IN_EN_SHIFT)
505 
506 /*
507  * FAULT_CLEAR (RW)
508  *
509  * software write 1 to clear fault event if pwm_cfg.fault_rec_time is 2'b11.
510  * software need to clear it after the fault signal is de-assert and before next fault
511  * one bit for one pwm channel
512  */
513 #define PWMV2_GLB_CTRL2_FAULT_CLEAR_MASK (0xFF00U)
514 #define PWMV2_GLB_CTRL2_FAULT_CLEAR_SHIFT (8U)
515 #define PWMV2_GLB_CTRL2_FAULT_CLEAR_SET(x) (((uint32_t)(x) << PWMV2_GLB_CTRL2_FAULT_CLEAR_SHIFT) & PWMV2_GLB_CTRL2_FAULT_CLEAR_MASK)
516 #define PWMV2_GLB_CTRL2_FAULT_CLEAR_GET(x) (((uint32_t)(x) & PWMV2_GLB_CTRL2_FAULT_CLEAR_MASK) >> PWMV2_GLB_CTRL2_FAULT_CLEAR_SHIFT)
517 
518 /*
519  * SHADOW_LOCK_EN (RW)
520  *
521  * enable shadow_lock feature, if cleared, shadow_lock will be always 0
522  */
523 #define PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_MASK (0x1U)
524 #define PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_SHIFT (0U)
525 #define PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_SET(x) (((uint32_t)(x) << PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_SHIFT) & PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_MASK)
526 #define PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_GET(x) (((uint32_t)(x) & PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_MASK) >> PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_SHIFT)
527 
528 /* Bitfield definition for register: GLB_CTRL3 */
529 /*
530  * ASYNC_FAULT_POL (RW)
531  *
532  * async fault polarity, default 0 for active high; set to 1 for active low
533  */
534 #define PWMV2_GLB_CTRL3_ASYNC_FAULT_POL_MASK (0xFFFFU)
535 #define PWMV2_GLB_CTRL3_ASYNC_FAULT_POL_SHIFT (0U)
536 #define PWMV2_GLB_CTRL3_ASYNC_FAULT_POL_SET(x) (((uint32_t)(x) << PWMV2_GLB_CTRL3_ASYNC_FAULT_POL_SHIFT) & PWMV2_GLB_CTRL3_ASYNC_FAULT_POL_MASK)
537 #define PWMV2_GLB_CTRL3_ASYNC_FAULT_POL_GET(x) (((uint32_t)(x) & PWMV2_GLB_CTRL3_ASYNC_FAULT_POL_MASK) >> PWMV2_GLB_CTRL3_ASYNC_FAULT_POL_SHIFT)
538 
539 /* Bitfield definition for register array: CNT_RELOAD_WORK */
540 /*
541  * VALUE (RO)
542  *
543  * counter0 reload working register
544  */
545 #define PWMV2_CNT_RELOAD_WORK_VALUE_MASK (0xFFFFFFFFUL)
546 #define PWMV2_CNT_RELOAD_WORK_VALUE_SHIFT (0U)
547 #define PWMV2_CNT_RELOAD_WORK_VALUE_GET(x) (((uint32_t)(x) & PWMV2_CNT_RELOAD_WORK_VALUE_MASK) >> PWMV2_CNT_RELOAD_WORK_VALUE_SHIFT)
548 
549 /* Bitfield definition for register array: CMP_VAL_WORK */
550 /*
551  * VALUE (RO)
552  *
553  * compare point working register
554  */
555 #define PWMV2_CMP_VAL_WORK_VALUE_MASK (0xFFFFFFFFUL)
556 #define PWMV2_CMP_VAL_WORK_VALUE_SHIFT (0U)
557 #define PWMV2_CMP_VAL_WORK_VALUE_GET(x) (((uint32_t)(x) & PWMV2_CMP_VAL_WORK_VALUE_MASK) >> PWMV2_CMP_VAL_WORK_VALUE_SHIFT)
558 
559 /* Bitfield definition for register: FORCE_WORK */
560 /*
561  * OUT_POLARITY (RO)
562  *
563  * force working register
564  */
565 #define PWMV2_FORCE_WORK_OUT_POLARITY_MASK (0xFF0000UL)
566 #define PWMV2_FORCE_WORK_OUT_POLARITY_SHIFT (16U)
567 #define PWMV2_FORCE_WORK_OUT_POLARITY_GET(x) (((uint32_t)(x) & PWMV2_FORCE_WORK_OUT_POLARITY_MASK) >> PWMV2_FORCE_WORK_OUT_POLARITY_SHIFT)
568 
569 /*
570  * FORCE_MODE (RO)
571  *
572  * force_mode work register
573  */
574 #define PWMV2_FORCE_WORK_FORCE_MODE_MASK (0xFFFFU)
575 #define PWMV2_FORCE_WORK_FORCE_MODE_SHIFT (0U)
576 #define PWMV2_FORCE_WORK_FORCE_MODE_GET(x) (((uint32_t)(x) & PWMV2_FORCE_WORK_FORCE_MODE_MASK) >> PWMV2_FORCE_WORK_FORCE_MODE_SHIFT)
577 
578 /* Bitfield definition for register array: CNT_VAL */
579 /*
580  * VALUE (RO)
581  *
582  * main counter value
583  */
584 #define PWMV2_CNT_VAL_VALUE_MASK (0xFFFFFFFFUL)
585 #define PWMV2_CNT_VAL_VALUE_SHIFT (0U)
586 #define PWMV2_CNT_VAL_VALUE_GET(x) (((uint32_t)(x) & PWMV2_CNT_VAL_VALUE_MASK) >> PWMV2_CNT_VAL_VALUE_SHIFT)
587 
588 /* Bitfield definition for register array: DAC_VALUE_SV */
589 /*
590  * VALUE (RW)
591  *
592  * save dac0_value when dac0_valid if dac_sw_mode is 0;
593  * software write dac_value directly if dac_sw_mode is 1
594  */
595 #define PWMV2_DAC_VALUE_SV_VALUE_MASK (0xFFFFFFFFUL)
596 #define PWMV2_DAC_VALUE_SV_VALUE_SHIFT (0U)
597 #define PWMV2_DAC_VALUE_SV_VALUE_SET(x) (((uint32_t)(x) << PWMV2_DAC_VALUE_SV_VALUE_SHIFT) & PWMV2_DAC_VALUE_SV_VALUE_MASK)
598 #define PWMV2_DAC_VALUE_SV_VALUE_GET(x) (((uint32_t)(x) & PWMV2_DAC_VALUE_SV_VALUE_MASK) >> PWMV2_DAC_VALUE_SV_VALUE_SHIFT)
599 
600 /* Bitfield definition for register array: CAPTURE_POS */
601 /*
602  * CAPTURE_POS (RO)
603  *
604  * related counter value captured at input negedge
605  */
606 #define PWMV2_CAPTURE_POS_CAPTURE_POS_MASK (0xFFFFFF00UL)
607 #define PWMV2_CAPTURE_POS_CAPTURE_POS_SHIFT (8U)
608 #define PWMV2_CAPTURE_POS_CAPTURE_POS_GET(x) (((uint32_t)(x) & PWMV2_CAPTURE_POS_CAPTURE_POS_MASK) >> PWMV2_CAPTURE_POS_CAPTURE_POS_SHIFT)
609 
610 /*
611  * CAPTURE_SELGPIO (RW)
612  *
613  * 0: result from CAP[ 7:0], from trgm
614  * 1: result from CAP[15:8], from gpio
615  */
616 #define PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_MASK (0x10U)
617 #define PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_SHIFT (4U)
618 #define PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_SET(x) (((uint32_t)(x) << PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_SHIFT) & PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_MASK)
619 #define PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_GET(x) (((uint32_t)(x) & PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_MASK) >> PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_SHIFT)
620 
621 /*
622  * CNT_INDEX (RW)
623  *
624  * related counter
625  */
626 #define PWMV2_CAPTURE_POS_CNT_INDEX_MASK (0x3U)
627 #define PWMV2_CAPTURE_POS_CNT_INDEX_SHIFT (0U)
628 #define PWMV2_CAPTURE_POS_CNT_INDEX_SET(x) (((uint32_t)(x) << PWMV2_CAPTURE_POS_CNT_INDEX_SHIFT) & PWMV2_CAPTURE_POS_CNT_INDEX_MASK)
629 #define PWMV2_CAPTURE_POS_CNT_INDEX_GET(x) (((uint32_t)(x) & PWMV2_CAPTURE_POS_CNT_INDEX_MASK) >> PWMV2_CAPTURE_POS_CNT_INDEX_SHIFT)
630 
631 /* Bitfield definition for register array: CAPTURE_NEG */
632 /*
633  * CAPTURE_NEG (RO)
634  *
635  * counter value captured at input negedge
636  */
637 #define PWMV2_CAPTURE_NEG_CAPTURE_NEG_MASK (0xFFFFFF00UL)
638 #define PWMV2_CAPTURE_NEG_CAPTURE_NEG_SHIFT (8U)
639 #define PWMV2_CAPTURE_NEG_CAPTURE_NEG_GET(x) (((uint32_t)(x) & PWMV2_CAPTURE_NEG_CAPTURE_NEG_MASK) >> PWMV2_CAPTURE_NEG_CAPTURE_NEG_SHIFT)
640 
641 /* Bitfield definition for register: IRQ_STS */
642 /*
643  * IRQ_CAL_OVERFLOW (W1C)
644  *
645  * end of output burst
646  */
647 #define PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_MASK (0x80000000UL)
648 #define PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_SHIFT (31U)
649 #define PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_SET(x) (((uint32_t)(x) << PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_SHIFT) & PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_MASK)
650 #define PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_GET(x) (((uint32_t)(x) & PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_MASK) >> PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_SHIFT)
651 
652 /*
653  * IRQ_BURSTEND (RO)
654  *
655  * end of output burst
656  */
657 #define PWMV2_IRQ_STS_IRQ_BURSTEND_MASK (0x20U)
658 #define PWMV2_IRQ_STS_IRQ_BURSTEND_SHIFT (5U)
659 #define PWMV2_IRQ_STS_IRQ_BURSTEND_GET(x) (((uint32_t)(x) & PWMV2_IRQ_STS_IRQ_BURSTEND_MASK) >> PWMV2_IRQ_STS_IRQ_BURSTEND_SHIFT)
660 
661 /*
662  * IRQ_FAULT (RO)
663  *
664  * for external fault event
665  */
666 #define PWMV2_IRQ_STS_IRQ_FAULT_MASK (0x10U)
667 #define PWMV2_IRQ_STS_IRQ_FAULT_SHIFT (4U)
668 #define PWMV2_IRQ_STS_IRQ_FAULT_GET(x) (((uint32_t)(x) & PWMV2_IRQ_STS_IRQ_FAULT_MASK) >> PWMV2_IRQ_STS_IRQ_FAULT_SHIFT)
669 
670 /*
671  * IRQ_CAPTURE_NEG (RO)
672  *
673  * capture negedge status
674  */
675 #define PWMV2_IRQ_STS_IRQ_CAPTURE_NEG_MASK (0x8U)
676 #define PWMV2_IRQ_STS_IRQ_CAPTURE_NEG_SHIFT (3U)
677 #define PWMV2_IRQ_STS_IRQ_CAPTURE_NEG_GET(x) (((uint32_t)(x) & PWMV2_IRQ_STS_IRQ_CAPTURE_NEG_MASK) >> PWMV2_IRQ_STS_IRQ_CAPTURE_NEG_SHIFT)
678 
679 /*
680  * IRQ_CAPTURE_POS (RO)
681  *
682  * capture posedge status
683  */
684 #define PWMV2_IRQ_STS_IRQ_CAPTURE_POS_MASK (0x4U)
685 #define PWMV2_IRQ_STS_IRQ_CAPTURE_POS_SHIFT (2U)
686 #define PWMV2_IRQ_STS_IRQ_CAPTURE_POS_GET(x) (((uint32_t)(x) & PWMV2_IRQ_STS_IRQ_CAPTURE_POS_MASK) >> PWMV2_IRQ_STS_IRQ_CAPTURE_POS_SHIFT)
687 
688 /*
689  * IRQ_RELOAD (RO)
690  *
691  * when clock counter reach the reload time
692  */
693 #define PWMV2_IRQ_STS_IRQ_RELOAD_MASK (0x2U)
694 #define PWMV2_IRQ_STS_IRQ_RELOAD_SHIFT (1U)
695 #define PWMV2_IRQ_STS_IRQ_RELOAD_GET(x) (((uint32_t)(x) & PWMV2_IRQ_STS_IRQ_RELOAD_MASK) >> PWMV2_IRQ_STS_IRQ_RELOAD_SHIFT)
696 
697 /*
698  * IRQ_CMP (RO)
699  *
700  * for 24 channel, compare event
701  */
702 #define PWMV2_IRQ_STS_IRQ_CMP_MASK (0x1U)
703 #define PWMV2_IRQ_STS_IRQ_CMP_SHIFT (0U)
704 #define PWMV2_IRQ_STS_IRQ_CMP_GET(x) (((uint32_t)(x) & PWMV2_IRQ_STS_IRQ_CMP_MASK) >> PWMV2_IRQ_STS_IRQ_CMP_SHIFT)
705 
706 /* Bitfield definition for register: IRQ_EN */
707 /*
708  * IRQ_EN_OVERFLOW (RW)
709  *
710  * enable interrupt when calculation unit overflow
711  */
712 #define PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_MASK (0x80000000UL)
713 #define PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_SHIFT (31U)
714 #define PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_SET(x) (((uint32_t)(x) << PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_SHIFT) & PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_MASK)
715 #define PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_GET(x) (((uint32_t)(x) & PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_MASK) >> PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_SHIFT)
716 
717 /* Bitfield definition for register: IRQ_STS_CMP */
718 /*
719  * IRQ_STS_CMP (W1C)
720  *
721  * interrupt flag for compare point match event, and each bit means one compare point.
722  */
723 #define PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_MASK (0xFFFFFFUL)
724 #define PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_SHIFT (0U)
725 #define PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_SET(x) (((uint32_t)(x) << PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_SHIFT) & PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_MASK)
726 #define PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_GET(x) (((uint32_t)(x) & PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_MASK) >> PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_SHIFT)
727 
728 /* Bitfield definition for register: IRQ_STS_RELOAD */
729 /*
730  * IRQ_STS_RELOAD (W1C)
731  *
732  * interrupt flag for reload event , and each bit means one main counter.
733  */
734 #define PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_MASK (0xFU)
735 #define PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_SHIFT (0U)
736 #define PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_SET(x) (((uint32_t)(x) << PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_SHIFT) & PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_MASK)
737 #define PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_GET(x) (((uint32_t)(x) & PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_MASK) >> PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_SHIFT)
738 
739 /* Bitfield definition for register: IRQ_STS_CAP_POS */
740 /*
741  * IRQ_STS_CAP_POS (W1C)
742  *
743  * interrupt flag for posedge capture event , and each bit means one capture channel.
744  */
745 #define PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_MASK (0xFFU)
746 #define PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_SHIFT (0U)
747 #define PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_SET(x) (((uint32_t)(x) << PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_SHIFT) & PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_MASK)
748 #define PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_GET(x) (((uint32_t)(x) & PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_MASK) >> PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_SHIFT)
749 
750 /* Bitfield definition for register: IRQ_STS_CAP_NEG */
751 /*
752  * IRQ_STS_CAP_NEG (W1C)
753  *
754  * interrupt flag for negedge capture event , and each bit means one capture channel.
755  */
756 #define PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_MASK (0xFFU)
757 #define PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_SHIFT (0U)
758 #define PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_SET(x) (((uint32_t)(x) << PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_SHIFT) & PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_MASK)
759 #define PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_GET(x) (((uint32_t)(x) & PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_MASK) >> PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_SHIFT)
760 
761 /* Bitfield definition for register: IRQ_STS_FAULT */
762 /*
763  * IRQ_STS_FAULT (W1C)
764  *
765  * interrupt flag for external fault event , and each bit means one external fault channel.
766  */
767 #define PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_MASK (0xFFU)
768 #define PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_SHIFT (0U)
769 #define PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_SET(x) (((uint32_t)(x) << PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_SHIFT) & PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_MASK)
770 #define PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_GET(x) (((uint32_t)(x) & PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_MASK) >> PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_SHIFT)
771 
772 /* Bitfield definition for register: IRQ_STS_BURSTEND */
773 /*
774  * IRQ_STS_BURSTEND (W1C)
775  *
776  * interrupt flag for output burst done event , and each bit means one main counter.
777  */
778 #define PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_MASK (0xFU)
779 #define PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_SHIFT (0U)
780 #define PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_SET(x) (((uint32_t)(x) << PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_SHIFT) & PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_MASK)
781 #define PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_GET(x) (((uint32_t)(x) & PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_MASK) >> PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_SHIFT)
782 
783 /* Bitfield definition for register: IRQ_EN_CMP */
784 /*
785  * IRQ_EN_CMP (RW)
786  *
787  * interrupt enable field for compare point match event, and each bit means one compare point.
788  */
789 #define PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_MASK (0xFFFFFFUL)
790 #define PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_SHIFT (0U)
791 #define PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_SET(x) (((uint32_t)(x) << PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_SHIFT) & PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_MASK)
792 #define PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_GET(x) (((uint32_t)(x) & PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_MASK) >> PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_SHIFT)
793 
794 /* Bitfield definition for register: IRQ_EN_RELOAD */
795 /*
796  * IRQ_EN_RELOAD (RW)
797  *
798  * interrupt enable field for reload event , and each bit means one main counter.
799  */
800 #define PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_MASK (0xFU)
801 #define PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_SHIFT (0U)
802 #define PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_SET(x) (((uint32_t)(x) << PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_SHIFT) & PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_MASK)
803 #define PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_GET(x) (((uint32_t)(x) & PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_MASK) >> PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_SHIFT)
804 
805 /* Bitfield definition for register: IRQ_EN_CAP_POS */
806 /*
807  * IRQ_EN_CAP_POS (RW)
808  *
809  * interrupt enable field for posedge capture event , and each bit means one capture channel.
810  */
811 #define PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_MASK (0xFFU)
812 #define PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_SHIFT (0U)
813 #define PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_SET(x) (((uint32_t)(x) << PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_SHIFT) & PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_MASK)
814 #define PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_GET(x) (((uint32_t)(x) & PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_MASK) >> PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_SHIFT)
815 
816 /* Bitfield definition for register: IRQ_EN_CAP_NEG */
817 /*
818  * IRQ_EN_CAP_NEG (RW)
819  *
820  * interrupt enable field for negedge capture event , and each bit means one capture channel.
821  */
822 #define PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_MASK (0xFFU)
823 #define PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_SHIFT (0U)
824 #define PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_SET(x) (((uint32_t)(x) << PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_SHIFT) & PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_MASK)
825 #define PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_GET(x) (((uint32_t)(x) & PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_MASK) >> PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_SHIFT)
826 
827 /* Bitfield definition for register: IRQ_EN_FAULT */
828 /*
829  * IRQ_EN_FAULT (RW)
830  *
831  * interrupt enable field for external fault event , and each bit means one external fault channel.
832  */
833 #define PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_MASK (0xFFU)
834 #define PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_SHIFT (0U)
835 #define PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_SET(x) (((uint32_t)(x) << PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_SHIFT) & PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_MASK)
836 #define PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_GET(x) (((uint32_t)(x) & PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_MASK) >> PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_SHIFT)
837 
838 /* Bitfield definition for register: IRQ_EN_BURSTEND */
839 /*
840  * IRQ_EN_BURSTEND (RW)
841  *
842  * interrupt enable field for output burst done event , and each bit means one main counter.
843  */
844 #define PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_MASK (0xFU)
845 #define PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_SHIFT (0U)
846 #define PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_SET(x) (((uint32_t)(x) << PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_SHIFT) & PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_MASK)
847 #define PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_GET(x) (((uint32_t)(x) & PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_MASK) >> PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_SHIFT)
848 
849 /* Bitfield definition for register: DMA_EN */
850 /*
851  * DMA3_EN (RW)
852  *
853  * enable dma3
854  */
855 #define PWMV2_DMA_EN_DMA3_EN_MASK (0x80000000UL)
856 #define PWMV2_DMA_EN_DMA3_EN_SHIFT (31U)
857 #define PWMV2_DMA_EN_DMA3_EN_SET(x) (((uint32_t)(x) << PWMV2_DMA_EN_DMA3_EN_SHIFT) & PWMV2_DMA_EN_DMA3_EN_MASK)
858 #define PWMV2_DMA_EN_DMA3_EN_GET(x) (((uint32_t)(x) & PWMV2_DMA_EN_DMA3_EN_MASK) >> PWMV2_DMA_EN_DMA3_EN_SHIFT)
859 
860 /*
861  * DMA3_SEL (RW)
862  *
863  * selelct one of compare point(0~23) or one reload point(24~27) as dma0
864  */
865 #define PWMV2_DMA_EN_DMA3_SEL_MASK (0x1F000000UL)
866 #define PWMV2_DMA_EN_DMA3_SEL_SHIFT (24U)
867 #define PWMV2_DMA_EN_DMA3_SEL_SET(x) (((uint32_t)(x) << PWMV2_DMA_EN_DMA3_SEL_SHIFT) & PWMV2_DMA_EN_DMA3_SEL_MASK)
868 #define PWMV2_DMA_EN_DMA3_SEL_GET(x) (((uint32_t)(x) & PWMV2_DMA_EN_DMA3_SEL_MASK) >> PWMV2_DMA_EN_DMA3_SEL_SHIFT)
869 
870 /*
871  * DMA2_EN (RW)
872  *
873  * enable dma2
874  */
875 #define PWMV2_DMA_EN_DMA2_EN_MASK (0x800000UL)
876 #define PWMV2_DMA_EN_DMA2_EN_SHIFT (23U)
877 #define PWMV2_DMA_EN_DMA2_EN_SET(x) (((uint32_t)(x) << PWMV2_DMA_EN_DMA2_EN_SHIFT) & PWMV2_DMA_EN_DMA2_EN_MASK)
878 #define PWMV2_DMA_EN_DMA2_EN_GET(x) (((uint32_t)(x) & PWMV2_DMA_EN_DMA2_EN_MASK) >> PWMV2_DMA_EN_DMA2_EN_SHIFT)
879 
880 /*
881  * DMA2_SEL (RW)
882  *
883  * selelct one of compare point(0~23) or one reload point(24~27) as dma0
884  */
885 #define PWMV2_DMA_EN_DMA2_SEL_MASK (0x1F0000UL)
886 #define PWMV2_DMA_EN_DMA2_SEL_SHIFT (16U)
887 #define PWMV2_DMA_EN_DMA2_SEL_SET(x) (((uint32_t)(x) << PWMV2_DMA_EN_DMA2_SEL_SHIFT) & PWMV2_DMA_EN_DMA2_SEL_MASK)
888 #define PWMV2_DMA_EN_DMA2_SEL_GET(x) (((uint32_t)(x) & PWMV2_DMA_EN_DMA2_SEL_MASK) >> PWMV2_DMA_EN_DMA2_SEL_SHIFT)
889 
890 /*
891  * DMA1_EN (RW)
892  *
893  * enable dma1
894  */
895 #define PWMV2_DMA_EN_DMA1_EN_MASK (0x8000U)
896 #define PWMV2_DMA_EN_DMA1_EN_SHIFT (15U)
897 #define PWMV2_DMA_EN_DMA1_EN_SET(x) (((uint32_t)(x) << PWMV2_DMA_EN_DMA1_EN_SHIFT) & PWMV2_DMA_EN_DMA1_EN_MASK)
898 #define PWMV2_DMA_EN_DMA1_EN_GET(x) (((uint32_t)(x) & PWMV2_DMA_EN_DMA1_EN_MASK) >> PWMV2_DMA_EN_DMA1_EN_SHIFT)
899 
900 /*
901  * DMA1_SEL (RW)
902  *
903  * selelct one of compare point(0~23) or one reload point(24~27) as dma0
904  */
905 #define PWMV2_DMA_EN_DMA1_SEL_MASK (0x1F00U)
906 #define PWMV2_DMA_EN_DMA1_SEL_SHIFT (8U)
907 #define PWMV2_DMA_EN_DMA1_SEL_SET(x) (((uint32_t)(x) << PWMV2_DMA_EN_DMA1_SEL_SHIFT) & PWMV2_DMA_EN_DMA1_SEL_MASK)
908 #define PWMV2_DMA_EN_DMA1_SEL_GET(x) (((uint32_t)(x) & PWMV2_DMA_EN_DMA1_SEL_MASK) >> PWMV2_DMA_EN_DMA1_SEL_SHIFT)
909 
910 /*
911  * DMA0_EN (RW)
912  *
913  * enable dma0
914  */
915 #define PWMV2_DMA_EN_DMA0_EN_MASK (0x80U)
916 #define PWMV2_DMA_EN_DMA0_EN_SHIFT (7U)
917 #define PWMV2_DMA_EN_DMA0_EN_SET(x) (((uint32_t)(x) << PWMV2_DMA_EN_DMA0_EN_SHIFT) & PWMV2_DMA_EN_DMA0_EN_MASK)
918 #define PWMV2_DMA_EN_DMA0_EN_GET(x) (((uint32_t)(x) & PWMV2_DMA_EN_DMA0_EN_MASK) >> PWMV2_DMA_EN_DMA0_EN_SHIFT)
919 
920 /*
921  * DMA0_SEL (RW)
922  *
923  * selelct one of compare point(0~23) or one reload point(24~27) as dma0
924  */
925 #define PWMV2_DMA_EN_DMA0_SEL_MASK (0x1FU)
926 #define PWMV2_DMA_EN_DMA0_SEL_SHIFT (0U)
927 #define PWMV2_DMA_EN_DMA0_SEL_SET(x) (((uint32_t)(x) << PWMV2_DMA_EN_DMA0_SEL_SHIFT) & PWMV2_DMA_EN_DMA0_SEL_MASK)
928 #define PWMV2_DMA_EN_DMA0_SEL_GET(x) (((uint32_t)(x) & PWMV2_DMA_EN_DMA0_SEL_MASK) >> PWMV2_DMA_EN_DMA0_SEL_SHIFT)
929 
930 /* Bitfield definition for register of struct array CNT: CFG0 */
931 /*
932  * RLD_CMP_SEL1 (RW)
933  *
934  * select one compare point from 24, set to 0x1F to disable current selection, used for reload value, compare value, force value update
935  */
936 #define PWMV2_CNT_CFG0_RLD_CMP_SEL1_MASK (0x1F000000UL)
937 #define PWMV2_CNT_CFG0_RLD_CMP_SEL1_SHIFT (24U)
938 #define PWMV2_CNT_CFG0_RLD_CMP_SEL1_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG0_RLD_CMP_SEL1_SHIFT) & PWMV2_CNT_CFG0_RLD_CMP_SEL1_MASK)
939 #define PWMV2_CNT_CFG0_RLD_CMP_SEL1_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG0_RLD_CMP_SEL1_MASK) >> PWMV2_CNT_CFG0_RLD_CMP_SEL1_SHIFT)
940 
941 /*
942  * RLD_CMP_SEL0 (RW)
943  *
944  * select one compare point from 24, set to 0x1F to disable current selection
945  */
946 #define PWMV2_CNT_CFG0_RLD_CMP_SEL0_MASK (0x1F0000UL)
947 #define PWMV2_CNT_CFG0_RLD_CMP_SEL0_SHIFT (16U)
948 #define PWMV2_CNT_CFG0_RLD_CMP_SEL0_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG0_RLD_CMP_SEL0_SHIFT) & PWMV2_CNT_CFG0_RLD_CMP_SEL0_MASK)
949 #define PWMV2_CNT_CFG0_RLD_CMP_SEL0_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG0_RLD_CMP_SEL0_MASK) >> PWMV2_CNT_CFG0_RLD_CMP_SEL0_SHIFT)
950 
951 /*
952  * RLD_TRIG_SEL (RW)
953  *
954  * select one trigger from 8, should set to pulse in trig_mux
955  */
956 #define PWMV2_CNT_CFG0_RLD_TRIG_SEL_MASK (0x7000U)
957 #define PWMV2_CNT_CFG0_RLD_TRIG_SEL_SHIFT (12U)
958 #define PWMV2_CNT_CFG0_RLD_TRIG_SEL_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG0_RLD_TRIG_SEL_SHIFT) & PWMV2_CNT_CFG0_RLD_TRIG_SEL_MASK)
959 #define PWMV2_CNT_CFG0_RLD_TRIG_SEL_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG0_RLD_TRIG_SEL_MASK) >> PWMV2_CNT_CFG0_RLD_TRIG_SEL_SHIFT)
960 
961 /*
962  * RLD_UPDATE_TIME (RW)
963  *
964  * define when to use the calculation output value as reload time
965  * 00: software set work_ctrl1.shadow_lock bit
966  * 01: use compare point selected by rld_cmp_sel0 or rld_cmp_sel1
967  * 10: counter reload time
968  * 11: use rld_trig_sel to select one of the input trigger
969  * NOTE: 00 is not recommended since the update time is not controllable, may cause error in complex application.
970  */
971 #define PWMV2_CNT_CFG0_RLD_UPDATE_TIME_MASK (0x300U)
972 #define PWMV2_CNT_CFG0_RLD_UPDATE_TIME_SHIFT (8U)
973 #define PWMV2_CNT_CFG0_RLD_UPDATE_TIME_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG0_RLD_UPDATE_TIME_SHIFT) & PWMV2_CNT_CFG0_RLD_UPDATE_TIME_MASK)
974 #define PWMV2_CNT_CFG0_RLD_UPDATE_TIME_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG0_RLD_UPDATE_TIME_MASK) >> PWMV2_CNT_CFG0_RLD_UPDATE_TIME_SHIFT)
975 
976 /*
977  * CNT_D_PARAM (RW)
978  *
979  * input dac data parameter
980  */
981 #define PWMV2_CNT_CFG0_CNT_D_PARAM_MASK (0x1FU)
982 #define PWMV2_CNT_CFG0_CNT_D_PARAM_SHIFT (0U)
983 #define PWMV2_CNT_CFG0_CNT_D_PARAM_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG0_CNT_D_PARAM_SHIFT) & PWMV2_CNT_CFG0_CNT_D_PARAM_MASK)
984 #define PWMV2_CNT_CFG0_CNT_D_PARAM_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG0_CNT_D_PARAM_MASK) >> PWMV2_CNT_CFG0_CNT_D_PARAM_SHIFT)
985 
986 /* Bitfield definition for register of struct array CNT: CFG1 */
987 /*
988  * CNT_DAC_INDEX (RW)
989  *
990  * select one of the dac value
991  */
992 #define PWMV2_CNT_CFG1_CNT_DAC_INDEX_MASK (0x3000000UL)
993 #define PWMV2_CNT_CFG1_CNT_DAC_INDEX_SHIFT (24U)
994 #define PWMV2_CNT_CFG1_CNT_DAC_INDEX_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG1_CNT_DAC_INDEX_SHIFT) & PWMV2_CNT_CFG1_CNT_DAC_INDEX_MASK)
995 #define PWMV2_CNT_CFG1_CNT_DAC_INDEX_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG1_CNT_DAC_INDEX_MASK) >> PWMV2_CNT_CFG1_CNT_DAC_INDEX_SHIFT)
996 
997 /*
998  * CNT_LU_EN (RW)
999  *
1000  * set to enable up limit, use cnt_lu_off to select one of the shadow register value as limitation
1001  */
1002 #define PWMV2_CNT_CFG1_CNT_LU_EN_MASK (0x800000UL)
1003 #define PWMV2_CNT_CFG1_CNT_LU_EN_SHIFT (23U)
1004 #define PWMV2_CNT_CFG1_CNT_LU_EN_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG1_CNT_LU_EN_SHIFT) & PWMV2_CNT_CFG1_CNT_LU_EN_MASK)
1005 #define PWMV2_CNT_CFG1_CNT_LU_EN_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG1_CNT_LU_EN_MASK) >> PWMV2_CNT_CFG1_CNT_LU_EN_SHIFT)
1006 
1007 /*
1008  * CNT_LIM_UP (RW)
1009  *
1010  * up limit offset selection, from one of the shadow_val
1011  */
1012 #define PWMV2_CNT_CFG1_CNT_LIM_UP_MASK (0x1F0000UL)
1013 #define PWMV2_CNT_CFG1_CNT_LIM_UP_SHIFT (16U)
1014 #define PWMV2_CNT_CFG1_CNT_LIM_UP_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG1_CNT_LIM_UP_SHIFT) & PWMV2_CNT_CFG1_CNT_LIM_UP_MASK)
1015 #define PWMV2_CNT_CFG1_CNT_LIM_UP_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG1_CNT_LIM_UP_MASK) >> PWMV2_CNT_CFG1_CNT_LIM_UP_SHIFT)
1016 
1017 /*
1018  * CNT_LL_EN (RW)
1019  *
1020  * set to enable low limit
1021  */
1022 #define PWMV2_CNT_CFG1_CNT_LL_EN_MASK (0x8000U)
1023 #define PWMV2_CNT_CFG1_CNT_LL_EN_SHIFT (15U)
1024 #define PWMV2_CNT_CFG1_CNT_LL_EN_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG1_CNT_LL_EN_SHIFT) & PWMV2_CNT_CFG1_CNT_LL_EN_MASK)
1025 #define PWMV2_CNT_CFG1_CNT_LL_EN_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG1_CNT_LL_EN_MASK) >> PWMV2_CNT_CFG1_CNT_LL_EN_SHIFT)
1026 
1027 /*
1028  * CNT_LIM_LO (RW)
1029  *
1030  * low limit offset selection, from one of the shadow_val
1031  */
1032 #define PWMV2_CNT_CFG1_CNT_LIM_LO_MASK (0x1F00U)
1033 #define PWMV2_CNT_CFG1_CNT_LIM_LO_SHIFT (8U)
1034 #define PWMV2_CNT_CFG1_CNT_LIM_LO_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG1_CNT_LIM_LO_SHIFT) & PWMV2_CNT_CFG1_CNT_LIM_LO_MASK)
1035 #define PWMV2_CNT_CFG1_CNT_LIM_LO_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG1_CNT_LIM_LO_MASK) >> PWMV2_CNT_CFG1_CNT_LIM_LO_SHIFT)
1036 
1037 /*
1038  * CNT_IN_OFF (RW)
1039  *
1040  * input data offset selection, from one of the shadow_val, default just shadow reload time
1041  */
1042 #define PWMV2_CNT_CFG1_CNT_IN_OFF_MASK (0x1FU)
1043 #define PWMV2_CNT_CFG1_CNT_IN_OFF_SHIFT (0U)
1044 #define PWMV2_CNT_CFG1_CNT_IN_OFF_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG1_CNT_IN_OFF_SHIFT) & PWMV2_CNT_CFG1_CNT_IN_OFF_MASK)
1045 #define PWMV2_CNT_CFG1_CNT_IN_OFF_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG1_CNT_IN_OFF_MASK) >> PWMV2_CNT_CFG1_CNT_IN_OFF_SHIFT)
1046 
1047 /* Bitfield definition for register of struct array CNT: CFG2 */
1048 /*
1049  * CNT_RELOAD_EN (RW)
1050  *
1051  * set to use input signal(selected by cnt_reload_trig) to reload timer
1052  */
1053 #define PWMV2_CNT_CFG2_CNT_RELOAD_EN_MASK (0x80000000UL)
1054 #define PWMV2_CNT_CFG2_CNT_RELOAD_EN_SHIFT (31U)
1055 #define PWMV2_CNT_CFG2_CNT_RELOAD_EN_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_RELOAD_EN_SHIFT) & PWMV2_CNT_CFG2_CNT_RELOAD_EN_MASK)
1056 #define PWMV2_CNT_CFG2_CNT_RELOAD_EN_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_RELOAD_EN_MASK) >> PWMV2_CNT_CFG2_CNT_RELOAD_EN_SHIFT)
1057 
1058 /*
1059  * CNT_RELOAD_TRIG (RW)
1060  *
1061  * select one trigger from 8, should set to pulse in trig_mux
1062  */
1063 #define PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_MASK (0x7000000UL)
1064 #define PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_SHIFT (24U)
1065 #define PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_SHIFT) & PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_MASK)
1066 #define PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_MASK) >> PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_SHIFT)
1067 
1068 /*
1069  * CNT_UPDATE_TRIG1 (RW)
1070  *
1071  * select one trigger from 8, should set to pulse in trig_mux
1072  */
1073 #define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_MASK (0x700000UL)
1074 #define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_SHIFT (20U)
1075 #define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_SHIFT) & PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_MASK)
1076 #define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_MASK) >> PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_SHIFT)
1077 
1078 /*
1079  * CNT_UPDATE_EN1 (RW)
1080  *
1081  * set to enable using trig1 to load calculation cell output to counter
1082  */
1083 #define PWMV2_CNT_CFG2_CNT_UPDATE_EN1_MASK (0x80000UL)
1084 #define PWMV2_CNT_CFG2_CNT_UPDATE_EN1_SHIFT (19U)
1085 #define PWMV2_CNT_CFG2_CNT_UPDATE_EN1_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_UPDATE_EN1_SHIFT) & PWMV2_CNT_CFG2_CNT_UPDATE_EN1_MASK)
1086 #define PWMV2_CNT_CFG2_CNT_UPDATE_EN1_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_UPDATE_EN1_MASK) >> PWMV2_CNT_CFG2_CNT_UPDATE_EN1_SHIFT)
1087 
1088 /*
1089  * CNT_TRIG1 (RW)
1090  *
1091  * change counter value to one of the calculation cell output when cnt_update_triger1 issued
1092  */
1093 #define PWMV2_CNT_CFG2_CNT_TRIG1_MASK (0xF000U)
1094 #define PWMV2_CNT_CFG2_CNT_TRIG1_SHIFT (12U)
1095 #define PWMV2_CNT_CFG2_CNT_TRIG1_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_TRIG1_SHIFT) & PWMV2_CNT_CFG2_CNT_TRIG1_MASK)
1096 #define PWMV2_CNT_CFG2_CNT_TRIG1_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_TRIG1_MASK) >> PWMV2_CNT_CFG2_CNT_TRIG1_SHIFT)
1097 
1098 /*
1099  * CNT_UPDATE_TRIG0 (RW)
1100  *
1101  * select one trigger from 8, should set to pulse in trig_mux
1102  */
1103 #define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_MASK (0x700U)
1104 #define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_SHIFT (8U)
1105 #define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_SHIFT) & PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_MASK)
1106 #define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_MASK) >> PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_SHIFT)
1107 
1108 /*
1109  * CNT_UPDATE_EN0 (RW)
1110  *
1111  * set to enable using trig0 to load calculation cell output to counter
1112  */
1113 #define PWMV2_CNT_CFG2_CNT_UPDATE_EN0_MASK (0x80U)
1114 #define PWMV2_CNT_CFG2_CNT_UPDATE_EN0_SHIFT (7U)
1115 #define PWMV2_CNT_CFG2_CNT_UPDATE_EN0_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_UPDATE_EN0_SHIFT) & PWMV2_CNT_CFG2_CNT_UPDATE_EN0_MASK)
1116 #define PWMV2_CNT_CFG2_CNT_UPDATE_EN0_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_UPDATE_EN0_MASK) >> PWMV2_CNT_CFG2_CNT_UPDATE_EN0_SHIFT)
1117 
1118 /*
1119  * CNT_TRIG0 (RW)
1120  *
1121  * change counter value to one of the calculation cell output when cnt_update_triger0 issued
1122  */
1123 #define PWMV2_CNT_CFG2_CNT_TRIG0_MASK (0xFU)
1124 #define PWMV2_CNT_CFG2_CNT_TRIG0_SHIFT (0U)
1125 #define PWMV2_CNT_CFG2_CNT_TRIG0_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_TRIG0_SHIFT) & PWMV2_CNT_CFG2_CNT_TRIG0_MASK)
1126 #define PWMV2_CNT_CFG2_CNT_TRIG0_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_TRIG0_MASK) >> PWMV2_CNT_CFG2_CNT_TRIG0_SHIFT)
1127 
1128 /* Bitfield definition for register of struct array CNT: CFG3 */
1129 /*
1130  * CNT_START_SEL (RW)
1131  *
1132  * select one trigger from 8, should set to pulse in trig_mux
1133  */
1134 #define PWMV2_CNT_CFG3_CNT_START_SEL_MASK (0x700000UL)
1135 #define PWMV2_CNT_CFG3_CNT_START_SEL_SHIFT (20U)
1136 #define PWMV2_CNT_CFG3_CNT_START_SEL_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG3_CNT_START_SEL_SHIFT) & PWMV2_CNT_CFG3_CNT_START_SEL_MASK)
1137 #define PWMV2_CNT_CFG3_CNT_START_SEL_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG3_CNT_START_SEL_MASK) >> PWMV2_CNT_CFG3_CNT_START_SEL_SHIFT)
1138 
1139 /*
1140  * CNT_HW_START_EN (RW)
1141  *
1142  * enable use trigger to start pwm output(at next reload point), by cnt_start_sel
1143  */
1144 #define PWMV2_CNT_CFG3_CNT_HW_START_EN_MASK (0x20000UL)
1145 #define PWMV2_CNT_CFG3_CNT_HW_START_EN_SHIFT (17U)
1146 #define PWMV2_CNT_CFG3_CNT_HW_START_EN_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG3_CNT_HW_START_EN_SHIFT) & PWMV2_CNT_CFG3_CNT_HW_START_EN_MASK)
1147 #define PWMV2_CNT_CFG3_CNT_HW_START_EN_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG3_CNT_HW_START_EN_MASK) >> PWMV2_CNT_CFG3_CNT_HW_START_EN_SHIFT)
1148 
1149 /*
1150  * CNT_BURST (RW)
1151  *
1152  * output pwm wave for configured burst(timer period),
1153  * 0 for one burst; 1 for two burst.
1154  * set to 0xFFFF for always output pwm wave
1155  * bit's only used when setting cnt_sw_start or trigger selected by cnt_start_sel
1156  */
1157 #define PWMV2_CNT_CFG3_CNT_BURST_MASK (0xFFFFU)
1158 #define PWMV2_CNT_CFG3_CNT_BURST_SHIFT (0U)
1159 #define PWMV2_CNT_CFG3_CNT_BURST_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG3_CNT_BURST_SHIFT) & PWMV2_CNT_CFG3_CNT_BURST_MASK)
1160 #define PWMV2_CNT_CFG3_CNT_BURST_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG3_CNT_BURST_MASK) >> PWMV2_CNT_CFG3_CNT_BURST_SHIFT)
1161 
1162 /* Bitfield definition for register: CNT_GLBCFG */
1163 /*
1164  * CNT_SW_START (WO)
1165  *
1166  * set to start pwm output(at next reload point), write only, Auto clear.
1167  * User can disable pwm output before burst end by start again with cnt_burst=0
1168  */
1169 #define PWMV2_CNT_GLBCFG_CNT_SW_START_MASK (0xF0000UL)
1170 #define PWMV2_CNT_GLBCFG_CNT_SW_START_SHIFT (16U)
1171 #define PWMV2_CNT_GLBCFG_CNT_SW_START_SET(x) (((uint32_t)(x) << PWMV2_CNT_GLBCFG_CNT_SW_START_SHIFT) & PWMV2_CNT_GLBCFG_CNT_SW_START_MASK)
1172 #define PWMV2_CNT_GLBCFG_CNT_SW_START_GET(x) (((uint32_t)(x) & PWMV2_CNT_GLBCFG_CNT_SW_START_MASK) >> PWMV2_CNT_GLBCFG_CNT_SW_START_SHIFT)
1173 
1174 /*
1175  * TIMER_RESET (WO)
1176  *
1177  * set to clear current timer. Auto clear
1178  */
1179 #define PWMV2_CNT_GLBCFG_TIMER_RESET_MASK (0xF00U)
1180 #define PWMV2_CNT_GLBCFG_TIMER_RESET_SHIFT (8U)
1181 #define PWMV2_CNT_GLBCFG_TIMER_RESET_SET(x) (((uint32_t)(x) << PWMV2_CNT_GLBCFG_TIMER_RESET_SHIFT) & PWMV2_CNT_GLBCFG_TIMER_RESET_MASK)
1182 #define PWMV2_CNT_GLBCFG_TIMER_RESET_GET(x) (((uint32_t)(x) & PWMV2_CNT_GLBCFG_TIMER_RESET_MASK) >> PWMV2_CNT_GLBCFG_TIMER_RESET_SHIFT)
1183 
1184 /*
1185  * TIMER_ENABLE (RW)
1186  *
1187  * 1 to enable the main cycle counter; 0 to stop the counter;
1188  * NOTE: when counter stopped, the related trigger_out will be cleared to 0, the related pwm output will keep value not changed.
1189  */
1190 #define PWMV2_CNT_GLBCFG_TIMER_ENABLE_MASK (0xFU)
1191 #define PWMV2_CNT_GLBCFG_TIMER_ENABLE_SHIFT (0U)
1192 #define PWMV2_CNT_GLBCFG_TIMER_ENABLE_SET(x) (((uint32_t)(x) << PWMV2_CNT_GLBCFG_TIMER_ENABLE_SHIFT) & PWMV2_CNT_GLBCFG_TIMER_ENABLE_MASK)
1193 #define PWMV2_CNT_GLBCFG_TIMER_ENABLE_GET(x) (((uint32_t)(x) & PWMV2_CNT_GLBCFG_TIMER_ENABLE_MASK) >> PWMV2_CNT_GLBCFG_TIMER_ENABLE_SHIFT)
1194 
1195 /* Bitfield definition for register of struct array CAL: CFG0 */
1196 /*
1197  * CAL_LU_PARAM (RW)
1198  *
1199  * up limit parameter
1200  */
1201 #define PWMV2_CAL_CFG0_CAL_LU_PARAM_MASK (0x1F000000UL)
1202 #define PWMV2_CAL_CFG0_CAL_LU_PARAM_SHIFT (24U)
1203 #define PWMV2_CAL_CFG0_CAL_LU_PARAM_SET(x) (((uint32_t)(x) << PWMV2_CAL_CFG0_CAL_LU_PARAM_SHIFT) & PWMV2_CAL_CFG0_CAL_LU_PARAM_MASK)
1204 #define PWMV2_CAL_CFG0_CAL_LU_PARAM_GET(x) (((uint32_t)(x) & PWMV2_CAL_CFG0_CAL_LU_PARAM_MASK) >> PWMV2_CAL_CFG0_CAL_LU_PARAM_SHIFT)
1205 
1206 /*
1207  * CAL_LL_PARAM (RW)
1208  *
1209  * low limit parameter
1210  */
1211 #define PWMV2_CAL_CFG0_CAL_LL_PARAM_MASK (0x1F0000UL)
1212 #define PWMV2_CAL_CFG0_CAL_LL_PARAM_SHIFT (16U)
1213 #define PWMV2_CAL_CFG0_CAL_LL_PARAM_SET(x) (((uint32_t)(x) << PWMV2_CAL_CFG0_CAL_LL_PARAM_SHIFT) & PWMV2_CAL_CFG0_CAL_LL_PARAM_MASK)
1214 #define PWMV2_CAL_CFG0_CAL_LL_PARAM_GET(x) (((uint32_t)(x) & PWMV2_CAL_CFG0_CAL_LL_PARAM_MASK) >> PWMV2_CAL_CFG0_CAL_LL_PARAM_SHIFT)
1215 
1216 /*
1217  * CAL_T_PARAM (RW)
1218  *
1219  * period parameter
1220  */
1221 #define PWMV2_CAL_CFG0_CAL_T_PARAM_MASK (0x1F00U)
1222 #define PWMV2_CAL_CFG0_CAL_T_PARAM_SHIFT (8U)
1223 #define PWMV2_CAL_CFG0_CAL_T_PARAM_SET(x) (((uint32_t)(x) << PWMV2_CAL_CFG0_CAL_T_PARAM_SHIFT) & PWMV2_CAL_CFG0_CAL_T_PARAM_MASK)
1224 #define PWMV2_CAL_CFG0_CAL_T_PARAM_GET(x) (((uint32_t)(x) & PWMV2_CAL_CFG0_CAL_T_PARAM_MASK) >> PWMV2_CAL_CFG0_CAL_T_PARAM_SHIFT)
1225 
1226 /*
1227  * CAL_D_PARAM (RW)
1228  *
1229  * dac/counter value parameter
1230  */
1231 #define PWMV2_CAL_CFG0_CAL_D_PARAM_MASK (0x1FU)
1232 #define PWMV2_CAL_CFG0_CAL_D_PARAM_SHIFT (0U)
1233 #define PWMV2_CAL_CFG0_CAL_D_PARAM_SET(x) (((uint32_t)(x) << PWMV2_CAL_CFG0_CAL_D_PARAM_SHIFT) & PWMV2_CAL_CFG0_CAL_D_PARAM_MASK)
1234 #define PWMV2_CAL_CFG0_CAL_D_PARAM_GET(x) (((uint32_t)(x) & PWMV2_CAL_CFG0_CAL_D_PARAM_MASK) >> PWMV2_CAL_CFG0_CAL_D_PARAM_SHIFT)
1235 
1236 /* Bitfield definition for register of struct array CAL: CFG1 */
1237 /*
1238  * CAL_T_INDEX (RW)
1239  *
1240  * select one of 4 counter reload time
1241  */
1242 #define PWMV2_CAL_CFG1_CAL_T_INDEX_MASK (0x30000000UL)
1243 #define PWMV2_CAL_CFG1_CAL_T_INDEX_SHIFT (28U)
1244 #define PWMV2_CAL_CFG1_CAL_T_INDEX_SET(x) (((uint32_t)(x) << PWMV2_CAL_CFG1_CAL_T_INDEX_SHIFT) & PWMV2_CAL_CFG1_CAL_T_INDEX_MASK)
1245 #define PWMV2_CAL_CFG1_CAL_T_INDEX_GET(x) (((uint32_t)(x) & PWMV2_CAL_CFG1_CAL_T_INDEX_MASK) >> PWMV2_CAL_CFG1_CAL_T_INDEX_SHIFT)
1246 
1247 /*
1248  * CAL_IN_INDEX (RW)
1249  *
1250  * 0~3 to select one of the dac input value; 4~7 to select one of the current counter value
1251  */
1252 #define PWMV2_CAL_CFG1_CAL_IN_INDEX_MASK (0x7000000UL)
1253 #define PWMV2_CAL_CFG1_CAL_IN_INDEX_SHIFT (24U)
1254 #define PWMV2_CAL_CFG1_CAL_IN_INDEX_SET(x) (((uint32_t)(x) << PWMV2_CAL_CFG1_CAL_IN_INDEX_SHIFT) & PWMV2_CAL_CFG1_CAL_IN_INDEX_MASK)
1255 #define PWMV2_CAL_CFG1_CAL_IN_INDEX_GET(x) (((uint32_t)(x) & PWMV2_CAL_CFG1_CAL_IN_INDEX_MASK) >> PWMV2_CAL_CFG1_CAL_IN_INDEX_SHIFT)
1256 
1257 /*
1258  * CAL_LU_EN (RW)
1259  *
1260  * set to enable up limit
1261  */
1262 #define PWMV2_CAL_CFG1_CAL_LU_EN_MASK (0x800000UL)
1263 #define PWMV2_CAL_CFG1_CAL_LU_EN_SHIFT (23U)
1264 #define PWMV2_CAL_CFG1_CAL_LU_EN_SET(x) (((uint32_t)(x) << PWMV2_CAL_CFG1_CAL_LU_EN_SHIFT) & PWMV2_CAL_CFG1_CAL_LU_EN_MASK)
1265 #define PWMV2_CAL_CFG1_CAL_LU_EN_GET(x) (((uint32_t)(x) & PWMV2_CAL_CFG1_CAL_LU_EN_MASK) >> PWMV2_CAL_CFG1_CAL_LU_EN_SHIFT)
1266 
1267 /*
1268  * CAL_LIM_UP (RW)
1269  *
1270  * up limit offset selection, select from one of the shadow_val
1271  */
1272 #define PWMV2_CAL_CFG1_CAL_LIM_UP_MASK (0x1F0000UL)
1273 #define PWMV2_CAL_CFG1_CAL_LIM_UP_SHIFT (16U)
1274 #define PWMV2_CAL_CFG1_CAL_LIM_UP_SET(x) (((uint32_t)(x) << PWMV2_CAL_CFG1_CAL_LIM_UP_SHIFT) & PWMV2_CAL_CFG1_CAL_LIM_UP_MASK)
1275 #define PWMV2_CAL_CFG1_CAL_LIM_UP_GET(x) (((uint32_t)(x) & PWMV2_CAL_CFG1_CAL_LIM_UP_MASK) >> PWMV2_CAL_CFG1_CAL_LIM_UP_SHIFT)
1276 
1277 /*
1278  * CAL_LL_EN (RW)
1279  *
1280  * set to enable low limit
1281  */
1282 #define PWMV2_CAL_CFG1_CAL_LL_EN_MASK (0x8000U)
1283 #define PWMV2_CAL_CFG1_CAL_LL_EN_SHIFT (15U)
1284 #define PWMV2_CAL_CFG1_CAL_LL_EN_SET(x) (((uint32_t)(x) << PWMV2_CAL_CFG1_CAL_LL_EN_SHIFT) & PWMV2_CAL_CFG1_CAL_LL_EN_MASK)
1285 #define PWMV2_CAL_CFG1_CAL_LL_EN_GET(x) (((uint32_t)(x) & PWMV2_CAL_CFG1_CAL_LL_EN_MASK) >> PWMV2_CAL_CFG1_CAL_LL_EN_SHIFT)
1286 
1287 /*
1288  * CAL_LIM_LO (RW)
1289  *
1290  * low limit offset selection, select from one of the shadow_val
1291  */
1292 #define PWMV2_CAL_CFG1_CAL_LIM_LO_MASK (0x1F00U)
1293 #define PWMV2_CAL_CFG1_CAL_LIM_LO_SHIFT (8U)
1294 #define PWMV2_CAL_CFG1_CAL_LIM_LO_SET(x) (((uint32_t)(x) << PWMV2_CAL_CFG1_CAL_LIM_LO_SHIFT) & PWMV2_CAL_CFG1_CAL_LIM_LO_MASK)
1295 #define PWMV2_CAL_CFG1_CAL_LIM_LO_GET(x) (((uint32_t)(x) & PWMV2_CAL_CFG1_CAL_LIM_LO_MASK) >> PWMV2_CAL_CFG1_CAL_LIM_LO_SHIFT)
1296 
1297 /*
1298  * CAL_IN_OFF (RW)
1299  *
1300  * offset for calculation unit, select from one of the shadow_val.
1301  */
1302 #define PWMV2_CAL_CFG1_CAL_IN_OFF_MASK (0x1FU)
1303 #define PWMV2_CAL_CFG1_CAL_IN_OFF_SHIFT (0U)
1304 #define PWMV2_CAL_CFG1_CAL_IN_OFF_SET(x) (((uint32_t)(x) << PWMV2_CAL_CFG1_CAL_IN_OFF_SHIFT) & PWMV2_CAL_CFG1_CAL_IN_OFF_MASK)
1305 #define PWMV2_CAL_CFG1_CAL_IN_OFF_GET(x) (((uint32_t)(x) & PWMV2_CAL_CFG1_CAL_IN_OFF_MASK) >> PWMV2_CAL_CFG1_CAL_IN_OFF_SHIFT)
1306 
1307 /* Bitfield definition for register of struct array CMP: CFG */
1308 /*
1309  * CMP_TRIG_SEL (RW)
1310  *
1311  * select one trigger from 8, should set to pulse in trig_mux
1312  */
1313 #define PWMV2_CMP_CFG_CMP_TRIG_SEL_MASK (0x70000000UL)
1314 #define PWMV2_CMP_CFG_CMP_TRIG_SEL_SHIFT (28U)
1315 #define PWMV2_CMP_CFG_CMP_TRIG_SEL_SET(x) (((uint32_t)(x) << PWMV2_CMP_CFG_CMP_TRIG_SEL_SHIFT) & PWMV2_CMP_CFG_CMP_TRIG_SEL_MASK)
1316 #define PWMV2_CMP_CFG_CMP_TRIG_SEL_GET(x) (((uint32_t)(x) & PWMV2_CMP_CFG_CMP_TRIG_SEL_MASK) >> PWMV2_CMP_CFG_CMP_TRIG_SEL_SHIFT)
1317 
1318 /*
1319  * CMP_UPDATE_TIME (RW)
1320  *
1321  * define when to use the shadow register value for working register(trig_cmp)
1322  * 000: software set work_ctrl1.shadow_lock bit
1323  * 001: update immediately(at next cycle)
1324  * 010: related counter reload time
1325  * 011: use cmp_update_trigger(from trig_mux, selected by cmp_trig_sel)
1326  * 100: use the related counter rld_cmp_sel0 to select one compare point
1327  * 101: use the related counter rld_cmp_sel1, to select one compare point
1328  * 11x: reserved, no update.
1329  */
1330 #define PWMV2_CMP_CFG_CMP_UPDATE_TIME_MASK (0x7000000UL)
1331 #define PWMV2_CMP_CFG_CMP_UPDATE_TIME_SHIFT (24U)
1332 #define PWMV2_CMP_CFG_CMP_UPDATE_TIME_SET(x) (((uint32_t)(x) << PWMV2_CMP_CFG_CMP_UPDATE_TIME_SHIFT) & PWMV2_CMP_CFG_CMP_UPDATE_TIME_MASK)
1333 #define PWMV2_CMP_CFG_CMP_UPDATE_TIME_GET(x) (((uint32_t)(x) & PWMV2_CMP_CFG_CMP_UPDATE_TIME_MASK) >> PWMV2_CMP_CFG_CMP_UPDATE_TIME_SHIFT)
1334 
1335 /*
1336  * CMP_IN_SEL (RW)
1337  *
1338  * 0x00~0x1B select one of the shadow_val directly
1339  * 0x20~0x2F select one of the calculation cell output
1340  * 0x30~0x37 select one of capture_pos value(low 8bit are 0)
1341  * 0x38+k select T/4
1342  * 0x3E select 0xFFFFF000
1343  * 0x3F select 0xFFFFFF00
1344  * others select 0
1345  */
1346 #define PWMV2_CMP_CFG_CMP_IN_SEL_MASK (0x3F0000UL)
1347 #define PWMV2_CMP_CFG_CMP_IN_SEL_SHIFT (16U)
1348 #define PWMV2_CMP_CFG_CMP_IN_SEL_SET(x) (((uint32_t)(x) << PWMV2_CMP_CFG_CMP_IN_SEL_SHIFT) & PWMV2_CMP_CFG_CMP_IN_SEL_MASK)
1349 #define PWMV2_CMP_CFG_CMP_IN_SEL_GET(x) (((uint32_t)(x) & PWMV2_CMP_CFG_CMP_IN_SEL_MASK) >> PWMV2_CMP_CFG_CMP_IN_SEL_SHIFT)
1350 
1351 /*
1352  * CMP_CNT (RW)
1353  *
1354  * select one from 4 counters, only for N>=16.
1355  * for N<16, this field is0, every 4 compare point related to one counter(0123 for counter0, 4567 for counter1….)
1356  */
1357 #define PWMV2_CMP_CFG_CMP_CNT_MASK (0xC000U)
1358 #define PWMV2_CMP_CFG_CMP_CNT_SHIFT (14U)
1359 #define PWMV2_CMP_CFG_CMP_CNT_SET(x) (((uint32_t)(x) << PWMV2_CMP_CFG_CMP_CNT_SHIFT) & PWMV2_CMP_CFG_CMP_CNT_MASK)
1360 #define PWMV2_CMP_CFG_CMP_CNT_GET(x) (((uint32_t)(x) & PWMV2_CMP_CFG_CMP_CNT_MASK) >> PWMV2_CMP_CFG_CMP_CNT_SHIFT)
1361 
1362 
1363 
1364 /* SHADOW_VAL register group index macro definition */
1365 #define PWMV2_SHADOW_VAL_0 (0UL)
1366 #define PWMV2_SHADOW_VAL_1 (1UL)
1367 #define PWMV2_SHADOW_VAL_2 (2UL)
1368 #define PWMV2_SHADOW_VAL_3 (3UL)
1369 #define PWMV2_SHADOW_VAL_4 (4UL)
1370 #define PWMV2_SHADOW_VAL_5 (5UL)
1371 #define PWMV2_SHADOW_VAL_6 (6UL)
1372 #define PWMV2_SHADOW_VAL_7 (7UL)
1373 #define PWMV2_SHADOW_VAL_8 (8UL)
1374 #define PWMV2_SHADOW_VAL_9 (9UL)
1375 #define PWMV2_SHADOW_VAL_10 (10UL)
1376 #define PWMV2_SHADOW_VAL_11 (11UL)
1377 #define PWMV2_SHADOW_VAL_12 (12UL)
1378 #define PWMV2_SHADOW_VAL_13 (13UL)
1379 #define PWMV2_SHADOW_VAL_14 (14UL)
1380 #define PWMV2_SHADOW_VAL_15 (15UL)
1381 #define PWMV2_SHADOW_VAL_16 (16UL)
1382 #define PWMV2_SHADOW_VAL_17 (17UL)
1383 #define PWMV2_SHADOW_VAL_18 (18UL)
1384 #define PWMV2_SHADOW_VAL_19 (19UL)
1385 #define PWMV2_SHADOW_VAL_20 (20UL)
1386 #define PWMV2_SHADOW_VAL_21 (21UL)
1387 #define PWMV2_SHADOW_VAL_22 (22UL)
1388 #define PWMV2_SHADOW_VAL_23 (23UL)
1389 #define PWMV2_SHADOW_VAL_24 (24UL)
1390 #define PWMV2_SHADOW_VAL_25 (25UL)
1391 #define PWMV2_SHADOW_VAL_26 (26UL)
1392 #define PWMV2_SHADOW_VAL_27 (27UL)
1393 
1394 /* PWM register group index macro definition */
1395 #define PWMV2_PWM_0 (0UL)
1396 #define PWMV2_PWM_1 (1UL)
1397 #define PWMV2_PWM_2 (2UL)
1398 #define PWMV2_PWM_3 (3UL)
1399 #define PWMV2_PWM_4 (4UL)
1400 #define PWMV2_PWM_5 (5UL)
1401 #define PWMV2_PWM_6 (6UL)
1402 #define PWMV2_PWM_7 (7UL)
1403 
1404 /* TRIGGER_CFG register group index macro definition */
1405 #define PWMV2_TRIGGER_CFG_0 (0UL)
1406 #define PWMV2_TRIGGER_CFG_1 (1UL)
1407 #define PWMV2_TRIGGER_CFG_2 (2UL)
1408 #define PWMV2_TRIGGER_CFG_3 (3UL)
1409 #define PWMV2_TRIGGER_CFG_4 (4UL)
1410 #define PWMV2_TRIGGER_CFG_5 (5UL)
1411 #define PWMV2_TRIGGER_CFG_6 (6UL)
1412 #define PWMV2_TRIGGER_CFG_7 (7UL)
1413 
1414 /* CNT_RELOAD_WORK register group index macro definition */
1415 #define PWMV2_CNT_RELOAD_WORK_0 (0UL)
1416 #define PWMV2_CNT_RELOAD_WORK_1 (1UL)
1417 #define PWMV2_CNT_RELOAD_WORK_2 (2UL)
1418 #define PWMV2_CNT_RELOAD_WORK_3 (3UL)
1419 
1420 /* CMP_VAL_WORK register group index macro definition */
1421 #define PWMV2_CMP_VAL_WORK_0 (0UL)
1422 #define PWMV2_CMP_VAL_WORK_1 (1UL)
1423 #define PWMV2_CMP_VAL_WORK_2 (2UL)
1424 #define PWMV2_CMP_VAL_WORK_3 (3UL)
1425 #define PWMV2_CMP_VAL_WORK_4 (4UL)
1426 #define PWMV2_CMP_VAL_WORK_5 (5UL)
1427 #define PWMV2_CMP_VAL_WORK_6 (6UL)
1428 #define PWMV2_CMP_VAL_WORK_7 (7UL)
1429 #define PWMV2_CMP_VAL_WORK_8 (8UL)
1430 #define PWMV2_CMP_VAL_WORK_9 (9UL)
1431 #define PWMV2_CMP_VAL_WORK_10 (10UL)
1432 #define PWMV2_CMP_VAL_WORK_11 (11UL)
1433 #define PWMV2_CMP_VAL_WORK_12 (12UL)
1434 #define PWMV2_CMP_VAL_WORK_13 (13UL)
1435 #define PWMV2_CMP_VAL_WORK_14 (14UL)
1436 #define PWMV2_CMP_VAL_WORK_15 (15UL)
1437 #define PWMV2_CMP_VAL_WORK_16 (16UL)
1438 #define PWMV2_CMP_VAL_WORK_17 (17UL)
1439 #define PWMV2_CMP_VAL_WORK_18 (18UL)
1440 #define PWMV2_CMP_VAL_WORK_19 (19UL)
1441 #define PWMV2_CMP_VAL_WORK_20 (20UL)
1442 #define PWMV2_CMP_VAL_WORK_21 (21UL)
1443 #define PWMV2_CMP_VAL_WORK_22 (22UL)
1444 #define PWMV2_CMP_VAL_WORK_23 (23UL)
1445 
1446 /* CNT_VAL register group index macro definition */
1447 #define PWMV2_CNT_VAL_0 (0UL)
1448 #define PWMV2_CNT_VAL_1 (1UL)
1449 #define PWMV2_CNT_VAL_2 (2UL)
1450 #define PWMV2_CNT_VAL_3 (3UL)
1451 
1452 /* DAC_VALUE_SV register group index macro definition */
1453 #define PWMV2_DAC_VALUE_SV_0 (0UL)
1454 #define PWMV2_DAC_VALUE_SV_1 (1UL)
1455 #define PWMV2_DAC_VALUE_SV_2 (2UL)
1456 #define PWMV2_DAC_VALUE_SV_3 (3UL)
1457 
1458 /* CAPTURE_POS register group index macro definition */
1459 #define PWMV2_CAPTURE_POS_0 (0UL)
1460 #define PWMV2_CAPTURE_POS_1 (1UL)
1461 #define PWMV2_CAPTURE_POS_2 (2UL)
1462 #define PWMV2_CAPTURE_POS_3 (3UL)
1463 #define PWMV2_CAPTURE_POS_4 (4UL)
1464 #define PWMV2_CAPTURE_POS_5 (5UL)
1465 #define PWMV2_CAPTURE_POS_6 (6UL)
1466 #define PWMV2_CAPTURE_POS_7 (7UL)
1467 
1468 /* CAPTURE_NEG register group index macro definition */
1469 #define PWMV2_CAPTURE_NEG_0 (0UL)
1470 #define PWMV2_CAPTURE_NEG_1 (1UL)
1471 #define PWMV2_CAPTURE_NEG_2 (2UL)
1472 #define PWMV2_CAPTURE_NEG_3 (3UL)
1473 #define PWMV2_CAPTURE_NEG_4 (4UL)
1474 #define PWMV2_CAPTURE_NEG_5 (5UL)
1475 #define PWMV2_CAPTURE_NEG_6 (6UL)
1476 #define PWMV2_CAPTURE_NEG_7 (7UL)
1477 
1478 /* CNT register group index macro definition */
1479 #define PWMV2_CNT_0 (0UL)
1480 #define PWMV2_CNT_1 (1UL)
1481 #define PWMV2_CNT_2 (2UL)
1482 #define PWMV2_CNT_3 (3UL)
1483 
1484 /* CAL register group index macro definition */
1485 #define PWMV2_CAL_0 (0UL)
1486 #define PWMV2_CAL_1 (1UL)
1487 #define PWMV2_CAL_2 (2UL)
1488 #define PWMV2_CAL_3 (3UL)
1489 #define PWMV2_CAL_4 (4UL)
1490 #define PWMV2_CAL_5 (5UL)
1491 #define PWMV2_CAL_6 (6UL)
1492 #define PWMV2_CAL_7 (7UL)
1493 #define PWMV2_CAL_8 (8UL)
1494 #define PWMV2_CAL_9 (9UL)
1495 #define PWMV2_CAL_10 (10UL)
1496 #define PWMV2_CAL_11 (11UL)
1497 #define PWMV2_CAL_12 (12UL)
1498 #define PWMV2_CAL_13 (13UL)
1499 #define PWMV2_CAL_14 (14UL)
1500 #define PWMV2_CAL_15 (15UL)
1501 
1502 /* CMP register group index macro definition */
1503 #define PWMV2_CMP_0 (0UL)
1504 #define PWMV2_CMP_1 (1UL)
1505 #define PWMV2_CMP_2 (2UL)
1506 #define PWMV2_CMP_3 (3UL)
1507 #define PWMV2_CMP_4 (4UL)
1508 #define PWMV2_CMP_5 (5UL)
1509 #define PWMV2_CMP_6 (6UL)
1510 #define PWMV2_CMP_7 (7UL)
1511 #define PWMV2_CMP_8 (8UL)
1512 #define PWMV2_CMP_9 (9UL)
1513 #define PWMV2_CMP_10 (10UL)
1514 #define PWMV2_CMP_11 (11UL)
1515 #define PWMV2_CMP_12 (12UL)
1516 #define PWMV2_CMP_13 (13UL)
1517 #define PWMV2_CMP_14 (14UL)
1518 #define PWMV2_CMP_15 (15UL)
1519 #define PWMV2_CMP_16 (16UL)
1520 #define PWMV2_CMP_17 (17UL)
1521 #define PWMV2_CMP_18 (18UL)
1522 #define PWMV2_CMP_19 (19UL)
1523 #define PWMV2_CMP_20 (20UL)
1524 #define PWMV2_CMP_21 (21UL)
1525 #define PWMV2_CMP_22 (22UL)
1526 #define PWMV2_CMP_23 (23UL)
1527 
1528 
1529 #endif /* HPM_PWMV2_H */
PWMV2_Type
Definition: hpm_pwmv2_regs.h:12