HPM SDK
HPMicro Software Development Kit
hpm_qeiv2_regs.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_QEIV2_H
10 #define HPM_QEIV2_H
11 
12 typedef struct {
13  __RW uint32_t CR; /* 0x0: Control register */
14  __RW uint32_t PHCFG; /* 0x4: Phase configure register */
15  __RW uint32_t WDGCFG; /* 0x8: Watchdog configure register */
16  __RW uint32_t PHIDX; /* 0xC: Phase index register */
17  __RW uint32_t TRGOEN; /* 0x10: Tigger output enable register */
18  __RW uint32_t READEN; /* 0x14: Read event enable register */
19  __RW uint32_t ZCMP; /* 0x18: Z comparator */
20  __RW uint32_t PHCMP; /* 0x1C: Phase comparator */
21  __RW uint32_t SPDCMP; /* 0x20: Speed comparator */
22  __RW uint32_t DMAEN; /* 0x24: DMA request enable register */
23  __RW uint32_t SR; /* 0x28: Status register */
24  __RW uint32_t IRQEN; /* 0x2C: Interrupt request register */
25  struct {
26  __RW uint32_t Z; /* 0x30: Z counter */
27  __R uint32_t PH; /* 0x34: Phase counter */
28  __RW uint32_t SPD; /* 0x38: Speed counter */
29  __R uint32_t TMR; /* 0x3C: Timer counter */
30  } COUNT[4];
31  __R uint8_t RESERVED0[16]; /* 0x70 - 0x7F: Reserved */
32  __RW uint32_t ZCMP2; /* 0x80: Z comparator */
33  __RW uint32_t PHCMP2; /* 0x84: Phase comparator */
34  __RW uint32_t SPDCMP2; /* 0x88: Speed comparator */
35  __RW uint32_t MATCH_CFG; /* 0x8C: */
36  __RW uint32_t FILT_CFG[6]; /* 0x90 - 0xA4: A signal filter config */
37  __R uint8_t RESERVED1[88]; /* 0xA8 - 0xFF: Reserved */
38  __RW uint32_t QEI_CFG; /* 0x100: qei config register */
39  __R uint8_t RESERVED2[12]; /* 0x104 - 0x10F: Reserved */
40  __RW uint32_t PULSE0_NUM; /* 0x110: pulse0_num */
41  __RW uint32_t PULSE1_NUM; /* 0x114: pulse1_num */
42  __R uint32_t CYCLE0_CNT; /* 0x118: cycle0_cnt */
43  __R uint32_t CYCLE0PULSE_CNT; /* 0x11C: cycle0pulse_cnt */
44  __R uint32_t CYCLE1_CNT; /* 0x120: cycle1_cnt */
45  __R uint32_t CYCLE1PULSE_CNT; /* 0x124: cycle1pulse_cnt */
46  __R uint32_t CYCLE0_SNAP0; /* 0x128: cycle0_snap0 */
47  __R uint32_t CYCLE0_SNAP1; /* 0x12C: cycle0_snap1 */
48  __R uint32_t CYCLE1_SNAP0; /* 0x130: cycle1_snap0 */
49  __R uint32_t CYCLE1_SNAP1; /* 0x134: cycle1_snap1 */
50  __R uint8_t RESERVED3[8]; /* 0x138 - 0x13F: Reserved */
51  __RW uint32_t CYCLE0_NUM; /* 0x140: cycle0_num */
52  __RW uint32_t CYCLE1_NUM; /* 0x144: cycle1_num */
53  __R uint32_t PULSE0_CNT; /* 0x148: pulse0_cnt */
54  __R uint32_t PULSE0CYCLE_CNT; /* 0x14C: pulse0cycle_cnt */
55  __R uint32_t PULSE1_CNT; /* 0x150: pulse1_cnt */
56  __R uint32_t PULSE1CYCLE_CNT; /* 0x154: pulse1cycle_cnt */
57  __R uint32_t PULSE0_SNAP0; /* 0x158: pulse0_snap0 */
58  __R uint32_t PULSE0CYCLE_SNAP0; /* 0x15C: pulse0cycle_snap0 */
59  __R uint32_t PULSE0_SNAP1; /* 0x160: pulse0_snap1 */
60  __R uint32_t PULSE0CYCLE_SNAP1; /* 0x164: pulse0cycle_snap1 */
61  __R uint32_t PULSE1_SNAP0; /* 0x168: pulse1_snap0 */
62  __R uint32_t PULSE1CYCLE_SNAP0; /* 0x16C: pulse1cycle_snap0 */
63  __R uint32_t PULSE1_SNAP1; /* 0x170: pulse1_snap1 */
64  __R uint32_t PULSE1CYCLE_SNAP1; /* 0x174: pulse1cycle_snap1 */
65  __R uint8_t RESERVED4[104]; /* 0x178 - 0x1DF: Reserved */
66  __R uint32_t TIMESTAMP; /* 0x1E0: timestamp */
67  __R uint8_t RESERVED5[12]; /* 0x1E4 - 0x1EF: Reserved */
68  __RW uint32_t ADC_THRESHOLD; /* 0x1F0: adc_threshold */
69  __R uint8_t RESERVED6[12]; /* 0x1F4 - 0x1FF: Reserved */
70  __RW uint32_t ADCX_CFG0; /* 0x200: adcx_cfg0 */
71  __RW uint32_t ADCX_CFG1; /* 0x204: adcx_cfg1 */
72  __RW uint32_t ADCX_CFG2; /* 0x208: adcx_cfg2 */
73  __R uint8_t RESERVED7[4]; /* 0x20C - 0x20F: Reserved */
74  __RW uint32_t ADCY_CFG0; /* 0x210: adcy_cfg0 */
75  __RW uint32_t ADCY_CFG1; /* 0x214: adcy_cfg1 */
76  __RW uint32_t ADCY_CFG2; /* 0x218: adcy_cfg2 */
77  __R uint8_t RESERVED8[4]; /* 0x21C - 0x21F: Reserved */
78  __RW uint32_t CAL_CFG; /* 0x220: cal_cfg */
79  __R uint8_t RESERVED9[12]; /* 0x224 - 0x22F: Reserved */
80  __RW uint32_t PHASE_PARAM; /* 0x230: phase_param */
81  __R uint8_t RESERVED10[4]; /* 0x234 - 0x237: Reserved */
82  __RW uint32_t POS_THRESHOLD; /* 0x238: pos_threshold */
83  __R uint8_t RESERVED11[4]; /* 0x23C - 0x23F: Reserved */
84  __RW uint32_t UVW_POS[6]; /* 0x240 - 0x254: uvw_pos0 */
85  __RW uint32_t UVW_POS_CFG[6]; /* 0x258 - 0x26C: uvw_pos0_cfg */
86  __R uint8_t RESERVED12[16]; /* 0x270 - 0x27F: Reserved */
87  __RW uint32_t PHASE_CNT; /* 0x280: phase_cnt */
88  __W uint32_t PHASE_UPDATE; /* 0x284: phase_update */
89  __RW uint32_t POSITION; /* 0x288: position */
90  __W uint32_t POSITION_UPDATE; /* 0x28C: position_update */
91  __R uint32_t ANGLE; /* 0x290: angle */
92  __RW uint32_t POS_TIMEOUT; /* 0x294: pos_timeout */
93  __R uint8_t RESERVED13[40]; /* 0x298 - 0x2BF: Reserved */
94  __RW uint32_t TOGI_CFG0; /* 0x2C0: togi_cfg0 */
95  __RW uint32_t TOGI_CFG1; /* 0x2C4: togi_cfg1 */
96  __R uint8_t RESERVED14[8]; /* 0x2C8 - 0x2CF: Reserved */
97  __R uint32_t SINP_ACC; /* 0x2D0: sinp_acc */
98  __R uint32_t SINN_ACC; /* 0x2D4: sinn_acc */
99  __R uint32_t COSP_ACC; /* 0x2D8: cosp_acc */
100  __R uint32_t COSN_ACC; /* 0x2DC: cosn_acc */
101 } QEIV2_Type;
102 
103 
104 /* Bitfield definition for register: CR */
105 /*
106  * READ (WO)
107  *
108  * 1- load phcnt, zcnt, spdcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0
109  */
110 #define QEIV2_CR_READ_MASK (0x80000000UL)
111 #define QEIV2_CR_READ_SHIFT (31U)
112 #define QEIV2_CR_READ_SET(x) (((uint32_t)(x) << QEIV2_CR_READ_SHIFT) & QEIV2_CR_READ_MASK)
113 #define QEIV2_CR_READ_GET(x) (((uint32_t)(x) & QEIV2_CR_READ_MASK) >> QEIV2_CR_READ_SHIFT)
114 
115 /*
116  * ZCNTCFG (RW)
117  *
118  * 1- zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0
119  * 0- zcnt will increment or decrement when Z input assert
120  */
121 #define QEIV2_CR_ZCNTCFG_MASK (0x400000UL)
122 #define QEIV2_CR_ZCNTCFG_SHIFT (22U)
123 #define QEIV2_CR_ZCNTCFG_SET(x) (((uint32_t)(x) << QEIV2_CR_ZCNTCFG_SHIFT) & QEIV2_CR_ZCNTCFG_MASK)
124 #define QEIV2_CR_ZCNTCFG_GET(x) (((uint32_t)(x) & QEIV2_CR_ZCNTCFG_MASK) >> QEIV2_CR_ZCNTCFG_SHIFT)
125 
126 /*
127  * PHCALIZ (RW)
128  *
129  * 1- phcnt will set to phidx when Z input assert(for abz digital signsl)
130  */
131 #define QEIV2_CR_PHCALIZ_MASK (0x200000UL)
132 #define QEIV2_CR_PHCALIZ_SHIFT (21U)
133 #define QEIV2_CR_PHCALIZ_SET(x) (((uint32_t)(x) << QEIV2_CR_PHCALIZ_SHIFT) & QEIV2_CR_PHCALIZ_MASK)
134 #define QEIV2_CR_PHCALIZ_GET(x) (((uint32_t)(x) & QEIV2_CR_PHCALIZ_MASK) >> QEIV2_CR_PHCALIZ_SHIFT)
135 
136 /*
137  * Z_ONLY_EN (RW)
138  *
139  * 1- phcnt will set to phidx when Z input assert(for xy analog signal and digital z, also need set phcaliz)
140  */
141 #define QEIV2_CR_Z_ONLY_EN_MASK (0x100000UL)
142 #define QEIV2_CR_Z_ONLY_EN_SHIFT (20U)
143 #define QEIV2_CR_Z_ONLY_EN_SET(x) (((uint32_t)(x) << QEIV2_CR_Z_ONLY_EN_SHIFT) & QEIV2_CR_Z_ONLY_EN_MASK)
144 #define QEIV2_CR_Z_ONLY_EN_GET(x) (((uint32_t)(x) & QEIV2_CR_Z_ONLY_EN_MASK) >> QEIV2_CR_Z_ONLY_EN_SHIFT)
145 
146 /*
147  * H2FDIR0 (RW)
148  *
149  */
150 #define QEIV2_CR_H2FDIR0_MASK (0x80000UL)
151 #define QEIV2_CR_H2FDIR0_SHIFT (19U)
152 #define QEIV2_CR_H2FDIR0_SET(x) (((uint32_t)(x) << QEIV2_CR_H2FDIR0_SHIFT) & QEIV2_CR_H2FDIR0_MASK)
153 #define QEIV2_CR_H2FDIR0_GET(x) (((uint32_t)(x) & QEIV2_CR_H2FDIR0_MASK) >> QEIV2_CR_H2FDIR0_SHIFT)
154 
155 /*
156  * H2FDIR1 (RW)
157  *
158  */
159 #define QEIV2_CR_H2FDIR1_MASK (0x40000UL)
160 #define QEIV2_CR_H2FDIR1_SHIFT (18U)
161 #define QEIV2_CR_H2FDIR1_SET(x) (((uint32_t)(x) << QEIV2_CR_H2FDIR1_SHIFT) & QEIV2_CR_H2FDIR1_MASK)
162 #define QEIV2_CR_H2FDIR1_GET(x) (((uint32_t)(x) & QEIV2_CR_H2FDIR1_MASK) >> QEIV2_CR_H2FDIR1_SHIFT)
163 
164 /*
165  * H2RDIR0 (RW)
166  *
167  */
168 #define QEIV2_CR_H2RDIR0_MASK (0x20000UL)
169 #define QEIV2_CR_H2RDIR0_SHIFT (17U)
170 #define QEIV2_CR_H2RDIR0_SET(x) (((uint32_t)(x) << QEIV2_CR_H2RDIR0_SHIFT) & QEIV2_CR_H2RDIR0_MASK)
171 #define QEIV2_CR_H2RDIR0_GET(x) (((uint32_t)(x) & QEIV2_CR_H2RDIR0_MASK) >> QEIV2_CR_H2RDIR0_SHIFT)
172 
173 /*
174  * H2RDIR1 (RW)
175  *
176  */
177 #define QEIV2_CR_H2RDIR1_MASK (0x10000UL)
178 #define QEIV2_CR_H2RDIR1_SHIFT (16U)
179 #define QEIV2_CR_H2RDIR1_SET(x) (((uint32_t)(x) << QEIV2_CR_H2RDIR1_SHIFT) & QEIV2_CR_H2RDIR1_MASK)
180 #define QEIV2_CR_H2RDIR1_GET(x) (((uint32_t)(x) & QEIV2_CR_H2RDIR1_MASK) >> QEIV2_CR_H2RDIR1_SHIFT)
181 
182 /*
183  * PAUSEPOS (RW)
184  *
185  * 1- pause position output valid when PAUSE assert
186  */
187 #define QEIV2_CR_PAUSEPOS_MASK (0x8000U)
188 #define QEIV2_CR_PAUSEPOS_SHIFT (15U)
189 #define QEIV2_CR_PAUSEPOS_SET(x) (((uint32_t)(x) << QEIV2_CR_PAUSEPOS_SHIFT) & QEIV2_CR_PAUSEPOS_MASK)
190 #define QEIV2_CR_PAUSEPOS_GET(x) (((uint32_t)(x) & QEIV2_CR_PAUSEPOS_MASK) >> QEIV2_CR_PAUSEPOS_SHIFT)
191 
192 /*
193  * PAUSESPD (RW)
194  *
195  * 1- pause spdcnt when PAUSE assert
196  */
197 #define QEIV2_CR_PAUSESPD_MASK (0x4000U)
198 #define QEIV2_CR_PAUSESPD_SHIFT (14U)
199 #define QEIV2_CR_PAUSESPD_SET(x) (((uint32_t)(x) << QEIV2_CR_PAUSESPD_SHIFT) & QEIV2_CR_PAUSESPD_MASK)
200 #define QEIV2_CR_PAUSESPD_GET(x) (((uint32_t)(x) & QEIV2_CR_PAUSESPD_MASK) >> QEIV2_CR_PAUSESPD_SHIFT)
201 
202 /*
203  * PAUSEPH (RW)
204  *
205  * 1- pause phcnt when PAUSE assert
206  */
207 #define QEIV2_CR_PAUSEPH_MASK (0x2000U)
208 #define QEIV2_CR_PAUSEPH_SHIFT (13U)
209 #define QEIV2_CR_PAUSEPH_SET(x) (((uint32_t)(x) << QEIV2_CR_PAUSEPH_SHIFT) & QEIV2_CR_PAUSEPH_MASK)
210 #define QEIV2_CR_PAUSEPH_GET(x) (((uint32_t)(x) & QEIV2_CR_PAUSEPH_MASK) >> QEIV2_CR_PAUSEPH_SHIFT)
211 
212 /*
213  * PAUSEZ (RW)
214  *
215  * 1- pause zcnt when PAUSE assert
216  */
217 #define QEIV2_CR_PAUSEZ_MASK (0x1000U)
218 #define QEIV2_CR_PAUSEZ_SHIFT (12U)
219 #define QEIV2_CR_PAUSEZ_SET(x) (((uint32_t)(x) << QEIV2_CR_PAUSEZ_SHIFT) & QEIV2_CR_PAUSEZ_MASK)
220 #define QEIV2_CR_PAUSEZ_GET(x) (((uint32_t)(x) & QEIV2_CR_PAUSEZ_MASK) >> QEIV2_CR_PAUSEZ_SHIFT)
221 
222 /*
223  * HFDIR0 (RW)
224  *
225  * 1- HOMEF will set at H rising edge when dir == 1 (negative rotation direction)
226  */
227 #define QEIV2_CR_HFDIR0_MASK (0x800U)
228 #define QEIV2_CR_HFDIR0_SHIFT (11U)
229 #define QEIV2_CR_HFDIR0_SET(x) (((uint32_t)(x) << QEIV2_CR_HFDIR0_SHIFT) & QEIV2_CR_HFDIR0_MASK)
230 #define QEIV2_CR_HFDIR0_GET(x) (((uint32_t)(x) & QEIV2_CR_HFDIR0_MASK) >> QEIV2_CR_HFDIR0_SHIFT)
231 
232 /*
233  * HFDIR1 (RW)
234  *
235  * 1- HOMEF will set at H rising edge when dir == 0 (positive rotation direction)
236  */
237 #define QEIV2_CR_HFDIR1_MASK (0x400U)
238 #define QEIV2_CR_HFDIR1_SHIFT (10U)
239 #define QEIV2_CR_HFDIR1_SET(x) (((uint32_t)(x) << QEIV2_CR_HFDIR1_SHIFT) & QEIV2_CR_HFDIR1_MASK)
240 #define QEIV2_CR_HFDIR1_GET(x) (((uint32_t)(x) & QEIV2_CR_HFDIR1_MASK) >> QEIV2_CR_HFDIR1_SHIFT)
241 
242 /*
243  * HRDIR0 (RW)
244  *
245  * 1- HOMEF will set at H falling edge when dir == 1 (negative rotation direction)
246  */
247 #define QEIV2_CR_HRDIR0_MASK (0x200U)
248 #define QEIV2_CR_HRDIR0_SHIFT (9U)
249 #define QEIV2_CR_HRDIR0_SET(x) (((uint32_t)(x) << QEIV2_CR_HRDIR0_SHIFT) & QEIV2_CR_HRDIR0_MASK)
250 #define QEIV2_CR_HRDIR0_GET(x) (((uint32_t)(x) & QEIV2_CR_HRDIR0_MASK) >> QEIV2_CR_HRDIR0_SHIFT)
251 
252 /*
253  * HRDIR1 (RW)
254  *
255  * 1- HOMEF will set at H falling edge when dir == 1 (positive rotation direction)
256  */
257 #define QEIV2_CR_HRDIR1_MASK (0x100U)
258 #define QEIV2_CR_HRDIR1_SHIFT (8U)
259 #define QEIV2_CR_HRDIR1_SET(x) (((uint32_t)(x) << QEIV2_CR_HRDIR1_SHIFT) & QEIV2_CR_HRDIR1_MASK)
260 #define QEIV2_CR_HRDIR1_GET(x) (((uint32_t)(x) & QEIV2_CR_HRDIR1_MASK) >> QEIV2_CR_HRDIR1_SHIFT)
261 
262 /*
263  * FAULTPOS (RW)
264  *
265  */
266 #define QEIV2_CR_FAULTPOS_MASK (0x40U)
267 #define QEIV2_CR_FAULTPOS_SHIFT (6U)
268 #define QEIV2_CR_FAULTPOS_SET(x) (((uint32_t)(x) << QEIV2_CR_FAULTPOS_SHIFT) & QEIV2_CR_FAULTPOS_MASK)
269 #define QEIV2_CR_FAULTPOS_GET(x) (((uint32_t)(x) & QEIV2_CR_FAULTPOS_MASK) >> QEIV2_CR_FAULTPOS_SHIFT)
270 
271 /*
272  * SNAPEN (RW)
273  *
274  * 1- load phcnt, zcnt, spdcnt and tmrcnt into their snap registers when snapi input assert
275  */
276 #define QEIV2_CR_SNAPEN_MASK (0x20U)
277 #define QEIV2_CR_SNAPEN_SHIFT (5U)
278 #define QEIV2_CR_SNAPEN_SET(x) (((uint32_t)(x) << QEIV2_CR_SNAPEN_SHIFT) & QEIV2_CR_SNAPEN_MASK)
279 #define QEIV2_CR_SNAPEN_GET(x) (((uint32_t)(x) & QEIV2_CR_SNAPEN_MASK) >> QEIV2_CR_SNAPEN_SHIFT)
280 
281 /*
282  * RSTCNT (RW)
283  *
284  * 1- reset zcnt, spdcnt and tmrcnt to 0. reset phcnt to phidx
285  */
286 #define QEIV2_CR_RSTCNT_MASK (0x10U)
287 #define QEIV2_CR_RSTCNT_SHIFT (4U)
288 #define QEIV2_CR_RSTCNT_SET(x) (((uint32_t)(x) << QEIV2_CR_RSTCNT_SHIFT) & QEIV2_CR_RSTCNT_MASK)
289 #define QEIV2_CR_RSTCNT_GET(x) (((uint32_t)(x) & QEIV2_CR_RSTCNT_MASK) >> QEIV2_CR_RSTCNT_SHIFT)
290 
291 /*
292  * RD_SEL (RW)
293  *
294  * define the width/counter value(affect width_match, width_match2, width_cur, timer_cur, width_read, timer_read,
295  * width_snap0,width_snap1, timer_snap0, timer_snap1)
296  * 0 : same as hpm1000/500/500s;
297  * 1: use width for position; use timer for angle
298  */
299 #define QEIV2_CR_RD_SEL_MASK (0x8U)
300 #define QEIV2_CR_RD_SEL_SHIFT (3U)
301 #define QEIV2_CR_RD_SEL_SET(x) (((uint32_t)(x) << QEIV2_CR_RD_SEL_SHIFT) & QEIV2_CR_RD_SEL_MASK)
302 #define QEIV2_CR_RD_SEL_GET(x) (((uint32_t)(x) & QEIV2_CR_RD_SEL_MASK) >> QEIV2_CR_RD_SEL_SHIFT)
303 
304 /*
305  * ENCTYP (RW)
306  *
307  * 000-abz; 001-pd; 010-ud; 011-UVW(hal)
308  * 100-single A; 101-single sin; 110: sin&cos
309  */
310 #define QEIV2_CR_ENCTYP_MASK (0x7U)
311 #define QEIV2_CR_ENCTYP_SHIFT (0U)
312 #define QEIV2_CR_ENCTYP_SET(x) (((uint32_t)(x) << QEIV2_CR_ENCTYP_SHIFT) & QEIV2_CR_ENCTYP_MASK)
313 #define QEIV2_CR_ENCTYP_GET(x) (((uint32_t)(x) & QEIV2_CR_ENCTYP_MASK) >> QEIV2_CR_ENCTYP_SHIFT)
314 
315 /* Bitfield definition for register: PHCFG */
316 /*
317  * PHMAX (RW)
318  *
319  * maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax
320  */
321 #define QEIV2_PHCFG_PHMAX_MASK (0xFFFFFFFFUL)
322 #define QEIV2_PHCFG_PHMAX_SHIFT (0U)
323 #define QEIV2_PHCFG_PHMAX_SET(x) (((uint32_t)(x) << QEIV2_PHCFG_PHMAX_SHIFT) & QEIV2_PHCFG_PHMAX_MASK)
324 #define QEIV2_PHCFG_PHMAX_GET(x) (((uint32_t)(x) & QEIV2_PHCFG_PHMAX_MASK) >> QEIV2_PHCFG_PHMAX_SHIFT)
325 
326 /* Bitfield definition for register: WDGCFG */
327 /*
328  * WDGEN (RW)
329  *
330  * 1- enable wdog counter
331  */
332 #define QEIV2_WDGCFG_WDGEN_MASK (0x80000000UL)
333 #define QEIV2_WDGCFG_WDGEN_SHIFT (31U)
334 #define QEIV2_WDGCFG_WDGEN_SET(x) (((uint32_t)(x) << QEIV2_WDGCFG_WDGEN_SHIFT) & QEIV2_WDGCFG_WDGEN_MASK)
335 #define QEIV2_WDGCFG_WDGEN_GET(x) (((uint32_t)(x) & QEIV2_WDGCFG_WDGEN_MASK) >> QEIV2_WDGCFG_WDGEN_SHIFT)
336 
337 /*
338  * WDOG_CFG (RW)
339  *
340  * define as stop if phase_cnt change is less than it
341  * if 0, then each change of phase_cnt will clear wdog counter;
342  * if 2, then phase_cnt change larger than 2 will clear wdog counter
343  */
344 #define QEIV2_WDGCFG_WDOG_CFG_MASK (0x70000000UL)
345 #define QEIV2_WDGCFG_WDOG_CFG_SHIFT (28U)
346 #define QEIV2_WDGCFG_WDOG_CFG_SET(x) (((uint32_t)(x) << QEIV2_WDGCFG_WDOG_CFG_SHIFT) & QEIV2_WDGCFG_WDOG_CFG_MASK)
347 #define QEIV2_WDGCFG_WDOG_CFG_GET(x) (((uint32_t)(x) & QEIV2_WDGCFG_WDOG_CFG_MASK) >> QEIV2_WDGCFG_WDOG_CFG_SHIFT)
348 
349 /*
350  * WDGTO (RW)
351  *
352  * watch dog timeout value
353  */
354 #define QEIV2_WDGCFG_WDGTO_MASK (0xFFFFFFFUL)
355 #define QEIV2_WDGCFG_WDGTO_SHIFT (0U)
356 #define QEIV2_WDGCFG_WDGTO_SET(x) (((uint32_t)(x) << QEIV2_WDGCFG_WDGTO_SHIFT) & QEIV2_WDGCFG_WDGTO_MASK)
357 #define QEIV2_WDGCFG_WDGTO_GET(x) (((uint32_t)(x) & QEIV2_WDGCFG_WDGTO_MASK) >> QEIV2_WDGCFG_WDGTO_SHIFT)
358 
359 /* Bitfield definition for register: PHIDX */
360 /*
361  * PHIDX (RW)
362  *
363  * phcnt reset value, phcnt will reset to phidx when phcaliz set to 1
364  */
365 #define QEIV2_PHIDX_PHIDX_MASK (0xFFFFFFFFUL)
366 #define QEIV2_PHIDX_PHIDX_SHIFT (0U)
367 #define QEIV2_PHIDX_PHIDX_SET(x) (((uint32_t)(x) << QEIV2_PHIDX_PHIDX_SHIFT) & QEIV2_PHIDX_PHIDX_MASK)
368 #define QEIV2_PHIDX_PHIDX_GET(x) (((uint32_t)(x) & QEIV2_PHIDX_PHIDX_MASK) >> QEIV2_PHIDX_PHIDX_SHIFT)
369 
370 /* Bitfield definition for register: TRGOEN */
371 /*
372  * WDGFEN (RW)
373  *
374  * 1- enable trigger output when wdg flag set
375  */
376 #define QEIV2_TRGOEN_WDGFEN_MASK (0x80000000UL)
377 #define QEIV2_TRGOEN_WDGFEN_SHIFT (31U)
378 #define QEIV2_TRGOEN_WDGFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_WDGFEN_SHIFT) & QEIV2_TRGOEN_WDGFEN_MASK)
379 #define QEIV2_TRGOEN_WDGFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_WDGFEN_MASK) >> QEIV2_TRGOEN_WDGFEN_SHIFT)
380 
381 /*
382  * HOMEFEN (RW)
383  *
384  * 1- enable trigger output when homef flag set
385  */
386 #define QEIV2_TRGOEN_HOMEFEN_MASK (0x40000000UL)
387 #define QEIV2_TRGOEN_HOMEFEN_SHIFT (30U)
388 #define QEIV2_TRGOEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_HOMEFEN_SHIFT) & QEIV2_TRGOEN_HOMEFEN_MASK)
389 #define QEIV2_TRGOEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_HOMEFEN_MASK) >> QEIV2_TRGOEN_HOMEFEN_SHIFT)
390 
391 /*
392  * POSCMPFEN (RW)
393  *
394  * 1- enable trigger output when poscmpf flag set
395  */
396 #define QEIV2_TRGOEN_POSCMPFEN_MASK (0x20000000UL)
397 #define QEIV2_TRGOEN_POSCMPFEN_SHIFT (29U)
398 #define QEIV2_TRGOEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_POSCMPFEN_SHIFT) & QEIV2_TRGOEN_POSCMPFEN_MASK)
399 #define QEIV2_TRGOEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_POSCMPFEN_MASK) >> QEIV2_TRGOEN_POSCMPFEN_SHIFT)
400 
401 /*
402  * ZPHFEN (RW)
403  *
404  * 1- enable trigger output when zphf flag set
405  */
406 #define QEIV2_TRGOEN_ZPHFEN_MASK (0x10000000UL)
407 #define QEIV2_TRGOEN_ZPHFEN_SHIFT (28U)
408 #define QEIV2_TRGOEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_ZPHFEN_SHIFT) & QEIV2_TRGOEN_ZPHFEN_MASK)
409 #define QEIV2_TRGOEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_ZPHFEN_MASK) >> QEIV2_TRGOEN_ZPHFEN_SHIFT)
410 
411 /*
412  * ZMISSFEN (RW)
413  *
414  */
415 #define QEIV2_TRGOEN_ZMISSFEN_MASK (0x8000000UL)
416 #define QEIV2_TRGOEN_ZMISSFEN_SHIFT (27U)
417 #define QEIV2_TRGOEN_ZMISSFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_ZMISSFEN_SHIFT) & QEIV2_TRGOEN_ZMISSFEN_MASK)
418 #define QEIV2_TRGOEN_ZMISSFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_ZMISSFEN_MASK) >> QEIV2_TRGOEN_ZMISSFEN_SHIFT)
419 
420 /*
421  * WIDTHTMFEN (RW)
422  *
423  */
424 #define QEIV2_TRGOEN_WIDTHTMFEN_MASK (0x4000000UL)
425 #define QEIV2_TRGOEN_WIDTHTMFEN_SHIFT (26U)
426 #define QEIV2_TRGOEN_WIDTHTMFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_WIDTHTMFEN_SHIFT) & QEIV2_TRGOEN_WIDTHTMFEN_MASK)
427 #define QEIV2_TRGOEN_WIDTHTMFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_WIDTHTMFEN_MASK) >> QEIV2_TRGOEN_WIDTHTMFEN_SHIFT)
428 
429 /*
430  * POS2CMPFEN (RW)
431  *
432  */
433 #define QEIV2_TRGOEN_POS2CMPFEN_MASK (0x2000000UL)
434 #define QEIV2_TRGOEN_POS2CMPFEN_SHIFT (25U)
435 #define QEIV2_TRGOEN_POS2CMPFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_POS2CMPFEN_SHIFT) & QEIV2_TRGOEN_POS2CMPFEN_MASK)
436 #define QEIV2_TRGOEN_POS2CMPFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_POS2CMPFEN_MASK) >> QEIV2_TRGOEN_POS2CMPFEN_SHIFT)
437 
438 /*
439  * DIRCHGFEN (RW)
440  *
441  */
442 #define QEIV2_TRGOEN_DIRCHGFEN_MASK (0x1000000UL)
443 #define QEIV2_TRGOEN_DIRCHGFEN_SHIFT (24U)
444 #define QEIV2_TRGOEN_DIRCHGFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_DIRCHGFEN_SHIFT) & QEIV2_TRGOEN_DIRCHGFEN_MASK)
445 #define QEIV2_TRGOEN_DIRCHGFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_DIRCHGFEN_MASK) >> QEIV2_TRGOEN_DIRCHGFEN_SHIFT)
446 
447 /*
448  * CYCLE0FEN (RW)
449  *
450  */
451 #define QEIV2_TRGOEN_CYCLE0FEN_MASK (0x800000UL)
452 #define QEIV2_TRGOEN_CYCLE0FEN_SHIFT (23U)
453 #define QEIV2_TRGOEN_CYCLE0FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_CYCLE0FEN_SHIFT) & QEIV2_TRGOEN_CYCLE0FEN_MASK)
454 #define QEIV2_TRGOEN_CYCLE0FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_CYCLE0FEN_MASK) >> QEIV2_TRGOEN_CYCLE0FEN_SHIFT)
455 
456 /*
457  * CYCLE1FEN (RW)
458  *
459  */
460 #define QEIV2_TRGOEN_CYCLE1FEN_MASK (0x400000UL)
461 #define QEIV2_TRGOEN_CYCLE1FEN_SHIFT (22U)
462 #define QEIV2_TRGOEN_CYCLE1FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_CYCLE1FEN_SHIFT) & QEIV2_TRGOEN_CYCLE1FEN_MASK)
463 #define QEIV2_TRGOEN_CYCLE1FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_CYCLE1FEN_MASK) >> QEIV2_TRGOEN_CYCLE1FEN_SHIFT)
464 
465 /*
466  * PULSE0FEN (RW)
467  *
468  */
469 #define QEIV2_TRGOEN_PULSE0FEN_MASK (0x200000UL)
470 #define QEIV2_TRGOEN_PULSE0FEN_SHIFT (21U)
471 #define QEIV2_TRGOEN_PULSE0FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_PULSE0FEN_SHIFT) & QEIV2_TRGOEN_PULSE0FEN_MASK)
472 #define QEIV2_TRGOEN_PULSE0FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_PULSE0FEN_MASK) >> QEIV2_TRGOEN_PULSE0FEN_SHIFT)
473 
474 /*
475  * PULSE1FEN (RW)
476  *
477  */
478 #define QEIV2_TRGOEN_PULSE1FEN_MASK (0x100000UL)
479 #define QEIV2_TRGOEN_PULSE1FEN_SHIFT (20U)
480 #define QEIV2_TRGOEN_PULSE1FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_PULSE1FEN_SHIFT) & QEIV2_TRGOEN_PULSE1FEN_MASK)
481 #define QEIV2_TRGOEN_PULSE1FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_PULSE1FEN_MASK) >> QEIV2_TRGOEN_PULSE1FEN_SHIFT)
482 
483 /*
484  * HOME2FEN (RW)
485  *
486  */
487 #define QEIV2_TRGOEN_HOME2FEN_MASK (0x80000UL)
488 #define QEIV2_TRGOEN_HOME2FEN_SHIFT (19U)
489 #define QEIV2_TRGOEN_HOME2FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_HOME2FEN_SHIFT) & QEIV2_TRGOEN_HOME2FEN_MASK)
490 #define QEIV2_TRGOEN_HOME2FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_HOME2FEN_MASK) >> QEIV2_TRGOEN_HOME2FEN_SHIFT)
491 
492 /*
493  * FAULTFEN (RW)
494  *
495  */
496 #define QEIV2_TRGOEN_FAULTFEN_MASK (0x40000UL)
497 #define QEIV2_TRGOEN_FAULTFEN_SHIFT (18U)
498 #define QEIV2_TRGOEN_FAULTFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_FAULTFEN_SHIFT) & QEIV2_TRGOEN_FAULTFEN_MASK)
499 #define QEIV2_TRGOEN_FAULTFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_FAULTFEN_MASK) >> QEIV2_TRGOEN_FAULTFEN_SHIFT)
500 
501 /* Bitfield definition for register: READEN */
502 /*
503  * WDGFEN (RW)
504  *
505  * 1- load counters to their read registers when wdg flag set
506  */
507 #define QEIV2_READEN_WDGFEN_MASK (0x80000000UL)
508 #define QEIV2_READEN_WDGFEN_SHIFT (31U)
509 #define QEIV2_READEN_WDGFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_WDGFEN_SHIFT) & QEIV2_READEN_WDGFEN_MASK)
510 #define QEIV2_READEN_WDGFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_WDGFEN_MASK) >> QEIV2_READEN_WDGFEN_SHIFT)
511 
512 /*
513  * HOMEFEN (RW)
514  *
515  * 1- load counters to their read registers when homef flag set
516  */
517 #define QEIV2_READEN_HOMEFEN_MASK (0x40000000UL)
518 #define QEIV2_READEN_HOMEFEN_SHIFT (30U)
519 #define QEIV2_READEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_HOMEFEN_SHIFT) & QEIV2_READEN_HOMEFEN_MASK)
520 #define QEIV2_READEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_HOMEFEN_MASK) >> QEIV2_READEN_HOMEFEN_SHIFT)
521 
522 /*
523  * POSCMPFEN (RW)
524  *
525  * 1- load counters to their read registers when poscmpf flag set
526  */
527 #define QEIV2_READEN_POSCMPFEN_MASK (0x20000000UL)
528 #define QEIV2_READEN_POSCMPFEN_SHIFT (29U)
529 #define QEIV2_READEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_POSCMPFEN_SHIFT) & QEIV2_READEN_POSCMPFEN_MASK)
530 #define QEIV2_READEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_POSCMPFEN_MASK) >> QEIV2_READEN_POSCMPFEN_SHIFT)
531 
532 /*
533  * ZPHFEN (RW)
534  *
535  * 1- load counters to their read registers when zphf flag set
536  */
537 #define QEIV2_READEN_ZPHFEN_MASK (0x10000000UL)
538 #define QEIV2_READEN_ZPHFEN_SHIFT (28U)
539 #define QEIV2_READEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_ZPHFEN_SHIFT) & QEIV2_READEN_ZPHFEN_MASK)
540 #define QEIV2_READEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_ZPHFEN_MASK) >> QEIV2_READEN_ZPHFEN_SHIFT)
541 
542 /*
543  * ZMISSFEN (RW)
544  *
545  */
546 #define QEIV2_READEN_ZMISSFEN_MASK (0x8000000UL)
547 #define QEIV2_READEN_ZMISSFEN_SHIFT (27U)
548 #define QEIV2_READEN_ZMISSFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_ZMISSFEN_SHIFT) & QEIV2_READEN_ZMISSFEN_MASK)
549 #define QEIV2_READEN_ZMISSFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_ZMISSFEN_MASK) >> QEIV2_READEN_ZMISSFEN_SHIFT)
550 
551 /*
552  * WIDTHTMFEN (RW)
553  *
554  */
555 #define QEIV2_READEN_WIDTHTMFEN_MASK (0x4000000UL)
556 #define QEIV2_READEN_WIDTHTMFEN_SHIFT (26U)
557 #define QEIV2_READEN_WIDTHTMFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_WIDTHTMFEN_SHIFT) & QEIV2_READEN_WIDTHTMFEN_MASK)
558 #define QEIV2_READEN_WIDTHTMFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_WIDTHTMFEN_MASK) >> QEIV2_READEN_WIDTHTMFEN_SHIFT)
559 
560 /*
561  * POS2CMPFEN (RW)
562  *
563  */
564 #define QEIV2_READEN_POS2CMPFEN_MASK (0x2000000UL)
565 #define QEIV2_READEN_POS2CMPFEN_SHIFT (25U)
566 #define QEIV2_READEN_POS2CMPFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_POS2CMPFEN_SHIFT) & QEIV2_READEN_POS2CMPFEN_MASK)
567 #define QEIV2_READEN_POS2CMPFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_POS2CMPFEN_MASK) >> QEIV2_READEN_POS2CMPFEN_SHIFT)
568 
569 /*
570  * DIRCHGFEN (RW)
571  *
572  */
573 #define QEIV2_READEN_DIRCHGFEN_MASK (0x1000000UL)
574 #define QEIV2_READEN_DIRCHGFEN_SHIFT (24U)
575 #define QEIV2_READEN_DIRCHGFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_DIRCHGFEN_SHIFT) & QEIV2_READEN_DIRCHGFEN_MASK)
576 #define QEIV2_READEN_DIRCHGFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_DIRCHGFEN_MASK) >> QEIV2_READEN_DIRCHGFEN_SHIFT)
577 
578 /*
579  * CYCLE0FEN (RW)
580  *
581  */
582 #define QEIV2_READEN_CYCLE0FEN_MASK (0x800000UL)
583 #define QEIV2_READEN_CYCLE0FEN_SHIFT (23U)
584 #define QEIV2_READEN_CYCLE0FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_CYCLE0FEN_SHIFT) & QEIV2_READEN_CYCLE0FEN_MASK)
585 #define QEIV2_READEN_CYCLE0FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_CYCLE0FEN_MASK) >> QEIV2_READEN_CYCLE0FEN_SHIFT)
586 
587 /*
588  * CYCLE1FEN (RW)
589  *
590  */
591 #define QEIV2_READEN_CYCLE1FEN_MASK (0x400000UL)
592 #define QEIV2_READEN_CYCLE1FEN_SHIFT (22U)
593 #define QEIV2_READEN_CYCLE1FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_CYCLE1FEN_SHIFT) & QEIV2_READEN_CYCLE1FEN_MASK)
594 #define QEIV2_READEN_CYCLE1FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_CYCLE1FEN_MASK) >> QEIV2_READEN_CYCLE1FEN_SHIFT)
595 
596 /*
597  * PULSE0FEN (RW)
598  *
599  */
600 #define QEIV2_READEN_PULSE0FEN_MASK (0x200000UL)
601 #define QEIV2_READEN_PULSE0FEN_SHIFT (21U)
602 #define QEIV2_READEN_PULSE0FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_PULSE0FEN_SHIFT) & QEIV2_READEN_PULSE0FEN_MASK)
603 #define QEIV2_READEN_PULSE0FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_PULSE0FEN_MASK) >> QEIV2_READEN_PULSE0FEN_SHIFT)
604 
605 /*
606  * PULSE1FEN (RW)
607  *
608  */
609 #define QEIV2_READEN_PULSE1FEN_MASK (0x100000UL)
610 #define QEIV2_READEN_PULSE1FEN_SHIFT (20U)
611 #define QEIV2_READEN_PULSE1FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_PULSE1FEN_SHIFT) & QEIV2_READEN_PULSE1FEN_MASK)
612 #define QEIV2_READEN_PULSE1FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_PULSE1FEN_MASK) >> QEIV2_READEN_PULSE1FEN_SHIFT)
613 
614 /*
615  * HOME2FEN (RW)
616  *
617  */
618 #define QEIV2_READEN_HOME2FEN_MASK (0x80000UL)
619 #define QEIV2_READEN_HOME2FEN_SHIFT (19U)
620 #define QEIV2_READEN_HOME2FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_HOME2FEN_SHIFT) & QEIV2_READEN_HOME2FEN_MASK)
621 #define QEIV2_READEN_HOME2FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_HOME2FEN_MASK) >> QEIV2_READEN_HOME2FEN_SHIFT)
622 
623 /*
624  * FAULTFEN (RW)
625  *
626  */
627 #define QEIV2_READEN_FAULTFEN_MASK (0x40000UL)
628 #define QEIV2_READEN_FAULTFEN_SHIFT (18U)
629 #define QEIV2_READEN_FAULTFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_FAULTFEN_SHIFT) & QEIV2_READEN_FAULTFEN_MASK)
630 #define QEIV2_READEN_FAULTFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_FAULTFEN_MASK) >> QEIV2_READEN_FAULTFEN_SHIFT)
631 
632 /* Bitfield definition for register: ZCMP */
633 /*
634  * ZCMP (RW)
635  *
636  * zcnt postion compare value
637  */
638 #define QEIV2_ZCMP_ZCMP_MASK (0xFFFFFFFFUL)
639 #define QEIV2_ZCMP_ZCMP_SHIFT (0U)
640 #define QEIV2_ZCMP_ZCMP_SET(x) (((uint32_t)(x) << QEIV2_ZCMP_ZCMP_SHIFT) & QEIV2_ZCMP_ZCMP_MASK)
641 #define QEIV2_ZCMP_ZCMP_GET(x) (((uint32_t)(x) & QEIV2_ZCMP_ZCMP_MASK) >> QEIV2_ZCMP_ZCMP_SHIFT)
642 
643 /* Bitfield definition for register: PHCMP */
644 /*
645  * PHCMP (RW)
646  *
647  * phcnt position compare value
648  */
649 #define QEIV2_PHCMP_PHCMP_MASK (0xFFFFFFFFUL)
650 #define QEIV2_PHCMP_PHCMP_SHIFT (0U)
651 #define QEIV2_PHCMP_PHCMP_SET(x) (((uint32_t)(x) << QEIV2_PHCMP_PHCMP_SHIFT) & QEIV2_PHCMP_PHCMP_MASK)
652 #define QEIV2_PHCMP_PHCMP_GET(x) (((uint32_t)(x) & QEIV2_PHCMP_PHCMP_MASK) >> QEIV2_PHCMP_PHCMP_SHIFT)
653 
654 /* Bitfield definition for register: SPDCMP */
655 /*
656  * SPDCMP (RW)
657  *
658  * spdcnt position compare value
659  */
660 #define QEIV2_SPDCMP_SPDCMP_MASK (0xFFFFFFFFUL)
661 #define QEIV2_SPDCMP_SPDCMP_SHIFT (0U)
662 #define QEIV2_SPDCMP_SPDCMP_SET(x) (((uint32_t)(x) << QEIV2_SPDCMP_SPDCMP_SHIFT) & QEIV2_SPDCMP_SPDCMP_MASK)
663 #define QEIV2_SPDCMP_SPDCMP_GET(x) (((uint32_t)(x) & QEIV2_SPDCMP_SPDCMP_MASK) >> QEIV2_SPDCMP_SPDCMP_SHIFT)
664 
665 /* Bitfield definition for register: DMAEN */
666 /*
667  * WDGFEN (RW)
668  *
669  * 1- generate dma request when wdg flag set
670  */
671 #define QEIV2_DMAEN_WDGFEN_MASK (0x80000000UL)
672 #define QEIV2_DMAEN_WDGFEN_SHIFT (31U)
673 #define QEIV2_DMAEN_WDGFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_WDGFEN_SHIFT) & QEIV2_DMAEN_WDGFEN_MASK)
674 #define QEIV2_DMAEN_WDGFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_WDGFEN_MASK) >> QEIV2_DMAEN_WDGFEN_SHIFT)
675 
676 /*
677  * HOMEFEN (RW)
678  *
679  * 1- generate dma request when homef flag set
680  */
681 #define QEIV2_DMAEN_HOMEFEN_MASK (0x40000000UL)
682 #define QEIV2_DMAEN_HOMEFEN_SHIFT (30U)
683 #define QEIV2_DMAEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_HOMEFEN_SHIFT) & QEIV2_DMAEN_HOMEFEN_MASK)
684 #define QEIV2_DMAEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_HOMEFEN_MASK) >> QEIV2_DMAEN_HOMEFEN_SHIFT)
685 
686 /*
687  * POSCMPFEN (RW)
688  *
689  * 1- generate dma request when poscmpf flag set
690  */
691 #define QEIV2_DMAEN_POSCMPFEN_MASK (0x20000000UL)
692 #define QEIV2_DMAEN_POSCMPFEN_SHIFT (29U)
693 #define QEIV2_DMAEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_POSCMPFEN_SHIFT) & QEIV2_DMAEN_POSCMPFEN_MASK)
694 #define QEIV2_DMAEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_POSCMPFEN_MASK) >> QEIV2_DMAEN_POSCMPFEN_SHIFT)
695 
696 /*
697  * ZPHFEN (RW)
698  *
699  * 1- generate dma request when zphf flag set
700  */
701 #define QEIV2_DMAEN_ZPHFEN_MASK (0x10000000UL)
702 #define QEIV2_DMAEN_ZPHFEN_SHIFT (28U)
703 #define QEIV2_DMAEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_ZPHFEN_SHIFT) & QEIV2_DMAEN_ZPHFEN_MASK)
704 #define QEIV2_DMAEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_ZPHFEN_MASK) >> QEIV2_DMAEN_ZPHFEN_SHIFT)
705 
706 /*
707  * ZMISSFEN (RW)
708  *
709  */
710 #define QEIV2_DMAEN_ZMISSFEN_MASK (0x8000000UL)
711 #define QEIV2_DMAEN_ZMISSFEN_SHIFT (27U)
712 #define QEIV2_DMAEN_ZMISSFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_ZMISSFEN_SHIFT) & QEIV2_DMAEN_ZMISSFEN_MASK)
713 #define QEIV2_DMAEN_ZMISSFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_ZMISSFEN_MASK) >> QEIV2_DMAEN_ZMISSFEN_SHIFT)
714 
715 /*
716  * WIDTHTMFEN (RW)
717  *
718  */
719 #define QEIV2_DMAEN_WIDTHTMFEN_MASK (0x4000000UL)
720 #define QEIV2_DMAEN_WIDTHTMFEN_SHIFT (26U)
721 #define QEIV2_DMAEN_WIDTHTMFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_WIDTHTMFEN_SHIFT) & QEIV2_DMAEN_WIDTHTMFEN_MASK)
722 #define QEIV2_DMAEN_WIDTHTMFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_WIDTHTMFEN_MASK) >> QEIV2_DMAEN_WIDTHTMFEN_SHIFT)
723 
724 /*
725  * POS2CMPFEN (RW)
726  *
727  */
728 #define QEIV2_DMAEN_POS2CMPFEN_MASK (0x2000000UL)
729 #define QEIV2_DMAEN_POS2CMPFEN_SHIFT (25U)
730 #define QEIV2_DMAEN_POS2CMPFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_POS2CMPFEN_SHIFT) & QEIV2_DMAEN_POS2CMPFEN_MASK)
731 #define QEIV2_DMAEN_POS2CMPFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_POS2CMPFEN_MASK) >> QEIV2_DMAEN_POS2CMPFEN_SHIFT)
732 
733 /*
734  * DIRCHGFEN (RW)
735  *
736  */
737 #define QEIV2_DMAEN_DIRCHGFEN_MASK (0x1000000UL)
738 #define QEIV2_DMAEN_DIRCHGFEN_SHIFT (24U)
739 #define QEIV2_DMAEN_DIRCHGFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_DIRCHGFEN_SHIFT) & QEIV2_DMAEN_DIRCHGFEN_MASK)
740 #define QEIV2_DMAEN_DIRCHGFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_DIRCHGFEN_MASK) >> QEIV2_DMAEN_DIRCHGFEN_SHIFT)
741 
742 /*
743  * CYCLE0FEN (RW)
744  *
745  */
746 #define QEIV2_DMAEN_CYCLE0FEN_MASK (0x800000UL)
747 #define QEIV2_DMAEN_CYCLE0FEN_SHIFT (23U)
748 #define QEIV2_DMAEN_CYCLE0FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_CYCLE0FEN_SHIFT) & QEIV2_DMAEN_CYCLE0FEN_MASK)
749 #define QEIV2_DMAEN_CYCLE0FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_CYCLE0FEN_MASK) >> QEIV2_DMAEN_CYCLE0FEN_SHIFT)
750 
751 /*
752  * CYCLE1FEN (RW)
753  *
754  */
755 #define QEIV2_DMAEN_CYCLE1FEN_MASK (0x400000UL)
756 #define QEIV2_DMAEN_CYCLE1FEN_SHIFT (22U)
757 #define QEIV2_DMAEN_CYCLE1FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_CYCLE1FEN_SHIFT) & QEIV2_DMAEN_CYCLE1FEN_MASK)
758 #define QEIV2_DMAEN_CYCLE1FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_CYCLE1FEN_MASK) >> QEIV2_DMAEN_CYCLE1FEN_SHIFT)
759 
760 /*
761  * PULSE0FEN (RW)
762  *
763  */
764 #define QEIV2_DMAEN_PULSE0FEN_MASK (0x200000UL)
765 #define QEIV2_DMAEN_PULSE0FEN_SHIFT (21U)
766 #define QEIV2_DMAEN_PULSE0FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_PULSE0FEN_SHIFT) & QEIV2_DMAEN_PULSE0FEN_MASK)
767 #define QEIV2_DMAEN_PULSE0FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_PULSE0FEN_MASK) >> QEIV2_DMAEN_PULSE0FEN_SHIFT)
768 
769 /*
770  * PULSE1FEN (RW)
771  *
772  */
773 #define QEIV2_DMAEN_PULSE1FEN_MASK (0x100000UL)
774 #define QEIV2_DMAEN_PULSE1FEN_SHIFT (20U)
775 #define QEIV2_DMAEN_PULSE1FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_PULSE1FEN_SHIFT) & QEIV2_DMAEN_PULSE1FEN_MASK)
776 #define QEIV2_DMAEN_PULSE1FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_PULSE1FEN_MASK) >> QEIV2_DMAEN_PULSE1FEN_SHIFT)
777 
778 /*
779  * HOME2FEN (RW)
780  *
781  */
782 #define QEIV2_DMAEN_HOME2FEN_MASK (0x80000UL)
783 #define QEIV2_DMAEN_HOME2FEN_SHIFT (19U)
784 #define QEIV2_DMAEN_HOME2FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_HOME2FEN_SHIFT) & QEIV2_DMAEN_HOME2FEN_MASK)
785 #define QEIV2_DMAEN_HOME2FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_HOME2FEN_MASK) >> QEIV2_DMAEN_HOME2FEN_SHIFT)
786 
787 /*
788  * FAULTFEN (RW)
789  *
790  */
791 #define QEIV2_DMAEN_FAULTFEN_MASK (0x40000UL)
792 #define QEIV2_DMAEN_FAULTFEN_SHIFT (18U)
793 #define QEIV2_DMAEN_FAULTFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_FAULTFEN_SHIFT) & QEIV2_DMAEN_FAULTFEN_MASK)
794 #define QEIV2_DMAEN_FAULTFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_FAULTFEN_MASK) >> QEIV2_DMAEN_FAULTFEN_SHIFT)
795 
796 /* Bitfield definition for register: SR */
797 /*
798  * WDGF (RW)
799  *
800  * watchdog flag
801  */
802 #define QEIV2_SR_WDGF_MASK (0x80000000UL)
803 #define QEIV2_SR_WDGF_SHIFT (31U)
804 #define QEIV2_SR_WDGF_SET(x) (((uint32_t)(x) << QEIV2_SR_WDGF_SHIFT) & QEIV2_SR_WDGF_MASK)
805 #define QEIV2_SR_WDGF_GET(x) (((uint32_t)(x) & QEIV2_SR_WDGF_MASK) >> QEIV2_SR_WDGF_SHIFT)
806 
807 /*
808  * HOMEF (RW)
809  *
810  * home flag
811  */
812 #define QEIV2_SR_HOMEF_MASK (0x40000000UL)
813 #define QEIV2_SR_HOMEF_SHIFT (30U)
814 #define QEIV2_SR_HOMEF_SET(x) (((uint32_t)(x) << QEIV2_SR_HOMEF_SHIFT) & QEIV2_SR_HOMEF_MASK)
815 #define QEIV2_SR_HOMEF_GET(x) (((uint32_t)(x) & QEIV2_SR_HOMEF_MASK) >> QEIV2_SR_HOMEF_SHIFT)
816 
817 /*
818  * POSCMPF (RW)
819  *
820  * postion compare match flag
821  */
822 #define QEIV2_SR_POSCMPF_MASK (0x20000000UL)
823 #define QEIV2_SR_POSCMPF_SHIFT (29U)
824 #define QEIV2_SR_POSCMPF_SET(x) (((uint32_t)(x) << QEIV2_SR_POSCMPF_SHIFT) & QEIV2_SR_POSCMPF_MASK)
825 #define QEIV2_SR_POSCMPF_GET(x) (((uint32_t)(x) & QEIV2_SR_POSCMPF_MASK) >> QEIV2_SR_POSCMPF_SHIFT)
826 
827 /*
828  * ZPHF (RW)
829  *
830  * z input flag
831  */
832 #define QEIV2_SR_ZPHF_MASK (0x10000000UL)
833 #define QEIV2_SR_ZPHF_SHIFT (28U)
834 #define QEIV2_SR_ZPHF_SET(x) (((uint32_t)(x) << QEIV2_SR_ZPHF_SHIFT) & QEIV2_SR_ZPHF_MASK)
835 #define QEIV2_SR_ZPHF_GET(x) (((uint32_t)(x) & QEIV2_SR_ZPHF_MASK) >> QEIV2_SR_ZPHF_SHIFT)
836 
837 /*
838  * ZMISSF (RW)
839  *
840  */
841 #define QEIV2_SR_ZMISSF_MASK (0x8000000UL)
842 #define QEIV2_SR_ZMISSF_SHIFT (27U)
843 #define QEIV2_SR_ZMISSF_SET(x) (((uint32_t)(x) << QEIV2_SR_ZMISSF_SHIFT) & QEIV2_SR_ZMISSF_MASK)
844 #define QEIV2_SR_ZMISSF_GET(x) (((uint32_t)(x) & QEIV2_SR_ZMISSF_MASK) >> QEIV2_SR_ZMISSF_SHIFT)
845 
846 /*
847  * WIDTHTMF (RW)
848  *
849  */
850 #define QEIV2_SR_WIDTHTMF_MASK (0x4000000UL)
851 #define QEIV2_SR_WIDTHTMF_SHIFT (26U)
852 #define QEIV2_SR_WIDTHTMF_SET(x) (((uint32_t)(x) << QEIV2_SR_WIDTHTMF_SHIFT) & QEIV2_SR_WIDTHTMF_MASK)
853 #define QEIV2_SR_WIDTHTMF_GET(x) (((uint32_t)(x) & QEIV2_SR_WIDTHTMF_MASK) >> QEIV2_SR_WIDTHTMF_SHIFT)
854 
855 /*
856  * POS2CMPF (RW)
857  *
858  */
859 #define QEIV2_SR_POS2CMPF_MASK (0x2000000UL)
860 #define QEIV2_SR_POS2CMPF_SHIFT (25U)
861 #define QEIV2_SR_POS2CMPF_SET(x) (((uint32_t)(x) << QEIV2_SR_POS2CMPF_SHIFT) & QEIV2_SR_POS2CMPF_MASK)
862 #define QEIV2_SR_POS2CMPF_GET(x) (((uint32_t)(x) & QEIV2_SR_POS2CMPF_MASK) >> QEIV2_SR_POS2CMPF_SHIFT)
863 
864 /*
865  * DIRCHGF (RW)
866  *
867  */
868 #define QEIV2_SR_DIRCHGF_MASK (0x1000000UL)
869 #define QEIV2_SR_DIRCHGF_SHIFT (24U)
870 #define QEIV2_SR_DIRCHGF_SET(x) (((uint32_t)(x) << QEIV2_SR_DIRCHGF_SHIFT) & QEIV2_SR_DIRCHGF_MASK)
871 #define QEIV2_SR_DIRCHGF_GET(x) (((uint32_t)(x) & QEIV2_SR_DIRCHGF_MASK) >> QEIV2_SR_DIRCHGF_SHIFT)
872 
873 /*
874  * CYCLE0F (RW)
875  *
876  */
877 #define QEIV2_SR_CYCLE0F_MASK (0x800000UL)
878 #define QEIV2_SR_CYCLE0F_SHIFT (23U)
879 #define QEIV2_SR_CYCLE0F_SET(x) (((uint32_t)(x) << QEIV2_SR_CYCLE0F_SHIFT) & QEIV2_SR_CYCLE0F_MASK)
880 #define QEIV2_SR_CYCLE0F_GET(x) (((uint32_t)(x) & QEIV2_SR_CYCLE0F_MASK) >> QEIV2_SR_CYCLE0F_SHIFT)
881 
882 /*
883  * CYCLE1F (RW)
884  *
885  */
886 #define QEIV2_SR_CYCLE1F_MASK (0x400000UL)
887 #define QEIV2_SR_CYCLE1F_SHIFT (22U)
888 #define QEIV2_SR_CYCLE1F_SET(x) (((uint32_t)(x) << QEIV2_SR_CYCLE1F_SHIFT) & QEIV2_SR_CYCLE1F_MASK)
889 #define QEIV2_SR_CYCLE1F_GET(x) (((uint32_t)(x) & QEIV2_SR_CYCLE1F_MASK) >> QEIV2_SR_CYCLE1F_SHIFT)
890 
891 /*
892  * PULSE0F (RW)
893  *
894  */
895 #define QEIV2_SR_PULSE0F_MASK (0x200000UL)
896 #define QEIV2_SR_PULSE0F_SHIFT (21U)
897 #define QEIV2_SR_PULSE0F_SET(x) (((uint32_t)(x) << QEIV2_SR_PULSE0F_SHIFT) & QEIV2_SR_PULSE0F_MASK)
898 #define QEIV2_SR_PULSE0F_GET(x) (((uint32_t)(x) & QEIV2_SR_PULSE0F_MASK) >> QEIV2_SR_PULSE0F_SHIFT)
899 
900 /*
901  * PULSE1F (RW)
902  *
903  */
904 #define QEIV2_SR_PULSE1F_MASK (0x100000UL)
905 #define QEIV2_SR_PULSE1F_SHIFT (20U)
906 #define QEIV2_SR_PULSE1F_SET(x) (((uint32_t)(x) << QEIV2_SR_PULSE1F_SHIFT) & QEIV2_SR_PULSE1F_MASK)
907 #define QEIV2_SR_PULSE1F_GET(x) (((uint32_t)(x) & QEIV2_SR_PULSE1F_MASK) >> QEIV2_SR_PULSE1F_SHIFT)
908 
909 /*
910  * HOME2F (RW)
911  *
912  */
913 #define QEIV2_SR_HOME2F_MASK (0x80000UL)
914 #define QEIV2_SR_HOME2F_SHIFT (19U)
915 #define QEIV2_SR_HOME2F_SET(x) (((uint32_t)(x) << QEIV2_SR_HOME2F_SHIFT) & QEIV2_SR_HOME2F_MASK)
916 #define QEIV2_SR_HOME2F_GET(x) (((uint32_t)(x) & QEIV2_SR_HOME2F_MASK) >> QEIV2_SR_HOME2F_SHIFT)
917 
918 /*
919  * FAULTF (RW)
920  *
921  */
922 #define QEIV2_SR_FAULTF_MASK (0x40000UL)
923 #define QEIV2_SR_FAULTF_SHIFT (18U)
924 #define QEIV2_SR_FAULTF_SET(x) (((uint32_t)(x) << QEIV2_SR_FAULTF_SHIFT) & QEIV2_SR_FAULTF_MASK)
925 #define QEIV2_SR_FAULTF_GET(x) (((uint32_t)(x) & QEIV2_SR_FAULTF_MASK) >> QEIV2_SR_FAULTF_SHIFT)
926 
927 /* Bitfield definition for register: IRQEN */
928 /*
929  * WDGIE (RW)
930  *
931  * 1- generate interrupt when wdg flag set
932  */
933 #define QEIV2_IRQEN_WDGIE_MASK (0x80000000UL)
934 #define QEIV2_IRQEN_WDGIE_SHIFT (31U)
935 #define QEIV2_IRQEN_WDGIE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_WDGIE_SHIFT) & QEIV2_IRQEN_WDGIE_MASK)
936 #define QEIV2_IRQEN_WDGIE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_WDGIE_MASK) >> QEIV2_IRQEN_WDGIE_SHIFT)
937 
938 /*
939  * HOMEIE (RW)
940  *
941  * 1- generate interrupt when homef flag set
942  */
943 #define QEIV2_IRQEN_HOMEIE_MASK (0x40000000UL)
944 #define QEIV2_IRQEN_HOMEIE_SHIFT (30U)
945 #define QEIV2_IRQEN_HOMEIE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_HOMEIE_SHIFT) & QEIV2_IRQEN_HOMEIE_MASK)
946 #define QEIV2_IRQEN_HOMEIE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_HOMEIE_MASK) >> QEIV2_IRQEN_HOMEIE_SHIFT)
947 
948 /*
949  * POSCMPIE (RW)
950  *
951  * 1- generate interrupt when poscmpf flag set
952  */
953 #define QEIV2_IRQEN_POSCMPIE_MASK (0x20000000UL)
954 #define QEIV2_IRQEN_POSCMPIE_SHIFT (29U)
955 #define QEIV2_IRQEN_POSCMPIE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_POSCMPIE_SHIFT) & QEIV2_IRQEN_POSCMPIE_MASK)
956 #define QEIV2_IRQEN_POSCMPIE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_POSCMPIE_MASK) >> QEIV2_IRQEN_POSCMPIE_SHIFT)
957 
958 /*
959  * ZPHIE (RW)
960  *
961  * 1- generate interrupt when zphf flag set
962  */
963 #define QEIV2_IRQEN_ZPHIE_MASK (0x10000000UL)
964 #define QEIV2_IRQEN_ZPHIE_SHIFT (28U)
965 #define QEIV2_IRQEN_ZPHIE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_ZPHIE_SHIFT) & QEIV2_IRQEN_ZPHIE_MASK)
966 #define QEIV2_IRQEN_ZPHIE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_ZPHIE_MASK) >> QEIV2_IRQEN_ZPHIE_SHIFT)
967 
968 /*
969  * ZMISSE (RW)
970  *
971  */
972 #define QEIV2_IRQEN_ZMISSE_MASK (0x8000000UL)
973 #define QEIV2_IRQEN_ZMISSE_SHIFT (27U)
974 #define QEIV2_IRQEN_ZMISSE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_ZMISSE_SHIFT) & QEIV2_IRQEN_ZMISSE_MASK)
975 #define QEIV2_IRQEN_ZMISSE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_ZMISSE_MASK) >> QEIV2_IRQEN_ZMISSE_SHIFT)
976 
977 /*
978  * WIDTHTME (RW)
979  *
980  */
981 #define QEIV2_IRQEN_WIDTHTME_MASK (0x4000000UL)
982 #define QEIV2_IRQEN_WIDTHTME_SHIFT (26U)
983 #define QEIV2_IRQEN_WIDTHTME_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_WIDTHTME_SHIFT) & QEIV2_IRQEN_WIDTHTME_MASK)
984 #define QEIV2_IRQEN_WIDTHTME_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_WIDTHTME_MASK) >> QEIV2_IRQEN_WIDTHTME_SHIFT)
985 
986 /*
987  * POS2CMPE (RW)
988  *
989  */
990 #define QEIV2_IRQEN_POS2CMPE_MASK (0x2000000UL)
991 #define QEIV2_IRQEN_POS2CMPE_SHIFT (25U)
992 #define QEIV2_IRQEN_POS2CMPE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_POS2CMPE_SHIFT) & QEIV2_IRQEN_POS2CMPE_MASK)
993 #define QEIV2_IRQEN_POS2CMPE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_POS2CMPE_MASK) >> QEIV2_IRQEN_POS2CMPE_SHIFT)
994 
995 /*
996  * DIRCHGE (RW)
997  *
998  */
999 #define QEIV2_IRQEN_DIRCHGE_MASK (0x1000000UL)
1000 #define QEIV2_IRQEN_DIRCHGE_SHIFT (24U)
1001 #define QEIV2_IRQEN_DIRCHGE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_DIRCHGE_SHIFT) & QEIV2_IRQEN_DIRCHGE_MASK)
1002 #define QEIV2_IRQEN_DIRCHGE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_DIRCHGE_MASK) >> QEIV2_IRQEN_DIRCHGE_SHIFT)
1003 
1004 /*
1005  * CYCLE0E (RW)
1006  *
1007  */
1008 #define QEIV2_IRQEN_CYCLE0E_MASK (0x800000UL)
1009 #define QEIV2_IRQEN_CYCLE0E_SHIFT (23U)
1010 #define QEIV2_IRQEN_CYCLE0E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_CYCLE0E_SHIFT) & QEIV2_IRQEN_CYCLE0E_MASK)
1011 #define QEIV2_IRQEN_CYCLE0E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_CYCLE0E_MASK) >> QEIV2_IRQEN_CYCLE0E_SHIFT)
1012 
1013 /*
1014  * CYCLE1E (RW)
1015  *
1016  */
1017 #define QEIV2_IRQEN_CYCLE1E_MASK (0x400000UL)
1018 #define QEIV2_IRQEN_CYCLE1E_SHIFT (22U)
1019 #define QEIV2_IRQEN_CYCLE1E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_CYCLE1E_SHIFT) & QEIV2_IRQEN_CYCLE1E_MASK)
1020 #define QEIV2_IRQEN_CYCLE1E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_CYCLE1E_MASK) >> QEIV2_IRQEN_CYCLE1E_SHIFT)
1021 
1022 /*
1023  * PULSE0E (RW)
1024  *
1025  */
1026 #define QEIV2_IRQEN_PULSE0E_MASK (0x200000UL)
1027 #define QEIV2_IRQEN_PULSE0E_SHIFT (21U)
1028 #define QEIV2_IRQEN_PULSE0E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_PULSE0E_SHIFT) & QEIV2_IRQEN_PULSE0E_MASK)
1029 #define QEIV2_IRQEN_PULSE0E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_PULSE0E_MASK) >> QEIV2_IRQEN_PULSE0E_SHIFT)
1030 
1031 /*
1032  * PULSE1E (RW)
1033  *
1034  */
1035 #define QEIV2_IRQEN_PULSE1E_MASK (0x100000UL)
1036 #define QEIV2_IRQEN_PULSE1E_SHIFT (20U)
1037 #define QEIV2_IRQEN_PULSE1E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_PULSE1E_SHIFT) & QEIV2_IRQEN_PULSE1E_MASK)
1038 #define QEIV2_IRQEN_PULSE1E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_PULSE1E_MASK) >> QEIV2_IRQEN_PULSE1E_SHIFT)
1039 
1040 /*
1041  * HOME2E (RW)
1042  *
1043  */
1044 #define QEIV2_IRQEN_HOME2E_MASK (0x80000UL)
1045 #define QEIV2_IRQEN_HOME2E_SHIFT (19U)
1046 #define QEIV2_IRQEN_HOME2E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_HOME2E_SHIFT) & QEIV2_IRQEN_HOME2E_MASK)
1047 #define QEIV2_IRQEN_HOME2E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_HOME2E_MASK) >> QEIV2_IRQEN_HOME2E_SHIFT)
1048 
1049 /*
1050  * FAULTE (RW)
1051  *
1052  */
1053 #define QEIV2_IRQEN_FAULTE_MASK (0x40000UL)
1054 #define QEIV2_IRQEN_FAULTE_SHIFT (18U)
1055 #define QEIV2_IRQEN_FAULTE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_FAULTE_SHIFT) & QEIV2_IRQEN_FAULTE_MASK)
1056 #define QEIV2_IRQEN_FAULTE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_FAULTE_MASK) >> QEIV2_IRQEN_FAULTE_SHIFT)
1057 
1058 /* Bitfield definition for register of struct array COUNT: Z */
1059 /*
1060  * ZCNT (RW)
1061  *
1062  * zcnt value
1063  */
1064 #define QEIV2_COUNT_Z_ZCNT_MASK (0xFFFFFFFFUL)
1065 #define QEIV2_COUNT_Z_ZCNT_SHIFT (0U)
1066 #define QEIV2_COUNT_Z_ZCNT_SET(x) (((uint32_t)(x) << QEIV2_COUNT_Z_ZCNT_SHIFT) & QEIV2_COUNT_Z_ZCNT_MASK)
1067 #define QEIV2_COUNT_Z_ZCNT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_Z_ZCNT_MASK) >> QEIV2_COUNT_Z_ZCNT_SHIFT)
1068 
1069 /* Bitfield definition for register of struct array COUNT: PH */
1070 /*
1071  * DIR (RO)
1072  *
1073  * 1- reverse rotation
1074  * 0- forward rotation
1075  */
1076 #define QEIV2_COUNT_PH_DIR_MASK (0x40000000UL)
1077 #define QEIV2_COUNT_PH_DIR_SHIFT (30U)
1078 #define QEIV2_COUNT_PH_DIR_GET(x) (((uint32_t)(x) & QEIV2_COUNT_PH_DIR_MASK) >> QEIV2_COUNT_PH_DIR_SHIFT)
1079 
1080 /*
1081  * ASTAT (RO)
1082  *
1083  * 1- a input is high
1084  * 0- a input is low
1085  */
1086 #define QEIV2_COUNT_PH_ASTAT_MASK (0x4000000UL)
1087 #define QEIV2_COUNT_PH_ASTAT_SHIFT (26U)
1088 #define QEIV2_COUNT_PH_ASTAT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_PH_ASTAT_MASK) >> QEIV2_COUNT_PH_ASTAT_SHIFT)
1089 
1090 /*
1091  * BSTAT (RO)
1092  *
1093  * 1- b input is high
1094  * 0- b input is low
1095  */
1096 #define QEIV2_COUNT_PH_BSTAT_MASK (0x2000000UL)
1097 #define QEIV2_COUNT_PH_BSTAT_SHIFT (25U)
1098 #define QEIV2_COUNT_PH_BSTAT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_PH_BSTAT_MASK) >> QEIV2_COUNT_PH_BSTAT_SHIFT)
1099 
1100 /*
1101  * PHCNT (RO)
1102  *
1103  * phcnt value
1104  */
1105 #define QEIV2_COUNT_PH_PHCNT_MASK (0x1FFFFFUL)
1106 #define QEIV2_COUNT_PH_PHCNT_SHIFT (0U)
1107 #define QEIV2_COUNT_PH_PHCNT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_PH_PHCNT_MASK) >> QEIV2_COUNT_PH_PHCNT_SHIFT)
1108 
1109 /* Bitfield definition for register of struct array COUNT: SPD */
1110 /*
1111  * DIR (RO)
1112  *
1113  * 1- reverse rotation
1114  * 0- forward rotation
1115  */
1116 #define QEIV2_COUNT_SPD_DIR_MASK (0x80000000UL)
1117 #define QEIV2_COUNT_SPD_DIR_SHIFT (31U)
1118 #define QEIV2_COUNT_SPD_DIR_GET(x) (((uint32_t)(x) & QEIV2_COUNT_SPD_DIR_MASK) >> QEIV2_COUNT_SPD_DIR_SHIFT)
1119 
1120 /*
1121  * ASTAT (RO)
1122  *
1123  * 1- a input is high
1124  * 0- a input is low
1125  */
1126 #define QEIV2_COUNT_SPD_ASTAT_MASK (0x40000000UL)
1127 #define QEIV2_COUNT_SPD_ASTAT_SHIFT (30U)
1128 #define QEIV2_COUNT_SPD_ASTAT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_SPD_ASTAT_MASK) >> QEIV2_COUNT_SPD_ASTAT_SHIFT)
1129 
1130 /*
1131  * BSTAT (RW)
1132  *
1133  * 1- b input is high
1134  * 0- b input is low
1135  */
1136 #define QEIV2_COUNT_SPD_BSTAT_MASK (0x20000000UL)
1137 #define QEIV2_COUNT_SPD_BSTAT_SHIFT (29U)
1138 #define QEIV2_COUNT_SPD_BSTAT_SET(x) (((uint32_t)(x) << QEIV2_COUNT_SPD_BSTAT_SHIFT) & QEIV2_COUNT_SPD_BSTAT_MASK)
1139 #define QEIV2_COUNT_SPD_BSTAT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_SPD_BSTAT_MASK) >> QEIV2_COUNT_SPD_BSTAT_SHIFT)
1140 
1141 /*
1142  * SPDCNT (RO)
1143  *
1144  * spdcnt value
1145  */
1146 #define QEIV2_COUNT_SPD_SPDCNT_MASK (0xFFFFFFFUL)
1147 #define QEIV2_COUNT_SPD_SPDCNT_SHIFT (0U)
1148 #define QEIV2_COUNT_SPD_SPDCNT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_SPD_SPDCNT_MASK) >> QEIV2_COUNT_SPD_SPDCNT_SHIFT)
1149 
1150 /* Bitfield definition for register of struct array COUNT: TMR */
1151 /*
1152  * TMRCNT (RO)
1153  *
1154  * 32 bit free run timer
1155  */
1156 #define QEIV2_COUNT_TMR_TMRCNT_MASK (0xFFFFFFFFUL)
1157 #define QEIV2_COUNT_TMR_TMRCNT_SHIFT (0U)
1158 #define QEIV2_COUNT_TMR_TMRCNT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_TMR_TMRCNT_MASK) >> QEIV2_COUNT_TMR_TMRCNT_SHIFT)
1159 
1160 /* Bitfield definition for register: ZCMP2 */
1161 /*
1162  * ZCMP2 (RW)
1163  *
1164  */
1165 #define QEIV2_ZCMP2_ZCMP2_MASK (0xFFFFFFFFUL)
1166 #define QEIV2_ZCMP2_ZCMP2_SHIFT (0U)
1167 #define QEIV2_ZCMP2_ZCMP2_SET(x) (((uint32_t)(x) << QEIV2_ZCMP2_ZCMP2_SHIFT) & QEIV2_ZCMP2_ZCMP2_MASK)
1168 #define QEIV2_ZCMP2_ZCMP2_GET(x) (((uint32_t)(x) & QEIV2_ZCMP2_ZCMP2_MASK) >> QEIV2_ZCMP2_ZCMP2_SHIFT)
1169 
1170 /* Bitfield definition for register: PHCMP2 */
1171 /*
1172  * PHCMP2 (RW)
1173  *
1174  */
1175 #define QEIV2_PHCMP2_PHCMP2_MASK (0xFFFFFFFFUL)
1176 #define QEIV2_PHCMP2_PHCMP2_SHIFT (0U)
1177 #define QEIV2_PHCMP2_PHCMP2_SET(x) (((uint32_t)(x) << QEIV2_PHCMP2_PHCMP2_SHIFT) & QEIV2_PHCMP2_PHCMP2_MASK)
1178 #define QEIV2_PHCMP2_PHCMP2_GET(x) (((uint32_t)(x) & QEIV2_PHCMP2_PHCMP2_MASK) >> QEIV2_PHCMP2_PHCMP2_SHIFT)
1179 
1180 /* Bitfield definition for register: SPDCMP2 */
1181 /*
1182  * SPDCMP2 (RW)
1183  *
1184  */
1185 #define QEIV2_SPDCMP2_SPDCMP2_MASK (0xFFFFFFFFUL)
1186 #define QEIV2_SPDCMP2_SPDCMP2_SHIFT (0U)
1187 #define QEIV2_SPDCMP2_SPDCMP2_SET(x) (((uint32_t)(x) << QEIV2_SPDCMP2_SPDCMP2_SHIFT) & QEIV2_SPDCMP2_SPDCMP2_MASK)
1188 #define QEIV2_SPDCMP2_SPDCMP2_GET(x) (((uint32_t)(x) & QEIV2_SPDCMP2_SPDCMP2_MASK) >> QEIV2_SPDCMP2_SPDCMP2_SHIFT)
1189 
1190 /* Bitfield definition for register: MATCH_CFG */
1191 /*
1192  * ZCMPDIS (RW)
1193  *
1194  * 1- postion compare not include zcnt
1195  */
1196 #define QEIV2_MATCH_CFG_ZCMPDIS_MASK (0x80000000UL)
1197 #define QEIV2_MATCH_CFG_ZCMPDIS_SHIFT (31U)
1198 #define QEIV2_MATCH_CFG_ZCMPDIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_ZCMPDIS_SHIFT) & QEIV2_MATCH_CFG_ZCMPDIS_MASK)
1199 #define QEIV2_MATCH_CFG_ZCMPDIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_ZCMPDIS_MASK) >> QEIV2_MATCH_CFG_ZCMPDIS_SHIFT)
1200 
1201 /*
1202  * DIRCMPDIS (RW)
1203  *
1204  * 1- postion compare not include rotation direction
1205  */
1206 #define QEIV2_MATCH_CFG_DIRCMPDIS_MASK (0x40000000UL)
1207 #define QEIV2_MATCH_CFG_DIRCMPDIS_SHIFT (30U)
1208 #define QEIV2_MATCH_CFG_DIRCMPDIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMPDIS_SHIFT) & QEIV2_MATCH_CFG_DIRCMPDIS_MASK)
1209 #define QEIV2_MATCH_CFG_DIRCMPDIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMPDIS_MASK) >> QEIV2_MATCH_CFG_DIRCMPDIS_SHIFT)
1210 
1211 /*
1212  * DIRCMP (RW)
1213  *
1214  * 0- position compare need positive rotation
1215  * 1- position compare need negative rotation
1216  */
1217 #define QEIV2_MATCH_CFG_DIRCMP_MASK (0x20000000UL)
1218 #define QEIV2_MATCH_CFG_DIRCMP_SHIFT (29U)
1219 #define QEIV2_MATCH_CFG_DIRCMP_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMP_SHIFT) & QEIV2_MATCH_CFG_DIRCMP_MASK)
1220 #define QEIV2_MATCH_CFG_DIRCMP_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMP_MASK) >> QEIV2_MATCH_CFG_DIRCMP_SHIFT)
1221 
1222 /*
1223  * SPDCMPDIS (RW)
1224  *
1225  */
1226 #define QEIV2_MATCH_CFG_SPDCMPDIS_MASK (0x10000000UL)
1227 #define QEIV2_MATCH_CFG_SPDCMPDIS_SHIFT (28U)
1228 #define QEIV2_MATCH_CFG_SPDCMPDIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_SPDCMPDIS_SHIFT) & QEIV2_MATCH_CFG_SPDCMPDIS_MASK)
1229 #define QEIV2_MATCH_CFG_SPDCMPDIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_SPDCMPDIS_MASK) >> QEIV2_MATCH_CFG_SPDCMPDIS_SHIFT)
1230 
1231 /*
1232  * PHASE_MATCH_DIS (RW)
1233  *
1234  */
1235 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_MASK (0x8000000UL)
1236 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SHIFT (27U)
1237 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SHIFT) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS_MASK)
1238 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS_MASK) >> QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SHIFT)
1239 
1240 /*
1241  * POS_MATCH_DIR (RW)
1242  *
1243  */
1244 #define QEIV2_MATCH_CFG_POS_MATCH_DIR_MASK (0x4000000UL)
1245 #define QEIV2_MATCH_CFG_POS_MATCH_DIR_SHIFT (26U)
1246 #define QEIV2_MATCH_CFG_POS_MATCH_DIR_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH_DIR_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH_DIR_MASK)
1247 #define QEIV2_MATCH_CFG_POS_MATCH_DIR_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH_DIR_MASK) >> QEIV2_MATCH_CFG_POS_MATCH_DIR_SHIFT)
1248 
1249 /*
1250  * POS_MATCH_OPT (RW)
1251  *
1252  */
1253 #define QEIV2_MATCH_CFG_POS_MATCH_OPT_MASK (0x2000000UL)
1254 #define QEIV2_MATCH_CFG_POS_MATCH_OPT_SHIFT (25U)
1255 #define QEIV2_MATCH_CFG_POS_MATCH_OPT_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH_OPT_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH_OPT_MASK)
1256 #define QEIV2_MATCH_CFG_POS_MATCH_OPT_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH_OPT_MASK) >> QEIV2_MATCH_CFG_POS_MATCH_OPT_SHIFT)
1257 
1258 /*
1259  * ZCMP2DIS (RW)
1260  *
1261  */
1262 #define QEIV2_MATCH_CFG_ZCMP2DIS_MASK (0x8000U)
1263 #define QEIV2_MATCH_CFG_ZCMP2DIS_SHIFT (15U)
1264 #define QEIV2_MATCH_CFG_ZCMP2DIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_ZCMP2DIS_SHIFT) & QEIV2_MATCH_CFG_ZCMP2DIS_MASK)
1265 #define QEIV2_MATCH_CFG_ZCMP2DIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_ZCMP2DIS_MASK) >> QEIV2_MATCH_CFG_ZCMP2DIS_SHIFT)
1266 
1267 /*
1268  * DIRCMP2DIS (RW)
1269  *
1270  */
1271 #define QEIV2_MATCH_CFG_DIRCMP2DIS_MASK (0x4000U)
1272 #define QEIV2_MATCH_CFG_DIRCMP2DIS_SHIFT (14U)
1273 #define QEIV2_MATCH_CFG_DIRCMP2DIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMP2DIS_SHIFT) & QEIV2_MATCH_CFG_DIRCMP2DIS_MASK)
1274 #define QEIV2_MATCH_CFG_DIRCMP2DIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMP2DIS_MASK) >> QEIV2_MATCH_CFG_DIRCMP2DIS_SHIFT)
1275 
1276 /*
1277  * DIRCMP2 (RW)
1278  *
1279  */
1280 #define QEIV2_MATCH_CFG_DIRCMP2_MASK (0x2000U)
1281 #define QEIV2_MATCH_CFG_DIRCMP2_SHIFT (13U)
1282 #define QEIV2_MATCH_CFG_DIRCMP2_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMP2_SHIFT) & QEIV2_MATCH_CFG_DIRCMP2_MASK)
1283 #define QEIV2_MATCH_CFG_DIRCMP2_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMP2_MASK) >> QEIV2_MATCH_CFG_DIRCMP2_SHIFT)
1284 
1285 /*
1286  * SPDCMP2DIS (RW)
1287  *
1288  */
1289 #define QEIV2_MATCH_CFG_SPDCMP2DIS_MASK (0x1000U)
1290 #define QEIV2_MATCH_CFG_SPDCMP2DIS_SHIFT (12U)
1291 #define QEIV2_MATCH_CFG_SPDCMP2DIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_SPDCMP2DIS_SHIFT) & QEIV2_MATCH_CFG_SPDCMP2DIS_MASK)
1292 #define QEIV2_MATCH_CFG_SPDCMP2DIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_SPDCMP2DIS_MASK) >> QEIV2_MATCH_CFG_SPDCMP2DIS_SHIFT)
1293 
1294 /*
1295  * PHASE_MATCH_DIS2 (RW)
1296  *
1297  */
1298 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_MASK (0x800U)
1299 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SHIFT (11U)
1300 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SHIFT) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_MASK)
1301 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_MASK) >> QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SHIFT)
1302 
1303 /*
1304  * POS_MATCH2_DIR (RW)
1305  *
1306  */
1307 #define QEIV2_MATCH_CFG_POS_MATCH2_DIR_MASK (0x400U)
1308 #define QEIV2_MATCH_CFG_POS_MATCH2_DIR_SHIFT (10U)
1309 #define QEIV2_MATCH_CFG_POS_MATCH2_DIR_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH2_DIR_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH2_DIR_MASK)
1310 #define QEIV2_MATCH_CFG_POS_MATCH2_DIR_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH2_DIR_MASK) >> QEIV2_MATCH_CFG_POS_MATCH2_DIR_SHIFT)
1311 
1312 /*
1313  * POS_MATCH2_OPT (RW)
1314  *
1315  */
1316 #define QEIV2_MATCH_CFG_POS_MATCH2_OPT_MASK (0x200U)
1317 #define QEIV2_MATCH_CFG_POS_MATCH2_OPT_SHIFT (9U)
1318 #define QEIV2_MATCH_CFG_POS_MATCH2_OPT_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH2_OPT_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH2_OPT_MASK)
1319 #define QEIV2_MATCH_CFG_POS_MATCH2_OPT_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH2_OPT_MASK) >> QEIV2_MATCH_CFG_POS_MATCH2_OPT_SHIFT)
1320 
1321 /* Bitfield definition for register array: FILT_CFG */
1322 /*
1323  * OUTINV (RW)
1324  *
1325  * 1- Filter will invert the output
1326  * 0- Filter will not invert the output
1327  */
1328 #define QEIV2_FILT_CFG_OUTINV_MASK (0x10000UL)
1329 #define QEIV2_FILT_CFG_OUTINV_SHIFT (16U)
1330 #define QEIV2_FILT_CFG_OUTINV_SET(x) (((uint32_t)(x) << QEIV2_FILT_CFG_OUTINV_SHIFT) & QEIV2_FILT_CFG_OUTINV_MASK)
1331 #define QEIV2_FILT_CFG_OUTINV_GET(x) (((uint32_t)(x) & QEIV2_FILT_CFG_OUTINV_MASK) >> QEIV2_FILT_CFG_OUTINV_SHIFT)
1332 
1333 /*
1334  * MODE (RW)
1335  *
1336  * This bitfields defines the filter mode
1337  * 000-bypass;
1338  * 100-rapid change mode;
1339  * 101-delay filter mode;
1340  * 110-stable low mode;
1341  * 111-stable high mode
1342  */
1343 #define QEIV2_FILT_CFG_MODE_MASK (0xE000U)
1344 #define QEIV2_FILT_CFG_MODE_SHIFT (13U)
1345 #define QEIV2_FILT_CFG_MODE_SET(x) (((uint32_t)(x) << QEIV2_FILT_CFG_MODE_SHIFT) & QEIV2_FILT_CFG_MODE_MASK)
1346 #define QEIV2_FILT_CFG_MODE_GET(x) (((uint32_t)(x) & QEIV2_FILT_CFG_MODE_MASK) >> QEIV2_FILT_CFG_MODE_SHIFT)
1347 
1348 /*
1349  * SYNCEN (RW)
1350  *
1351  * set to enable sychronization input signal with TRGM clock
1352  */
1353 #define QEIV2_FILT_CFG_SYNCEN_MASK (0x1000U)
1354 #define QEIV2_FILT_CFG_SYNCEN_SHIFT (12U)
1355 #define QEIV2_FILT_CFG_SYNCEN_SET(x) (((uint32_t)(x) << QEIV2_FILT_CFG_SYNCEN_SHIFT) & QEIV2_FILT_CFG_SYNCEN_MASK)
1356 #define QEIV2_FILT_CFG_SYNCEN_GET(x) (((uint32_t)(x) & QEIV2_FILT_CFG_SYNCEN_MASK) >> QEIV2_FILT_CFG_SYNCEN_SHIFT)
1357 
1358 /*
1359  * FILTLEN (RW)
1360  *
1361  * This bitfields defines the filter counter length.
1362  */
1363 #define QEIV2_FILT_CFG_FILTLEN_MASK (0xFFFU)
1364 #define QEIV2_FILT_CFG_FILTLEN_SHIFT (0U)
1365 #define QEIV2_FILT_CFG_FILTLEN_SET(x) (((uint32_t)(x) << QEIV2_FILT_CFG_FILTLEN_SHIFT) & QEIV2_FILT_CFG_FILTLEN_MASK)
1366 #define QEIV2_FILT_CFG_FILTLEN_GET(x) (((uint32_t)(x) & QEIV2_FILT_CFG_FILTLEN_MASK) >> QEIV2_FILT_CFG_FILTLEN_SHIFT)
1367 
1368 /* Bitfield definition for register: QEI_CFG */
1369 /*
1370  * SW_PULSE0_RESTART (RW)
1371  *
1372  * set to restart cycle counter for configed pulse_num. HW auto clear
1373  */
1374 #define QEIV2_QEI_CFG_SW_PULSE0_RESTART_MASK (0x80000000UL)
1375 #define QEIV2_QEI_CFG_SW_PULSE0_RESTART_SHIFT (31U)
1376 #define QEIV2_QEI_CFG_SW_PULSE0_RESTART_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SW_PULSE0_RESTART_SHIFT) & QEIV2_QEI_CFG_SW_PULSE0_RESTART_MASK)
1377 #define QEIV2_QEI_CFG_SW_PULSE0_RESTART_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SW_PULSE0_RESTART_MASK) >> QEIV2_QEI_CFG_SW_PULSE0_RESTART_SHIFT)
1378 
1379 /*
1380  * SW_PULSE1_RESTART (RW)
1381  *
1382  */
1383 #define QEIV2_QEI_CFG_SW_PULSE1_RESTART_MASK (0x40000000UL)
1384 #define QEIV2_QEI_CFG_SW_PULSE1_RESTART_SHIFT (30U)
1385 #define QEIV2_QEI_CFG_SW_PULSE1_RESTART_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SW_PULSE1_RESTART_SHIFT) & QEIV2_QEI_CFG_SW_PULSE1_RESTART_MASK)
1386 #define QEIV2_QEI_CFG_SW_PULSE1_RESTART_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SW_PULSE1_RESTART_MASK) >> QEIV2_QEI_CFG_SW_PULSE1_RESTART_SHIFT)
1387 
1388 /*
1389  * SW_CYCLE0_RESTART (RW)
1390  *
1391  * set to restart pulse counter for configed cycle_num. HW auto clear
1392  */
1393 #define QEIV2_QEI_CFG_SW_CYCLE0_RESTART_MASK (0x20000000UL)
1394 #define QEIV2_QEI_CFG_SW_CYCLE0_RESTART_SHIFT (29U)
1395 #define QEIV2_QEI_CFG_SW_CYCLE0_RESTART_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SW_CYCLE0_RESTART_SHIFT) & QEIV2_QEI_CFG_SW_CYCLE0_RESTART_MASK)
1396 #define QEIV2_QEI_CFG_SW_CYCLE0_RESTART_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SW_CYCLE0_RESTART_MASK) >> QEIV2_QEI_CFG_SW_CYCLE0_RESTART_SHIFT)
1397 
1398 /*
1399  * SW_CYCLE1_RESTART (RW)
1400  *
1401  */
1402 #define QEIV2_QEI_CFG_SW_CYCLE1_RESTART_MASK (0x10000000UL)
1403 #define QEIV2_QEI_CFG_SW_CYCLE1_RESTART_SHIFT (28U)
1404 #define QEIV2_QEI_CFG_SW_CYCLE1_RESTART_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SW_CYCLE1_RESTART_SHIFT) & QEIV2_QEI_CFG_SW_CYCLE1_RESTART_MASK)
1405 #define QEIV2_QEI_CFG_SW_CYCLE1_RESTART_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SW_CYCLE1_RESTART_MASK) >> QEIV2_QEI_CFG_SW_CYCLE1_RESTART_SHIFT)
1406 
1407 /*
1408  * PULSE0_ONESHOT (RW)
1409  *
1410  * set to use oneshot mode for configed pulse_num
1411  */
1412 #define QEIV2_QEI_CFG_PULSE0_ONESHOT_MASK (0x80000UL)
1413 #define QEIV2_QEI_CFG_PULSE0_ONESHOT_SHIFT (19U)
1414 #define QEIV2_QEI_CFG_PULSE0_ONESHOT_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_PULSE0_ONESHOT_SHIFT) & QEIV2_QEI_CFG_PULSE0_ONESHOT_MASK)
1415 #define QEIV2_QEI_CFG_PULSE0_ONESHOT_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_PULSE0_ONESHOT_MASK) >> QEIV2_QEI_CFG_PULSE0_ONESHOT_SHIFT)
1416 
1417 /*
1418  * PULSE1_ONESHOT (RW)
1419  *
1420  */
1421 #define QEIV2_QEI_CFG_PULSE1_ONESHOT_MASK (0x40000UL)
1422 #define QEIV2_QEI_CFG_PULSE1_ONESHOT_SHIFT (18U)
1423 #define QEIV2_QEI_CFG_PULSE1_ONESHOT_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_PULSE1_ONESHOT_SHIFT) & QEIV2_QEI_CFG_PULSE1_ONESHOT_MASK)
1424 #define QEIV2_QEI_CFG_PULSE1_ONESHOT_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_PULSE1_ONESHOT_MASK) >> QEIV2_QEI_CFG_PULSE1_ONESHOT_SHIFT)
1425 
1426 /*
1427  * CYCLE0_ONESHOT (RW)
1428  *
1429  * set to use oneshot mode for configed cycle_num
1430  */
1431 #define QEIV2_QEI_CFG_CYCLE0_ONESHOT_MASK (0x20000UL)
1432 #define QEIV2_QEI_CFG_CYCLE0_ONESHOT_SHIFT (17U)
1433 #define QEIV2_QEI_CFG_CYCLE0_ONESHOT_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_CYCLE0_ONESHOT_SHIFT) & QEIV2_QEI_CFG_CYCLE0_ONESHOT_MASK)
1434 #define QEIV2_QEI_CFG_CYCLE0_ONESHOT_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_CYCLE0_ONESHOT_MASK) >> QEIV2_QEI_CFG_CYCLE0_ONESHOT_SHIFT)
1435 
1436 /*
1437  * CYCLE1_ONESHOT (RW)
1438  *
1439  */
1440 #define QEIV2_QEI_CFG_CYCLE1_ONESHOT_MASK (0x10000UL)
1441 #define QEIV2_QEI_CFG_CYCLE1_ONESHOT_SHIFT (16U)
1442 #define QEIV2_QEI_CFG_CYCLE1_ONESHOT_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_CYCLE1_ONESHOT_SHIFT) & QEIV2_QEI_CFG_CYCLE1_ONESHOT_MASK)
1443 #define QEIV2_QEI_CFG_CYCLE1_ONESHOT_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_CYCLE1_ONESHOT_MASK) >> QEIV2_QEI_CFG_CYCLE1_ONESHOT_SHIFT)
1444 
1445 /*
1446  * SPEED_DIR_CHG_EN (RW)
1447  *
1448  * clear counter if detect direction change
1449  */
1450 #define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK (0x1000U)
1451 #define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SHIFT (12U)
1452 #define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SHIFT) & QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK)
1453 #define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK) >> QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SHIFT)
1454 
1455 /*
1456  * TRIG_PULSE0_EN (RW)
1457  *
1458  * set to enable trigger start cycle counter for configed pulse_num(from the selected edge)
1459  */
1460 #define QEIV2_QEI_CFG_TRIG_PULSE0_EN_MASK (0x800U)
1461 #define QEIV2_QEI_CFG_TRIG_PULSE0_EN_SHIFT (11U)
1462 #define QEIV2_QEI_CFG_TRIG_PULSE0_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_TRIG_PULSE0_EN_SHIFT) & QEIV2_QEI_CFG_TRIG_PULSE0_EN_MASK)
1463 #define QEIV2_QEI_CFG_TRIG_PULSE0_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_TRIG_PULSE0_EN_MASK) >> QEIV2_QEI_CFG_TRIG_PULSE0_EN_SHIFT)
1464 
1465 /*
1466  * TRIG_PULSE1_EN (RW)
1467  *
1468  */
1469 #define QEIV2_QEI_CFG_TRIG_PULSE1_EN_MASK (0x400U)
1470 #define QEIV2_QEI_CFG_TRIG_PULSE1_EN_SHIFT (10U)
1471 #define QEIV2_QEI_CFG_TRIG_PULSE1_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_TRIG_PULSE1_EN_SHIFT) & QEIV2_QEI_CFG_TRIG_PULSE1_EN_MASK)
1472 #define QEIV2_QEI_CFG_TRIG_PULSE1_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_TRIG_PULSE1_EN_MASK) >> QEIV2_QEI_CFG_TRIG_PULSE1_EN_SHIFT)
1473 
1474 /*
1475  * TRIG_CYCLE0_EN (RW)
1476  *
1477  * set to enable trigger start pulse counter for configed cycle_num
1478  */
1479 #define QEIV2_QEI_CFG_TRIG_CYCLE0_EN_MASK (0x200U)
1480 #define QEIV2_QEI_CFG_TRIG_CYCLE0_EN_SHIFT (9U)
1481 #define QEIV2_QEI_CFG_TRIG_CYCLE0_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_TRIG_CYCLE0_EN_SHIFT) & QEIV2_QEI_CFG_TRIG_CYCLE0_EN_MASK)
1482 #define QEIV2_QEI_CFG_TRIG_CYCLE0_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_TRIG_CYCLE0_EN_MASK) >> QEIV2_QEI_CFG_TRIG_CYCLE0_EN_SHIFT)
1483 
1484 /*
1485  * TRIG_CYCLE1_EN (RW)
1486  *
1487  */
1488 #define QEIV2_QEI_CFG_TRIG_CYCLE1_EN_MASK (0x100U)
1489 #define QEIV2_QEI_CFG_TRIG_CYCLE1_EN_SHIFT (8U)
1490 #define QEIV2_QEI_CFG_TRIG_CYCLE1_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_TRIG_CYCLE1_EN_SHIFT) & QEIV2_QEI_CFG_TRIG_CYCLE1_EN_MASK)
1491 #define QEIV2_QEI_CFG_TRIG_CYCLE1_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_TRIG_CYCLE1_EN_MASK) >> QEIV2_QEI_CFG_TRIG_CYCLE1_EN_SHIFT)
1492 
1493 /*
1494  * UVW_POS_OPT0 (RW)
1495  *
1496  * set to output next area position for QEO use;
1497  * clr to output exact point position for MMC use
1498  */
1499 #define QEIV2_QEI_CFG_UVW_POS_OPT0_MASK (0x20U)
1500 #define QEIV2_QEI_CFG_UVW_POS_OPT0_SHIFT (5U)
1501 #define QEIV2_QEI_CFG_UVW_POS_OPT0_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_UVW_POS_OPT0_SHIFT) & QEIV2_QEI_CFG_UVW_POS_OPT0_MASK)
1502 #define QEIV2_QEI_CFG_UVW_POS_OPT0_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_UVW_POS_OPT0_MASK) >> QEIV2_QEI_CFG_UVW_POS_OPT0_SHIFT)
1503 
1504 /*
1505  * NEGEDGE_EN (RW)
1506  *
1507  * bit4: negedge enable
1508  * bit3: posedge enable
1509  * bit2: W in hal enable
1510  * bit1: signal b(or V in hal) enable
1511  * bit0: signal a(or U in hal) enable
1512  * such as:
1513  * 01001: use posedge A
1514  * 11010: use both edge of signal B
1515  * 11111: use both edge of all HAL siganls
1516  */
1517 #define QEIV2_QEI_CFG_NEGEDGE_EN_MASK (0x10U)
1518 #define QEIV2_QEI_CFG_NEGEDGE_EN_SHIFT (4U)
1519 #define QEIV2_QEI_CFG_NEGEDGE_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_NEGEDGE_EN_SHIFT) & QEIV2_QEI_CFG_NEGEDGE_EN_MASK)
1520 #define QEIV2_QEI_CFG_NEGEDGE_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_NEGEDGE_EN_MASK) >> QEIV2_QEI_CFG_NEGEDGE_EN_SHIFT)
1521 
1522 /*
1523  * POSIDGE_EN (RW)
1524  *
1525  */
1526 #define QEIV2_QEI_CFG_POSIDGE_EN_MASK (0x8U)
1527 #define QEIV2_QEI_CFG_POSIDGE_EN_SHIFT (3U)
1528 #define QEIV2_QEI_CFG_POSIDGE_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_POSIDGE_EN_SHIFT) & QEIV2_QEI_CFG_POSIDGE_EN_MASK)
1529 #define QEIV2_QEI_CFG_POSIDGE_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_POSIDGE_EN_MASK) >> QEIV2_QEI_CFG_POSIDGE_EN_SHIFT)
1530 
1531 /*
1532  * SIGZ_EN (RW)
1533  *
1534  */
1535 #define QEIV2_QEI_CFG_SIGZ_EN_MASK (0x4U)
1536 #define QEIV2_QEI_CFG_SIGZ_EN_SHIFT (2U)
1537 #define QEIV2_QEI_CFG_SIGZ_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SIGZ_EN_SHIFT) & QEIV2_QEI_CFG_SIGZ_EN_MASK)
1538 #define QEIV2_QEI_CFG_SIGZ_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SIGZ_EN_MASK) >> QEIV2_QEI_CFG_SIGZ_EN_SHIFT)
1539 
1540 /*
1541  * SIGB_EN (RW)
1542  *
1543  */
1544 #define QEIV2_QEI_CFG_SIGB_EN_MASK (0x2U)
1545 #define QEIV2_QEI_CFG_SIGB_EN_SHIFT (1U)
1546 #define QEIV2_QEI_CFG_SIGB_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SIGB_EN_SHIFT) & QEIV2_QEI_CFG_SIGB_EN_MASK)
1547 #define QEIV2_QEI_CFG_SIGB_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SIGB_EN_MASK) >> QEIV2_QEI_CFG_SIGB_EN_SHIFT)
1548 
1549 /*
1550  * SIGA_EN (RW)
1551  *
1552  */
1553 #define QEIV2_QEI_CFG_SIGA_EN_MASK (0x1U)
1554 #define QEIV2_QEI_CFG_SIGA_EN_SHIFT (0U)
1555 #define QEIV2_QEI_CFG_SIGA_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SIGA_EN_SHIFT) & QEIV2_QEI_CFG_SIGA_EN_MASK)
1556 #define QEIV2_QEI_CFG_SIGA_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SIGA_EN_MASK) >> QEIV2_QEI_CFG_SIGA_EN_SHIFT)
1557 
1558 /* Bitfield definition for register: PULSE0_NUM */
1559 /*
1560  * PULSE0_NUM (RW)
1561  *
1562  * for speed detection, will count the cycle number for configed pulse_num
1563  */
1564 #define QEIV2_PULSE0_NUM_PULSE0_NUM_MASK (0xFFFFFFFFUL)
1565 #define QEIV2_PULSE0_NUM_PULSE0_NUM_SHIFT (0U)
1566 #define QEIV2_PULSE0_NUM_PULSE0_NUM_SET(x) (((uint32_t)(x) << QEIV2_PULSE0_NUM_PULSE0_NUM_SHIFT) & QEIV2_PULSE0_NUM_PULSE0_NUM_MASK)
1567 #define QEIV2_PULSE0_NUM_PULSE0_NUM_GET(x) (((uint32_t)(x) & QEIV2_PULSE0_NUM_PULSE0_NUM_MASK) >> QEIV2_PULSE0_NUM_PULSE0_NUM_SHIFT)
1568 
1569 /* Bitfield definition for register: PULSE1_NUM */
1570 /*
1571  * PULSE1_NUM (RW)
1572  *
1573  */
1574 #define QEIV2_PULSE1_NUM_PULSE1_NUM_MASK (0xFFFFFFFFUL)
1575 #define QEIV2_PULSE1_NUM_PULSE1_NUM_SHIFT (0U)
1576 #define QEIV2_PULSE1_NUM_PULSE1_NUM_SET(x) (((uint32_t)(x) << QEIV2_PULSE1_NUM_PULSE1_NUM_SHIFT) & QEIV2_PULSE1_NUM_PULSE1_NUM_MASK)
1577 #define QEIV2_PULSE1_NUM_PULSE1_NUM_GET(x) (((uint32_t)(x) & QEIV2_PULSE1_NUM_PULSE1_NUM_MASK) >> QEIV2_PULSE1_NUM_PULSE1_NUM_SHIFT)
1578 
1579 /* Bitfield definition for register: CYCLE0_CNT */
1580 /*
1581  * CYCLE0_CNT (RO)
1582  *
1583  */
1584 #define QEIV2_CYCLE0_CNT_CYCLE0_CNT_MASK (0xFFFFFFFFUL)
1585 #define QEIV2_CYCLE0_CNT_CYCLE0_CNT_SHIFT (0U)
1586 #define QEIV2_CYCLE0_CNT_CYCLE0_CNT_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0_CNT_CYCLE0_CNT_MASK) >> QEIV2_CYCLE0_CNT_CYCLE0_CNT_SHIFT)
1587 
1588 /* Bitfield definition for register: CYCLE0PULSE_CNT */
1589 /*
1590  * CYCLE0PULSE_CNT (RO)
1591  *
1592  */
1593 #define QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_MASK (0xFFFFFFFFUL)
1594 #define QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_SHIFT (0U)
1595 #define QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_MASK) >> QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_SHIFT)
1596 
1597 /* Bitfield definition for register: CYCLE1_CNT */
1598 /*
1599  * CYCLE1_CNT (RO)
1600  *
1601  */
1602 #define QEIV2_CYCLE1_CNT_CYCLE1_CNT_MASK (0xFFFFFFFFUL)
1603 #define QEIV2_CYCLE1_CNT_CYCLE1_CNT_SHIFT (0U)
1604 #define QEIV2_CYCLE1_CNT_CYCLE1_CNT_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1_CNT_CYCLE1_CNT_MASK) >> QEIV2_CYCLE1_CNT_CYCLE1_CNT_SHIFT)
1605 
1606 /* Bitfield definition for register: CYCLE1PULSE_CNT */
1607 /*
1608  * CYCLE1PULSE_CNT (RO)
1609  *
1610  */
1611 #define QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_MASK (0xFFFFFFFFUL)
1612 #define QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_SHIFT (0U)
1613 #define QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_MASK) >> QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_SHIFT)
1614 
1615 /* Bitfield definition for register: CYCLE0_SNAP0 */
1616 /*
1617  * CYCLE0_SNAP0 (RO)
1618  *
1619  */
1620 #define QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_MASK (0xFFFFFFFFUL)
1621 #define QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_SHIFT (0U)
1622 #define QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_MASK) >> QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_SHIFT)
1623 
1624 /* Bitfield definition for register: CYCLE0_SNAP1 */
1625 /*
1626  * CYCLE0_SNAP1 (RO)
1627  *
1628  */
1629 #define QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_MASK (0xFFFFFFFFUL)
1630 #define QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_SHIFT (0U)
1631 #define QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_MASK) >> QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_SHIFT)
1632 
1633 /* Bitfield definition for register: CYCLE1_SNAP0 */
1634 /*
1635  * CYCLE1_SNAP0 (RO)
1636  *
1637  */
1638 #define QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_MASK (0xFFFFFFFFUL)
1639 #define QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_SHIFT (0U)
1640 #define QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_MASK) >> QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_SHIFT)
1641 
1642 /* Bitfield definition for register: CYCLE1_SNAP1 */
1643 /*
1644  * CYCLE1_SNAP1 (RO)
1645  *
1646  */
1647 #define QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_MASK (0xFFFFFFFFUL)
1648 #define QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_SHIFT (0U)
1649 #define QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_MASK) >> QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_SHIFT)
1650 
1651 /* Bitfield definition for register: CYCLE0_NUM */
1652 /*
1653  * CYCLE0_NUM (RW)
1654  *
1655  */
1656 #define QEIV2_CYCLE0_NUM_CYCLE0_NUM_MASK (0xFFFFFFFFUL)
1657 #define QEIV2_CYCLE0_NUM_CYCLE0_NUM_SHIFT (0U)
1658 #define QEIV2_CYCLE0_NUM_CYCLE0_NUM_SET(x) (((uint32_t)(x) << QEIV2_CYCLE0_NUM_CYCLE0_NUM_SHIFT) & QEIV2_CYCLE0_NUM_CYCLE0_NUM_MASK)
1659 #define QEIV2_CYCLE0_NUM_CYCLE0_NUM_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0_NUM_CYCLE0_NUM_MASK) >> QEIV2_CYCLE0_NUM_CYCLE0_NUM_SHIFT)
1660 
1661 /* Bitfield definition for register: CYCLE1_NUM */
1662 /*
1663  * CYCLE1_NUM (RW)
1664  *
1665  */
1666 #define QEIV2_CYCLE1_NUM_CYCLE1_NUM_MASK (0xFFFFFFFFUL)
1667 #define QEIV2_CYCLE1_NUM_CYCLE1_NUM_SHIFT (0U)
1668 #define QEIV2_CYCLE1_NUM_CYCLE1_NUM_SET(x) (((uint32_t)(x) << QEIV2_CYCLE1_NUM_CYCLE1_NUM_SHIFT) & QEIV2_CYCLE1_NUM_CYCLE1_NUM_MASK)
1669 #define QEIV2_CYCLE1_NUM_CYCLE1_NUM_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1_NUM_CYCLE1_NUM_MASK) >> QEIV2_CYCLE1_NUM_CYCLE1_NUM_SHIFT)
1670 
1671 /* Bitfield definition for register: PULSE0_CNT */
1672 /*
1673  * PULSE0_CNT (RO)
1674  *
1675  */
1676 #define QEIV2_PULSE0_CNT_PULSE0_CNT_MASK (0xFFFFFFFFUL)
1677 #define QEIV2_PULSE0_CNT_PULSE0_CNT_SHIFT (0U)
1678 #define QEIV2_PULSE0_CNT_PULSE0_CNT_GET(x) (((uint32_t)(x) & QEIV2_PULSE0_CNT_PULSE0_CNT_MASK) >> QEIV2_PULSE0_CNT_PULSE0_CNT_SHIFT)
1679 
1680 /* Bitfield definition for register: PULSE0CYCLE_CNT */
1681 /*
1682  * PULSE0CYCLE_CNT (RO)
1683  *
1684  */
1685 #define QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_MASK (0xFFFFFFFFUL)
1686 #define QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_SHIFT (0U)
1687 #define QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_GET(x) (((uint32_t)(x) & QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_MASK) >> QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_SHIFT)
1688 
1689 /* Bitfield definition for register: PULSE1_CNT */
1690 /*
1691  * PULSE1_CNT (RO)
1692  *
1693  */
1694 #define QEIV2_PULSE1_CNT_PULSE1_CNT_MASK (0xFFFFFFFFUL)
1695 #define QEIV2_PULSE1_CNT_PULSE1_CNT_SHIFT (0U)
1696 #define QEIV2_PULSE1_CNT_PULSE1_CNT_GET(x) (((uint32_t)(x) & QEIV2_PULSE1_CNT_PULSE1_CNT_MASK) >> QEIV2_PULSE1_CNT_PULSE1_CNT_SHIFT)
1697 
1698 /* Bitfield definition for register: PULSE1CYCLE_CNT */
1699 /*
1700  * PULSE1CYCLE_CNT (RO)
1701  *
1702  */
1703 #define QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_MASK (0xFFFFFFFFUL)
1704 #define QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_SHIFT (0U)
1705 #define QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_GET(x) (((uint32_t)(x) & QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_MASK) >> QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_SHIFT)
1706 
1707 /* Bitfield definition for register: PULSE0_SNAP0 */
1708 /*
1709  * PULSE0_SNAP0 (RO)
1710  *
1711  */
1712 #define QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_MASK (0xFFFFFFFFUL)
1713 #define QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_SHIFT (0U)
1714 #define QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_MASK) >> QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_SHIFT)
1715 
1716 /* Bitfield definition for register: PULSE0CYCLE_SNAP0 */
1717 /*
1718  * PULSE0CYCLE_SNAP0 (RO)
1719  *
1720  */
1721 #define QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_MASK (0xFFFFFFFFUL)
1722 #define QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_SHIFT (0U)
1723 #define QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_MASK) >> QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_SHIFT)
1724 
1725 /* Bitfield definition for register: PULSE0_SNAP1 */
1726 /*
1727  * PULSE0_SNAP1 (RO)
1728  *
1729  */
1730 #define QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_MASK (0xFFFFFFFFUL)
1731 #define QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_SHIFT (0U)
1732 #define QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_MASK) >> QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_SHIFT)
1733 
1734 /* Bitfield definition for register: PULSE0CYCLE_SNAP1 */
1735 /*
1736  * PULSE0CYCLE_SNAP1 (RO)
1737  *
1738  */
1739 #define QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_MASK (0xFFFFFFFFUL)
1740 #define QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_SHIFT (0U)
1741 #define QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_MASK) >> QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_SHIFT)
1742 
1743 /* Bitfield definition for register: PULSE1_SNAP0 */
1744 /*
1745  * PULSE1_SNAP0 (RO)
1746  *
1747  */
1748 #define QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_MASK (0xFFFFFFFFUL)
1749 #define QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_SHIFT (0U)
1750 #define QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_MASK) >> QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_SHIFT)
1751 
1752 /* Bitfield definition for register: PULSE1CYCLE_SNAP0 */
1753 /*
1754  * PULSE1CYCLE_SNAP0 (RO)
1755  *
1756  */
1757 #define QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_MASK (0xFFFFFFFFUL)
1758 #define QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_SHIFT (0U)
1759 #define QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_MASK) >> QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_SHIFT)
1760 
1761 /* Bitfield definition for register: PULSE1_SNAP1 */
1762 /*
1763  * PULSE1_SNAP1 (RO)
1764  *
1765  */
1766 #define QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_MASK (0xFFFFFFFFUL)
1767 #define QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_SHIFT (0U)
1768 #define QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_MASK) >> QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_SHIFT)
1769 
1770 /* Bitfield definition for register: PULSE1CYCLE_SNAP1 */
1771 /*
1772  * PULSE1CYCLE_SNAP1 (RO)
1773  *
1774  */
1775 #define QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_MASK (0xFFFFFFFFUL)
1776 #define QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_SHIFT (0U)
1777 #define QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_MASK) >> QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_SHIFT)
1778 
1779 /* Bitfield definition for register: TIMESTAMP */
1780 /*
1781  * TIMESTAMP (RO)
1782  *
1783  * for SIN/COS mode, it saves the timestampe of the begining of first ADC sample time;
1784  * for ABZ mode, it saves the timestampe of edge of input signals
1785  */
1786 #define QEIV2_TIMESTAMP_TIMESTAMP_MASK (0xFFFFFFFFUL)
1787 #define QEIV2_TIMESTAMP_TIMESTAMP_SHIFT (0U)
1788 #define QEIV2_TIMESTAMP_TIMESTAMP_GET(x) (((uint32_t)(x) & QEIV2_TIMESTAMP_TIMESTAMP_MASK) >> QEIV2_TIMESTAMP_TIMESTAMP_SHIFT)
1789 
1790 /* Bitfield definition for register: ADC_THRESHOLD */
1791 /*
1792  * LOW_LIMIT (RW)
1793  *
1794  * for SINCOS mode, if (max+min/2) of the two adc result, is small than limit,
1795  * then this value is treated as unvalid, no position output.
1796  * this is uesd to avoid wrong adc resule(such as 0 or same sin cos value)
1797  */
1798 #define QEIV2_ADC_THRESHOLD_LOW_LIMIT_MASK (0xFFFF0000UL)
1799 #define QEIV2_ADC_THRESHOLD_LOW_LIMIT_SHIFT (16U)
1800 #define QEIV2_ADC_THRESHOLD_LOW_LIMIT_SET(x) (((uint32_t)(x) << QEIV2_ADC_THRESHOLD_LOW_LIMIT_SHIFT) & QEIV2_ADC_THRESHOLD_LOW_LIMIT_MASK)
1801 #define QEIV2_ADC_THRESHOLD_LOW_LIMIT_GET(x) (((uint32_t)(x) & QEIV2_ADC_THRESHOLD_LOW_LIMIT_MASK) >> QEIV2_ADC_THRESHOLD_LOW_LIMIT_SHIFT)
1802 
1803 /*
1804  * HIGH_LIMIT (RW)
1805  *
1806  * high limit for SINCOS mode adc result
1807  */
1808 #define QEIV2_ADC_THRESHOLD_HIGH_LIMIT_MASK (0xFFFFU)
1809 #define QEIV2_ADC_THRESHOLD_HIGH_LIMIT_SHIFT (0U)
1810 #define QEIV2_ADC_THRESHOLD_HIGH_LIMIT_SET(x) (((uint32_t)(x) << QEIV2_ADC_THRESHOLD_HIGH_LIMIT_SHIFT) & QEIV2_ADC_THRESHOLD_HIGH_LIMIT_MASK)
1811 #define QEIV2_ADC_THRESHOLD_HIGH_LIMIT_GET(x) (((uint32_t)(x) & QEIV2_ADC_THRESHOLD_HIGH_LIMIT_MASK) >> QEIV2_ADC_THRESHOLD_HIGH_LIMIT_SHIFT)
1812 
1813 /* Bitfield definition for register: ADCX_CFG0 */
1814 /*
1815  * X_ADCSEL (RW)
1816  *
1817  */
1818 #define QEIV2_ADCX_CFG0_X_ADCSEL_MASK (0x100U)
1819 #define QEIV2_ADCX_CFG0_X_ADCSEL_SHIFT (8U)
1820 #define QEIV2_ADCX_CFG0_X_ADCSEL_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG0_X_ADCSEL_SHIFT) & QEIV2_ADCX_CFG0_X_ADCSEL_MASK)
1821 #define QEIV2_ADCX_CFG0_X_ADCSEL_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG0_X_ADCSEL_MASK) >> QEIV2_ADCX_CFG0_X_ADCSEL_SHIFT)
1822 
1823 /*
1824  * X_ADC_ENABLE (RW)
1825  *
1826  */
1827 #define QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK (0x80U)
1828 #define QEIV2_ADCX_CFG0_X_ADC_ENABLE_SHIFT (7U)
1829 #define QEIV2_ADCX_CFG0_X_ADC_ENABLE_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG0_X_ADC_ENABLE_SHIFT) & QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK)
1830 #define QEIV2_ADCX_CFG0_X_ADC_ENABLE_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK) >> QEIV2_ADCX_CFG0_X_ADC_ENABLE_SHIFT)
1831 
1832 /*
1833  * X_CHAN (RW)
1834  *
1835  */
1836 #define QEIV2_ADCX_CFG0_X_CHAN_MASK (0x1FU)
1837 #define QEIV2_ADCX_CFG0_X_CHAN_SHIFT (0U)
1838 #define QEIV2_ADCX_CFG0_X_CHAN_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG0_X_CHAN_SHIFT) & QEIV2_ADCX_CFG0_X_CHAN_MASK)
1839 #define QEIV2_ADCX_CFG0_X_CHAN_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG0_X_CHAN_MASK) >> QEIV2_ADCX_CFG0_X_CHAN_SHIFT)
1840 
1841 /* Bitfield definition for register: ADCX_CFG1 */
1842 /*
1843  * X_PARAM1 (RW)
1844  *
1845  */
1846 #define QEIV2_ADCX_CFG1_X_PARAM1_MASK (0xFFFF0000UL)
1847 #define QEIV2_ADCX_CFG1_X_PARAM1_SHIFT (16U)
1848 #define QEIV2_ADCX_CFG1_X_PARAM1_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG1_X_PARAM1_SHIFT) & QEIV2_ADCX_CFG1_X_PARAM1_MASK)
1849 #define QEIV2_ADCX_CFG1_X_PARAM1_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG1_X_PARAM1_MASK) >> QEIV2_ADCX_CFG1_X_PARAM1_SHIFT)
1850 
1851 /*
1852  * X_PARAM0 (RW)
1853  *
1854  */
1855 #define QEIV2_ADCX_CFG1_X_PARAM0_MASK (0xFFFFU)
1856 #define QEIV2_ADCX_CFG1_X_PARAM0_SHIFT (0U)
1857 #define QEIV2_ADCX_CFG1_X_PARAM0_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG1_X_PARAM0_SHIFT) & QEIV2_ADCX_CFG1_X_PARAM0_MASK)
1858 #define QEIV2_ADCX_CFG1_X_PARAM0_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG1_X_PARAM0_MASK) >> QEIV2_ADCX_CFG1_X_PARAM0_SHIFT)
1859 
1860 /* Bitfield definition for register: ADCX_CFG2 */
1861 /*
1862  * X_OFFSET (RW)
1863  *
1864  */
1865 #define QEIV2_ADCX_CFG2_X_OFFSET_MASK (0xFFFFFFFFUL)
1866 #define QEIV2_ADCX_CFG2_X_OFFSET_SHIFT (0U)
1867 #define QEIV2_ADCX_CFG2_X_OFFSET_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG2_X_OFFSET_SHIFT) & QEIV2_ADCX_CFG2_X_OFFSET_MASK)
1868 #define QEIV2_ADCX_CFG2_X_OFFSET_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG2_X_OFFSET_MASK) >> QEIV2_ADCX_CFG2_X_OFFSET_SHIFT)
1869 
1870 /* Bitfield definition for register: ADCY_CFG0 */
1871 /*
1872  * Y_ADCSEL (RW)
1873  *
1874  */
1875 #define QEIV2_ADCY_CFG0_Y_ADCSEL_MASK (0x100U)
1876 #define QEIV2_ADCY_CFG0_Y_ADCSEL_SHIFT (8U)
1877 #define QEIV2_ADCY_CFG0_Y_ADCSEL_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG0_Y_ADCSEL_SHIFT) & QEIV2_ADCY_CFG0_Y_ADCSEL_MASK)
1878 #define QEIV2_ADCY_CFG0_Y_ADCSEL_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG0_Y_ADCSEL_MASK) >> QEIV2_ADCY_CFG0_Y_ADCSEL_SHIFT)
1879 
1880 /*
1881  * Y_ADC_ENABLE (RW)
1882  *
1883  */
1884 #define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK (0x80U)
1885 #define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SHIFT (7U)
1886 #define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SHIFT) & QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK)
1887 #define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK) >> QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SHIFT)
1888 
1889 /*
1890  * Y_CHAN (RW)
1891  *
1892  */
1893 #define QEIV2_ADCY_CFG0_Y_CHAN_MASK (0x1FU)
1894 #define QEIV2_ADCY_CFG0_Y_CHAN_SHIFT (0U)
1895 #define QEIV2_ADCY_CFG0_Y_CHAN_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG0_Y_CHAN_SHIFT) & QEIV2_ADCY_CFG0_Y_CHAN_MASK)
1896 #define QEIV2_ADCY_CFG0_Y_CHAN_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG0_Y_CHAN_MASK) >> QEIV2_ADCY_CFG0_Y_CHAN_SHIFT)
1897 
1898 /* Bitfield definition for register: ADCY_CFG1 */
1899 /*
1900  * Y_PARAM1 (RW)
1901  *
1902  */
1903 #define QEIV2_ADCY_CFG1_Y_PARAM1_MASK (0xFFFF0000UL)
1904 #define QEIV2_ADCY_CFG1_Y_PARAM1_SHIFT (16U)
1905 #define QEIV2_ADCY_CFG1_Y_PARAM1_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG1_Y_PARAM1_SHIFT) & QEIV2_ADCY_CFG1_Y_PARAM1_MASK)
1906 #define QEIV2_ADCY_CFG1_Y_PARAM1_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG1_Y_PARAM1_MASK) >> QEIV2_ADCY_CFG1_Y_PARAM1_SHIFT)
1907 
1908 /*
1909  * Y_PARAM0 (RW)
1910  *
1911  */
1912 #define QEIV2_ADCY_CFG1_Y_PARAM0_MASK (0xFFFFU)
1913 #define QEIV2_ADCY_CFG1_Y_PARAM0_SHIFT (0U)
1914 #define QEIV2_ADCY_CFG1_Y_PARAM0_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG1_Y_PARAM0_SHIFT) & QEIV2_ADCY_CFG1_Y_PARAM0_MASK)
1915 #define QEIV2_ADCY_CFG1_Y_PARAM0_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG1_Y_PARAM0_MASK) >> QEIV2_ADCY_CFG1_Y_PARAM0_SHIFT)
1916 
1917 /* Bitfield definition for register: ADCY_CFG2 */
1918 /*
1919  * Y_OFFSET (RW)
1920  *
1921  */
1922 #define QEIV2_ADCY_CFG2_Y_OFFSET_MASK (0xFFFFFFFFUL)
1923 #define QEIV2_ADCY_CFG2_Y_OFFSET_SHIFT (0U)
1924 #define QEIV2_ADCY_CFG2_Y_OFFSET_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG2_Y_OFFSET_SHIFT) & QEIV2_ADCY_CFG2_Y_OFFSET_MASK)
1925 #define QEIV2_ADCY_CFG2_Y_OFFSET_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG2_Y_OFFSET_MASK) >> QEIV2_ADCY_CFG2_Y_OFFSET_SHIFT)
1926 
1927 /* Bitfield definition for register: CAL_CFG */
1928 /*
1929  * XY_DELAY (RW)
1930  *
1931  * valid x/y delay, larger than this delay will be treated as invalid data.
1932  * Default 1.25us@200MHz; max 80ms;
1933  */
1934 #define QEIV2_CAL_CFG_XY_DELAY_MASK (0xFFFFFFUL)
1935 #define QEIV2_CAL_CFG_XY_DELAY_SHIFT (0U)
1936 #define QEIV2_CAL_CFG_XY_DELAY_SET(x) (((uint32_t)(x) << QEIV2_CAL_CFG_XY_DELAY_SHIFT) & QEIV2_CAL_CFG_XY_DELAY_MASK)
1937 #define QEIV2_CAL_CFG_XY_DELAY_GET(x) (((uint32_t)(x) & QEIV2_CAL_CFG_XY_DELAY_MASK) >> QEIV2_CAL_CFG_XY_DELAY_SHIFT)
1938 
1939 /* Bitfield definition for register: PHASE_PARAM */
1940 /*
1941  * PHASE_PARAM (RW)
1942  *
1943  */
1944 #define QEIV2_PHASE_PARAM_PHASE_PARAM_MASK (0xFFFFFFFFUL)
1945 #define QEIV2_PHASE_PARAM_PHASE_PARAM_SHIFT (0U)
1946 #define QEIV2_PHASE_PARAM_PHASE_PARAM_SET(x) (((uint32_t)(x) << QEIV2_PHASE_PARAM_PHASE_PARAM_SHIFT) & QEIV2_PHASE_PARAM_PHASE_PARAM_MASK)
1947 #define QEIV2_PHASE_PARAM_PHASE_PARAM_GET(x) (((uint32_t)(x) & QEIV2_PHASE_PARAM_PHASE_PARAM_MASK) >> QEIV2_PHASE_PARAM_PHASE_PARAM_SHIFT)
1948 
1949 /* Bitfield definition for register: POS_THRESHOLD */
1950 /*
1951  * POS_THRESHOLD (RW)
1952  *
1953  */
1954 #define QEIV2_POS_THRESHOLD_POS_THRESHOLD_MASK (0xFFFFFFFFUL)
1955 #define QEIV2_POS_THRESHOLD_POS_THRESHOLD_SHIFT (0U)
1956 #define QEIV2_POS_THRESHOLD_POS_THRESHOLD_SET(x) (((uint32_t)(x) << QEIV2_POS_THRESHOLD_POS_THRESHOLD_SHIFT) & QEIV2_POS_THRESHOLD_POS_THRESHOLD_MASK)
1957 #define QEIV2_POS_THRESHOLD_POS_THRESHOLD_GET(x) (((uint32_t)(x) & QEIV2_POS_THRESHOLD_POS_THRESHOLD_MASK) >> QEIV2_POS_THRESHOLD_POS_THRESHOLD_SHIFT)
1958 
1959 /* Bitfield definition for register array: UVW_POS */
1960 /*
1961  * UVW_POS0 (RW)
1962  *
1963  */
1964 #define QEIV2_UVW_POS_UVW_POS0_MASK (0xFFFFFFFFUL)
1965 #define QEIV2_UVW_POS_UVW_POS0_SHIFT (0U)
1966 #define QEIV2_UVW_POS_UVW_POS0_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_UVW_POS0_SHIFT) & QEIV2_UVW_POS_UVW_POS0_MASK)
1967 #define QEIV2_UVW_POS_UVW_POS0_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_UVW_POS0_MASK) >> QEIV2_UVW_POS_UVW_POS0_SHIFT)
1968 
1969 /* Bitfield definition for register array: UVW_POS_CFG */
1970 /*
1971  * POS_EN (RW)
1972  *
1973  */
1974 #define QEIV2_UVW_POS_CFG_POS_EN_MASK (0x40U)
1975 #define QEIV2_UVW_POS_CFG_POS_EN_SHIFT (6U)
1976 #define QEIV2_UVW_POS_CFG_POS_EN_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_CFG_POS_EN_SHIFT) & QEIV2_UVW_POS_CFG_POS_EN_MASK)
1977 #define QEIV2_UVW_POS_CFG_POS_EN_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_CFG_POS_EN_MASK) >> QEIV2_UVW_POS_CFG_POS_EN_SHIFT)
1978 
1979 /*
1980  * U_POS_SEL (RW)
1981  *
1982  */
1983 #define QEIV2_UVW_POS_CFG_U_POS_SEL_MASK (0x30U)
1984 #define QEIV2_UVW_POS_CFG_U_POS_SEL_SHIFT (4U)
1985 #define QEIV2_UVW_POS_CFG_U_POS_SEL_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_CFG_U_POS_SEL_SHIFT) & QEIV2_UVW_POS_CFG_U_POS_SEL_MASK)
1986 #define QEIV2_UVW_POS_CFG_U_POS_SEL_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_CFG_U_POS_SEL_MASK) >> QEIV2_UVW_POS_CFG_U_POS_SEL_SHIFT)
1987 
1988 /*
1989  * V_POS_SEL (RW)
1990  *
1991  */
1992 #define QEIV2_UVW_POS_CFG_V_POS_SEL_MASK (0xCU)
1993 #define QEIV2_UVW_POS_CFG_V_POS_SEL_SHIFT (2U)
1994 #define QEIV2_UVW_POS_CFG_V_POS_SEL_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_CFG_V_POS_SEL_SHIFT) & QEIV2_UVW_POS_CFG_V_POS_SEL_MASK)
1995 #define QEIV2_UVW_POS_CFG_V_POS_SEL_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_CFG_V_POS_SEL_MASK) >> QEIV2_UVW_POS_CFG_V_POS_SEL_SHIFT)
1996 
1997 /*
1998  * W_POS_SEL (RW)
1999  *
2000  */
2001 #define QEIV2_UVW_POS_CFG_W_POS_SEL_MASK (0x3U)
2002 #define QEIV2_UVW_POS_CFG_W_POS_SEL_SHIFT (0U)
2003 #define QEIV2_UVW_POS_CFG_W_POS_SEL_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_CFG_W_POS_SEL_SHIFT) & QEIV2_UVW_POS_CFG_W_POS_SEL_MASK)
2004 #define QEIV2_UVW_POS_CFG_W_POS_SEL_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_CFG_W_POS_SEL_MASK) >> QEIV2_UVW_POS_CFG_W_POS_SEL_SHIFT)
2005 
2006 /* Bitfield definition for register: PHASE_CNT */
2007 /*
2008  * PHASE_CNT (RW)
2009  *
2010  */
2011 #define QEIV2_PHASE_CNT_PHASE_CNT_MASK (0xFFFFFFFFUL)
2012 #define QEIV2_PHASE_CNT_PHASE_CNT_SHIFT (0U)
2013 #define QEIV2_PHASE_CNT_PHASE_CNT_SET(x) (((uint32_t)(x) << QEIV2_PHASE_CNT_PHASE_CNT_SHIFT) & QEIV2_PHASE_CNT_PHASE_CNT_MASK)
2014 #define QEIV2_PHASE_CNT_PHASE_CNT_GET(x) (((uint32_t)(x) & QEIV2_PHASE_CNT_PHASE_CNT_MASK) >> QEIV2_PHASE_CNT_PHASE_CNT_SHIFT)
2015 
2016 /* Bitfield definition for register: PHASE_UPDATE */
2017 /*
2018  * INC (WO)
2019  *
2020  * set to add value to phase_cnt
2021  */
2022 #define QEIV2_PHASE_UPDATE_INC_MASK (0x80000000UL)
2023 #define QEIV2_PHASE_UPDATE_INC_SHIFT (31U)
2024 #define QEIV2_PHASE_UPDATE_INC_SET(x) (((uint32_t)(x) << QEIV2_PHASE_UPDATE_INC_SHIFT) & QEIV2_PHASE_UPDATE_INC_MASK)
2025 #define QEIV2_PHASE_UPDATE_INC_GET(x) (((uint32_t)(x) & QEIV2_PHASE_UPDATE_INC_MASK) >> QEIV2_PHASE_UPDATE_INC_SHIFT)
2026 
2027 /*
2028  * DEC (WO)
2029  *
2030  * set to minus value from phase_cnt(set inc and dec same time willl act inc)
2031  */
2032 #define QEIV2_PHASE_UPDATE_DEC_MASK (0x40000000UL)
2033 #define QEIV2_PHASE_UPDATE_DEC_SHIFT (30U)
2034 #define QEIV2_PHASE_UPDATE_DEC_SET(x) (((uint32_t)(x) << QEIV2_PHASE_UPDATE_DEC_SHIFT) & QEIV2_PHASE_UPDATE_DEC_MASK)
2035 #define QEIV2_PHASE_UPDATE_DEC_GET(x) (((uint32_t)(x) & QEIV2_PHASE_UPDATE_DEC_MASK) >> QEIV2_PHASE_UPDATE_DEC_SHIFT)
2036 
2037 /*
2038  * VALUE (WO)
2039  *
2040  * value to be added or minus from phase_cnt. only valid when inc or dec is set in one 32bit write operation
2041  */
2042 #define QEIV2_PHASE_UPDATE_VALUE_MASK (0x3FFFFFFFUL)
2043 #define QEIV2_PHASE_UPDATE_VALUE_SHIFT (0U)
2044 #define QEIV2_PHASE_UPDATE_VALUE_SET(x) (((uint32_t)(x) << QEIV2_PHASE_UPDATE_VALUE_SHIFT) & QEIV2_PHASE_UPDATE_VALUE_MASK)
2045 #define QEIV2_PHASE_UPDATE_VALUE_GET(x) (((uint32_t)(x) & QEIV2_PHASE_UPDATE_VALUE_MASK) >> QEIV2_PHASE_UPDATE_VALUE_SHIFT)
2046 
2047 /* Bitfield definition for register: POSITION */
2048 /*
2049  * POSITION (RW)
2050  *
2051  */
2052 #define QEIV2_POSITION_POSITION_MASK (0xFFFFFFFFUL)
2053 #define QEIV2_POSITION_POSITION_SHIFT (0U)
2054 #define QEIV2_POSITION_POSITION_SET(x) (((uint32_t)(x) << QEIV2_POSITION_POSITION_SHIFT) & QEIV2_POSITION_POSITION_MASK)
2055 #define QEIV2_POSITION_POSITION_GET(x) (((uint32_t)(x) & QEIV2_POSITION_POSITION_MASK) >> QEIV2_POSITION_POSITION_SHIFT)
2056 
2057 /* Bitfield definition for register: POSITION_UPDATE */
2058 /*
2059  * INC (WO)
2060  *
2061  * set to add value to position
2062  */
2063 #define QEIV2_POSITION_UPDATE_INC_MASK (0x80000000UL)
2064 #define QEIV2_POSITION_UPDATE_INC_SHIFT (31U)
2065 #define QEIV2_POSITION_UPDATE_INC_SET(x) (((uint32_t)(x) << QEIV2_POSITION_UPDATE_INC_SHIFT) & QEIV2_POSITION_UPDATE_INC_MASK)
2066 #define QEIV2_POSITION_UPDATE_INC_GET(x) (((uint32_t)(x) & QEIV2_POSITION_UPDATE_INC_MASK) >> QEIV2_POSITION_UPDATE_INC_SHIFT)
2067 
2068 /*
2069  * DEC (WO)
2070  *
2071  * set to minus value from position(set inc and dec same time willl act inc)
2072  */
2073 #define QEIV2_POSITION_UPDATE_DEC_MASK (0x40000000UL)
2074 #define QEIV2_POSITION_UPDATE_DEC_SHIFT (30U)
2075 #define QEIV2_POSITION_UPDATE_DEC_SET(x) (((uint32_t)(x) << QEIV2_POSITION_UPDATE_DEC_SHIFT) & QEIV2_POSITION_UPDATE_DEC_MASK)
2076 #define QEIV2_POSITION_UPDATE_DEC_GET(x) (((uint32_t)(x) & QEIV2_POSITION_UPDATE_DEC_MASK) >> QEIV2_POSITION_UPDATE_DEC_SHIFT)
2077 
2078 /*
2079  * VALUE (WO)
2080  *
2081  * value to be added or minus from position. only valid when inc or dec is set in one 32bit write operation
2082  */
2083 #define QEIV2_POSITION_UPDATE_VALUE_MASK (0x3FFFFFFFUL)
2084 #define QEIV2_POSITION_UPDATE_VALUE_SHIFT (0U)
2085 #define QEIV2_POSITION_UPDATE_VALUE_SET(x) (((uint32_t)(x) << QEIV2_POSITION_UPDATE_VALUE_SHIFT) & QEIV2_POSITION_UPDATE_VALUE_MASK)
2086 #define QEIV2_POSITION_UPDATE_VALUE_GET(x) (((uint32_t)(x) & QEIV2_POSITION_UPDATE_VALUE_MASK) >> QEIV2_POSITION_UPDATE_VALUE_SHIFT)
2087 
2088 /* Bitfield definition for register: ANGLE */
2089 /*
2090  * ANGLE (RO)
2091  *
2092  */
2093 #define QEIV2_ANGLE_ANGLE_MASK (0xFFFFFFFFUL)
2094 #define QEIV2_ANGLE_ANGLE_SHIFT (0U)
2095 #define QEIV2_ANGLE_ANGLE_GET(x) (((uint32_t)(x) & QEIV2_ANGLE_ANGLE_MASK) >> QEIV2_ANGLE_ANGLE_SHIFT)
2096 
2097 /* Bitfield definition for register: POS_TIMEOUT */
2098 /*
2099  * ENABLE (RW)
2100  *
2101  * enable position timeout feature, if timeout, send valid again
2102  */
2103 #define QEIV2_POS_TIMEOUT_ENABLE_MASK (0x80000000UL)
2104 #define QEIV2_POS_TIMEOUT_ENABLE_SHIFT (31U)
2105 #define QEIV2_POS_TIMEOUT_ENABLE_SET(x) (((uint32_t)(x) << QEIV2_POS_TIMEOUT_ENABLE_SHIFT) & QEIV2_POS_TIMEOUT_ENABLE_MASK)
2106 #define QEIV2_POS_TIMEOUT_ENABLE_GET(x) (((uint32_t)(x) & QEIV2_POS_TIMEOUT_ENABLE_MASK) >> QEIV2_POS_TIMEOUT_ENABLE_SHIFT)
2107 
2108 /*
2109  * TIMEOUT (RW)
2110  *
2111  * postion timeout value
2112  */
2113 #define QEIV2_POS_TIMEOUT_TIMEOUT_MASK (0x7FFFFFFFUL)
2114 #define QEIV2_POS_TIMEOUT_TIMEOUT_SHIFT (0U)
2115 #define QEIV2_POS_TIMEOUT_TIMEOUT_SET(x) (((uint32_t)(x) << QEIV2_POS_TIMEOUT_TIMEOUT_SHIFT) & QEIV2_POS_TIMEOUT_TIMEOUT_MASK)
2116 #define QEIV2_POS_TIMEOUT_TIMEOUT_GET(x) (((uint32_t)(x) & QEIV2_POS_TIMEOUT_TIMEOUT_MASK) >> QEIV2_POS_TIMEOUT_TIMEOUT_SHIFT)
2117 
2118 /* Bitfield definition for register: TOGI_CFG0 */
2119 /*
2120  * SIN_TOGI (RW)
2121  *
2122  * set to use TOGI architecture for single SIN input
2123  */
2124 #define QEIV2_TOGI_CFG0_SIN_TOGI_MASK (0x80000000UL)
2125 #define QEIV2_TOGI_CFG0_SIN_TOGI_SHIFT (31U)
2126 #define QEIV2_TOGI_CFG0_SIN_TOGI_SET(x) (((uint32_t)(x) << QEIV2_TOGI_CFG0_SIN_TOGI_SHIFT) & QEIV2_TOGI_CFG0_SIN_TOGI_MASK)
2127 #define QEIV2_TOGI_CFG0_SIN_TOGI_GET(x) (((uint32_t)(x) & QEIV2_TOGI_CFG0_SIN_TOGI_MASK) >> QEIV2_TOGI_CFG0_SIN_TOGI_SHIFT)
2128 
2129 /* Bitfield definition for register: TOGI_CFG1 */
2130 /*
2131  * W_PARAM (RW)
2132  *
2133  * w_param is angle speed, which is 2*PI*signal_hz/adc_sample_rate*2^28.
2134  * for example, 50Hz signal with 1MHz ADC sample rate, angle speed is 2*3.14159*50/1000000*0x10000000,
2135  * which is 84331(0x1496B, default value)
2136  * if 50Hz with 2MHz sample rate, should config to 0xA4B6
2137  */
2138 #define QEIV2_TOGI_CFG1_W_PARAM_MASK (0xFFFFFFFUL)
2139 #define QEIV2_TOGI_CFG1_W_PARAM_SHIFT (0U)
2140 #define QEIV2_TOGI_CFG1_W_PARAM_SET(x) (((uint32_t)(x) << QEIV2_TOGI_CFG1_W_PARAM_SHIFT) & QEIV2_TOGI_CFG1_W_PARAM_MASK)
2141 #define QEIV2_TOGI_CFG1_W_PARAM_GET(x) (((uint32_t)(x) & QEIV2_TOGI_CFG1_W_PARAM_MASK) >> QEIV2_TOGI_CFG1_W_PARAM_SHIFT)
2142 
2143 /* Bitfield definition for register: SINP_ACC */
2144 /*
2145  * SINP_ACC (RO)
2146  *
2147  * positive SIN value acc in one period, updated when calculated SIN from pos to neg.
2148  * each SIN value is 16bit unsinged value(0x8000 for SIN30(0.5) )
2149  */
2150 #define QEIV2_SINP_ACC_SINP_ACC_MASK (0xFFFFFFFFUL)
2151 #define QEIV2_SINP_ACC_SINP_ACC_SHIFT (0U)
2152 #define QEIV2_SINP_ACC_SINP_ACC_GET(x) (((uint32_t)(x) & QEIV2_SINP_ACC_SINP_ACC_MASK) >> QEIV2_SINP_ACC_SINP_ACC_SHIFT)
2153 
2154 /* Bitfield definition for register: SINN_ACC */
2155 /*
2156  * SINN_ACC (RO)
2157  *
2158  * negative SIN value acc in one period, updated when calculated SIN from neg to pos
2159  * each SIN value is 16bit unsinged value(0x8000 for SIN330(-0.5) )
2160  */
2161 #define QEIV2_SINN_ACC_SINN_ACC_MASK (0xFFFFFFFFUL)
2162 #define QEIV2_SINN_ACC_SINN_ACC_SHIFT (0U)
2163 #define QEIV2_SINN_ACC_SINN_ACC_GET(x) (((uint32_t)(x) & QEIV2_SINN_ACC_SINN_ACC_MASK) >> QEIV2_SINN_ACC_SINN_ACC_SHIFT)
2164 
2165 /* Bitfield definition for register: COSP_ACC */
2166 /*
2167  * COSP_ACC (RO)
2168  *
2169  * positive COS value acc in one period, updated when calculated COS from pos to neg
2170  */
2171 #define QEIV2_COSP_ACC_COSP_ACC_MASK (0xFFFFFFFFUL)
2172 #define QEIV2_COSP_ACC_COSP_ACC_SHIFT (0U)
2173 #define QEIV2_COSP_ACC_COSP_ACC_GET(x) (((uint32_t)(x) & QEIV2_COSP_ACC_COSP_ACC_MASK) >> QEIV2_COSP_ACC_COSP_ACC_SHIFT)
2174 
2175 /* Bitfield definition for register: COSN_ACC */
2176 /*
2177  * COSN_ACC (RO)
2178  *
2179  * negative COS value acc in one period, updated when calculated COS from neg to pos
2180  */
2181 #define QEIV2_COSN_ACC_COSN_ACC_MASK (0xFFFFFFFFUL)
2182 #define QEIV2_COSN_ACC_COSN_ACC_SHIFT (0U)
2183 #define QEIV2_COSN_ACC_COSN_ACC_GET(x) (((uint32_t)(x) & QEIV2_COSN_ACC_COSN_ACC_MASK) >> QEIV2_COSN_ACC_COSN_ACC_SHIFT)
2184 
2185 
2186 
2187 /* COUNT register group index macro definition */
2188 #define QEIV2_COUNT_CURRENT (0UL)
2189 #define QEIV2_COUNT_READ (1UL)
2190 #define QEIV2_COUNT_SNAP0 (2UL)
2191 #define QEIV2_COUNT_SNAP1 (3UL)
2192 
2193 /* FILT_CFG register group index macro definition */
2194 #define QEIV2_FILT_CFG_FILT_CFG_A (0UL)
2195 #define QEIV2_FILT_CFG_FILT_CFG_B (1UL)
2196 #define QEIV2_FILT_CFG_FILT_CFG_Z (2UL)
2197 #define QEIV2_FILT_CFG_FILT_CFG_H (3UL)
2198 #define QEIV2_FILT_CFG_FILT_CFG_H2 (4UL)
2199 #define QEIV2_FILT_CFG_FILT_CFG_F (5UL)
2200 
2201 /* UVW_POS register group index macro definition */
2202 #define QEIV2_UVW_POS_UVW_POS0 (0UL)
2203 #define QEIV2_UVW_POS_UVW_POS1 (1UL)
2204 #define QEIV2_UVW_POS_UVW_POS2 (2UL)
2205 #define QEIV2_UVW_POS_UVW_POS3 (3UL)
2206 #define QEIV2_UVW_POS_UVW_POS4 (4UL)
2207 #define QEIV2_UVW_POS_UVW_POS5 (5UL)
2208 
2209 /* UVW_POS_CFG register group index macro definition */
2210 #define QEIV2_UVW_POS_CFG_UVW_POS0_CFG (0UL)
2211 #define QEIV2_UVW_POS_CFG_UVW_POS1_CFG (1UL)
2212 #define QEIV2_UVW_POS_CFG_UVW_POS2_CFG (2UL)
2213 #define QEIV2_UVW_POS_CFG_UVW_POS3_CFG (3UL)
2214 #define QEIV2_UVW_POS_CFG_UVW_POS4_CFG (4UL)
2215 #define QEIV2_UVW_POS_CFG_UVW_POS5_CFG (5UL)
2216 
2217 
2218 #endif /* HPM_QEIV2_H */
QEIV2_Type
Definition: hpm_qeiv2_regs.h:12