HPM SDK
HPMicro Software Development Kit
hpm_sysctl_regs.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_SYSCTL_H
10 #define HPM_SYSCTL_H
11 
12 typedef struct {
13  __RW uint32_t RESOURCE[344]; /* 0x0 - 0x55C: Resource control register for cpu0_core */
14  __R uint8_t RESERVED0[672]; /* 0x560 - 0x7FF: Reserved */
15  struct {
16  __RW uint32_t VALUE; /* 0x800: Group setting */
17  __RW uint32_t SET; /* 0x804: Group setting */
18  __RW uint32_t CLEAR; /* 0x808: Group setting */
19  __RW uint32_t TOGGLE; /* 0x80C: Group setting */
20  } GROUP0[3];
21  __R uint8_t RESERVED1[16]; /* 0x830 - 0x83F: Reserved */
22  struct {
23  __RW uint32_t VALUE; /* 0x840: Group setting */
24  __RW uint32_t SET; /* 0x844: Group setting */
25  __RW uint32_t CLEAR; /* 0x848: Group setting */
26  __RW uint32_t TOGGLE; /* 0x84C: Group setting */
27  } GROUP1[3];
28  __R uint8_t RESERVED2[144]; /* 0x870 - 0x8FF: Reserved */
29  struct {
30  __RW uint32_t VALUE; /* 0x900: Affiliate of Group */
31  __RW uint32_t SET; /* 0x904: Affiliate of Group */
32  __RW uint32_t CLEAR; /* 0x908: Affiliate of Group */
33  __RW uint32_t TOGGLE; /* 0x90C: Affiliate of Group */
34  } AFFILIATE[2];
35  struct {
36  __RW uint32_t VALUE; /* 0x920: Retention Contol */
37  __RW uint32_t SET; /* 0x924: Retention Contol */
38  __RW uint32_t CLEAR; /* 0x928: Retention Contol */
39  __RW uint32_t TOGGLE; /* 0x92C: Retention Contol */
40  } RETENTION[2];
41  __R uint8_t RESERVED3[1728]; /* 0x940 - 0xFFF: Reserved */
42  struct {
43  __RW uint32_t STATUS; /* 0x1000: Power Setting */
44  __RW uint32_t LF_WAIT; /* 0x1004: Power Setting */
45  __R uint8_t RESERVED0[4]; /* 0x1008 - 0x100B: Reserved */
46  __RW uint32_t OFF_WAIT; /* 0x100C: Power Setting */
47  } POWER[2];
48  __R uint8_t RESERVED4[992]; /* 0x1020 - 0x13FF: Reserved */
49  struct {
50  __RW uint32_t CONTROL; /* 0x1400: Reset Setting */
51  __RW uint32_t CONFIG; /* 0x1404: Reset Setting */
52  __R uint8_t RESERVED0[4]; /* 0x1408 - 0x140B: Reserved */
53  __RW uint32_t COUNTER; /* 0x140C: Reset Setting */
54  } RESET[3];
55  __R uint8_t RESERVED5[976]; /* 0x1430 - 0x17FF: Reserved */
56  __RW uint32_t CLOCK[45]; /* 0x1800 - 0x18B0: Clock setting */
57  __R uint8_t RESERVED6[844]; /* 0x18B4 - 0x1BFF: Reserved */
58  __RW uint32_t ADCCLK[4]; /* 0x1C00 - 0x1C0C: Clock setting */
59  __RW uint32_t I2SCLK[2]; /* 0x1C10 - 0x1C14: Clock setting */
60  __R uint8_t RESERVED7[1000]; /* 0x1C18 - 0x1FFF: Reserved */
61  __RW uint32_t GLOBAL00; /* 0x2000: Clock senario */
62  __R uint8_t RESERVED8[1020]; /* 0x2004 - 0x23FF: Reserved */
63  struct {
64  __RW uint32_t CONTROL; /* 0x2400: Clock measure and monitor control */
65  __R uint32_t CURRENT; /* 0x2404: Clock measure result */
66  __RW uint32_t LOW_LIMIT; /* 0x2408: Clock lower limit */
67  __RW uint32_t HIGH_LIMIT; /* 0x240C: Clock upper limit */
68  __R uint8_t RESERVED0[16]; /* 0x2410 - 0x241F: Reserved */
69  } MONITOR[4];
70  __R uint8_t RESERVED9[896]; /* 0x2480 - 0x27FF: Reserved */
71  struct {
72  __RW uint32_t LP; /* 0x2800: CPU0 LP control */
73  __RW uint32_t LOCK; /* 0x2804: CPU0 Lock GPR */
74  __RW uint32_t GPR[14]; /* 0x2808 - 0x283C: CPU0 GPR0 */
75  __R uint32_t WAKEUP_STATUS[4]; /* 0x2840 - 0x284C: CPU0 wakeup IRQ status */
76  __R uint8_t RESERVED0[48]; /* 0x2850 - 0x287F: Reserved */
77  __RW uint32_t WAKEUP_ENABLE[4]; /* 0x2880 - 0x288C: CPU0 wakeup IRQ enable */
78  __R uint8_t RESERVED1[880]; /* 0x2890 - 0x2BFF: Reserved */
79  } CPU[2];
80 } SYSCTL_Type;
81 
82 
83 /* Bitfield definition for register array: RESOURCE */
84 /*
85  * GLB_BUSY (RO)
86  *
87  * global busy
88  * 0: no changes pending to any nodes
89  * 1: any of nodes is changing status
90  */
91 #define SYSCTL_RESOURCE_GLB_BUSY_MASK (0x80000000UL)
92 #define SYSCTL_RESOURCE_GLB_BUSY_SHIFT (31U)
93 #define SYSCTL_RESOURCE_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_GLB_BUSY_MASK) >> SYSCTL_RESOURCE_GLB_BUSY_SHIFT)
94 
95 /*
96  * LOC_BUSY (RO)
97  *
98  * local busy
99  * 0: no change is pending for current node
100  * 1: current node is changing status
101  */
102 #define SYSCTL_RESOURCE_LOC_BUSY_MASK (0x40000000UL)
103 #define SYSCTL_RESOURCE_LOC_BUSY_SHIFT (30U)
104 #define SYSCTL_RESOURCE_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_LOC_BUSY_MASK) >> SYSCTL_RESOURCE_LOC_BUSY_SHIFT)
105 
106 /*
107  * MODE (RW)
108  *
109  * resource work mode
110  * 0:auto turn on and off as system required(recommended)
111  * 1:always on
112  * 2:always off
113  * 3:reserved
114  */
115 #define SYSCTL_RESOURCE_MODE_MASK (0x3U)
116 #define SYSCTL_RESOURCE_MODE_SHIFT (0U)
117 #define SYSCTL_RESOURCE_MODE_SET(x) (((uint32_t)(x) << SYSCTL_RESOURCE_MODE_SHIFT) & SYSCTL_RESOURCE_MODE_MASK)
118 #define SYSCTL_RESOURCE_MODE_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_MODE_MASK) >> SYSCTL_RESOURCE_MODE_SHIFT)
119 
120 /* Bitfield definition for register of struct array GROUP0: VALUE */
121 /*
122  * LINK (RW)
123  *
124  * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral
125  * 0: peripheral is not needed
126  * 1: periphera is needed
127  */
128 #define SYSCTL_GROUP0_VALUE_LINK_MASK (0xFFFFFFFFUL)
129 #define SYSCTL_GROUP0_VALUE_LINK_SHIFT (0U)
130 #define SYSCTL_GROUP0_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_VALUE_LINK_SHIFT) & SYSCTL_GROUP0_VALUE_LINK_MASK)
131 #define SYSCTL_GROUP0_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_VALUE_LINK_MASK) >> SYSCTL_GROUP0_VALUE_LINK_SHIFT)
132 
133 /* Bitfield definition for register of struct array GROUP0: SET */
134 /*
135  * LINK (RW)
136  *
137  * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral
138  * 0: no effect
139  * 1: add periphera into this group，periphera is needed
140  */
141 #define SYSCTL_GROUP0_SET_LINK_MASK (0xFFFFFFFFUL)
142 #define SYSCTL_GROUP0_SET_LINK_SHIFT (0U)
143 #define SYSCTL_GROUP0_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_SET_LINK_SHIFT) & SYSCTL_GROUP0_SET_LINK_MASK)
144 #define SYSCTL_GROUP0_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_SET_LINK_MASK) >> SYSCTL_GROUP0_SET_LINK_SHIFT)
145 
146 /* Bitfield definition for register of struct array GROUP0: CLEAR */
147 /*
148  * LINK (RW)
149  *
150  * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral
151  * 0: no effect
152  * 1: delete periphera in this group，periphera is not needed
153  */
154 #define SYSCTL_GROUP0_CLEAR_LINK_MASK (0xFFFFFFFFUL)
155 #define SYSCTL_GROUP0_CLEAR_LINK_SHIFT (0U)
156 #define SYSCTL_GROUP0_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_CLEAR_LINK_SHIFT) & SYSCTL_GROUP0_CLEAR_LINK_MASK)
157 #define SYSCTL_GROUP0_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_CLEAR_LINK_MASK) >> SYSCTL_GROUP0_CLEAR_LINK_SHIFT)
158 
159 /* Bitfield definition for register of struct array GROUP0: TOGGLE */
160 /*
161  * LINK (RW)
162  *
163  * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral
164  * 0: no effect
165  * 1: toggle the result that whether periphera is needed before
166  */
167 #define SYSCTL_GROUP0_TOGGLE_LINK_MASK (0xFFFFFFFFUL)
168 #define SYSCTL_GROUP0_TOGGLE_LINK_SHIFT (0U)
169 #define SYSCTL_GROUP0_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_TOGGLE_LINK_SHIFT) & SYSCTL_GROUP0_TOGGLE_LINK_MASK)
170 #define SYSCTL_GROUP0_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_TOGGLE_LINK_MASK) >> SYSCTL_GROUP0_TOGGLE_LINK_SHIFT)
171 
172 /* Bitfield definition for register of struct array GROUP1: VALUE */
173 /*
174  * LINK (RW)
175  *
176  * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral
177  * 0: peripheral is not needed
178  * 1: periphera is needed
179  */
180 #define SYSCTL_GROUP1_VALUE_LINK_MASK (0xFFFFFFFFUL)
181 #define SYSCTL_GROUP1_VALUE_LINK_SHIFT (0U)
182 #define SYSCTL_GROUP1_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_VALUE_LINK_SHIFT) & SYSCTL_GROUP1_VALUE_LINK_MASK)
183 #define SYSCTL_GROUP1_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_VALUE_LINK_MASK) >> SYSCTL_GROUP1_VALUE_LINK_SHIFT)
184 
185 /* Bitfield definition for register of struct array GROUP1: SET */
186 /*
187  * LINK (RW)
188  *
189  * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral
190  * 0: no effect
191  * 1: add periphera into this group，periphera is needed
192  */
193 #define SYSCTL_GROUP1_SET_LINK_MASK (0xFFFFFFFFUL)
194 #define SYSCTL_GROUP1_SET_LINK_SHIFT (0U)
195 #define SYSCTL_GROUP1_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_SET_LINK_SHIFT) & SYSCTL_GROUP1_SET_LINK_MASK)
196 #define SYSCTL_GROUP1_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_SET_LINK_MASK) >> SYSCTL_GROUP1_SET_LINK_SHIFT)
197 
198 /* Bitfield definition for register of struct array GROUP1: CLEAR */
199 /*
200  * LINK (RW)
201  *
202  * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral
203  * 0: no effect
204  * 1: delete periphera in this group，periphera is not needed
205  */
206 #define SYSCTL_GROUP1_CLEAR_LINK_MASK (0xFFFFFFFFUL)
207 #define SYSCTL_GROUP1_CLEAR_LINK_SHIFT (0U)
208 #define SYSCTL_GROUP1_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_CLEAR_LINK_SHIFT) & SYSCTL_GROUP1_CLEAR_LINK_MASK)
209 #define SYSCTL_GROUP1_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_CLEAR_LINK_MASK) >> SYSCTL_GROUP1_CLEAR_LINK_SHIFT)
210 
211 /* Bitfield definition for register of struct array GROUP1: TOGGLE */
212 /*
213  * LINK (RW)
214  *
215  * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral
216  * 0: no effect
217  * 1: toggle the result that whether periphera is needed before
218  */
219 #define SYSCTL_GROUP1_TOGGLE_LINK_MASK (0xFFFFFFFFUL)
220 #define SYSCTL_GROUP1_TOGGLE_LINK_SHIFT (0U)
221 #define SYSCTL_GROUP1_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_TOGGLE_LINK_SHIFT) & SYSCTL_GROUP1_TOGGLE_LINK_MASK)
222 #define SYSCTL_GROUP1_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_TOGGLE_LINK_MASK) >> SYSCTL_GROUP1_TOGGLE_LINK_SHIFT)
223 
224 /* Bitfield definition for register of struct array AFFILIATE: VALUE */
225 /*
226  * LINK (RW)
227  *
228  * Affiliate groups of cpu0, each bit represents a group
229  * bit0: cpu0 depends on group0
230  * bit1: cpu0 depends on group1
231  * bit2: cpu0 depends on group2
232  * bit3: cpu0 depends on group3
233  */
234 #define SYSCTL_AFFILIATE_VALUE_LINK_MASK (0xFU)
235 #define SYSCTL_AFFILIATE_VALUE_LINK_SHIFT (0U)
236 #define SYSCTL_AFFILIATE_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_VALUE_LINK_SHIFT) & SYSCTL_AFFILIATE_VALUE_LINK_MASK)
237 #define SYSCTL_AFFILIATE_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_VALUE_LINK_MASK) >> SYSCTL_AFFILIATE_VALUE_LINK_SHIFT)
238 
239 /* Bitfield definition for register of struct array AFFILIATE: SET */
240 /*
241  * LINK (RW)
242  *
243  * Affiliate groups of cpu0，each bit represents a group
244  * 0: no effect
245  * 1: the group is assigned to CPU0
246  */
247 #define SYSCTL_AFFILIATE_SET_LINK_MASK (0xFU)
248 #define SYSCTL_AFFILIATE_SET_LINK_SHIFT (0U)
249 #define SYSCTL_AFFILIATE_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_SET_LINK_SHIFT) & SYSCTL_AFFILIATE_SET_LINK_MASK)
250 #define SYSCTL_AFFILIATE_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_SET_LINK_MASK) >> SYSCTL_AFFILIATE_SET_LINK_SHIFT)
251 
252 /* Bitfield definition for register of struct array AFFILIATE: CLEAR */
253 /*
254  * LINK (RW)
255  *
256  * Affiliate groups of cpu0, each bit represents a group
257  * 0: no effect
258  * 1: the group is not assigned to CPU0
259  */
260 #define SYSCTL_AFFILIATE_CLEAR_LINK_MASK (0xFU)
261 #define SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT (0U)
262 #define SYSCTL_AFFILIATE_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK)
263 #define SYSCTL_AFFILIATE_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK) >> SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT)
264 
265 /* Bitfield definition for register of struct array AFFILIATE: TOGGLE */
266 /*
267  * LINK (RW)
268  *
269  * Affiliate groups of cpu0, each bit represents a group
270  * 0: no effect
271  * 1: toggle the result that whether the group is assigned to CPU0 before
272  */
273 #define SYSCTL_AFFILIATE_TOGGLE_LINK_MASK (0xFU)
274 #define SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT (0U)
275 #define SYSCTL_AFFILIATE_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK)
276 #define SYSCTL_AFFILIATE_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK) >> SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT)
277 
278 /* Bitfield definition for register of struct array RETENTION: VALUE */
279 /*
280  * LINK (RW)
281  *
282  * retention setting while CPU0 enter stop mode, each bit represents a resource
283  * bit00: soc_mem is kept on while cpu0 stop
284  * bit01: soc_ctx is kept on while cpu0 stop
285  * bit02: cpu0_mem is kept on while cpu0 stop
286  * bit03: cpu0_ctx is kept on while cpu0 stop
287  * bit04: cpu1_mem is kept on while cpu0 stop
288  * bit05: cpu1_ctx is kept on while cpu0 stop
289  * bit06: xtal_hold is kept on while cpu0 stop
290  * bit07: pll0_hold is kept on while cpu0 stop
291  * bit08: pll1_hold is kept on while cpu0 stop
292  * bit09: pll2_hold is kept on while cpu0 stop
293  */
294 #define SYSCTL_RETENTION_VALUE_LINK_MASK (0x3FFU)
295 #define SYSCTL_RETENTION_VALUE_LINK_SHIFT (0U)
296 #define SYSCTL_RETENTION_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_VALUE_LINK_SHIFT) & SYSCTL_RETENTION_VALUE_LINK_MASK)
297 #define SYSCTL_RETENTION_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_VALUE_LINK_MASK) >> SYSCTL_RETENTION_VALUE_LINK_SHIFT)
298 
299 /* Bitfield definition for register of struct array RETENTION: SET */
300 /*
301  * LINK (RW)
302  *
303  * retention setting while CPU0 enter stop mode, each bit represents a resource
304  * 0: no effect
305  * 1: keep
306  */
307 #define SYSCTL_RETENTION_SET_LINK_MASK (0x3FFU)
308 #define SYSCTL_RETENTION_SET_LINK_SHIFT (0U)
309 #define SYSCTL_RETENTION_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_SET_LINK_SHIFT) & SYSCTL_RETENTION_SET_LINK_MASK)
310 #define SYSCTL_RETENTION_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_SET_LINK_MASK) >> SYSCTL_RETENTION_SET_LINK_SHIFT)
311 
312 /* Bitfield definition for register of struct array RETENTION: CLEAR */
313 /*
314  * LINK (RW)
315  *
316  * retention setting while CPU0 enter stop mode, each bit represents a resource
317  * 0: no effect
318  * 1: no keep
319  */
320 #define SYSCTL_RETENTION_CLEAR_LINK_MASK (0x3FFU)
321 #define SYSCTL_RETENTION_CLEAR_LINK_SHIFT (0U)
322 #define SYSCTL_RETENTION_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_CLEAR_LINK_SHIFT) & SYSCTL_RETENTION_CLEAR_LINK_MASK)
323 #define SYSCTL_RETENTION_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_CLEAR_LINK_MASK) >> SYSCTL_RETENTION_CLEAR_LINK_SHIFT)
324 
325 /* Bitfield definition for register of struct array RETENTION: TOGGLE */
326 /*
327  * LINK (RW)
328  *
329  * retention setting while CPU0 enter stop mode, each bit represents a resource
330  * 0: no effect
331  * 1: toggle the result that whether the resource is kept on while CPU0 stop before
332  */
333 #define SYSCTL_RETENTION_TOGGLE_LINK_MASK (0x3FFU)
334 #define SYSCTL_RETENTION_TOGGLE_LINK_SHIFT (0U)
335 #define SYSCTL_RETENTION_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_TOGGLE_LINK_SHIFT) & SYSCTL_RETENTION_TOGGLE_LINK_MASK)
336 #define SYSCTL_RETENTION_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_TOGGLE_LINK_MASK) >> SYSCTL_RETENTION_TOGGLE_LINK_SHIFT)
337 
338 /* Bitfield definition for register of struct array POWER: STATUS */
339 /*
340  * FLAG (RW)
341  *
342  * flag represents power cycle happened from last clear of this bit
343  * 0: power domain did not edurance power cycle since last clear of this bit
344  * 1: power domain enduranced power cycle since last clear of this bit
345  */
346 #define SYSCTL_POWER_STATUS_FLAG_MASK (0x80000000UL)
347 #define SYSCTL_POWER_STATUS_FLAG_SHIFT (31U)
348 #define SYSCTL_POWER_STATUS_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_SHIFT) & SYSCTL_POWER_STATUS_FLAG_MASK)
349 #define SYSCTL_POWER_STATUS_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_MASK) >> SYSCTL_POWER_STATUS_FLAG_SHIFT)
350 
351 /*
352  * FLAG_WAKE (RW)
353  *
354  * flag represents wakeup power cycle happened from last clear of this bit
355  * 0: power domain did not edurance wakeup power cycle since last clear of this bit
356  * 1: power domain enduranced wakeup power cycle since last clear of this bit
357  */
358 #define SYSCTL_POWER_STATUS_FLAG_WAKE_MASK (0x40000000UL)
359 #define SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT (30U)
360 #define SYSCTL_POWER_STATUS_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK)
361 #define SYSCTL_POWER_STATUS_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK) >> SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT)
362 
363 /*
364  * MEM_RET_N (RO)
365  *
366  * memory info retention control signal
367  * 0: memory enter retention mode
368  * 1: memory exit retention mode
369  */
370 #define SYSCTL_POWER_STATUS_MEM_RET_N_MASK (0x20000UL)
371 #define SYSCTL_POWER_STATUS_MEM_RET_N_SHIFT (17U)
372 #define SYSCTL_POWER_STATUS_MEM_RET_N_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_MEM_RET_N_MASK) >> SYSCTL_POWER_STATUS_MEM_RET_N_SHIFT)
373 
374 /*
375  * MEM_RET_P (RO)
376  *
377  * memory info retention control signal
378  * 0: memory not enterexitretention mode
379  * 1: memory enter retention mode
380  */
381 #define SYSCTL_POWER_STATUS_MEM_RET_P_MASK (0x10000UL)
382 #define SYSCTL_POWER_STATUS_MEM_RET_P_SHIFT (16U)
383 #define SYSCTL_POWER_STATUS_MEM_RET_P_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_MEM_RET_P_MASK) >> SYSCTL_POWER_STATUS_MEM_RET_P_SHIFT)
384 
385 /*
386  * LF_DISABLE (RO)
387  *
388  * low fanout power switch disable
389  * 0: low fanout power switches are turned on
390  * 1: low fanout power switches are truned off
391  */
392 #define SYSCTL_POWER_STATUS_LF_DISABLE_MASK (0x1000U)
393 #define SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT (12U)
394 #define SYSCTL_POWER_STATUS_LF_DISABLE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_DISABLE_MASK) >> SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT)
395 
396 /*
397  * LF_ACK (RO)
398  *
399  * low fanout power switch feedback
400  * 0: low fanout power switches are turned on
401  * 1: low fanout power switches are truned off
402  */
403 #define SYSCTL_POWER_STATUS_LF_ACK_MASK (0x100U)
404 #define SYSCTL_POWER_STATUS_LF_ACK_SHIFT (8U)
405 #define SYSCTL_POWER_STATUS_LF_ACK_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_ACK_MASK) >> SYSCTL_POWER_STATUS_LF_ACK_SHIFT)
406 
407 /* Bitfield definition for register of struct array POWER: LF_WAIT */
408 /*
409  * WAIT (RW)
410  *
411  * wait time for low fan out power switch turn on, default value is 255
412  * 0: 0 clock cycle
413  * 1: 1 clock cycles
414  * . . .
415  * clock cycles count on 24MHz
416  */
417 #define SYSCTL_POWER_LF_WAIT_WAIT_MASK (0xFFFFFUL)
418 #define SYSCTL_POWER_LF_WAIT_WAIT_SHIFT (0U)
419 #define SYSCTL_POWER_LF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_LF_WAIT_WAIT_MASK)
420 #define SYSCTL_POWER_LF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_LF_WAIT_WAIT_MASK) >> SYSCTL_POWER_LF_WAIT_WAIT_SHIFT)
421 
422 /* Bitfield definition for register of struct array POWER: OFF_WAIT */
423 /*
424  * WAIT (RW)
425  *
426  * wait time for power switch turn off, default value is 15
427  * 0: 0 clock cycle
428  * 1: 1 clock cycles
429  * . . .
430  * clock cycles count on 24MHz
431  */
432 #define SYSCTL_POWER_OFF_WAIT_WAIT_MASK (0xFFFFFUL)
433 #define SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT (0U)
434 #define SYSCTL_POWER_OFF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK)
435 #define SYSCTL_POWER_OFF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK) >> SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT)
436 
437 /* Bitfield definition for register of struct array RESET: CONTROL */
438 /*
439  * FLAG (RW)
440  *
441  * flag represents reset happened from last clear of this bit
442  * 0: domain did not edurance reset cycle since last clear of this bit
443  * 1: domain enduranced reset cycle since last clear of this bit
444  */
445 #define SYSCTL_RESET_CONTROL_FLAG_MASK (0x80000000UL)
446 #define SYSCTL_RESET_CONTROL_FLAG_SHIFT (31U)
447 #define SYSCTL_RESET_CONTROL_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_MASK)
448 #define SYSCTL_RESET_CONTROL_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_MASK) >> SYSCTL_RESET_CONTROL_FLAG_SHIFT)
449 
450 /*
451  * FLAG_WAKE (RW)
452  *
453  * flag represents wakeup reset happened from last clear of this bit
454  * 0: domain did not edurance wakeup reset cycle since last clear of this bit
455  * 1: domain enduranced wakeup reset cycle since last clear of this bit
456  */
457 #define SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK (0x40000000UL)
458 #define SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT (30U)
459 #define SYSCTL_RESET_CONTROL_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK)
460 #define SYSCTL_RESET_CONTROL_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK) >> SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT)
461 
462 /*
463  * HOLD (RW)
464  *
465  * perform reset and hold in reset, until ths bit cleared by software
466  * 0: reset is released for function
467  * 1: reset is assert and hold
468  */
469 #define SYSCTL_RESET_CONTROL_HOLD_MASK (0x10U)
470 #define SYSCTL_RESET_CONTROL_HOLD_SHIFT (4U)
471 #define SYSCTL_RESET_CONTROL_HOLD_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_HOLD_SHIFT) & SYSCTL_RESET_CONTROL_HOLD_MASK)
472 #define SYSCTL_RESET_CONTROL_HOLD_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_HOLD_MASK) >> SYSCTL_RESET_CONTROL_HOLD_SHIFT)
473 
474 /*
475  * RESET (RW)
476  *
477  * perform reset and release imediately
478  * 0: reset is released
479  * 1 reset is asserted and will release automaticly
480  */
481 #define SYSCTL_RESET_CONTROL_RESET_MASK (0x1U)
482 #define SYSCTL_RESET_CONTROL_RESET_SHIFT (0U)
483 #define SYSCTL_RESET_CONTROL_RESET_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_RESET_SHIFT) & SYSCTL_RESET_CONTROL_RESET_MASK)
484 #define SYSCTL_RESET_CONTROL_RESET_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_RESET_MASK) >> SYSCTL_RESET_CONTROL_RESET_SHIFT)
485 
486 /* Bitfield definition for register of struct array RESET: CONFIG */
487 /*
488  * PRE_WAIT (RW)
489  *
490  * wait cycle numbers before assert reset
491  * 0: wait 0 cycle
492  * 1: wait 1 cycles
493  * . . .
494  * Note, clock cycle is base on 24M
495  */
496 #define SYSCTL_RESET_CONFIG_PRE_WAIT_MASK (0xFF0000UL)
497 #define SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT (16U)
498 #define SYSCTL_RESET_CONFIG_PRE_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK)
499 #define SYSCTL_RESET_CONFIG_PRE_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK) >> SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT)
500 
501 /*
502  * RSTCLK_NUM (RW)
503  *
504  * reset clock number(must be even number)
505  * 0: 0 cycle
506  * 1: 0 cycles
507  * 2: 2 cycles
508  * 3: 2 cycles
509  * . . .
510  * Note, clock cycle is base on 24M
511  */
512 #define SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK (0xFF00U)
513 #define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT (8U)
514 #define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK)
515 #define SYSCTL_RESET_CONFIG_RSTCLK_NUM_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK) >> SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT)
516 
517 /*
518  * POST_WAIT (RW)
519  *
520  * time guard band for reset release
521  * 0: wait 0 cycle
522  * 1: wait 1 cycles
523  * . . .
524  * Note, clock cycle is base on 24M
525  */
526 #define SYSCTL_RESET_CONFIG_POST_WAIT_MASK (0xFFU)
527 #define SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT (0U)
528 #define SYSCTL_RESET_CONFIG_POST_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK)
529 #define SYSCTL_RESET_CONFIG_POST_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK) >> SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT)
530 
531 /* Bitfield definition for register of struct array RESET: COUNTER */
532 /*
533  * COUNTER (RW)
534  *
535  * self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset
536  * 0: wait 0 cycle
537  * 1: wait 1 cycles
538  * . . .
539  * Note, clock cycle is base on 24M
540  */
541 #define SYSCTL_RESET_COUNTER_COUNTER_MASK (0xFFFFFUL)
542 #define SYSCTL_RESET_COUNTER_COUNTER_SHIFT (0U)
543 #define SYSCTL_RESET_COUNTER_COUNTER_SET(x) (((uint32_t)(x) << SYSCTL_RESET_COUNTER_COUNTER_SHIFT) & SYSCTL_RESET_COUNTER_COUNTER_MASK)
544 #define SYSCTL_RESET_COUNTER_COUNTER_GET(x) (((uint32_t)(x) & SYSCTL_RESET_COUNTER_COUNTER_MASK) >> SYSCTL_RESET_COUNTER_COUNTER_SHIFT)
545 
546 /* Bitfield definition for register array: CLOCK */
547 /*
548  * GLB_BUSY (RO)
549  *
550  * global busy
551  * 0: no changes pending to any clock
552  * 1: any of nodes is changing status
553  */
554 #define SYSCTL_CLOCK_GLB_BUSY_MASK (0x80000000UL)
555 #define SYSCTL_CLOCK_GLB_BUSY_SHIFT (31U)
556 #define SYSCTL_CLOCK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_GLB_BUSY_MASK) >> SYSCTL_CLOCK_GLB_BUSY_SHIFT)
557 
558 /*
559  * LOC_BUSY (RO)
560  *
561  * local busy
562  * 0: a change is pending for current node
563  * 1: current node is changing status
564  */
565 #define SYSCTL_CLOCK_LOC_BUSY_MASK (0x40000000UL)
566 #define SYSCTL_CLOCK_LOC_BUSY_SHIFT (30U)
567 #define SYSCTL_CLOCK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_LOC_BUSY_MASK) >> SYSCTL_CLOCK_LOC_BUSY_SHIFT)
568 
569 /*
570  * PRESERVE (RW)
571  *
572  * preserve function against global select
573  * 0: select global clock setting
574  * 1: not select global clock setting
575  */
576 #define SYSCTL_CLOCK_PRESERVE_MASK (0x10000000UL)
577 #define SYSCTL_CLOCK_PRESERVE_SHIFT (28U)
578 #define SYSCTL_CLOCK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_PRESERVE_SHIFT) & SYSCTL_CLOCK_PRESERVE_MASK)
579 #define SYSCTL_CLOCK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_PRESERVE_MASK) >> SYSCTL_CLOCK_PRESERVE_SHIFT)
580 
581 /*
582  * MUX (RW)
583  *
584  * current mux in clock component
585  * 0:osc0_clk0
586  * 1:pll0_clk0
587  * 2:pll0_clk1
588  * 3:pll1_clk0
589  * 4:pll1_clk1
590  * 5:pll1_clk2
591  * 6:pll2_clk0
592  * 7:pll2_clk1
593  */
594 #define SYSCTL_CLOCK_MUX_MASK (0x700U)
595 #define SYSCTL_CLOCK_MUX_SHIFT (8U)
596 #define SYSCTL_CLOCK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_MUX_SHIFT) & SYSCTL_CLOCK_MUX_MASK)
597 #define SYSCTL_CLOCK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_MUX_MASK) >> SYSCTL_CLOCK_MUX_SHIFT)
598 
599 /*
600  * DIV (RW)
601  *
602  * clock divider
603  * 0: divider by 1
604  * 1: divider by 2
605  * 2: divider by 3
606  * . . .
607  * 255: divider by 256
608  */
609 #define SYSCTL_CLOCK_DIV_MASK (0xFFU)
610 #define SYSCTL_CLOCK_DIV_SHIFT (0U)
611 #define SYSCTL_CLOCK_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_DIV_SHIFT) & SYSCTL_CLOCK_DIV_MASK)
612 #define SYSCTL_CLOCK_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_DIV_MASK) >> SYSCTL_CLOCK_DIV_SHIFT)
613 
614 /* Bitfield definition for register array: ADCCLK */
615 /*
616  * GLB_BUSY (RO)
617  *
618  * global busy
619  * 0: no changes pending to any clock
620  * 1: any of nodes is changing status
621  */
622 #define SYSCTL_ADCCLK_GLB_BUSY_MASK (0x80000000UL)
623 #define SYSCTL_ADCCLK_GLB_BUSY_SHIFT (31U)
624 #define SYSCTL_ADCCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_GLB_BUSY_MASK) >> SYSCTL_ADCCLK_GLB_BUSY_SHIFT)
625 
626 /*
627  * LOC_BUSY (RO)
628  *
629  * local busy
630  * 0: a change is pending for current node
631  * 1: current node is changing status
632  */
633 #define SYSCTL_ADCCLK_LOC_BUSY_MASK (0x40000000UL)
634 #define SYSCTL_ADCCLK_LOC_BUSY_SHIFT (30U)
635 #define SYSCTL_ADCCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_LOC_BUSY_MASK) >> SYSCTL_ADCCLK_LOC_BUSY_SHIFT)
636 
637 /*
638  * PRESERVE (RW)
639  *
640  * preserve function against global select
641  * 0: select global clock setting
642  * 1: not select global clock setting
643  */
644 #define SYSCTL_ADCCLK_PRESERVE_MASK (0x10000000UL)
645 #define SYSCTL_ADCCLK_PRESERVE_SHIFT (28U)
646 #define SYSCTL_ADCCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_PRESERVE_SHIFT) & SYSCTL_ADCCLK_PRESERVE_MASK)
647 #define SYSCTL_ADCCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_PRESERVE_MASK) >> SYSCTL_ADCCLK_PRESERVE_SHIFT)
648 
649 /*
650  * MUX (RW)
651  *
652  * current mux
653  * 0: ahb0 clock
654  * 1: ana clock N
655  */
656 #define SYSCTL_ADCCLK_MUX_MASK (0x100U)
657 #define SYSCTL_ADCCLK_MUX_SHIFT (8U)
658 #define SYSCTL_ADCCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_MUX_SHIFT) & SYSCTL_ADCCLK_MUX_MASK)
659 #define SYSCTL_ADCCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_MUX_MASK) >> SYSCTL_ADCCLK_MUX_SHIFT)
660 
661 /* Bitfield definition for register array: I2SCLK */
662 /*
663  * GLB_BUSY (RO)
664  *
665  * global busy
666  * 0: no changes pending to any clock
667  * 1: any of nodes is changing status
668  */
669 #define SYSCTL_I2SCLK_GLB_BUSY_MASK (0x80000000UL)
670 #define SYSCTL_I2SCLK_GLB_BUSY_SHIFT (31U)
671 #define SYSCTL_I2SCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_GLB_BUSY_MASK) >> SYSCTL_I2SCLK_GLB_BUSY_SHIFT)
672 
673 /*
674  * LOC_BUSY (RO)
675  *
676  * local busy
677  * 0: a change is pending for current node
678  * 1: current node is changing status
679  */
680 #define SYSCTL_I2SCLK_LOC_BUSY_MASK (0x40000000UL)
681 #define SYSCTL_I2SCLK_LOC_BUSY_SHIFT (30U)
682 #define SYSCTL_I2SCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_LOC_BUSY_MASK) >> SYSCTL_I2SCLK_LOC_BUSY_SHIFT)
683 
684 /*
685  * PRESERVE (RW)
686  *
687  * preserve function against global select
688  * 0: select global clock setting
689  * 1: not select global clock setting
690  */
691 #define SYSCTL_I2SCLK_PRESERVE_MASK (0x10000000UL)
692 #define SYSCTL_I2SCLK_PRESERVE_SHIFT (28U)
693 #define SYSCTL_I2SCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_I2SCLK_PRESERVE_SHIFT) & SYSCTL_I2SCLK_PRESERVE_MASK)
694 #define SYSCTL_I2SCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_PRESERVE_MASK) >> SYSCTL_I2SCLK_PRESERVE_SHIFT)
695 
696 /*
697  * MUX (RW)
698  *
699  * current mux
700  * 0: aud clock N
701  * 1: aud clock 0 for others , aud clock 1 for i2s0
702  */
703 #define SYSCTL_I2SCLK_MUX_MASK (0x100U)
704 #define SYSCTL_I2SCLK_MUX_SHIFT (8U)
705 #define SYSCTL_I2SCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_I2SCLK_MUX_SHIFT) & SYSCTL_I2SCLK_MUX_MASK)
706 #define SYSCTL_I2SCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_MUX_MASK) >> SYSCTL_I2SCLK_MUX_SHIFT)
707 
708 /* Bitfield definition for register: GLOBAL00 */
709 /*
710  * MUX (RW)
711  *
712  * global clock override request
713  * bit0: override to preset0
714  * bit1: override to preset1
715  * bit2: override to preset2
716  * bit3: override to preset3
717  * bit4: override to preset4
718  * bit5: override to preset5
719  * bit6: override to preset6
720  * bit7: override to preset7
721  */
722 #define SYSCTL_GLOBAL00_MUX_MASK (0xFFU)
723 #define SYSCTL_GLOBAL00_MUX_SHIFT (0U)
724 #define SYSCTL_GLOBAL00_MUX_SET(x) (((uint32_t)(x) << SYSCTL_GLOBAL00_MUX_SHIFT) & SYSCTL_GLOBAL00_MUX_MASK)
725 #define SYSCTL_GLOBAL00_MUX_GET(x) (((uint32_t)(x) & SYSCTL_GLOBAL00_MUX_MASK) >> SYSCTL_GLOBAL00_MUX_SHIFT)
726 
727 /* Bitfield definition for register of struct array MONITOR: CONTROL */
728 /*
729  * VALID (RW)
730  *
731  * result is ready for read
732  * 0: not ready
733  * 1: result is ready
734  */
735 #define SYSCTL_MONITOR_CONTROL_VALID_MASK (0x80000000UL)
736 #define SYSCTL_MONITOR_CONTROL_VALID_SHIFT (31U)
737 #define SYSCTL_MONITOR_CONTROL_VALID_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_VALID_SHIFT) & SYSCTL_MONITOR_CONTROL_VALID_MASK)
738 #define SYSCTL_MONITOR_CONTROL_VALID_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_VALID_MASK) >> SYSCTL_MONITOR_CONTROL_VALID_SHIFT)
739 
740 /*
741  * DIV_BUSY (RO)
742  *
743  * divider is applying new setting
744  */
745 #define SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK (0x8000000UL)
746 #define SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT (27U)
747 #define SYSCTL_MONITOR_CONTROL_DIV_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT)
748 
749 /*
750  * OUTEN (RW)
751  *
752  * enable clock output
753  */
754 #define SYSCTL_MONITOR_CONTROL_OUTEN_MASK (0x1000000UL)
755 #define SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT (24U)
756 #define SYSCTL_MONITOR_CONTROL_OUTEN_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK)
757 #define SYSCTL_MONITOR_CONTROL_OUTEN_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK) >> SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT)
758 
759 /*
760  * DIV (RW)
761  *
762  * output divider
763  */
764 #define SYSCTL_MONITOR_CONTROL_DIV_MASK (0xFF0000UL)
765 #define SYSCTL_MONITOR_CONTROL_DIV_SHIFT (16U)
766 #define SYSCTL_MONITOR_CONTROL_DIV_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_DIV_SHIFT) & SYSCTL_MONITOR_CONTROL_DIV_MASK)
767 #define SYSCTL_MONITOR_CONTROL_DIV_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_SHIFT)
768 
769 /*
770  * HIGH (RW)
771  *
772  * clock frequency higher than upper limit
773  */
774 #define SYSCTL_MONITOR_CONTROL_HIGH_MASK (0x8000U)
775 #define SYSCTL_MONITOR_CONTROL_HIGH_SHIFT (15U)
776 #define SYSCTL_MONITOR_CONTROL_HIGH_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_HIGH_SHIFT) & SYSCTL_MONITOR_CONTROL_HIGH_MASK)
777 #define SYSCTL_MONITOR_CONTROL_HIGH_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_HIGH_MASK) >> SYSCTL_MONITOR_CONTROL_HIGH_SHIFT)
778 
779 /*
780  * LOW (RW)
781  *
782  * clock frequency lower than lower limit
783  */
784 #define SYSCTL_MONITOR_CONTROL_LOW_MASK (0x4000U)
785 #define SYSCTL_MONITOR_CONTROL_LOW_SHIFT (14U)
786 #define SYSCTL_MONITOR_CONTROL_LOW_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_LOW_SHIFT) & SYSCTL_MONITOR_CONTROL_LOW_MASK)
787 #define SYSCTL_MONITOR_CONTROL_LOW_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_LOW_MASK) >> SYSCTL_MONITOR_CONTROL_LOW_SHIFT)
788 
789 /*
790  * START (RW)
791  *
792  * start measurement
793  */
794 #define SYSCTL_MONITOR_CONTROL_START_MASK (0x1000U)
795 #define SYSCTL_MONITOR_CONTROL_START_SHIFT (12U)
796 #define SYSCTL_MONITOR_CONTROL_START_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_START_SHIFT) & SYSCTL_MONITOR_CONTROL_START_MASK)
797 #define SYSCTL_MONITOR_CONTROL_START_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_START_MASK) >> SYSCTL_MONITOR_CONTROL_START_SHIFT)
798 
799 /*
800  * MODE (RW)
801  *
802  * work mode,
803  * 0: register value will be compared to measurement
804  * 1: upper and lower value will be recordered in register
805  */
806 #define SYSCTL_MONITOR_CONTROL_MODE_MASK (0x400U)
807 #define SYSCTL_MONITOR_CONTROL_MODE_SHIFT (10U)
808 #define SYSCTL_MONITOR_CONTROL_MODE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_MODE_SHIFT) & SYSCTL_MONITOR_CONTROL_MODE_MASK)
809 #define SYSCTL_MONITOR_CONTROL_MODE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_MODE_MASK) >> SYSCTL_MONITOR_CONTROL_MODE_SHIFT)
810 
811 /*
812  * ACCURACY (RW)
813  *
814  * measurement accuracy,
815  * 0: resolution is 1kHz
816  * 1: resolution is 1Hz
817  */
818 #define SYSCTL_MONITOR_CONTROL_ACCURACY_MASK (0x200U)
819 #define SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT (9U)
820 #define SYSCTL_MONITOR_CONTROL_ACCURACY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK)
821 #define SYSCTL_MONITOR_CONTROL_ACCURACY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK) >> SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT)
822 
823 /*
824  * REFERENCE (RW)
825  *
826  * refrence clock selection,
827  * 0: 32k
828  * 1: 24M
829  */
830 #define SYSCTL_MONITOR_CONTROL_REFERENCE_MASK (0x100U)
831 #define SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT (8U)
832 #define SYSCTL_MONITOR_CONTROL_REFERENCE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK)
833 #define SYSCTL_MONITOR_CONTROL_REFERENCE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK) >> SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT)
834 
835 /*
836  * SELECTION (RW)
837  *
838  * clock measurement selection
839  */
840 #define SYSCTL_MONITOR_CONTROL_SELECTION_MASK (0xFFU)
841 #define SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT (0U)
842 #define SYSCTL_MONITOR_CONTROL_SELECTION_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK)
843 #define SYSCTL_MONITOR_CONTROL_SELECTION_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK) >> SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT)
844 
845 /* Bitfield definition for register of struct array MONITOR: CURRENT */
846 /*
847  * FREQUENCY (RO)
848  *
849  * self updating measure result
850  */
851 #define SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK (0xFFFFFFFFUL)
852 #define SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT (0U)
853 #define SYSCTL_MONITOR_CURRENT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK) >> SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT)
854 
855 /* Bitfield definition for register of struct array MONITOR: LOW_LIMIT */
856 /*
857  * FREQUENCY (RW)
858  *
859  * lower frequency
860  */
861 #define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL)
862 #define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT (0U)
863 #define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK)
864 #define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT)
865 
866 /* Bitfield definition for register of struct array MONITOR: HIGH_LIMIT */
867 /*
868  * FREQUENCY (RW)
869  *
870  * upper frequency
871  */
872 #define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL)
873 #define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT (0U)
874 #define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK)
875 #define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT)
876 
877 /* Bitfield definition for register of struct array CPU: LP */
878 /*
879  * WAKE_CNT (RW)
880  *
881  * CPU0 wake up counter, counter satuated at 255, write 0x00 to clear
882  */
883 #define SYSCTL_CPU_LP_WAKE_CNT_MASK (0xFF000000UL)
884 #define SYSCTL_CPU_LP_WAKE_CNT_SHIFT (24U)
885 #define SYSCTL_CPU_LP_WAKE_CNT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_CNT_SHIFT) & SYSCTL_CPU_LP_WAKE_CNT_MASK)
886 #define SYSCTL_CPU_LP_WAKE_CNT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_CNT_MASK) >> SYSCTL_CPU_LP_WAKE_CNT_SHIFT)
887 
888 /*
889  * HALT (RW)
890  *
891  * halt request for CPU0,
892  * 0: CPU0 will start to execute after reset or receive wakeup request
893  * 1: CPU0 will not start after reset, or wakeup after WFI
894  */
895 #define SYSCTL_CPU_LP_HALT_MASK (0x10000UL)
896 #define SYSCTL_CPU_LP_HALT_SHIFT (16U)
897 #define SYSCTL_CPU_LP_HALT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_HALT_SHIFT) & SYSCTL_CPU_LP_HALT_MASK)
898 #define SYSCTL_CPU_LP_HALT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_HALT_MASK) >> SYSCTL_CPU_LP_HALT_SHIFT)
899 
900 /*
901  * WAKE (RO)
902  *
903  * CPU0 is waking up
904  * 0: CPU0 wake up not asserted
905  * 1: CPU0 wake up asserted
906  */
907 #define SYSCTL_CPU_LP_WAKE_MASK (0x2000U)
908 #define SYSCTL_CPU_LP_WAKE_SHIFT (13U)
909 #define SYSCTL_CPU_LP_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_MASK) >> SYSCTL_CPU_LP_WAKE_SHIFT)
910 
911 /*
912  * EXEC (RO)
913  *
914  * CPU0 is executing
915  * 0: CPU0 is not executing
916  * 1: CPU0 is executing
917  */
918 #define SYSCTL_CPU_LP_EXEC_MASK (0x1000U)
919 #define SYSCTL_CPU_LP_EXEC_SHIFT (12U)
920 #define SYSCTL_CPU_LP_EXEC_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_EXEC_MASK) >> SYSCTL_CPU_LP_EXEC_SHIFT)
921 
922 /*
923  * WAKE_FLAG (RW)
924  *
925  * CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit
926  * 0: CPU0 wakeup not happened
927  * 1: CPU0 wake up happened
928  */
929 #define SYSCTL_CPU_LP_WAKE_FLAG_MASK (0x400U)
930 #define SYSCTL_CPU_LP_WAKE_FLAG_SHIFT (10U)
931 #define SYSCTL_CPU_LP_WAKE_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_FLAG_SHIFT) & SYSCTL_CPU_LP_WAKE_FLAG_MASK)
932 #define SYSCTL_CPU_LP_WAKE_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_FLAG_MASK) >> SYSCTL_CPU_LP_WAKE_FLAG_SHIFT)
933 
934 /*
935  * SLEEP_FLAG (RW)
936  *
937  * CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit
938  * 0: CPU0 sleep not happened
939  * 1: CPU0 sleep happened
940  */
941 #define SYSCTL_CPU_LP_SLEEP_FLAG_MASK (0x200U)
942 #define SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT (9U)
943 #define SYSCTL_CPU_LP_SLEEP_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK)
944 #define SYSCTL_CPU_LP_SLEEP_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK) >> SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT)
945 
946 /*
947  * RESET_FLAG (RW)
948  *
949  * CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit
950  * 0: CPU0 reset not happened
951  * 1: CPU0 reset happened
952  */
953 #define SYSCTL_CPU_LP_RESET_FLAG_MASK (0x100U)
954 #define SYSCTL_CPU_LP_RESET_FLAG_SHIFT (8U)
955 #define SYSCTL_CPU_LP_RESET_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_RESET_FLAG_SHIFT) & SYSCTL_CPU_LP_RESET_FLAG_MASK)
956 #define SYSCTL_CPU_LP_RESET_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_RESET_FLAG_MASK) >> SYSCTL_CPU_LP_RESET_FLAG_SHIFT)
957 
958 /*
959  * MODE (RW)
960  *
961  * Low power mode, system behavior after WFI
962  * 00: CPU clock stop after WFI
963  * 01: System enter low power mode after WFI
964  * 10: Keep running after WFI
965  * 11: reserved
966  */
967 #define SYSCTL_CPU_LP_MODE_MASK (0x3U)
968 #define SYSCTL_CPU_LP_MODE_SHIFT (0U)
969 #define SYSCTL_CPU_LP_MODE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_MODE_SHIFT) & SYSCTL_CPU_LP_MODE_MASK)
970 #define SYSCTL_CPU_LP_MODE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_MODE_MASK) >> SYSCTL_CPU_LP_MODE_SHIFT)
971 
972 /* Bitfield definition for register of struct array CPU: LOCK */
973 /*
974  * GPR (RW)
975  *
976  * Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset
977  */
978 #define SYSCTL_CPU_LOCK_GPR_MASK (0xFFFCU)
979 #define SYSCTL_CPU_LOCK_GPR_SHIFT (2U)
980 #define SYSCTL_CPU_LOCK_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_GPR_SHIFT) & SYSCTL_CPU_LOCK_GPR_MASK)
981 #define SYSCTL_CPU_LOCK_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_GPR_MASK) >> SYSCTL_CPU_LOCK_GPR_SHIFT)
982 
983 /*
984  * LOCK (RW)
985  *
986  * Lock bit for CPU_LOCK
987  */
988 #define SYSCTL_CPU_LOCK_LOCK_MASK (0x2U)
989 #define SYSCTL_CPU_LOCK_LOCK_SHIFT (1U)
990 #define SYSCTL_CPU_LOCK_LOCK_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_LOCK_SHIFT) & SYSCTL_CPU_LOCK_LOCK_MASK)
991 #define SYSCTL_CPU_LOCK_LOCK_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_LOCK_MASK) >> SYSCTL_CPU_LOCK_LOCK_SHIFT)
992 
993 /* Bitfield definition for register of struct array CPU: GPR0 */
994 /*
995  * GPR (RW)
996  *
997  * register for software to handle resume, can save resume address or status
998  */
999 #define SYSCTL_CPU_GPR_GPR_MASK (0xFFFFFFFFUL)
1000 #define SYSCTL_CPU_GPR_GPR_SHIFT (0U)
1001 #define SYSCTL_CPU_GPR_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_GPR_GPR_SHIFT) & SYSCTL_CPU_GPR_GPR_MASK)
1002 #define SYSCTL_CPU_GPR_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_GPR_GPR_MASK) >> SYSCTL_CPU_GPR_GPR_SHIFT)
1003 
1004 /* Bitfield definition for register of struct array CPU: STATUS0 */
1005 /*
1006  * STATUS (RO)
1007  *
1008  * IRQ values
1009  */
1010 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK (0xFFFFFFFFUL)
1011 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT (0U)
1012 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK) >> SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT)
1013 
1014 /* Bitfield definition for register of struct array CPU: ENABLE0 */
1015 /*
1016  * ENABLE (RW)
1017  *
1018  * IRQ wakeup enable
1019  */
1020 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK (0xFFFFFFFFUL)
1021 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT (0U)
1022 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK)
1023 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK) >> SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT)
1024 
1025 
1026 
1027 /* RESOURCE register group index macro definition */
1028 #define SYSCTL_RESOURCE_CPU0 (0UL)
1029 #define SYSCTL_RESOURCE_CPX0 (1UL)
1030 #define SYSCTL_RESOURCE_CPU1 (8UL)
1031 #define SYSCTL_RESOURCE_CPX1 (9UL)
1032 #define SYSCTL_RESOURCE_POW_CPU0 (21UL)
1033 #define SYSCTL_RESOURCE_POW_CPU1 (22UL)
1034 #define SYSCTL_RESOURCE_RST_SOC (23UL)
1035 #define SYSCTL_RESOURCE_RST_CPU0 (24UL)
1036 #define SYSCTL_RESOURCE_RST_CPU1 (25UL)
1037 #define SYSCTL_RESOURCE_CLK_SRC_XTAL (32UL)
1038 #define SYSCTL_RESOURCE_CLK_SRC_PLL0 (33UL)
1039 #define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL0 (34UL)
1040 #define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL0 (35UL)
1041 #define SYSCTL_RESOURCE_CLK_SRC_PLL1 (36UL)
1042 #define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL1 (37UL)
1043 #define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL1 (38UL)
1044 #define SYSCTL_RESOURCE_CLK_SRC_CLK2_PLL1 (39UL)
1045 #define SYSCTL_RESOURCE_CLK_SRC_PLL2 (40UL)
1046 #define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL2 (41UL)
1047 #define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL2 (42UL)
1048 #define SYSCTL_RESOURCE_CLK_SRC_PLL0_REF (43UL)
1049 #define SYSCTL_RESOURCE_CLK_SRC_PLL1_REF (44UL)
1050 #define SYSCTL_RESOURCE_CLK_SRC_PLL2_REF (45UL)
1051 #define SYSCTL_RESOURCE_CLK_TOP_CPU0 (64UL)
1052 #define SYSCTL_RESOURCE_CLK_TOP_MCT0 (65UL)
1053 #define SYSCTL_RESOURCE_CLK_TOP_CPU1 (66UL)
1054 #define SYSCTL_RESOURCE_CLK_TOP_MCT1 (67UL)
1055 #define SYSCTL_RESOURCE_CLK_TOP_AHB0 (68UL)
1056 #define SYSCTL_RESOURCE_CLK_TOP_AXIF (69UL)
1057 #define SYSCTL_RESOURCE_CLK_TOP_AXIS (70UL)
1058 #define SYSCTL_RESOURCE_CLK_TOP_AXIC (71UL)
1059 #define SYSCTL_RESOURCE_CLK_TOP_TMR0 (72UL)
1060 #define SYSCTL_RESOURCE_CLK_TOP_TMR1 (73UL)
1061 #define SYSCTL_RESOURCE_CLK_TOP_TMR2 (74UL)
1062 #define SYSCTL_RESOURCE_CLK_TOP_TMR3 (75UL)
1063 #define SYSCTL_RESOURCE_CLK_TOP_I2C0 (76UL)
1064 #define SYSCTL_RESOURCE_CLK_TOP_I2C1 (77UL)
1065 #define SYSCTL_RESOURCE_CLK_TOP_I2C2 (78UL)
1066 #define SYSCTL_RESOURCE_CLK_TOP_I2C3 (79UL)
1067 #define SYSCTL_RESOURCE_CLK_TOP_SPI0 (80UL)
1068 #define SYSCTL_RESOURCE_CLK_TOP_SPI1 (81UL)
1069 #define SYSCTL_RESOURCE_CLK_TOP_SPI2 (82UL)
1070 #define SYSCTL_RESOURCE_CLK_TOP_SPI3 (83UL)
1071 #define SYSCTL_RESOURCE_CLK_TOP_URT0 (84UL)
1072 #define SYSCTL_RESOURCE_CLK_TOP_URT1 (85UL)
1073 #define SYSCTL_RESOURCE_CLK_TOP_URT2 (86UL)
1074 #define SYSCTL_RESOURCE_CLK_TOP_URT3 (87UL)
1075 #define SYSCTL_RESOURCE_CLK_TOP_URT4 (88UL)
1076 #define SYSCTL_RESOURCE_CLK_TOP_URT5 (89UL)
1077 #define SYSCTL_RESOURCE_CLK_TOP_URT6 (90UL)
1078 #define SYSCTL_RESOURCE_CLK_TOP_URT7 (91UL)
1079 #define SYSCTL_RESOURCE_CLK_TOP_CAN0 (92UL)
1080 #define SYSCTL_RESOURCE_CLK_TOP_CAN1 (93UL)
1081 #define SYSCTL_RESOURCE_CLK_TOP_CAN2 (94UL)
1082 #define SYSCTL_RESOURCE_CLK_TOP_CAN3 (95UL)
1083 #define SYSCTL_RESOURCE_CLK_TOP_XPI0 (96UL)
1084 #define SYSCTL_RESOURCE_CLK_TOP_FEMC (97UL)
1085 #define SYSCTL_RESOURCE_CLK_TOP_ETH0 (98UL)
1086 #define SYSCTL_RESOURCE_CLK_TOP_PTP0 (99UL)
1087 #define SYSCTL_RESOURCE_CLK_TOP_REF0 (100UL)
1088 #define SYSCTL_RESOURCE_CLK_TOP_REF1 (101UL)
1089 #define SYSCTL_RESOURCE_CLK_TOP_NTM0 (102UL)
1090 #define SYSCTL_RESOURCE_CLK_TOP_ANA0 (103UL)
1091 #define SYSCTL_RESOURCE_CLK_TOP_ANA1 (104UL)
1092 #define SYSCTL_RESOURCE_CLK_TOP_ANA2 (105UL)
1093 #define SYSCTL_RESOURCE_CLK_TOP_ANA3 (106UL)
1094 #define SYSCTL_RESOURCE_CLK_TOP_AUD0 (107UL)
1095 #define SYSCTL_RESOURCE_CLK_TOP_AUD1 (108UL)
1096 #define SYSCTL_RESOURCE_CLK_TOP_ADC0 (113UL)
1097 #define SYSCTL_RESOURCE_CLK_TOP_ADC1 (114UL)
1098 #define SYSCTL_RESOURCE_CLK_TOP_ADC2 (115UL)
1099 #define SYSCTL_RESOURCE_CLK_TOP_ADC3 (116UL)
1100 #define SYSCTL_RESOURCE_CLK_TOP_I2S0 (117UL)
1101 #define SYSCTL_RESOURCE_CLK_TOP_I2S1 (118UL)
1102 #define SYSCTL_RESOURCE_AHBP (256UL)
1103 #define SYSCTL_RESOURCE_AXIS (257UL)
1104 #define SYSCTL_RESOURCE_AXIC (258UL)
1105 #define SYSCTL_RESOURCE_ROM0 (259UL)
1106 #define SYSCTL_RESOURCE_LMM0 (260UL)
1107 #define SYSCTL_RESOURCE_MCT0 (261UL)
1108 #define SYSCTL_RESOURCE_LMM1 (262UL)
1109 #define SYSCTL_RESOURCE_MCT1 (263UL)
1110 #define SYSCTL_RESOURCE_TMR0 (264UL)
1111 #define SYSCTL_RESOURCE_TMR1 (265UL)
1112 #define SYSCTL_RESOURCE_TMR2 (266UL)
1113 #define SYSCTL_RESOURCE_TMR3 (267UL)
1114 #define SYSCTL_RESOURCE_I2C0 (268UL)
1115 #define SYSCTL_RESOURCE_I2C1 (269UL)
1116 #define SYSCTL_RESOURCE_I2C2 (270UL)
1117 #define SYSCTL_RESOURCE_I2C3 (271UL)
1118 #define SYSCTL_RESOURCE_SPI0 (272UL)
1119 #define SYSCTL_RESOURCE_SPI1 (273UL)
1120 #define SYSCTL_RESOURCE_SPI2 (274UL)
1121 #define SYSCTL_RESOURCE_SPI3 (275UL)
1122 #define SYSCTL_RESOURCE_URT0 (276UL)
1123 #define SYSCTL_RESOURCE_URT1 (277UL)
1124 #define SYSCTL_RESOURCE_URT2 (278UL)
1125 #define SYSCTL_RESOURCE_URT3 (279UL)
1126 #define SYSCTL_RESOURCE_URT4 (280UL)
1127 #define SYSCTL_RESOURCE_URT5 (281UL)
1128 #define SYSCTL_RESOURCE_URT6 (282UL)
1129 #define SYSCTL_RESOURCE_URT7 (283UL)
1130 #define SYSCTL_RESOURCE_CRC0 (284UL)
1131 #define SYSCTL_RESOURCE_TSNS (285UL)
1132 #define SYSCTL_RESOURCE_WDG0 (286UL)
1133 #define SYSCTL_RESOURCE_WDG1 (287UL)
1134 #define SYSCTL_RESOURCE_WDG2 (288UL)
1135 #define SYSCTL_RESOURCE_WDG3 (289UL)
1136 #define SYSCTL_RESOURCE_MBX0 (290UL)
1137 #define SYSCTL_RESOURCE_MBX1 (291UL)
1138 #define SYSCTL_RESOURCE_GPIO (292UL)
1139 #define SYSCTL_RESOURCE_PPI0 (293UL)
1140 #define SYSCTL_RESOURCE_HDMA (294UL)
1141 #define SYSCTL_RESOURCE_LOBS (295UL)
1142 #define SYSCTL_RESOURCE_ADC0 (296UL)
1143 #define SYSCTL_RESOURCE_ADC1 (297UL)
1144 #define SYSCTL_RESOURCE_ADC2 (298UL)
1145 #define SYSCTL_RESOURCE_ADC3 (299UL)
1146 #define SYSCTL_RESOURCE_DAC0 (300UL)
1147 #define SYSCTL_RESOURCE_DAC1 (301UL)
1148 #define SYSCTL_RESOURCE_CMP0 (302UL)
1149 #define SYSCTL_RESOURCE_CMP1 (303UL)
1150 #define SYSCTL_RESOURCE_CMP2 (304UL)
1151 #define SYSCTL_RESOURCE_CMP3 (305UL)
1152 #define SYSCTL_RESOURCE_I2S0 (306UL)
1153 #define SYSCTL_RESOURCE_I2S1 (307UL)
1154 #define SYSCTL_RESOURCE_PDM0 (308UL)
1155 #define SYSCTL_RESOURCE_CLSD (309UL)
1156 #define SYSCTL_RESOURCE_CAN0 (310UL)
1157 #define SYSCTL_RESOURCE_CAN1 (311UL)
1158 #define SYSCTL_RESOURCE_CAN2 (312UL)
1159 #define SYSCTL_RESOURCE_CAN3 (313UL)
1160 #define SYSCTL_RESOURCE_PTPC (314UL)
1161 #define SYSCTL_RESOURCE_QEI0 (315UL)
1162 #define SYSCTL_RESOURCE_QEI1 (316UL)
1163 #define SYSCTL_RESOURCE_QEO0 (317UL)
1164 #define SYSCTL_RESOURCE_QEO1 (318UL)
1165 #define SYSCTL_RESOURCE_PWM0 (319UL)
1166 #define SYSCTL_RESOURCE_PWM1 (320UL)
1167 #define SYSCTL_RESOURCE_PWM2 (321UL)
1168 #define SYSCTL_RESOURCE_PWM3 (322UL)
1169 #define SYSCTL_RESOURCE_RDC0 (323UL)
1170 #define SYSCTL_RESOURCE_SDM0 (324UL)
1171 #define SYSCTL_RESOURCE_PLB0 (325UL)
1172 #define SYSCTL_RESOURCE_SEI0 (326UL)
1173 #define SYSCTL_RESOURCE_MTG0 (327UL)
1174 #define SYSCTL_RESOURCE_VSC0 (328UL)
1175 #define SYSCTL_RESOURCE_CLC0 (329UL)
1176 #define SYSCTL_RESOURCE_EMDS (330UL)
1177 #define SYSCTL_RESOURCE_RNG0 (331UL)
1178 #define SYSCTL_RESOURCE_SDP0 (332UL)
1179 #define SYSCTL_RESOURCE_KMAN (333UL)
1180 #define SYSCTL_RESOURCE_XPI0 (334UL)
1181 #define SYSCTL_RESOURCE_FEMC (335UL)
1182 #define SYSCTL_RESOURCE_RAM0 (336UL)
1183 #define SYSCTL_RESOURCE_XDMA (337UL)
1184 #define SYSCTL_RESOURCE_FFA0 (338UL)
1185 #define SYSCTL_RESOURCE_ETH0 (339UL)
1186 #define SYSCTL_RESOURCE_USB0 (340UL)
1187 #define SYSCTL_RESOURCE_NTM0 (341UL)
1188 #define SYSCTL_RESOURCE_REF0 (342UL)
1189 #define SYSCTL_RESOURCE_REF1 (343UL)
1190 
1191 /* GROUP0 register group index macro definition */
1192 #define SYSCTL_GROUP0_LINK0 (0UL)
1193 #define SYSCTL_GROUP0_LINK1 (1UL)
1194 #define SYSCTL_GROUP0_LINK2 (2UL)
1195 
1196 /* GROUP1 register group index macro definition */
1197 #define SYSCTL_GROUP1_LINK0 (0UL)
1198 #define SYSCTL_GROUP1_LINK1 (1UL)
1199 #define SYSCTL_GROUP1_LINK2 (2UL)
1200 
1201 /* AFFILIATE register group index macro definition */
1202 #define SYSCTL_AFFILIATE_CPU0 (0UL)
1203 #define SYSCTL_AFFILIATE_CPU1 (1UL)
1204 
1205 /* RETENTION register group index macro definition */
1206 #define SYSCTL_RETENTION_CPU0 (0UL)
1207 #define SYSCTL_RETENTION_CPU1 (1UL)
1208 
1209 /* POWER register group index macro definition */
1210 #define SYSCTL_POWER_CPU0 (0UL)
1211 #define SYSCTL_POWER_CPU1 (1UL)
1212 
1213 /* RESET register group index macro definition */
1214 #define SYSCTL_RESET_SOC (0UL)
1215 #define SYSCTL_RESET_CPU0 (1UL)
1216 #define SYSCTL_RESET_CPU1 (2UL)
1217 
1218 /* CLOCK register group index macro definition */
1219 #define SYSCTL_CLOCK_CLK_TOP_CPU0 (0UL)
1220 #define SYSCTL_CLOCK_CLK_TOP_MCT0 (1UL)
1221 #define SYSCTL_CLOCK_CLK_TOP_CPU1 (2UL)
1222 #define SYSCTL_CLOCK_CLK_TOP_MCT1 (3UL)
1223 #define SYSCTL_CLOCK_CLK_TOP_AHB0 (4UL)
1224 #define SYSCTL_CLOCK_CLK_TOP_AXIF (5UL)
1225 #define SYSCTL_CLOCK_CLK_TOP_AXIS (6UL)
1226 #define SYSCTL_CLOCK_CLK_TOP_AXIC (7UL)
1227 #define SYSCTL_CLOCK_CLK_TOP_TMR0 (8UL)
1228 #define SYSCTL_CLOCK_CLK_TOP_TMR1 (9UL)
1229 #define SYSCTL_CLOCK_CLK_TOP_TMR2 (10UL)
1230 #define SYSCTL_CLOCK_CLK_TOP_TMR3 (11UL)
1231 #define SYSCTL_CLOCK_CLK_TOP_I2C0 (12UL)
1232 #define SYSCTL_CLOCK_CLK_TOP_I2C1 (13UL)
1233 #define SYSCTL_CLOCK_CLK_TOP_I2C2 (14UL)
1234 #define SYSCTL_CLOCK_CLK_TOP_I2C3 (15UL)
1235 #define SYSCTL_CLOCK_CLK_TOP_SPI0 (16UL)
1236 #define SYSCTL_CLOCK_CLK_TOP_SPI1 (17UL)
1237 #define SYSCTL_CLOCK_CLK_TOP_SPI2 (18UL)
1238 #define SYSCTL_CLOCK_CLK_TOP_SPI3 (19UL)
1239 #define SYSCTL_CLOCK_CLK_TOP_URT0 (20UL)
1240 #define SYSCTL_CLOCK_CLK_TOP_URT1 (21UL)
1241 #define SYSCTL_CLOCK_CLK_TOP_URT2 (22UL)
1242 #define SYSCTL_CLOCK_CLK_TOP_URT3 (23UL)
1243 #define SYSCTL_CLOCK_CLK_TOP_URT4 (24UL)
1244 #define SYSCTL_CLOCK_CLK_TOP_URT5 (25UL)
1245 #define SYSCTL_CLOCK_CLK_TOP_URT6 (26UL)
1246 #define SYSCTL_CLOCK_CLK_TOP_URT7 (27UL)
1247 #define SYSCTL_CLOCK_CLK_TOP_CAN0 (28UL)
1248 #define SYSCTL_CLOCK_CLK_TOP_CAN1 (29UL)
1249 #define SYSCTL_CLOCK_CLK_TOP_CAN2 (30UL)
1250 #define SYSCTL_CLOCK_CLK_TOP_CAN3 (31UL)
1251 #define SYSCTL_CLOCK_CLK_TOP_XPI0 (32UL)
1252 #define SYSCTL_CLOCK_CLK_TOP_FEMC (33UL)
1253 #define SYSCTL_CLOCK_CLK_TOP_ETH0 (34UL)
1254 #define SYSCTL_CLOCK_CLK_TOP_PTP0 (35UL)
1255 #define SYSCTL_CLOCK_CLK_TOP_REF0 (36UL)
1256 #define SYSCTL_CLOCK_CLK_TOP_REF1 (37UL)
1257 #define SYSCTL_CLOCK_CLK_TOP_NTM0 (38UL)
1258 #define SYSCTL_CLOCK_CLK_TOP_ANA0 (39UL)
1259 #define SYSCTL_CLOCK_CLK_TOP_ANA1 (40UL)
1260 #define SYSCTL_CLOCK_CLK_TOP_ANA2 (41UL)
1261 #define SYSCTL_CLOCK_CLK_TOP_ANA3 (42UL)
1262 #define SYSCTL_CLOCK_CLK_TOP_AUD0 (43UL)
1263 #define SYSCTL_CLOCK_CLK_TOP_AUD1 (44UL)
1264 
1265 /* ADCCLK register group index macro definition */
1266 #define SYSCTL_ADCCLK_CLK_TOP_ADC0 (0UL)
1267 #define SYSCTL_ADCCLK_CLK_TOP_ADC1 (1UL)
1268 #define SYSCTL_ADCCLK_CLK_TOP_ADC2 (2UL)
1269 #define SYSCTL_ADCCLK_CLK_TOP_ADC3 (3UL)
1270 
1271 /* I2SCLK register group index macro definition */
1272 #define SYSCTL_I2SCLK_CLK_TOP_I2S0 (0UL)
1273 #define SYSCTL_I2SCLK_CLK_TOP_I2S1 (1UL)
1274 
1275 /* MONITOR register group index macro definition */
1276 #define SYSCTL_MONITOR_SLICE0 (0UL)
1277 #define SYSCTL_MONITOR_SLICE1 (1UL)
1278 #define SYSCTL_MONITOR_SLICE2 (2UL)
1279 #define SYSCTL_MONITOR_SLICE3 (3UL)
1280 
1281 /* GPR register group index macro definition */
1282 #define SYSCTL_CPU_GPR_GPR0 (0UL)
1283 #define SYSCTL_CPU_GPR_GPR1 (1UL)
1284 #define SYSCTL_CPU_GPR_GPR2 (2UL)
1285 #define SYSCTL_CPU_GPR_GPR3 (3UL)
1286 #define SYSCTL_CPU_GPR_GPR4 (4UL)
1287 #define SYSCTL_CPU_GPR_GPR5 (5UL)
1288 #define SYSCTL_CPU_GPR_GPR6 (6UL)
1289 #define SYSCTL_CPU_GPR_GPR7 (7UL)
1290 #define SYSCTL_CPU_GPR_GPR8 (8UL)
1291 #define SYSCTL_CPU_GPR_GPR9 (9UL)
1292 #define SYSCTL_CPU_GPR_GPR10 (10UL)
1293 #define SYSCTL_CPU_GPR_GPR11 (11UL)
1294 #define SYSCTL_CPU_GPR_GPR12 (12UL)
1295 #define SYSCTL_CPU_GPR_GPR13 (13UL)
1296 
1297 /* WAKEUP_STATUS register group index macro definition */
1298 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS0 (0UL)
1299 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS1 (1UL)
1300 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS2 (2UL)
1301 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS3 (3UL)
1302 
1303 /* WAKEUP_ENABLE register group index macro definition */
1304 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE0 (0UL)
1305 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE1 (1UL)
1306 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE2 (2UL)
1307 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE3 (3UL)
1308 
1309 /* CPU register group index macro definition */
1310 #define SYSCTL_CPU_CPU0 (0UL)
1311 #define SYSCTL_CPU_CPU1 (1UL)
1312 
1313 
1314 #endif /* HPM_SYSCTL_H */
SYSCTL_Type
Definition: hpm_sysctl_regs.h:12