HPM SDK
HPMicro Software Development Kit
hpm_vsc_regs.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_VSC_H
10 #define HPM_VSC_H
11 
12 typedef struct {
13  __RW uint32_t ABC_MODE; /* 0x0: abc mode */
14  __RW uint32_t ADC_CHAN_ASSIGN; /* 0x4: assign adc_chan for value_a/b/c */
15  __RW uint32_t VALUE_A_DATA_OPT; /* 0x8: value_a data operation mode */
16  __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */
17  __RW uint32_t VALUE_B_DATA_OPT; /* 0x10: value_b data operation mode */
18  __R uint8_t RESERVED1[4]; /* 0x14 - 0x17: Reserved */
19  __RW uint32_t VALUE_C_DATA_OPT; /* 0x18: value_c data operation mode */
20  __R uint8_t RESERVED2[4]; /* 0x1C - 0x1F: Reserved */
21  __RW uint32_t VALUE_A_OFFSET; /* 0x20: value_a offset */
22  __RW uint32_t VALUE_B_OFFSET; /* 0x24: value_b_offset */
23  __RW uint32_t VALUE_C_OFFSET; /* 0x28: value_c offset */
24  __RW uint32_t IRQ_STATUS; /* 0x2C: irq status */
25  __RW uint32_t VALUE_A_SW; /* 0x30: value_a software inject value */
26  __RW uint32_t VALUE_B_SW; /* 0x34: value_b software inject value */
27  __RW uint32_t VALUE_C_SW; /* 0x38: value_c software inject value */
28  __W uint32_t VALUE_SW_READY; /* 0x3C: software inject value_a/value_b/value_c ready */
29  __W uint32_t TRIGGER_SW; /* 0x40: software trigger event */
30  __RW uint32_t TIMELOCK; /* 0x44: timestamp mode and postion capture ctrl */
31  __RW uint32_t POSITION_SW; /* 0x48: position software inject value */
32  __RW uint32_t ADC_WAIT_CYCLE; /* 0x4C: adc wait cycle after trigger adc capture event */
33  __RW uint32_t POS_WAIT_CYCLE; /* 0x50: pos wait cycle after trigger adc capture event */
34  __RW uint32_t IRQ_ENABLE; /* 0x54: irq bit enable */
35  __RW uint32_t ADC_PHASE_TOLERATE; /* 0x58: adc phase tolerate */
36  __RW uint32_t POS_POLE; /* 0x5C: position pole num */
37  __R uint8_t RESERVED3[160]; /* 0x60 - 0xFF: Reserved */
38  __R uint32_t ID_POSEDGE; /* 0x100: posedge order Id value */
39  __R uint32_t IQ_POSEDGE; /* 0x104: posedge order Iq value */
40  __R uint32_t ID_NEGEDGE; /* 0x108: negedge order Id value */
41  __R uint32_t IQ_NEGEDGE; /* 0x10C: negedge order Iq value */
42  __R uint32_t ALPHA_POSEDGE; /* 0x110: posedge order alpha value */
43  __R uint32_t BETA_POSEDGE; /* 0x114: posedge order beta value */
44  __R uint32_t ALPHA_NEGEDGE; /* 0x118: negedge order alpha value */
45  __R uint32_t BETA_NEGEDGE; /* 0x11C: negedge order beta value */
46  __R uint32_t TIMESTAMP_LOCKED; /* 0x120: timestamp_locked */
47  __R uint32_t DEBUG_STATUS0; /* 0x124: debug_status0 */
48 } VSC_Type;
49 
50 
51 /* Bitfield definition for register: ABC_MODE */
52 /*
53  * PHASE_ABSENT_MODE (RW)
54  *
55  * whether using value_a and value_b instead of three phase
56  */
57 #define VSC_ABC_MODE_PHASE_ABSENT_MODE_MASK (0x80000000UL)
58 #define VSC_ABC_MODE_PHASE_ABSENT_MODE_SHIFT (31U)
59 #define VSC_ABC_MODE_PHASE_ABSENT_MODE_SET(x) (((uint32_t)(x) << VSC_ABC_MODE_PHASE_ABSENT_MODE_SHIFT) & VSC_ABC_MODE_PHASE_ABSENT_MODE_MASK)
60 #define VSC_ABC_MODE_PHASE_ABSENT_MODE_GET(x) (((uint32_t)(x) & VSC_ABC_MODE_PHASE_ABSENT_MODE_MASK) >> VSC_ABC_MODE_PHASE_ABSENT_MODE_SHIFT)
61 
62 /*
63  * POSTION_USE_LAST_LOCKED (RW)
64  *
65  * position will not blockage vsc convert. always use last locked position, it should be cfg to 1 when position_capture_mode=2'b00 and adc valure are injected by software;
66  */
67 #define VSC_ABC_MODE_POSTION_USE_LAST_LOCKED_MASK (0x40000000UL)
68 #define VSC_ABC_MODE_POSTION_USE_LAST_LOCKED_SHIFT (30U)
69 #define VSC_ABC_MODE_POSTION_USE_LAST_LOCKED_SET(x) (((uint32_t)(x) << VSC_ABC_MODE_POSTION_USE_LAST_LOCKED_SHIFT) & VSC_ABC_MODE_POSTION_USE_LAST_LOCKED_MASK)
70 #define VSC_ABC_MODE_POSTION_USE_LAST_LOCKED_GET(x) (((uint32_t)(x) & VSC_ABC_MODE_POSTION_USE_LAST_LOCKED_MASK) >> VSC_ABC_MODE_POSTION_USE_LAST_LOCKED_SHIFT)
71 
72 /*
73  * VALUE_C_WIDTH (RW)
74  *
75  * numbers of value_c for each convert
76  */
77 #define VSC_ABC_MODE_VALUE_C_WIDTH_MASK (0xF000000UL)
78 #define VSC_ABC_MODE_VALUE_C_WIDTH_SHIFT (24U)
79 #define VSC_ABC_MODE_VALUE_C_WIDTH_SET(x) (((uint32_t)(x) << VSC_ABC_MODE_VALUE_C_WIDTH_SHIFT) & VSC_ABC_MODE_VALUE_C_WIDTH_MASK)
80 #define VSC_ABC_MODE_VALUE_C_WIDTH_GET(x) (((uint32_t)(x) & VSC_ABC_MODE_VALUE_C_WIDTH_MASK) >> VSC_ABC_MODE_VALUE_C_WIDTH_SHIFT)
81 
82 /*
83  * VALUE_B_WIDTH (RW)
84  *
85  * numbers of value_b for each convert
86  */
87 #define VSC_ABC_MODE_VALUE_B_WIDTH_MASK (0xF00000UL)
88 #define VSC_ABC_MODE_VALUE_B_WIDTH_SHIFT (20U)
89 #define VSC_ABC_MODE_VALUE_B_WIDTH_SET(x) (((uint32_t)(x) << VSC_ABC_MODE_VALUE_B_WIDTH_SHIFT) & VSC_ABC_MODE_VALUE_B_WIDTH_MASK)
90 #define VSC_ABC_MODE_VALUE_B_WIDTH_GET(x) (((uint32_t)(x) & VSC_ABC_MODE_VALUE_B_WIDTH_MASK) >> VSC_ABC_MODE_VALUE_B_WIDTH_SHIFT)
91 
92 /*
93  * VALUE_A_WIDTH (RW)
94  *
95  * numbers of value_a for each convert
96  */
97 #define VSC_ABC_MODE_VALUE_A_WIDTH_MASK (0xF0000UL)
98 #define VSC_ABC_MODE_VALUE_A_WIDTH_SHIFT (16U)
99 #define VSC_ABC_MODE_VALUE_A_WIDTH_SET(x) (((uint32_t)(x) << VSC_ABC_MODE_VALUE_A_WIDTH_SHIFT) & VSC_ABC_MODE_VALUE_A_WIDTH_MASK)
100 #define VSC_ABC_MODE_VALUE_A_WIDTH_GET(x) (((uint32_t)(x) & VSC_ABC_MODE_VALUE_A_WIDTH_MASK) >> VSC_ABC_MODE_VALUE_A_WIDTH_SHIFT)
101 
102 /*
103  * VALUE_C_LOC (RW)
104  *
105  * the adc index of value_c:
106  * 2'b:00: resevered;
107  * 2'b:01: from adc0;
108  * 2'b:10: from adc1;
109  * 2'b:11: from adc2;
110  */
111 #define VSC_ABC_MODE_VALUE_C_LOC_MASK (0x3000U)
112 #define VSC_ABC_MODE_VALUE_C_LOC_SHIFT (12U)
113 #define VSC_ABC_MODE_VALUE_C_LOC_SET(x) (((uint32_t)(x) << VSC_ABC_MODE_VALUE_C_LOC_SHIFT) & VSC_ABC_MODE_VALUE_C_LOC_MASK)
114 #define VSC_ABC_MODE_VALUE_C_LOC_GET(x) (((uint32_t)(x) & VSC_ABC_MODE_VALUE_C_LOC_MASK) >> VSC_ABC_MODE_VALUE_C_LOC_SHIFT)
115 
116 /*
117  * VALUE_B_LOC (RW)
118  *
119  * the adc index of value_b:
120  * 2'b:00: resevered;
121  * 2'b:01: from adc0;
122  * 2'b:10: from adc1;
123  * 2'b:11: from adc2;
124  */
125 #define VSC_ABC_MODE_VALUE_B_LOC_MASK (0x300U)
126 #define VSC_ABC_MODE_VALUE_B_LOC_SHIFT (8U)
127 #define VSC_ABC_MODE_VALUE_B_LOC_SET(x) (((uint32_t)(x) << VSC_ABC_MODE_VALUE_B_LOC_SHIFT) & VSC_ABC_MODE_VALUE_B_LOC_MASK)
128 #define VSC_ABC_MODE_VALUE_B_LOC_GET(x) (((uint32_t)(x) & VSC_ABC_MODE_VALUE_B_LOC_MASK) >> VSC_ABC_MODE_VALUE_B_LOC_SHIFT)
129 
130 /*
131  * VALUE_A_LOC (RW)
132  *
133  * the adc index of value_a:
134  * 2'b:00: resevered;
135  * 2'b:01: from adc0;
136  * 2'b:10: from adc1;
137  * 2'b:11: from adc2;
138  */
139 #define VSC_ABC_MODE_VALUE_A_LOC_MASK (0x30U)
140 #define VSC_ABC_MODE_VALUE_A_LOC_SHIFT (4U)
141 #define VSC_ABC_MODE_VALUE_A_LOC_SET(x) (((uint32_t)(x) << VSC_ABC_MODE_VALUE_A_LOC_SHIFT) & VSC_ABC_MODE_VALUE_A_LOC_MASK)
142 #define VSC_ABC_MODE_VALUE_A_LOC_GET(x) (((uint32_t)(x) & VSC_ABC_MODE_VALUE_A_LOC_MASK) >> VSC_ABC_MODE_VALUE_A_LOC_SHIFT)
143 
144 /*
145  * ENABLE_VSC (RW)
146  *
147  * enable vsc convert:
148  * 0: disable vsc convert
149  * 1: enable vsc convert
150  */
151 #define VSC_ABC_MODE_ENABLE_VSC_MASK (0x8U)
152 #define VSC_ABC_MODE_ENABLE_VSC_SHIFT (3U)
153 #define VSC_ABC_MODE_ENABLE_VSC_SET(x) (((uint32_t)(x) << VSC_ABC_MODE_ENABLE_VSC_SHIFT) & VSC_ABC_MODE_ENABLE_VSC_MASK)
154 #define VSC_ABC_MODE_ENABLE_VSC_GET(x) (((uint32_t)(x) & VSC_ABC_MODE_ENABLE_VSC_MASK) >> VSC_ABC_MODE_ENABLE_VSC_SHIFT)
155 
156 /* Bitfield definition for register: ADC_CHAN_ASSIGN */
157 /*
158  * VALUE_C_CHAN (RW)
159  *
160  * value_c's adc chan
161  */
162 #define VSC_ADC_CHAN_ASSIGN_VALUE_C_CHAN_MASK (0x1F0000UL)
163 #define VSC_ADC_CHAN_ASSIGN_VALUE_C_CHAN_SHIFT (16U)
164 #define VSC_ADC_CHAN_ASSIGN_VALUE_C_CHAN_SET(x) (((uint32_t)(x) << VSC_ADC_CHAN_ASSIGN_VALUE_C_CHAN_SHIFT) & VSC_ADC_CHAN_ASSIGN_VALUE_C_CHAN_MASK)
165 #define VSC_ADC_CHAN_ASSIGN_VALUE_C_CHAN_GET(x) (((uint32_t)(x) & VSC_ADC_CHAN_ASSIGN_VALUE_C_CHAN_MASK) >> VSC_ADC_CHAN_ASSIGN_VALUE_C_CHAN_SHIFT)
166 
167 /*
168  * VALUE_B_CHAN (RW)
169  *
170  * value_b's adc chan
171  */
172 #define VSC_ADC_CHAN_ASSIGN_VALUE_B_CHAN_MASK (0x1F00U)
173 #define VSC_ADC_CHAN_ASSIGN_VALUE_B_CHAN_SHIFT (8U)
174 #define VSC_ADC_CHAN_ASSIGN_VALUE_B_CHAN_SET(x) (((uint32_t)(x) << VSC_ADC_CHAN_ASSIGN_VALUE_B_CHAN_SHIFT) & VSC_ADC_CHAN_ASSIGN_VALUE_B_CHAN_MASK)
175 #define VSC_ADC_CHAN_ASSIGN_VALUE_B_CHAN_GET(x) (((uint32_t)(x) & VSC_ADC_CHAN_ASSIGN_VALUE_B_CHAN_MASK) >> VSC_ADC_CHAN_ASSIGN_VALUE_B_CHAN_SHIFT)
176 
177 /*
178  * VALUE_A_CHAN (RW)
179  *
180  * value_a's adc chan
181  */
182 #define VSC_ADC_CHAN_ASSIGN_VALUE_A_CHAN_MASK (0x1FU)
183 #define VSC_ADC_CHAN_ASSIGN_VALUE_A_CHAN_SHIFT (0U)
184 #define VSC_ADC_CHAN_ASSIGN_VALUE_A_CHAN_SET(x) (((uint32_t)(x) << VSC_ADC_CHAN_ASSIGN_VALUE_A_CHAN_SHIFT) & VSC_ADC_CHAN_ASSIGN_VALUE_A_CHAN_MASK)
185 #define VSC_ADC_CHAN_ASSIGN_VALUE_A_CHAN_GET(x) (((uint32_t)(x) & VSC_ADC_CHAN_ASSIGN_VALUE_A_CHAN_MASK) >> VSC_ADC_CHAN_ASSIGN_VALUE_A_CHAN_SHIFT)
186 
187 /* Bitfield definition for register: VALUE_A_DATA_OPT */
188 /*
189  * OPT_3 (RW)
190  *
191  * 0: PLUS_MUL_1
192  * 1: PLUS_MUL_2
193  * 5: PLUS_DIV_2
194  * 6: PLUS_DIV_3
195  * 7: PLUS_DIV_4
196  * 8: MINUS MUL 1
197  * 9: MINUS MUL 2
198  * 13: MINUS DIV 2
199  * 14: MINUS DIV 3
200  * 15: MINUS DIV 4
201  */
202 #define VSC_VALUE_A_DATA_OPT_OPT_3_MASK (0xF000U)
203 #define VSC_VALUE_A_DATA_OPT_OPT_3_SHIFT (12U)
204 #define VSC_VALUE_A_DATA_OPT_OPT_3_SET(x) (((uint32_t)(x) << VSC_VALUE_A_DATA_OPT_OPT_3_SHIFT) & VSC_VALUE_A_DATA_OPT_OPT_3_MASK)
205 #define VSC_VALUE_A_DATA_OPT_OPT_3_GET(x) (((uint32_t)(x) & VSC_VALUE_A_DATA_OPT_OPT_3_MASK) >> VSC_VALUE_A_DATA_OPT_OPT_3_SHIFT)
206 
207 /*
208  * OPT_2 (RW)
209  *
210  * 0: PLUS_MUL_1
211  * 1: PLUS_MUL_2
212  * 5: PLUS_DIV_2
213  * 6: PLUS_DIV_3
214  * 7: PLUS_DIV_4
215  * 8: MINUS MUL 1
216  * 9: MINUS MUL 2
217  * 13: MINUS DIV 2
218  * 14: MINUS DIV 3
219  * 15: MINUS DIV 4
220  */
221 #define VSC_VALUE_A_DATA_OPT_OPT_2_MASK (0xF00U)
222 #define VSC_VALUE_A_DATA_OPT_OPT_2_SHIFT (8U)
223 #define VSC_VALUE_A_DATA_OPT_OPT_2_SET(x) (((uint32_t)(x) << VSC_VALUE_A_DATA_OPT_OPT_2_SHIFT) & VSC_VALUE_A_DATA_OPT_OPT_2_MASK)
224 #define VSC_VALUE_A_DATA_OPT_OPT_2_GET(x) (((uint32_t)(x) & VSC_VALUE_A_DATA_OPT_OPT_2_MASK) >> VSC_VALUE_A_DATA_OPT_OPT_2_SHIFT)
225 
226 /*
227  * OPT_1 (RW)
228  *
229  * 0: PLUS_MUL_1
230  * 1: PLUS_MUL_2
231  * 5: PLUS_DIV_2
232  * 6: PLUS_DIV_3
233  * 7: PLUS_DIV_4
234  * 8: MINUS MUL 1
235  * 9: MINUS MUL 2
236  * 13: MINUS DIV 2
237  * 14: MINUS DIV 3
238  * 15: MINUS DIV 4
239  */
240 #define VSC_VALUE_A_DATA_OPT_OPT_1_MASK (0xF0U)
241 #define VSC_VALUE_A_DATA_OPT_OPT_1_SHIFT (4U)
242 #define VSC_VALUE_A_DATA_OPT_OPT_1_SET(x) (((uint32_t)(x) << VSC_VALUE_A_DATA_OPT_OPT_1_SHIFT) & VSC_VALUE_A_DATA_OPT_OPT_1_MASK)
243 #define VSC_VALUE_A_DATA_OPT_OPT_1_GET(x) (((uint32_t)(x) & VSC_VALUE_A_DATA_OPT_OPT_1_MASK) >> VSC_VALUE_A_DATA_OPT_OPT_1_SHIFT)
244 
245 /*
246  * OPT_0 (RW)
247  *
248  * 0: PLUS_MUL_1
249  * 1: PLUS_MUL_2
250  * 5: PLUS_DIV_2
251  * 6: PLUS_DIV_3
252  * 7: PLUS_DIV_4
253  * 8: MINUS MUL 1
254  * 9: MINUS MUL 2
255  * 13: MINUS DIV 2
256  * 14: MINUS DIV 3
257  * 15: MINUS DIV 4
258  */
259 #define VSC_VALUE_A_DATA_OPT_OPT_0_MASK (0xFU)
260 #define VSC_VALUE_A_DATA_OPT_OPT_0_SHIFT (0U)
261 #define VSC_VALUE_A_DATA_OPT_OPT_0_SET(x) (((uint32_t)(x) << VSC_VALUE_A_DATA_OPT_OPT_0_SHIFT) & VSC_VALUE_A_DATA_OPT_OPT_0_MASK)
262 #define VSC_VALUE_A_DATA_OPT_OPT_0_GET(x) (((uint32_t)(x) & VSC_VALUE_A_DATA_OPT_OPT_0_MASK) >> VSC_VALUE_A_DATA_OPT_OPT_0_SHIFT)
263 
264 /* Bitfield definition for register: VALUE_B_DATA_OPT */
265 /*
266  * OPT_3 (RW)
267  *
268  * 0: PLUS_MUL_1
269  * 1: PLUS_MUL_2
270  * 5: PLUS_DIV_2
271  * 6: PLUS_DIV_3
272  * 7: PLUS_DIV_4
273  * 8: MINUS MUL 1
274  * 9: MINUS MUL 2
275  * 13: MINUS DIV 2
276  * 14: MINUS DIV 3
277  * 15: MINUS DIV 4
278  */
279 #define VSC_VALUE_B_DATA_OPT_OPT_3_MASK (0xF000U)
280 #define VSC_VALUE_B_DATA_OPT_OPT_3_SHIFT (12U)
281 #define VSC_VALUE_B_DATA_OPT_OPT_3_SET(x) (((uint32_t)(x) << VSC_VALUE_B_DATA_OPT_OPT_3_SHIFT) & VSC_VALUE_B_DATA_OPT_OPT_3_MASK)
282 #define VSC_VALUE_B_DATA_OPT_OPT_3_GET(x) (((uint32_t)(x) & VSC_VALUE_B_DATA_OPT_OPT_3_MASK) >> VSC_VALUE_B_DATA_OPT_OPT_3_SHIFT)
283 
284 /*
285  * OPT_2 (RW)
286  *
287  * 0: PLUS_MUL_1
288  * 1: PLUS_MUL_2
289  * 5: PLUS_DIV_2
290  * 6: PLUS_DIV_3
291  * 7: PLUS_DIV_4
292  * 8: MINUS MUL 1
293  * 9: MINUS MUL 2
294  * 13: MINUS DIV 2
295  * 14: MINUS DIV 3
296  * 15: MINUS DIV 4
297  */
298 #define VSC_VALUE_B_DATA_OPT_OPT_2_MASK (0xF00U)
299 #define VSC_VALUE_B_DATA_OPT_OPT_2_SHIFT (8U)
300 #define VSC_VALUE_B_DATA_OPT_OPT_2_SET(x) (((uint32_t)(x) << VSC_VALUE_B_DATA_OPT_OPT_2_SHIFT) & VSC_VALUE_B_DATA_OPT_OPT_2_MASK)
301 #define VSC_VALUE_B_DATA_OPT_OPT_2_GET(x) (((uint32_t)(x) & VSC_VALUE_B_DATA_OPT_OPT_2_MASK) >> VSC_VALUE_B_DATA_OPT_OPT_2_SHIFT)
302 
303 /*
304  * OPT_1 (RW)
305  *
306  * 0: PLUS_MUL_1
307  * 1: PLUS_MUL_2
308  * 5: PLUS_DIV_2
309  * 6: PLUS_DIV_3
310  * 7: PLUS_DIV_4
311  * 8: MINUS MUL 1
312  * 9: MINUS MUL 2
313  * 13: MINUS DIV 2
314  * 14: MINUS DIV 3
315  * 15: MINUS DIV 4
316  */
317 #define VSC_VALUE_B_DATA_OPT_OPT_1_MASK (0xF0U)
318 #define VSC_VALUE_B_DATA_OPT_OPT_1_SHIFT (4U)
319 #define VSC_VALUE_B_DATA_OPT_OPT_1_SET(x) (((uint32_t)(x) << VSC_VALUE_B_DATA_OPT_OPT_1_SHIFT) & VSC_VALUE_B_DATA_OPT_OPT_1_MASK)
320 #define VSC_VALUE_B_DATA_OPT_OPT_1_GET(x) (((uint32_t)(x) & VSC_VALUE_B_DATA_OPT_OPT_1_MASK) >> VSC_VALUE_B_DATA_OPT_OPT_1_SHIFT)
321 
322 /*
323  * OPT_0 (RW)
324  *
325  * 0: PLUS_MUL_1
326  * 1: PLUS_MUL_2
327  * 5: PLUS_DIV_2
328  * 6: PLUS_DIV_3
329  * 7: PLUS_DIV_4
330  * 8: MINUS MUL 1
331  * 9: MINUS MUL 2
332  * 13: MINUS DIV 2
333  * 14: MINUS DIV 3
334  * 15: MINUS DIV 4
335  */
336 #define VSC_VALUE_B_DATA_OPT_OPT_0_MASK (0xFU)
337 #define VSC_VALUE_B_DATA_OPT_OPT_0_SHIFT (0U)
338 #define VSC_VALUE_B_DATA_OPT_OPT_0_SET(x) (((uint32_t)(x) << VSC_VALUE_B_DATA_OPT_OPT_0_SHIFT) & VSC_VALUE_B_DATA_OPT_OPT_0_MASK)
339 #define VSC_VALUE_B_DATA_OPT_OPT_0_GET(x) (((uint32_t)(x) & VSC_VALUE_B_DATA_OPT_OPT_0_MASK) >> VSC_VALUE_B_DATA_OPT_OPT_0_SHIFT)
340 
341 /* Bitfield definition for register: VALUE_C_DATA_OPT */
342 /*
343  * OPT_3 (RW)
344  *
345  * 0: PLUS_MUL_1
346  * 1: PLUS_MUL_2
347  * 5: PLUS_DIV_2
348  * 6: PLUS_DIV_3
349  * 7: PLUS_DIV_4
350  * 8: MINUS MUL 1
351  * 9: MINUS MUL 2
352  * 13: MINUS DIV 2
353  * 14: MINUS DIV 3
354  * 15: MINUS DIV 4
355  */
356 #define VSC_VALUE_C_DATA_OPT_OPT_3_MASK (0xF000U)
357 #define VSC_VALUE_C_DATA_OPT_OPT_3_SHIFT (12U)
358 #define VSC_VALUE_C_DATA_OPT_OPT_3_SET(x) (((uint32_t)(x) << VSC_VALUE_C_DATA_OPT_OPT_3_SHIFT) & VSC_VALUE_C_DATA_OPT_OPT_3_MASK)
359 #define VSC_VALUE_C_DATA_OPT_OPT_3_GET(x) (((uint32_t)(x) & VSC_VALUE_C_DATA_OPT_OPT_3_MASK) >> VSC_VALUE_C_DATA_OPT_OPT_3_SHIFT)
360 
361 /*
362  * OPT_2 (RW)
363  *
364  * 0: PLUS_MUL_1
365  * 1: PLUS_MUL_2
366  * 5: PLUS_DIV_2
367  * 6: PLUS_DIV_3
368  * 7: PLUS_DIV_4
369  * 8: MINUS MUL 1
370  * 9: MINUS MUL 2
371  * 13: MINUS DIV 2
372  * 14: MINUS DIV 3
373  * 15: MINUS DIV 4
374  */
375 #define VSC_VALUE_C_DATA_OPT_OPT_2_MASK (0xF00U)
376 #define VSC_VALUE_C_DATA_OPT_OPT_2_SHIFT (8U)
377 #define VSC_VALUE_C_DATA_OPT_OPT_2_SET(x) (((uint32_t)(x) << VSC_VALUE_C_DATA_OPT_OPT_2_SHIFT) & VSC_VALUE_C_DATA_OPT_OPT_2_MASK)
378 #define VSC_VALUE_C_DATA_OPT_OPT_2_GET(x) (((uint32_t)(x) & VSC_VALUE_C_DATA_OPT_OPT_2_MASK) >> VSC_VALUE_C_DATA_OPT_OPT_2_SHIFT)
379 
380 /*
381  * OPT_1 (RW)
382  *
383  * 0: PLUS_MUL_1
384  * 1: PLUS_MUL_2
385  * 5: PLUS_DIV_2
386  * 6: PLUS_DIV_3
387  * 7: PLUS_DIV_4
388  * 8: MINUS MUL 1
389  * 9: MINUS MUL 2
390  * 13: MINUS DIV 2
391  * 14: MINUS DIV 3
392  * 15: MINUS DIV 4
393  */
394 #define VSC_VALUE_C_DATA_OPT_OPT_1_MASK (0xF0U)
395 #define VSC_VALUE_C_DATA_OPT_OPT_1_SHIFT (4U)
396 #define VSC_VALUE_C_DATA_OPT_OPT_1_SET(x) (((uint32_t)(x) << VSC_VALUE_C_DATA_OPT_OPT_1_SHIFT) & VSC_VALUE_C_DATA_OPT_OPT_1_MASK)
397 #define VSC_VALUE_C_DATA_OPT_OPT_1_GET(x) (((uint32_t)(x) & VSC_VALUE_C_DATA_OPT_OPT_1_MASK) >> VSC_VALUE_C_DATA_OPT_OPT_1_SHIFT)
398 
399 /*
400  * OPT_0 (RW)
401  *
402  * 0: PLUS_MUL_1
403  * 1: PLUS_MUL_2
404  * 5: PLUS_DIV_2
405  * 6: PLUS_DIV_3
406  * 7: PLUS_DIV_4
407  * 8: MINUS MUL 1
408  * 9: MINUS MUL 2
409  * 13: MINUS DIV 2
410  * 14: MINUS DIV 3
411  * 15: MINUS DIV 4
412  */
413 #define VSC_VALUE_C_DATA_OPT_OPT_0_MASK (0xFU)
414 #define VSC_VALUE_C_DATA_OPT_OPT_0_SHIFT (0U)
415 #define VSC_VALUE_C_DATA_OPT_OPT_0_SET(x) (((uint32_t)(x) << VSC_VALUE_C_DATA_OPT_OPT_0_SHIFT) & VSC_VALUE_C_DATA_OPT_OPT_0_MASK)
416 #define VSC_VALUE_C_DATA_OPT_OPT_0_GET(x) (((uint32_t)(x) & VSC_VALUE_C_DATA_OPT_OPT_0_MASK) >> VSC_VALUE_C_DATA_OPT_OPT_0_SHIFT)
417 
418 /* Bitfield definition for register: VALUE_A_OFFSET */
419 /*
420  * VALUE_A_OFFSET (RW)
421  *
422  * value_a offset
423  */
424 #define VSC_VALUE_A_OFFSET_VALUE_A_OFFSET_MASK (0xFFFFFFFFUL)
425 #define VSC_VALUE_A_OFFSET_VALUE_A_OFFSET_SHIFT (0U)
426 #define VSC_VALUE_A_OFFSET_VALUE_A_OFFSET_SET(x) (((uint32_t)(x) << VSC_VALUE_A_OFFSET_VALUE_A_OFFSET_SHIFT) & VSC_VALUE_A_OFFSET_VALUE_A_OFFSET_MASK)
427 #define VSC_VALUE_A_OFFSET_VALUE_A_OFFSET_GET(x) (((uint32_t)(x) & VSC_VALUE_A_OFFSET_VALUE_A_OFFSET_MASK) >> VSC_VALUE_A_OFFSET_VALUE_A_OFFSET_SHIFT)
428 
429 /* Bitfield definition for register: VALUE_B_OFFSET */
430 /*
431  * VALUE_B_OFFSET (RW)
432  *
433  * value_b_offset
434  */
435 #define VSC_VALUE_B_OFFSET_VALUE_B_OFFSET_MASK (0xFFFFFFFFUL)
436 #define VSC_VALUE_B_OFFSET_VALUE_B_OFFSET_SHIFT (0U)
437 #define VSC_VALUE_B_OFFSET_VALUE_B_OFFSET_SET(x) (((uint32_t)(x) << VSC_VALUE_B_OFFSET_VALUE_B_OFFSET_SHIFT) & VSC_VALUE_B_OFFSET_VALUE_B_OFFSET_MASK)
438 #define VSC_VALUE_B_OFFSET_VALUE_B_OFFSET_GET(x) (((uint32_t)(x) & VSC_VALUE_B_OFFSET_VALUE_B_OFFSET_MASK) >> VSC_VALUE_B_OFFSET_VALUE_B_OFFSET_SHIFT)
439 
440 /* Bitfield definition for register: VALUE_C_OFFSET */
441 /*
442  * VALUE_C_OFFSET (RW)
443  *
444  * value_c offset
445  */
446 #define VSC_VALUE_C_OFFSET_VALUE_C_OFFSET_MASK (0xFFFFFFFFUL)
447 #define VSC_VALUE_C_OFFSET_VALUE_C_OFFSET_SHIFT (0U)
448 #define VSC_VALUE_C_OFFSET_VALUE_C_OFFSET_SET(x) (((uint32_t)(x) << VSC_VALUE_C_OFFSET_VALUE_C_OFFSET_SHIFT) & VSC_VALUE_C_OFFSET_VALUE_C_OFFSET_MASK)
449 #define VSC_VALUE_C_OFFSET_VALUE_C_OFFSET_GET(x) (((uint32_t)(x) & VSC_VALUE_C_OFFSET_VALUE_C_OFFSET_MASK) >> VSC_VALUE_C_OFFSET_VALUE_C_OFFSET_SHIFT)
450 
451 /* Bitfield definition for register: IRQ_STATUS */
452 /*
453  * IRQ_STATUS (RW)
454  *
455  * irq status bit:
456  * bit0: vsc convert done irq.
457  * bit1: in adc three-phase mode, if ABS(value_a+value_b+value_c) > adc_phase_tolerate, will trigger irq.
458  * bit2: value_c overflow during capture process.
459  * bit3: value_b_overflow during capture process.
460  * bit4: value_a_overflow during capture process.
461  * bit5: adc2 chan not capture enough adc value.
462  * bit6: adc1 chan not capture enough adc value.
463  * bit7: adc0 chan not capture enough adc value.
464  * bit8: position not got valid before pos_wait_cycle timeout.
465  * bit9: adc2 wait cycle timeout.
466  * bit10: adc1 wait cycle timeout.
467  * bit11: adc0 wait cycle timeout.
468  * bit12: trigger_in break vsc convert even if adc or position is ready.
469  */
470 #define VSC_IRQ_STATUS_IRQ_STATUS_MASK (0xFFFFFFFFUL)
471 #define VSC_IRQ_STATUS_IRQ_STATUS_SHIFT (0U)
472 #define VSC_IRQ_STATUS_IRQ_STATUS_SET(x) (((uint32_t)(x) << VSC_IRQ_STATUS_IRQ_STATUS_SHIFT) & VSC_IRQ_STATUS_IRQ_STATUS_MASK)
473 #define VSC_IRQ_STATUS_IRQ_STATUS_GET(x) (((uint32_t)(x) & VSC_IRQ_STATUS_IRQ_STATUS_MASK) >> VSC_IRQ_STATUS_IRQ_STATUS_SHIFT)
474 
475 /* Bitfield definition for register: VALUE_A_SW */
476 /*
477  * VALUE_A_SW (RW)
478  *
479  * value_a_sw
480  */
481 #define VSC_VALUE_A_SW_VALUE_A_SW_MASK (0xFFFFFFFFUL)
482 #define VSC_VALUE_A_SW_VALUE_A_SW_SHIFT (0U)
483 #define VSC_VALUE_A_SW_VALUE_A_SW_SET(x) (((uint32_t)(x) << VSC_VALUE_A_SW_VALUE_A_SW_SHIFT) & VSC_VALUE_A_SW_VALUE_A_SW_MASK)
484 #define VSC_VALUE_A_SW_VALUE_A_SW_GET(x) (((uint32_t)(x) & VSC_VALUE_A_SW_VALUE_A_SW_MASK) >> VSC_VALUE_A_SW_VALUE_A_SW_SHIFT)
485 
486 /* Bitfield definition for register: VALUE_B_SW */
487 /*
488  * VALUE_B_SW (RW)
489  *
490  * value_b_sw
491  */
492 #define VSC_VALUE_B_SW_VALUE_B_SW_MASK (0xFFFFFFFFUL)
493 #define VSC_VALUE_B_SW_VALUE_B_SW_SHIFT (0U)
494 #define VSC_VALUE_B_SW_VALUE_B_SW_SET(x) (((uint32_t)(x) << VSC_VALUE_B_SW_VALUE_B_SW_SHIFT) & VSC_VALUE_B_SW_VALUE_B_SW_MASK)
495 #define VSC_VALUE_B_SW_VALUE_B_SW_GET(x) (((uint32_t)(x) & VSC_VALUE_B_SW_VALUE_B_SW_MASK) >> VSC_VALUE_B_SW_VALUE_B_SW_SHIFT)
496 
497 /* Bitfield definition for register: VALUE_C_SW */
498 /*
499  * VALUE_C_SW (RW)
500  *
501  * value_c_sw
502  */
503 #define VSC_VALUE_C_SW_VALUE_C_SW_MASK (0xFFFFFFFFUL)
504 #define VSC_VALUE_C_SW_VALUE_C_SW_SHIFT (0U)
505 #define VSC_VALUE_C_SW_VALUE_C_SW_SET(x) (((uint32_t)(x) << VSC_VALUE_C_SW_VALUE_C_SW_SHIFT) & VSC_VALUE_C_SW_VALUE_C_SW_MASK)
506 #define VSC_VALUE_C_SW_VALUE_C_SW_GET(x) (((uint32_t)(x) & VSC_VALUE_C_SW_VALUE_C_SW_MASK) >> VSC_VALUE_C_SW_VALUE_C_SW_SHIFT)
507 
508 /* Bitfield definition for register: VALUE_SW_READY */
509 /*
510  * VALUE_SW_READY (W1C)
511  *
512  * software inject value_a/value_b/value_c ready
513  */
514 #define VSC_VALUE_SW_READY_VALUE_SW_READY_MASK (0x1U)
515 #define VSC_VALUE_SW_READY_VALUE_SW_READY_SHIFT (0U)
516 #define VSC_VALUE_SW_READY_VALUE_SW_READY_SET(x) (((uint32_t)(x) << VSC_VALUE_SW_READY_VALUE_SW_READY_SHIFT) & VSC_VALUE_SW_READY_VALUE_SW_READY_MASK)
517 #define VSC_VALUE_SW_READY_VALUE_SW_READY_GET(x) (((uint32_t)(x) & VSC_VALUE_SW_READY_VALUE_SW_READY_MASK) >> VSC_VALUE_SW_READY_VALUE_SW_READY_SHIFT)
518 
519 /* Bitfield definition for register: TRIGGER_SW */
520 /*
521  * TRIGGER_SW (W1C)
522  *
523  * software trigger to start waiting adc capture value, same as hardwire trigger_in
524  */
525 #define VSC_TRIGGER_SW_TRIGGER_SW_MASK (0x1U)
526 #define VSC_TRIGGER_SW_TRIGGER_SW_SHIFT (0U)
527 #define VSC_TRIGGER_SW_TRIGGER_SW_SET(x) (((uint32_t)(x) << VSC_TRIGGER_SW_TRIGGER_SW_SHIFT) & VSC_TRIGGER_SW_TRIGGER_SW_MASK)
528 #define VSC_TRIGGER_SW_TRIGGER_SW_GET(x) (((uint32_t)(x) & VSC_TRIGGER_SW_TRIGGER_SW_MASK) >> VSC_TRIGGER_SW_TRIGGER_SW_SHIFT)
529 
530 /* Bitfield definition for register: TIMELOCK */
531 /*
532  * POSITION_CAPTURE_MODE (RW)
533  *
534  * postion capture mode:
535  * 00: position use last valid data when adc value capture finish
536  * 01: position use frist valid data after adc value capture
537  * 10: position use last valid data before adc value capture
538  * other: reserved
539  */
540 #define VSC_TIMELOCK_POSITION_CAPTURE_MODE_MASK (0x3000U)
541 #define VSC_TIMELOCK_POSITION_CAPTURE_MODE_SHIFT (12U)
542 #define VSC_TIMELOCK_POSITION_CAPTURE_MODE_SET(x) (((uint32_t)(x) << VSC_TIMELOCK_POSITION_CAPTURE_MODE_SHIFT) & VSC_TIMELOCK_POSITION_CAPTURE_MODE_MASK)
543 #define VSC_TIMELOCK_POSITION_CAPTURE_MODE_GET(x) (((uint32_t)(x) & VSC_TIMELOCK_POSITION_CAPTURE_MODE_MASK) >> VSC_TIMELOCK_POSITION_CAPTURE_MODE_SHIFT)
544 
545 /*
546  * ADC_TIMESTAMP_SEL (RW)
547  *
548  * adc timestamp select：
549  * 0：reserved;
550  * 1: from value_a;
551  * 2: from value_b;
552  * 3: from value_c;
553  */
554 #define VSC_TIMELOCK_ADC_TIMESTAMP_SEL_MASK (0x30U)
555 #define VSC_TIMELOCK_ADC_TIMESTAMP_SEL_SHIFT (4U)
556 #define VSC_TIMELOCK_ADC_TIMESTAMP_SEL_SET(x) (((uint32_t)(x) << VSC_TIMELOCK_ADC_TIMESTAMP_SEL_SHIFT) & VSC_TIMELOCK_ADC_TIMESTAMP_SEL_MASK)
557 #define VSC_TIMELOCK_ADC_TIMESTAMP_SEL_GET(x) (((uint32_t)(x) & VSC_TIMELOCK_ADC_TIMESTAMP_SEL_MASK) >> VSC_TIMELOCK_ADC_TIMESTAMP_SEL_SHIFT)
558 
559 /*
560  * VALUE_COUNTER_SEL (RW)
561  *
562  * adc timestamp use which number index of adc_timestamp_sel used.
563  */
564 #define VSC_TIMELOCK_VALUE_COUNTER_SEL_MASK (0xFU)
565 #define VSC_TIMELOCK_VALUE_COUNTER_SEL_SHIFT (0U)
566 #define VSC_TIMELOCK_VALUE_COUNTER_SEL_SET(x) (((uint32_t)(x) << VSC_TIMELOCK_VALUE_COUNTER_SEL_SHIFT) & VSC_TIMELOCK_VALUE_COUNTER_SEL_MASK)
567 #define VSC_TIMELOCK_VALUE_COUNTER_SEL_GET(x) (((uint32_t)(x) & VSC_TIMELOCK_VALUE_COUNTER_SEL_MASK) >> VSC_TIMELOCK_VALUE_COUNTER_SEL_SHIFT)
568 
569 /* Bitfield definition for register: POSITION_SW */
570 /*
571  * POSITION_SW (RW)
572  *
573  * position_sw
574  */
575 #define VSC_POSITION_SW_POSITION_SW_MASK (0xFFFFFFFFUL)
576 #define VSC_POSITION_SW_POSITION_SW_SHIFT (0U)
577 #define VSC_POSITION_SW_POSITION_SW_SET(x) (((uint32_t)(x) << VSC_POSITION_SW_POSITION_SW_SHIFT) & VSC_POSITION_SW_POSITION_SW_MASK)
578 #define VSC_POSITION_SW_POSITION_SW_GET(x) (((uint32_t)(x) & VSC_POSITION_SW_POSITION_SW_MASK) >> VSC_POSITION_SW_POSITION_SW_SHIFT)
579 
580 /* Bitfield definition for register: ADC_WAIT_CYCLE */
581 /*
582  * ADC_WAIT_CYCLE (RW)
583  *
584  * adc wait cycle after trigger adc capture event
585  */
586 #define VSC_ADC_WAIT_CYCLE_ADC_WAIT_CYCLE_MASK (0xFFFFFFFFUL)
587 #define VSC_ADC_WAIT_CYCLE_ADC_WAIT_CYCLE_SHIFT (0U)
588 #define VSC_ADC_WAIT_CYCLE_ADC_WAIT_CYCLE_SET(x) (((uint32_t)(x) << VSC_ADC_WAIT_CYCLE_ADC_WAIT_CYCLE_SHIFT) & VSC_ADC_WAIT_CYCLE_ADC_WAIT_CYCLE_MASK)
589 #define VSC_ADC_WAIT_CYCLE_ADC_WAIT_CYCLE_GET(x) (((uint32_t)(x) & VSC_ADC_WAIT_CYCLE_ADC_WAIT_CYCLE_MASK) >> VSC_ADC_WAIT_CYCLE_ADC_WAIT_CYCLE_SHIFT)
590 
591 /* Bitfield definition for register: POS_WAIT_CYCLE */
592 /*
593  * POS_WAIT_CYCLE (RW)
594  *
595  * position wait cycle after trigger adc capture event
596  */
597 #define VSC_POS_WAIT_CYCLE_POS_WAIT_CYCLE_MASK (0xFFFFFFFFUL)
598 #define VSC_POS_WAIT_CYCLE_POS_WAIT_CYCLE_SHIFT (0U)
599 #define VSC_POS_WAIT_CYCLE_POS_WAIT_CYCLE_SET(x) (((uint32_t)(x) << VSC_POS_WAIT_CYCLE_POS_WAIT_CYCLE_SHIFT) & VSC_POS_WAIT_CYCLE_POS_WAIT_CYCLE_MASK)
600 #define VSC_POS_WAIT_CYCLE_POS_WAIT_CYCLE_GET(x) (((uint32_t)(x) & VSC_POS_WAIT_CYCLE_POS_WAIT_CYCLE_MASK) >> VSC_POS_WAIT_CYCLE_POS_WAIT_CYCLE_SHIFT)
601 
602 /* Bitfield definition for register: IRQ_ENABLE */
603 /*
604  * IRQ_ENABLE (RW)
605  *
606  * irq enable bit:
607  * bit0: vsc convert done irq.
608  * bit1: in adc three-phase mode, if ABS(value_a+value_b+value_c) > adc_phase_tolerate, will trigger irq.
609  * bit2: value_c overflow during capture process.
610  * bit3: value_b_overflow during capture process.
611  * bit4: value_a_overflow during capture process.
612  * bit5: adc2 chan not capture enough adc value.
613  * bit6: adc1 chan not capture enough adc value.
614  * bit7: adc0 chan not capture enough adc value.
615  * bit8: position not got valid before pos_wait_cycle timeout.
616  * bit9: adc2 wait cycle timeout.
617  * bit10: adc1 wait cycle timeout.
618  * bit11: adc0 wait cycle timeout.
619  * bit12: trigger_in break vsc convert even if adc or position is ready.
620  */
621 #define VSC_IRQ_ENABLE_IRQ_ENABLE_MASK (0xFFFFFFFFUL)
622 #define VSC_IRQ_ENABLE_IRQ_ENABLE_SHIFT (0U)
623 #define VSC_IRQ_ENABLE_IRQ_ENABLE_SET(x) (((uint32_t)(x) << VSC_IRQ_ENABLE_IRQ_ENABLE_SHIFT) & VSC_IRQ_ENABLE_IRQ_ENABLE_MASK)
624 #define VSC_IRQ_ENABLE_IRQ_ENABLE_GET(x) (((uint32_t)(x) & VSC_IRQ_ENABLE_IRQ_ENABLE_MASK) >> VSC_IRQ_ENABLE_IRQ_ENABLE_SHIFT)
625 
626 /* Bitfield definition for register: ADC_PHASE_TOLERATE */
627 /*
628  * ADC_PHASE_TOLERATE (RW)
629  *
630  * in adc three-phase mode, if ABS(value_a+value_b+value_c) > adc_phase_tolerate, will trigger irq.
631  */
632 #define VSC_ADC_PHASE_TOLERATE_ADC_PHASE_TOLERATE_MASK (0xFFFFFFFFUL)
633 #define VSC_ADC_PHASE_TOLERATE_ADC_PHASE_TOLERATE_SHIFT (0U)
634 #define VSC_ADC_PHASE_TOLERATE_ADC_PHASE_TOLERATE_SET(x) (((uint32_t)(x) << VSC_ADC_PHASE_TOLERATE_ADC_PHASE_TOLERATE_SHIFT) & VSC_ADC_PHASE_TOLERATE_ADC_PHASE_TOLERATE_MASK)
635 #define VSC_ADC_PHASE_TOLERATE_ADC_PHASE_TOLERATE_GET(x) (((uint32_t)(x) & VSC_ADC_PHASE_TOLERATE_ADC_PHASE_TOLERATE_MASK) >> VSC_ADC_PHASE_TOLERATE_ADC_PHASE_TOLERATE_SHIFT)
636 
637 /* Bitfield definition for register: POS_POLE */
638 /*
639  * POS_POLE (RW)
640  *
641  * pole number
642  */
643 #define VSC_POS_POLE_POS_POLE_MASK (0xFFFFU)
644 #define VSC_POS_POLE_POS_POLE_SHIFT (0U)
645 #define VSC_POS_POLE_POS_POLE_SET(x) (((uint32_t)(x) << VSC_POS_POLE_POS_POLE_SHIFT) & VSC_POS_POLE_POS_POLE_MASK)
646 #define VSC_POS_POLE_POS_POLE_GET(x) (((uint32_t)(x) & VSC_POS_POLE_POS_POLE_MASK) >> VSC_POS_POLE_POS_POLE_SHIFT)
647 
648 /* Bitfield definition for register: ID_POSEDGE */
649 /*
650  * ID_POSEDGE (RO)
651  *
652  * posedge order Id value
653  */
654 #define VSC_ID_POSEDGE_ID_POSEDGE_MASK (0xFFFFFFFFUL)
655 #define VSC_ID_POSEDGE_ID_POSEDGE_SHIFT (0U)
656 #define VSC_ID_POSEDGE_ID_POSEDGE_GET(x) (((uint32_t)(x) & VSC_ID_POSEDGE_ID_POSEDGE_MASK) >> VSC_ID_POSEDGE_ID_POSEDGE_SHIFT)
657 
658 /* Bitfield definition for register: IQ_POSEDGE */
659 /*
660  * IQ_POSEDGE (RO)
661  *
662  * posedge order Iq value
663  */
664 #define VSC_IQ_POSEDGE_IQ_POSEDGE_MASK (0xFFFFFFFFUL)
665 #define VSC_IQ_POSEDGE_IQ_POSEDGE_SHIFT (0U)
666 #define VSC_IQ_POSEDGE_IQ_POSEDGE_GET(x) (((uint32_t)(x) & VSC_IQ_POSEDGE_IQ_POSEDGE_MASK) >> VSC_IQ_POSEDGE_IQ_POSEDGE_SHIFT)
667 
668 /* Bitfield definition for register: ID_NEGEDGE */
669 /*
670  * ID_NEGEDGE (RO)
671  *
672  * negedge order Id value
673  */
674 #define VSC_ID_NEGEDGE_ID_NEGEDGE_MASK (0xFFFFFFFFUL)
675 #define VSC_ID_NEGEDGE_ID_NEGEDGE_SHIFT (0U)
676 #define VSC_ID_NEGEDGE_ID_NEGEDGE_GET(x) (((uint32_t)(x) & VSC_ID_NEGEDGE_ID_NEGEDGE_MASK) >> VSC_ID_NEGEDGE_ID_NEGEDGE_SHIFT)
677 
678 /* Bitfield definition for register: IQ_NEGEDGE */
679 /*
680  * IQ_NEGEDGE (RO)
681  *
682  * negedge order Iq value
683  */
684 #define VSC_IQ_NEGEDGE_IQ_NEGEDGE_MASK (0xFFFFFFFFUL)
685 #define VSC_IQ_NEGEDGE_IQ_NEGEDGE_SHIFT (0U)
686 #define VSC_IQ_NEGEDGE_IQ_NEGEDGE_GET(x) (((uint32_t)(x) & VSC_IQ_NEGEDGE_IQ_NEGEDGE_MASK) >> VSC_IQ_NEGEDGE_IQ_NEGEDGE_SHIFT)
687 
688 /* Bitfield definition for register: ALPHA_POSEDGE */
689 /*
690  * ALPHA_POSEDGE (RO)
691  *
692  * posedge order alpha value
693  */
694 #define VSC_ALPHA_POSEDGE_ALPHA_POSEDGE_MASK (0xFFFFFFFFUL)
695 #define VSC_ALPHA_POSEDGE_ALPHA_POSEDGE_SHIFT (0U)
696 #define VSC_ALPHA_POSEDGE_ALPHA_POSEDGE_GET(x) (((uint32_t)(x) & VSC_ALPHA_POSEDGE_ALPHA_POSEDGE_MASK) >> VSC_ALPHA_POSEDGE_ALPHA_POSEDGE_SHIFT)
697 
698 /* Bitfield definition for register: BETA_POSEDGE */
699 /*
700  * BETA_POSEDGE (RO)
701  *
702  * posedge order beta value
703  */
704 #define VSC_BETA_POSEDGE_BETA_POSEDGE_MASK (0xFFFFFFFFUL)
705 #define VSC_BETA_POSEDGE_BETA_POSEDGE_SHIFT (0U)
706 #define VSC_BETA_POSEDGE_BETA_POSEDGE_GET(x) (((uint32_t)(x) & VSC_BETA_POSEDGE_BETA_POSEDGE_MASK) >> VSC_BETA_POSEDGE_BETA_POSEDGE_SHIFT)
707 
708 /* Bitfield definition for register: ALPHA_NEGEDGE */
709 /*
710  * ALPHA_NEGEDGE (RO)
711  *
712  * negedge order alpha value
713  */
714 #define VSC_ALPHA_NEGEDGE_ALPHA_NEGEDGE_MASK (0xFFFFFFFFUL)
715 #define VSC_ALPHA_NEGEDGE_ALPHA_NEGEDGE_SHIFT (0U)
716 #define VSC_ALPHA_NEGEDGE_ALPHA_NEGEDGE_GET(x) (((uint32_t)(x) & VSC_ALPHA_NEGEDGE_ALPHA_NEGEDGE_MASK) >> VSC_ALPHA_NEGEDGE_ALPHA_NEGEDGE_SHIFT)
717 
718 /* Bitfield definition for register: BETA_NEGEDGE */
719 /*
720  * BETA_NEGEDGE (RO)
721  *
722  * negedge order beta value
723  */
724 #define VSC_BETA_NEGEDGE_BETA_NEGEDGE_MASK (0xFFFFFFFFUL)
725 #define VSC_BETA_NEGEDGE_BETA_NEGEDGE_SHIFT (0U)
726 #define VSC_BETA_NEGEDGE_BETA_NEGEDGE_GET(x) (((uint32_t)(x) & VSC_BETA_NEGEDGE_BETA_NEGEDGE_MASK) >> VSC_BETA_NEGEDGE_BETA_NEGEDGE_SHIFT)
727 
728 /* Bitfield definition for register: TIMESTAMP_LOCKED */
729 /*
730  * TIMESTAMP_LOCKED (RO)
731  *
732  * timestamp_locked
733  */
734 #define VSC_TIMESTAMP_LOCKED_TIMESTAMP_LOCKED_MASK (0xFFFFFFFFUL)
735 #define VSC_TIMESTAMP_LOCKED_TIMESTAMP_LOCKED_SHIFT (0U)
736 #define VSC_TIMESTAMP_LOCKED_TIMESTAMP_LOCKED_GET(x) (((uint32_t)(x) & VSC_TIMESTAMP_LOCKED_TIMESTAMP_LOCKED_MASK) >> VSC_TIMESTAMP_LOCKED_TIMESTAMP_LOCKED_SHIFT)
737 
738 /* Bitfield definition for register: DEBUG_STATUS0 */
739 /*
740  * VALUE_A_COUNTER (RO)
741  *
742  * value_a_counter
743  */
744 #define VSC_DEBUG_STATUS0_VALUE_A_COUNTER_MASK (0xF00U)
745 #define VSC_DEBUG_STATUS0_VALUE_A_COUNTER_SHIFT (8U)
746 #define VSC_DEBUG_STATUS0_VALUE_A_COUNTER_GET(x) (((uint32_t)(x) & VSC_DEBUG_STATUS0_VALUE_A_COUNTER_MASK) >> VSC_DEBUG_STATUS0_VALUE_A_COUNTER_SHIFT)
747 
748 /*
749  * VALUE_B_COUNTER (RO)
750  *
751  * value_b_counter
752  */
753 #define VSC_DEBUG_STATUS0_VALUE_B_COUNTER_MASK (0xF0U)
754 #define VSC_DEBUG_STATUS0_VALUE_B_COUNTER_SHIFT (4U)
755 #define VSC_DEBUG_STATUS0_VALUE_B_COUNTER_GET(x) (((uint32_t)(x) & VSC_DEBUG_STATUS0_VALUE_B_COUNTER_MASK) >> VSC_DEBUG_STATUS0_VALUE_B_COUNTER_SHIFT)
756 
757 /*
758  * VALUE_C_COUNTER (RO)
759  *
760  * value_c_counter
761  */
762 #define VSC_DEBUG_STATUS0_VALUE_C_COUNTER_MASK (0xFU)
763 #define VSC_DEBUG_STATUS0_VALUE_C_COUNTER_SHIFT (0U)
764 #define VSC_DEBUG_STATUS0_VALUE_C_COUNTER_GET(x) (((uint32_t)(x) & VSC_DEBUG_STATUS0_VALUE_C_COUNTER_MASK) >> VSC_DEBUG_STATUS0_VALUE_C_COUNTER_SHIFT)
765 
766 
767 
768 
769 #endif /* HPM_VSC_H */
VSC_Type
Definition: hpm_vsc_regs.h:12