HPM SDK
HPMicro Software Development Kit
hpm_ddrphy_regs.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_DDRPHY_H
10 #define HPM_DDRPHY_H
11 
12 typedef struct {
13  __R uint32_t RIDR; /* 0x0: Revision Identification Register */
14  __RW uint32_t PIR; /* 0x4: PHY Initialization Register (PIR) */
15  __RW uint32_t PGCR0; /* 0x8: PHY General Configuration Registers 0-1 (PGCR0- 1) */
16  __RW uint32_t PGCR1; /* 0xC: PHY General Configuration Registers 0-1 (PGCR0- 1) */
17  __R uint32_t PGSR0; /* 0x10: “PHY General Status Registers 0-1 (PGSR0-1)” on page 89 */
18  __R uint32_t PGSR1; /* 0x14: “PHY General Status Registers 0-1 (PGSR0-1)” on page 89 */
19  __RW uint32_t PLLCR; /* 0x18: “PLL Control Register (PLLCR)” on page 91 */
20  __RW uint32_t PTR0; /* 0x1C: PHY Timing Registers 0-4 (PTR0-4) */
21  __RW uint32_t PTR1; /* 0x20: PHY Timing Registers 0-4 (PTR0-4) */
22  __RW uint32_t PTR2; /* 0x24: PHY Timing Registers 0-4 (PTR0-4) */
23  __RW uint32_t PTR3; /* 0x28: PHY Timing Registers 0-4 (PTR0-4) */
24  __RW uint32_t PTR4; /* 0x2C: PHY Timing Registers 0-4 (PTR0-4) */
25  __RW uint32_t ACMDLR; /* 0x30: “AC Master Delay Line Register (ACMDLR)” on page 96 */
26  __RW uint32_t ACBDLR; /* 0x34: “AC Bit Delay Line Register (ACBDLR)” on page 96 */
27  __RW uint32_t ACIOCR; /* 0x38: “AC I/O Configuration Register (ACIOCR)” on page 97 */
28  __RW uint32_t DXCCR; /* 0x3C: “DATX8 Common Configuration Register (DXCCR)” on page 99 */
29  __RW uint32_t DSGCR; /* 0x40: “DDR System General Configuration Register (DSGCR)” on page 101 */
30  __RW uint32_t DCR; /* 0x44: “DRAM Configuration Register (DCR)” on page 103 */
31  __RW uint32_t DTPR0; /* 0x48: DRAM Timing Parameters Register 0-2 (DTPR0-2) */
32  __RW uint32_t DTPR1; /* 0x4C: DRAM Timing Parameters Register 0-2 (DTPR0-2) */
33  __RW uint32_t DTPR2; /* 0x50: DRAM Timing Parameters Register 0-2 (DTPR0-2) */
34  union {
35  __RW uint32_t MR0; /* 0x54: “Mode Register 0 (MR0)” on page 108 */
36  __RW uint32_t MR; /* 0x54: */
37  };
38  union {
39  __RW uint32_t MR1; /* 0x58: “Mode Register 1 (MR1)” on page 111 */
40  __RW uint32_t EMR; /* 0x58: */
41  };
42  union {
43  __RW uint32_t MR2; /* 0x5C: “Mode Register 2/Extended Mode Register 2 (MR2/EMR2)” on page 114 */
44  __RW uint32_t EMR2; /* 0x5C: */
45  };
46  union {
47  __RW uint32_t MR3; /* 0x60: “Mode Register 3 (MR3)” on page 116 */
48  __RW uint32_t EMR3; /* 0x60: */
49  };
50  __RW uint32_t ODTCR; /* 0x64: “ODT Configuration Register (ODTCR)” on page 117 */
51  __RW uint32_t DTCR; /* 0x68: “Data Training Configuration Register (DTCR)” on page 118 */
52  __RW uint32_t DTAR0; /* 0x6C: Data Training Address Register 0-3 (DTAR0-3) */
53  __RW uint32_t DTAR1; /* 0x70: Data Training Address Register 0-3 (DTAR0-3) */
54  __RW uint32_t DTAR2; /* 0x74: Data Training Address Register 0-3 (DTAR0-3) */
55  __RW uint32_t DTAR3; /* 0x78: Data Training Address Register 0-3 (DTAR0-3) */
56  __RW uint32_t DTDR0; /* 0x7C: Data Training Eye Data Register 0-1 (DTEDR0-1) */
57  __RW uint32_t DTDR1; /* 0x80: Data Training Eye Data Register 0-1 (DTEDR0-1) */
58  __R uint32_t DTEDR0; /* 0x84: Data Training Eye Data Register 0-1 (DTEDR0-1) */
59  __R uint32_t DTEDR1; /* 0x88: Data Training Eye Data Register 0-1 (DTEDR0-1) */
60  __RW uint32_t PGCR2; /* 0x8C: “PHY General Configuration Register 2 (PGCR2)” on page 87 */
61  __R uint8_t RESERVED0[32]; /* 0x90 - 0xAF: Reserved */
62  __R uint32_t RDIMMGCR0; /* 0xB0: RDIMM General Configuration Register 0-1 (RDIMMGCR0-1) */
63  __R uint32_t RDIMMGCR1; /* 0xB4: RDIMM General Configuration Register 0-1 (RDIMMGCR0-1) */
64  __R uint32_t RDIMMCR0; /* 0xB8: RDIMM Control Register 0-1 (RDIMMCR0-1) */
65  __R uint32_t RDIMMCR1; /* 0xBC: RDIMM Control Register 0-1 (RDIMMCR0-1) */
66  __RW uint32_t DCUAR; /* 0xC0: “DCU Address Register (DCUAR)” on page 129 */
67  __RW uint32_t DCUDR; /* 0xC4: “DCU Data Register (DCUDR)” on page 130 */
68  __RW uint32_t DCURR; /* 0xC8: “DCU Run Register (DCURR)” on page 130 */
69  __RW uint32_t DCULR; /* 0xCC: “DCU Loop Register (DCULR)” on page 131 */
70  __RW uint32_t DCUGCR; /* 0xD0: “DCU General Configuration Register (DCUGCR)” on page 132 */
71  __RW uint32_t DCUTPR; /* 0xD4: “DCU Timing Parameter Register (DCUTPR)” on page 132 */
72  __R uint32_t DCUSR0; /* 0xD8: DCU Status Register 0-1 (DCUSR0-1) */
73  __R uint32_t DCUSR1; /* 0xDC: DCU Status Register 0-1 (DCUSR0-1) */
74  __R uint8_t RESERVED1[32]; /* 0xE0 - 0xFF: Reserved */
75  __RW uint32_t BISTRR; /* 0x100: “BIST Run Register (BISTRR)” on page 133 */
76  __RW uint32_t BISTWCR; /* 0x104: “BIST Word Count Register (BISTWCR)” on page 136 */
77  __RW uint32_t BISTMSKR0; /* 0x108: BIST Mask Register 0-2 (BISTMSKR0-2) */
78  __RW uint32_t BISTMSKR1; /* 0x10C: BIST Mask Register 0-2 (BISTMSKR0-2) */
79  __RW uint32_t BISTMSKR2; /* 0x110: BIST Mask Register 0-2 (BISTMSKR0-2) */
80  __RW uint32_t BISTLSR; /* 0x114: “BIST LFSR Seed Register (BISTLSR)” on page 137 */
81  __RW uint32_t BISTAR0; /* 0x118: BIST Address Register 0-2 (BISTAR0-2) */
82  __RW uint32_t BISTAR1; /* 0x11C: BIST Address Register 0-2 (BISTAR0-2) */
83  __RW uint32_t BISTAR2; /* 0x120: BIST Address Register 0-2 (BISTAR0-2) */
84  __RW uint32_t BISTUDPR; /* 0x124: “BIST User Data Pattern Register (BISTUDPR)” on page 138 */
85  __R uint32_t BISTGSR; /* 0x128: “BIST General Status Register (BISTGSR)” on page 139 */
86  __R uint32_t BISTWER; /* 0x12C: “BIST Word Error Register (BISTWER)” on page 139 */
87  __R uint32_t BISTBER0; /* 0x130: BIST Bit Error Register 0-3 (BISTBER0-3) */
88  __R uint32_t BISTBER1; /* 0x134: BIST Bit Error Register 0-3 (BISTBER0-3) */
89  __R uint32_t BISTBER2; /* 0x138: BIST Bit Error Register 0-3 (BISTBER0-3) */
90  __R uint32_t BISTBER3; /* 0x13C: BIST Bit Error Register 0-3 (BISTBER0-3) */
91  __R uint32_t BISTWCSR; /* 0x140: “BIST Word Count Status Register (BISTWCSR)” on page 141 */
92  __R uint32_t BISTFWR0; /* 0x144: BIST Fail Word Register 0-2 (BISTFWR0-2) */
93  __R uint32_t BISTFWR1; /* 0x148: BIST Fail Word Register 0-2 (BISTFWR0-2) */
94  __R uint32_t BISTFWR2; /* 0x14C: BIST Fail Word Register 0-2 (BISTFWR0-2) */
95  __R uint8_t RESERVED2[36]; /* 0x150 - 0x173: Reserved */
96  __RW uint32_t AACR; /* 0x174: “Anti-Aging Control Register (AACR)” on page 143 */
97  __RW uint32_t GPR0; /* 0x178: General Purpose Register 0-1 (GPR0-1) */
98  __RW uint32_t GPR1; /* 0x17C: General Purpose Register 0-1 (GPR0-1) */
99  struct {
100  __RW uint32_t CR0; /* 0x180: Impedance Control Register 0-1 (ZQnCR0-1) */
101  __RW uint32_t CR1; /* 0x184: Impedance Control Register 0-1 (ZQnCR0-1) */
102  __R uint32_t SR0; /* 0x188: Impedance Status Register 0-1 (ZQnSR0-1) */
103  __R uint32_t SR1; /* 0x18C: Impedance Status Register 0-1 (ZQnSR0-1) */
104  } ZQ[4];
105  struct {
106  __RW uint32_t GCR; /* 0x1C0: “DATX8 General Configuration Register (DXnGCR)” on page 148 */
107  __R uint32_t GSR0; /* 0x1C4: DATX8 General Status Registers 0-2 (DXnGSR0-2) */
108  __R uint32_t GSR1; /* 0x1C8: DATX8 General Status Registers 0-2 (DXnGSR0-2) */
109  __RW uint32_t BDLR0; /* 0x1CC: DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) */
110  __RW uint32_t BDLR1; /* 0x1D0: DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) */
111  __RW uint32_t BDLR2; /* 0x1D4: DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) */
112  __RW uint32_t BDLR3; /* 0x1D8: DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) */
113  __RW uint32_t BDLR4; /* 0x1DC: DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) */
114  __RW uint32_t LCDLR0; /* 0x1E0: DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) */
115  __RW uint32_t LCDLR1; /* 0x1E4: DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) */
116  __RW uint32_t LCDLR2; /* 0x1E8: DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) */
117  __RW uint32_t MDLR; /* 0x1EC: “DATX8 Master Delay Line Register (DXnMDLR)” on page 157 */
118  __RW uint32_t GTR; /* 0x1F0: “DATX8 General Timing Register (DXnGTR)” on page 159 */
119  __RW uint32_t GSR2; /* 0x1F4: “DATX8 General Status Register 2 (DXnGSR2)” on page 152 */
120  __R uint8_t RESERVED0[8]; /* 0x1F8 - 0x1FF: Reserved */
121  } DX[9];
122 } DDRPHY_Type;
123 
124 
125 /* Bitfield definition for register: RIDR */
126 /*
127  * UDRID (R)
128  *
129  * User-Defined Revision ID: General purpose revision identification set by the user.
130  */
131 #define DDRPHY_RIDR_UDRID_MASK (0xFF000000UL)
132 #define DDRPHY_RIDR_UDRID_SHIFT (24U)
133 #define DDRPHY_RIDR_UDRID_GET(x) (((uint32_t)(x) & DDRPHY_RIDR_UDRID_MASK) >> DDRPHY_RIDR_UDRID_SHIFT)
134 
135 /*
136  * PHYMJR (R)
137  *
138  * PHY Major Revision: Indicates major revision of the PHY such addition of the features that make the new version not compatible with previous versions.
139  */
140 #define DDRPHY_RIDR_PHYMJR_MASK (0xF00000UL)
141 #define DDRPHY_RIDR_PHYMJR_SHIFT (20U)
142 #define DDRPHY_RIDR_PHYMJR_GET(x) (((uint32_t)(x) & DDRPHY_RIDR_PHYMJR_MASK) >> DDRPHY_RIDR_PHYMJR_SHIFT)
143 
144 /*
145  * PHYMDR (R)
146  *
147  * PHY Moderate Revision: Indicates moderate revision of the PHY such as addition of new features. Normally the new version is still compatible with previous versions.
148  */
149 #define DDRPHY_RIDR_PHYMDR_MASK (0xF0000UL)
150 #define DDRPHY_RIDR_PHYMDR_SHIFT (16U)
151 #define DDRPHY_RIDR_PHYMDR_GET(x) (((uint32_t)(x) & DDRPHY_RIDR_PHYMDR_MASK) >> DDRPHY_RIDR_PHYMDR_SHIFT)
152 
153 /*
154  * PHYMNR (R)
155  *
156  * PHY Minor Revision: Indicates minor update of the PHY such as bug fixes. Normally no new features are included.
157  */
158 #define DDRPHY_RIDR_PHYMNR_MASK (0xF000U)
159 #define DDRPHY_RIDR_PHYMNR_SHIFT (12U)
160 #define DDRPHY_RIDR_PHYMNR_GET(x) (((uint32_t)(x) & DDRPHY_RIDR_PHYMNR_MASK) >> DDRPHY_RIDR_PHYMNR_SHIFT)
161 
162 /*
163  * PUBMJR (R)
164  *
165  * PUB Major Revision: Indicates major revision of the PUB such addition of the features that make the new version not compatible with previous versions.
166  */
167 #define DDRPHY_RIDR_PUBMJR_MASK (0xF00U)
168 #define DDRPHY_RIDR_PUBMJR_SHIFT (8U)
169 #define DDRPHY_RIDR_PUBMJR_GET(x) (((uint32_t)(x) & DDRPHY_RIDR_PUBMJR_MASK) >> DDRPHY_RIDR_PUBMJR_SHIFT)
170 
171 /*
172  * PUBMDR (R)
173  *
174  * PUB Moderate Revision: Indicates moderate revision of the PUB such as addition of new features. Normally the new version is still compatible with previous versions.
175  */
176 #define DDRPHY_RIDR_PUBMDR_MASK (0xF0U)
177 #define DDRPHY_RIDR_PUBMDR_SHIFT (4U)
178 #define DDRPHY_RIDR_PUBMDR_GET(x) (((uint32_t)(x) & DDRPHY_RIDR_PUBMDR_MASK) >> DDRPHY_RIDR_PUBMDR_SHIFT)
179 
180 /*
181  * PUBMNR (R)
182  *
183  * PUB Minor Revision: Indicates minor update of the PUB such as bug fixes. Normally no new features are included.
184  */
185 #define DDRPHY_RIDR_PUBMNR_MASK (0xFU)
186 #define DDRPHY_RIDR_PUBMNR_SHIFT (0U)
187 #define DDRPHY_RIDR_PUBMNR_GET(x) (((uint32_t)(x) & DDRPHY_RIDR_PUBMNR_MASK) >> DDRPHY_RIDR_PUBMNR_SHIFT)
188 
189 /* Bitfield definition for register: PIR */
190 /*
191  * INITBYP (R/W)
192  *
193  * Initialization Bypass: Bypasses or stops, if set, all initialization routines currently running, including PHY initialization, DRAM initialization, and PHY training.
194  * Initialization may be triggered manually using INIT and the other relevant bits of the PIR register. This bit is self-clearing.
195  */
196 #define DDRPHY_PIR_INITBYP_MASK (0x80000000UL)
197 #define DDRPHY_PIR_INITBYP_SHIFT (31U)
198 #define DDRPHY_PIR_INITBYP_SET(x) (((uint32_t)(x) << DDRPHY_PIR_INITBYP_SHIFT) & DDRPHY_PIR_INITBYP_MASK)
199 #define DDRPHY_PIR_INITBYP_GET(x) (((uint32_t)(x) & DDRPHY_PIR_INITBYP_MASK) >> DDRPHY_PIR_INITBYP_SHIFT)
200 
201 /*
202  * ZCALBYP (R/W)
203  *
204  * Impedance Calibration Bypass: Bypasses or stops, if set, impedance calibration of all ZQ control blocks that automatically triggers after reset. Impedance calibration may be triggered manually using INIT and ZCAL bits of the PIR register. This bit is self-clearing.
205  */
206 #define DDRPHY_PIR_ZCALBYP_MASK (0x40000000UL)
207 #define DDRPHY_PIR_ZCALBYP_SHIFT (30U)
208 #define DDRPHY_PIR_ZCALBYP_SET(x) (((uint32_t)(x) << DDRPHY_PIR_ZCALBYP_SHIFT) & DDRPHY_PIR_ZCALBYP_MASK)
209 #define DDRPHY_PIR_ZCALBYP_GET(x) (((uint32_t)(x) & DDRPHY_PIR_ZCALBYP_MASK) >> DDRPHY_PIR_ZCALBYP_SHIFT)
210 
211 /*
212  * DCALBYP (R/W)
213  *
214  * Digital Delay Line (DDL) Calibration Bypass: Bypasses or stops, if set, DDL calibration that automatically triggers after reset. DDL calibration may be triggered manually using INIT and DCAL bits of the PIR register. This bit is self- clearing.
215  */
216 #define DDRPHY_PIR_DCALBYP_MASK (0x20000000UL)
217 #define DDRPHY_PIR_DCALBYP_SHIFT (29U)
218 #define DDRPHY_PIR_DCALBYP_SET(x) (((uint32_t)(x) << DDRPHY_PIR_DCALBYP_SHIFT) & DDRPHY_PIR_DCALBYP_MASK)
219 #define DDRPHY_PIR_DCALBYP_GET(x) (((uint32_t)(x) & DDRPHY_PIR_DCALBYP_MASK) >> DDRPHY_PIR_DCALBYP_SHIFT)
220 
221 /*
222  * LOCKBYP (R/W)
223  *
224  * PLL Lock Bypass: Bypasses or stops, if set, the waiting of PLLs to lock. PLL lock wait is automatically triggered after reset. PLL lock wait may be triggered manually using INIT and PLLINIT bits of the PIR register. This bit is self-clearing.
225  */
226 #define DDRPHY_PIR_LOCKBYP_MASK (0x10000000UL)
227 #define DDRPHY_PIR_LOCKBYP_SHIFT (28U)
228 #define DDRPHY_PIR_LOCKBYP_SET(x) (((uint32_t)(x) << DDRPHY_PIR_LOCKBYP_SHIFT) & DDRPHY_PIR_LOCKBYP_MASK)
229 #define DDRPHY_PIR_LOCKBYP_GET(x) (((uint32_t)(x) & DDRPHY_PIR_LOCKBYP_MASK) >> DDRPHY_PIR_LOCKBYP_SHIFT)
230 
231 /*
232  * CLRSR (R/W)
233  *
234  * Clear Status Registers: Writing 1 to this bit clears (reset to 0) select status bits in register PGSR0.
235  * This bit is primarily for debug purposes and is typically not needed during normal functional operation. It can be used when PGSR.IDONE=1, to manually clear a selection of the PGSR status bits, although starting a new initialization process (PIR[0].INIT = 1’b1) automatically clears the PGSR status bits associated with the initialization steps enabled.
236  * The following list describes which bits within the PGSR0 register are cleared when CLRSR is set to 1’b1 and which bits are not cleared:
237  * The following bits are not cleared by PIR[27] (CLRSR):
238  * PGSR0[31] (APLOCK)
239  * PGSR0[29:28] (PLDONE_CHN)
240  * PGSR0[23] (WLAERR)
241  * PGSR0[21] (WLERR)
242  * PGSR0[4] (DIDONE)
243  * PGSR0[2] (DCDONE)
244  * PGSR0[1] (PLDONE)
245  * PGSR0[0] (IDONE)
246  * The following bits are always zero:
247  * PGSR0[30] (reserved)
248  * PGSR0[19:12] (reserved)
249  * The following bits are cleared unconditionally by PIR[27] (CLRSR):
250  * PGSR0[27] (WEERR)
251  * PGSR0[26] (REERR)
252  * PGSR0[25] (WDERR)
253  * PGSR0[24] (RDERR)
254  * - PGSR0[22] (QSGERR)
255  * - PGSR0[20] (ZCERR)
256  * - PGSR0[11] (WEDONE)
257  * - PGSR0[10] (REDONE)
258  * - PGSR0[9] (WDDONE)
259  * - PGSR0[8] (RDDONE)
260  * - PGSR0[7] (WLADONE)
261  * - PGSR0[6] (QSGDONE)
262  * - PGSR0[5] (WLDONE)
263  * - PGSR0[3] (ZCDONE)
264  */
265 #define DDRPHY_PIR_CLRSR_MASK (0x8000000UL)
266 #define DDRPHY_PIR_CLRSR_SHIFT (27U)
267 #define DDRPHY_PIR_CLRSR_SET(x) (((uint32_t)(x) << DDRPHY_PIR_CLRSR_SHIFT) & DDRPHY_PIR_CLRSR_MASK)
268 #define DDRPHY_PIR_CLRSR_GET(x) (((uint32_t)(x) & DDRPHY_PIR_CLRSR_MASK) >> DDRPHY_PIR_CLRSR_SHIFT)
269 
270 /*
271  * RDIMMINIT (R/W)
272  *
273  * RDIMM Initialization: Executes the RDIMM buffer chip initialization before executing DRAM initialization. The RDIMM buffer chip initialization is run after the DRAM is reset and CKE have been driven high by the DRAM initialization sequence.
274  */
275 #define DDRPHY_PIR_RDIMMINIT_MASK (0x80000UL)
276 #define DDRPHY_PIR_RDIMMINIT_SHIFT (19U)
277 #define DDRPHY_PIR_RDIMMINIT_SET(x) (((uint32_t)(x) << DDRPHY_PIR_RDIMMINIT_SHIFT) & DDRPHY_PIR_RDIMMINIT_MASK)
278 #define DDRPHY_PIR_RDIMMINIT_GET(x) (((uint32_t)(x) & DDRPHY_PIR_RDIMMINIT_MASK) >> DDRPHY_PIR_RDIMMINIT_SHIFT)
279 
280 /*
281  * CTLDINIT (R/W)
282  *
283  * Controller DRAM Initialization: Indicates, if set, that DRAM initialization will be performed by the controller. Otherwise if not set it indicates that DRAM initialization will be performed using the built-in initialization sequence or using software through the configuration port.
284  */
285 #define DDRPHY_PIR_CTLDINIT_MASK (0x40000UL)
286 #define DDRPHY_PIR_CTLDINIT_SHIFT (18U)
287 #define DDRPHY_PIR_CTLDINIT_SET(x) (((uint32_t)(x) << DDRPHY_PIR_CTLDINIT_SHIFT) & DDRPHY_PIR_CTLDINIT_MASK)
288 #define DDRPHY_PIR_CTLDINIT_GET(x) (((uint32_t)(x) & DDRPHY_PIR_CTLDINIT_MASK) >> DDRPHY_PIR_CTLDINIT_SHIFT)
289 
290 /*
291  * PLLBYP (R/W)
292  *
293  * PLL Bypass: A setting of 1 on this bit will put all PHY PLLs in bypass mode.
294  */
295 #define DDRPHY_PIR_PLLBYP_MASK (0x20000UL)
296 #define DDRPHY_PIR_PLLBYP_SHIFT (17U)
297 #define DDRPHY_PIR_PLLBYP_SET(x) (((uint32_t)(x) << DDRPHY_PIR_PLLBYP_SHIFT) & DDRPHY_PIR_PLLBYP_MASK)
298 #define DDRPHY_PIR_PLLBYP_GET(x) (((uint32_t)(x) & DDRPHY_PIR_PLLBYP_MASK) >> DDRPHY_PIR_PLLBYP_SHIFT)
299 
300 /*
301  * ICPC (R/W)
302  *
303  * Initialization Complete Pin Configuration: Specifies how the DFI initialization complete output pin (dfi_init_complete) should be used to indicate the status of initialization. Valid value are:
304  * 0 = Asserted after PHY initialization (DLL locking and impedance calibration) is complete.
305  * 1 = Asserted after PHY initialization is complete and the triggered the PUB initialization (DRAM initialization, data training, or initialization trigger with no selected initialization) is complete.
306  */
307 #define DDRPHY_PIR_ICPC_MASK (0x10000UL)
308 #define DDRPHY_PIR_ICPC_SHIFT (16U)
309 #define DDRPHY_PIR_ICPC_SET(x) (((uint32_t)(x) << DDRPHY_PIR_ICPC_SHIFT) & DDRPHY_PIR_ICPC_MASK)
310 #define DDRPHY_PIR_ICPC_GET(x) (((uint32_t)(x) & DDRPHY_PIR_ICPC_MASK) >> DDRPHY_PIR_ICPC_SHIFT)
311 
312 /*
313  * WREYE (R/W)
314  *
315  * Write Data Eye Training: Executes a PUB training routine to maximize the write data eye.
316  */
317 #define DDRPHY_PIR_WREYE_MASK (0x8000U)
318 #define DDRPHY_PIR_WREYE_SHIFT (15U)
319 #define DDRPHY_PIR_WREYE_SET(x) (((uint32_t)(x) << DDRPHY_PIR_WREYE_SHIFT) & DDRPHY_PIR_WREYE_MASK)
320 #define DDRPHY_PIR_WREYE_GET(x) (((uint32_t)(x) & DDRPHY_PIR_WREYE_MASK) >> DDRPHY_PIR_WREYE_SHIFT)
321 
322 /*
323  * RDEYE (R/W)
324  *
325  * Read Data Eye Training: Executes a PUB training routine to maximize the read data eye.
326  */
327 #define DDRPHY_PIR_RDEYE_MASK (0x4000U)
328 #define DDRPHY_PIR_RDEYE_SHIFT (14U)
329 #define DDRPHY_PIR_RDEYE_SET(x) (((uint32_t)(x) << DDRPHY_PIR_RDEYE_SHIFT) & DDRPHY_PIR_RDEYE_MASK)
330 #define DDRPHY_PIR_RDEYE_GET(x) (((uint32_t)(x) & DDRPHY_PIR_RDEYE_MASK) >> DDRPHY_PIR_RDEYE_SHIFT)
331 
332 /*
333  * WRDSKW (R/W)
334  *
335  * Write Data Bit Deskew: Executes a PUB training routine to deskew the DQ bits during write.
336  */
337 #define DDRPHY_PIR_WRDSKW_MASK (0x2000U)
338 #define DDRPHY_PIR_WRDSKW_SHIFT (13U)
339 #define DDRPHY_PIR_WRDSKW_SET(x) (((uint32_t)(x) << DDRPHY_PIR_WRDSKW_SHIFT) & DDRPHY_PIR_WRDSKW_MASK)
340 #define DDRPHY_PIR_WRDSKW_GET(x) (((uint32_t)(x) & DDRPHY_PIR_WRDSKW_MASK) >> DDRPHY_PIR_WRDSKW_SHIFT)
341 
342 /*
343  * RDDSKW (R/W)
344  *
345  * Read Data Bit Deskew: Executes a PUB training routine to deskew the DQ bits during read.
346  */
347 #define DDRPHY_PIR_RDDSKW_MASK (0x1000U)
348 #define DDRPHY_PIR_RDDSKW_SHIFT (12U)
349 #define DDRPHY_PIR_RDDSKW_SET(x) (((uint32_t)(x) << DDRPHY_PIR_RDDSKW_SHIFT) & DDRPHY_PIR_RDDSKW_MASK)
350 #define DDRPHY_PIR_RDDSKW_GET(x) (((uint32_t)(x) & DDRPHY_PIR_RDDSKW_MASK) >> DDRPHY_PIR_RDDSKW_SHIFT)
351 
352 /*
353  * WLADJ (R/W)
354  *
355  * Write Leveling Adjust (DDR3 Only): Executes a PUB training routine that re- adjusts the write latency used during write in case the write leveling routine changed the expected latency.
356  * Note: Ensure that the DCU command cache is cleared prior to running WLADJ.
357  */
358 #define DDRPHY_PIR_WLADJ_MASK (0x800U)
359 #define DDRPHY_PIR_WLADJ_SHIFT (11U)
360 #define DDRPHY_PIR_WLADJ_SET(x) (((uint32_t)(x) << DDRPHY_PIR_WLADJ_SHIFT) & DDRPHY_PIR_WLADJ_MASK)
361 #define DDRPHY_PIR_WLADJ_GET(x) (((uint32_t)(x) & DDRPHY_PIR_WLADJ_MASK) >> DDRPHY_PIR_WLADJ_SHIFT)
362 
363 /*
364  * QSGATE (R/W)
365  *
366  * Read DQS Gate Training: Executes a PUB training routine to determine the optimum position of the read data DQS strobe for maximum system timing margins.
367  */
368 #define DDRPHY_PIR_QSGATE_MASK (0x400U)
369 #define DDRPHY_PIR_QSGATE_SHIFT (10U)
370 #define DDRPHY_PIR_QSGATE_SET(x) (((uint32_t)(x) << DDRPHY_PIR_QSGATE_SHIFT) & DDRPHY_PIR_QSGATE_MASK)
371 #define DDRPHY_PIR_QSGATE_GET(x) (((uint32_t)(x) & DDRPHY_PIR_QSGATE_MASK) >> DDRPHY_PIR_QSGATE_SHIFT)
372 
373 /*
374  * WL (R/W)
375  *
376  * Write Leveling (DDR3 Only): Executes a PUB write leveling routine.
377  */
378 #define DDRPHY_PIR_WL_MASK (0x200U)
379 #define DDRPHY_PIR_WL_SHIFT (9U)
380 #define DDRPHY_PIR_WL_SET(x) (((uint32_t)(x) << DDRPHY_PIR_WL_SHIFT) & DDRPHY_PIR_WL_MASK)
381 #define DDRPHY_PIR_WL_GET(x) (((uint32_t)(x) & DDRPHY_PIR_WL_MASK) >> DDRPHY_PIR_WL_SHIFT)
382 
383 /*
384  * DRAMINIT (R/W)
385  *
386  * DRAM Initialization: Executes the DRAM initialization sequence.
387  */
388 #define DDRPHY_PIR_DRAMINIT_MASK (0x100U)
389 #define DDRPHY_PIR_DRAMINIT_SHIFT (8U)
390 #define DDRPHY_PIR_DRAMINIT_SET(x) (((uint32_t)(x) << DDRPHY_PIR_DRAMINIT_SHIFT) & DDRPHY_PIR_DRAMINIT_MASK)
391 #define DDRPHY_PIR_DRAMINIT_GET(x) (((uint32_t)(x) & DDRPHY_PIR_DRAMINIT_MASK) >> DDRPHY_PIR_DRAMINIT_SHIFT)
392 
393 /*
394  * DRAMRST (R/W)
395  *
396  * DRAM Reset (DDR3 Only): Issues a reset to the DRAM (by driving the DRAM reset pin low) and wait 200us. This can be triggered in isolation or with the full DRAM initialization (DRAMINIT). For the later case, the reset is issued and 200us is waited before starting the full initialization sequence.
397  */
398 #define DDRPHY_PIR_DRAMRST_MASK (0x80U)
399 #define DDRPHY_PIR_DRAMRST_SHIFT (7U)
400 #define DDRPHY_PIR_DRAMRST_SET(x) (((uint32_t)(x) << DDRPHY_PIR_DRAMRST_SHIFT) & DDRPHY_PIR_DRAMRST_MASK)
401 #define DDRPHY_PIR_DRAMRST_GET(x) (((uint32_t)(x) & DDRPHY_PIR_DRAMRST_MASK) >> DDRPHY_PIR_DRAMRST_SHIFT)
402 
403 /*
404  * PHYRST (R/W)
405  *
406  * PHY Reset: Resets the AC and DATX8 modules by asserting the AC/DATX8 reset pin.
407  */
408 #define DDRPHY_PIR_PHYRST_MASK (0x40U)
409 #define DDRPHY_PIR_PHYRST_SHIFT (6U)
410 #define DDRPHY_PIR_PHYRST_SET(x) (((uint32_t)(x) << DDRPHY_PIR_PHYRST_SHIFT) & DDRPHY_PIR_PHYRST_MASK)
411 #define DDRPHY_PIR_PHYRST_GET(x) (((uint32_t)(x) & DDRPHY_PIR_PHYRST_MASK) >> DDRPHY_PIR_PHYRST_SHIFT)
412 
413 /*
414  * DCAL (R/W)
415  *
416  * Digital Delay Line (DDL) Calibration: Performs PHY delay line calibration.
417  */
418 #define DDRPHY_PIR_DCAL_MASK (0x20U)
419 #define DDRPHY_PIR_DCAL_SHIFT (5U)
420 #define DDRPHY_PIR_DCAL_SET(x) (((uint32_t)(x) << DDRPHY_PIR_DCAL_SHIFT) & DDRPHY_PIR_DCAL_MASK)
421 #define DDRPHY_PIR_DCAL_GET(x) (((uint32_t)(x) & DDRPHY_PIR_DCAL_MASK) >> DDRPHY_PIR_DCAL_SHIFT)
422 
423 /*
424  * PLLINIT (R/W)
425  *
426  * PLL Initialization: Executes the PLL initialization sequence which includes correct driving of PLL power-down, reset and gear shift pins, and then waiting for the PHY PLLs to lock.
427  */
428 #define DDRPHY_PIR_PLLINIT_MASK (0x10U)
429 #define DDRPHY_PIR_PLLINIT_SHIFT (4U)
430 #define DDRPHY_PIR_PLLINIT_SET(x) (((uint32_t)(x) << DDRPHY_PIR_PLLINIT_SHIFT) & DDRPHY_PIR_PLLINIT_MASK)
431 #define DDRPHY_PIR_PLLINIT_GET(x) (((uint32_t)(x) & DDRPHY_PIR_PLLINIT_MASK) >> DDRPHY_PIR_PLLINIT_SHIFT)
432 
433 /*
434  * ZCAL (R/W)
435  *
436  * Impedance Calibration: Performs PHY impedance calibration. When set the impedance calibration will be performed in parallel with PHY initialization (PLL initialization + DDL calibration + PHY reset).
437  */
438 #define DDRPHY_PIR_ZCAL_MASK (0x2U)
439 #define DDRPHY_PIR_ZCAL_SHIFT (1U)
440 #define DDRPHY_PIR_ZCAL_SET(x) (((uint32_t)(x) << DDRPHY_PIR_ZCAL_SHIFT) & DDRPHY_PIR_ZCAL_MASK)
441 #define DDRPHY_PIR_ZCAL_GET(x) (((uint32_t)(x) & DDRPHY_PIR_ZCAL_MASK) >> DDRPHY_PIR_ZCAL_SHIFT)
442 
443 /*
444  * INIT (R/W)
445  *
446  * Initialization Trigger: A write of '1' to this bit triggers the DDR system initialization, including PHY initialization, DRAM initialization, and PHY training. The exact initialization steps to be executed are specified in bits 1 to 15 of this register. A bit setting of 1 means the step will be executed as part of the initialization sequence, while a setting of ‘0’ means the step will be bypassed. The initialization trigger bit is self-clearing.
447  */
448 #define DDRPHY_PIR_INIT_MASK (0x1U)
449 #define DDRPHY_PIR_INIT_SHIFT (0U)
450 #define DDRPHY_PIR_INIT_SET(x) (((uint32_t)(x) << DDRPHY_PIR_INIT_SHIFT) & DDRPHY_PIR_INIT_MASK)
451 #define DDRPHY_PIR_INIT_GET(x) (((uint32_t)(x) & DDRPHY_PIR_INIT_MASK) >> DDRPHY_PIR_INIT_SHIFT)
452 
453 /* Bitfield definition for register: PGCR0 */
454 /*
455  * CKEN (R/W)
456  *
457  * CK Enable: Controls whether the CK going to the SDRAM is enabled (toggling) or disabled (static value) and whether the CK is inverted. Two bits for each of the up to three CK pairs. Valid values for the two bits are:
458  * 00 = CK disabled (Driven to constant 0) 01 = CK toggling with inverted polarity
459  * 10 = CK toggling with normal polarity (This should be the default setting) 11 = CK disabled (Driven to constant 1)
460  */
461 #define DDRPHY_PGCR0_CKEN_MASK (0xFC000000UL)
462 #define DDRPHY_PGCR0_CKEN_SHIFT (26U)
463 #define DDRPHY_PGCR0_CKEN_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_CKEN_SHIFT) & DDRPHY_PGCR0_CKEN_MASK)
464 #define DDRPHY_PGCR0_CKEN_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_CKEN_MASK) >> DDRPHY_PGCR0_CKEN_SHIFT)
465 
466 /*
467  * PUBMODE (R/W)
468  *
469  * Enables, if set, the PUB to control the interface to the PHY and SDRAM. In this mode the DFI commands from the controller are ignored. The bit must be set to 0 after the system determines it is convenient to pass control of the DFI bus to the controller. When set to 0 the DFI interface has control of the PHY and SDRAM interface except when triggering pub operations such as BIST, DCU or data training.
470  */
471 #define DDRPHY_PGCR0_PUBMODE_MASK (0x2000000UL)
472 #define DDRPHY_PGCR0_PUBMODE_SHIFT (25U)
473 #define DDRPHY_PGCR0_PUBMODE_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_PUBMODE_SHIFT) & DDRPHY_PGCR0_PUBMODE_MASK)
474 #define DDRPHY_PGCR0_PUBMODE_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_PUBMODE_MASK) >> DDRPHY_PGCR0_PUBMODE_SHIFT)
475 
476 /*
477  * DTOSEL (R/W)
478  *
479  * Digital Test Output Select: Selects the PHY digital test output that is driven onto PHY digital test output (phy_dto) pin: Valid values are:
480  * 00000 = DATX8 0 PLL digital test output 00001 = DATX8 1 PLL digital test output 00010 = DATX8 2 PLL digital test output 00011 = DATX8 3 PLL digital test output 00100 = DATX8 4 PLL digital test output 00101 = DATX8 5 PLL digital test output 00110 = DATX8 6 PLL digital test output 00111 = DATX8 7 PLL digital test output 01000 = DATX8 8 PLL digital test output 01001 = AC PLL digital test output 01010 – 01111 = Reserved
481  * 10000 = DATX8 0 delay line digital test output 10001 = DATX8 1 delay line digital test output 10010 = DATX8 2 delay line digital test output 10011 = DATX8 3 delay line digital test output 10100 = DATX8 4 delay line digital test output 10101 = DATX8 5 delay line digital test output 10110 = DATX8 6 delay line digital test output 10111 = DATX8 7 delay line digital test output 11000 = DATX8 8 delay line digital test output 11001 = AC delay line digital test output 11010 – 11111 = Reserved
482  */
483 #define DDRPHY_PGCR0_DTOSEL_MASK (0x7C000UL)
484 #define DDRPHY_PGCR0_DTOSEL_SHIFT (14U)
485 #define DDRPHY_PGCR0_DTOSEL_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_DTOSEL_SHIFT) & DDRPHY_PGCR0_DTOSEL_MASK)
486 #define DDRPHY_PGCR0_DTOSEL_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_DTOSEL_MASK) >> DDRPHY_PGCR0_DTOSEL_SHIFT)
487 
488 /*
489  * OSCWDL (R/W)
490  *
491  * Oscillator Mode Write-Leveling Delay Line Select: Selects which of the two write leveling LCDLs is active. The delay select value of the inactive LCDL is set to zero while the delay select value of the active LCDL can be varied by the input write leveling delay select pin. Valid values are:
492  * 00 = No WL LCDL is active 01 = DDR WL LCDL is active 10 = SDR WL LCDL is active 11 = Both LCDLs are active
493  */
494 #define DDRPHY_PGCR0_OSCWDL_MASK (0x3000U)
495 #define DDRPHY_PGCR0_OSCWDL_SHIFT (12U)
496 #define DDRPHY_PGCR0_OSCWDL_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_OSCWDL_SHIFT) & DDRPHY_PGCR0_OSCWDL_MASK)
497 #define DDRPHY_PGCR0_OSCWDL_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_OSCWDL_MASK) >> DDRPHY_PGCR0_OSCWDL_SHIFT)
498 
499 /*
500  * OSCDIV (R/W)
501  *
502  * Oscillator Mode Division: Specifies the factor by which the delay line oscillator mode output is divided down before it is output on the delay line digital test output pin dl_dto. Valid values are:
503  * 000 = Divide by 1
504  * 001 = Divide by 256
505  * 010 = Divide by 512
506  * 011 = Divide by 1024
507  * 100 = Divide by 2048
508  * 101 = Divide by 4096
509  * 110 = Divide by 8192
510  * 111 = Divide by 65536
511  */
512 #define DDRPHY_PGCR0_OSCDIV_MASK (0xE00U)
513 #define DDRPHY_PGCR0_OSCDIV_SHIFT (9U)
514 #define DDRPHY_PGCR0_OSCDIV_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_OSCDIV_SHIFT) & DDRPHY_PGCR0_OSCDIV_MASK)
515 #define DDRPHY_PGCR0_OSCDIV_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_OSCDIV_MASK) >> DDRPHY_PGCR0_OSCDIV_SHIFT)
516 
517 /*
518  * OSCEN (R/W)
519  *
520  * Oscillator Enable: Enables, if set, the delay line oscillation.
521  */
522 #define DDRPHY_PGCR0_OSCEN_MASK (0x100U)
523 #define DDRPHY_PGCR0_OSCEN_SHIFT (8U)
524 #define DDRPHY_PGCR0_OSCEN_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_OSCEN_SHIFT) & DDRPHY_PGCR0_OSCEN_MASK)
525 #define DDRPHY_PGCR0_OSCEN_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_OSCEN_MASK) >> DDRPHY_PGCR0_OSCEN_SHIFT)
526 
527 /*
528  * DLTST (R/W)
529  *
530  * Delay Line Test Start: A write of '1' to this bit will trigger delay line oscillator mode period measurement. This bit is not self clearing and needs to be reset to '0' before the measurement can be re-triggered.
531  */
532 #define DDRPHY_PGCR0_DLTST_MASK (0x80U)
533 #define DDRPHY_PGCR0_DLTST_SHIFT (7U)
534 #define DDRPHY_PGCR0_DLTST_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_DLTST_SHIFT) & DDRPHY_PGCR0_DLTST_MASK)
535 #define DDRPHY_PGCR0_DLTST_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_DLTST_MASK) >> DDRPHY_PGCR0_DLTST_SHIFT)
536 
537 /*
538  * DLTMODE (R/W)
539  *
540  * Delay Line Test Mode: Selects, if set, the delay line oscillator test mode. Setting this bit also clears all delay line register values. For DL oscillator testing, first set this bit, then apply desired non-zero LCDL and BDL register programmings.
541  */
542 #define DDRPHY_PGCR0_DLTMODE_MASK (0x40U)
543 #define DDRPHY_PGCR0_DLTMODE_SHIFT (6U)
544 #define DDRPHY_PGCR0_DLTMODE_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_DLTMODE_SHIFT) & DDRPHY_PGCR0_DLTMODE_MASK)
545 #define DDRPHY_PGCR0_DLTMODE_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_DLTMODE_MASK) >> DDRPHY_PGCR0_DLTMODE_SHIFT)
546 
547 /*
548  * RDBVT (R/W)
549  *
550  * Read Data BDL VT Compensation: Enables, if set, the VT drift compensation of the read data bit delay lines.
551  */
552 #define DDRPHY_PGCR0_RDBVT_MASK (0x20U)
553 #define DDRPHY_PGCR0_RDBVT_SHIFT (5U)
554 #define DDRPHY_PGCR0_RDBVT_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_RDBVT_SHIFT) & DDRPHY_PGCR0_RDBVT_MASK)
555 #define DDRPHY_PGCR0_RDBVT_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_RDBVT_MASK) >> DDRPHY_PGCR0_RDBVT_SHIFT)
556 
557 /*
558  * WDBVT (R/W)
559  *
560  * Write Data BDL VT Compensation: Enables, if set, the VT drift compensation of the write data bit delay lines.
561  */
562 #define DDRPHY_PGCR0_WDBVT_MASK (0x10U)
563 #define DDRPHY_PGCR0_WDBVT_SHIFT (4U)
564 #define DDRPHY_PGCR0_WDBVT_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_WDBVT_SHIFT) & DDRPHY_PGCR0_WDBVT_MASK)
565 #define DDRPHY_PGCR0_WDBVT_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_WDBVT_MASK) >> DDRPHY_PGCR0_WDBVT_SHIFT)
566 
567 /*
568  * RGLVT (R/W)
569  *
570  * Read DQS Gating LCDL Delay VT Compensation: Enables, if set, the VT drift compensation of the read DQS gating LCDL.
571  */
572 #define DDRPHY_PGCR0_RGLVT_MASK (0x8U)
573 #define DDRPHY_PGCR0_RGLVT_SHIFT (3U)
574 #define DDRPHY_PGCR0_RGLVT_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_RGLVT_SHIFT) & DDRPHY_PGCR0_RGLVT_MASK)
575 #define DDRPHY_PGCR0_RGLVT_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_RGLVT_MASK) >> DDRPHY_PGCR0_RGLVT_SHIFT)
576 
577 /*
578  * RDLVT (R/W)
579  *
580  * Read DQS LCDL Delay VT Compensation: Enables, if set, the VT drift compensation of the read DQS LCDL.
581  */
582 #define DDRPHY_PGCR0_RDLVT_MASK (0x4U)
583 #define DDRPHY_PGCR0_RDLVT_SHIFT (2U)
584 #define DDRPHY_PGCR0_RDLVT_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_RDLVT_SHIFT) & DDRPHY_PGCR0_RDLVT_MASK)
585 #define DDRPHY_PGCR0_RDLVT_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_RDLVT_MASK) >> DDRPHY_PGCR0_RDLVT_SHIFT)
586 
587 /*
588  * WDLVT (R/W)
589  *
590  * Write DQ LCDL Delay VT Compensation: Enables, if set, the VT drift compensation of the write DQ LCDL.
591  */
592 #define DDRPHY_PGCR0_WDLVT_MASK (0x2U)
593 #define DDRPHY_PGCR0_WDLVT_SHIFT (1U)
594 #define DDRPHY_PGCR0_WDLVT_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_WDLVT_SHIFT) & DDRPHY_PGCR0_WDLVT_MASK)
595 #define DDRPHY_PGCR0_WDLVT_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_WDLVT_MASK) >> DDRPHY_PGCR0_WDLVT_SHIFT)
596 
597 /*
598  * WLLVT (R/W)
599  *
600  * Write Leveling LCDL Delay VT Compensation: Enables, if set, the VT drift compensation of the write leveling LCDL.
601  */
602 #define DDRPHY_PGCR0_WLLVT_MASK (0x1U)
603 #define DDRPHY_PGCR0_WLLVT_SHIFT (0U)
604 #define DDRPHY_PGCR0_WLLVT_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_WLLVT_SHIFT) & DDRPHY_PGCR0_WLLVT_MASK)
605 #define DDRPHY_PGCR0_WLLVT_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_WLLVT_MASK) >> DDRPHY_PGCR0_WLLVT_SHIFT)
606 
607 /* Bitfield definition for register: PGCR1 */
608 /*
609  * LBMODE (R/W)
610  *
611  * Loopback Mode: Indicates, if set, that the PHY/PUB is in loopback mode.
612  */
613 #define DDRPHY_PGCR1_LBMODE_MASK (0x80000000UL)
614 #define DDRPHY_PGCR1_LBMODE_SHIFT (31U)
615 #define DDRPHY_PGCR1_LBMODE_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_LBMODE_SHIFT) & DDRPHY_PGCR1_LBMODE_MASK)
616 #define DDRPHY_PGCR1_LBMODE_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_LBMODE_MASK) >> DDRPHY_PGCR1_LBMODE_SHIFT)
617 
618 /*
619  * LBGDQS (R/W)
620  *
621  * Loopback DQS Gating: Selects the DQS gating mode that should be used when the PHY is in loopback mode, including BIST loopback mode. Valid values are:
622  * 00 = DQS gate is always on
623  * 01 = DQS gate training will be triggered on the PUB 10 = DQS gate is set manually using software
624  * 11 = Reserved
625  */
626 #define DDRPHY_PGCR1_LBGDQS_MASK (0x60000000UL)
627 #define DDRPHY_PGCR1_LBGDQS_SHIFT (29U)
628 #define DDRPHY_PGCR1_LBGDQS_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_LBGDQS_SHIFT) & DDRPHY_PGCR1_LBGDQS_MASK)
629 #define DDRPHY_PGCR1_LBGDQS_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_LBGDQS_MASK) >> DDRPHY_PGCR1_LBGDQS_SHIFT)
630 
631 /*
632  * LBDQSS (R/W)
633  *
634  * Loopback DQS Shift: Selects how the read DQS is shifted during loopback to ensure that the read DQS is centered into the read data eye. Valid values are:
635  * 1b0 = PUB sets the read DQS LCDL to 0 (internally). DQS is already shifted 90 degrees by write path
636  * 1b1 = The read DQS shift is set manually through software
637  */
638 #define DDRPHY_PGCR1_LBDQSS_MASK (0x10000000UL)
639 #define DDRPHY_PGCR1_LBDQSS_SHIFT (28U)
640 #define DDRPHY_PGCR1_LBDQSS_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_LBDQSS_SHIFT) & DDRPHY_PGCR1_LBDQSS_MASK)
641 #define DDRPHY_PGCR1_LBDQSS_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_LBDQSS_MASK) >> DDRPHY_PGCR1_LBDQSS_SHIFT)
642 
643 /*
644  * IOLB (R/W)
645  *
646  * I/O Loop-Back Select: Selects where inside the I/O the loop-back of signals happens. Valid values are:
647  * 0 = Loopback is after output buffer; output enable must be asserted 1 = Loopback is before output buffer; output enable is don’t care
648  */
649 #define DDRPHY_PGCR1_IOLB_MASK (0x8000000UL)
650 #define DDRPHY_PGCR1_IOLB_SHIFT (27U)
651 #define DDRPHY_PGCR1_IOLB_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_IOLB_SHIFT) & DDRPHY_PGCR1_IOLB_MASK)
652 #define DDRPHY_PGCR1_IOLB_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_IOLB_MASK) >> DDRPHY_PGCR1_IOLB_SHIFT)
653 
654 /*
655  * INHVT (R/W)
656  *
657  * VT Calculation Inhibit: Inhibits calculation of the next VT compensated delay line values. A value of 1 will inhibit the VT calculation. This bit should be set to 1 during writes to the delay line registers.
658  */
659 #define DDRPHY_PGCR1_INHVT_MASK (0x4000000UL)
660 #define DDRPHY_PGCR1_INHVT_SHIFT (26U)
661 #define DDRPHY_PGCR1_INHVT_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_INHVT_SHIFT) & DDRPHY_PGCR1_INHVT_MASK)
662 #define DDRPHY_PGCR1_INHVT_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_INHVT_MASK) >> DDRPHY_PGCR1_INHVT_SHIFT)
663 
664 /*
665  * DXHRST (R/W)
666  *
667  * DX PHY High-Speed Reset: a Write of '0' to this bit resets the DX macro without resetting the PUB RTL logic. This bit is not self-clearing and a '1' must be written to de-assert the reset.
668  */
669 #define DDRPHY_PGCR1_DXHRST_MASK (0x2000000UL)
670 #define DDRPHY_PGCR1_DXHRST_SHIFT (25U)
671 #define DDRPHY_PGCR1_DXHRST_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_DXHRST_SHIFT) & DDRPHY_PGCR1_DXHRST_MASK)
672 #define DDRPHY_PGCR1_DXHRST_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_DXHRST_MASK) >> DDRPHY_PGCR1_DXHRST_SHIFT)
673 
674 /*
675  * ZCKSEL (R/W)
676  *
677  * Impedance Clock Divider Select: Selects the divide ratio for the clock used by the impedance control logic relative to the clock used by the memory controller and SDRAM.
678  * Valid values are:
679  * 00 = Divide by 2
680  * 01 = Divide by 8
681  * 10 = Divide by 32
682  * 11 = Divide by 64
683  * For more information, refer to “Impedance Calibration” on page 174.
684  */
685 #define DDRPHY_PGCR1_ZCKSEL_MASK (0x1800000UL)
686 #define DDRPHY_PGCR1_ZCKSEL_SHIFT (23U)
687 #define DDRPHY_PGCR1_ZCKSEL_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_ZCKSEL_SHIFT) & DDRPHY_PGCR1_ZCKSEL_MASK)
688 #define DDRPHY_PGCR1_ZCKSEL_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_ZCKSEL_MASK) >> DDRPHY_PGCR1_ZCKSEL_SHIFT)
689 
690 /*
691  * DLDLMT (R/W)
692  *
693  * Delay Line VT Drift Limit: Specifies the minimum change in the delay line VT drift in one direction which should result in the assertion of the delay line VT drift status signal (vt_drift). The limit is specified in terms of delay select values. A value of 0 disables the assertion of delay line VT drift status signal.
694  */
695 #define DDRPHY_PGCR1_DLDLMT_MASK (0x7F8000UL)
696 #define DDRPHY_PGCR1_DLDLMT_SHIFT (15U)
697 #define DDRPHY_PGCR1_DLDLMT_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_DLDLMT_SHIFT) & DDRPHY_PGCR1_DLDLMT_MASK)
698 #define DDRPHY_PGCR1_DLDLMT_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_DLDLMT_MASK) >> DDRPHY_PGCR1_DLDLMT_SHIFT)
699 
700 /*
701  * FDEPTH (R/W)
702  *
703  * Filter Depth: Specifies the number of measurements over which all AC and DATX8 initial period measurements, that happen after reset or when calibration is manually triggered, are averaged. Valid values are:
704  * 00 = 2
705  * 01 = 4
706  * 10 = 8
707  * 11 = 16
708  */
709 #define DDRPHY_PGCR1_FDEPTH_MASK (0x6000U)
710 #define DDRPHY_PGCR1_FDEPTH_SHIFT (13U)
711 #define DDRPHY_PGCR1_FDEPTH_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_FDEPTH_SHIFT) & DDRPHY_PGCR1_FDEPTH_MASK)
712 #define DDRPHY_PGCR1_FDEPTH_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_FDEPTH_MASK) >> DDRPHY_PGCR1_FDEPTH_SHIFT)
713 
714 /*
715  * LPFDEPTH (R/W)
716  *
717  * Low-Pass Filter Depth: Specifies the number of measurements over which MDL period measurements are filtered. This determines the time constant of the low pass filter. Valid values are:
718  * 00 = 2
719  * 01 = 4
720  * 10 = 8
721  * 11 = 16
722  */
723 #define DDRPHY_PGCR1_LPFDEPTH_MASK (0x1800U)
724 #define DDRPHY_PGCR1_LPFDEPTH_SHIFT (11U)
725 #define DDRPHY_PGCR1_LPFDEPTH_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_LPFDEPTH_SHIFT) & DDRPHY_PGCR1_LPFDEPTH_MASK)
726 #define DDRPHY_PGCR1_LPFDEPTH_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_LPFDEPTH_MASK) >> DDRPHY_PGCR1_LPFDEPTH_SHIFT)
727 
728 /*
729  * LPFEN (R/W)
730  *
731  * Low-Pass Filter Enable: Enables, if set, the low pass filtering of MDL period measurements.
732  */
733 #define DDRPHY_PGCR1_LPFEN_MASK (0x400U)
734 #define DDRPHY_PGCR1_LPFEN_SHIFT (10U)
735 #define DDRPHY_PGCR1_LPFEN_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_LPFEN_SHIFT) & DDRPHY_PGCR1_LPFEN_MASK)
736 #define DDRPHY_PGCR1_LPFEN_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_LPFEN_MASK) >> DDRPHY_PGCR1_LPFEN_SHIFT)
737 
738 /*
739  * MDLEN (R/W)
740  *
741  * Master Delay Line Enable: Enables, if set, the AC master delay line calibration to perform subsequent period measurements following the initial period measurements that are performed after reset or on when calibration is manually triggered. These additional measurements are accumulated and filtered as long as this bit remains high.
742  */
743 #define DDRPHY_PGCR1_MDLEN_MASK (0x200U)
744 #define DDRPHY_PGCR1_MDLEN_SHIFT (9U)
745 #define DDRPHY_PGCR1_MDLEN_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_MDLEN_SHIFT) & DDRPHY_PGCR1_MDLEN_MASK)
746 #define DDRPHY_PGCR1_MDLEN_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_MDLEN_MASK) >> DDRPHY_PGCR1_MDLEN_SHIFT)
747 
748 /*
749  * IODDRM (R/W)
750  *
751  * I/O DDR Mode (D3F I/O Only): Selects the DDR mode for the I/Os. These bits connect to bits [2:1] of the IOM pin of the SSTL I/O. For more information, refer to the SSTL I/O chapter in the DWC DDR PHY Databook.
752  */
753 #define DDRPHY_PGCR1_IODDRM_MASK (0x180U)
754 #define DDRPHY_PGCR1_IODDRM_SHIFT (7U)
755 #define DDRPHY_PGCR1_IODDRM_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_IODDRM_SHIFT) & DDRPHY_PGCR1_IODDRM_MASK)
756 #define DDRPHY_PGCR1_IODDRM_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_IODDRM_MASK) >> DDRPHY_PGCR1_IODDRM_SHIFT)
757 
758 /*
759  * WLSELT (R/W)
760  *
761  * Write Leveling Select Type: Selects the encoding type for the write leveling select signal depending on the desired setup/hold margins for the internal pipelines. Refer to the DDR PHY Databook for details of how the select type is used. Valid values are:
762  * 0 = Type 1: Setup margin of 90 degrees and hold margin of 90 degrees 1 = Type 2: Setup margin of 135 degrees and hold margin of 45 degrees
763  */
764 #define DDRPHY_PGCR1_WLSELT_MASK (0x40U)
765 #define DDRPHY_PGCR1_WLSELT_SHIFT (6U)
766 #define DDRPHY_PGCR1_WLSELT_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_WLSELT_SHIFT) & DDRPHY_PGCR1_WLSELT_MASK)
767 #define DDRPHY_PGCR1_WLSELT_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_WLSELT_MASK) >> DDRPHY_PGCR1_WLSELT_SHIFT)
768 
769 /*
770  * ACHRST (R/W)
771  *
772  * AC PHY High-Speed Reset: a Write of '0' to this bit resets the AC macro without resetting the PUB RTL logic. This bit is not self-clearing and a '1' must be written to de-assert the reset.
773  */
774 #define DDRPHY_PGCR1_ACHRST_MASK (0x20U)
775 #define DDRPHY_PGCR1_ACHRST_SHIFT (5U)
776 #define DDRPHY_PGCR1_ACHRST_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_ACHRST_SHIFT) & DDRPHY_PGCR1_ACHRST_MASK)
777 #define DDRPHY_PGCR1_ACHRST_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_ACHRST_MASK) >> DDRPHY_PGCR1_ACHRST_SHIFT)
778 
779 /*
780  * WSLOPT (R/W)
781  *
782  * Write System Latency Optimization: controls the insertion of a pipeline stage on the AC signals from the DFI interface to the PHY to cater for a negative write system latency (WSL) value (only -1 possible).
783  * 0x0 = A pipeline stage is inserted only if WL2 training results in a WSL of -1 for any rank
784  * 0x1 = Inserts a pipeline stage
785  */
786 #define DDRPHY_PGCR1_WSLOPT_MASK (0x10U)
787 #define DDRPHY_PGCR1_WSLOPT_SHIFT (4U)
788 #define DDRPHY_PGCR1_WSLOPT_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_WSLOPT_SHIFT) & DDRPHY_PGCR1_WSLOPT_MASK)
789 #define DDRPHY_PGCR1_WSLOPT_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_WSLOPT_MASK) >> DDRPHY_PGCR1_WSLOPT_SHIFT)
790 
791 /*
792  * WLSTEP (R/W)
793  *
794  * Write Leveling Step: Specifies the number of delay step-size increments during each step of write leveling. Valid values are:
795  * 0 = computed to be 1/2 of the associated lane's DXnGSR0.WLPRD value 1 = 1 step size
796  */
797 #define DDRPHY_PGCR1_WLSTEP_MASK (0x4U)
798 #define DDRPHY_PGCR1_WLSTEP_SHIFT (2U)
799 #define DDRPHY_PGCR1_WLSTEP_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_WLSTEP_SHIFT) & DDRPHY_PGCR1_WLSTEP_MASK)
800 #define DDRPHY_PGCR1_WLSTEP_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_WLSTEP_MASK) >> DDRPHY_PGCR1_WLSTEP_SHIFT)
801 
802 /*
803  * WLMODE (R/W)
804  *
805  * Write Leveling (Software) Mode: Indicates, if set, that the PUB is in software write leveling mode in which software executes single steps of DQS pulsing by writing '1' to PIR.WL. The write leveling DQ status from the DRAM is captured in DXnGSR0.WLDQ.
806  */
807 #define DDRPHY_PGCR1_WLMODE_MASK (0x2U)
808 #define DDRPHY_PGCR1_WLMODE_SHIFT (1U)
809 #define DDRPHY_PGCR1_WLMODE_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_WLMODE_SHIFT) & DDRPHY_PGCR1_WLMODE_MASK)
810 #define DDRPHY_PGCR1_WLMODE_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_WLMODE_MASK) >> DDRPHY_PGCR1_WLMODE_SHIFT)
811 
812 /*
813  * PDDISDX (R/W)
814  *
815  * Power Down Disabled Byte: Indicates, if set, that the PLL and I/Os of a disabled byte should be powered down.
816  */
817 #define DDRPHY_PGCR1_PDDISDX_MASK (0x1U)
818 #define DDRPHY_PGCR1_PDDISDX_SHIFT (0U)
819 #define DDRPHY_PGCR1_PDDISDX_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_PDDISDX_SHIFT) & DDRPHY_PGCR1_PDDISDX_MASK)
820 #define DDRPHY_PGCR1_PDDISDX_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_PDDISDX_MASK) >> DDRPHY_PGCR1_PDDISDX_SHIFT)
821 
822 /* Bitfield definition for register: PGSR0 */
823 /*
824  * APLOCK (R)
825  *
826  * AC PLL Lock: Indicates, if set, that AC PLL has locked. This is a direct status of the AC PLL lock pin.
827  */
828 #define DDRPHY_PGSR0_APLOCK_MASK (0x80000000UL)
829 #define DDRPHY_PGSR0_APLOCK_SHIFT (31U)
830 #define DDRPHY_PGSR0_APLOCK_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_APLOCK_MASK) >> DDRPHY_PGSR0_APLOCK_SHIFT)
831 
832 /*
833  * PLDONE_CHN (R)
834  *
835  * PLL Lock Done per Channel: Indicates PLL locking has completed for each underlying channel. Bit 28 represents channel 0 while bit 29 represents channel 1.
836  */
837 #define DDRPHY_PGSR0_PLDONE_CHN_MASK (0x30000000UL)
838 #define DDRPHY_PGSR0_PLDONE_CHN_SHIFT (28U)
839 #define DDRPHY_PGSR0_PLDONE_CHN_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_PLDONE_CHN_MASK) >> DDRPHY_PGSR0_PLDONE_CHN_SHIFT)
840 
841 /*
842  * WEERR (R)
843  *
844  * Write Eye Training Error: Indicates, if set, that there is an error in write eye training.
845  */
846 #define DDRPHY_PGSR0_WEERR_MASK (0x8000000UL)
847 #define DDRPHY_PGSR0_WEERR_SHIFT (27U)
848 #define DDRPHY_PGSR0_WEERR_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_WEERR_MASK) >> DDRPHY_PGSR0_WEERR_SHIFT)
849 
850 /*
851  * REERR (R)
852  *
853  * Read Data Eye Training Error: Indicates, if set, that there is an error in read eye training.
854  */
855 #define DDRPHY_PGSR0_REERR_MASK (0x4000000UL)
856 #define DDRPHY_PGSR0_REERR_SHIFT (26U)
857 #define DDRPHY_PGSR0_REERR_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_REERR_MASK) >> DDRPHY_PGSR0_REERR_SHIFT)
858 
859 /*
860  * WDERR (R)
861  *
862  * Write Data Bit Deskew Error: Indicates, if set, that there is an error in write bit deskew.
863  */
864 #define DDRPHY_PGSR0_WDERR_MASK (0x2000000UL)
865 #define DDRPHY_PGSR0_WDERR_SHIFT (25U)
866 #define DDRPHY_PGSR0_WDERR_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_WDERR_MASK) >> DDRPHY_PGSR0_WDERR_SHIFT)
867 
868 /*
869  * RDERR (R)
870  *
871  * Read Data Bit Deskew Error: Indicates, if set, that there is an error in read bit deskew.
872  */
873 #define DDRPHY_PGSR0_RDERR_MASK (0x1000000UL)
874 #define DDRPHY_PGSR0_RDERR_SHIFT (24U)
875 #define DDRPHY_PGSR0_RDERR_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_RDERR_MASK) >> DDRPHY_PGSR0_RDERR_SHIFT)
876 
877 /*
878  * WLAERR (R)
879  *
880  * Write Data Leveling Adjustment Error: Indicates, if set, that there is an error in write leveling adjustment.
881  */
882 #define DDRPHY_PGSR0_WLAERR_MASK (0x800000UL)
883 #define DDRPHY_PGSR0_WLAERR_SHIFT (23U)
884 #define DDRPHY_PGSR0_WLAERR_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_WLAERR_MASK) >> DDRPHY_PGSR0_WLAERR_SHIFT)
885 
886 /*
887  * QSGERR (R)
888  *
889  * Read DQS Gate Training Error: Indicates, if set, that there is an error in DQS gate training.
890  */
891 #define DDRPHY_PGSR0_QSGERR_MASK (0x400000UL)
892 #define DDRPHY_PGSR0_QSGERR_SHIFT (22U)
893 #define DDRPHY_PGSR0_QSGERR_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_QSGERR_MASK) >> DDRPHY_PGSR0_QSGERR_SHIFT)
894 
895 /*
896  * WLERR (R)
897  *
898  * Write Leveling Error: Indicates, if set, that there is an error in write leveling.
899  */
900 #define DDRPHY_PGSR0_WLERR_MASK (0x200000UL)
901 #define DDRPHY_PGSR0_WLERR_SHIFT (21U)
902 #define DDRPHY_PGSR0_WLERR_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_WLERR_MASK) >> DDRPHY_PGSR0_WLERR_SHIFT)
903 
904 /*
905  * ZCERR (R)
906  *
907  * Impedance Calibration Error: Indicates, if set, that there is an error in impedance calibration.
908  */
909 #define DDRPHY_PGSR0_ZCERR_MASK (0x100000UL)
910 #define DDRPHY_PGSR0_ZCERR_SHIFT (20U)
911 #define DDRPHY_PGSR0_ZCERR_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_ZCERR_MASK) >> DDRPHY_PGSR0_ZCERR_SHIFT)
912 
913 /*
914  * WEDONE (R)
915  *
916  * Write Data Eye Training Done: Indicates, if set, that write eye training has completed.
917  */
918 #define DDRPHY_PGSR0_WEDONE_MASK (0x800U)
919 #define DDRPHY_PGSR0_WEDONE_SHIFT (11U)
920 #define DDRPHY_PGSR0_WEDONE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_WEDONE_MASK) >> DDRPHY_PGSR0_WEDONE_SHIFT)
921 
922 /*
923  * REDONE (R)
924  *
925  * Read Data Eye Training Done: Indicates, if set, that read eye training has completed.
926  */
927 #define DDRPHY_PGSR0_REDONE_MASK (0x400U)
928 #define DDRPHY_PGSR0_REDONE_SHIFT (10U)
929 #define DDRPHY_PGSR0_REDONE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_REDONE_MASK) >> DDRPHY_PGSR0_REDONE_SHIFT)
930 
931 /*
932  * WDDONE (R)
933  *
934  * Write Data Bit Deskew Done: Indicates, if set, that write bit deskew has completed.
935  */
936 #define DDRPHY_PGSR0_WDDONE_MASK (0x200U)
937 #define DDRPHY_PGSR0_WDDONE_SHIFT (9U)
938 #define DDRPHY_PGSR0_WDDONE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_WDDONE_MASK) >> DDRPHY_PGSR0_WDDONE_SHIFT)
939 
940 /*
941  * RDDONE (R)
942  *
943  * Read Data Bit Deskew Done: Indicates, if set, that read bit deskew has completed.
944  */
945 #define DDRPHY_PGSR0_RDDONE_MASK (0x100U)
946 #define DDRPHY_PGSR0_RDDONE_SHIFT (8U)
947 #define DDRPHY_PGSR0_RDDONE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_RDDONE_MASK) >> DDRPHY_PGSR0_RDDONE_SHIFT)
948 
949 /*
950  * WLADONE (R)
951  *
952  * Write Leveling Adjustment Done: Indicates, if set, that write leveling adjustment has completed.
953  */
954 #define DDRPHY_PGSR0_WLADONE_MASK (0x80U)
955 #define DDRPHY_PGSR0_WLADONE_SHIFT (7U)
956 #define DDRPHY_PGSR0_WLADONE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_WLADONE_MASK) >> DDRPHY_PGSR0_WLADONE_SHIFT)
957 
958 /*
959  * QSGDONE (R)
960  *
961  * Read DQS Gate Training Done: Indicates, if set, that DQS gate training has completed.
962  */
963 #define DDRPHY_PGSR0_QSGDONE_MASK (0x40U)
964 #define DDRPHY_PGSR0_QSGDONE_SHIFT (6U)
965 #define DDRPHY_PGSR0_QSGDONE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_QSGDONE_MASK) >> DDRPHY_PGSR0_QSGDONE_SHIFT)
966 
967 /*
968  * WLDONE (R)
969  *
970  * Write Leveling Done: Indicates, if set, that write leveling has completed.
971  */
972 #define DDRPHY_PGSR0_WLDONE_MASK (0x20U)
973 #define DDRPHY_PGSR0_WLDONE_SHIFT (5U)
974 #define DDRPHY_PGSR0_WLDONE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_WLDONE_MASK) >> DDRPHY_PGSR0_WLDONE_SHIFT)
975 
976 /*
977  * DIDONE (R)
978  *
979  * DRAM Initialization Done: Indicates, if set, that DRAM initialization has completed.
980  */
981 #define DDRPHY_PGSR0_DIDONE_MASK (0x10U)
982 #define DDRPHY_PGSR0_DIDONE_SHIFT (4U)
983 #define DDRPHY_PGSR0_DIDONE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_DIDONE_MASK) >> DDRPHY_PGSR0_DIDONE_SHIFT)
984 
985 /*
986  * ZCDONE (R)
987  *
988  * Impedance Calibration Done: Indicates, if set, that impedance calibration has completed.
989  */
990 #define DDRPHY_PGSR0_ZCDONE_MASK (0x8U)
991 #define DDRPHY_PGSR0_ZCDONE_SHIFT (3U)
992 #define DDRPHY_PGSR0_ZCDONE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_ZCDONE_MASK) >> DDRPHY_PGSR0_ZCDONE_SHIFT)
993 
994 /*
995  * DCDONE (R)
996  *
997  * Digital Delay Line (DDL) Calibration Done: Indicates, if set, that DDL calibration has completed.
998  */
999 #define DDRPHY_PGSR0_DCDONE_MASK (0x4U)
1000 #define DDRPHY_PGSR0_DCDONE_SHIFT (2U)
1001 #define DDRPHY_PGSR0_DCDONE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_DCDONE_MASK) >> DDRPHY_PGSR0_DCDONE_SHIFT)
1002 
1003 /*
1004  * PLDONE (R)
1005  *
1006  * PLL Lock Done: Indicates, if set, that PLL locking has completed.
1007  */
1008 #define DDRPHY_PGSR0_PLDONE_MASK (0x2U)
1009 #define DDRPHY_PGSR0_PLDONE_SHIFT (1U)
1010 #define DDRPHY_PGSR0_PLDONE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_PLDONE_MASK) >> DDRPHY_PGSR0_PLDONE_SHIFT)
1011 
1012 /*
1013  * IDONE (R)
1014  *
1015  * Initialization Done: Indicates, if set, that the DDR system initialization has completed. This bit is set after all the selected initialization routines in PIR register have completed.
1016  */
1017 #define DDRPHY_PGSR0_IDONE_MASK (0x1U)
1018 #define DDRPHY_PGSR0_IDONE_SHIFT (0U)
1019 #define DDRPHY_PGSR0_IDONE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_IDONE_MASK) >> DDRPHY_PGSR0_IDONE_SHIFT)
1020 
1021 /* Bitfield definition for register: PGSR1 */
1022 /*
1023  * PARERR (R)
1024  *
1025  * RDIMM Parity Error: Indicates, if set, that there was a parity error (i.e. err_out_n was sampled low) during one of the transactions to the RDIMM buffer chip. This bit remains asserted until cleared by the PIR.CLRSR.
1026  */
1027 #define DDRPHY_PGSR1_PARERR_MASK (0x80000000UL)
1028 #define DDRPHY_PGSR1_PARERR_SHIFT (31U)
1029 #define DDRPHY_PGSR1_PARERR_GET(x) (((uint32_t)(x) & DDRPHY_PGSR1_PARERR_MASK) >> DDRPHY_PGSR1_PARERR_SHIFT)
1030 
1031 /*
1032  * VTSTOP (R)
1033  *
1034  * VT Stop: Indicates, if set, that the VT calculation logic has stopped computing the next values for the VT compensated delay line values. After assertion of the PGCR.INHVT, the VTSTOP bit should be read to ensure all VT compensation logic has stopped computations before writing to the delay line registers.
1035  */
1036 #define DDRPHY_PGSR1_VTSTOP_MASK (0x40000000UL)
1037 #define DDRPHY_PGSR1_VTSTOP_SHIFT (30U)
1038 #define DDRPHY_PGSR1_VTSTOP_GET(x) (((uint32_t)(x) & DDRPHY_PGSR1_VTSTOP_MASK) >> DDRPHY_PGSR1_VTSTOP_SHIFT)
1039 
1040 /*
1041  * DLTCODE (R)
1042  *
1043  * Delay Line Test Code: Returns the code measured by the PHY control block that corresponds to the period of the AC delay line digital test output.
1044  */
1045 #define DDRPHY_PGSR1_DLTCODE_MASK (0x1FFFFFEUL)
1046 #define DDRPHY_PGSR1_DLTCODE_SHIFT (1U)
1047 #define DDRPHY_PGSR1_DLTCODE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR1_DLTCODE_MASK) >> DDRPHY_PGSR1_DLTCODE_SHIFT)
1048 
1049 /*
1050  * DLTDONE (R)
1051  *
1052  * Delay Line Test Done: Indicates, if set, that the PHY control block has finished doing period measurement of the AC delay line digital test output.
1053  */
1054 #define DDRPHY_PGSR1_DLTDONE_MASK (0x1U)
1055 #define DDRPHY_PGSR1_DLTDONE_SHIFT (0U)
1056 #define DDRPHY_PGSR1_DLTDONE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR1_DLTDONE_MASK) >> DDRPHY_PGSR1_DLTDONE_SHIFT)
1057 
1058 /* Bitfield definition for register: PLLCR */
1059 /*
1060  * BYP (R/W)
1061  *
1062  * PLL Bypass: Bypasses the PLL, if set, to 1.
1063  */
1064 #define DDRPHY_PLLCR_BYP_MASK (0x80000000UL)
1065 #define DDRPHY_PLLCR_BYP_SHIFT (31U)
1066 #define DDRPHY_PLLCR_BYP_SET(x) (((uint32_t)(x) << DDRPHY_PLLCR_BYP_SHIFT) & DDRPHY_PLLCR_BYP_MASK)
1067 #define DDRPHY_PLLCR_BYP_GET(x) (((uint32_t)(x) & DDRPHY_PLLCR_BYP_MASK) >> DDRPHY_PLLCR_BYP_SHIFT)
1068 
1069 /*
1070  * PLLRST (R/W)
1071  *
1072  * PLL Rest: Resets the PLLs by driving the PLL reset pin. This bit is not self-clearing and a ‘0’ must be written to de-assert the reset.
1073  */
1074 #define DDRPHY_PLLCR_PLLRST_MASK (0x40000000UL)
1075 #define DDRPHY_PLLCR_PLLRST_SHIFT (30U)
1076 #define DDRPHY_PLLCR_PLLRST_SET(x) (((uint32_t)(x) << DDRPHY_PLLCR_PLLRST_SHIFT) & DDRPHY_PLLCR_PLLRST_MASK)
1077 #define DDRPHY_PLLCR_PLLRST_GET(x) (((uint32_t)(x) & DDRPHY_PLLCR_PLLRST_MASK) >> DDRPHY_PLLCR_PLLRST_SHIFT)
1078 
1079 /*
1080  * PLLPD (R/W)
1081  *
1082  * PLL Power Down: Puts the PLLs in power down mode by driving the PLL power down pin. This bit is not self-clearing and a ‘0’ must be written to de-assert the power-down.
1083  */
1084 #define DDRPHY_PLLCR_PLLPD_MASK (0x20000000UL)
1085 #define DDRPHY_PLLCR_PLLPD_SHIFT (29U)
1086 #define DDRPHY_PLLCR_PLLPD_SET(x) (((uint32_t)(x) << DDRPHY_PLLCR_PLLPD_SHIFT) & DDRPHY_PLLCR_PLLPD_MASK)
1087 #define DDRPHY_PLLCR_PLLPD_GET(x) (((uint32_t)(x) & DDRPHY_PLLCR_PLLPD_MASK) >> DDRPHY_PLLCR_PLLPD_SHIFT)
1088 
1089 /*
1090  * FRQSEL (R/W)
1091  *
1092  * PLL Frequency Select: Selects the operating range of the PLL. Valid values for PHYs that go up to 2133 Mbps are:
1093  * 00 = PLL reference clock (ctl_clk/REF_CLK) ranges from 335MHz to 533MHz 01 = PLL reference clock (ctl_clk/REF_CLK) ranges from 225MHz to 385MHz 10 = Reserved
1094  * 11 = PLL reference clock (ctl_clk/REF_CLK) ranges from 166MHz to 275MHz
1095  * Valid values for PHYs that don’t go up to 2133 Mbps are:
1096  * 00 = PLL reference clock (ctl_clk/REF_CLK) ranges from 250MHz to 400MHz 01 = PLL reference clock (ctl_clk/REF_CLK) ranges from 166MHz to 300MHz 10 = Reserved
1097  * 11 = Reserved
1098  */
1099 #define DDRPHY_PLLCR_FRQSEL_MASK (0xC0000UL)
1100 #define DDRPHY_PLLCR_FRQSEL_SHIFT (18U)
1101 #define DDRPHY_PLLCR_FRQSEL_SET(x) (((uint32_t)(x) << DDRPHY_PLLCR_FRQSEL_SHIFT) & DDRPHY_PLLCR_FRQSEL_MASK)
1102 #define DDRPHY_PLLCR_FRQSEL_GET(x) (((uint32_t)(x) & DDRPHY_PLLCR_FRQSEL_MASK) >> DDRPHY_PLLCR_FRQSEL_SHIFT)
1103 
1104 /*
1105  * QPMODE (R/W)
1106  *
1107  * PLL Quadrature Phase Mode: Enables, if set, the quadrature phase clock outputs. This mode is not used in this version of the PHY.
1108  */
1109 #define DDRPHY_PLLCR_QPMODE_MASK (0x20000UL)
1110 #define DDRPHY_PLLCR_QPMODE_SHIFT (17U)
1111 #define DDRPHY_PLLCR_QPMODE_SET(x) (((uint32_t)(x) << DDRPHY_PLLCR_QPMODE_SHIFT) & DDRPHY_PLLCR_QPMODE_MASK)
1112 #define DDRPHY_PLLCR_QPMODE_GET(x) (((uint32_t)(x) & DDRPHY_PLLCR_QPMODE_MASK) >> DDRPHY_PLLCR_QPMODE_SHIFT)
1113 
1114 /*
1115  * CPPC (R/W)
1116  *
1117  * Charge Pump Proportional Current Control
1118  */
1119 #define DDRPHY_PLLCR_CPPC_MASK (0x1E000UL)
1120 #define DDRPHY_PLLCR_CPPC_SHIFT (13U)
1121 #define DDRPHY_PLLCR_CPPC_SET(x) (((uint32_t)(x) << DDRPHY_PLLCR_CPPC_SHIFT) & DDRPHY_PLLCR_CPPC_MASK)
1122 #define DDRPHY_PLLCR_CPPC_GET(x) (((uint32_t)(x) & DDRPHY_PLLCR_CPPC_MASK) >> DDRPHY_PLLCR_CPPC_SHIFT)
1123 
1124 /*
1125  * CPIC (R/W)
1126  *
1127  * Charge Pump Integrating Current Control
1128  */
1129 #define DDRPHY_PLLCR_CPIC_MASK (0x1800U)
1130 #define DDRPHY_PLLCR_CPIC_SHIFT (11U)
1131 #define DDRPHY_PLLCR_CPIC_SET(x) (((uint32_t)(x) << DDRPHY_PLLCR_CPIC_SHIFT) & DDRPHY_PLLCR_CPIC_MASK)
1132 #define DDRPHY_PLLCR_CPIC_GET(x) (((uint32_t)(x) & DDRPHY_PLLCR_CPIC_MASK) >> DDRPHY_PLLCR_CPIC_SHIFT)
1133 
1134 /*
1135  * GSHIFT (R/W)
1136  *
1137  * Gear Shift: Enables, if set, rapid locking mode.
1138  */
1139 #define DDRPHY_PLLCR_GSHIFT_MASK (0x400U)
1140 #define DDRPHY_PLLCR_GSHIFT_SHIFT (10U)
1141 #define DDRPHY_PLLCR_GSHIFT_SET(x) (((uint32_t)(x) << DDRPHY_PLLCR_GSHIFT_SHIFT) & DDRPHY_PLLCR_GSHIFT_MASK)
1142 #define DDRPHY_PLLCR_GSHIFT_GET(x) (((uint32_t)(x) & DDRPHY_PLLCR_GSHIFT_MASK) >> DDRPHY_PLLCR_GSHIFT_SHIFT)
1143 
1144 /*
1145  * ATOEN (R/W)
1146  *
1147  * Analog Test Enable (ATOEN): Selects the analog test signal that is driven on the analog test output pin. Otherwise the analog test output is tri-stated. This allows analog test output pins from multiple PLLs to be connected together. Valid values are:
1148  * 0000 = All PLL analog test signals are tri-stated 0001 = AC PLL analog test signal is driven out
1149  * 0010 = DATX8 0 PLL analog test signal is driven out 0011 = DATX8 1 PLL analog test signal is driven out 0100 = DATX8 2 PLL analog test signal is driven out 0101 = DATX8 3 PLL analog test signal is driven out 0110 = DATX8 4 PLL analog test signal is driven out 0111 = DATX8 5 PLL analog test signal is driven out 1000 = DATX8 6 PLL analog test signal is driven out 1001 = DATX8 7 PLL analog test signal is driven out 1010 = DATX8 8 PLL analog test signal is driven out 1011 – 1111 = Reserved
1150  */
1151 #define DDRPHY_PLLCR_ATOEN_MASK (0x3C0U)
1152 #define DDRPHY_PLLCR_ATOEN_SHIFT (6U)
1153 #define DDRPHY_PLLCR_ATOEN_SET(x) (((uint32_t)(x) << DDRPHY_PLLCR_ATOEN_SHIFT) & DDRPHY_PLLCR_ATOEN_MASK)
1154 #define DDRPHY_PLLCR_ATOEN_GET(x) (((uint32_t)(x) & DDRPHY_PLLCR_ATOEN_MASK) >> DDRPHY_PLLCR_ATOEN_SHIFT)
1155 
1156 /*
1157  * ATC (R/W)
1158  *
1159  * Analog Test Control: Selects various PLL analog test signals to be brought out via PLL analog test output pin (pll_ato). Valid values are:
1160  * 0000 = Reserved
1161  * 0001 = vdd_ckin
1162  * 0010 = vrfbf
1163  * 0011 = vdd_cko
1164  * 0100 = vp_cp
1165  * 0101 = vpfil(vp)
1166  * 0110 = Reserved
1167  * 0111 = gd
1168  * 1000 = vcntrl_atb
1169  * 1001 = vref_atb
1170  * 1010 = vpsf_atb
1171  * 1011 – 1111 = Reserved
1172  */
1173 #define DDRPHY_PLLCR_ATC_MASK (0x3CU)
1174 #define DDRPHY_PLLCR_ATC_SHIFT (2U)
1175 #define DDRPHY_PLLCR_ATC_SET(x) (((uint32_t)(x) << DDRPHY_PLLCR_ATC_SHIFT) & DDRPHY_PLLCR_ATC_MASK)
1176 #define DDRPHY_PLLCR_ATC_GET(x) (((uint32_t)(x) & DDRPHY_PLLCR_ATC_MASK) >> DDRPHY_PLLCR_ATC_SHIFT)
1177 
1178 /*
1179  * DTC (R/W)
1180  *
1181  * Digital Test Control: Selects various PLL digital test signals and other test mode signals to be brought out via bit [1] of the PLL digital test output (pll_dto[1]). Valid values are:
1182  * 00 = ‘0’ (Test output is disabled) 01 = PLL x1 clock (X1)
1183  * 10 = PLL reference (input) clock (REF_CLK) 11 = PLL feedback clock (FB_X1)
1184  */
1185 #define DDRPHY_PLLCR_DTC_MASK (0x3U)
1186 #define DDRPHY_PLLCR_DTC_SHIFT (0U)
1187 #define DDRPHY_PLLCR_DTC_SET(x) (((uint32_t)(x) << DDRPHY_PLLCR_DTC_SHIFT) & DDRPHY_PLLCR_DTC_MASK)
1188 #define DDRPHY_PLLCR_DTC_GET(x) (((uint32_t)(x) & DDRPHY_PLLCR_DTC_MASK) >> DDRPHY_PLLCR_DTC_SHIFT)
1189 
1190 /* Bitfield definition for register: PTR0 */
1191 /*
1192  * TPLLPD (R/W)
1193  *
1194  * PLL Power-Down Time: Number of configuration or APB clock cycles that the PLL must remain in power-down mode, i.e. number of clock cycles from when PLL power-down pin is asserted to when PLL power-down pin is de-asserted. This must correspond to a value that is equal to or more than 1us. Default value corresponds to 1us.
1195  */
1196 #define DDRPHY_PTR0_TPLLPD_MASK (0xFFE00000UL)
1197 #define DDRPHY_PTR0_TPLLPD_SHIFT (21U)
1198 #define DDRPHY_PTR0_TPLLPD_SET(x) (((uint32_t)(x) << DDRPHY_PTR0_TPLLPD_SHIFT) & DDRPHY_PTR0_TPLLPD_MASK)
1199 #define DDRPHY_PTR0_TPLLPD_GET(x) (((uint32_t)(x) & DDRPHY_PTR0_TPLLPD_MASK) >> DDRPHY_PTR0_TPLLPD_SHIFT)
1200 
1201 /*
1202  * TPLLGS (R/W)
1203  *
1204  * PLL Gear Shift Time: Number of configuration or APB clock cycles from when the PLL reset pin is de-asserted to when the PLL gear shift pin is de-asserted. This must correspond to a value that is equal to or more than 4us. Default value corresponds to 4us.
1205  */
1206 #define DDRPHY_PTR0_TPLLGS_MASK (0x1FFFC0UL)
1207 #define DDRPHY_PTR0_TPLLGS_SHIFT (6U)
1208 #define DDRPHY_PTR0_TPLLGS_SET(x) (((uint32_t)(x) << DDRPHY_PTR0_TPLLGS_SHIFT) & DDRPHY_PTR0_TPLLGS_MASK)
1209 #define DDRPHY_PTR0_TPLLGS_GET(x) (((uint32_t)(x) & DDRPHY_PTR0_TPLLGS_MASK) >> DDRPHY_PTR0_TPLLGS_SHIFT)
1210 
1211 /*
1212  * TPHYRST (R/W)
1213  *
1214  * PHY Reset Time: Number of configuration or APB clock cycles that the PHY reset must remain asserted after PHY calibration is done before the reset to the PHY is de-asserted. This is used to extend the reset to the PHY so that the reset is asserted for some clock cycles after the clocks are stable. Valid values are from 1 to 63 (the value must be non-zero).
1215  */
1216 #define DDRPHY_PTR0_TPHYRST_MASK (0x3FU)
1217 #define DDRPHY_PTR0_TPHYRST_SHIFT (0U)
1218 #define DDRPHY_PTR0_TPHYRST_SET(x) (((uint32_t)(x) << DDRPHY_PTR0_TPHYRST_SHIFT) & DDRPHY_PTR0_TPHYRST_MASK)
1219 #define DDRPHY_PTR0_TPHYRST_GET(x) (((uint32_t)(x) & DDRPHY_PTR0_TPHYRST_MASK) >> DDRPHY_PTR0_TPHYRST_SHIFT)
1220 
1221 /* Bitfield definition for register: PTR1 */
1222 /*
1223  * TPLLLOCK (R/W)
1224  *
1225  * PLL Lock Time: Number of configuration or APB clock cycles for the PLL to stabilize and lock, i.e. number of clock cycles from when the PLL reset pin is de-asserted to when the PLL has lock and is ready for use. This must correspond to a value that is equal to or more than 100us. Default value corresponds to 100us.
1226  */
1227 #define DDRPHY_PTR1_TPLLLOCK_MASK (0xFFFF0000UL)
1228 #define DDRPHY_PTR1_TPLLLOCK_SHIFT (16U)
1229 #define DDRPHY_PTR1_TPLLLOCK_SET(x) (((uint32_t)(x) << DDRPHY_PTR1_TPLLLOCK_SHIFT) & DDRPHY_PTR1_TPLLLOCK_MASK)
1230 #define DDRPHY_PTR1_TPLLLOCK_GET(x) (((uint32_t)(x) & DDRPHY_PTR1_TPLLLOCK_MASK) >> DDRPHY_PTR1_TPLLLOCK_SHIFT)
1231 
1232 /*
1233  * TPLLRST (R/W)
1234  *
1235  * PLL Reset Time: Number of configuration or APB clock cycles that the PLL must remain in reset mode, i.e. number of clock cycles from when PLL power-down pin is de-asserted and PLL reset pin is asserted to when PLL reset pin is de-asserted.
1236  * The setting must correspond to a value that is equal to, or greater than, 3us.
1237  */
1238 #define DDRPHY_PTR1_TPLLRST_MASK (0x1FFFU)
1239 #define DDRPHY_PTR1_TPLLRST_SHIFT (0U)
1240 #define DDRPHY_PTR1_TPLLRST_SET(x) (((uint32_t)(x) << DDRPHY_PTR1_TPLLRST_SHIFT) & DDRPHY_PTR1_TPLLRST_MASK)
1241 #define DDRPHY_PTR1_TPLLRST_GET(x) (((uint32_t)(x) & DDRPHY_PTR1_TPLLRST_MASK) >> DDRPHY_PTR1_TPLLRST_SHIFT)
1242 
1243 /* Bitfield definition for register: PTR2 */
1244 /*
1245  * TWLDLYS (R/W)
1246  *
1247  * Write Leveling Delay Settling Time: Number of controller clock cycles from when a new value of the write leveling delay is applies to the LCDL to when to DQS high is driven high. This allows the delay to settle.
1248  */
1249 #define DDRPHY_PTR2_TWLDLYS_MASK (0xF8000UL)
1250 #define DDRPHY_PTR2_TWLDLYS_SHIFT (15U)
1251 #define DDRPHY_PTR2_TWLDLYS_SET(x) (((uint32_t)(x) << DDRPHY_PTR2_TWLDLYS_SHIFT) & DDRPHY_PTR2_TWLDLYS_MASK)
1252 #define DDRPHY_PTR2_TWLDLYS_GET(x) (((uint32_t)(x) & DDRPHY_PTR2_TWLDLYS_MASK) >> DDRPHY_PTR2_TWLDLYS_SHIFT)
1253 
1254 /*
1255  * TCALH (R/W)
1256  *
1257  * Calibration Hold Time: Number of controller clock cycles from when the clock was disabled (cal_clk_en deasserted) to when calibration is enable (cal_en asserted).
1258  */
1259 #define DDRPHY_PTR2_TCALH_MASK (0x7C00U)
1260 #define DDRPHY_PTR2_TCALH_SHIFT (10U)
1261 #define DDRPHY_PTR2_TCALH_SET(x) (((uint32_t)(x) << DDRPHY_PTR2_TCALH_SHIFT) & DDRPHY_PTR2_TCALH_MASK)
1262 #define DDRPHY_PTR2_TCALH_GET(x) (((uint32_t)(x) & DDRPHY_PTR2_TCALH_MASK) >> DDRPHY_PTR2_TCALH_SHIFT)
1263 
1264 /*
1265  * TCALS (R/W)
1266  *
1267  * Calibration Setup Time: Number of controller clock cycles from when calibration is enabled (cal_en asserted) to when the calibration clock is asserted again (cal_clk_en asserted).
1268  */
1269 #define DDRPHY_PTR2_TCALS_MASK (0x3E0U)
1270 #define DDRPHY_PTR2_TCALS_SHIFT (5U)
1271 #define DDRPHY_PTR2_TCALS_SET(x) (((uint32_t)(x) << DDRPHY_PTR2_TCALS_SHIFT) & DDRPHY_PTR2_TCALS_MASK)
1272 #define DDRPHY_PTR2_TCALS_GET(x) (((uint32_t)(x) & DDRPHY_PTR2_TCALS_MASK) >> DDRPHY_PTR2_TCALS_SHIFT)
1273 
1274 /*
1275  * TCALON (R/W)
1276  *
1277  * Calibration On Time: Number of clock cycles that the calibration clock is enabled (cal_clk_en asserted).
1278  */
1279 #define DDRPHY_PTR2_TCALON_MASK (0x1FU)
1280 #define DDRPHY_PTR2_TCALON_SHIFT (0U)
1281 #define DDRPHY_PTR2_TCALON_SET(x) (((uint32_t)(x) << DDRPHY_PTR2_TCALON_SHIFT) & DDRPHY_PTR2_TCALON_MASK)
1282 #define DDRPHY_PTR2_TCALON_GET(x) (((uint32_t)(x) & DDRPHY_PTR2_TCALON_MASK) >> DDRPHY_PTR2_TCALON_SHIFT)
1283 
1284 /* Bitfield definition for register: PTR3 */
1285 /*
1286  * TDINIT1 (R/W)
1287  *
1288  * DRAM Initialization Time 1: DRAM initialization time in DRAM clock cycles corresponding to the following:
1289  * DDR3 = CKE high time to first command (tRFC + 10 ns or 5 tCK, whichever is bigger) DDR2 = CKE high time to first command (400 ns)
1290  * Default value corresponds to DDR3 tRFC of 360ns at 1066 MHz.
1291  */
1292 #define DDRPHY_PTR3_TDINIT1_MASK (0x1FF00000UL)
1293 #define DDRPHY_PTR3_TDINIT1_SHIFT (20U)
1294 #define DDRPHY_PTR3_TDINIT1_SET(x) (((uint32_t)(x) << DDRPHY_PTR3_TDINIT1_SHIFT) & DDRPHY_PTR3_TDINIT1_MASK)
1295 #define DDRPHY_PTR3_TDINIT1_GET(x) (((uint32_t)(x) & DDRPHY_PTR3_TDINIT1_MASK) >> DDRPHY_PTR3_TDINIT1_SHIFT)
1296 
1297 /*
1298  * TDINIT0 (R/W)
1299  *
1300  * DRAM Initialization Time 0: DRAM initialization time in DRAM clock cycles corresponding to the following:
1301  * DDR3 = CKE low time with power and clock stable (500 us) DDR2 = CKE low time with power and clock stable (200 us) Default value corresponds to DDR3 500 us at 1066 MHz.
1302  * During Verilog simulations, it is recommended that this value is changed to a much smaller value in order to avoid long simulation times. However, this may cause a memory model error, due to a violation of the CKE setup sequence. This violation is expected if this value is not programmed to the required SDRAM CKE low time, but memory models should be able to tolerate this violation without malfunction of the model.
1303  */
1304 #define DDRPHY_PTR3_TDINIT0_MASK (0xFFFFFUL)
1305 #define DDRPHY_PTR3_TDINIT0_SHIFT (0U)
1306 #define DDRPHY_PTR3_TDINIT0_SET(x) (((uint32_t)(x) << DDRPHY_PTR3_TDINIT0_SHIFT) & DDRPHY_PTR3_TDINIT0_MASK)
1307 #define DDRPHY_PTR3_TDINIT0_GET(x) (((uint32_t)(x) & DDRPHY_PTR3_TDINIT0_MASK) >> DDRPHY_PTR3_TDINIT0_SHIFT)
1308 
1309 /* Bitfield definition for register: PTR4 */
1310 /*
1311  * TDINIT3 (R/W)
1312  *
1313  * DRAM Initialization Time 3: DRAM initialization time in DRAM clock cycles corresponding to the following:
1314  * DDR3 = Time from ZQ initialization command to first command (1 us) Default value corresponds to the DDR3 640ns at 1066 MHz.
1315  */
1316 #define DDRPHY_PTR4_TDINIT3_MASK (0xFFC0000UL)
1317 #define DDRPHY_PTR4_TDINIT3_SHIFT (18U)
1318 #define DDRPHY_PTR4_TDINIT3_SET(x) (((uint32_t)(x) << DDRPHY_PTR4_TDINIT3_SHIFT) & DDRPHY_PTR4_TDINIT3_MASK)
1319 #define DDRPHY_PTR4_TDINIT3_GET(x) (((uint32_t)(x) & DDRPHY_PTR4_TDINIT3_MASK) >> DDRPHY_PTR4_TDINIT3_SHIFT)
1320 
1321 /*
1322  * TDINIT2 (R/W)
1323  *
1324  * DRAM Initialization Time 2: DRAM initialization time in DRAM clock cycles corresponding to the following:
1325  * DDR3 = Reset low time (200 us on power-up or 100 ns after power-up) Default value corresponds to DDR3 200 us at 1066 MHz.
1326  */
1327 #define DDRPHY_PTR4_TDINIT2_MASK (0x3FFFFUL)
1328 #define DDRPHY_PTR4_TDINIT2_SHIFT (0U)
1329 #define DDRPHY_PTR4_TDINIT2_SET(x) (((uint32_t)(x) << DDRPHY_PTR4_TDINIT2_SHIFT) & DDRPHY_PTR4_TDINIT2_MASK)
1330 #define DDRPHY_PTR4_TDINIT2_GET(x) (((uint32_t)(x) & DDRPHY_PTR4_TDINIT2_MASK) >> DDRPHY_PTR4_TDINIT2_SHIFT)
1331 
1332 /* Bitfield definition for register: ACMDLR */
1333 /*
1334  * MDLD (R/W)
1335  *
1336  * MDL Delay: Delay select for the LCDL for the Master Delay Line.
1337  */
1338 #define DDRPHY_ACMDLR_MDLD_MASK (0xFF0000UL)
1339 #define DDRPHY_ACMDLR_MDLD_SHIFT (16U)
1340 #define DDRPHY_ACMDLR_MDLD_SET(x) (((uint32_t)(x) << DDRPHY_ACMDLR_MDLD_SHIFT) & DDRPHY_ACMDLR_MDLD_MASK)
1341 #define DDRPHY_ACMDLR_MDLD_GET(x) (((uint32_t)(x) & DDRPHY_ACMDLR_MDLD_MASK) >> DDRPHY_ACMDLR_MDLD_SHIFT)
1342 
1343 /*
1344  * TPRD (R/W)
1345  *
1346  * Target Period: Target period measured by the master delay line calibration for VT drift compensation. This is the current measured value of the period and is continuously updated if the MDL is enabled to do so.
1347  */
1348 #define DDRPHY_ACMDLR_TPRD_MASK (0xFF00U)
1349 #define DDRPHY_ACMDLR_TPRD_SHIFT (8U)
1350 #define DDRPHY_ACMDLR_TPRD_SET(x) (((uint32_t)(x) << DDRPHY_ACMDLR_TPRD_SHIFT) & DDRPHY_ACMDLR_TPRD_MASK)
1351 #define DDRPHY_ACMDLR_TPRD_GET(x) (((uint32_t)(x) & DDRPHY_ACMDLR_TPRD_MASK) >> DDRPHY_ACMDLR_TPRD_SHIFT)
1352 
1353 /*
1354  * IPRD (R/W)
1355  *
1356  * Initial Period: Initial period measured by the master delay line calibration for VT drift compensation. This value is used as the denominator when calculating the ratios of updates during VT compensation.
1357  */
1358 #define DDRPHY_ACMDLR_IPRD_MASK (0xFFU)
1359 #define DDRPHY_ACMDLR_IPRD_SHIFT (0U)
1360 #define DDRPHY_ACMDLR_IPRD_SET(x) (((uint32_t)(x) << DDRPHY_ACMDLR_IPRD_SHIFT) & DDRPHY_ACMDLR_IPRD_MASK)
1361 #define DDRPHY_ACMDLR_IPRD_GET(x) (((uint32_t)(x) & DDRPHY_ACMDLR_IPRD_MASK) >> DDRPHY_ACMDLR_IPRD_SHIFT)
1362 
1363 /* Bitfield definition for register: ACBDLR */
1364 /*
1365  * ACBD (R/W)
1366  *
1367  * Address/Command Bit Delay: Delay select for the BDLs on address and command signals.
1368  */
1369 #define DDRPHY_ACBDLR_ACBD_MASK (0xFC0000UL)
1370 #define DDRPHY_ACBDLR_ACBD_SHIFT (18U)
1371 #define DDRPHY_ACBDLR_ACBD_SET(x) (((uint32_t)(x) << DDRPHY_ACBDLR_ACBD_SHIFT) & DDRPHY_ACBDLR_ACBD_MASK)
1372 #define DDRPHY_ACBDLR_ACBD_GET(x) (((uint32_t)(x) & DDRPHY_ACBDLR_ACBD_MASK) >> DDRPHY_ACBDLR_ACBD_SHIFT)
1373 
1374 /*
1375  * CK2BD (R/W)
1376  *
1377  * CK2 Bit Delay: Delay select for the BDL on CK2.
1378  */
1379 #define DDRPHY_ACBDLR_CK2BD_MASK (0x3F000UL)
1380 #define DDRPHY_ACBDLR_CK2BD_SHIFT (12U)
1381 #define DDRPHY_ACBDLR_CK2BD_SET(x) (((uint32_t)(x) << DDRPHY_ACBDLR_CK2BD_SHIFT) & DDRPHY_ACBDLR_CK2BD_MASK)
1382 #define DDRPHY_ACBDLR_CK2BD_GET(x) (((uint32_t)(x) & DDRPHY_ACBDLR_CK2BD_MASK) >> DDRPHY_ACBDLR_CK2BD_SHIFT)
1383 
1384 /*
1385  * CK1BD (R/W)
1386  *
1387  * CK1 Bit Delay: Delay select for the BDL on CK1.
1388  */
1389 #define DDRPHY_ACBDLR_CK1BD_MASK (0xFC0U)
1390 #define DDRPHY_ACBDLR_CK1BD_SHIFT (6U)
1391 #define DDRPHY_ACBDLR_CK1BD_SET(x) (((uint32_t)(x) << DDRPHY_ACBDLR_CK1BD_SHIFT) & DDRPHY_ACBDLR_CK1BD_MASK)
1392 #define DDRPHY_ACBDLR_CK1BD_GET(x) (((uint32_t)(x) & DDRPHY_ACBDLR_CK1BD_MASK) >> DDRPHY_ACBDLR_CK1BD_SHIFT)
1393 
1394 /*
1395  * CK0BD (R/W)
1396  *
1397  * CK0 Bit Delay: Delay select for the BDL on CK0.
1398  */
1399 #define DDRPHY_ACBDLR_CK0BD_MASK (0x3FU)
1400 #define DDRPHY_ACBDLR_CK0BD_SHIFT (0U)
1401 #define DDRPHY_ACBDLR_CK0BD_SET(x) (((uint32_t)(x) << DDRPHY_ACBDLR_CK0BD_SHIFT) & DDRPHY_ACBDLR_CK0BD_MASK)
1402 #define DDRPHY_ACBDLR_CK0BD_GET(x) (((uint32_t)(x) & DDRPHY_ACBDLR_CK0BD_MASK) >> DDRPHY_ACBDLR_CK0BD_SHIFT)
1403 
1404 /* Bitfield definition for register: ACIOCR */
1405 /*
1406  * ACSR (R/W)
1407  *
1408  * Address/Command Slew Rate (D3F I/O Only): Selects slew rate of the I/O for all address and command pins.
1409  */
1410 #define DDRPHY_ACIOCR_ACSR_MASK (0xC0000000UL)
1411 #define DDRPHY_ACIOCR_ACSR_SHIFT (30U)
1412 #define DDRPHY_ACIOCR_ACSR_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_ACSR_SHIFT) & DDRPHY_ACIOCR_ACSR_MASK)
1413 #define DDRPHY_ACIOCR_ACSR_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_ACSR_MASK) >> DDRPHY_ACIOCR_ACSR_SHIFT)
1414 
1415 /*
1416  * RSTIOM (R/W)
1417  *
1418  * SDRAM Reset I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for SDRAM Reset.
1419  */
1420 #define DDRPHY_ACIOCR_RSTIOM_MASK (0x20000000UL)
1421 #define DDRPHY_ACIOCR_RSTIOM_SHIFT (29U)
1422 #define DDRPHY_ACIOCR_RSTIOM_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_RSTIOM_SHIFT) & DDRPHY_ACIOCR_RSTIOM_MASK)
1423 #define DDRPHY_ACIOCR_RSTIOM_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_RSTIOM_MASK) >> DDRPHY_ACIOCR_RSTIOM_SHIFT)
1424 
1425 /*
1426  * RSTPDR (R/W)
1427  *
1428  * SDRAM Reset Power Down Receiver: Powers down, when set, the input receiver on the I/O for SDRAM RST# pin.
1429  */
1430 #define DDRPHY_ACIOCR_RSTPDR_MASK (0x10000000UL)
1431 #define DDRPHY_ACIOCR_RSTPDR_SHIFT (28U)
1432 #define DDRPHY_ACIOCR_RSTPDR_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_RSTPDR_SHIFT) & DDRPHY_ACIOCR_RSTPDR_MASK)
1433 #define DDRPHY_ACIOCR_RSTPDR_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_RSTPDR_MASK) >> DDRPHY_ACIOCR_RSTPDR_SHIFT)
1434 
1435 /*
1436  * RSTPDD1 (R/W)
1437  *
1438  * SDRAM Reset Power Down Driver: Powers down, when set, the output driver on the I/O for SDRAM RST# pin.
1439  */
1440 #define DDRPHY_ACIOCR_RSTPDD1_MASK (0x8000000UL)
1441 #define DDRPHY_ACIOCR_RSTPDD1_SHIFT (27U)
1442 #define DDRPHY_ACIOCR_RSTPDD1_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_RSTPDD1_SHIFT) & DDRPHY_ACIOCR_RSTPDD1_MASK)
1443 #define DDRPHY_ACIOCR_RSTPDD1_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_RSTPDD1_MASK) >> DDRPHY_ACIOCR_RSTPDD1_SHIFT)
1444 
1445 /*
1446  * RSTODT (R/W)
1447  *
1448  * SDRAM Reset On-Die Termination: Enables, when set, the on-die termination on the I/O for SDRAM RST# pin.
1449  */
1450 #define DDRPHY_ACIOCR_RSTODT_MASK (0x4000000UL)
1451 #define DDRPHY_ACIOCR_RSTODT_SHIFT (26U)
1452 #define DDRPHY_ACIOCR_RSTODT_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_RSTODT_SHIFT) & DDRPHY_ACIOCR_RSTODT_MASK)
1453 #define DDRPHY_ACIOCR_RSTODT_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_RSTODT_MASK) >> DDRPHY_ACIOCR_RSTODT_SHIFT)
1454 
1455 /*
1456  * RANKPDR (R/W)
1457  *
1458  * Rank Power Down Receiver: Powers down, when set, the input receiver on the I/O CKE[3:0], ODT[3:0], and CS#[3:0] pins. RANKPDR[0] controls the power down for CKE[0], ODT[0], and CS#[0], RANKPDR[1] controls the power down for CKE[1], ODT[1], and CS#[1], and so on.
1459  */
1460 #define DDRPHY_ACIOCR_RANKPDR_MASK (0x3C00000UL)
1461 #define DDRPHY_ACIOCR_RANKPDR_SHIFT (22U)
1462 #define DDRPHY_ACIOCR_RANKPDR_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_RANKPDR_SHIFT) & DDRPHY_ACIOCR_RANKPDR_MASK)
1463 #define DDRPHY_ACIOCR_RANKPDR_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_RANKPDR_MASK) >> DDRPHY_ACIOCR_RANKPDR_SHIFT)
1464 
1465 /*
1466  * CSPDD1 (R/W)
1467  *
1468  * CS# Power Down Driver: Powers down, when set, the output driver on the I/O for CS#[3:0] pins. CSPDD[0] controls the power down for CS#[0], CSPDD[1] controls the power down for CS#[1], and so on. CKE and ODT driver power down is controlled by DSGCR register.
1469  */
1470 #define DDRPHY_ACIOCR_CSPDD1_MASK (0x3C0000UL)
1471 #define DDRPHY_ACIOCR_CSPDD1_SHIFT (18U)
1472 #define DDRPHY_ACIOCR_CSPDD1_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_CSPDD1_SHIFT) & DDRPHY_ACIOCR_CSPDD1_MASK)
1473 #define DDRPHY_ACIOCR_CSPDD1_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_CSPDD1_MASK) >> DDRPHY_ACIOCR_CSPDD1_SHIFT)
1474 
1475 /*
1476  * RANKODT (R/W)
1477  *
1478  * Rank On-Die Termination: Enables, when set, the on-die termination on the I/O for CKE[3:0], ODT[3:0], and CS#[3:0] pins. RANKODT[0] controls the on-die termination for CKE[0], ODT[0], and CS#[0], RANKODT[1] controls the on-die termination for CKE[1], ODT[1], and CS#[1], and so on.
1479  */
1480 #define DDRPHY_ACIOCR_RANKODT_MASK (0x3C000UL)
1481 #define DDRPHY_ACIOCR_RANKODT_SHIFT (14U)
1482 #define DDRPHY_ACIOCR_RANKODT_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_RANKODT_SHIFT) & DDRPHY_ACIOCR_RANKODT_MASK)
1483 #define DDRPHY_ACIOCR_RANKODT_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_RANKODT_MASK) >> DDRPHY_ACIOCR_RANKODT_SHIFT)
1484 
1485 /*
1486  * CKPDR (R/W)
1487  *
1488  * CK Power Down Receiver: Powers down, when set, the input receiver on the I/O for CK[0], CK[1], and CK[2] pins, respectively.
1489  */
1490 #define DDRPHY_ACIOCR_CKPDR_MASK (0x3800U)
1491 #define DDRPHY_ACIOCR_CKPDR_SHIFT (11U)
1492 #define DDRPHY_ACIOCR_CKPDR_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_CKPDR_SHIFT) & DDRPHY_ACIOCR_CKPDR_MASK)
1493 #define DDRPHY_ACIOCR_CKPDR_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_CKPDR_MASK) >> DDRPHY_ACIOCR_CKPDR_SHIFT)
1494 
1495 /*
1496  * CKPDD1 (R/W)
1497  *
1498  * CK Power Down Driver: Powers down, when set, the output driver on the I/O for CK[0], CK[1], and CK[2] pins, respectively.
1499  */
1500 #define DDRPHY_ACIOCR_CKPDD1_MASK (0x700U)
1501 #define DDRPHY_ACIOCR_CKPDD1_SHIFT (8U)
1502 #define DDRPHY_ACIOCR_CKPDD1_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_CKPDD1_SHIFT) & DDRPHY_ACIOCR_CKPDD1_MASK)
1503 #define DDRPHY_ACIOCR_CKPDD1_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_CKPDD1_MASK) >> DDRPHY_ACIOCR_CKPDD1_SHIFT)
1504 
1505 /*
1506  * CKODT (R/W)
1507  *
1508  * CK On-Die Termination: Enables, when set, the on-die termination on the I/O for CK[0], CK[1], and CK[2] pins, respectively.
1509  */
1510 #define DDRPHY_ACIOCR_CKODT_MASK (0xE0U)
1511 #define DDRPHY_ACIOCR_CKODT_SHIFT (5U)
1512 #define DDRPHY_ACIOCR_CKODT_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_CKODT_SHIFT) & DDRPHY_ACIOCR_CKODT_MASK)
1513 #define DDRPHY_ACIOCR_CKODT_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_CKODT_MASK) >> DDRPHY_ACIOCR_CKODT_SHIFT)
1514 
1515 /*
1516  * ACPDR (R/W)
1517  *
1518  * AC Power Down Receiver: Powers down, when set, the input receiver on the I/O for RAS#, CAS#, WE#, BA[2:0], and A[15:0] pins.
1519  */
1520 #define DDRPHY_ACIOCR_ACPDR_MASK (0x10U)
1521 #define DDRPHY_ACIOCR_ACPDR_SHIFT (4U)
1522 #define DDRPHY_ACIOCR_ACPDR_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_ACPDR_SHIFT) & DDRPHY_ACIOCR_ACPDR_MASK)
1523 #define DDRPHY_ACIOCR_ACPDR_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_ACPDR_MASK) >> DDRPHY_ACIOCR_ACPDR_SHIFT)
1524 
1525 /*
1526  * ACPDD1 (R/W)
1527  *
1528  * AC Power Down Driver: Powers down, when set, the output driver on the I/O for RAS#, CAS#, WE#, BA[2:0], and A[15:0] pins.
1529  */
1530 #define DDRPHY_ACIOCR_ACPDD1_MASK (0x8U)
1531 #define DDRPHY_ACIOCR_ACPDD1_SHIFT (3U)
1532 #define DDRPHY_ACIOCR_ACPDD1_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_ACPDD1_SHIFT) & DDRPHY_ACIOCR_ACPDD1_MASK)
1533 #define DDRPHY_ACIOCR_ACPDD1_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_ACPDD1_MASK) >> DDRPHY_ACIOCR_ACPDD1_SHIFT)
1534 
1535 /*
1536  * ACODT (R/W)
1537  *
1538  * Address/Command On-Die Termination: Enables, when set, the on-die termination on the I/O for RAS#, CAS#, WE#, BA[2:0], and A[15:0] pins.
1539  */
1540 #define DDRPHY_ACIOCR_ACODT_MASK (0x4U)
1541 #define DDRPHY_ACIOCR_ACODT_SHIFT (2U)
1542 #define DDRPHY_ACIOCR_ACODT_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_ACODT_SHIFT) & DDRPHY_ACIOCR_ACODT_MASK)
1543 #define DDRPHY_ACIOCR_ACODT_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_ACODT_MASK) >> DDRPHY_ACIOCR_ACODT_SHIFT)
1544 
1545 /*
1546  * ACOE (R/W)
1547  *
1548  * Address/Command Output Enable: Enables, when set, the output driver on the I/O for all address and command pins.
1549  */
1550 #define DDRPHY_ACIOCR_ACOE_MASK (0x2U)
1551 #define DDRPHY_ACIOCR_ACOE_SHIFT (1U)
1552 #define DDRPHY_ACIOCR_ACOE_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_ACOE_SHIFT) & DDRPHY_ACIOCR_ACOE_MASK)
1553 #define DDRPHY_ACIOCR_ACOE_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_ACOE_MASK) >> DDRPHY_ACIOCR_ACOE_SHIFT)
1554 
1555 /*
1556  * ACIOM (R/W)
1557  *
1558  * Address/Command I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for all address and command pins. This bit connects to bit
1559  * [0] of the IOM pin on the D3F I/Os, and for other I/O libraries, it connects to the IOM pin of the I/O.
1560  */
1561 #define DDRPHY_ACIOCR_ACIOM_MASK (0x1U)
1562 #define DDRPHY_ACIOCR_ACIOM_SHIFT (0U)
1563 #define DDRPHY_ACIOCR_ACIOM_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_ACIOM_SHIFT) & DDRPHY_ACIOCR_ACIOM_MASK)
1564 #define DDRPHY_ACIOCR_ACIOM_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_ACIOM_MASK) >> DDRPHY_ACIOCR_ACIOM_SHIFT)
1565 
1566 /* Bitfield definition for register: DXCCR */
1567 /*
1568  * DDPDRCDO (R/W)
1569  *
1570  * Dynamic Data Power Down Receiver Count Down Offset: Offset applied in calculating window of time where receiver is powered up
1571  */
1572 #define DDRPHY_DXCCR_DDPDRCDO_MASK (0xF0000000UL)
1573 #define DDRPHY_DXCCR_DDPDRCDO_SHIFT (28U)
1574 #define DDRPHY_DXCCR_DDPDRCDO_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_DDPDRCDO_SHIFT) & DDRPHY_DXCCR_DDPDRCDO_MASK)
1575 #define DDRPHY_DXCCR_DDPDRCDO_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_DDPDRCDO_MASK) >> DDRPHY_DXCCR_DDPDRCDO_SHIFT)
1576 
1577 /*
1578  * DDPDDCDO (R/W)
1579  *
1580  * Dynamic Data Power Down Driver Count Down Offset: Offset applied in calculating window of time where driver is powered up
1581  */
1582 #define DDRPHY_DXCCR_DDPDDCDO_MASK (0xF000000UL)
1583 #define DDRPHY_DXCCR_DDPDDCDO_SHIFT (24U)
1584 #define DDRPHY_DXCCR_DDPDDCDO_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_DDPDDCDO_SHIFT) & DDRPHY_DXCCR_DDPDDCDO_MASK)
1585 #define DDRPHY_DXCCR_DDPDDCDO_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_DDPDDCDO_MASK) >> DDRPHY_DXCCR_DDPDDCDO_SHIFT)
1586 
1587 /*
1588  * DYNDXPDR (R/W)
1589  *
1590  * Data Power Down Receiver: Dynamically powers down, when set, the input receiver on I/O for the DQ pins of the active DATX8 macros. Applies only when DXPDR and DXnGCR.DXPDR are not set to 1. Receiver is powered-up on a DFI READ command and powered-down (trddata_en + fixed_read_latency + n) HDR cycles after the last DFI READ command. Note that n is defined by the register bit field DXCCR[31:28] (DDPDRCDO).
1591  */
1592 #define DDRPHY_DXCCR_DYNDXPDR_MASK (0x800000UL)
1593 #define DDRPHY_DXCCR_DYNDXPDR_SHIFT (23U)
1594 #define DDRPHY_DXCCR_DYNDXPDR_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_DYNDXPDR_SHIFT) & DDRPHY_DXCCR_DYNDXPDR_MASK)
1595 #define DDRPHY_DXCCR_DYNDXPDR_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_DYNDXPDR_MASK) >> DDRPHY_DXCCR_DYNDXPDR_SHIFT)
1596 
1597 /*
1598  * DYNDXPDD1 (R/W)
1599  *
1600  * Dynamic Data Power Down Driver: Dynamically powers down, when set, the output driver on I/O for the DQ pins of the active DATX8 macros. Applies only when DXPDD and DXnGCR.DXPDD are not set to 1. Driver is powered-up on a DFI WRITE command and powered-down (twrlat + WL/2 + n) HDR cycles after the last DFI WRITE command. Note that n is defined by the register bit field DXCCR[27:24] (DDPDDCDO).
1601  */
1602 #define DDRPHY_DXCCR_DYNDXPDD1_MASK (0x400000UL)
1603 #define DDRPHY_DXCCR_DYNDXPDD1_SHIFT (22U)
1604 #define DDRPHY_DXCCR_DYNDXPDD1_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_DYNDXPDD1_SHIFT) & DDRPHY_DXCCR_DYNDXPDD1_MASK)
1605 #define DDRPHY_DXCCR_DYNDXPDD1_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_DYNDXPDD1_MASK) >> DDRPHY_DXCCR_DYNDXPDD1_SHIFT)
1606 
1607 /*
1608  * UDQIOM (R/W)
1609  *
1610  * Unused DQ I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for unused DQ pins.
1611  */
1612 #define DDRPHY_DXCCR_UDQIOM_MASK (0x200000UL)
1613 #define DDRPHY_DXCCR_UDQIOM_SHIFT (21U)
1614 #define DDRPHY_DXCCR_UDQIOM_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_UDQIOM_SHIFT) & DDRPHY_DXCCR_UDQIOM_MASK)
1615 #define DDRPHY_DXCCR_UDQIOM_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_UDQIOM_MASK) >> DDRPHY_DXCCR_UDQIOM_SHIFT)
1616 
1617 /*
1618  * UDQPDR (R/W)
1619  *
1620  * Unused DQ Power Down Receiver: Powers down, when set, the input receiver on the I/O for unused DQ pins.
1621  */
1622 #define DDRPHY_DXCCR_UDQPDR_MASK (0x100000UL)
1623 #define DDRPHY_DXCCR_UDQPDR_SHIFT (20U)
1624 #define DDRPHY_DXCCR_UDQPDR_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_UDQPDR_SHIFT) & DDRPHY_DXCCR_UDQPDR_MASK)
1625 #define DDRPHY_DXCCR_UDQPDR_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_UDQPDR_MASK) >> DDRPHY_DXCCR_UDQPDR_SHIFT)
1626 
1627 /*
1628  * UDQPDD1 (R/W)
1629  *
1630  * Unused DQ Power Down Driver: Powers down, when set, the output driver on the I/O for unused DQ pins.
1631  */
1632 #define DDRPHY_DXCCR_UDQPDD1_MASK (0x80000UL)
1633 #define DDRPHY_DXCCR_UDQPDD1_SHIFT (19U)
1634 #define DDRPHY_DXCCR_UDQPDD1_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_UDQPDD1_SHIFT) & DDRPHY_DXCCR_UDQPDD1_MASK)
1635 #define DDRPHY_DXCCR_UDQPDD1_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_UDQPDD1_MASK) >> DDRPHY_DXCCR_UDQPDD1_SHIFT)
1636 
1637 /*
1638  * UDQODT (R/W)
1639  *
1640  * Unused DQ On-Die Termination: Enables, when set, the on-die termination on the I/O for unused DQ pins.
1641  */
1642 #define DDRPHY_DXCCR_UDQODT_MASK (0x40000UL)
1643 #define DDRPHY_DXCCR_UDQODT_SHIFT (18U)
1644 #define DDRPHY_DXCCR_UDQODT_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_UDQODT_SHIFT) & DDRPHY_DXCCR_UDQODT_MASK)
1645 #define DDRPHY_DXCCR_UDQODT_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_UDQODT_MASK) >> DDRPHY_DXCCR_UDQODT_SHIFT)
1646 
1647 /*
1648  * MSBUDQ (R/W)
1649  *
1650  * Most Significant Byte Unused DQs: Specifies the number of DQ bits that are not used in the most significant byte. The used (valid) bits for this byte are [8-MSBDQ- 1:0]. To disable the whole byte, use the DXnGCR.DXEN register.
1651  */
1652 #define DDRPHY_DXCCR_MSBUDQ_MASK (0x38000UL)
1653 #define DDRPHY_DXCCR_MSBUDQ_SHIFT (15U)
1654 #define DDRPHY_DXCCR_MSBUDQ_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_MSBUDQ_SHIFT) & DDRPHY_DXCCR_MSBUDQ_MASK)
1655 #define DDRPHY_DXCCR_MSBUDQ_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_MSBUDQ_MASK) >> DDRPHY_DXCCR_MSBUDQ_SHIFT)
1656 
1657 /*
1658  * DXSR (R/W)
1659  *
1660  * Data Slew Rate (D3F I/O Only): Selects slew rate of the I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros.
1661  */
1662 #define DDRPHY_DXCCR_DXSR_MASK (0x6000U)
1663 #define DDRPHY_DXCCR_DXSR_SHIFT (13U)
1664 #define DDRPHY_DXCCR_DXSR_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_DXSR_SHIFT) & DDRPHY_DXCCR_DXSR_MASK)
1665 #define DDRPHY_DXCCR_DXSR_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_DXSR_MASK) >> DDRPHY_DXCCR_DXSR_SHIFT)
1666 
1667 /*
1668  * DQSNRES (R/W)
1669  *
1670  * DQS# Resistor: Selects the on-die pull-up/pull-down resistor for DQS# pins. Same encoding as DQSRES.
1671  * Refer PHY databook for pull-down/pull-up resistor values (RA_SEL/RB_SEL) for DQS/DQS_b.
1672  */
1673 #define DDRPHY_DXCCR_DQSNRES_MASK (0x1E00U)
1674 #define DDRPHY_DXCCR_DQSNRES_SHIFT (9U)
1675 #define DDRPHY_DXCCR_DQSNRES_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_DQSNRES_SHIFT) & DDRPHY_DXCCR_DQSNRES_MASK)
1676 #define DDRPHY_DXCCR_DQSNRES_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_DQSNRES_MASK) >> DDRPHY_DXCCR_DQSNRES_SHIFT)
1677 
1678 /*
1679  * DQSRES (R/W)
1680  *
1681  * DQS Resistor: Selects the on-die pull-down/pull-up resistor for DQS pins. DQSRES[3] selects pull-down (when set to 0) or pull-up (when set to 1). DQSRES[2:0] selects the resistor value.
1682  * Refer PHY databook for pull-down/pull-up resistor values (RA_SEL/RB_SEL) for DQS/DQS_b.
1683  */
1684 #define DDRPHY_DXCCR_DQSRES_MASK (0x1E0U)
1685 #define DDRPHY_DXCCR_DQSRES_SHIFT (5U)
1686 #define DDRPHY_DXCCR_DQSRES_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_DQSRES_SHIFT) & DDRPHY_DXCCR_DQSRES_MASK)
1687 #define DDRPHY_DXCCR_DQSRES_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_DQSRES_MASK) >> DDRPHY_DXCCR_DQSRES_SHIFT)
1688 
1689 /*
1690  * DXPDR (R/W)
1691  *
1692  * Data Power Down Receiver: Powers down, when set, the input receiver on I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros. This bit is ORed with the PDR configuration bit of the individual DATX8.
1693  */
1694 #define DDRPHY_DXCCR_DXPDR_MASK (0x10U)
1695 #define DDRPHY_DXCCR_DXPDR_SHIFT (4U)
1696 #define DDRPHY_DXCCR_DXPDR_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_DXPDR_SHIFT) & DDRPHY_DXCCR_DXPDR_MASK)
1697 #define DDRPHY_DXCCR_DXPDR_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_DXPDR_MASK) >> DDRPHY_DXCCR_DXPDR_SHIFT)
1698 
1699 /*
1700  * DXPDD1 (R/W)
1701  *
1702  * Data Power Down Driver: Powers down, when set, the output driver on I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros. This bit is ORed with the PDD configuration bit of the individual DATX8.
1703  */
1704 #define DDRPHY_DXCCR_DXPDD1_MASK (0x8U)
1705 #define DDRPHY_DXCCR_DXPDD1_SHIFT (3U)
1706 #define DDRPHY_DXCCR_DXPDD1_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_DXPDD1_SHIFT) & DDRPHY_DXCCR_DXPDD1_MASK)
1707 #define DDRPHY_DXCCR_DXPDD1_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_DXPDD1_MASK) >> DDRPHY_DXCCR_DXPDD1_SHIFT)
1708 
1709 /*
1710  * MDLEN (R/W)
1711  *
1712  * Master Delay Line Enable: Enables, if set, all DATX8 master delay line calibration to perform subsequent period measurements following the initial period measurements that are performed after reset or on when calibration is manually triggered. These additional measurements are accumulated and filtered as long as this bit remains high. This bit is ANDed with the MDLEN bit in the individual DATX8.
1713  */
1714 #define DDRPHY_DXCCR_MDLEN_MASK (0x4U)
1715 #define DDRPHY_DXCCR_MDLEN_SHIFT (2U)
1716 #define DDRPHY_DXCCR_MDLEN_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_MDLEN_SHIFT) & DDRPHY_DXCCR_MDLEN_MASK)
1717 #define DDRPHY_DXCCR_MDLEN_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_MDLEN_MASK) >> DDRPHY_DXCCR_MDLEN_SHIFT)
1718 
1719 /*
1720  * DXIOM (R/W)
1721  *
1722  * Data I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros. This bit is ORed with the IOM configuration bit of the individual DATX8.
1723  */
1724 #define DDRPHY_DXCCR_DXIOM_MASK (0x2U)
1725 #define DDRPHY_DXCCR_DXIOM_SHIFT (1U)
1726 #define DDRPHY_DXCCR_DXIOM_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_DXIOM_SHIFT) & DDRPHY_DXCCR_DXIOM_MASK)
1727 #define DDRPHY_DXCCR_DXIOM_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_DXIOM_MASK) >> DDRPHY_DXCCR_DXIOM_SHIFT)
1728 
1729 /*
1730  * DXODT (R/W)
1731  *
1732  * Data On-Die Termination: Enables, when set, the on-die termination on the I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros. This bit is ORed with the ODT configuration bit of the individual DATX8 (“DATX8 General Configuration Register (DXnGCR)” on page 148)
1733  */
1734 #define DDRPHY_DXCCR_DXODT_MASK (0x1U)
1735 #define DDRPHY_DXCCR_DXODT_SHIFT (0U)
1736 #define DDRPHY_DXCCR_DXODT_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_DXODT_SHIFT) & DDRPHY_DXCCR_DXODT_MASK)
1737 #define DDRPHY_DXCCR_DXODT_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_DXODT_MASK) >> DDRPHY_DXCCR_DXODT_SHIFT)
1738 
1739 /* Bitfield definition for register: DSGCR */
1740 /*
1741  * CKEOE (R/W)
1742  *
1743  * SDRAM CKE Output Enable: Enables, when set, the output driver on the I/O for SDRAM CKE pins.
1744  */
1745 #define DDRPHY_DSGCR_CKEOE_MASK (0x80000000UL)
1746 #define DDRPHY_DSGCR_CKEOE_SHIFT (31U)
1747 #define DDRPHY_DSGCR_CKEOE_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_CKEOE_SHIFT) & DDRPHY_DSGCR_CKEOE_MASK)
1748 #define DDRPHY_DSGCR_CKEOE_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_CKEOE_MASK) >> DDRPHY_DSGCR_CKEOE_SHIFT)
1749 
1750 /*
1751  * RSTOE (R/W)
1752  *
1753  * SDRAM Reset Output Enable: Enables, when set, the output driver on the I/O for SDRAM RST# pin.
1754  */
1755 #define DDRPHY_DSGCR_RSTOE_MASK (0x40000000UL)
1756 #define DDRPHY_DSGCR_RSTOE_SHIFT (30U)
1757 #define DDRPHY_DSGCR_RSTOE_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_RSTOE_SHIFT) & DDRPHY_DSGCR_RSTOE_MASK)
1758 #define DDRPHY_DSGCR_RSTOE_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_RSTOE_MASK) >> DDRPHY_DSGCR_RSTOE_SHIFT)
1759 
1760 /*
1761  * ODTOE (R/W)
1762  *
1763  * SDRAM ODT Output Enable: Enables, when set, the output driver on the I/O for SDRAM ODT pins.
1764  */
1765 #define DDRPHY_DSGCR_ODTOE_MASK (0x20000000UL)
1766 #define DDRPHY_DSGCR_ODTOE_SHIFT (29U)
1767 #define DDRPHY_DSGCR_ODTOE_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_ODTOE_SHIFT) & DDRPHY_DSGCR_ODTOE_MASK)
1768 #define DDRPHY_DSGCR_ODTOE_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_ODTOE_MASK) >> DDRPHY_DSGCR_ODTOE_SHIFT)
1769 
1770 /*
1771  * CKOE (R/W)
1772  *
1773  * SDRAM CK Output Enable: Enables, when set, the output driver on the I/O for SDRAM CK/CK# pins.
1774  */
1775 #define DDRPHY_DSGCR_CKOE_MASK (0x10000000UL)
1776 #define DDRPHY_DSGCR_CKOE_SHIFT (28U)
1777 #define DDRPHY_DSGCR_CKOE_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_CKOE_SHIFT) & DDRPHY_DSGCR_CKOE_MASK)
1778 #define DDRPHY_DSGCR_CKOE_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_CKOE_MASK) >> DDRPHY_DSGCR_CKOE_SHIFT)
1779 
1780 /*
1781  * ODTPDD1 (R/W)
1782  *
1783  * ODT Power Down Driver: Powers down, when set, the output driver on the I/O for ODT[3:0] pins. ODTPDD[0] controls the power down for ODT[0], ODTPDD[1] controls the power down for ODT[1], and so on.
1784  */
1785 #define DDRPHY_DSGCR_ODTPDD1_MASK (0xF000000UL)
1786 #define DDRPHY_DSGCR_ODTPDD1_SHIFT (24U)
1787 #define DDRPHY_DSGCR_ODTPDD1_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_ODTPDD1_SHIFT) & DDRPHY_DSGCR_ODTPDD1_MASK)
1788 #define DDRPHY_DSGCR_ODTPDD1_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_ODTPDD1_MASK) >> DDRPHY_DSGCR_ODTPDD1_SHIFT)
1789 
1790 /*
1791  * CKEPDD1 (R/W)
1792  *
1793  * CKE Power Down Driver: Powers down, when set, the output driver on the I/O for CKE[3:0] pins. CKEPDD[0] controls the power down for CKE[0], CKEPDD[1] controls the power down for CKE[1], and so on.
1794  */
1795 #define DDRPHY_DSGCR_CKEPDD1_MASK (0xF00000UL)
1796 #define DDRPHY_DSGCR_CKEPDD1_SHIFT (20U)
1797 #define DDRPHY_DSGCR_CKEPDD1_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_CKEPDD1_SHIFT) & DDRPHY_DSGCR_CKEPDD1_MASK)
1798 #define DDRPHY_DSGCR_CKEPDD1_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_CKEPDD1_MASK) >> DDRPHY_DSGCR_CKEPDD1_SHIFT)
1799 
1800 /*
1801  * SDRMODE (R/W)
1802  *
1803  * Single Data Rate Mode: Indicates, if set, that the external controller is configured to run in single data rate (SDR) mode. Otherwise if not set the controller is running in half data rate (HDR) mode. This bit not supported in the current version of the PUB.
1804  */
1805 #define DDRPHY_DSGCR_SDRMODE_MASK (0x80000UL)
1806 #define DDRPHY_DSGCR_SDRMODE_SHIFT (19U)
1807 #define DDRPHY_DSGCR_SDRMODE_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_SDRMODE_SHIFT) & DDRPHY_DSGCR_SDRMODE_MASK)
1808 #define DDRPHY_DSGCR_SDRMODE_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_SDRMODE_MASK) >> DDRPHY_DSGCR_SDRMODE_SHIFT)
1809 
1810 /*
1811  * RRMODE (R/W)
1812  *
1813  * Rise-to-Rise Mode: Indicates, if set, that the PHY mission mode is configured to run in rise-to-rise mode. Otherwise if not set the PHY mission mode is running in rise-to- fall mode.
1814  */
1815 #define DDRPHY_DSGCR_RRMODE_MASK (0x40000UL)
1816 #define DDRPHY_DSGCR_RRMODE_SHIFT (18U)
1817 #define DDRPHY_DSGCR_RRMODE_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_RRMODE_SHIFT) & DDRPHY_DSGCR_RRMODE_MASK)
1818 #define DDRPHY_DSGCR_RRMODE_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_RRMODE_MASK) >> DDRPHY_DSGCR_RRMODE_SHIFT)
1819 
1820 /*
1821  * ATOAE (R/W)
1822  *
1823  * ATO Analog Test Enable: Enables, if set, the analog test output (ATO) I/O.
1824  */
1825 #define DDRPHY_DSGCR_ATOAE_MASK (0x20000UL)
1826 #define DDRPHY_DSGCR_ATOAE_SHIFT (17U)
1827 #define DDRPHY_DSGCR_ATOAE_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_ATOAE_SHIFT) & DDRPHY_DSGCR_ATOAE_MASK)
1828 #define DDRPHY_DSGCR_ATOAE_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_ATOAE_MASK) >> DDRPHY_DSGCR_ATOAE_SHIFT)
1829 
1830 /*
1831  * DTOOE (R/W)
1832  *
1833  * DTO Output Enable: Enables, when set, the output driver on the I/O for DTO pins.
1834  */
1835 #define DDRPHY_DSGCR_DTOOE_MASK (0x10000UL)
1836 #define DDRPHY_DSGCR_DTOOE_SHIFT (16U)
1837 #define DDRPHY_DSGCR_DTOOE_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_DTOOE_SHIFT) & DDRPHY_DSGCR_DTOOE_MASK)
1838 #define DDRPHY_DSGCR_DTOOE_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_DTOOE_MASK) >> DDRPHY_DSGCR_DTOOE_SHIFT)
1839 
1840 /*
1841  * DTOIOM (R/W)
1842  *
1843  * DTO I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for DTO pins.
1844  */
1845 #define DDRPHY_DSGCR_DTOIOM_MASK (0x8000U)
1846 #define DDRPHY_DSGCR_DTOIOM_SHIFT (15U)
1847 #define DDRPHY_DSGCR_DTOIOM_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_DTOIOM_SHIFT) & DDRPHY_DSGCR_DTOIOM_MASK)
1848 #define DDRPHY_DSGCR_DTOIOM_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_DTOIOM_MASK) >> DDRPHY_DSGCR_DTOIOM_SHIFT)
1849 
1850 /*
1851  * DTOPDR (R/W)
1852  *
1853  * DTO Power Down Receiver: Powers down, when set, the input receiver on the I/O for DTO pins.
1854  */
1855 #define DDRPHY_DSGCR_DTOPDR_MASK (0x4000U)
1856 #define DDRPHY_DSGCR_DTOPDR_SHIFT (14U)
1857 #define DDRPHY_DSGCR_DTOPDR_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_DTOPDR_SHIFT) & DDRPHY_DSGCR_DTOPDR_MASK)
1858 #define DDRPHY_DSGCR_DTOPDR_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_DTOPDR_MASK) >> DDRPHY_DSGCR_DTOPDR_SHIFT)
1859 
1860 /*
1861  * DTOPDD1 (R/W)
1862  *
1863  * DTO Power Down Driver: Powers down, when set, the output driver on the I/O for DTO pins.
1864  */
1865 #define DDRPHY_DSGCR_DTOPDD1_MASK (0x2000U)
1866 #define DDRPHY_DSGCR_DTOPDD1_SHIFT (13U)
1867 #define DDRPHY_DSGCR_DTOPDD1_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_DTOPDD1_SHIFT) & DDRPHY_DSGCR_DTOPDD1_MASK)
1868 #define DDRPHY_DSGCR_DTOPDD1_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_DTOPDD1_MASK) >> DDRPHY_DSGCR_DTOPDD1_SHIFT)
1869 
1870 /*
1871  * DTOODT (R/W)
1872  *
1873  * DTO On-Die Termination: Enables, when set, the on-die termination on the I/O for DTO pins.
1874  */
1875 #define DDRPHY_DSGCR_DTOODT_MASK (0x1000U)
1876 #define DDRPHY_DSGCR_DTOODT_SHIFT (12U)
1877 #define DDRPHY_DSGCR_DTOODT_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_DTOODT_SHIFT) & DDRPHY_DSGCR_DTOODT_MASK)
1878 #define DDRPHY_DSGCR_DTOODT_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_DTOODT_MASK) >> DDRPHY_DSGCR_DTOODT_SHIFT)
1879 
1880 /*
1881  * PUAD (R/W)
1882  *
1883  * PHY Update Acknowledge Delay: Specifies the number of clock cycles that the indication for the completion of PHY update from the PHY to the controller should be delayed. This essentially delays, by this many clock cycles, the de-assertion of dfi_ctrlup_ack and dfi_phyupd_req signals relative to the time when the delay lines or I/Os are updated.
1884  */
1885 #define DDRPHY_DSGCR_PUAD_MASK (0xF00U)
1886 #define DDRPHY_DSGCR_PUAD_SHIFT (8U)
1887 #define DDRPHY_DSGCR_PUAD_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_PUAD_SHIFT) & DDRPHY_DSGCR_PUAD_MASK)
1888 #define DDRPHY_DSGCR_PUAD_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_PUAD_MASK) >> DDRPHY_DSGCR_PUAD_SHIFT)
1889 
1890 /*
1891  * BRRMODE (R/W)
1892  *
1893  * Bypass Rise-to-Rise Mode: Indicates, if set, that the PHY bypass mode is configured to run in rise-to-rise mode. Otherwise if not set the PHY bypass mode is running in rise-to-fall mode.
1894  */
1895 #define DDRPHY_DSGCR_BRRMODE_MASK (0x80U)
1896 #define DDRPHY_DSGCR_BRRMODE_SHIFT (7U)
1897 #define DDRPHY_DSGCR_BRRMODE_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_BRRMODE_SHIFT) & DDRPHY_DSGCR_BRRMODE_MASK)
1898 #define DDRPHY_DSGCR_BRRMODE_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_BRRMODE_MASK) >> DDRPHY_DSGCR_BRRMODE_SHIFT)
1899 
1900 /*
1901  * DQSGX (R/W)
1902  *
1903  * DQS Gate Extension: Specifies, if set, that the DQS gating must be extended by two DRAM clock cycles and then re-centered, i.e. one clock cycle extension on either side.
1904  */
1905 #define DDRPHY_DSGCR_DQSGX_MASK (0x40U)
1906 #define DDRPHY_DSGCR_DQSGX_SHIFT (6U)
1907 #define DDRPHY_DSGCR_DQSGX_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_DQSGX_SHIFT) & DDRPHY_DSGCR_DQSGX_MASK)
1908 #define DDRPHY_DSGCR_DQSGX_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_DQSGX_MASK) >> DDRPHY_DSGCR_DQSGX_SHIFT)
1909 
1910 /*
1911  * CUAEN (R/W)
1912  *
1913  * Controller Update Acknowledge Enable: Specifies, if set, that the PHY should issue controller update acknowledge when the DFI controller update request is asserted. By default the PHY does not acknowledge controller initiated update requests but simply does an update whenever there is a controller update request. This speeds up the update.
1914  */
1915 #define DDRPHY_DSGCR_CUAEN_MASK (0x20U)
1916 #define DDRPHY_DSGCR_CUAEN_SHIFT (5U)
1917 #define DDRPHY_DSGCR_CUAEN_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_CUAEN_SHIFT) & DDRPHY_DSGCR_CUAEN_MASK)
1918 #define DDRPHY_DSGCR_CUAEN_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_CUAEN_MASK) >> DDRPHY_DSGCR_CUAEN_SHIFT)
1919 
1920 /*
1921  * LPPLLPD (R/W)
1922  *
1923  * Low Power PLL Power Down: Specifies, if set, that the PHY should respond to the DFI low power opportunity request and power down the PLL of the byte if the wakeup time request satisfies the PLL lock time.
1924  */
1925 #define DDRPHY_DSGCR_LPPLLPD_MASK (0x10U)
1926 #define DDRPHY_DSGCR_LPPLLPD_SHIFT (4U)
1927 #define DDRPHY_DSGCR_LPPLLPD_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_LPPLLPD_SHIFT) & DDRPHY_DSGCR_LPPLLPD_MASK)
1928 #define DDRPHY_DSGCR_LPPLLPD_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_LPPLLPD_MASK) >> DDRPHY_DSGCR_LPPLLPD_SHIFT)
1929 
1930 /*
1931  * LPIOPD (R/W)
1932  *
1933  * Low Power I/O Power Down: Specifies, if set, that the PHY should respond to the DFI low power opportunity request and power down the I/Os of the byte.
1934  */
1935 #define DDRPHY_DSGCR_LPIOPD_MASK (0x8U)
1936 #define DDRPHY_DSGCR_LPIOPD_SHIFT (3U)
1937 #define DDRPHY_DSGCR_LPIOPD_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_LPIOPD_SHIFT) & DDRPHY_DSGCR_LPIOPD_MASK)
1938 #define DDRPHY_DSGCR_LPIOPD_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_LPIOPD_MASK) >> DDRPHY_DSGCR_LPIOPD_SHIFT)
1939 
1940 /*
1941  * ZUEN (R/W)
1942  *
1943  * Impedance Update Enable: Specifies, if set, that in addition to DDL VT update, the PHY could also perform impedance calibration (update).
1944  * Refer to the “Impedance Control Register 0-1 (ZQnCR0-1)” on page 145 bit fields DFICU0, DFICU1 and DFICCU bits to control if an impedance calibration is performed (update) with a DFI controller update request.
1945  * Refer to the “Impedance Control Register 0-1 (ZQnCR0-1)” on page 145 bit fields DFIPU0 and DFIPU1 bits to control if an impedance calibration is performed (update) with a DFI PHY update request.
1946  */
1947 #define DDRPHY_DSGCR_ZUEN_MASK (0x4U)
1948 #define DDRPHY_DSGCR_ZUEN_SHIFT (2U)
1949 #define DDRPHY_DSGCR_ZUEN_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_ZUEN_SHIFT) & DDRPHY_DSGCR_ZUEN_MASK)
1950 #define DDRPHY_DSGCR_ZUEN_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_ZUEN_MASK) >> DDRPHY_DSGCR_ZUEN_SHIFT)
1951 
1952 /*
1953  * BDISEN (R/W)
1954  *
1955  * Byte Disable Enable: Specifies, if set, that the PHY should respond to DFI byte disable request. Otherwise the byte disable from the DFI is ignored in which case bytes can only be disabled using the DXnGCR register.
1956  */
1957 #define DDRPHY_DSGCR_BDISEN_MASK (0x2U)
1958 #define DDRPHY_DSGCR_BDISEN_SHIFT (1U)
1959 #define DDRPHY_DSGCR_BDISEN_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_BDISEN_SHIFT) & DDRPHY_DSGCR_BDISEN_MASK)
1960 #define DDRPHY_DSGCR_BDISEN_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_BDISEN_MASK) >> DDRPHY_DSGCR_BDISEN_SHIFT)
1961 
1962 /*
1963  * PUREN (R/W)
1964  *
1965  * PHY Update Request Enable: Specifies if set, that the PHY should issue PHY- initiated update request when there is DDL VT drift.
1966  */
1967 #define DDRPHY_DSGCR_PUREN_MASK (0x1U)
1968 #define DDRPHY_DSGCR_PUREN_SHIFT (0U)
1969 #define DDRPHY_DSGCR_PUREN_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_PUREN_SHIFT) & DDRPHY_DSGCR_PUREN_MASK)
1970 #define DDRPHY_DSGCR_PUREN_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_PUREN_MASK) >> DDRPHY_DSGCR_PUREN_SHIFT)
1971 
1972 /* Bitfield definition for register: DCR */
1973 /*
1974  * UDIMM (R/W)
1975  *
1976  * Un-buffered DIMM Address Mirroring: Indicates, if set, that there is address mirroring on the second rank of an un-buffered DIMM (the rank connected to CS#[1]). In this case, the PUB re-scrambles the bank and address when sending mode register commands to the second rank. This only applies to PUB internal SDRAM transactions. Transactions generated by the controller must make its own adjustments when using an un-buffered DIMM. DCR[NOSRA] must be set if address mirroring is enabled.
1977  */
1978 #define DDRPHY_DCR_UDIMM_MASK (0x20000000UL)
1979 #define DDRPHY_DCR_UDIMM_SHIFT (29U)
1980 #define DDRPHY_DCR_UDIMM_SET(x) (((uint32_t)(x) << DDRPHY_DCR_UDIMM_SHIFT) & DDRPHY_DCR_UDIMM_MASK)
1981 #define DDRPHY_DCR_UDIMM_GET(x) (((uint32_t)(x) & DDRPHY_DCR_UDIMM_MASK) >> DDRPHY_DCR_UDIMM_SHIFT)
1982 
1983 /*
1984  * DDR2T (R/W)
1985  *
1986  * DDR 2T Timing: Indicates, if set, that 2T timing should be used by PUB internally generated SDRAM transactions.
1987  */
1988 #define DDRPHY_DCR_DDR2T_MASK (0x10000000UL)
1989 #define DDRPHY_DCR_DDR2T_SHIFT (28U)
1990 #define DDRPHY_DCR_DDR2T_SET(x) (((uint32_t)(x) << DDRPHY_DCR_DDR2T_SHIFT) & DDRPHY_DCR_DDR2T_MASK)
1991 #define DDRPHY_DCR_DDR2T_GET(x) (((uint32_t)(x) & DDRPHY_DCR_DDR2T_MASK) >> DDRPHY_DCR_DDR2T_SHIFT)
1992 
1993 /*
1994  * NOSRA (R/W)
1995  *
1996  * No Simultaneous Rank Access: Specifies, if set, that simultaneous rank access on the same clock cycle is not allowed. This means that multiple chip select signals should not be asserted at the same time. This may be required on some DIMM systems.
1997  */
1998 #define DDRPHY_DCR_NOSRA_MASK (0x8000000UL)
1999 #define DDRPHY_DCR_NOSRA_SHIFT (27U)
2000 #define DDRPHY_DCR_NOSRA_SET(x) (((uint32_t)(x) << DDRPHY_DCR_NOSRA_SHIFT) & DDRPHY_DCR_NOSRA_MASK)
2001 #define DDRPHY_DCR_NOSRA_GET(x) (((uint32_t)(x) & DDRPHY_DCR_NOSRA_MASK) >> DDRPHY_DCR_NOSRA_SHIFT)
2002 
2003 /*
2004  * BYTEMASK (R/W)
2005  *
2006  * Byte Mask: Mask applied to all beats of read data on all bytes lanes during read DQS gate training. This allows training to be conducted based on selected bit(s) from the byte lanes.
2007  * Valid values for each bit are:
2008  * 0 = Disable compare for that bit 1 = Enable compare for that bit
2009  * Note that this mask applies in DDR3 MPR operation mode as well and must be in keeping with the PDQ field setting.
2010  */
2011 #define DDRPHY_DCR_BYTEMASK_MASK (0x3FC00UL)
2012 #define DDRPHY_DCR_BYTEMASK_SHIFT (10U)
2013 #define DDRPHY_DCR_BYTEMASK_SET(x) (((uint32_t)(x) << DDRPHY_DCR_BYTEMASK_SHIFT) & DDRPHY_DCR_BYTEMASK_MASK)
2014 #define DDRPHY_DCR_BYTEMASK_GET(x) (((uint32_t)(x) & DDRPHY_DCR_BYTEMASK_MASK) >> DDRPHY_DCR_BYTEMASK_SHIFT)
2015 
2016 /*
2017  * MPRDQ (R/W)
2018  *
2019  * Multi-Purpose Register (MPR) DQ (DDR3 Only): Specifies the value that is driven on non-primary DQ pins during MPR reads. Valid values are:
2020  * 0 = Primary DQ drives out the data from MPR (0-1-0-1); non-primary DQs drive ‘0’ 1 = Primary DQ and non-primary DQs all drive the same data from MPR (0-1-0-1)
2021  */
2022 #define DDRPHY_DCR_MPRDQ_MASK (0x80U)
2023 #define DDRPHY_DCR_MPRDQ_SHIFT (7U)
2024 #define DDRPHY_DCR_MPRDQ_SET(x) (((uint32_t)(x) << DDRPHY_DCR_MPRDQ_SHIFT) & DDRPHY_DCR_MPRDQ_MASK)
2025 #define DDRPHY_DCR_MPRDQ_GET(x) (((uint32_t)(x) & DDRPHY_DCR_MPRDQ_MASK) >> DDRPHY_DCR_MPRDQ_SHIFT)
2026 
2027 /*
2028  * PDQ (R/W)
2029  *
2030  * Primary DQ (DDR3 Only): Specifies the DQ pin in a byte that is designated as a primary pin for Multi-Purpose Register (MPR) reads. Valid values are 0 to 7 for DQ[0] to DQ[7], respectively.
2031  */
2032 #define DDRPHY_DCR_PDQ_MASK (0x70U)
2033 #define DDRPHY_DCR_PDQ_SHIFT (4U)
2034 #define DDRPHY_DCR_PDQ_SET(x) (((uint32_t)(x) << DDRPHY_DCR_PDQ_SHIFT) & DDRPHY_DCR_PDQ_MASK)
2035 #define DDRPHY_DCR_PDQ_GET(x) (((uint32_t)(x) & DDRPHY_DCR_PDQ_MASK) >> DDRPHY_DCR_PDQ_SHIFT)
2036 
2037 /*
2038  * DDR8BNK (R/W)
2039  *
2040  * DDR 8-Bank: Indicates, if set, that the SDRAM used has 8 banks. tRPA = tRP+1 and tFAW are used for 8-bank DRAMs, otherwise tRPA = tRP and no tFAW is used.
2041  * Note that a setting of 1 for DRAMs that have fewer than 8 banks results in correct functionality, but less tight DRAM command spacing for the parameters.
2042  */
2043 #define DDRPHY_DCR_DDR8BNK_MASK (0x8U)
2044 #define DDRPHY_DCR_DDR8BNK_SHIFT (3U)
2045 #define DDRPHY_DCR_DDR8BNK_SET(x) (((uint32_t)(x) << DDRPHY_DCR_DDR8BNK_SHIFT) & DDRPHY_DCR_DDR8BNK_MASK)
2046 #define DDRPHY_DCR_DDR8BNK_GET(x) (((uint32_t)(x) & DDRPHY_DCR_DDR8BNK_MASK) >> DDRPHY_DCR_DDR8BNK_SHIFT)
2047 
2048 /*
2049  * DDRMD (R/W)
2050  *
2051  * DDR Mode: SDRAM DDR mode. Valid values are: 000 = Reserved
2052  * 001 = Reserved
2053  * 010 = DDR2
2054  * 011 = DDR3
2055  * 100 – 111 = Reserved
2056  */
2057 #define DDRPHY_DCR_DDRMD_MASK (0x7U)
2058 #define DDRPHY_DCR_DDRMD_SHIFT (0U)
2059 #define DDRPHY_DCR_DDRMD_SET(x) (((uint32_t)(x) << DDRPHY_DCR_DDRMD_SHIFT) & DDRPHY_DCR_DDRMD_MASK)
2060 #define DDRPHY_DCR_DDRMD_GET(x) (((uint32_t)(x) & DDRPHY_DCR_DDRMD_MASK) >> DDRPHY_DCR_DDRMD_SHIFT)
2061 
2062 /* Bitfield definition for register: DTPR0 */
2063 /*
2064  * TRC (R/W)
2065  *
2066  * Activate to activate command delay (same bank). Valid values are 2 to 63.
2067  */
2068 #define DDRPHY_DTPR0_TRC_MASK (0xFC000000UL)
2069 #define DDRPHY_DTPR0_TRC_SHIFT (26U)
2070 #define DDRPHY_DTPR0_TRC_SET(x) (((uint32_t)(x) << DDRPHY_DTPR0_TRC_SHIFT) & DDRPHY_DTPR0_TRC_MASK)
2071 #define DDRPHY_DTPR0_TRC_GET(x) (((uint32_t)(x) & DDRPHY_DTPR0_TRC_MASK) >> DDRPHY_DTPR0_TRC_SHIFT)
2072 
2073 /*
2074  * TRRD (R/W)
2075  *
2076  * Activate to activate command delay (different banks). Valid values are 1 to 15.
2077  */
2078 #define DDRPHY_DTPR0_TRRD_MASK (0x3C00000UL)
2079 #define DDRPHY_DTPR0_TRRD_SHIFT (22U)
2080 #define DDRPHY_DTPR0_TRRD_SET(x) (((uint32_t)(x) << DDRPHY_DTPR0_TRRD_SHIFT) & DDRPHY_DTPR0_TRRD_MASK)
2081 #define DDRPHY_DTPR0_TRRD_GET(x) (((uint32_t)(x) & DDRPHY_DTPR0_TRRD_MASK) >> DDRPHY_DTPR0_TRRD_SHIFT)
2082 
2083 /*
2084  * TRAS (R/W)
2085  *
2086  * Activate to precharge command delay. Valid values are 2 to 63.
2087  */
2088 #define DDRPHY_DTPR0_TRAS_MASK (0x3F0000UL)
2089 #define DDRPHY_DTPR0_TRAS_SHIFT (16U)
2090 #define DDRPHY_DTPR0_TRAS_SET(x) (((uint32_t)(x) << DDRPHY_DTPR0_TRAS_SHIFT) & DDRPHY_DTPR0_TRAS_MASK)
2091 #define DDRPHY_DTPR0_TRAS_GET(x) (((uint32_t)(x) & DDRPHY_DTPR0_TRAS_MASK) >> DDRPHY_DTPR0_TRAS_SHIFT)
2092 
2093 /*
2094  * TRCD (R/W)
2095  *
2096  * Activate to read or write delay. Minimum time from when an activate command is issued to when a read or write to the activated row can be issued. Valid values are 2 to 15.
2097  */
2098 #define DDRPHY_DTPR0_TRCD_MASK (0xF000U)
2099 #define DDRPHY_DTPR0_TRCD_SHIFT (12U)
2100 #define DDRPHY_DTPR0_TRCD_SET(x) (((uint32_t)(x) << DDRPHY_DTPR0_TRCD_SHIFT) & DDRPHY_DTPR0_TRCD_MASK)
2101 #define DDRPHY_DTPR0_TRCD_GET(x) (((uint32_t)(x) & DDRPHY_DTPR0_TRCD_MASK) >> DDRPHY_DTPR0_TRCD_SHIFT)
2102 
2103 /*
2104  * TRP (R/W)
2105  *
2106  * Precharge command period: The minimum time between a precharge command and any other command. Note that the Controller automatically derives tRPA for 8- bank DDR2 devices by adding 1 to tRP. Valid values are 2 to 15.
2107  */
2108 #define DDRPHY_DTPR0_TRP_MASK (0xF00U)
2109 #define DDRPHY_DTPR0_TRP_SHIFT (8U)
2110 #define DDRPHY_DTPR0_TRP_SET(x) (((uint32_t)(x) << DDRPHY_DTPR0_TRP_SHIFT) & DDRPHY_DTPR0_TRP_MASK)
2111 #define DDRPHY_DTPR0_TRP_GET(x) (((uint32_t)(x) & DDRPHY_DTPR0_TRP_MASK) >> DDRPHY_DTPR0_TRP_SHIFT)
2112 
2113 /*
2114  * TWTR (R/W)
2115  *
2116  * Internal write to read command delay. Valid values are 1 to 15.
2117  */
2118 #define DDRPHY_DTPR0_TWTR_MASK (0xF0U)
2119 #define DDRPHY_DTPR0_TWTR_SHIFT (4U)
2120 #define DDRPHY_DTPR0_TWTR_SET(x) (((uint32_t)(x) << DDRPHY_DTPR0_TWTR_SHIFT) & DDRPHY_DTPR0_TWTR_MASK)
2121 #define DDRPHY_DTPR0_TWTR_GET(x) (((uint32_t)(x) & DDRPHY_DTPR0_TWTR_MASK) >> DDRPHY_DTPR0_TWTR_SHIFT)
2122 
2123 /*
2124  * TRTP (R/W)
2125  *
2126  * Internal read to precharge command delay. Valid values are 2 to 15.
2127  */
2128 #define DDRPHY_DTPR0_TRTP_MASK (0xFU)
2129 #define DDRPHY_DTPR0_TRTP_SHIFT (0U)
2130 #define DDRPHY_DTPR0_TRTP_SET(x) (((uint32_t)(x) << DDRPHY_DTPR0_TRTP_SHIFT) & DDRPHY_DTPR0_TRTP_MASK)
2131 #define DDRPHY_DTPR0_TRTP_GET(x) (((uint32_t)(x) & DDRPHY_DTPR0_TRTP_MASK) >> DDRPHY_DTPR0_TRTP_SHIFT)
2132 
2133 /* Bitfield definition for register: DTPR1 */
2134 /*
2135  * TAOND_TAOFD (R/W)
2136  *
2137  * ODT turn-on/turn-off delays (DDR2 only). Valid values are: 00 = 2/2.5
2138  * 01 = 3/3.5
2139  * 10 = 4/4.5
2140  * 11 = 5/5.5
2141  * Most DDR2 devices utilize a fixed value of 2/2.5. For non-standard SDRAMs, the user must ensure that the operational Write Latency is always greater than or equal to the ODT turn-on delay. For example, a DDR2 SDRAM with CAS latency set to 3 and CAS additive latency set to 0 has a Write Latency of 2. Thus 2/2.5 can be used, but not 3/3.5 or higher.
2142  */
2143 #define DDRPHY_DTPR1_TAOND_TAOFD_MASK (0xC0000000UL)
2144 #define DDRPHY_DTPR1_TAOND_TAOFD_SHIFT (30U)
2145 #define DDRPHY_DTPR1_TAOND_TAOFD_SET(x) (((uint32_t)(x) << DDRPHY_DTPR1_TAOND_TAOFD_SHIFT) & DDRPHY_DTPR1_TAOND_TAOFD_MASK)
2146 #define DDRPHY_DTPR1_TAOND_TAOFD_GET(x) (((uint32_t)(x) & DDRPHY_DTPR1_TAOND_TAOFD_MASK) >> DDRPHY_DTPR1_TAOND_TAOFD_SHIFT)
2147 
2148 /*
2149  * TWLO (R/W)
2150  *
2151  * Write leveling output delay: Number of clock cycles from when write leveling DQS is driven high by the control block to when the results from the SDRAM on DQ is sampled by the control block. This must include the SDRAM tWLO timing parameter plus the round trip delay from control block to SDRAM back to control block.
2152  */
2153 #define DDRPHY_DTPR1_TWLO_MASK (0x3C000000UL)
2154 #define DDRPHY_DTPR1_TWLO_SHIFT (26U)
2155 #define DDRPHY_DTPR1_TWLO_SET(x) (((uint32_t)(x) << DDRPHY_DTPR1_TWLO_SHIFT) & DDRPHY_DTPR1_TWLO_MASK)
2156 #define DDRPHY_DTPR1_TWLO_GET(x) (((uint32_t)(x) & DDRPHY_DTPR1_TWLO_MASK) >> DDRPHY_DTPR1_TWLO_SHIFT)
2157 
2158 /*
2159  * TWLMRD (R/W)
2160  *
2161  * Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge.
2162  */
2163 #define DDRPHY_DTPR1_TWLMRD_MASK (0x3F00000UL)
2164 #define DDRPHY_DTPR1_TWLMRD_SHIFT (20U)
2165 #define DDRPHY_DTPR1_TWLMRD_SET(x) (((uint32_t)(x) << DDRPHY_DTPR1_TWLMRD_SHIFT) & DDRPHY_DTPR1_TWLMRD_MASK)
2166 #define DDRPHY_DTPR1_TWLMRD_GET(x) (((uint32_t)(x) & DDRPHY_DTPR1_TWLMRD_MASK) >> DDRPHY_DTPR1_TWLMRD_SHIFT)
2167 
2168 /*
2169  * TRFC (R/W)
2170  *
2171  * Refresh-to-Refresh: Indicates the minimum time between two refresh commands or between a refresh and an active command. This is derived from the minimum refresh interval from the datasheet, tRFC(min), divided by the clock cycle time. The default number of clock cycles is for the largest JEDEC tRFC(min parameter value supported.
2172  */
2173 #define DDRPHY_DTPR1_TRFC_MASK (0xFF800UL)
2174 #define DDRPHY_DTPR1_TRFC_SHIFT (11U)
2175 #define DDRPHY_DTPR1_TRFC_SET(x) (((uint32_t)(x) << DDRPHY_DTPR1_TRFC_SHIFT) & DDRPHY_DTPR1_TRFC_MASK)
2176 #define DDRPHY_DTPR1_TRFC_GET(x) (((uint32_t)(x) & DDRPHY_DTPR1_TRFC_MASK) >> DDRPHY_DTPR1_TRFC_SHIFT)
2177 
2178 /*
2179  * TFAW (R/W)
2180  *
2181  * 4-bank activate period. No more than 4-bank activate commands may be issued in a given tFAW period. Only applies to 8-bank devices. Valid values are 2 to 63.
2182  */
2183 #define DDRPHY_DTPR1_TFAW_MASK (0x7E0U)
2184 #define DDRPHY_DTPR1_TFAW_SHIFT (5U)
2185 #define DDRPHY_DTPR1_TFAW_SET(x) (((uint32_t)(x) << DDRPHY_DTPR1_TFAW_SHIFT) & DDRPHY_DTPR1_TFAW_MASK)
2186 #define DDRPHY_DTPR1_TFAW_GET(x) (((uint32_t)(x) & DDRPHY_DTPR1_TFAW_MASK) >> DDRPHY_DTPR1_TFAW_SHIFT)
2187 
2188 /*
2189  * TMOD (R/W)
2190  *
2191  * Load mode update delay (DDR3 only). The minimum time between a load mode register command and a non-load mode register command. Valid values are: 000 = 12
2192  * 001 = 13
2193  * 010 = 14
2194  * 011 = 15
2195  * 100 = 16
2196  * 101 = 17
2197  * 110 – 111 = Reserved
2198  */
2199 #define DDRPHY_DTPR1_TMOD_MASK (0x1CU)
2200 #define DDRPHY_DTPR1_TMOD_SHIFT (2U)
2201 #define DDRPHY_DTPR1_TMOD_SET(x) (((uint32_t)(x) << DDRPHY_DTPR1_TMOD_SHIFT) & DDRPHY_DTPR1_TMOD_MASK)
2202 #define DDRPHY_DTPR1_TMOD_GET(x) (((uint32_t)(x) & DDRPHY_DTPR1_TMOD_MASK) >> DDRPHY_DTPR1_TMOD_SHIFT)
2203 
2204 /*
2205  * TMRD (R/W)
2206  *
2207  * Load mode cycle time: The minimum time between a load mode register command and any other command. For DDR3 this is the minimum time between two load mode register commands. Valid values for DDR2 are 2 to 3. For DDR3, the value used for tMRD is 4 plus the value programmed in these bits, i.e. tMRD value for DDR3 ranges from 4 to 7.
2208  */
2209 #define DDRPHY_DTPR1_TMRD_MASK (0x3U)
2210 #define DDRPHY_DTPR1_TMRD_SHIFT (0U)
2211 #define DDRPHY_DTPR1_TMRD_SET(x) (((uint32_t)(x) << DDRPHY_DTPR1_TMRD_SHIFT) & DDRPHY_DTPR1_TMRD_MASK)
2212 #define DDRPHY_DTPR1_TMRD_GET(x) (((uint32_t)(x) & DDRPHY_DTPR1_TMRD_MASK) >> DDRPHY_DTPR1_TMRD_SHIFT)
2213 
2214 /* Bitfield definition for register: DTPR2 */
2215 /*
2216  * TCCD (R/W)
2217  *
2218  * Read to read and write to write command delay. Valid values are: 0 = BL/2 for DDR2 and 4 for DDR3
2219  * 1 = BL/2 + 1 for DDR2 and 5 for DDR3
2220  */
2221 #define DDRPHY_DTPR2_TCCD_MASK (0x80000000UL)
2222 #define DDRPHY_DTPR2_TCCD_SHIFT (31U)
2223 #define DDRPHY_DTPR2_TCCD_SET(x) (((uint32_t)(x) << DDRPHY_DTPR2_TCCD_SHIFT) & DDRPHY_DTPR2_TCCD_MASK)
2224 #define DDRPHY_DTPR2_TCCD_GET(x) (((uint32_t)(x) & DDRPHY_DTPR2_TCCD_MASK) >> DDRPHY_DTPR2_TCCD_SHIFT)
2225 
2226 /*
2227  * TRTW (R/W)
2228  *
2229  * Read to Write command delay. Valid values are:
2230  * 0 = standard bus turn around delay
2231  * 1 = add 1 clock to standard bus turn around delay
2232  * This parameter allows the user to increase the delay between issuing Write commands to the SDRAM when preceded by Read commands. This provides an option to increase bus turn-around margin for high frequency systems.
2233  */
2234 #define DDRPHY_DTPR2_TRTW_MASK (0x40000000UL)
2235 #define DDRPHY_DTPR2_TRTW_SHIFT (30U)
2236 #define DDRPHY_DTPR2_TRTW_SET(x) (((uint32_t)(x) << DDRPHY_DTPR2_TRTW_SHIFT) & DDRPHY_DTPR2_TRTW_MASK)
2237 #define DDRPHY_DTPR2_TRTW_GET(x) (((uint32_t)(x) & DDRPHY_DTPR2_TRTW_MASK) >> DDRPHY_DTPR2_TRTW_SHIFT)
2238 
2239 /*
2240  * TRTODT (R/W)
2241  *
2242  * Read to ODT delay (DDR3 only). Specifies whether ODT can be enabled immediately after the read post-amble or one clock delay has to be added. Valid values are:
2243  * 0 = ODT may be turned on immediately after read post-amble
2244  * 1 = ODT may not be turned on until one clock after the read post-amble
2245  * If tRTODT is set to 1, then the read-to-write latency is increased by 1 if ODT is enabled.
2246  */
2247 #define DDRPHY_DTPR2_TRTODT_MASK (0x20000000UL)
2248 #define DDRPHY_DTPR2_TRTODT_SHIFT (29U)
2249 #define DDRPHY_DTPR2_TRTODT_SET(x) (((uint32_t)(x) << DDRPHY_DTPR2_TRTODT_SHIFT) & DDRPHY_DTPR2_TRTODT_MASK)
2250 #define DDRPHY_DTPR2_TRTODT_GET(x) (((uint32_t)(x) & DDRPHY_DTPR2_TRTODT_MASK) >> DDRPHY_DTPR2_TRTODT_SHIFT)
2251 
2252 /*
2253  * TDLLK (R/W)
2254  *
2255  * DLL locking time. Valid values are 2 to 1023.
2256  */
2257 #define DDRPHY_DTPR2_TDLLK_MASK (0x1FF80000UL)
2258 #define DDRPHY_DTPR2_TDLLK_SHIFT (19U)
2259 #define DDRPHY_DTPR2_TDLLK_SET(x) (((uint32_t)(x) << DDRPHY_DTPR2_TDLLK_SHIFT) & DDRPHY_DTPR2_TDLLK_MASK)
2260 #define DDRPHY_DTPR2_TDLLK_GET(x) (((uint32_t)(x) & DDRPHY_DTPR2_TDLLK_MASK) >> DDRPHY_DTPR2_TDLLK_SHIFT)
2261 
2262 /*
2263  * TCKE (R/W)
2264  *
2265  * CKE minimum pulse width. Also specifies the minimum time that the SDRAM must remain in power down or self refresh mode. For DDR3 this parameter must be set to the value of tCKESR which is usually bigger than the value of tCKE. Valid values are 2 to 15.
2266  */
2267 #define DDRPHY_DTPR2_TCKE_MASK (0x78000UL)
2268 #define DDRPHY_DTPR2_TCKE_SHIFT (15U)
2269 #define DDRPHY_DTPR2_TCKE_SET(x) (((uint32_t)(x) << DDRPHY_DTPR2_TCKE_SHIFT) & DDRPHY_DTPR2_TCKE_MASK)
2270 #define DDRPHY_DTPR2_TCKE_GET(x) (((uint32_t)(x) & DDRPHY_DTPR2_TCKE_MASK) >> DDRPHY_DTPR2_TCKE_SHIFT)
2271 
2272 /*
2273  * TXP (R/W)
2274  *
2275  * Power down exit delay. The minimum time between a power down exit command and any other command. This parameter must be set to the maximum of the various minimum power down exit delay parameters specified in the SDRAM datasheet, i.e. max(tXP, tXARD, tXARDS) for DDR2 and max(tXP, tXPDLL) for DDR3. Valid values are 2 to 31.
2276  */
2277 #define DDRPHY_DTPR2_TXP_MASK (0x7C00U)
2278 #define DDRPHY_DTPR2_TXP_SHIFT (10U)
2279 #define DDRPHY_DTPR2_TXP_SET(x) (((uint32_t)(x) << DDRPHY_DTPR2_TXP_SHIFT) & DDRPHY_DTPR2_TXP_MASK)
2280 #define DDRPHY_DTPR2_TXP_GET(x) (((uint32_t)(x) & DDRPHY_DTPR2_TXP_MASK) >> DDRPHY_DTPR2_TXP_SHIFT)
2281 
2282 /*
2283  * TXS (R/W)
2284  *
2285  * Self refresh exit delay. The minimum time between a self refresh exit command and any other command. This parameter must be set to the maximum of the various minimum self refresh exit delay parameters specified in the SDRAM datasheet, i.e. max(tXSNR, tXSRD) for DDR2 and max(tXS, tXSDLL) for DDR3. Valid values are 2 to 1023.
2286  */
2287 #define DDRPHY_DTPR2_TXS_MASK (0x3FFU)
2288 #define DDRPHY_DTPR2_TXS_SHIFT (0U)
2289 #define DDRPHY_DTPR2_TXS_SET(x) (((uint32_t)(x) << DDRPHY_DTPR2_TXS_SHIFT) & DDRPHY_DTPR2_TXS_MASK)
2290 #define DDRPHY_DTPR2_TXS_GET(x) (((uint32_t)(x) & DDRPHY_DTPR2_TXS_MASK) >> DDRPHY_DTPR2_TXS_SHIFT)
2291 
2292 /* Bitfield definition for register: MR0 */
2293 /*
2294  * PD (R/W)
2295  *
2296  * Power-Down Control: Controls the exit time for power-down modes. Refer to the SDRAM datasheet for details on power-down modes. Valid values are:
2297  * 0 = Slow exit (DLL off) 1 = Fast exit (DLL on)
2298  */
2299 #define DDRPHY_MR0_PD_MASK (0x1000U)
2300 #define DDRPHY_MR0_PD_SHIFT (12U)
2301 #define DDRPHY_MR0_PD_SET(x) (((uint32_t)(x) << DDRPHY_MR0_PD_SHIFT) & DDRPHY_MR0_PD_MASK)
2302 #define DDRPHY_MR0_PD_GET(x) (((uint32_t)(x) & DDRPHY_MR0_PD_MASK) >> DDRPHY_MR0_PD_SHIFT)
2303 
2304 /*
2305  * WR (R/W)
2306  *
2307  * Write Recovery: This is the value of the write recovery. It is calculated by dividing the datasheet write recovery time, tWR (ns) by the datasheet clock cycle time, tCK (ns) and rounding up a non-integer value to the next integer. Valid values are:
2308  * 000 = 16
2309  * 001 = 5
2310  * 010 = 6
2311  * 011 = 7
2312  * 100 = 8
2313  * 101 = 10
2314  * 110 = 12
2315  * 111 = 14
2316  * All other settings are reserved and should not be used.
2317  * NOTE: tWR (ns) is the time from the first SDRAM positive clock edge after the last data-in pair of a write command, to when a precharge of the same bank can be issued.
2318  */
2319 #define DDRPHY_MR0_WR_MASK (0xE00U)
2320 #define DDRPHY_MR0_WR_SHIFT (9U)
2321 #define DDRPHY_MR0_WR_SET(x) (((uint32_t)(x) << DDRPHY_MR0_WR_SHIFT) & DDRPHY_MR0_WR_MASK)
2322 #define DDRPHY_MR0_WR_GET(x) (((uint32_t)(x) & DDRPHY_MR0_WR_MASK) >> DDRPHY_MR0_WR_SHIFT)
2323 
2324 /*
2325  * DR (R/W)
2326  *
2327  * DLL Reset: Writing a ‘1’ to this bit will reset the SDRAM DLL. This bit is self- clearing, i.e. it returns back to ‘0’ after the DLL reset has been issued.
2328  */
2329 #define DDRPHY_MR0_DR_MASK (0x100U)
2330 #define DDRPHY_MR0_DR_SHIFT (8U)
2331 #define DDRPHY_MR0_DR_SET(x) (((uint32_t)(x) << DDRPHY_MR0_DR_SHIFT) & DDRPHY_MR0_DR_MASK)
2332 #define DDRPHY_MR0_DR_GET(x) (((uint32_t)(x) & DDRPHY_MR0_DR_MASK) >> DDRPHY_MR0_DR_SHIFT)
2333 
2334 /*
2335  * TM (R/W)
2336  *
2337  * Operating Mode: Selects either normal operating mode (0) or test mode (1). Test mode is reserved for the manufacturer and should not be used.
2338  */
2339 #define DDRPHY_MR0_TM_MASK (0x80U)
2340 #define DDRPHY_MR0_TM_SHIFT (7U)
2341 #define DDRPHY_MR0_TM_SET(x) (((uint32_t)(x) << DDRPHY_MR0_TM_SHIFT) & DDRPHY_MR0_TM_MASK)
2342 #define DDRPHY_MR0_TM_GET(x) (((uint32_t)(x) & DDRPHY_MR0_TM_MASK) >> DDRPHY_MR0_TM_SHIFT)
2343 
2344 /*
2345  * CLH (R/W)
2346  *
2347  * CAS Latency: The delay between when the SDRAM registers a read command to when data is available. Valid values are:
2348  * 0010 = 5
2349  * 0100 = 6
2350  * 0110 = 7
2351  * 1000 = 8
2352  * 1010 = 9
2353  * 1100 = 10
2354  * 1110 = 11
2355  * 0001 = 12
2356  * 0011 = 13
2357  * 0101 = 14
2358  * All other settings are reserved and should not be used.
2359  */
2360 #define DDRPHY_MR0_CLH_MASK (0x70U)
2361 #define DDRPHY_MR0_CLH_SHIFT (4U)
2362 #define DDRPHY_MR0_CLH_SET(x) (((uint32_t)(x) << DDRPHY_MR0_CLH_SHIFT) & DDRPHY_MR0_CLH_MASK)
2363 #define DDRPHY_MR0_CLH_GET(x) (((uint32_t)(x) & DDRPHY_MR0_CLH_MASK) >> DDRPHY_MR0_CLH_SHIFT)
2364 
2365 /*
2366  * BT (R/W)
2367  *
2368  * Burst Type: Indicates whether a burst is sequential (0) or interleaved (1).
2369  */
2370 #define DDRPHY_MR0_BT_MASK (0x8U)
2371 #define DDRPHY_MR0_BT_SHIFT (3U)
2372 #define DDRPHY_MR0_BT_SET(x) (((uint32_t)(x) << DDRPHY_MR0_BT_SHIFT) & DDRPHY_MR0_BT_MASK)
2373 #define DDRPHY_MR0_BT_GET(x) (((uint32_t)(x) & DDRPHY_MR0_BT_MASK) >> DDRPHY_MR0_BT_SHIFT)
2374 
2375 /*
2376  * CLL (R/W)
2377  *
2378  * CAS Latency low bit
2379  */
2380 #define DDRPHY_MR0_CLL_MASK (0x4U)
2381 #define DDRPHY_MR0_CLL_SHIFT (2U)
2382 #define DDRPHY_MR0_CLL_SET(x) (((uint32_t)(x) << DDRPHY_MR0_CLL_SHIFT) & DDRPHY_MR0_CLL_MASK)
2383 #define DDRPHY_MR0_CLL_GET(x) (((uint32_t)(x) & DDRPHY_MR0_CLL_MASK) >> DDRPHY_MR0_CLL_SHIFT)
2384 
2385 /*
2386  * BL (R/W)
2387  *
2388  * Burst Length: Determines the maximum number of column locations that can be accessed during a given read or write command. Valid values are:
2389  * Valid values for DDR3 are: 00 = 8 (Fixed)
2390  * 01 = 4 or 8 (On the fly)
2391  * 10 = 4 (Fixed)
2392  * 11 = Reserved
2393  */
2394 #define DDRPHY_MR0_BL_MASK (0x3U)
2395 #define DDRPHY_MR0_BL_SHIFT (0U)
2396 #define DDRPHY_MR0_BL_SET(x) (((uint32_t)(x) << DDRPHY_MR0_BL_SHIFT) & DDRPHY_MR0_BL_MASK)
2397 #define DDRPHY_MR0_BL_GET(x) (((uint32_t)(x) & DDRPHY_MR0_BL_MASK) >> DDRPHY_MR0_BL_SHIFT)
2398 
2399 /* Bitfield definition for register: MR */
2400 /*
2401  * PD (R/W)
2402  *
2403  * Power-Down Control: Controls the exit time for power-down modes. Refer to the SDRAM datasheet for details on power-down modes. Valid values are:
2404  * 0 = Fast exit 1 = Slow exit
2405  */
2406 #define DDRPHY_MR_PD_MASK (0x1000U)
2407 #define DDRPHY_MR_PD_SHIFT (12U)
2408 #define DDRPHY_MR_PD_SET(x) (((uint32_t)(x) << DDRPHY_MR_PD_SHIFT) & DDRPHY_MR_PD_MASK)
2409 #define DDRPHY_MR_PD_GET(x) (((uint32_t)(x) & DDRPHY_MR_PD_MASK) >> DDRPHY_MR_PD_SHIFT)
2410 
2411 /*
2412  * WR (R/W)
2413  *
2414  * Write Recovery: This is the value of the write recovery. It is calculated by dividing the datasheet write recovery time, tWR (ns) by the datasheet clock cycle time, tCK (ns) and rounding up a non-integer value to the next integer. Valid values are:
2415  * 001 = 2
2416  * 010 = 3
2417  * 011 = 4
2418  * 100 = 5
2419  * 101 = 6
2420  * All other settings are reserved and should not be used.
2421  * NOTE: tWR (ns) is the time from the first SDRAM positive clock edge after the last data-in pair of a write command, to when a precharge of the same bank can be issued.
2422  */
2423 #define DDRPHY_MR_WR_MASK (0xE00U)
2424 #define DDRPHY_MR_WR_SHIFT (9U)
2425 #define DDRPHY_MR_WR_SET(x) (((uint32_t)(x) << DDRPHY_MR_WR_SHIFT) & DDRPHY_MR_WR_MASK)
2426 #define DDRPHY_MR_WR_GET(x) (((uint32_t)(x) & DDRPHY_MR_WR_MASK) >> DDRPHY_MR_WR_SHIFT)
2427 
2428 /*
2429  * DR (R/W)
2430  *
2431  * DLL Reset: Writing a ‘1’ to this bit will reset the SDRAM DLL. This bit is self- clearing, i.e. it returns back to ‘0’ after the DLL reset has been issued.
2432  */
2433 #define DDRPHY_MR_DR_MASK (0x100U)
2434 #define DDRPHY_MR_DR_SHIFT (8U)
2435 #define DDRPHY_MR_DR_SET(x) (((uint32_t)(x) << DDRPHY_MR_DR_SHIFT) & DDRPHY_MR_DR_MASK)
2436 #define DDRPHY_MR_DR_GET(x) (((uint32_t)(x) & DDRPHY_MR_DR_MASK) >> DDRPHY_MR_DR_SHIFT)
2437 
2438 /*
2439  * TM (R/W)
2440  *
2441  * Operating Mode: Selects either normal operating mode (0) or test mode (1). Test mode is reserved for the manufacturer and should not be used.
2442  */
2443 #define DDRPHY_MR_TM_MASK (0x80U)
2444 #define DDRPHY_MR_TM_SHIFT (7U)
2445 #define DDRPHY_MR_TM_SET(x) (((uint32_t)(x) << DDRPHY_MR_TM_SHIFT) & DDRPHY_MR_TM_MASK)
2446 #define DDRPHY_MR_TM_GET(x) (((uint32_t)(x) & DDRPHY_MR_TM_MASK) >> DDRPHY_MR_TM_SHIFT)
2447 
2448 /*
2449  * CL (R/W)
2450  *
2451  * CAS Latency: The delay between when the SDRAM registers a read command to when data is available. Valid values are:
2452  * 010 = 2
2453  * 011 = 3
2454  * 100 = 4
2455  * 101 = 5
2456  * 110 = 6
2457  * 111 = 7
2458  * All other settings are reserved and should not be used.
2459  */
2460 #define DDRPHY_MR_CL_MASK (0x70U)
2461 #define DDRPHY_MR_CL_SHIFT (4U)
2462 #define DDRPHY_MR_CL_SET(x) (((uint32_t)(x) << DDRPHY_MR_CL_SHIFT) & DDRPHY_MR_CL_MASK)
2463 #define DDRPHY_MR_CL_GET(x) (((uint32_t)(x) & DDRPHY_MR_CL_MASK) >> DDRPHY_MR_CL_SHIFT)
2464 
2465 /*
2466  * BT (R/W)
2467  *
2468  * Burst Type: Indicates whether a burst is sequential (0) or interleaved (1).
2469  */
2470 #define DDRPHY_MR_BT_MASK (0x8U)
2471 #define DDRPHY_MR_BT_SHIFT (3U)
2472 #define DDRPHY_MR_BT_SET(x) (((uint32_t)(x) << DDRPHY_MR_BT_SHIFT) & DDRPHY_MR_BT_MASK)
2473 #define DDRPHY_MR_BT_GET(x) (((uint32_t)(x) & DDRPHY_MR_BT_MASK) >> DDRPHY_MR_BT_SHIFT)
2474 
2475 /*
2476  * BL (R/W)
2477  *
2478  * Burst Length: Determines the maximum number of column locations that can be accessed during a given read or write command. Valid values are:
2479  * 010 = 4
2480  * 011 = 8
2481  * All other settings are reserved and should not be used.
2482  */
2483 #define DDRPHY_MR_BL_MASK (0x7U)
2484 #define DDRPHY_MR_BL_SHIFT (0U)
2485 #define DDRPHY_MR_BL_SET(x) (((uint32_t)(x) << DDRPHY_MR_BL_SHIFT) & DDRPHY_MR_BL_MASK)
2486 #define DDRPHY_MR_BL_GET(x) (((uint32_t)(x) & DDRPHY_MR_BL_MASK) >> DDRPHY_MR_BL_SHIFT)
2487 
2488 /* Bitfield definition for register: MR1 */
2489 /*
2490  * QOFF (R/W)
2491  *
2492  * Output Enable/Disable: When ‘0’, all outputs function normal; when ‘1’ all SDRAM outputs are disabled removing output buffer current. This feature is intended to be used for IDD characterization of read current and should not be used in normal operation.
2493  */
2494 #define DDRPHY_MR1_QOFF_MASK (0x1000U)
2495 #define DDRPHY_MR1_QOFF_SHIFT (12U)
2496 #define DDRPHY_MR1_QOFF_SET(x) (((uint32_t)(x) << DDRPHY_MR1_QOFF_SHIFT) & DDRPHY_MR1_QOFF_MASK)
2497 #define DDRPHY_MR1_QOFF_GET(x) (((uint32_t)(x) & DDRPHY_MR1_QOFF_MASK) >> DDRPHY_MR1_QOFF_SHIFT)
2498 
2499 /*
2500  * TDQS (R/W)
2501  *
2502  * Termination Data Strobe: When enabled (‘1’) TDQS provides additional termination resistance outputs that may be useful in some system configurations. Refer to the SDRAM datasheet for details.
2503  */
2504 #define DDRPHY_MR1_TDQS_MASK (0x800U)
2505 #define DDRPHY_MR1_TDQS_SHIFT (11U)
2506 #define DDRPHY_MR1_TDQS_SET(x) (((uint32_t)(x) << DDRPHY_MR1_TDQS_SHIFT) & DDRPHY_MR1_TDQS_MASK)
2507 #define DDRPHY_MR1_TDQS_GET(x) (((uint32_t)(x) & DDRPHY_MR1_TDQS_MASK) >> DDRPHY_MR1_TDQS_SHIFT)
2508 
2509 /*
2510  * RTTH (R/W)
2511  *
2512  * On Die Termination high bit
2513  */
2514 #define DDRPHY_MR1_RTTH_MASK (0x200U)
2515 #define DDRPHY_MR1_RTTH_SHIFT (9U)
2516 #define DDRPHY_MR1_RTTH_SET(x) (((uint32_t)(x) << DDRPHY_MR1_RTTH_SHIFT) & DDRPHY_MR1_RTTH_MASK)
2517 #define DDRPHY_MR1_RTTH_GET(x) (((uint32_t)(x) & DDRPHY_MR1_RTTH_MASK) >> DDRPHY_MR1_RTTH_SHIFT)
2518 
2519 /*
2520  * LEVEL (R/W)
2521  *
2522  * Write Leveling Enable: Enables write-leveling when set.
2523  */
2524 #define DDRPHY_MR1_LEVEL_MASK (0x80U)
2525 #define DDRPHY_MR1_LEVEL_SHIFT (7U)
2526 #define DDRPHY_MR1_LEVEL_SET(x) (((uint32_t)(x) << DDRPHY_MR1_LEVEL_SHIFT) & DDRPHY_MR1_LEVEL_MASK)
2527 #define DDRPHY_MR1_LEVEL_GET(x) (((uint32_t)(x) & DDRPHY_MR1_LEVEL_MASK) >> DDRPHY_MR1_LEVEL_SHIFT)
2528 
2529 /*
2530  * RTTM (R/W)
2531  *
2532  * On Die Termination mid bit:
2533  * Selects the effective resistance for SDRAM on die termination. Valid values are:
2534  * 000 = ODT disabled 001 = RZQ/4
2535  * 010 = RZQ/2
2536  * 011 = RZQ/6
2537  * 100 = RZQ/12
2538  * 101 = RZQ/8
2539  * All other settings are reserved and should not be used.
2540  * Bit on [9, 6,2]
2541  */
2542 #define DDRPHY_MR1_RTTM_MASK (0x40U)
2543 #define DDRPHY_MR1_RTTM_SHIFT (6U)
2544 #define DDRPHY_MR1_RTTM_SET(x) (((uint32_t)(x) << DDRPHY_MR1_RTTM_SHIFT) & DDRPHY_MR1_RTTM_MASK)
2545 #define DDRPHY_MR1_RTTM_GET(x) (((uint32_t)(x) & DDRPHY_MR1_RTTM_MASK) >> DDRPHY_MR1_RTTM_SHIFT)
2546 
2547 /*
2548  * DICH (R/W)
2549  *
2550  * Output Driver Impedance Control high bit:
2551  * Controls the output drive strength. Valid values are:
2552  * 00 = RZQ/6
2553  * 01 = RZQ7
2554  * 10 = Reserved
2555  * 11 = Reserved
2556  */
2557 #define DDRPHY_MR1_DICH_MASK (0x20U)
2558 #define DDRPHY_MR1_DICH_SHIFT (5U)
2559 #define DDRPHY_MR1_DICH_SET(x) (((uint32_t)(x) << DDRPHY_MR1_DICH_SHIFT) & DDRPHY_MR1_DICH_MASK)
2560 #define DDRPHY_MR1_DICH_GET(x) (((uint32_t)(x) & DDRPHY_MR1_DICH_MASK) >> DDRPHY_MR1_DICH_SHIFT)
2561 
2562 /*
2563  * AL (R/W)
2564  *
2565  * Posted CAS Additive Latency: Setting additive latency that allows read and write commands to be issued to the SDRAM earlier than normal (refer to the SDRAM datasheet for details). Valid values are:
2566  * 00 = 0 (AL disabled)
2567  * 01 = CL - 1
2568  * 10 = CL - 2
2569  * 11 = Reserved
2570  */
2571 #define DDRPHY_MR1_AL_MASK (0x18U)
2572 #define DDRPHY_MR1_AL_SHIFT (3U)
2573 #define DDRPHY_MR1_AL_SET(x) (((uint32_t)(x) << DDRPHY_MR1_AL_SHIFT) & DDRPHY_MR1_AL_MASK)
2574 #define DDRPHY_MR1_AL_GET(x) (((uint32_t)(x) & DDRPHY_MR1_AL_MASK) >> DDRPHY_MR1_AL_SHIFT)
2575 
2576 /*
2577  * RTTL (R/W)
2578  *
2579  * On Die Termination low bit
2580  */
2581 #define DDRPHY_MR1_RTTL_MASK (0x4U)
2582 #define DDRPHY_MR1_RTTL_SHIFT (2U)
2583 #define DDRPHY_MR1_RTTL_SET(x) (((uint32_t)(x) << DDRPHY_MR1_RTTL_SHIFT) & DDRPHY_MR1_RTTL_MASK)
2584 #define DDRPHY_MR1_RTTL_GET(x) (((uint32_t)(x) & DDRPHY_MR1_RTTL_MASK) >> DDRPHY_MR1_RTTL_SHIFT)
2585 
2586 /*
2587  * DICL (R/W)
2588  *
2589  * Output Driver Impedance Control low bit
2590  */
2591 #define DDRPHY_MR1_DICL_MASK (0x2U)
2592 #define DDRPHY_MR1_DICL_SHIFT (1U)
2593 #define DDRPHY_MR1_DICL_SET(x) (((uint32_t)(x) << DDRPHY_MR1_DICL_SHIFT) & DDRPHY_MR1_DICL_MASK)
2594 #define DDRPHY_MR1_DICL_GET(x) (((uint32_t)(x) & DDRPHY_MR1_DICL_MASK) >> DDRPHY_MR1_DICL_SHIFT)
2595 
2596 /*
2597  * DE (R/W)
2598  *
2599  * DLL Enable/Disable: Enable (0) or disable (1) the DLL. DLL must be enabled for normal operation.
2600  * Note: SDRAM DLL off mode is not supported
2601  */
2602 #define DDRPHY_MR1_DE_MASK (0x1U)
2603 #define DDRPHY_MR1_DE_SHIFT (0U)
2604 #define DDRPHY_MR1_DE_SET(x) (((uint32_t)(x) << DDRPHY_MR1_DE_SHIFT) & DDRPHY_MR1_DE_MASK)
2605 #define DDRPHY_MR1_DE_GET(x) (((uint32_t)(x) & DDRPHY_MR1_DE_MASK) >> DDRPHY_MR1_DE_SHIFT)
2606 
2607 /* Bitfield definition for register: EMR */
2608 /*
2609  * QOFF (R/W)
2610  *
2611  * Output Enable/Disable: When ‘0’, all outputs function normal; when ‘1’ all SDRAM outputs are disabled removing output buffer current. This feature is intended to be
2612  * used for IDD characterization of read current and should not be used in normal operation.
2613  */
2614 #define DDRPHY_EMR_QOFF_MASK (0x1000U)
2615 #define DDRPHY_EMR_QOFF_SHIFT (12U)
2616 #define DDRPHY_EMR_QOFF_SET(x) (((uint32_t)(x) << DDRPHY_EMR_QOFF_SHIFT) & DDRPHY_EMR_QOFF_MASK)
2617 #define DDRPHY_EMR_QOFF_GET(x) (((uint32_t)(x) & DDRPHY_EMR_QOFF_MASK) >> DDRPHY_EMR_QOFF_SHIFT)
2618 
2619 /*
2620  * RDQS (R/W)
2621  *
2622  * RDQS Enable/Disable: When enabled (‘1’), RDQS is identical in function and timing to data strobe DQS during a read, and ignored during a write. A ‘0’ disables the SDRAM from driving RDQS. The Controller does not allow the user to change this bit.
2623  */
2624 #define DDRPHY_EMR_RDQS_MASK (0x800U)
2625 #define DDRPHY_EMR_RDQS_SHIFT (11U)
2626 #define DDRPHY_EMR_RDQS_SET(x) (((uint32_t)(x) << DDRPHY_EMR_RDQS_SHIFT) & DDRPHY_EMR_RDQS_MASK)
2627 #define DDRPHY_EMR_RDQS_GET(x) (((uint32_t)(x) & DDRPHY_EMR_RDQS_MASK) >> DDRPHY_EMR_RDQS_SHIFT)
2628 
2629 /*
2630  * DQS (R/W)
2631  *
2632  * DQS_b Enable/Disable: When ‘0’, DQS_b is the complement of the differential data strobe pair DQS/DQS_b. When ‘1’, DQS is used in a single-ended mode and the DQS_b pin is disabled. Also used to similarly enable/disable RDQS_b if RDQS is enabled. The Controller does not allow the user to change this bit.
2633  */
2634 #define DDRPHY_EMR_DQS_MASK (0x400U)
2635 #define DDRPHY_EMR_DQS_SHIFT (10U)
2636 #define DDRPHY_EMR_DQS_SET(x) (((uint32_t)(x) << DDRPHY_EMR_DQS_SHIFT) & DDRPHY_EMR_DQS_MASK)
2637 #define DDRPHY_EMR_DQS_GET(x) (((uint32_t)(x) & DDRPHY_EMR_DQS_MASK) >> DDRPHY_EMR_DQS_SHIFT)
2638 
2639 /*
2640  * OCD (R/W)
2641  *
2642  * Off-Chip Driver (OCD) Impedance Calibration: Used to calibrate and match pull-up to pull- down impedance to 18  nominal (refer to the SDRAM datasheet for details). Valid values are:
2643  * 000 = OCD calibration mode exit 001 = Drive (1) pull-up
2644  * 010 = Drive (0) pull-down
2645  * 100 = OCD enter adjust mode 111 = OCD calibration default
2646  * All other settings are reserved and should not be used. Note that OCD is not supported by all vendors. Refer to the SDRAM datasheet for details on the recommended OCD settings.
2647  */
2648 #define DDRPHY_EMR_OCD_MASK (0x380U)
2649 #define DDRPHY_EMR_OCD_SHIFT (7U)
2650 #define DDRPHY_EMR_OCD_SET(x) (((uint32_t)(x) << DDRPHY_EMR_OCD_SHIFT) & DDRPHY_EMR_OCD_MASK)
2651 #define DDRPHY_EMR_OCD_GET(x) (((uint32_t)(x) & DDRPHY_EMR_OCD_MASK) >> DDRPHY_EMR_OCD_SHIFT)
2652 
2653 /*
2654  * RTTH (R/W)
2655  *
2656  * On Die Termination high bit:
2657  * Selects the effective resistance for SDRAM on die termination. Valid values are:
2658  * 00 = ODT disabled 01 = 75
2659  * 10 = 150
2660  * 11 = 50 (some vendors)
2661  */
2662 #define DDRPHY_EMR_RTTH_MASK (0x40U)
2663 #define DDRPHY_EMR_RTTH_SHIFT (6U)
2664 #define DDRPHY_EMR_RTTH_SET(x) (((uint32_t)(x) << DDRPHY_EMR_RTTH_SHIFT) & DDRPHY_EMR_RTTH_MASK)
2665 #define DDRPHY_EMR_RTTH_GET(x) (((uint32_t)(x) & DDRPHY_EMR_RTTH_MASK) >> DDRPHY_EMR_RTTH_SHIFT)
2666 
2667 /*
2668  * AL (R/W)
2669  *
2670  * Posted CAS Additive Latency: Setting additive latency that allows read and write commands to be issued to the SDRAM earlier than normal (refer to the SDRAM datasheet for details). Valid values are:
2671  * 000 = 0
2672  * 001 = 1
2673  * 010 = 2
2674  * 011 = 3
2675  * 100 = 4
2676  * 101 = 5
2677  * All other settings are reserved and should not be used. The maximum allowed value of AL is tRCD-1.
2678  */
2679 #define DDRPHY_EMR_AL_MASK (0x38U)
2680 #define DDRPHY_EMR_AL_SHIFT (3U)
2681 #define DDRPHY_EMR_AL_SET(x) (((uint32_t)(x) << DDRPHY_EMR_AL_SHIFT) & DDRPHY_EMR_AL_MASK)
2682 #define DDRPHY_EMR_AL_GET(x) (((uint32_t)(x) & DDRPHY_EMR_AL_MASK) >> DDRPHY_EMR_AL_SHIFT)
2683 
2684 /*
2685  * RTTL (R/W)
2686  *
2687  * On Die Termination low bit:
2688  */
2689 #define DDRPHY_EMR_RTTL_MASK (0x4U)
2690 #define DDRPHY_EMR_RTTL_SHIFT (2U)
2691 #define DDRPHY_EMR_RTTL_SET(x) (((uint32_t)(x) << DDRPHY_EMR_RTTL_SHIFT) & DDRPHY_EMR_RTTL_MASK)
2692 #define DDRPHY_EMR_RTTL_GET(x) (((uint32_t)(x) & DDRPHY_EMR_RTTL_MASK) >> DDRPHY_EMR_RTTL_SHIFT)
2693 
2694 /*
2695  * DIC (R/W)
2696  *
2697  * Output Driver Impedance Control: Controls the output drive strength. Valid values are:
2698  * 0 = Full strength
2699  * 1 = Reduced strength
2700  */
2701 #define DDRPHY_EMR_DIC_MASK (0x2U)
2702 #define DDRPHY_EMR_DIC_SHIFT (1U)
2703 #define DDRPHY_EMR_DIC_SET(x) (((uint32_t)(x) << DDRPHY_EMR_DIC_SHIFT) & DDRPHY_EMR_DIC_MASK)
2704 #define DDRPHY_EMR_DIC_GET(x) (((uint32_t)(x) & DDRPHY_EMR_DIC_MASK) >> DDRPHY_EMR_DIC_SHIFT)
2705 
2706 /*
2707  * DE (R/W)
2708  *
2709  * DLL Enable/Disable: Enable (0) or disable (1) the DLL. DLL must be enabled for normal operation.
2710  */
2711 #define DDRPHY_EMR_DE_MASK (0x1U)
2712 #define DDRPHY_EMR_DE_SHIFT (0U)
2713 #define DDRPHY_EMR_DE_SET(x) (((uint32_t)(x) << DDRPHY_EMR_DE_SHIFT) & DDRPHY_EMR_DE_MASK)
2714 #define DDRPHY_EMR_DE_GET(x) (((uint32_t)(x) & DDRPHY_EMR_DE_MASK) >> DDRPHY_EMR_DE_SHIFT)
2715 
2716 /* Bitfield definition for register: MR2 */
2717 /*
2718  * RTTWR (R/W)
2719  *
2720  * Dynamic ODT: Selects RTT for dynamic ODT. Valid values are: 00 = Dynamic ODT off
2721  * 01 = RZQ/4
2722  * 10 = RZQ/2
2723  * 11 = Reserved
2724  */
2725 #define DDRPHY_MR2_RTTWR_MASK (0x600U)
2726 #define DDRPHY_MR2_RTTWR_SHIFT (9U)
2727 #define DDRPHY_MR2_RTTWR_SET(x) (((uint32_t)(x) << DDRPHY_MR2_RTTWR_SHIFT) & DDRPHY_MR2_RTTWR_MASK)
2728 #define DDRPHY_MR2_RTTWR_GET(x) (((uint32_t)(x) & DDRPHY_MR2_RTTWR_MASK) >> DDRPHY_MR2_RTTWR_SHIFT)
2729 
2730 /*
2731  * SRT (R/W)
2732  *
2733  * Self-Refresh Temperature Range: Selects either normal (‘0’) or extended (‘1’) operating temperature range during self-refresh.
2734  */
2735 #define DDRPHY_MR2_SRT_MASK (0x80U)
2736 #define DDRPHY_MR2_SRT_SHIFT (7U)
2737 #define DDRPHY_MR2_SRT_SET(x) (((uint32_t)(x) << DDRPHY_MR2_SRT_SHIFT) & DDRPHY_MR2_SRT_MASK)
2738 #define DDRPHY_MR2_SRT_GET(x) (((uint32_t)(x) & DDRPHY_MR2_SRT_MASK) >> DDRPHY_MR2_SRT_SHIFT)
2739 
2740 /*
2741  * ASR (R/W)
2742  *
2743  * Auto Self-Refresh: When enabled (‘1’), SDRAM automatically provides self-refresh power management functions for all supported operating temperature values.
2744  * Otherwise the SRT bit must be programmed to indicate the temperature range.
2745  */
2746 #define DDRPHY_MR2_ASR_MASK (0x40U)
2747 #define DDRPHY_MR2_ASR_SHIFT (6U)
2748 #define DDRPHY_MR2_ASR_SET(x) (((uint32_t)(x) << DDRPHY_MR2_ASR_SHIFT) & DDRPHY_MR2_ASR_MASK)
2749 #define DDRPHY_MR2_ASR_GET(x) (((uint32_t)(x) & DDRPHY_MR2_ASR_MASK) >> DDRPHY_MR2_ASR_SHIFT)
2750 
2751 /*
2752  * CWL (R/W)
2753  *
2754  * CAS Write Latency: The delay between when the SDRAM registers a write command to when write data is available. Valid values are:
2755  * 000 = 5 (tCK > 2.5ns)
2756  * 001 = 6 (2.5ns > tCK > 1.875ns)
2757  * 010 = 7 (1.875ns > tCK> 1.5ns)
2758  * 011 = 8 (1.5ns > tCK > 1.25ns)
2759  * 100 = 9 (1.25ns > tCK > 1.07ns)
2760  * 101 = 10 (1.07ns > tCK > 0.935ns)
2761  * 110 = 11 (0.935ns > tCK > 0.833ns)
2762  * 111 = 12 (0.833ns > tCK > 0.75ns)
2763  * All other settings are reserved and should not be used.
2764  */
2765 #define DDRPHY_MR2_CWL_MASK (0x38U)
2766 #define DDRPHY_MR2_CWL_SHIFT (3U)
2767 #define DDRPHY_MR2_CWL_SET(x) (((uint32_t)(x) << DDRPHY_MR2_CWL_SHIFT) & DDRPHY_MR2_CWL_MASK)
2768 #define DDRPHY_MR2_CWL_GET(x) (((uint32_t)(x) & DDRPHY_MR2_CWL_MASK) >> DDRPHY_MR2_CWL_SHIFT)
2769 
2770 /*
2771  * PASR (R/W)
2772  *
2773  * Partial Array Self Refresh: Specifies that data located in areas of the array beyond the specified location will be lost if self refresh is entered.
2774  * Valid settings for 4 banks are:
2775  * 000 = Full Array
2776  * 001 = Half Array (BA[1:0] = 00 & 01)
2777  * 010 = Quarter Array (BA[1:0] = 00) 011 = Not defined
2778  * 100 = 3/4 Array (BA[1:0] = 01, 10, & 11)
2779  * 101 = Half Array (BA[1:0] = 10 & 11)
2780  * 110 = Quarter Array (BA[1:0] = 11) 111 = Not defined
2781  * Valid settings for 8 banks are:
2782  * 000 = Full Array
2783  * 001 = Half Array (BA[2:0] = 000, 001, 010 & 011)
2784  * 010 = Quarter Array (BA[2:0] = 000, 001) 011 = 1/8 Array (BA[2:0] = 000)
2785  * 100 = 3/4 Array (BA[2:0] = 010, 011, 100, 101, 110 & 111)
2786  * 101 = Half Array (BA[2:0] = 100, 101, 110 & 111)
2787  * 110 = Quarter Array (BA[2:0] = 110 & 111)
2788  * 111 = 1/8 Array (BA[2:0] 111)
2789  */
2790 #define DDRPHY_MR2_PASR_MASK (0x7U)
2791 #define DDRPHY_MR2_PASR_SHIFT (0U)
2792 #define DDRPHY_MR2_PASR_SET(x) (((uint32_t)(x) << DDRPHY_MR2_PASR_SHIFT) & DDRPHY_MR2_PASR_MASK)
2793 #define DDRPHY_MR2_PASR_GET(x) (((uint32_t)(x) & DDRPHY_MR2_PASR_MASK) >> DDRPHY_MR2_PASR_SHIFT)
2794 
2795 /* Bitfield definition for register: EMR2 */
2796 /*
2797  * SRF (R/W)
2798  *
2799  * Self Refresh Rate: Enables, if set, high temperature self refresh rate.
2800  */
2801 #define DDRPHY_EMR2_SRF_MASK (0x80U)
2802 #define DDRPHY_EMR2_SRF_SHIFT (7U)
2803 #define DDRPHY_EMR2_SRF_SET(x) (((uint32_t)(x) << DDRPHY_EMR2_SRF_SHIFT) & DDRPHY_EMR2_SRF_MASK)
2804 #define DDRPHY_EMR2_SRF_GET(x) (((uint32_t)(x) & DDRPHY_EMR2_SRF_MASK) >> DDRPHY_EMR2_SRF_SHIFT)
2805 
2806 /*
2807  * DCC (R/W)
2808  *
2809  * Duty Cycle Corrector: Enables, if set, duty cycle correction within SDRAM.
2810  */
2811 #define DDRPHY_EMR2_DCC_MASK (0x8U)
2812 #define DDRPHY_EMR2_DCC_SHIFT (3U)
2813 #define DDRPHY_EMR2_DCC_SET(x) (((uint32_t)(x) << DDRPHY_EMR2_DCC_SHIFT) & DDRPHY_EMR2_DCC_MASK)
2814 #define DDRPHY_EMR2_DCC_GET(x) (((uint32_t)(x) & DDRPHY_EMR2_DCC_MASK) >> DDRPHY_EMR2_DCC_SHIFT)
2815 
2816 /*
2817  * PASR (R/W)
2818  *
2819  * Partial Array Self Refresh: Specifies that data located in areas of the array beyond the specified location will be lost if self refresh is entered.
2820  * Valid settings for 4 banks are:
2821  * 000 = Full Array
2822  * 001 = Half Array (BA[1:0] = 00 & 01)
2823  * 010 = Quarter Array (BA[1:0] = 00) 011 = Not defined
2824  * 100 = 3/4 Array (BA[1:0] = 01, 10, & 11)
2825  * 101 = Half Array (BA[1:0] = 10 & 11)
2826  * 110 = Quarter Array (BA[1:0] = 11) 111 = Not defined
2827  * Valid settings for 8 banks are:
2828  * 000 = Full Array
2829  * 001 = Half Array (BA[2:0] = 000, 001, 010 & 011)
2830  * 010 = Quarter Array (BA[2:0] = 000, 001) 011 = 1/8 Array (BA[2:0] = 000)
2831  * 100 = 3/4 Array (BA[2:0] = 010, 011, 100, 101, 110 & 111)
2832  * 101 = Half Array (BA[2:0] = 100, 101, 110 & 111)
2833  * 110 = Quarter Array (BA[2:0] = 110 & 111)
2834  * 111 = 1/8 Array (BA[2:0] 111)
2835  */
2836 #define DDRPHY_EMR2_PASR_MASK (0x7U)
2837 #define DDRPHY_EMR2_PASR_SHIFT (0U)
2838 #define DDRPHY_EMR2_PASR_SET(x) (((uint32_t)(x) << DDRPHY_EMR2_PASR_SHIFT) & DDRPHY_EMR2_PASR_MASK)
2839 #define DDRPHY_EMR2_PASR_GET(x) (((uint32_t)(x) & DDRPHY_EMR2_PASR_MASK) >> DDRPHY_EMR2_PASR_SHIFT)
2840 
2841 /* Bitfield definition for register: MR3 */
2842 /*
2843  * MPR (R/W)
2844  *
2845  * Multi-Purpose Register Enable: Enables, if set, that read data should come from the Multi-Purpose Register. Otherwise read data come from the DRAM array.
2846  */
2847 #define DDRPHY_MR3_MPR_MASK (0x4U)
2848 #define DDRPHY_MR3_MPR_SHIFT (2U)
2849 #define DDRPHY_MR3_MPR_SET(x) (((uint32_t)(x) << DDRPHY_MR3_MPR_SHIFT) & DDRPHY_MR3_MPR_MASK)
2850 #define DDRPHY_MR3_MPR_GET(x) (((uint32_t)(x) & DDRPHY_MR3_MPR_MASK) >> DDRPHY_MR3_MPR_SHIFT)
2851 
2852 /*
2853  * MPRLOC (R/W)
2854  *
2855  * Multi-Purpose Register (MPR) Location: Selects MPR data location: Valid value are: 00 = Predefined pattern for system calibration
2856  * All other settings are reserved and should not be used.
2857  */
2858 #define DDRPHY_MR3_MPRLOC_MASK (0x3U)
2859 #define DDRPHY_MR3_MPRLOC_SHIFT (0U)
2860 #define DDRPHY_MR3_MPRLOC_SET(x) (((uint32_t)(x) << DDRPHY_MR3_MPRLOC_SHIFT) & DDRPHY_MR3_MPRLOC_MASK)
2861 #define DDRPHY_MR3_MPRLOC_GET(x) (((uint32_t)(x) & DDRPHY_MR3_MPRLOC_MASK) >> DDRPHY_MR3_MPRLOC_SHIFT)
2862 
2863 /* Bitfield definition for register: EMR3 */
2864 /* Bitfield definition for register: ODTCR */
2865 /*
2866  * WRODT3 (R/W)
2867  *
2868  */
2869 #define DDRPHY_ODTCR_WRODT3_MASK (0xF0000000UL)
2870 #define DDRPHY_ODTCR_WRODT3_SHIFT (28U)
2871 #define DDRPHY_ODTCR_WRODT3_SET(x) (((uint32_t)(x) << DDRPHY_ODTCR_WRODT3_SHIFT) & DDRPHY_ODTCR_WRODT3_MASK)
2872 #define DDRPHY_ODTCR_WRODT3_GET(x) (((uint32_t)(x) & DDRPHY_ODTCR_WRODT3_MASK) >> DDRPHY_ODTCR_WRODT3_SHIFT)
2873 
2874 /*
2875  * WRODT2 (R/W)
2876  *
2877  */
2878 #define DDRPHY_ODTCR_WRODT2_MASK (0xF000000UL)
2879 #define DDRPHY_ODTCR_WRODT2_SHIFT (24U)
2880 #define DDRPHY_ODTCR_WRODT2_SET(x) (((uint32_t)(x) << DDRPHY_ODTCR_WRODT2_SHIFT) & DDRPHY_ODTCR_WRODT2_MASK)
2881 #define DDRPHY_ODTCR_WRODT2_GET(x) (((uint32_t)(x) & DDRPHY_ODTCR_WRODT2_MASK) >> DDRPHY_ODTCR_WRODT2_SHIFT)
2882 
2883 /*
2884  * WRODT1 (R/W)
2885  *
2886  */
2887 #define DDRPHY_ODTCR_WRODT1_MASK (0xF00000UL)
2888 #define DDRPHY_ODTCR_WRODT1_SHIFT (20U)
2889 #define DDRPHY_ODTCR_WRODT1_SET(x) (((uint32_t)(x) << DDRPHY_ODTCR_WRODT1_SHIFT) & DDRPHY_ODTCR_WRODT1_MASK)
2890 #define DDRPHY_ODTCR_WRODT1_GET(x) (((uint32_t)(x) & DDRPHY_ODTCR_WRODT1_MASK) >> DDRPHY_ODTCR_WRODT1_SHIFT)
2891 
2892 /*
2893  * WRODT0 (R/W)
2894  *
2895  * Write ODT: Specifies whether ODT should be enabled (‘1’) or disabled (‘0’) on each of the up to four ranks when a write command is sent to rank n. WRODT0, WRODT1, WRODT2, and WRODT3 specify ODT settings when a write is to rank 0, rank 1, rank 2, and rank 3, respectively. The four bits of each field each represent a rank, the LSB being rank 0 and the MSB being rank 3. Default is to enable ODT only on rank being written to.
2896  */
2897 #define DDRPHY_ODTCR_WRODT0_MASK (0xF0000UL)
2898 #define DDRPHY_ODTCR_WRODT0_SHIFT (16U)
2899 #define DDRPHY_ODTCR_WRODT0_SET(x) (((uint32_t)(x) << DDRPHY_ODTCR_WRODT0_SHIFT) & DDRPHY_ODTCR_WRODT0_MASK)
2900 #define DDRPHY_ODTCR_WRODT0_GET(x) (((uint32_t)(x) & DDRPHY_ODTCR_WRODT0_MASK) >> DDRPHY_ODTCR_WRODT0_SHIFT)
2901 
2902 /*
2903  * RDODT3 (R/W)
2904  *
2905  */
2906 #define DDRPHY_ODTCR_RDODT3_MASK (0xF000U)
2907 #define DDRPHY_ODTCR_RDODT3_SHIFT (12U)
2908 #define DDRPHY_ODTCR_RDODT3_SET(x) (((uint32_t)(x) << DDRPHY_ODTCR_RDODT3_SHIFT) & DDRPHY_ODTCR_RDODT3_MASK)
2909 #define DDRPHY_ODTCR_RDODT3_GET(x) (((uint32_t)(x) & DDRPHY_ODTCR_RDODT3_MASK) >> DDRPHY_ODTCR_RDODT3_SHIFT)
2910 
2911 /*
2912  * RDODT2 (R/W)
2913  *
2914  */
2915 #define DDRPHY_ODTCR_RDODT2_MASK (0xF00U)
2916 #define DDRPHY_ODTCR_RDODT2_SHIFT (8U)
2917 #define DDRPHY_ODTCR_RDODT2_SET(x) (((uint32_t)(x) << DDRPHY_ODTCR_RDODT2_SHIFT) & DDRPHY_ODTCR_RDODT2_MASK)
2918 #define DDRPHY_ODTCR_RDODT2_GET(x) (((uint32_t)(x) & DDRPHY_ODTCR_RDODT2_MASK) >> DDRPHY_ODTCR_RDODT2_SHIFT)
2919 
2920 /*
2921  * RDODT1 (R/W)
2922  *
2923  */
2924 #define DDRPHY_ODTCR_RDODT1_MASK (0xF0U)
2925 #define DDRPHY_ODTCR_RDODT1_SHIFT (4U)
2926 #define DDRPHY_ODTCR_RDODT1_SET(x) (((uint32_t)(x) << DDRPHY_ODTCR_RDODT1_SHIFT) & DDRPHY_ODTCR_RDODT1_MASK)
2927 #define DDRPHY_ODTCR_RDODT1_GET(x) (((uint32_t)(x) & DDRPHY_ODTCR_RDODT1_MASK) >> DDRPHY_ODTCR_RDODT1_SHIFT)
2928 
2929 /*
2930  * RDODT0 (R/W)
2931  *
2932  * Read ODT: Specifies whether ODT should be enabled (‘1’) or disabled (‘0’) on each of the up to four ranks when a read command is sent to rank n. RDODT0, RDODT1, RDODT2, and RDODT3 specify ODT settings when a read is to rank 0, rank 1, rank 2, and rank 3, respectively. The four bits of each field each represent a rank, the LSB being rank 0 and the MSB being rank 3. Default is to disable ODT during reads.
2933  */
2934 #define DDRPHY_ODTCR_RDODT0_MASK (0xFU)
2935 #define DDRPHY_ODTCR_RDODT0_SHIFT (0U)
2936 #define DDRPHY_ODTCR_RDODT0_SET(x) (((uint32_t)(x) << DDRPHY_ODTCR_RDODT0_SHIFT) & DDRPHY_ODTCR_RDODT0_MASK)
2937 #define DDRPHY_ODTCR_RDODT0_GET(x) (((uint32_t)(x) & DDRPHY_ODTCR_RDODT0_MASK) >> DDRPHY_ODTCR_RDODT0_SHIFT)
2938 
2939 /* Bitfield definition for register: DTCR */
2940 /*
2941  * RFSHDT (R/W)
2942  *
2943  * Refresh During Training: A non-zero value specifies that a burst of refreshes equal to the number specified in this field should be sent to the SDRAM after training each rank except the last rank.
2944  */
2945 #define DDRPHY_DTCR_RFSHDT_MASK (0xF0000000UL)
2946 #define DDRPHY_DTCR_RFSHDT_SHIFT (28U)
2947 #define DDRPHY_DTCR_RFSHDT_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_RFSHDT_SHIFT) & DDRPHY_DTCR_RFSHDT_MASK)
2948 #define DDRPHY_DTCR_RFSHDT_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_RFSHDT_MASK) >> DDRPHY_DTCR_RFSHDT_SHIFT)
2949 
2950 /*
2951  * RANKEN (R/W)
2952  *
2953  * Rank Enable: Specifies the ranks that are enabled for data-training. Bit 0 controls rank 0, bit 1 controls rank 1, bit 2 controls rank 2, and bit 3 controls rank 3. Setting the bit to ‘1’ enables the rank, and setting it to ‘0’ disables the rank.
2954  */
2955 #define DDRPHY_DTCR_RANKEN_MASK (0xF000000UL)
2956 #define DDRPHY_DTCR_RANKEN_SHIFT (24U)
2957 #define DDRPHY_DTCR_RANKEN_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_RANKEN_SHIFT) & DDRPHY_DTCR_RANKEN_MASK)
2958 #define DDRPHY_DTCR_RANKEN_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_RANKEN_MASK) >> DDRPHY_DTCR_RANKEN_SHIFT)
2959 
2960 /*
2961  * DTEXD (R/W)
2962  *
2963  * Data Training Extended Write DQS: Enables, if set, an extended write DQS whereby two additional pulses of DQS are added as post-amble to a burst of writes.
2964  * Generally this should only be enabled when running read bit deskew with the intention of performing read eye deskew prior to running write leveling adjustment.
2965  */
2966 #define DDRPHY_DTCR_DTEXD_MASK (0x400000UL)
2967 #define DDRPHY_DTCR_DTEXD_SHIFT (22U)
2968 #define DDRPHY_DTCR_DTEXD_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_DTEXD_SHIFT) & DDRPHY_DTCR_DTEXD_MASK)
2969 #define DDRPHY_DTCR_DTEXD_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_DTEXD_MASK) >> DDRPHY_DTCR_DTEXD_SHIFT)
2970 
2971 /*
2972  * DTDSTP (R/W)
2973  *
2974  * Data Training Debug Step: A write of 1 to this bit steps the data training algorithm through a single step. This bit is used to initiate one step of the data training algorithm in question.
2975  * This bit is self-clearing. To trigger the next step, this bit must be written to again. Note: The training steps must be repeated in order to get new data in the “Data Training Eye Data Register 0-1 (DTEDR0-1)” on page 122. For example, to see the
2976  * training results for a different lane, select that lane and repeat the training steps to
2977  * populate DTEDR0 and DTEDR1 with the correct data.
2978  */
2979 #define DDRPHY_DTCR_DTDSTP_MASK (0x200000UL)
2980 #define DDRPHY_DTCR_DTDSTP_SHIFT (21U)
2981 #define DDRPHY_DTCR_DTDSTP_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_DTDSTP_SHIFT) & DDRPHY_DTCR_DTDSTP_MASK)
2982 #define DDRPHY_DTCR_DTDSTP_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_DTDSTP_MASK) >> DDRPHY_DTCR_DTDSTP_SHIFT)
2983 
2984 /*
2985  * DTDEN (R/W)
2986  *
2987  * Data Training Debug Enable: Enables, if set, the data training single step debug mode.
2988  */
2989 #define DDRPHY_DTCR_DTDEN_MASK (0x100000UL)
2990 #define DDRPHY_DTCR_DTDEN_SHIFT (20U)
2991 #define DDRPHY_DTCR_DTDEN_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_DTDEN_SHIFT) & DDRPHY_DTCR_DTDEN_MASK)
2992 #define DDRPHY_DTCR_DTDEN_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_DTDEN_MASK) >> DDRPHY_DTCR_DTDEN_SHIFT)
2993 
2994 /*
2995  * DTDBS (R/W)
2996  *
2997  * Data Training Debug Byte Select: Selects the byte during data training single step debug mode.
2998  * Note: DTDEN is not used to enable this feature.
2999  */
3000 #define DDRPHY_DTCR_DTDBS_MASK (0xF0000UL)
3001 #define DDRPHY_DTCR_DTDBS_SHIFT (16U)
3002 #define DDRPHY_DTCR_DTDBS_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_DTDBS_SHIFT) & DDRPHY_DTCR_DTDBS_MASK)
3003 #define DDRPHY_DTCR_DTDBS_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_DTDBS_MASK) >> DDRPHY_DTCR_DTDBS_SHIFT)
3004 
3005 /*
3006  * DTWDQMO (R/W)
3007  *
3008  * Data Training WDQ Margin Override: If set, the Training WDQ Margin value specified in DTCR[11:8] (DTWDQM) is used during data training. Otherwise the value is computed as ¼ of the ddr_clk period measurement found during calibration of the WDQ LCDL.
3009  */
3010 #define DDRPHY_DTCR_DTWDQMO_MASK (0x4000U)
3011 #define DDRPHY_DTCR_DTWDQMO_SHIFT (14U)
3012 #define DDRPHY_DTCR_DTWDQMO_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_DTWDQMO_SHIFT) & DDRPHY_DTCR_DTWDQMO_MASK)
3013 #define DDRPHY_DTCR_DTWDQMO_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_DTWDQMO_MASK) >> DDRPHY_DTCR_DTWDQMO_SHIFT)
3014 
3015 /*
3016  * DTBDC (R/W)
3017  *
3018  * Data Training Bit Deskew Centering: Enables, if set, eye centering capability during write and read bit deskew training.
3019  */
3020 #define DDRPHY_DTCR_DTBDC_MASK (0x2000U)
3021 #define DDRPHY_DTCR_DTBDC_SHIFT (13U)
3022 #define DDRPHY_DTCR_DTBDC_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_DTBDC_SHIFT) & DDRPHY_DTCR_DTBDC_MASK)
3023 #define DDRPHY_DTCR_DTBDC_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_DTBDC_MASK) >> DDRPHY_DTCR_DTBDC_SHIFT)
3024 
3025 /*
3026  * DTWBDDM (R/W)
3027  *
3028  * Data Training Write Bit Deskew Data Mask, if set, it enables write bit deskew of the data mask
3029  */
3030 #define DDRPHY_DTCR_DTWBDDM_MASK (0x1000U)
3031 #define DDRPHY_DTCR_DTWBDDM_SHIFT (12U)
3032 #define DDRPHY_DTCR_DTWBDDM_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_DTWBDDM_SHIFT) & DDRPHY_DTCR_DTWBDDM_MASK)
3033 #define DDRPHY_DTCR_DTWBDDM_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_DTWBDDM_MASK) >> DDRPHY_DTCR_DTWBDDM_SHIFT)
3034 
3035 /*
3036  * DTWDQM (R/W)
3037  *
3038  * Training WDQ Margin: Defines how close to 0 or how close to 2*(wdq calibration_value) the WDQ LCDL can be moved during training. Basically defines how much timing margin.
3039  */
3040 #define DDRPHY_DTCR_DTWDQM_MASK (0xF00U)
3041 #define DDRPHY_DTCR_DTWDQM_SHIFT (8U)
3042 #define DDRPHY_DTCR_DTWDQM_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_DTWDQM_SHIFT) & DDRPHY_DTCR_DTWDQM_MASK)
3043 #define DDRPHY_DTCR_DTWDQM_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_DTWDQM_MASK) >> DDRPHY_DTCR_DTWDQM_SHIFT)
3044 
3045 /*
3046  * DTCMPD (R/W)
3047  *
3048  * Read Data Training Compare Data: Specifies, if set, that DQS gate training should also check if the returning read data is correct. Otherwise data-training only checks if the correct number of DQS edges were returned.
3049  */
3050 #define DDRPHY_DTCR_DTCMPD_MASK (0x80U)
3051 #define DDRPHY_DTCR_DTCMPD_SHIFT (7U)
3052 #define DDRPHY_DTCR_DTCMPD_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_DTCMPD_SHIFT) & DDRPHY_DTCR_DTCMPD_MASK)
3053 #define DDRPHY_DTCR_DTCMPD_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_DTCMPD_MASK) >> DDRPHY_DTCR_DTCMPD_SHIFT)
3054 
3055 /*
3056  * DTMPR (R/W)
3057  *
3058  * Read Data Training Using MPR (DDR3 Only): Specifies, if set, that DQS gate training should use the SDRAM Multi-Purpose Register (MPR) register. Otherwise data-training is performed by first writing to some locations in the SDRAM and then reading them back.
3059  */
3060 #define DDRPHY_DTCR_DTMPR_MASK (0x40U)
3061 #define DDRPHY_DTCR_DTMPR_SHIFT (6U)
3062 #define DDRPHY_DTCR_DTMPR_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_DTMPR_SHIFT) & DDRPHY_DTCR_DTMPR_MASK)
3063 #define DDRPHY_DTCR_DTMPR_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_DTMPR_MASK) >> DDRPHY_DTCR_DTMPR_SHIFT)
3064 
3065 /*
3066  * DTRANK (R/W)
3067  *
3068  * Data Training Rank: Select the SDRAM rank to be used during Read DQS gate training, Read/Write Data Bit Deskew, Read/Write Eye Training.
3069  */
3070 #define DDRPHY_DTCR_DTRANK_MASK (0x30U)
3071 #define DDRPHY_DTCR_DTRANK_SHIFT (4U)
3072 #define DDRPHY_DTCR_DTRANK_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_DTRANK_SHIFT) & DDRPHY_DTCR_DTRANK_MASK)
3073 #define DDRPHY_DTCR_DTRANK_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_DTRANK_MASK) >> DDRPHY_DTCR_DTRANK_SHIFT)
3074 
3075 /*
3076  * DTRPTN (R/W)
3077  *
3078  * Data Training Repeat Number: Repeat number used to confirm stability of DDR write or read.
3079  * Note: The minimum value should be 0x4 and the maximum value should be 0x14.
3080  */
3081 #define DDRPHY_DTCR_DTRPTN_MASK (0xFU)
3082 #define DDRPHY_DTCR_DTRPTN_SHIFT (0U)
3083 #define DDRPHY_DTCR_DTRPTN_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_DTRPTN_SHIFT) & DDRPHY_DTCR_DTRPTN_MASK)
3084 #define DDRPHY_DTCR_DTRPTN_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_DTRPTN_MASK) >> DDRPHY_DTCR_DTRPTN_SHIFT)
3085 
3086 /* Bitfield definition for register: DTAR0 */
3087 /*
3088  * DTBANK (R/W)
3089  *
3090  * Data Training Bank Address: Selects the SDRAM bank address to be used during data training.
3091  */
3092 #define DDRPHY_DTAR0_DTBANK_MASK (0x70000000UL)
3093 #define DDRPHY_DTAR0_DTBANK_SHIFT (28U)
3094 #define DDRPHY_DTAR0_DTBANK_SET(x) (((uint32_t)(x) << DDRPHY_DTAR0_DTBANK_SHIFT) & DDRPHY_DTAR0_DTBANK_MASK)
3095 #define DDRPHY_DTAR0_DTBANK_GET(x) (((uint32_t)(x) & DDRPHY_DTAR0_DTBANK_MASK) >> DDRPHY_DTAR0_DTBANK_SHIFT)
3096 
3097 /*
3098  * DTROW (R/W)
3099  *
3100  * Data Training Row Address: Selects the SDRAM row address to be used during data training.
3101  */
3102 #define DDRPHY_DTAR0_DTROW_MASK (0xFFFF000UL)
3103 #define DDRPHY_DTAR0_DTROW_SHIFT (12U)
3104 #define DDRPHY_DTAR0_DTROW_SET(x) (((uint32_t)(x) << DDRPHY_DTAR0_DTROW_SHIFT) & DDRPHY_DTAR0_DTROW_MASK)
3105 #define DDRPHY_DTAR0_DTROW_GET(x) (((uint32_t)(x) & DDRPHY_DTAR0_DTROW_MASK) >> DDRPHY_DTAR0_DTROW_SHIFT)
3106 
3107 /*
3108  * DTCOL (R/W)
3109  *
3110  * Data Training Column Address: Selects the SDRAM column address to be used during data training. The lower four bits of this address must always be “000”.
3111  */
3112 #define DDRPHY_DTAR0_DTCOL_MASK (0xFFFU)
3113 #define DDRPHY_DTAR0_DTCOL_SHIFT (0U)
3114 #define DDRPHY_DTAR0_DTCOL_SET(x) (((uint32_t)(x) << DDRPHY_DTAR0_DTCOL_SHIFT) & DDRPHY_DTAR0_DTCOL_MASK)
3115 #define DDRPHY_DTAR0_DTCOL_GET(x) (((uint32_t)(x) & DDRPHY_DTAR0_DTCOL_MASK) >> DDRPHY_DTAR0_DTCOL_SHIFT)
3116 
3117 /* Bitfield definition for register: DTAR1 */
3118 /*
3119  * DTBANK (R/W)
3120  *
3121  * Data Training Bank Address: Selects the SDRAM bank address to be used during data training.
3122  */
3123 #define DDRPHY_DTAR1_DTBANK_MASK (0x70000000UL)
3124 #define DDRPHY_DTAR1_DTBANK_SHIFT (28U)
3125 #define DDRPHY_DTAR1_DTBANK_SET(x) (((uint32_t)(x) << DDRPHY_DTAR1_DTBANK_SHIFT) & DDRPHY_DTAR1_DTBANK_MASK)
3126 #define DDRPHY_DTAR1_DTBANK_GET(x) (((uint32_t)(x) & DDRPHY_DTAR1_DTBANK_MASK) >> DDRPHY_DTAR1_DTBANK_SHIFT)
3127 
3128 /*
3129  * DTROW (R/W)
3130  *
3131  * Data Training Row Address: Selects the SDRAM row address to be used during data training.
3132  */
3133 #define DDRPHY_DTAR1_DTROW_MASK (0xFFFF000UL)
3134 #define DDRPHY_DTAR1_DTROW_SHIFT (12U)
3135 #define DDRPHY_DTAR1_DTROW_SET(x) (((uint32_t)(x) << DDRPHY_DTAR1_DTROW_SHIFT) & DDRPHY_DTAR1_DTROW_MASK)
3136 #define DDRPHY_DTAR1_DTROW_GET(x) (((uint32_t)(x) & DDRPHY_DTAR1_DTROW_MASK) >> DDRPHY_DTAR1_DTROW_SHIFT)
3137 
3138 /*
3139  * DTCOL (R/W)
3140  *
3141  * Data Training Column Address: Selects the SDRAM column address to be used during data training. The lower four bits of this address must always be “000”.
3142  */
3143 #define DDRPHY_DTAR1_DTCOL_MASK (0xFFFU)
3144 #define DDRPHY_DTAR1_DTCOL_SHIFT (0U)
3145 #define DDRPHY_DTAR1_DTCOL_SET(x) (((uint32_t)(x) << DDRPHY_DTAR1_DTCOL_SHIFT) & DDRPHY_DTAR1_DTCOL_MASK)
3146 #define DDRPHY_DTAR1_DTCOL_GET(x) (((uint32_t)(x) & DDRPHY_DTAR1_DTCOL_MASK) >> DDRPHY_DTAR1_DTCOL_SHIFT)
3147 
3148 /* Bitfield definition for register: DTAR2 */
3149 /*
3150  * DTBANK (R/W)
3151  *
3152  * Data Training Bank Address: Selects the SDRAM bank address to be used during data training.
3153  */
3154 #define DDRPHY_DTAR2_DTBANK_MASK (0x70000000UL)
3155 #define DDRPHY_DTAR2_DTBANK_SHIFT (28U)
3156 #define DDRPHY_DTAR2_DTBANK_SET(x) (((uint32_t)(x) << DDRPHY_DTAR2_DTBANK_SHIFT) & DDRPHY_DTAR2_DTBANK_MASK)
3157 #define DDRPHY_DTAR2_DTBANK_GET(x) (((uint32_t)(x) & DDRPHY_DTAR2_DTBANK_MASK) >> DDRPHY_DTAR2_DTBANK_SHIFT)
3158 
3159 /*
3160  * DTROW (R/W)
3161  *
3162  * Data Training Row Address: Selects the SDRAM row address to be used during data training.
3163  */
3164 #define DDRPHY_DTAR2_DTROW_MASK (0xFFFF000UL)
3165 #define DDRPHY_DTAR2_DTROW_SHIFT (12U)
3166 #define DDRPHY_DTAR2_DTROW_SET(x) (((uint32_t)(x) << DDRPHY_DTAR2_DTROW_SHIFT) & DDRPHY_DTAR2_DTROW_MASK)
3167 #define DDRPHY_DTAR2_DTROW_GET(x) (((uint32_t)(x) & DDRPHY_DTAR2_DTROW_MASK) >> DDRPHY_DTAR2_DTROW_SHIFT)
3168 
3169 /*
3170  * DTCOL (R/W)
3171  *
3172  * Data Training Column Address: Selects the SDRAM column address to be used during data training. The lower four bits of this address must always be “000”.
3173  */
3174 #define DDRPHY_DTAR2_DTCOL_MASK (0xFFFU)
3175 #define DDRPHY_DTAR2_DTCOL_SHIFT (0U)
3176 #define DDRPHY_DTAR2_DTCOL_SET(x) (((uint32_t)(x) << DDRPHY_DTAR2_DTCOL_SHIFT) & DDRPHY_DTAR2_DTCOL_MASK)
3177 #define DDRPHY_DTAR2_DTCOL_GET(x) (((uint32_t)(x) & DDRPHY_DTAR2_DTCOL_MASK) >> DDRPHY_DTAR2_DTCOL_SHIFT)
3178 
3179 /* Bitfield definition for register: DTAR3 */
3180 /*
3181  * DTBANK (R/W)
3182  *
3183  * Data Training Bank Address: Selects the SDRAM bank address to be used during data training.
3184  */
3185 #define DDRPHY_DTAR3_DTBANK_MASK (0x70000000UL)
3186 #define DDRPHY_DTAR3_DTBANK_SHIFT (28U)
3187 #define DDRPHY_DTAR3_DTBANK_SET(x) (((uint32_t)(x) << DDRPHY_DTAR3_DTBANK_SHIFT) & DDRPHY_DTAR3_DTBANK_MASK)
3188 #define DDRPHY_DTAR3_DTBANK_GET(x) (((uint32_t)(x) & DDRPHY_DTAR3_DTBANK_MASK) >> DDRPHY_DTAR3_DTBANK_SHIFT)
3189 
3190 /*
3191  * DTROW (R/W)
3192  *
3193  * Data Training Row Address: Selects the SDRAM row address to be used during data training.
3194  */
3195 #define DDRPHY_DTAR3_DTROW_MASK (0xFFFF000UL)
3196 #define DDRPHY_DTAR3_DTROW_SHIFT (12U)
3197 #define DDRPHY_DTAR3_DTROW_SET(x) (((uint32_t)(x) << DDRPHY_DTAR3_DTROW_SHIFT) & DDRPHY_DTAR3_DTROW_MASK)
3198 #define DDRPHY_DTAR3_DTROW_GET(x) (((uint32_t)(x) & DDRPHY_DTAR3_DTROW_MASK) >> DDRPHY_DTAR3_DTROW_SHIFT)
3199 
3200 /*
3201  * DTCOL (R/W)
3202  *
3203  * Data Training Column Address: Selects the SDRAM column address to be used during data training. The lower four bits of this address must always be “000”.
3204  */
3205 #define DDRPHY_DTAR3_DTCOL_MASK (0xFFFU)
3206 #define DDRPHY_DTAR3_DTCOL_SHIFT (0U)
3207 #define DDRPHY_DTAR3_DTCOL_SET(x) (((uint32_t)(x) << DDRPHY_DTAR3_DTCOL_SHIFT) & DDRPHY_DTAR3_DTCOL_MASK)
3208 #define DDRPHY_DTAR3_DTCOL_GET(x) (((uint32_t)(x) & DDRPHY_DTAR3_DTCOL_MASK) >> DDRPHY_DTAR3_DTCOL_SHIFT)
3209 
3210 /* Bitfield definition for register: DTDR0 */
3211 /*
3212  * DTBYTE3 (R/W)
3213  *
3214  */
3215 #define DDRPHY_DTDR0_DTBYTE3_MASK (0xFF000000UL)
3216 #define DDRPHY_DTDR0_DTBYTE3_SHIFT (24U)
3217 #define DDRPHY_DTDR0_DTBYTE3_SET(x) (((uint32_t)(x) << DDRPHY_DTDR0_DTBYTE3_SHIFT) & DDRPHY_DTDR0_DTBYTE3_MASK)
3218 #define DDRPHY_DTDR0_DTBYTE3_GET(x) (((uint32_t)(x) & DDRPHY_DTDR0_DTBYTE3_MASK) >> DDRPHY_DTDR0_DTBYTE3_SHIFT)
3219 
3220 /*
3221  * DTBYTE2 (R/W)
3222  *
3223  */
3224 #define DDRPHY_DTDR0_DTBYTE2_MASK (0xFF0000UL)
3225 #define DDRPHY_DTDR0_DTBYTE2_SHIFT (16U)
3226 #define DDRPHY_DTDR0_DTBYTE2_SET(x) (((uint32_t)(x) << DDRPHY_DTDR0_DTBYTE2_SHIFT) & DDRPHY_DTDR0_DTBYTE2_MASK)
3227 #define DDRPHY_DTDR0_DTBYTE2_GET(x) (((uint32_t)(x) & DDRPHY_DTDR0_DTBYTE2_MASK) >> DDRPHY_DTDR0_DTBYTE2_SHIFT)
3228 
3229 /*
3230  * DTBYTE1 (R/W)
3231  *
3232  */
3233 #define DDRPHY_DTDR0_DTBYTE1_MASK (0xFF00U)
3234 #define DDRPHY_DTDR0_DTBYTE1_SHIFT (8U)
3235 #define DDRPHY_DTDR0_DTBYTE1_SET(x) (((uint32_t)(x) << DDRPHY_DTDR0_DTBYTE1_SHIFT) & DDRPHY_DTDR0_DTBYTE1_MASK)
3236 #define DDRPHY_DTDR0_DTBYTE1_GET(x) (((uint32_t)(x) & DDRPHY_DTDR0_DTBYTE1_MASK) >> DDRPHY_DTDR0_DTBYTE1_SHIFT)
3237 
3238 /*
3239  * DTBYTE0 (R/W)
3240  *
3241  * Data Training Data: The first 4 bytes of data used during data training. This same data byte is used for each Byte Lane. Default sequence is a walking 1 while toggling data every data cycle.
3242  */
3243 #define DDRPHY_DTDR0_DTBYTE0_MASK (0xFFU)
3244 #define DDRPHY_DTDR0_DTBYTE0_SHIFT (0U)
3245 #define DDRPHY_DTDR0_DTBYTE0_SET(x) (((uint32_t)(x) << DDRPHY_DTDR0_DTBYTE0_SHIFT) & DDRPHY_DTDR0_DTBYTE0_MASK)
3246 #define DDRPHY_DTDR0_DTBYTE0_GET(x) (((uint32_t)(x) & DDRPHY_DTDR0_DTBYTE0_MASK) >> DDRPHY_DTDR0_DTBYTE0_SHIFT)
3247 
3248 /* Bitfield definition for register: DTDR1 */
3249 /*
3250  * DTBYTE7 (R/W)
3251  *
3252  */
3253 #define DDRPHY_DTDR1_DTBYTE7_MASK (0xFF000000UL)
3254 #define DDRPHY_DTDR1_DTBYTE7_SHIFT (24U)
3255 #define DDRPHY_DTDR1_DTBYTE7_SET(x) (((uint32_t)(x) << DDRPHY_DTDR1_DTBYTE7_SHIFT) & DDRPHY_DTDR1_DTBYTE7_MASK)
3256 #define DDRPHY_DTDR1_DTBYTE7_GET(x) (((uint32_t)(x) & DDRPHY_DTDR1_DTBYTE7_MASK) >> DDRPHY_DTDR1_DTBYTE7_SHIFT)
3257 
3258 /*
3259  * DTBYTE6 (R/W)
3260  *
3261  */
3262 #define DDRPHY_DTDR1_DTBYTE6_MASK (0xFF0000UL)
3263 #define DDRPHY_DTDR1_DTBYTE6_SHIFT (16U)
3264 #define DDRPHY_DTDR1_DTBYTE6_SET(x) (((uint32_t)(x) << DDRPHY_DTDR1_DTBYTE6_SHIFT) & DDRPHY_DTDR1_DTBYTE6_MASK)
3265 #define DDRPHY_DTDR1_DTBYTE6_GET(x) (((uint32_t)(x) & DDRPHY_DTDR1_DTBYTE6_MASK) >> DDRPHY_DTDR1_DTBYTE6_SHIFT)
3266 
3267 /*
3268  * DTBYTE5 (R/W)
3269  *
3270  */
3271 #define DDRPHY_DTDR1_DTBYTE5_MASK (0xFF00U)
3272 #define DDRPHY_DTDR1_DTBYTE5_SHIFT (8U)
3273 #define DDRPHY_DTDR1_DTBYTE5_SET(x) (((uint32_t)(x) << DDRPHY_DTDR1_DTBYTE5_SHIFT) & DDRPHY_DTDR1_DTBYTE5_MASK)
3274 #define DDRPHY_DTDR1_DTBYTE5_GET(x) (((uint32_t)(x) & DDRPHY_DTDR1_DTBYTE5_MASK) >> DDRPHY_DTDR1_DTBYTE5_SHIFT)
3275 
3276 /*
3277  * DTBYTE4 (R/W)
3278  *
3279  * Data Training Data: The second 4 bytes of data used during data training. This same data byte is used for each Byte Lane. Default sequence is a walking 1 while toggling data every data cycle.
3280  */
3281 #define DDRPHY_DTDR1_DTBYTE4_MASK (0xFFU)
3282 #define DDRPHY_DTDR1_DTBYTE4_SHIFT (0U)
3283 #define DDRPHY_DTDR1_DTBYTE4_SET(x) (((uint32_t)(x) << DDRPHY_DTDR1_DTBYTE4_SHIFT) & DDRPHY_DTDR1_DTBYTE4_MASK)
3284 #define DDRPHY_DTDR1_DTBYTE4_GET(x) (((uint32_t)(x) & DDRPHY_DTDR1_DTBYTE4_MASK) >> DDRPHY_DTDR1_DTBYTE4_SHIFT)
3285 
3286 /* Bitfield definition for register: DTEDR0 */
3287 /*
3288  * DTWBMX (R)
3289  *
3290  * Data Training Write BDL Shift Maximum.
3291  */
3292 #define DDRPHY_DTEDR0_DTWBMX_MASK (0xFF000000UL)
3293 #define DDRPHY_DTEDR0_DTWBMX_SHIFT (24U)
3294 #define DDRPHY_DTEDR0_DTWBMX_GET(x) (((uint32_t)(x) & DDRPHY_DTEDR0_DTWBMX_MASK) >> DDRPHY_DTEDR0_DTWBMX_SHIFT)
3295 
3296 /*
3297  * DTWBMN (R)
3298  *
3299  * Data Training Write BDL Shift Minimum.
3300  */
3301 #define DDRPHY_DTEDR0_DTWBMN_MASK (0xFF0000UL)
3302 #define DDRPHY_DTEDR0_DTWBMN_SHIFT (16U)
3303 #define DDRPHY_DTEDR0_DTWBMN_GET(x) (((uint32_t)(x) & DDRPHY_DTEDR0_DTWBMN_MASK) >> DDRPHY_DTEDR0_DTWBMN_SHIFT)
3304 
3305 /*
3306  * DTWLMX (R)
3307  *
3308  * Data Training WDQ LCDL Maximum.
3309  */
3310 #define DDRPHY_DTEDR0_DTWLMX_MASK (0xFF00U)
3311 #define DDRPHY_DTEDR0_DTWLMX_SHIFT (8U)
3312 #define DDRPHY_DTEDR0_DTWLMX_GET(x) (((uint32_t)(x) & DDRPHY_DTEDR0_DTWLMX_MASK) >> DDRPHY_DTEDR0_DTWLMX_SHIFT)
3313 
3314 /*
3315  * DTWLMN (R)
3316  *
3317  * Data Training WDQ LCDL Minimum.
3318  */
3319 #define DDRPHY_DTEDR0_DTWLMN_MASK (0xFFU)
3320 #define DDRPHY_DTEDR0_DTWLMN_SHIFT (0U)
3321 #define DDRPHY_DTEDR0_DTWLMN_GET(x) (((uint32_t)(x) & DDRPHY_DTEDR0_DTWLMN_MASK) >> DDRPHY_DTEDR0_DTWLMN_SHIFT)
3322 
3323 /* Bitfield definition for register: DTEDR1 */
3324 /*
3325  * DTRBMX (R)
3326  *
3327  * Data Training Read BDL Shift Maximum.
3328  */
3329 #define DDRPHY_DTEDR1_DTRBMX_MASK (0xFF000000UL)
3330 #define DDRPHY_DTEDR1_DTRBMX_SHIFT (24U)
3331 #define DDRPHY_DTEDR1_DTRBMX_GET(x) (((uint32_t)(x) & DDRPHY_DTEDR1_DTRBMX_MASK) >> DDRPHY_DTEDR1_DTRBMX_SHIFT)
3332 
3333 /*
3334  * DTRBMN (R)
3335  *
3336  * Data Training Read BDL Shift Minimum.
3337  */
3338 #define DDRPHY_DTEDR1_DTRBMN_MASK (0xFF0000UL)
3339 #define DDRPHY_DTEDR1_DTRBMN_SHIFT (16U)
3340 #define DDRPHY_DTEDR1_DTRBMN_GET(x) (((uint32_t)(x) & DDRPHY_DTEDR1_DTRBMN_MASK) >> DDRPHY_DTEDR1_DTRBMN_SHIFT)
3341 
3342 /*
3343  * DTRLMX (R)
3344  *
3345  * Data Training RDQS LCDL Maximum.
3346  */
3347 #define DDRPHY_DTEDR1_DTRLMX_MASK (0xFF00U)
3348 #define DDRPHY_DTEDR1_DTRLMX_SHIFT (8U)
3349 #define DDRPHY_DTEDR1_DTRLMX_GET(x) (((uint32_t)(x) & DDRPHY_DTEDR1_DTRLMX_MASK) >> DDRPHY_DTEDR1_DTRLMX_SHIFT)
3350 
3351 /*
3352  * DTRLMN (R)
3353  *
3354  * Data Training RDQS LCDL Minimum.
3355  */
3356 #define DDRPHY_DTEDR1_DTRLMN_MASK (0xFFU)
3357 #define DDRPHY_DTEDR1_DTRLMN_SHIFT (0U)
3358 #define DDRPHY_DTEDR1_DTRLMN_GET(x) (((uint32_t)(x) & DDRPHY_DTEDR1_DTRLMN_MASK) >> DDRPHY_DTEDR1_DTRLMN_SHIFT)
3359 
3360 /* Bitfield definition for register: PGCR2 */
3361 /*
3362  * DYNACPDD1 (R/W)
3363  *
3364  * Dynamic AC Power Down Driver: Powers down, when set, the output driver on I/O for ADDR and BA. This bit is ORed with bit ACIOCR[3] (ACPDD).
3365  */
3366 #define DDRPHY_PGCR2_DYNACPDD1_MASK (0x80000000UL)
3367 #define DDRPHY_PGCR2_DYNACPDD1_SHIFT (31U)
3368 #define DDRPHY_PGCR2_DYNACPDD1_SET(x) (((uint32_t)(x) << DDRPHY_PGCR2_DYNACPDD1_SHIFT) & DDRPHY_PGCR2_DYNACPDD1_MASK)
3369 #define DDRPHY_PGCR2_DYNACPDD1_GET(x) (((uint32_t)(x) & DDRPHY_PGCR2_DYNACPDD1_MASK) >> DDRPHY_PGCR2_DYNACPDD1_SHIFT)
3370 
3371 /*
3372  * LPMSTRC0 (R/W)
3373  *
3374  * Low-Power Master Channel 0: set to 1 to have channel 0 act as master to drive channel 1 low-power functions simultaneously. Only valid in shared-AC mode.
3375  */
3376 #define DDRPHY_PGCR2_LPMSTRC0_MASK (0x40000000UL)
3377 #define DDRPHY_PGCR2_LPMSTRC0_SHIFT (30U)
3378 #define DDRPHY_PGCR2_LPMSTRC0_SET(x) (((uint32_t)(x) << DDRPHY_PGCR2_LPMSTRC0_SHIFT) & DDRPHY_PGCR2_LPMSTRC0_MASK)
3379 #define DDRPHY_PGCR2_LPMSTRC0_GET(x) (((uint32_t)(x) & DDRPHY_PGCR2_LPMSTRC0_MASK) >> DDRPHY_PGCR2_LPMSTRC0_SHIFT)
3380 
3381 /*
3382  * ACPDDC (R/W)
3383  *
3384  * AC Power-Down with Dual Channels: Set to 1 to power-down address/command lane when both data channels are powered-down. Only valid in shared-AC mode.
3385  */
3386 #define DDRPHY_PGCR2_ACPDDC_MASK (0x20000000UL)
3387 #define DDRPHY_PGCR2_ACPDDC_SHIFT (29U)
3388 #define DDRPHY_PGCR2_ACPDDC_SET(x) (((uint32_t)(x) << DDRPHY_PGCR2_ACPDDC_SHIFT) & DDRPHY_PGCR2_ACPDDC_MASK)
3389 #define DDRPHY_PGCR2_ACPDDC_GET(x) (((uint32_t)(x) & DDRPHY_PGCR2_ACPDDC_MASK) >> DDRPHY_PGCR2_ACPDDC_SHIFT)
3390 
3391 /*
3392  * SHRAC (R/W)
3393  *
3394  * Shared-AC mode: set to 1 to enable shared address/command mode with two independent data channels – available only if shared address/command mode support is compiled in.
3395  */
3396 #define DDRPHY_PGCR2_SHRAC_MASK (0x10000000UL)
3397 #define DDRPHY_PGCR2_SHRAC_SHIFT (28U)
3398 #define DDRPHY_PGCR2_SHRAC_SET(x) (((uint32_t)(x) << DDRPHY_PGCR2_SHRAC_SHIFT) & DDRPHY_PGCR2_SHRAC_MASK)
3399 #define DDRPHY_PGCR2_SHRAC_GET(x) (((uint32_t)(x) & DDRPHY_PGCR2_SHRAC_MASK) >> DDRPHY_PGCR2_SHRAC_SHIFT)
3400 
3401 /*
3402  * DTPMXTMR (R/W)
3403  *
3404  * Data Training PUB Mode Timer Exit: Specifies the number of controller clocks to wait when entering and exiting pub mode data training. The default value ensures controller refreshes do not cause memory model errors when entering and exiting data training. The value should be increased if controller initiated SDRAM ZQ short or long operation may occur just before or just after the execution of data training.
3405  */
3406 #define DDRPHY_PGCR2_DTPMXTMR_MASK (0xFF00000UL)
3407 #define DDRPHY_PGCR2_DTPMXTMR_SHIFT (20U)
3408 #define DDRPHY_PGCR2_DTPMXTMR_SET(x) (((uint32_t)(x) << DDRPHY_PGCR2_DTPMXTMR_SHIFT) & DDRPHY_PGCR2_DTPMXTMR_MASK)
3409 #define DDRPHY_PGCR2_DTPMXTMR_GET(x) (((uint32_t)(x) & DDRPHY_PGCR2_DTPMXTMR_MASK) >> DDRPHY_PGCR2_DTPMXTMR_SHIFT)
3410 
3411 /*
3412  * FXDLAT (R/W)
3413  *
3414  * Fixed Latency: Specified whether all reads should be returned to the controller with a fixed read latency. Enabling fixed read latency increases the read latency. Valid values are:
3415  * 0 = Disable fixed read latency 1 = Enable fixed read latency
3416  * Fixed read latency is calculated as (12 + (maximum DXnGTR.RxDGSL)/2) HDR clock cycles
3417  */
3418 #define DDRPHY_PGCR2_FXDLAT_MASK (0x80000UL)
3419 #define DDRPHY_PGCR2_FXDLAT_SHIFT (19U)
3420 #define DDRPHY_PGCR2_FXDLAT_SET(x) (((uint32_t)(x) << DDRPHY_PGCR2_FXDLAT_SHIFT) & DDRPHY_PGCR2_FXDLAT_MASK)
3421 #define DDRPHY_PGCR2_FXDLAT_GET(x) (((uint32_t)(x) & DDRPHY_PGCR2_FXDLAT_MASK) >> DDRPHY_PGCR2_FXDLAT_SHIFT)
3422 
3423 /*
3424  * NOBUB (R/W)
3425  *
3426  * No Bubbles: Specified whether reads should be returned to the controller with no bubbles. Enabling no-bubble reads increases the read latency. Valid values are: 0 = Bubbles are allowed during reads
3427  * 1 = Bubbles are not allowed during reads
3428  */
3429 #define DDRPHY_PGCR2_NOBUB_MASK (0x40000UL)
3430 #define DDRPHY_PGCR2_NOBUB_SHIFT (18U)
3431 #define DDRPHY_PGCR2_NOBUB_SET(x) (((uint32_t)(x) << DDRPHY_PGCR2_NOBUB_SHIFT) & DDRPHY_PGCR2_NOBUB_MASK)
3432 #define DDRPHY_PGCR2_NOBUB_GET(x) (((uint32_t)(x) & DDRPHY_PGCR2_NOBUB_MASK) >> DDRPHY_PGCR2_NOBUB_SHIFT)
3433 
3434 /*
3435  * TREFPRD (R/W)
3436  *
3437  * Refresh Period: Indicates the period, after which the PUB has to issue a refresh command to the SDRAM. This is derived from the maximum refresh interval from the datasheet, tRFC(max) or REFI, divided by the clock cycle time. A further 400 clocks must be subtracted from the derived number to account for command flow and missed slots of refreshes in the internal PUB blocks. The default corresponds to DDR3 9*7.8us at 1066MHz when a burst of 9 refreshes are issued at every refresh interval.
3438  */
3439 #define DDRPHY_PGCR2_TREFPRD_MASK (0x3FFFFUL)
3440 #define DDRPHY_PGCR2_TREFPRD_SHIFT (0U)
3441 #define DDRPHY_PGCR2_TREFPRD_SET(x) (((uint32_t)(x) << DDRPHY_PGCR2_TREFPRD_SHIFT) & DDRPHY_PGCR2_TREFPRD_MASK)
3442 #define DDRPHY_PGCR2_TREFPRD_GET(x) (((uint32_t)(x) & DDRPHY_PGCR2_TREFPRD_MASK) >> DDRPHY_PGCR2_TREFPRD_SHIFT)
3443 
3444 /* Bitfield definition for register: RDIMMGCR0 */
3445 /*
3446  * MIRROR (R)
3447  *
3448  * RDIMM Mirror: Selects between two different ballouts of the RDIMM buffer chip for front or back operation. This register bit controls the buffer chip MIRROR signal.
3449  */
3450 #define DDRPHY_RDIMMGCR0_MIRROR_MASK (0x80000000UL)
3451 #define DDRPHY_RDIMMGCR0_MIRROR_SHIFT (31U)
3452 #define DDRPHY_RDIMMGCR0_MIRROR_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_MIRROR_MASK) >> DDRPHY_RDIMMGCR0_MIRROR_SHIFT)
3453 
3454 /*
3455  * QCSEN (R)
3456  *
3457  * RDMIMM Quad CS Enable: Enables, if set, the Quad CS mode for the RDIMM registering buffer chip. This register bit controls the buffer chip QCSEN# signal.
3458  */
3459 #define DDRPHY_RDIMMGCR0_QCSEN_MASK (0x40000000UL)
3460 #define DDRPHY_RDIMMGCR0_QCSEN_SHIFT (30U)
3461 #define DDRPHY_RDIMMGCR0_QCSEN_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_QCSEN_MASK) >> DDRPHY_RDIMMGCR0_QCSEN_SHIFT)
3462 
3463 /*
3464  * MIRROROE (R)
3465  *
3466  * MIRROR Output Enable: Enables, when set, the output driver on the I/O for MIRROR pin.
3467  */
3468 #define DDRPHY_RDIMMGCR0_MIRROROE_MASK (0x20000000UL)
3469 #define DDRPHY_RDIMMGCR0_MIRROROE_SHIFT (29U)
3470 #define DDRPHY_RDIMMGCR0_MIRROROE_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_MIRROROE_MASK) >> DDRPHY_RDIMMGCR0_MIRROROE_SHIFT)
3471 
3472 /*
3473  * QCSENOE (R)
3474  *
3475  * QCSEN# Output Enable: Enables, when set, the output driver on the I/O for QCSEN# pin.
3476  */
3477 #define DDRPHY_RDIMMGCR0_QCSENOE_MASK (0x10000000UL)
3478 #define DDRPHY_RDIMMGCR0_QCSENOE_SHIFT (28U)
3479 #define DDRPHY_RDIMMGCR0_QCSENOE_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_QCSENOE_MASK) >> DDRPHY_RDIMMGCR0_QCSENOE_SHIFT)
3480 
3481 /*
3482  * RDIMMIOM (R)
3483  *
3484  * RDIMM Outputs I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for QCSEN# and MIRROR pins.
3485  */
3486 #define DDRPHY_RDIMMGCR0_RDIMMIOM_MASK (0x8000000UL)
3487 #define DDRPHY_RDIMMGCR0_RDIMMIOM_SHIFT (27U)
3488 #define DDRPHY_RDIMMGCR0_RDIMMIOM_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_RDIMMIOM_MASK) >> DDRPHY_RDIMMGCR0_RDIMMIOM_SHIFT)
3489 
3490 /*
3491  * RDIMMPDR (R)
3492  *
3493  * RDIMM Outputs Power Down Receiver: Powers down, when set, the input receiver on the I/O for QCSEN# and MIRROR pins.
3494  */
3495 #define DDRPHY_RDIMMGCR0_RDIMMPDR_MASK (0x4000000UL)
3496 #define DDRPHY_RDIMMGCR0_RDIMMPDR_SHIFT (26U)
3497 #define DDRPHY_RDIMMGCR0_RDIMMPDR_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_RDIMMPDR_MASK) >> DDRPHY_RDIMMGCR0_RDIMMPDR_SHIFT)
3498 
3499 /*
3500  * RDIMMPDD (R)
3501  *
3502  * RDIMM Outputs Power Down Driver: Powers down, when set, the output driver on the I/O for QCSEN# and MIRROR pins.
3503  */
3504 #define DDRPHY_RDIMMGCR0_RDIMMPDD_MASK (0x2000000UL)
3505 #define DDRPHY_RDIMMGCR0_RDIMMPDD_SHIFT (25U)
3506 #define DDRPHY_RDIMMGCR0_RDIMMPDD_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_RDIMMPDD_MASK) >> DDRPHY_RDIMMGCR0_RDIMMPDD_SHIFT)
3507 
3508 /*
3509  * RDIMMODT (R)
3510  *
3511  * RDIMM Outputs On-Die Termination: Enables, when set, the on-die termination on the I/O for QCSEN# and MIRROR pins.
3512  */
3513 #define DDRPHY_RDIMMGCR0_RDIMMODT_MASK (0x1000000UL)
3514 #define DDRPHY_RDIMMGCR0_RDIMMODT_SHIFT (24U)
3515 #define DDRPHY_RDIMMGCR0_RDIMMODT_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_RDIMMODT_MASK) >> DDRPHY_RDIMMGCR0_RDIMMODT_SHIFT)
3516 
3517 /*
3518  * ERROUTOE (R)
3519  *
3520  * ERROUT# Output Enable: Enables, when set, the output driver on the I/O for ERROUT# pin.
3521  */
3522 #define DDRPHY_RDIMMGCR0_ERROUTOE_MASK (0x800000UL)
3523 #define DDRPHY_RDIMMGCR0_ERROUTOE_SHIFT (23U)
3524 #define DDRPHY_RDIMMGCR0_ERROUTOE_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_ERROUTOE_MASK) >> DDRPHY_RDIMMGCR0_ERROUTOE_SHIFT)
3525 
3526 /*
3527  * ERROUTIOM (R)
3528  *
3529  * ERROUT# I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for ERROUT# pin.
3530  */
3531 #define DDRPHY_RDIMMGCR0_ERROUTIOM_MASK (0x400000UL)
3532 #define DDRPHY_RDIMMGCR0_ERROUTIOM_SHIFT (22U)
3533 #define DDRPHY_RDIMMGCR0_ERROUTIOM_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_ERROUTIOM_MASK) >> DDRPHY_RDIMMGCR0_ERROUTIOM_SHIFT)
3534 
3535 /*
3536  * ERROUTPDR (R)
3537  *
3538  * ERROUT# Power Down Receiver: Powers down, when set, the input receiver on the I/O for ERROUT# pin.
3539  */
3540 #define DDRPHY_RDIMMGCR0_ERROUTPDR_MASK (0x200000UL)
3541 #define DDRPHY_RDIMMGCR0_ERROUTPDR_SHIFT (21U)
3542 #define DDRPHY_RDIMMGCR0_ERROUTPDR_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_ERROUTPDR_MASK) >> DDRPHY_RDIMMGCR0_ERROUTPDR_SHIFT)
3543 
3544 /*
3545  * ERROUTPDD (R)
3546  *
3547  * ERROUT# Power Down Driver: Powers down, when set, the output driver on the I/O for ERROUT# pin.
3548  */
3549 #define DDRPHY_RDIMMGCR0_ERROUTPDD_MASK (0x100000UL)
3550 #define DDRPHY_RDIMMGCR0_ERROUTPDD_SHIFT (20U)
3551 #define DDRPHY_RDIMMGCR0_ERROUTPDD_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_ERROUTPDD_MASK) >> DDRPHY_RDIMMGCR0_ERROUTPDD_SHIFT)
3552 
3553 /*
3554  * ERROUTODT (R)
3555  *
3556  * ERROUT# On-Die Termination: Enables, when set, the on-die termination on the I/O for ERROUT# pin.
3557  */
3558 #define DDRPHY_RDIMMGCR0_ERROUTODT_MASK (0x80000UL)
3559 #define DDRPHY_RDIMMGCR0_ERROUTODT_SHIFT (19U)
3560 #define DDRPHY_RDIMMGCR0_ERROUTODT_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_ERROUTODT_MASK) >> DDRPHY_RDIMMGCR0_ERROUTODT_SHIFT)
3561 
3562 /*
3563  * PARINOE (R)
3564  *
3565  * PAR_IN Output Enable: Enables, when set, the output driver on the I/O for PAR_IN pin.
3566  */
3567 #define DDRPHY_RDIMMGCR0_PARINOE_MASK (0x40000UL)
3568 #define DDRPHY_RDIMMGCR0_PARINOE_SHIFT (18U)
3569 #define DDRPHY_RDIMMGCR0_PARINOE_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_PARINOE_MASK) >> DDRPHY_RDIMMGCR0_PARINOE_SHIFT)
3570 
3571 /*
3572  * PARINIOM (R)
3573  *
3574  * PAR_IN I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for PAR_IN pin.
3575  */
3576 #define DDRPHY_RDIMMGCR0_PARINIOM_MASK (0x20000UL)
3577 #define DDRPHY_RDIMMGCR0_PARINIOM_SHIFT (17U)
3578 #define DDRPHY_RDIMMGCR0_PARINIOM_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_PARINIOM_MASK) >> DDRPHY_RDIMMGCR0_PARINIOM_SHIFT)
3579 
3580 /*
3581  * PARINPDR (R)
3582  *
3583  * PAR_IN Power Down Receiver: Powers down, when set, the input receiver on the I/O for PAR_IN pin.
3584  */
3585 #define DDRPHY_RDIMMGCR0_PARINPDR_MASK (0x10000UL)
3586 #define DDRPHY_RDIMMGCR0_PARINPDR_SHIFT (16U)
3587 #define DDRPHY_RDIMMGCR0_PARINPDR_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_PARINPDR_MASK) >> DDRPHY_RDIMMGCR0_PARINPDR_SHIFT)
3588 
3589 /*
3590  * PARINPDD (R)
3591  *
3592  * PAR_IN Power Down Driver: Powers down, when set, the output driver on the I/O for PAR_IN pin.
3593  */
3594 #define DDRPHY_RDIMMGCR0_PARINPDD_MASK (0x8000U)
3595 #define DDRPHY_RDIMMGCR0_PARINPDD_SHIFT (15U)
3596 #define DDRPHY_RDIMMGCR0_PARINPDD_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_PARINPDD_MASK) >> DDRPHY_RDIMMGCR0_PARINPDD_SHIFT)
3597 
3598 /*
3599  * PARINODT (R)
3600  *
3601  * PAR_IN On-Die Termination: Enables, when set, the on-die termination on the I/O for PAR_IN pin.
3602  */
3603 #define DDRPHY_RDIMMGCR0_PARINODT_MASK (0x4000U)
3604 #define DDRPHY_RDIMMGCR0_PARINODT_SHIFT (14U)
3605 #define DDRPHY_RDIMMGCR0_PARINODT_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_PARINODT_MASK) >> DDRPHY_RDIMMGCR0_PARINODT_SHIFT)
3606 
3607 /*
3608  * SOPERR (R)
3609  *
3610  * Stop On Parity Error: Indicates, if set, that the PUB is to stop driving commands to the DRAM upon encountering a parity error. Transactions can resume only after status is cleared via PIR.CLRSR.
3611  */
3612 #define DDRPHY_RDIMMGCR0_SOPERR_MASK (0x4U)
3613 #define DDRPHY_RDIMMGCR0_SOPERR_SHIFT (2U)
3614 #define DDRPHY_RDIMMGCR0_SOPERR_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_SOPERR_MASK) >> DDRPHY_RDIMMGCR0_SOPERR_SHIFT)
3615 
3616 /*
3617  * ERRNOREG (R)
3618  *
3619  * Parity Error No Registering: Indicates, if set, that parity error signal from the RDIMM should be passed to the DFI controller without any synchronization or registering. Otherwise, the error signal is synchronized as shown in Figure 4-30 on page 262.
3620  */
3621 #define DDRPHY_RDIMMGCR0_ERRNOREG_MASK (0x2U)
3622 #define DDRPHY_RDIMMGCR0_ERRNOREG_SHIFT (1U)
3623 #define DDRPHY_RDIMMGCR0_ERRNOREG_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_ERRNOREG_MASK) >> DDRPHY_RDIMMGCR0_ERRNOREG_SHIFT)
3624 
3625 /*
3626  * RDIMM (R)
3627  *
3628  * Registered DIMM: Indicates, if set, that a registered DIMM is used. In this case, the PUB increases the SDRAM write and read latencies (WL/RL) by 1 and also enforces that accesses adhere to RDIMM buffer chip. This only applies to PUB internal SDRAM transactions. Transactions generated by the controller must make its own adjustments to WL/RL when using a registered DIMM. The DCR.NOSRA register bit must be set to ‘1’ if using the standard RDIMM buffer chip so that normal DRAM accesses do not assert multiple chip select bits at the same time.
3629  */
3630 #define DDRPHY_RDIMMGCR0_RDIMM_MASK (0x1U)
3631 #define DDRPHY_RDIMMGCR0_RDIMM_SHIFT (0U)
3632 #define DDRPHY_RDIMMGCR0_RDIMM_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_RDIMM_MASK) >> DDRPHY_RDIMMGCR0_RDIMM_SHIFT)
3633 
3634 /* Bitfield definition for register: RDIMMGCR1 */
3635 /*
3636  * CRINIT (R)
3637  *
3638  * Control Registers Initialization Enable: Indicates which RDIMM buffer chip control registers (RC0 to RC15) should be initialized (written) when the PUB is triggered to initialize the buffer chip. A setting of ‘1’ on CRINIT[n] bit means that CRn should be written during initialization.
3639  */
3640 #define DDRPHY_RDIMMGCR1_CRINIT_MASK (0xFFFF0000UL)
3641 #define DDRPHY_RDIMMGCR1_CRINIT_SHIFT (16U)
3642 #define DDRPHY_RDIMMGCR1_CRINIT_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR1_CRINIT_MASK) >> DDRPHY_RDIMMGCR1_CRINIT_SHIFT)
3643 
3644 /*
3645  * TBCMRD (R)
3646  *
3647  * Command word to command word programming delay: Number of DRAM clock cycles between two RDIMM buffer chip command programming accesses. The value used for tBCMRD is 8 plus the value programmed in these bits, i.e. tBCMRD value ranges from 8 to 15. This parameter corresponds to the buffer chip tMRD parameter.
3648  */
3649 #define DDRPHY_RDIMMGCR1_TBCMRD_MASK (0x7000U)
3650 #define DDRPHY_RDIMMGCR1_TBCMRD_SHIFT (12U)
3651 #define DDRPHY_RDIMMGCR1_TBCMRD_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR1_TBCMRD_MASK) >> DDRPHY_RDIMMGCR1_TBCMRD_SHIFT)
3652 
3653 /*
3654  * TBCSTAB (R)
3655  *
3656  * Stabilization time: Number of DRAM clock cycles for the RDIMM buffer chip to stabilize. This parameter corresponds to the buffer chip tSTAB parameter. Default value is in decimal format and corresponds to 6us at 533MHz.
3657  */
3658 #define DDRPHY_RDIMMGCR1_TBCSTAB_MASK (0xFFFU)
3659 #define DDRPHY_RDIMMGCR1_TBCSTAB_SHIFT (0U)
3660 #define DDRPHY_RDIMMGCR1_TBCSTAB_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR1_TBCSTAB_MASK) >> DDRPHY_RDIMMGCR1_TBCSTAB_SHIFT)
3661 
3662 /* Bitfield definition for register: RDIMMCR0 */
3663 /*
3664  * RC7 (R)
3665  *
3666  * Control Word 7: Reserved, free to use by vendor.
3667  */
3668 #define DDRPHY_RDIMMCR0_RC7_MASK (0xF0000000UL)
3669 #define DDRPHY_RDIMMCR0_RC7_SHIFT (28U)
3670 #define DDRPHY_RDIMMCR0_RC7_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR0_RC7_MASK) >> DDRPHY_RDIMMCR0_RC7_SHIFT)
3671 
3672 /*
3673  * RC6 (R)
3674  *
3675  * Control Word 6: Reserved, free to use by vendor.
3676  */
3677 #define DDRPHY_RDIMMCR0_RC6_MASK (0xF000000UL)
3678 #define DDRPHY_RDIMMCR0_RC6_SHIFT (24U)
3679 #define DDRPHY_RDIMMCR0_RC6_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR0_RC6_MASK) >> DDRPHY_RDIMMCR0_RC6_SHIFT)
3680 
3681 /*
3682  * RC5 (R)
3683  *
3684  * Control Word 5 (CK Driver Characteristics Control Word): RC5[1:0] is driver settings for clock Y1, Y1#, Y3, and Y3# outputs, and RC5[3:2] is driver settings for clock Y0, Y0#, Y2, and Y2# outputs. Bit definitions are:
3685  * 00 = Light drive (4 or 5 DRAM loads)
3686  * 01 = Moderate drive (8 or 10 DRAM loads)
3687  * 10 = Strong drive (16 or 20 DRAM loads)
3688  * 11 = Reserved
3689  */
3690 #define DDRPHY_RDIMMCR0_RC5_MASK (0xF00000UL)
3691 #define DDRPHY_RDIMMCR0_RC5_SHIFT (20U)
3692 #define DDRPHY_RDIMMCR0_RC5_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR0_RC5_MASK) >> DDRPHY_RDIMMCR0_RC5_SHIFT)
3693 
3694 /*
3695  * RC4 (R)
3696  *
3697  * Control Word 4 (Control Signals Driver Characteristics Control Word): RC4[1:0] is driver settings for control A outputs, and RC4[3:2] is driver settings for control B outputs. Bit definitions are:
3698  * 00 = Light drive (4 or 5 DRAM loads)
3699  * 01 = Moderate drive (8 or 10 DRAM loads)
3700  * 10 = Reserved
3701  * 11 = Reserved
3702  */
3703 #define DDRPHY_RDIMMCR0_RC4_MASK (0xF0000UL)
3704 #define DDRPHY_RDIMMCR0_RC4_SHIFT (16U)
3705 #define DDRPHY_RDIMMCR0_RC4_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR0_RC4_MASK) >> DDRPHY_RDIMMCR0_RC4_SHIFT)
3706 
3707 /*
3708  * RC3 (R)
3709  *
3710  * Control Word 3 (Command/Address Signals Driver Characteristics Control Word): RC3[1:0] is driver settings for command/address A outputs, and RC3[3:2] is driver settings for command/address B outputs. Bit definitions are:
3711  * 00 = Light drive (4 or 5 DRAM loads)
3712  * 01 = Moderate drive (8 or 10 DRAM loads)
3713  * 10 = Strong drive (16 or 20 DRAM loads)
3714  * 11 = Reserved
3715  */
3716 #define DDRPHY_RDIMMCR0_RC3_MASK (0xF000U)
3717 #define DDRPHY_RDIMMCR0_RC3_SHIFT (12U)
3718 #define DDRPHY_RDIMMCR0_RC3_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR0_RC3_MASK) >> DDRPHY_RDIMMCR0_RC3_SHIFT)
3719 
3720 /*
3721  * RC2 (R)
3722  *
3723  * Control Word 2 (Timing Control Word): Bit definitions are:
3724  * RC2[0]: 0 = Standard (1/2 clock) pre-launch, 1 = Prelaunch controlled by RC12. RC2[1]: 0 = Reserved.
3725  * RC2[2]: 0 = 100 Ohm input bus termination, 1 = 150 Ohm input bus termination. RC2[3]: 0 = Operation frequency band 1, 1 = Test mode frequency band 2.
3726  */
3727 #define DDRPHY_RDIMMCR0_RC2_MASK (0xF00U)
3728 #define DDRPHY_RDIMMCR0_RC2_SHIFT (8U)
3729 #define DDRPHY_RDIMMCR0_RC2_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR0_RC2_MASK) >> DDRPHY_RDIMMCR0_RC2_SHIFT)
3730 
3731 /*
3732  * RC1 (R)
3733  *
3734  * Control Word 1 (Clock Driver Enable Control Word): Bit definitions are: RC1[0]: 0 = Y0/Y0# clock enabled, 1 = Y0/Y0# clock disabled.
3735  * RC1[1]: 0 = Y1/Y1# clock enabled, 1 = Y1/Y1# clock disabled. RC1[2]: 0 = Y2/Y2# clock enabled, 1 = Y2/Y2# clock disabled. RC1[3]: 0 = Y3/Y3# clock enabled, 1 = Y3/Y3# clock disabled.
3736  */
3737 #define DDRPHY_RDIMMCR0_RC1_MASK (0xF0U)
3738 #define DDRPHY_RDIMMCR0_RC1_SHIFT (4U)
3739 #define DDRPHY_RDIMMCR0_RC1_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR0_RC1_MASK) >> DDRPHY_RDIMMCR0_RC1_SHIFT)
3740 
3741 /*
3742  * RC0 (R)
3743  *
3744  * Control Word 0 (Global Features Control Word): Bit definitions are: RC0[0]: 0 = Output inversion enabled, 1 = Output inversion disabled. RC0[1]: 0 = Floating outputs disabled, 1 = Floating outputs enabled. RC0[2]: 0 = A outputs enabled, 1 = A outputs disabled.
3745  * RC0[3]: 0 = B outputs enabled, 1 = B outputs disabled.
3746  */
3747 #define DDRPHY_RDIMMCR0_RC0_MASK (0xFU)
3748 #define DDRPHY_RDIMMCR0_RC0_SHIFT (0U)
3749 #define DDRPHY_RDIMMCR0_RC0_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR0_RC0_MASK) >> DDRPHY_RDIMMCR0_RC0_SHIFT)
3750 
3751 /* Bitfield definition for register: RDIMMCR1 */
3752 /*
3753  * RC15 (R)
3754  *
3755  * Control Word 15: Reserved for future use.
3756  */
3757 #define DDRPHY_RDIMMCR1_RC15_MASK (0xF0000000UL)
3758 #define DDRPHY_RDIMMCR1_RC15_SHIFT (28U)
3759 #define DDRPHY_RDIMMCR1_RC15_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR1_RC15_MASK) >> DDRPHY_RDIMMCR1_RC15_SHIFT)
3760 
3761 /*
3762  * RC14 (R)
3763  *
3764  * Control Word 14: Reserved for future use.
3765  */
3766 #define DDRPHY_RDIMMCR1_RC14_MASK (0xF000000UL)
3767 #define DDRPHY_RDIMMCR1_RC14_SHIFT (24U)
3768 #define DDRPHY_RDIMMCR1_RC14_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR1_RC14_MASK) >> DDRPHY_RDIMMCR1_RC14_SHIFT)
3769 
3770 /*
3771  * RC13 (R)
3772  *
3773  * Control Word 13: Reserved for future use.
3774  */
3775 #define DDRPHY_RDIMMCR1_RC13_MASK (0xF00000UL)
3776 #define DDRPHY_RDIMMCR1_RC13_SHIFT (20U)
3777 #define DDRPHY_RDIMMCR1_RC13_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR1_RC13_MASK) >> DDRPHY_RDIMMCR1_RC13_SHIFT)
3778 
3779 /*
3780  * RC12 (R)
3781  *
3782  * Control Word 12: Reserved for future use.
3783  */
3784 #define DDRPHY_RDIMMCR1_RC12_MASK (0xF0000UL)
3785 #define DDRPHY_RDIMMCR1_RC12_SHIFT (16U)
3786 #define DDRPHY_RDIMMCR1_RC12_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR1_RC12_MASK) >> DDRPHY_RDIMMCR1_RC12_SHIFT)
3787 
3788 /*
3789  * RC11 (R)
3790  *
3791  * Control Word 11 (Operating Voltage VDD Control Word): RC10[1:0] is VDD operating voltage setting as follows: 00 = DDR3 1.5V mode
3792  * 01 = DDR3L 1.35V mode
3793  * 10 = Reserved
3794  * 11 = Reserved RC10[3:2]: Reserved.
3795  */
3796 #define DDRPHY_RDIMMCR1_RC11_MASK (0xF000U)
3797 #define DDRPHY_RDIMMCR1_RC11_SHIFT (12U)
3798 #define DDRPHY_RDIMMCR1_RC11_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR1_RC11_MASK) >> DDRPHY_RDIMMCR1_RC11_SHIFT)
3799 
3800 /*
3801  * RC10 (R)
3802  *
3803  * Control Word 10 (RDIMM Operating Speed Control Word): RC10[2:0] is RDIMM operating speed setting as follows: 000 = DDR3/DDR3L-800
3804  * 001 = DDR3/DDR3L-1066
3805  * 010 = DDR3/DDR3L-1333
3806  * 011 = DDR3/DDR3L-1600
3807  * 100 = Reserved
3808  * 101 = Reserved
3809  * 110 = Reserved
3810  * 111 = Reserved RC10[3]: Don’t care.
3811  */
3812 #define DDRPHY_RDIMMCR1_RC10_MASK (0xF00U)
3813 #define DDRPHY_RDIMMCR1_RC10_SHIFT (8U)
3814 #define DDRPHY_RDIMMCR1_RC10_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR1_RC10_MASK) >> DDRPHY_RDIMMCR1_RC10_SHIFT)
3815 
3816 /*
3817  * RC9 (R)
3818  *
3819  * Control Word 9 (Power Saving Settings Control Word): Bit definitions are: RC9[0]: 0 = Floating outputs as defined in RC0, 1 = Weak drive enabled. RC9[1]: 0 = Reserved.
3820  * RC9[2]: 0 = CKE power down with IBT ON, QxODT is a function of DxODT, 1 = CKE power down with IBT off, QxODT held LOW. RC9[2] is valid only when RC9[3] is 1.
3821  * RC9[3]: 0 = CKE power down mode disabled, 1 = CKE power down mode enabled.
3822  */
3823 #define DDRPHY_RDIMMCR1_RC9_MASK (0xF0U)
3824 #define DDRPHY_RDIMMCR1_RC9_SHIFT (4U)
3825 #define DDRPHY_RDIMMCR1_RC9_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR1_RC9_MASK) >> DDRPHY_RDIMMCR1_RC9_SHIFT)
3826 
3827 /*
3828  * RC8 (R)
3829  *
3830  * Control Word 8 (Additional Input Bus Termination Setting Control Word): RC8[2:0] is Input Bus Termination (IBT) setting as follows:
3831  * 000 = IBT as defined in RC2. 001 = Reserved
3832  * 010 = 200 Ohm
3833  * 011 = Reserved
3834  * 100 = 300 Ohm
3835  * 101 = Reserved
3836  * 110 = Reserved
3837  * 111 = Off
3838  * RC8[3]: 0 = IBT off when MIRROR is HIGH, 1 = IBT on when MIRROR is high
3839  */
3840 #define DDRPHY_RDIMMCR1_RC8_MASK (0xFU)
3841 #define DDRPHY_RDIMMCR1_RC8_SHIFT (0U)
3842 #define DDRPHY_RDIMMCR1_RC8_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR1_RC8_MASK) >> DDRPHY_RDIMMCR1_RC8_SHIFT)
3843 
3844 /* Bitfield definition for register: DCUAR */
3845 /*
3846  * ATYPE (R/W)
3847  *
3848  * Access Type: Specifies the type of access to be performed using this address. Valid values are:
3849  * 0 = Write access 1 = Read access
3850  */
3851 #define DDRPHY_DCUAR_ATYPE_MASK (0x800U)
3852 #define DDRPHY_DCUAR_ATYPE_SHIFT (11U)
3853 #define DDRPHY_DCUAR_ATYPE_SET(x) (((uint32_t)(x) << DDRPHY_DCUAR_ATYPE_SHIFT) & DDRPHY_DCUAR_ATYPE_MASK)
3854 #define DDRPHY_DCUAR_ATYPE_GET(x) (((uint32_t)(x) & DDRPHY_DCUAR_ATYPE_MASK) >> DDRPHY_DCUAR_ATYPE_SHIFT)
3855 
3856 /*
3857  * INCA (R/W)
3858  *
3859  * Increment Address: Specifies, if set, that the cache address specified in WADDR and SADDR should be automatically incremented after each access of the cache. The increment happens in such a way that all the slices of a selected word are first accessed before going to the next word.
3860  */
3861 #define DDRPHY_DCUAR_INCA_MASK (0x400U)
3862 #define DDRPHY_DCUAR_INCA_SHIFT (10U)
3863 #define DDRPHY_DCUAR_INCA_SET(x) (((uint32_t)(x) << DDRPHY_DCUAR_INCA_SHIFT) & DDRPHY_DCUAR_INCA_MASK)
3864 #define DDRPHY_DCUAR_INCA_GET(x) (((uint32_t)(x) & DDRPHY_DCUAR_INCA_MASK) >> DDRPHY_DCUAR_INCA_SHIFT)
3865 
3866 /*
3867  * CSEL (R/W)
3868  *
3869  * Cache Select: Selects the cache to be accessed. Valid values are: 00 = Command cache
3870  * 01 = Expected data cache 10 = Read data cache
3871  * 11 = Reserved
3872  */
3873 #define DDRPHY_DCUAR_CSEL_MASK (0x300U)
3874 #define DDRPHY_DCUAR_CSEL_SHIFT (8U)
3875 #define DDRPHY_DCUAR_CSEL_SET(x) (((uint32_t)(x) << DDRPHY_DCUAR_CSEL_SHIFT) & DDRPHY_DCUAR_CSEL_MASK)
3876 #define DDRPHY_DCUAR_CSEL_GET(x) (((uint32_t)(x) & DDRPHY_DCUAR_CSEL_MASK) >> DDRPHY_DCUAR_CSEL_SHIFT)
3877 
3878 /*
3879  * CSADDR (R/W)
3880  *
3881  * Cache Slice Address: Address of the cache slice to be accessed.
3882  */
3883 #define DDRPHY_DCUAR_CSADDR_MASK (0xF0U)
3884 #define DDRPHY_DCUAR_CSADDR_SHIFT (4U)
3885 #define DDRPHY_DCUAR_CSADDR_SET(x) (((uint32_t)(x) << DDRPHY_DCUAR_CSADDR_SHIFT) & DDRPHY_DCUAR_CSADDR_MASK)
3886 #define DDRPHY_DCUAR_CSADDR_GET(x) (((uint32_t)(x) & DDRPHY_DCUAR_CSADDR_MASK) >> DDRPHY_DCUAR_CSADDR_SHIFT)
3887 
3888 /*
3889  * CWADDR (R/W)
3890  *
3891  * Cache Word Address: Address of the cache word to be accessed.
3892  */
3893 #define DDRPHY_DCUAR_CWADDR_MASK (0xFU)
3894 #define DDRPHY_DCUAR_CWADDR_SHIFT (0U)
3895 #define DDRPHY_DCUAR_CWADDR_SET(x) (((uint32_t)(x) << DDRPHY_DCUAR_CWADDR_SHIFT) & DDRPHY_DCUAR_CWADDR_MASK)
3896 #define DDRPHY_DCUAR_CWADDR_GET(x) (((uint32_t)(x) & DDRPHY_DCUAR_CWADDR_MASK) >> DDRPHY_DCUAR_CWADDR_SHIFT)
3897 
3898 /* Bitfield definition for register: DCUDR */
3899 /*
3900  * CDATA (R/W)
3901  *
3902  * Cache Data: Data to be written to or read from a cache. This data corresponds to the cache word slice specified by the DCU Address Register.
3903  */
3904 #define DDRPHY_DCUDR_CDATA_MASK (0xFFFFFFFFUL)
3905 #define DDRPHY_DCUDR_CDATA_SHIFT (0U)
3906 #define DDRPHY_DCUDR_CDATA_SET(x) (((uint32_t)(x) << DDRPHY_DCUDR_CDATA_SHIFT) & DDRPHY_DCUDR_CDATA_MASK)
3907 #define DDRPHY_DCUDR_CDATA_GET(x) (((uint32_t)(x) & DDRPHY_DCUDR_CDATA_MASK) >> DDRPHY_DCUDR_CDATA_SHIFT)
3908 
3909 /* Bitfield definition for register: DCURR */
3910 /*
3911  * XCEN (R/W)
3912  *
3913  * Expected Compare Enable: Indicates, if set, that read data coming back from the SDRAM should be should be compared with the expected data.
3914  */
3915 #define DDRPHY_DCURR_XCEN_MASK (0x800000UL)
3916 #define DDRPHY_DCURR_XCEN_SHIFT (23U)
3917 #define DDRPHY_DCURR_XCEN_SET(x) (((uint32_t)(x) << DDRPHY_DCURR_XCEN_SHIFT) & DDRPHY_DCURR_XCEN_MASK)
3918 #define DDRPHY_DCURR_XCEN_GET(x) (((uint32_t)(x) & DDRPHY_DCURR_XCEN_MASK) >> DDRPHY_DCURR_XCEN_SHIFT)
3919 
3920 /*
3921  * RCEN (R/W)
3922  *
3923  * Read Capture Enable: Indicates, if set, that read data coming back from the SDRAM should be captured into the read data cache.
3924  */
3925 #define DDRPHY_DCURR_RCEN_MASK (0x400000UL)
3926 #define DDRPHY_DCURR_RCEN_SHIFT (22U)
3927 #define DDRPHY_DCURR_RCEN_SET(x) (((uint32_t)(x) << DDRPHY_DCURR_RCEN_SHIFT) & DDRPHY_DCURR_RCEN_MASK)
3928 #define DDRPHY_DCURR_RCEN_GET(x) (((uint32_t)(x) & DDRPHY_DCURR_RCEN_MASK) >> DDRPHY_DCURR_RCEN_SHIFT)
3929 
3930 /*
3931  * SCOF (R/W)
3932  *
3933  * Stop Capture On Full: Specifies, if set, that the capture of read data should stop when the capture cache is full.
3934  */
3935 #define DDRPHY_DCURR_SCOF_MASK (0x200000UL)
3936 #define DDRPHY_DCURR_SCOF_SHIFT (21U)
3937 #define DDRPHY_DCURR_SCOF_SET(x) (((uint32_t)(x) << DDRPHY_DCURR_SCOF_SHIFT) & DDRPHY_DCURR_SCOF_MASK)
3938 #define DDRPHY_DCURR_SCOF_GET(x) (((uint32_t)(x) & DDRPHY_DCURR_SCOF_MASK) >> DDRPHY_DCURR_SCOF_SHIFT)
3939 
3940 /*
3941  * SONF (R/W)
3942  *
3943  * Stop On Nth Fail: Specifies, if set, that the execution of commands and the capture of read data should stop when there are N read data failures. The number of failures is specified by NFAIL. Otherwise commands execute until the end of the program or until manually stopped using a STOP command.
3944  */
3945 #define DDRPHY_DCURR_SONF_MASK (0x100000UL)
3946 #define DDRPHY_DCURR_SONF_SHIFT (20U)
3947 #define DDRPHY_DCURR_SONF_SET(x) (((uint32_t)(x) << DDRPHY_DCURR_SONF_SHIFT) & DDRPHY_DCURR_SONF_MASK)
3948 #define DDRPHY_DCURR_SONF_GET(x) (((uint32_t)(x) & DDRPHY_DCURR_SONF_MASK) >> DDRPHY_DCURR_SONF_SHIFT)
3949 
3950 /*
3951  * NFAIL (R/W)
3952  *
3953  * Number of Failures: Specifies the number of failures after which the execution of commands and the capture of read data should stop if SONF bit of this register is set. Execution of commands and the capture of read data will stop after (NFAIL+1) failures if SONF is set.
3954  * Valid values are from 0 to 254.
3955  */
3956 #define DDRPHY_DCURR_NFAIL_MASK (0xFF000UL)
3957 #define DDRPHY_DCURR_NFAIL_SHIFT (12U)
3958 #define DDRPHY_DCURR_NFAIL_SET(x) (((uint32_t)(x) << DDRPHY_DCURR_NFAIL_SHIFT) & DDRPHY_DCURR_NFAIL_MASK)
3959 #define DDRPHY_DCURR_NFAIL_GET(x) (((uint32_t)(x) & DDRPHY_DCURR_NFAIL_MASK) >> DDRPHY_DCURR_NFAIL_SHIFT)
3960 
3961 /*
3962  * EADDR (R/W)
3963  *
3964  * End Address: Cache word address where the execution of command should end.
3965  */
3966 #define DDRPHY_DCURR_EADDR_MASK (0xF00U)
3967 #define DDRPHY_DCURR_EADDR_SHIFT (8U)
3968 #define DDRPHY_DCURR_EADDR_SET(x) (((uint32_t)(x) << DDRPHY_DCURR_EADDR_SHIFT) & DDRPHY_DCURR_EADDR_MASK)
3969 #define DDRPHY_DCURR_EADDR_GET(x) (((uint32_t)(x) & DDRPHY_DCURR_EADDR_MASK) >> DDRPHY_DCURR_EADDR_SHIFT)
3970 
3971 /*
3972  * SADDR (R/W)
3973  *
3974  * Start Address: Cache word address where the execution of commands should begin.
3975  */
3976 #define DDRPHY_DCURR_SADDR_MASK (0xF0U)
3977 #define DDRPHY_DCURR_SADDR_SHIFT (4U)
3978 #define DDRPHY_DCURR_SADDR_SET(x) (((uint32_t)(x) << DDRPHY_DCURR_SADDR_SHIFT) & DDRPHY_DCURR_SADDR_MASK)
3979 #define DDRPHY_DCURR_SADDR_GET(x) (((uint32_t)(x) & DDRPHY_DCURR_SADDR_MASK) >> DDRPHY_DCURR_SADDR_SHIFT)
3980 
3981 /*
3982  * DINST (R/W)
3983  *
3984  * DCU Instruction: Selects the DCU command to be executed: Valid values are: 0000 = NOP: No operation
3985  * 0001 = Run: Triggers the execution of commands in the command cache. 0010 = Stop: Stops the execution of commands in the command cache.
3986  * 0011 = Stop Loop: Stops the execution of an infinite loop in the command cache. 0100 = Reset: Resets all DCU run time registers. See “DCU Status” on page 255 for details.
3987  * 0101 – 1111 Reserved
3988  */
3989 #define DDRPHY_DCURR_DINST_MASK (0xFU)
3990 #define DDRPHY_DCURR_DINST_SHIFT (0U)
3991 #define DDRPHY_DCURR_DINST_SET(x) (((uint32_t)(x) << DDRPHY_DCURR_DINST_SHIFT) & DDRPHY_DCURR_DINST_MASK)
3992 #define DDRPHY_DCURR_DINST_GET(x) (((uint32_t)(x) & DDRPHY_DCURR_DINST_MASK) >> DDRPHY_DCURR_DINST_SHIFT)
3993 
3994 /* Bitfield definition for register: DCULR */
3995 /*
3996  * XLEADDR (R/W)
3997  *
3998  * Expected Data Loop End Address: The last expected data cache word address that contains valid expected data. Expected data should looped between 0 and this address.
3999  * XLEADDR field uses only the following bits based on the cache depth:
4000  * DCU expected data cache = 4, XLEADDR[1:0]
4001  * DCU expected data cache = 8, XLEADDR[2:0]
4002  * DCU expected data cache = 16, XLEADDR[3:0]
4003  */
4004 #define DDRPHY_DCULR_XLEADDR_MASK (0xF0000000UL)
4005 #define DDRPHY_DCULR_XLEADDR_SHIFT (28U)
4006 #define DDRPHY_DCULR_XLEADDR_SET(x) (((uint32_t)(x) << DDRPHY_DCULR_XLEADDR_SHIFT) & DDRPHY_DCULR_XLEADDR_MASK)
4007 #define DDRPHY_DCULR_XLEADDR_GET(x) (((uint32_t)(x) & DDRPHY_DCULR_XLEADDR_MASK) >> DDRPHY_DCULR_XLEADDR_SHIFT)
4008 
4009 /*
4010  * IDA (R/W)
4011  *
4012  * Increment DRAM Address: Indicates, if set, that DRAM addresses should be incremented every time a DRAM read/write command inside the loop is executed.
4013  */
4014 #define DDRPHY_DCULR_IDA_MASK (0x20000UL)
4015 #define DDRPHY_DCULR_IDA_SHIFT (17U)
4016 #define DDRPHY_DCULR_IDA_SET(x) (((uint32_t)(x) << DDRPHY_DCULR_IDA_SHIFT) & DDRPHY_DCULR_IDA_MASK)
4017 #define DDRPHY_DCULR_IDA_GET(x) (((uint32_t)(x) & DDRPHY_DCULR_IDA_MASK) >> DDRPHY_DCULR_IDA_SHIFT)
4018 
4019 /*
4020  * LINF (R/W)
4021  *
4022  * Loop Infinite: Indicates, if set, that the loop should be executed indefinitely until stopped by the STOP command. Otherwise the loop is execute LCNT times.
4023  */
4024 #define DDRPHY_DCULR_LINF_MASK (0x10000UL)
4025 #define DDRPHY_DCULR_LINF_SHIFT (16U)
4026 #define DDRPHY_DCULR_LINF_SET(x) (((uint32_t)(x) << DDRPHY_DCULR_LINF_SHIFT) & DDRPHY_DCULR_LINF_MASK)
4027 #define DDRPHY_DCULR_LINF_GET(x) (((uint32_t)(x) & DDRPHY_DCULR_LINF_MASK) >> DDRPHY_DCULR_LINF_SHIFT)
4028 
4029 /*
4030  * LCNT (R/W)
4031  *
4032  * Loop Count: The number of times that the loop should be executed if LINF is not set.
4033  */
4034 #define DDRPHY_DCULR_LCNT_MASK (0xFF00U)
4035 #define DDRPHY_DCULR_LCNT_SHIFT (8U)
4036 #define DDRPHY_DCULR_LCNT_SET(x) (((uint32_t)(x) << DDRPHY_DCULR_LCNT_SHIFT) & DDRPHY_DCULR_LCNT_MASK)
4037 #define DDRPHY_DCULR_LCNT_GET(x) (((uint32_t)(x) & DDRPHY_DCULR_LCNT_MASK) >> DDRPHY_DCULR_LCNT_SHIFT)
4038 
4039 /*
4040  * LEADDR (R/W)
4041  *
4042  * Loop End Address: Command cache word address where the loop should end.
4043  */
4044 #define DDRPHY_DCULR_LEADDR_MASK (0xF0U)
4045 #define DDRPHY_DCULR_LEADDR_SHIFT (4U)
4046 #define DDRPHY_DCULR_LEADDR_SET(x) (((uint32_t)(x) << DDRPHY_DCULR_LEADDR_SHIFT) & DDRPHY_DCULR_LEADDR_MASK)
4047 #define DDRPHY_DCULR_LEADDR_GET(x) (((uint32_t)(x) & DDRPHY_DCULR_LEADDR_MASK) >> DDRPHY_DCULR_LEADDR_SHIFT)
4048 
4049 /*
4050  * LSADDR (R/W)
4051  *
4052  * Loop Start Address: Command cache word address where the loop should start.
4053  */
4054 #define DDRPHY_DCULR_LSADDR_MASK (0xFU)
4055 #define DDRPHY_DCULR_LSADDR_SHIFT (0U)
4056 #define DDRPHY_DCULR_LSADDR_SET(x) (((uint32_t)(x) << DDRPHY_DCULR_LSADDR_SHIFT) & DDRPHY_DCULR_LSADDR_MASK)
4057 #define DDRPHY_DCULR_LSADDR_GET(x) (((uint32_t)(x) & DDRPHY_DCULR_LSADDR_MASK) >> DDRPHY_DCULR_LSADDR_SHIFT)
4058 
4059 /* Bitfield definition for register: DCUGCR */
4060 /*
4061  * RCSW (R/W)
4062  *
4063  * Read Capture Start Word: The capture and compare of read data should start after Nth word. For example setting this value to 12 will skip the first 12 read data.
4064  */
4065 #define DDRPHY_DCUGCR_RCSW_MASK (0xFFFFU)
4066 #define DDRPHY_DCUGCR_RCSW_SHIFT (0U)
4067 #define DDRPHY_DCUGCR_RCSW_SET(x) (((uint32_t)(x) << DDRPHY_DCUGCR_RCSW_SHIFT) & DDRPHY_DCUGCR_RCSW_MASK)
4068 #define DDRPHY_DCUGCR_RCSW_GET(x) (((uint32_t)(x) & DDRPHY_DCUGCR_RCSW_MASK) >> DDRPHY_DCUGCR_RCSW_SHIFT)
4069 
4070 /* Bitfield definition for register: DCUTPR */
4071 /*
4072  * TDCUT3 (R/W)
4073  *
4074  * DCU Generic Timing Parameter 3
4075  */
4076 #define DDRPHY_DCUTPR_TDCUT3_MASK (0xFF000000UL)
4077 #define DDRPHY_DCUTPR_TDCUT3_SHIFT (24U)
4078 #define DDRPHY_DCUTPR_TDCUT3_SET(x) (((uint32_t)(x) << DDRPHY_DCUTPR_TDCUT3_SHIFT) & DDRPHY_DCUTPR_TDCUT3_MASK)
4079 #define DDRPHY_DCUTPR_TDCUT3_GET(x) (((uint32_t)(x) & DDRPHY_DCUTPR_TDCUT3_MASK) >> DDRPHY_DCUTPR_TDCUT3_SHIFT)
4080 
4081 /*
4082  * TDCUT2 (R/W)
4083  *
4084  * DCU Generic Timing Parameter 2
4085  */
4086 #define DDRPHY_DCUTPR_TDCUT2_MASK (0xFF0000UL)
4087 #define DDRPHY_DCUTPR_TDCUT2_SHIFT (16U)
4088 #define DDRPHY_DCUTPR_TDCUT2_SET(x) (((uint32_t)(x) << DDRPHY_DCUTPR_TDCUT2_SHIFT) & DDRPHY_DCUTPR_TDCUT2_MASK)
4089 #define DDRPHY_DCUTPR_TDCUT2_GET(x) (((uint32_t)(x) & DDRPHY_DCUTPR_TDCUT2_MASK) >> DDRPHY_DCUTPR_TDCUT2_SHIFT)
4090 
4091 /*
4092  * TDCUT1 (R/W)
4093  *
4094  * DCU Generic Timing Parameter 1
4095  */
4096 #define DDRPHY_DCUTPR_TDCUT1_MASK (0xFF00U)
4097 #define DDRPHY_DCUTPR_TDCUT1_SHIFT (8U)
4098 #define DDRPHY_DCUTPR_TDCUT1_SET(x) (((uint32_t)(x) << DDRPHY_DCUTPR_TDCUT1_SHIFT) & DDRPHY_DCUTPR_TDCUT1_MASK)
4099 #define DDRPHY_DCUTPR_TDCUT1_GET(x) (((uint32_t)(x) & DDRPHY_DCUTPR_TDCUT1_MASK) >> DDRPHY_DCUTPR_TDCUT1_SHIFT)
4100 
4101 /*
4102  * TDCUT0 (R/W)
4103  *
4104  * DCU Generic Timing Parameter 0
4105  */
4106 #define DDRPHY_DCUTPR_TDCUT0_MASK (0xFFU)
4107 #define DDRPHY_DCUTPR_TDCUT0_SHIFT (0U)
4108 #define DDRPHY_DCUTPR_TDCUT0_SET(x) (((uint32_t)(x) << DDRPHY_DCUTPR_TDCUT0_SHIFT) & DDRPHY_DCUTPR_TDCUT0_MASK)
4109 #define DDRPHY_DCUTPR_TDCUT0_GET(x) (((uint32_t)(x) & DDRPHY_DCUTPR_TDCUT0_MASK) >> DDRPHY_DCUTPR_TDCUT0_SHIFT)
4110 
4111 /* Bitfield definition for register: DCUSR0 */
4112 /*
4113  * CFULL (R)
4114  *
4115  * Capture Full: Indicates, if set, that the capture cache is full.
4116  */
4117 #define DDRPHY_DCUSR0_CFULL_MASK (0x4U)
4118 #define DDRPHY_DCUSR0_CFULL_SHIFT (2U)
4119 #define DDRPHY_DCUSR0_CFULL_GET(x) (((uint32_t)(x) & DDRPHY_DCUSR0_CFULL_MASK) >> DDRPHY_DCUSR0_CFULL_SHIFT)
4120 
4121 /*
4122  * CFAIL (R)
4123  *
4124  * Capture Fail: Indicates, if set, that at least one read data word has failed.
4125  */
4126 #define DDRPHY_DCUSR0_CFAIL_MASK (0x2U)
4127 #define DDRPHY_DCUSR0_CFAIL_SHIFT (1U)
4128 #define DDRPHY_DCUSR0_CFAIL_GET(x) (((uint32_t)(x) & DDRPHY_DCUSR0_CFAIL_MASK) >> DDRPHY_DCUSR0_CFAIL_SHIFT)
4129 
4130 /*
4131  * RDONE (R)
4132  *
4133  * Run Done: Indicates, if set, that the DCU has finished executing the commands in the command cache. This bit is also set to indicate that a STOP command has successfully been executed and command execution has stopped.
4134  */
4135 #define DDRPHY_DCUSR0_RDONE_MASK (0x1U)
4136 #define DDRPHY_DCUSR0_RDONE_SHIFT (0U)
4137 #define DDRPHY_DCUSR0_RDONE_GET(x) (((uint32_t)(x) & DDRPHY_DCUSR0_RDONE_MASK) >> DDRPHY_DCUSR0_RDONE_SHIFT)
4138 
4139 /* Bitfield definition for register: DCUSR1 */
4140 /*
4141  * LPCNT (R)
4142  *
4143  * Loop Count: Indicates the value of the loop count. This is useful when the program has stopped because of failures to assess how many reads were executed before first fail.
4144  */
4145 #define DDRPHY_DCUSR1_LPCNT_MASK (0xFF000000UL)
4146 #define DDRPHY_DCUSR1_LPCNT_SHIFT (24U)
4147 #define DDRPHY_DCUSR1_LPCNT_GET(x) (((uint32_t)(x) & DDRPHY_DCUSR1_LPCNT_MASK) >> DDRPHY_DCUSR1_LPCNT_SHIFT)
4148 
4149 /*
4150  * FLCNT (R)
4151  *
4152  * Fail Count: Number of read words that have failed.
4153  */
4154 #define DDRPHY_DCUSR1_FLCNT_MASK (0xFF0000UL)
4155 #define DDRPHY_DCUSR1_FLCNT_SHIFT (16U)
4156 #define DDRPHY_DCUSR1_FLCNT_GET(x) (((uint32_t)(x) & DDRPHY_DCUSR1_FLCNT_MASK) >> DDRPHY_DCUSR1_FLCNT_SHIFT)
4157 
4158 /*
4159  * RDCNT (R)
4160  *
4161  * Read Count: Number of read words returned from the SDRAM.
4162  */
4163 #define DDRPHY_DCUSR1_RDCNT_MASK (0xFFFFU)
4164 #define DDRPHY_DCUSR1_RDCNT_SHIFT (0U)
4165 #define DDRPHY_DCUSR1_RDCNT_GET(x) (((uint32_t)(x) & DDRPHY_DCUSR1_RDCNT_MASK) >> DDRPHY_DCUSR1_RDCNT_SHIFT)
4166 
4167 /* Bitfield definition for register: BISTRR */
4168 /*
4169  * BCCSEL (R/W)
4170  *
4171  * BIST Clock Cycle Select: Selects the clock numbers on which the AC loopback data is written into the FIFO. Data is written into the loopback FIFO once every four clock cycles. Valid values are:
4172  * 00 = Clock cycle 0, 4, 8, 12, etc.
4173  * 01 = Clock cycle 1, 5, 9, 13, etc.
4174  * 10 = Clock cycle 2, 6, 10, 14, etc.
4175  * 11 = Clock cycle 3, 7, 11, 15, etc.
4176  */
4177 #define DDRPHY_BISTRR_BCCSEL_MASK (0x6000000UL)
4178 #define DDRPHY_BISTRR_BCCSEL_SHIFT (25U)
4179 #define DDRPHY_BISTRR_BCCSEL_SET(x) (((uint32_t)(x) << DDRPHY_BISTRR_BCCSEL_SHIFT) & DDRPHY_BISTRR_BCCSEL_MASK)
4180 #define DDRPHY_BISTRR_BCCSEL_GET(x) (((uint32_t)(x) & DDRPHY_BISTRR_BCCSEL_MASK) >> DDRPHY_BISTRR_BCCSEL_SHIFT)
4181 
4182 /*
4183  * BCKSEL (R/W)
4184  *
4185  * BIST CK Select: Selects the CK that should be used to register the AC loopback signals from the I/Os. Valid values are:
4186  * 00 = CK[0]
4187  * 01 = CK[1]
4188  * 10 = CK[2]
4189  * 11 = Reserved
4190  */
4191 #define DDRPHY_BISTRR_BCKSEL_MASK (0x1800000UL)
4192 #define DDRPHY_BISTRR_BCKSEL_SHIFT (23U)
4193 #define DDRPHY_BISTRR_BCKSEL_SET(x) (((uint32_t)(x) << DDRPHY_BISTRR_BCKSEL_SHIFT) & DDRPHY_BISTRR_BCKSEL_MASK)
4194 #define DDRPHY_BISTRR_BCKSEL_GET(x) (((uint32_t)(x) & DDRPHY_BISTRR_BCKSEL_MASK) >> DDRPHY_BISTRR_BCKSEL_SHIFT)
4195 
4196 /*
4197  * BDXSEL (R/W)
4198  *
4199  * BIST DATX8 Select: Select the byte lane for comparison of loopback/read data. Valid values are 0 to 8.
4200  */
4201 #define DDRPHY_BISTRR_BDXSEL_MASK (0x780000UL)
4202 #define DDRPHY_BISTRR_BDXSEL_SHIFT (19U)
4203 #define DDRPHY_BISTRR_BDXSEL_SET(x) (((uint32_t)(x) << DDRPHY_BISTRR_BDXSEL_SHIFT) & DDRPHY_BISTRR_BDXSEL_MASK)
4204 #define DDRPHY_BISTRR_BDXSEL_GET(x) (((uint32_t)(x) & DDRPHY_BISTRR_BDXSEL_MASK) >> DDRPHY_BISTRR_BDXSEL_SHIFT)
4205 
4206 /*
4207  * BDPAT (R/W)
4208  *
4209  * BIST Data Pattern: Selects the data pattern used during BIST. Valid values are: 00 = Walking 0
4210  * 01 = Walking 1
4211  * 10 = LFSR-based pseudo-random
4212  * 11 = User programmable (Not valid for AC loopback).
4213  */
4214 #define DDRPHY_BISTRR_BDPAT_MASK (0x60000UL)
4215 #define DDRPHY_BISTRR_BDPAT_SHIFT (17U)
4216 #define DDRPHY_BISTRR_BDPAT_SET(x) (((uint32_t)(x) << DDRPHY_BISTRR_BDPAT_SHIFT) & DDRPHY_BISTRR_BDPAT_MASK)
4217 #define DDRPHY_BISTRR_BDPAT_GET(x) (((uint32_t)(x) & DDRPHY_BISTRR_BDPAT_MASK) >> DDRPHY_BISTRR_BDPAT_SHIFT)
4218 
4219 /*
4220  * BDMEN (R/W)
4221  *
4222  * BIST Data Mask Enable: Enables, if set, that the data mask BIST should be included in the BIST run, i.e. data pattern generated and loopback data compared. This is valid only for loopback mode.
4223  */
4224 #define DDRPHY_BISTRR_BDMEN_MASK (0x10000UL)
4225 #define DDRPHY_BISTRR_BDMEN_SHIFT (16U)
4226 #define DDRPHY_BISTRR_BDMEN_SET(x) (((uint32_t)(x) << DDRPHY_BISTRR_BDMEN_SHIFT) & DDRPHY_BISTRR_BDMEN_MASK)
4227 #define DDRPHY_BISTRR_BDMEN_GET(x) (((uint32_t)(x) & DDRPHY_BISTRR_BDMEN_MASK) >> DDRPHY_BISTRR_BDMEN_SHIFT)
4228 
4229 /*
4230  * BACEN (R/W)
4231  *
4232  * BIST AC Enable: Enables the running of BIST on the address/command lane PHY. This bit is exclusive with BDXEN, i.e. both cannot be set to ‘1’ at the same time.
4233  */
4234 #define DDRPHY_BISTRR_BACEN_MASK (0x8000U)
4235 #define DDRPHY_BISTRR_BACEN_SHIFT (15U)
4236 #define DDRPHY_BISTRR_BACEN_SET(x) (((uint32_t)(x) << DDRPHY_BISTRR_BACEN_SHIFT) & DDRPHY_BISTRR_BACEN_MASK)
4237 #define DDRPHY_BISTRR_BACEN_GET(x) (((uint32_t)(x) & DDRPHY_BISTRR_BACEN_MASK) >> DDRPHY_BISTRR_BACEN_SHIFT)
4238 
4239 /*
4240  * BDXEN (R/W)
4241  *
4242  * BIST DATX8 Enable: Enables the running of BIST on the data byte lane PHYs. This bit is exclusive with BACEN, i.e. both cannot be set to ‘1’ at the same time.
4243  */
4244 #define DDRPHY_BISTRR_BDXEN_MASK (0x4000U)
4245 #define DDRPHY_BISTRR_BDXEN_SHIFT (14U)
4246 #define DDRPHY_BISTRR_BDXEN_SET(x) (((uint32_t)(x) << DDRPHY_BISTRR_BDXEN_SHIFT) & DDRPHY_BISTRR_BDXEN_MASK)
4247 #define DDRPHY_BISTRR_BDXEN_GET(x) (((uint32_t)(x) & DDRPHY_BISTRR_BDXEN_MASK) >> DDRPHY_BISTRR_BDXEN_SHIFT)
4248 
4249 /*
4250  * BSONF (R/W)
4251  *
4252  * BIST Stop On Nth Fail: Specifies, if set, that the BIST should stop when an nth data word or address/command comparison error has been encountered.
4253  */
4254 #define DDRPHY_BISTRR_BSONF_MASK (0x2000U)
4255 #define DDRPHY_BISTRR_BSONF_SHIFT (13U)
4256 #define DDRPHY_BISTRR_BSONF_SET(x) (((uint32_t)(x) << DDRPHY_BISTRR_BSONF_SHIFT) & DDRPHY_BISTRR_BSONF_MASK)
4257 #define DDRPHY_BISTRR_BSONF_GET(x) (((uint32_t)(x) & DDRPHY_BISTRR_BSONF_MASK) >> DDRPHY_BISTRR_BSONF_SHIFT)
4258 
4259 /*
4260  * NFAIL (R/W)
4261  *
4262  * Number of Failures: Specifies the number of failures after which the execution of commands and the capture of read data should stop if BSONF bit of this register is set. Execution of commands and the capture of read data will stop after (NFAIL+1) failures if BSONF is set.
4263  */
4264 #define DDRPHY_BISTRR_NFAIL_MASK (0x1FE0U)
4265 #define DDRPHY_BISTRR_NFAIL_SHIFT (5U)
4266 #define DDRPHY_BISTRR_NFAIL_SET(x) (((uint32_t)(x) << DDRPHY_BISTRR_NFAIL_SHIFT) & DDRPHY_BISTRR_NFAIL_MASK)
4267 #define DDRPHY_BISTRR_NFAIL_GET(x) (((uint32_t)(x) & DDRPHY_BISTRR_NFAIL_MASK) >> DDRPHY_BISTRR_NFAIL_SHIFT)
4268 
4269 /*
4270  * BINF (R/W)
4271  *
4272  * BIST Infinite Run: Specifies, if set, that the BIST should be run indefinitely until when it is either stopped or a failure has been encountered. Otherwise BIST is run until number of BIST words specified in the BISTWCR register has been generated.
4273  */
4274 #define DDRPHY_BISTRR_BINF_MASK (0x10U)
4275 #define DDRPHY_BISTRR_BINF_SHIFT (4U)
4276 #define DDRPHY_BISTRR_BINF_SET(x) (((uint32_t)(x) << DDRPHY_BISTRR_BINF_SHIFT) & DDRPHY_BISTRR_BINF_MASK)
4277 #define DDRPHY_BISTRR_BINF_GET(x) (((uint32_t)(x) & DDRPHY_BISTRR_BINF_MASK) >> DDRPHY_BISTRR_BINF_SHIFT)
4278 
4279 /*
4280  * BMODE (R/W)
4281  *
4282  * BIST Mode: Selects the mode in which BIST is run. Valid values are:
4283  * 0 = Loopback mode: Address, commands and data loop back at the PHY I/Os.
4284  * 1 = DRAM mode: Address, commands and data go to DRAM for normal memory accesses.
4285  */
4286 #define DDRPHY_BISTRR_BMODE_MASK (0x8U)
4287 #define DDRPHY_BISTRR_BMODE_SHIFT (3U)
4288 #define DDRPHY_BISTRR_BMODE_SET(x) (((uint32_t)(x) << DDRPHY_BISTRR_BMODE_SHIFT) & DDRPHY_BISTRR_BMODE_MASK)
4289 #define DDRPHY_BISTRR_BMODE_GET(x) (((uint32_t)(x) & DDRPHY_BISTRR_BMODE_MASK) >> DDRPHY_BISTRR_BMODE_SHIFT)
4290 
4291 /*
4292  * BINST (R/W)
4293  *
4294  * BIST Instruction: Selects the BIST instruction to be executed: Valid values are: 000 = NOP: No operation
4295  * 001 = Run: Triggers the running of the BIST. 010 = Stop: Stops the running of the BIST.
4296  * 011 = Reset: Resets all BIST run-time registers, such as error counters. 100 – 111 Reserved
4297  */
4298 #define DDRPHY_BISTRR_BINST_MASK (0x7U)
4299 #define DDRPHY_BISTRR_BINST_SHIFT (0U)
4300 #define DDRPHY_BISTRR_BINST_SET(x) (((uint32_t)(x) << DDRPHY_BISTRR_BINST_SHIFT) & DDRPHY_BISTRR_BINST_MASK)
4301 #define DDRPHY_BISTRR_BINST_GET(x) (((uint32_t)(x) & DDRPHY_BISTRR_BINST_MASK) >> DDRPHY_BISTRR_BINST_SHIFT)
4302 
4303 /* Bitfield definition for register: BISTWCR */
4304 /*
4305  * BWCNT (R/W)
4306  *
4307  * BIST Word Count: Indicates the number of words to generate during BIST. This must be a multiple of DRAM burst length (BL) divided by 2, e.g. for BL=8, valid values are 4, 8, 12, 16, and so on.
4308  */
4309 #define DDRPHY_BISTWCR_BWCNT_MASK (0xFFFFU)
4310 #define DDRPHY_BISTWCR_BWCNT_SHIFT (0U)
4311 #define DDRPHY_BISTWCR_BWCNT_SET(x) (((uint32_t)(x) << DDRPHY_BISTWCR_BWCNT_SHIFT) & DDRPHY_BISTWCR_BWCNT_MASK)
4312 #define DDRPHY_BISTWCR_BWCNT_GET(x) (((uint32_t)(x) & DDRPHY_BISTWCR_BWCNT_MASK) >> DDRPHY_BISTWCR_BWCNT_SHIFT)
4313 
4314 /* Bitfield definition for register: BISTMSKR0 */
4315 /*
4316  * ODTMSK (R/W)
4317  *
4318  * Mask bit for each of the up to 4 ODT bits.
4319  */
4320 #define DDRPHY_BISTMSKR0_ODTMSK_MASK (0xF0000000UL)
4321 #define DDRPHY_BISTMSKR0_ODTMSK_SHIFT (28U)
4322 #define DDRPHY_BISTMSKR0_ODTMSK_SET(x) (((uint32_t)(x) << DDRPHY_BISTMSKR0_ODTMSK_SHIFT) & DDRPHY_BISTMSKR0_ODTMSK_MASK)
4323 #define DDRPHY_BISTMSKR0_ODTMSK_GET(x) (((uint32_t)(x) & DDRPHY_BISTMSKR0_ODTMSK_MASK) >> DDRPHY_BISTMSKR0_ODTMSK_SHIFT)
4324 
4325 /*
4326  * CSMSK (R/W)
4327  *
4328  * Mask bit for each of the up to 4 CS# bits.
4329  */
4330 #define DDRPHY_BISTMSKR0_CSMSK_MASK (0xF000000UL)
4331 #define DDRPHY_BISTMSKR0_CSMSK_SHIFT (24U)
4332 #define DDRPHY_BISTMSKR0_CSMSK_SET(x) (((uint32_t)(x) << DDRPHY_BISTMSKR0_CSMSK_SHIFT) & DDRPHY_BISTMSKR0_CSMSK_MASK)
4333 #define DDRPHY_BISTMSKR0_CSMSK_GET(x) (((uint32_t)(x) & DDRPHY_BISTMSKR0_CSMSK_MASK) >> DDRPHY_BISTMSKR0_CSMSK_SHIFT)
4334 
4335 /*
4336  * CKEMSK (R/W)
4337  *
4338  * Mask bit for each of the up to 4 CKE bits.
4339  */
4340 #define DDRPHY_BISTMSKR0_CKEMSK_MASK (0xF00000UL)
4341 #define DDRPHY_BISTMSKR0_CKEMSK_SHIFT (20U)
4342 #define DDRPHY_BISTMSKR0_CKEMSK_SET(x) (((uint32_t)(x) << DDRPHY_BISTMSKR0_CKEMSK_SHIFT) & DDRPHY_BISTMSKR0_CKEMSK_MASK)
4343 #define DDRPHY_BISTMSKR0_CKEMSK_GET(x) (((uint32_t)(x) & DDRPHY_BISTMSKR0_CKEMSK_MASK) >> DDRPHY_BISTMSKR0_CKEMSK_SHIFT)
4344 
4345 /*
4346  * WEMSK (R/W)
4347  *
4348  * Mask bit for the WE#.
4349  */
4350 #define DDRPHY_BISTMSKR0_WEMSK_MASK (0x80000UL)
4351 #define DDRPHY_BISTMSKR0_WEMSK_SHIFT (19U)
4352 #define DDRPHY_BISTMSKR0_WEMSK_SET(x) (((uint32_t)(x) << DDRPHY_BISTMSKR0_WEMSK_SHIFT) & DDRPHY_BISTMSKR0_WEMSK_MASK)
4353 #define DDRPHY_BISTMSKR0_WEMSK_GET(x) (((uint32_t)(x) & DDRPHY_BISTMSKR0_WEMSK_MASK) >> DDRPHY_BISTMSKR0_WEMSK_SHIFT)
4354 
4355 /*
4356  * BAMSK (R/W)
4357  *
4358  * Mask bit for each of the up to 3 bank address bits.
4359  */
4360 #define DDRPHY_BISTMSKR0_BAMSK_MASK (0x70000UL)
4361 #define DDRPHY_BISTMSKR0_BAMSK_SHIFT (16U)
4362 #define DDRPHY_BISTMSKR0_BAMSK_SET(x) (((uint32_t)(x) << DDRPHY_BISTMSKR0_BAMSK_SHIFT) & DDRPHY_BISTMSKR0_BAMSK_MASK)
4363 #define DDRPHY_BISTMSKR0_BAMSK_GET(x) (((uint32_t)(x) & DDRPHY_BISTMSKR0_BAMSK_MASK) >> DDRPHY_BISTMSKR0_BAMSK_SHIFT)
4364 
4365 /*
4366  * AMSK (R/W)
4367  *
4368  * Mask bit for each of the up to 16 address bits.
4369  */
4370 #define DDRPHY_BISTMSKR0_AMSK_MASK (0xFFFFU)
4371 #define DDRPHY_BISTMSKR0_AMSK_SHIFT (0U)
4372 #define DDRPHY_BISTMSKR0_AMSK_SET(x) (((uint32_t)(x) << DDRPHY_BISTMSKR0_AMSK_SHIFT) & DDRPHY_BISTMSKR0_AMSK_MASK)
4373 #define DDRPHY_BISTMSKR0_AMSK_GET(x) (((uint32_t)(x) & DDRPHY_BISTMSKR0_AMSK_MASK) >> DDRPHY_BISTMSKR0_AMSK_SHIFT)
4374 
4375 /* Bitfield definition for register: BISTMSKR1 */
4376 /*
4377  * DMMSK (R/W)
4378  *
4379  * Mask bit for the data mask (DM) bit.
4380  */
4381 #define DDRPHY_BISTMSKR1_DMMSK_MASK (0xF0000000UL)
4382 #define DDRPHY_BISTMSKR1_DMMSK_SHIFT (28U)
4383 #define DDRPHY_BISTMSKR1_DMMSK_SET(x) (((uint32_t)(x) << DDRPHY_BISTMSKR1_DMMSK_SHIFT) & DDRPHY_BISTMSKR1_DMMSK_MASK)
4384 #define DDRPHY_BISTMSKR1_DMMSK_GET(x) (((uint32_t)(x) & DDRPHY_BISTMSKR1_DMMSK_MASK) >> DDRPHY_BISTMSKR1_DMMSK_SHIFT)
4385 
4386 /*
4387  * PARMSK (R/W)
4388  *
4389  * Mask bit for the PAR_IN. Only for DIMM parity support and only if the design is compiled for less than 3 ranks.
4390  */
4391 #define DDRPHY_BISTMSKR1_PARMSK_MASK (0x8000000UL)
4392 #define DDRPHY_BISTMSKR1_PARMSK_SHIFT (27U)
4393 #define DDRPHY_BISTMSKR1_PARMSK_SET(x) (((uint32_t)(x) << DDRPHY_BISTMSKR1_PARMSK_SHIFT) & DDRPHY_BISTMSKR1_PARMSK_MASK)
4394 #define DDRPHY_BISTMSKR1_PARMSK_GET(x) (((uint32_t)(x) & DDRPHY_BISTMSKR1_PARMSK_MASK) >> DDRPHY_BISTMSKR1_PARMSK_SHIFT)
4395 
4396 /*
4397  * CASMSK (R/W)
4398  *
4399  * Mask bit for the CAS.
4400  */
4401 #define DDRPHY_BISTMSKR1_CASMSK_MASK (0x2U)
4402 #define DDRPHY_BISTMSKR1_CASMSK_SHIFT (1U)
4403 #define DDRPHY_BISTMSKR1_CASMSK_SET(x) (((uint32_t)(x) << DDRPHY_BISTMSKR1_CASMSK_SHIFT) & DDRPHY_BISTMSKR1_CASMSK_MASK)
4404 #define DDRPHY_BISTMSKR1_CASMSK_GET(x) (((uint32_t)(x) & DDRPHY_BISTMSKR1_CASMSK_MASK) >> DDRPHY_BISTMSKR1_CASMSK_SHIFT)
4405 
4406 /*
4407  * RASMSK (R/W)
4408  *
4409  * Mask bit for the RAS.
4410  */
4411 #define DDRPHY_BISTMSKR1_RASMSK_MASK (0x1U)
4412 #define DDRPHY_BISTMSKR1_RASMSK_SHIFT (0U)
4413 #define DDRPHY_BISTMSKR1_RASMSK_SET(x) (((uint32_t)(x) << DDRPHY_BISTMSKR1_RASMSK_SHIFT) & DDRPHY_BISTMSKR1_RASMSK_MASK)
4414 #define DDRPHY_BISTMSKR1_RASMSK_GET(x) (((uint32_t)(x) & DDRPHY_BISTMSKR1_RASMSK_MASK) >> DDRPHY_BISTMSKR1_RASMSK_SHIFT)
4415 
4416 /* Bitfield definition for register: BISTMSKR2 */
4417 /*
4418  * DQMSK (R/W)
4419  *
4420  * Mask bit for each of the 8 data (DQ) bits.
4421  */
4422 #define DDRPHY_BISTMSKR2_DQMSK_MASK (0xFFFFFFFFUL)
4423 #define DDRPHY_BISTMSKR2_DQMSK_SHIFT (0U)
4424 #define DDRPHY_BISTMSKR2_DQMSK_SET(x) (((uint32_t)(x) << DDRPHY_BISTMSKR2_DQMSK_SHIFT) & DDRPHY_BISTMSKR2_DQMSK_MASK)
4425 #define DDRPHY_BISTMSKR2_DQMSK_GET(x) (((uint32_t)(x) & DDRPHY_BISTMSKR2_DQMSK_MASK) >> DDRPHY_BISTMSKR2_DQMSK_SHIFT)
4426 
4427 /* Bitfield definition for register: BISTLSR */
4428 /*
4429  * SEED (R/W)
4430  *
4431  * LFSR seed for pseudo-random BIST patterns.
4432  */
4433 #define DDRPHY_BISTLSR_SEED_MASK (0xFFFFFFFFUL)
4434 #define DDRPHY_BISTLSR_SEED_SHIFT (0U)
4435 #define DDRPHY_BISTLSR_SEED_SET(x) (((uint32_t)(x) << DDRPHY_BISTLSR_SEED_SHIFT) & DDRPHY_BISTLSR_SEED_MASK)
4436 #define DDRPHY_BISTLSR_SEED_GET(x) (((uint32_t)(x) & DDRPHY_BISTLSR_SEED_MASK) >> DDRPHY_BISTLSR_SEED_SHIFT)
4437 
4438 /* Bitfield definition for register: BISTAR0 */
4439 /*
4440  * BBANK (R/W)
4441  *
4442  * BIST Bank Address: Selects the SDRAM bank address to be used during BIST.
4443  */
4444 #define DDRPHY_BISTAR0_BBANK_MASK (0x70000000UL)
4445 #define DDRPHY_BISTAR0_BBANK_SHIFT (28U)
4446 #define DDRPHY_BISTAR0_BBANK_SET(x) (((uint32_t)(x) << DDRPHY_BISTAR0_BBANK_SHIFT) & DDRPHY_BISTAR0_BBANK_MASK)
4447 #define DDRPHY_BISTAR0_BBANK_GET(x) (((uint32_t)(x) & DDRPHY_BISTAR0_BBANK_MASK) >> DDRPHY_BISTAR0_BBANK_SHIFT)
4448 
4449 /*
4450  * BROW (R/W)
4451  *
4452  * BIST Row Address: Selects the SDRAM row address to be used during BIST.
4453  */
4454 #define DDRPHY_BISTAR0_BROW_MASK (0xFFFF000UL)
4455 #define DDRPHY_BISTAR0_BROW_SHIFT (12U)
4456 #define DDRPHY_BISTAR0_BROW_SET(x) (((uint32_t)(x) << DDRPHY_BISTAR0_BROW_SHIFT) & DDRPHY_BISTAR0_BROW_MASK)
4457 #define DDRPHY_BISTAR0_BROW_GET(x) (((uint32_t)(x) & DDRPHY_BISTAR0_BROW_MASK) >> DDRPHY_BISTAR0_BROW_SHIFT)
4458 
4459 /*
4460  * BCOL (R/W)
4461  *
4462  * BIST Column Address: Selects the SDRAM column address to be used during BIST. The lower bits of this address must be “0000” for BL16, “000” for BL8, “00” for BL4 and “0” for BL2.
4463  */
4464 #define DDRPHY_BISTAR0_BCOL_MASK (0xFFFU)
4465 #define DDRPHY_BISTAR0_BCOL_SHIFT (0U)
4466 #define DDRPHY_BISTAR0_BCOL_SET(x) (((uint32_t)(x) << DDRPHY_BISTAR0_BCOL_SHIFT) & DDRPHY_BISTAR0_BCOL_MASK)
4467 #define DDRPHY_BISTAR0_BCOL_GET(x) (((uint32_t)(x) & DDRPHY_BISTAR0_BCOL_MASK) >> DDRPHY_BISTAR0_BCOL_SHIFT)
4468 
4469 /* Bitfield definition for register: BISTAR1 */
4470 /*
4471  * BAINC (R/W)
4472  *
4473  * BIST Address Increment: Selects the value by which the SDRAM address is incremented for each write/read access. This value must be at the beginning of a burst boundary, i.e. the lower bits must be “0000” for BL16, “000” for BL8, “00” for BL4 and “0” for BL2.
4474  */
4475 #define DDRPHY_BISTAR1_BAINC_MASK (0xFFF0U)
4476 #define DDRPHY_BISTAR1_BAINC_SHIFT (4U)
4477 #define DDRPHY_BISTAR1_BAINC_SET(x) (((uint32_t)(x) << DDRPHY_BISTAR1_BAINC_SHIFT) & DDRPHY_BISTAR1_BAINC_MASK)
4478 #define DDRPHY_BISTAR1_BAINC_GET(x) (((uint32_t)(x) & DDRPHY_BISTAR1_BAINC_MASK) >> DDRPHY_BISTAR1_BAINC_SHIFT)
4479 
4480 /*
4481  * BMRANK (R/W)
4482  *
4483  * BIST Maximum Rank: Specifies the maximum SDRAM rank to be used during BIST. The default value is set to maximum ranks minus 1. Example default shown here is for a 4-rank system
4484  */
4485 #define DDRPHY_BISTAR1_BMRANK_MASK (0xCU)
4486 #define DDRPHY_BISTAR1_BMRANK_SHIFT (2U)
4487 #define DDRPHY_BISTAR1_BMRANK_SET(x) (((uint32_t)(x) << DDRPHY_BISTAR1_BMRANK_SHIFT) & DDRPHY_BISTAR1_BMRANK_MASK)
4488 #define DDRPHY_BISTAR1_BMRANK_GET(x) (((uint32_t)(x) & DDRPHY_BISTAR1_BMRANK_MASK) >> DDRPHY_BISTAR1_BMRANK_SHIFT)
4489 
4490 /*
4491  * BRANK (R/W)
4492  *
4493  * BIST Rank: Selects the SDRAM rank to be used during BIST. Valid values range from 0 to maximum ranks minus 1.
4494  */
4495 #define DDRPHY_BISTAR1_BRANK_MASK (0x3U)
4496 #define DDRPHY_BISTAR1_BRANK_SHIFT (0U)
4497 #define DDRPHY_BISTAR1_BRANK_SET(x) (((uint32_t)(x) << DDRPHY_BISTAR1_BRANK_SHIFT) & DDRPHY_BISTAR1_BRANK_MASK)
4498 #define DDRPHY_BISTAR1_BRANK_GET(x) (((uint32_t)(x) & DDRPHY_BISTAR1_BRANK_MASK) >> DDRPHY_BISTAR1_BRANK_SHIFT)
4499 
4500 /* Bitfield definition for register: BISTAR2 */
4501 /*
4502  * BMBANK (R/W)
4503  *
4504  * BIST Maximum Bank Address: Specifies the maximum SDRAM bank address to be used during BIST before the address increments to the next rank.
4505  */
4506 #define DDRPHY_BISTAR2_BMBANK_MASK (0x70000000UL)
4507 #define DDRPHY_BISTAR2_BMBANK_SHIFT (28U)
4508 #define DDRPHY_BISTAR2_BMBANK_SET(x) (((uint32_t)(x) << DDRPHY_BISTAR2_BMBANK_SHIFT) & DDRPHY_BISTAR2_BMBANK_MASK)
4509 #define DDRPHY_BISTAR2_BMBANK_GET(x) (((uint32_t)(x) & DDRPHY_BISTAR2_BMBANK_MASK) >> DDRPHY_BISTAR2_BMBANK_SHIFT)
4510 
4511 /*
4512  * BMROW (R/W)
4513  *
4514  * BIST Maximum Row Address: Specifies the maximum SDRAM row address to be used during BIST before the address increments to the next bank.
4515  */
4516 #define DDRPHY_BISTAR2_BMROW_MASK (0xFFFF000UL)
4517 #define DDRPHY_BISTAR2_BMROW_SHIFT (12U)
4518 #define DDRPHY_BISTAR2_BMROW_SET(x) (((uint32_t)(x) << DDRPHY_BISTAR2_BMROW_SHIFT) & DDRPHY_BISTAR2_BMROW_MASK)
4519 #define DDRPHY_BISTAR2_BMROW_GET(x) (((uint32_t)(x) & DDRPHY_BISTAR2_BMROW_MASK) >> DDRPHY_BISTAR2_BMROW_SHIFT)
4520 
4521 /*
4522  * BMCOL (R/W)
4523  *
4524  * BIST Maximum Column Address: Specifies the maximum SDRAM column address to be used during BIST before the address increments to the next row.
4525  */
4526 #define DDRPHY_BISTAR2_BMCOL_MASK (0xFFFU)
4527 #define DDRPHY_BISTAR2_BMCOL_SHIFT (0U)
4528 #define DDRPHY_BISTAR2_BMCOL_SET(x) (((uint32_t)(x) << DDRPHY_BISTAR2_BMCOL_SHIFT) & DDRPHY_BISTAR2_BMCOL_MASK)
4529 #define DDRPHY_BISTAR2_BMCOL_GET(x) (((uint32_t)(x) & DDRPHY_BISTAR2_BMCOL_MASK) >> DDRPHY_BISTAR2_BMCOL_SHIFT)
4530 
4531 /* Bitfield definition for register: BISTUDPR */
4532 /*
4533  * BUDP1 (R/W)
4534  *
4535  * BIST User Data Pattern 1: Data to be applied on odd DQ pins during BIST.
4536  */
4537 #define DDRPHY_BISTUDPR_BUDP1_MASK (0xFFFF0000UL)
4538 #define DDRPHY_BISTUDPR_BUDP1_SHIFT (16U)
4539 #define DDRPHY_BISTUDPR_BUDP1_SET(x) (((uint32_t)(x) << DDRPHY_BISTUDPR_BUDP1_SHIFT) & DDRPHY_BISTUDPR_BUDP1_MASK)
4540 #define DDRPHY_BISTUDPR_BUDP1_GET(x) (((uint32_t)(x) & DDRPHY_BISTUDPR_BUDP1_MASK) >> DDRPHY_BISTUDPR_BUDP1_SHIFT)
4541 
4542 /*
4543  * BUDP0 (R/W)
4544  *
4545  * BIST User Data Pattern 0: Data to be applied on even DQ pins during BIST.
4546  */
4547 #define DDRPHY_BISTUDPR_BUDP0_MASK (0xFFFFU)
4548 #define DDRPHY_BISTUDPR_BUDP0_SHIFT (0U)
4549 #define DDRPHY_BISTUDPR_BUDP0_SET(x) (((uint32_t)(x) << DDRPHY_BISTUDPR_BUDP0_SHIFT) & DDRPHY_BISTUDPR_BUDP0_MASK)
4550 #define DDRPHY_BISTUDPR_BUDP0_GET(x) (((uint32_t)(x) & DDRPHY_BISTUDPR_BUDP0_MASK) >> DDRPHY_BISTUDPR_BUDP0_SHIFT)
4551 
4552 /* Bitfield definition for register: BISTGSR */
4553 /*
4554  * CASBER (R)
4555  *
4556  * CAS Bit Error: Indicates the number of bit errors on CAS.
4557  */
4558 #define DDRPHY_BISTGSR_CASBER_MASK (0xC0000000UL)
4559 #define DDRPHY_BISTGSR_CASBER_SHIFT (30U)
4560 #define DDRPHY_BISTGSR_CASBER_GET(x) (((uint32_t)(x) & DDRPHY_BISTGSR_CASBER_MASK) >> DDRPHY_BISTGSR_CASBER_SHIFT)
4561 
4562 /*
4563  * RASBER (R)
4564  *
4565  * RAS Bit Error: Indicates the number of bit errors on RAS.
4566  */
4567 #define DDRPHY_BISTGSR_RASBER_MASK (0x30000000UL)
4568 #define DDRPHY_BISTGSR_RASBER_SHIFT (28U)
4569 #define DDRPHY_BISTGSR_RASBER_GET(x) (((uint32_t)(x) & DDRPHY_BISTGSR_RASBER_MASK) >> DDRPHY_BISTGSR_RASBER_SHIFT)
4570 
4571 /*
4572  * DMBER (R)
4573  *
4574  * DM Bit Error: Indicates the number of bit errors on data mask (DM) bit. DMBER[1:0] are for even DQS cycles first DM beat, and DMBER[3:2] are for even DQS cycles second DM beat. Similarly, DMBER[5:4] are for odd DQS cycles first DM beat, and DMBER[7:6] are for odd DQS cycles second DM beat.
4575  */
4576 #define DDRPHY_BISTGSR_DMBER_MASK (0xFF00000UL)
4577 #define DDRPHY_BISTGSR_DMBER_SHIFT (20U)
4578 #define DDRPHY_BISTGSR_DMBER_GET(x) (((uint32_t)(x) & DDRPHY_BISTGSR_DMBER_MASK) >> DDRPHY_BISTGSR_DMBER_SHIFT)
4579 
4580 /*
4581  * PARBER (R)
4582  *
4583  * PAR_IN Bit Error (DIMM Only): Indicates the number of bit errors on PAR_IN
4584  */
4585 #define DDRPHY_BISTGSR_PARBER_MASK (0x30000UL)
4586 #define DDRPHY_BISTGSR_PARBER_SHIFT (16U)
4587 #define DDRPHY_BISTGSR_PARBER_GET(x) (((uint32_t)(x) & DDRPHY_BISTGSR_PARBER_MASK) >> DDRPHY_BISTGSR_PARBER_SHIFT)
4588 
4589 /*
4590  * BDXERR (R)
4591  *
4592  * BIST Data Error: indicates, if set, that there is a data comparison error in the byte lane.
4593  */
4594 #define DDRPHY_BISTGSR_BDXERR_MASK (0x4U)
4595 #define DDRPHY_BISTGSR_BDXERR_SHIFT (2U)
4596 #define DDRPHY_BISTGSR_BDXERR_GET(x) (((uint32_t)(x) & DDRPHY_BISTGSR_BDXERR_MASK) >> DDRPHY_BISTGSR_BDXERR_SHIFT)
4597 
4598 /*
4599  * BACERR (R)
4600  *
4601  * BIST Address/Command Error: indicates, if set, that there is a data comparison error in the address/command lane.
4602  */
4603 #define DDRPHY_BISTGSR_BACERR_MASK (0x2U)
4604 #define DDRPHY_BISTGSR_BACERR_SHIFT (1U)
4605 #define DDRPHY_BISTGSR_BACERR_GET(x) (((uint32_t)(x) & DDRPHY_BISTGSR_BACERR_MASK) >> DDRPHY_BISTGSR_BACERR_SHIFT)
4606 
4607 /*
4608  * BDONE (R)
4609  *
4610  * BIST Done: Indicates, if set, that the BIST has finished executing. This bit is reset to zero when BIST is triggered.
4611  */
4612 #define DDRPHY_BISTGSR_BDONE_MASK (0x1U)
4613 #define DDRPHY_BISTGSR_BDONE_SHIFT (0U)
4614 #define DDRPHY_BISTGSR_BDONE_GET(x) (((uint32_t)(x) & DDRPHY_BISTGSR_BDONE_MASK) >> DDRPHY_BISTGSR_BDONE_SHIFT)
4615 
4616 /* Bitfield definition for register: BISTWER */
4617 /*
4618  * DXWER (R)
4619  *
4620  * Byte Word Error: Indicates the number of word errors on the byte lane. An error on any bit of the data bus including the data mask bit increments the error count.
4621  */
4622 #define DDRPHY_BISTWER_DXWER_MASK (0xFFFF0000UL)
4623 #define DDRPHY_BISTWER_DXWER_SHIFT (16U)
4624 #define DDRPHY_BISTWER_DXWER_GET(x) (((uint32_t)(x) & DDRPHY_BISTWER_DXWER_MASK) >> DDRPHY_BISTWER_DXWER_SHIFT)
4625 
4626 /*
4627  * ACWER (R)
4628  *
4629  * Address/Command Word Error: Indicates the number of word errors on the address/command lane. An error on any bit of the address/command bus increments the error count.
4630  */
4631 #define DDRPHY_BISTWER_ACWER_MASK (0xFFFFU)
4632 #define DDRPHY_BISTWER_ACWER_SHIFT (0U)
4633 #define DDRPHY_BISTWER_ACWER_GET(x) (((uint32_t)(x) & DDRPHY_BISTWER_ACWER_MASK) >> DDRPHY_BISTWER_ACWER_SHIFT)
4634 
4635 /* Bitfield definition for register: BISTBER0 */
4636 /*
4637  * ABER (R)
4638  *
4639  * Address Bit Error: Each group of two bits indicate the bit error count on each of the
4640  */
4641 #define DDRPHY_BISTBER0_ABER_MASK (0xFFFFFFFFUL)
4642 #define DDRPHY_BISTBER0_ABER_SHIFT (0U)
4643 #define DDRPHY_BISTBER0_ABER_GET(x) (((uint32_t)(x) & DDRPHY_BISTBER0_ABER_MASK) >> DDRPHY_BISTBER0_ABER_SHIFT)
4644 
4645 /* Bitfield definition for register: BISTBER1 */
4646 /*
4647  * ODTBER (R)
4648  *
4649  * ODT Bit Error: Each group of two bits indicates the bit error count on each of the up to 4 ODT bits. [1:0] is the error count for ODT[0], [3:2] for ODT[1], and so on.
4650  */
4651 #define DDRPHY_BISTBER1_ODTBER_MASK (0xFF000000UL)
4652 #define DDRPHY_BISTBER1_ODTBER_SHIFT (24U)
4653 #define DDRPHY_BISTBER1_ODTBER_GET(x) (((uint32_t)(x) & DDRPHY_BISTBER1_ODTBER_MASK) >> DDRPHY_BISTBER1_ODTBER_SHIFT)
4654 
4655 /*
4656  * CSBER (R)
4657  *
4658  * CS# Bit Error: Each group of two bits indicate the bit error count on each of the up to 4 CS# bits. [1:0] is the error count for CS#[0], [3:2] for CS#[1], and so on.
4659  */
4660 #define DDRPHY_BISTBER1_CSBER_MASK (0xFF0000UL)
4661 #define DDRPHY_BISTBER1_CSBER_SHIFT (16U)
4662 #define DDRPHY_BISTBER1_CSBER_GET(x) (((uint32_t)(x) & DDRPHY_BISTBER1_CSBER_MASK) >> DDRPHY_BISTBER1_CSBER_SHIFT)
4663 
4664 /*
4665  * CKEBER (R)
4666  *
4667  * CKE Bit Error: Each group of two bits indicate the bit error count on each of the up to 4 CKE bits. [1:0] is the error count for CKE[0], [3:2] for CKE[1], and so on.
4668  */
4669 #define DDRPHY_BISTBER1_CKEBER_MASK (0xFF00U)
4670 #define DDRPHY_BISTBER1_CKEBER_SHIFT (8U)
4671 #define DDRPHY_BISTBER1_CKEBER_GET(x) (((uint32_t)(x) & DDRPHY_BISTBER1_CKEBER_MASK) >> DDRPHY_BISTBER1_CKEBER_SHIFT)
4672 
4673 /*
4674  * WEBER (R)
4675  *
4676  * WE# Bit Error: Indicates the number of bit errors on WE#.
4677  */
4678 #define DDRPHY_BISTBER1_WEBER_MASK (0xC0U)
4679 #define DDRPHY_BISTBER1_WEBER_SHIFT (6U)
4680 #define DDRPHY_BISTBER1_WEBER_GET(x) (((uint32_t)(x) & DDRPHY_BISTBER1_WEBER_MASK) >> DDRPHY_BISTBER1_WEBER_SHIFT)
4681 
4682 /*
4683  * BABER (R)
4684  *
4685  * Bank Address Bit Error: Each group of two bits indicate the bit error count on each of the up to 3 bank address bits. [1:0] is the error count for BA[0], [3:2] for BA[1], and so on.
4686  */
4687 #define DDRPHY_BISTBER1_BABER_MASK (0x3FU)
4688 #define DDRPHY_BISTBER1_BABER_SHIFT (0U)
4689 #define DDRPHY_BISTBER1_BABER_GET(x) (((uint32_t)(x) & DDRPHY_BISTBER1_BABER_MASK) >> DDRPHY_BISTBER1_BABER_SHIFT)
4690 
4691 /* Bitfield definition for register: BISTBER2 */
4692 /*
4693  * DQBER0 (R)
4694  *
4695  * Data Bit Error: The error count for even DQS cycles. The first 16 bits indicate the error count for the first data beat (i.e. the data driven out on DQ[7:0] on the rising edge of DQS). The second 16 bits indicate the error on the second data beat (i.e. the error count of the data driven out on DQ[7:0] on the falling edge of DQS). For each of the 16-bit group, the first 2 bits are for DQ[0], the second for DQ[1], and so on.
4696  */
4697 #define DDRPHY_BISTBER2_DQBER0_MASK (0xFFFFFFFFUL)
4698 #define DDRPHY_BISTBER2_DQBER0_SHIFT (0U)
4699 #define DDRPHY_BISTBER2_DQBER0_GET(x) (((uint32_t)(x) & DDRPHY_BISTBER2_DQBER0_MASK) >> DDRPHY_BISTBER2_DQBER0_SHIFT)
4700 
4701 /* Bitfield definition for register: BISTBER3 */
4702 /*
4703  * DQBER1 (R)
4704  *
4705  * Data Bit Error: The error count for odd DQS cycles. The first 16 bits indicate the error count for the first data beat (i.e. the data driven out on DQ[7:0] on the rising edge of DQS). The second 16 bits indicate the error on the second data beat (i.e. the error count of the data driven out on DQ[7:0] on the falling edge of DQS). For each of the 16-bit group, the first 2 bits are for DQ[0], the second for DQ[1], and so on.
4706  */
4707 #define DDRPHY_BISTBER3_DQBER1_MASK (0xFFFFFFFFUL)
4708 #define DDRPHY_BISTBER3_DQBER1_SHIFT (0U)
4709 #define DDRPHY_BISTBER3_DQBER1_GET(x) (((uint32_t)(x) & DDRPHY_BISTBER3_DQBER1_MASK) >> DDRPHY_BISTBER3_DQBER1_SHIFT)
4710 
4711 /* Bitfield definition for register: BISTWCSR */
4712 /*
4713  * DXWCNT (R)
4714  *
4715  * Byte Word Count: Indicates the number of words received from the byte lane.
4716  */
4717 #define DDRPHY_BISTWCSR_DXWCNT_MASK (0xFFFF0000UL)
4718 #define DDRPHY_BISTWCSR_DXWCNT_SHIFT (16U)
4719 #define DDRPHY_BISTWCSR_DXWCNT_GET(x) (((uint32_t)(x) & DDRPHY_BISTWCSR_DXWCNT_MASK) >> DDRPHY_BISTWCSR_DXWCNT_SHIFT)
4720 
4721 /*
4722  * ACWCNT (R)
4723  *
4724  * Address/Command Word Count: Indicates the number of words received from the address/command lane.
4725  */
4726 #define DDRPHY_BISTWCSR_ACWCNT_MASK (0xFFFFU)
4727 #define DDRPHY_BISTWCSR_ACWCNT_SHIFT (0U)
4728 #define DDRPHY_BISTWCSR_ACWCNT_GET(x) (((uint32_t)(x) & DDRPHY_BISTWCSR_ACWCNT_MASK) >> DDRPHY_BISTWCSR_ACWCNT_SHIFT)
4729 
4730 /* Bitfield definition for register: BISTFWR0 */
4731 /*
4732  * ODTWEBS (R)
4733  *
4734  * Bit status during a word error for each of the up to 4 ODT bits.
4735  */
4736 #define DDRPHY_BISTFWR0_ODTWEBS_MASK (0xF0000000UL)
4737 #define DDRPHY_BISTFWR0_ODTWEBS_SHIFT (28U)
4738 #define DDRPHY_BISTFWR0_ODTWEBS_GET(x) (((uint32_t)(x) & DDRPHY_BISTFWR0_ODTWEBS_MASK) >> DDRPHY_BISTFWR0_ODTWEBS_SHIFT)
4739 
4740 /*
4741  * CSWEBS (R)
4742  *
4743  * Bit status during a word error for each of the up to 4 CS# bits.
4744  */
4745 #define DDRPHY_BISTFWR0_CSWEBS_MASK (0xF000000UL)
4746 #define DDRPHY_BISTFWR0_CSWEBS_SHIFT (24U)
4747 #define DDRPHY_BISTFWR0_CSWEBS_GET(x) (((uint32_t)(x) & DDRPHY_BISTFWR0_CSWEBS_MASK) >> DDRPHY_BISTFWR0_CSWEBS_SHIFT)
4748 
4749 /*
4750  * CKEWEBS (R)
4751  *
4752  * Bit status during a word error for each of the up to 4 CKE bits.
4753  */
4754 #define DDRPHY_BISTFWR0_CKEWEBS_MASK (0xF00000UL)
4755 #define DDRPHY_BISTFWR0_CKEWEBS_SHIFT (20U)
4756 #define DDRPHY_BISTFWR0_CKEWEBS_GET(x) (((uint32_t)(x) & DDRPHY_BISTFWR0_CKEWEBS_MASK) >> DDRPHY_BISTFWR0_CKEWEBS_SHIFT)
4757 
4758 /*
4759  * WEWEBS (R)
4760  *
4761  * Bit status during a word error for the WE#.
4762  */
4763 #define DDRPHY_BISTFWR0_WEWEBS_MASK (0x80000UL)
4764 #define DDRPHY_BISTFWR0_WEWEBS_SHIFT (19U)
4765 #define DDRPHY_BISTFWR0_WEWEBS_GET(x) (((uint32_t)(x) & DDRPHY_BISTFWR0_WEWEBS_MASK) >> DDRPHY_BISTFWR0_WEWEBS_SHIFT)
4766 
4767 /*
4768  * BAWEBS (R)
4769  *
4770  * Bit status during a word error for each of the up to 3 bank address bits.
4771  */
4772 #define DDRPHY_BISTFWR0_BAWEBS_MASK (0x70000UL)
4773 #define DDRPHY_BISTFWR0_BAWEBS_SHIFT (16U)
4774 #define DDRPHY_BISTFWR0_BAWEBS_GET(x) (((uint32_t)(x) & DDRPHY_BISTFWR0_BAWEBS_MASK) >> DDRPHY_BISTFWR0_BAWEBS_SHIFT)
4775 
4776 /*
4777  * AWEBS (R)
4778  *
4779  * Bit status during a word error for each of the up to 16 address bits.
4780  */
4781 #define DDRPHY_BISTFWR0_AWEBS_MASK (0xFFFFU)
4782 #define DDRPHY_BISTFWR0_AWEBS_SHIFT (0U)
4783 #define DDRPHY_BISTFWR0_AWEBS_GET(x) (((uint32_t)(x) & DDRPHY_BISTFWR0_AWEBS_MASK) >> DDRPHY_BISTFWR0_AWEBS_SHIFT)
4784 
4785 /* Bitfield definition for register: BISTFWR1 */
4786 /*
4787  * DMWEBS (R)
4788  *
4789  * Bit status during a word error for the data mask (DM) bit. DMWEBS [0] is for the first DM beat, DMWEBS [1] is for the second DM beat, and so on.
4790  */
4791 #define DDRPHY_BISTFWR1_DMWEBS_MASK (0xF0000000UL)
4792 #define DDRPHY_BISTFWR1_DMWEBS_SHIFT (28U)
4793 #define DDRPHY_BISTFWR1_DMWEBS_GET(x) (((uint32_t)(x) & DDRPHY_BISTFWR1_DMWEBS_MASK) >> DDRPHY_BISTFWR1_DMWEBS_SHIFT)
4794 
4795 /*
4796  * PARWEBS (R)
4797  *
4798  * Bit status during a word error for the PAR_IN. Only for DIMM parity support
4799  */
4800 #define DDRPHY_BISTFWR1_PARWEBS_MASK (0x4000000UL)
4801 #define DDRPHY_BISTFWR1_PARWEBS_SHIFT (26U)
4802 #define DDRPHY_BISTFWR1_PARWEBS_GET(x) (((uint32_t)(x) & DDRPHY_BISTFWR1_PARWEBS_MASK) >> DDRPHY_BISTFWR1_PARWEBS_SHIFT)
4803 
4804 /*
4805  * CASWEBS (R)
4806  *
4807  * Bit status during a word error for the CAS.
4808  */
4809 #define DDRPHY_BISTFWR1_CASWEBS_MASK (0x2U)
4810 #define DDRPHY_BISTFWR1_CASWEBS_SHIFT (1U)
4811 #define DDRPHY_BISTFWR1_CASWEBS_GET(x) (((uint32_t)(x) & DDRPHY_BISTFWR1_CASWEBS_MASK) >> DDRPHY_BISTFWR1_CASWEBS_SHIFT)
4812 
4813 /*
4814  * RASWEBS (R)
4815  *
4816  * Bit status during a word error for the RAS.
4817  */
4818 #define DDRPHY_BISTFWR1_RASWEBS_MASK (0x1U)
4819 #define DDRPHY_BISTFWR1_RASWEBS_SHIFT (0U)
4820 #define DDRPHY_BISTFWR1_RASWEBS_GET(x) (((uint32_t)(x) & DDRPHY_BISTFWR1_RASWEBS_MASK) >> DDRPHY_BISTFWR1_RASWEBS_SHIFT)
4821 
4822 /* Bitfield definition for register: BISTFWR2 */
4823 /*
4824  * DQWEBS (R)
4825  *
4826  * Bit status during a word error for each of the 8 data (DQ) bits. The first 8 bits indicate the status of the first data beat (i.e. the status of the data driven out on DQ[7:0] on the rising edge of DQS). The second 8 bits indicate the status of the second data beat (i.e. the status of the data driven out on DQ[7:0] on the falling edge of DQS), and so on. For each of the 8-bit group, the first bit is for DQ[0], the second bit is for DQ[1], and so on.
4827  */
4828 #define DDRPHY_BISTFWR2_DQWEBS_MASK (0xFFFFFFFFUL)
4829 #define DDRPHY_BISTFWR2_DQWEBS_SHIFT (0U)
4830 #define DDRPHY_BISTFWR2_DQWEBS_GET(x) (((uint32_t)(x) & DDRPHY_BISTFWR2_DQWEBS_MASK) >> DDRPHY_BISTFWR2_DQWEBS_SHIFT)
4831 
4832 /* Bitfield definition for register: AACR */
4833 /*
4834  * AAOENC (R/W)
4835  *
4836  * Anti-Aging PAD Output Enable Control: Enables, if set, anti-aging toggling on the pad output enable signal “ctl_oe_n” going into the DATX8s. This will increase power consumption for the anti-aging feature.
4837  */
4838 #define DDRPHY_AACR_AAOENC_MASK (0x80000000UL)
4839 #define DDRPHY_AACR_AAOENC_SHIFT (31U)
4840 #define DDRPHY_AACR_AAOENC_SET(x) (((uint32_t)(x) << DDRPHY_AACR_AAOENC_SHIFT) & DDRPHY_AACR_AAOENC_MASK)
4841 #define DDRPHY_AACR_AAOENC_GET(x) (((uint32_t)(x) & DDRPHY_AACR_AAOENC_MASK) >> DDRPHY_AACR_AAOENC_SHIFT)
4842 
4843 /*
4844  * AAENC (R/W)
4845  *
4846  * Anti-Aging Enable Control: Enables, if set, the automatic toggling of the data going to the DATX8 when the data channel from the controller/PUB to DATX8 is idle for programmable number of clock cycles.
4847  */
4848 #define DDRPHY_AACR_AAENC_MASK (0x40000000UL)
4849 #define DDRPHY_AACR_AAENC_SHIFT (30U)
4850 #define DDRPHY_AACR_AAENC_SET(x) (((uint32_t)(x) << DDRPHY_AACR_AAENC_SHIFT) & DDRPHY_AACR_AAENC_MASK)
4851 #define DDRPHY_AACR_AAENC_GET(x) (((uint32_t)(x) & DDRPHY_AACR_AAENC_MASK) >> DDRPHY_AACR_AAENC_SHIFT)
4852 
4853 /*
4854  * AATR (R/W)
4855  *
4856  * Anti-Aging Toggle Rate: Defines the number of controller clock (ctl_clk) cycles after which the PUB will toggle the data going to DATX8 if the data channel between the controller/PUB and DATX8 has been idle for this long.
4857  * The default value correspond to a toggling count of 4096 ctl_clk cycles. For a ctl_clk running at 533MHz the toggle rate will be approximately 7.68us.
4858  * The default value may also be overridden by the macro DWC_AACR_AATR_DFLT.
4859  */
4860 #define DDRPHY_AACR_AATR_MASK (0x3FFFFFFFUL)
4861 #define DDRPHY_AACR_AATR_SHIFT (0U)
4862 #define DDRPHY_AACR_AATR_SET(x) (((uint32_t)(x) << DDRPHY_AACR_AATR_SHIFT) & DDRPHY_AACR_AATR_MASK)
4863 #define DDRPHY_AACR_AATR_GET(x) (((uint32_t)(x) & DDRPHY_AACR_AATR_MASK) >> DDRPHY_AACR_AATR_SHIFT)
4864 
4865 /* Bitfield definition for register: GPR0 */
4866 /*
4867  * GPR0 (R/W)
4868  *
4869  * General Purpose Register 0: General purpose register bits.
4870  */
4871 #define DDRPHY_GPR0_GPR0_MASK (0xFFFFFFFFUL)
4872 #define DDRPHY_GPR0_GPR0_SHIFT (0U)
4873 #define DDRPHY_GPR0_GPR0_SET(x) (((uint32_t)(x) << DDRPHY_GPR0_GPR0_SHIFT) & DDRPHY_GPR0_GPR0_MASK)
4874 #define DDRPHY_GPR0_GPR0_GET(x) (((uint32_t)(x) & DDRPHY_GPR0_GPR0_MASK) >> DDRPHY_GPR0_GPR0_SHIFT)
4875 
4876 /* Bitfield definition for register: GPR1 */
4877 /*
4878  * GPR1 (R/W)
4879  *
4880  * General Purpose Register 1: General purpose register bits.
4881  */
4882 #define DDRPHY_GPR1_GPR1_MASK (0xFFFFFFFFUL)
4883 #define DDRPHY_GPR1_GPR1_SHIFT (0U)
4884 #define DDRPHY_GPR1_GPR1_SET(x) (((uint32_t)(x) << DDRPHY_GPR1_GPR1_SHIFT) & DDRPHY_GPR1_GPR1_MASK)
4885 #define DDRPHY_GPR1_GPR1_GET(x) (((uint32_t)(x) & DDRPHY_GPR1_GPR1_MASK) >> DDRPHY_GPR1_GPR1_SHIFT)
4886 
4887 /* Bitfield definition for register of struct array ZQ: CR0 */
4888 /*
4889  * ZQPD (R/W)
4890  *
4891  * ZQ Power Down: Powers down, if set, the PZQ cell.
4892  */
4893 #define DDRPHY_ZQ_CR0_ZQPD_MASK (0x80000000UL)
4894 #define DDRPHY_ZQ_CR0_ZQPD_SHIFT (31U)
4895 #define DDRPHY_ZQ_CR0_ZQPD_SET(x) (((uint32_t)(x) << DDRPHY_ZQ_CR0_ZQPD_SHIFT) & DDRPHY_ZQ_CR0_ZQPD_MASK)
4896 #define DDRPHY_ZQ_CR0_ZQPD_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_CR0_ZQPD_MASK) >> DDRPHY_ZQ_CR0_ZQPD_SHIFT)
4897 
4898 /*
4899  * ZCALEN (R/W)
4900  *
4901  * Impedance Calibration Enable: Enables, if set, the impedance calibration of this ZQ control block when impedance calibration is triggered using either the ZCAL bit of PIR register or the DFI update interface.
4902  */
4903 #define DDRPHY_ZQ_CR0_ZCALEN_MASK (0x40000000UL)
4904 #define DDRPHY_ZQ_CR0_ZCALEN_SHIFT (30U)
4905 #define DDRPHY_ZQ_CR0_ZCALEN_SET(x) (((uint32_t)(x) << DDRPHY_ZQ_CR0_ZCALEN_SHIFT) & DDRPHY_ZQ_CR0_ZCALEN_MASK)
4906 #define DDRPHY_ZQ_CR0_ZCALEN_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_CR0_ZCALEN_MASK) >> DDRPHY_ZQ_CR0_ZCALEN_SHIFT)
4907 
4908 /*
4909  * ZCALBYP (R/W)
4910  *
4911  * Impedance Calibration Bypass: Bypasses, if set, impedance calibration of this ZQ control block when impedance calibration is already in progress. Impedance calibration can be disabled prior to trigger by using the ZCALEN bit.
4912  */
4913 #define DDRPHY_ZQ_CR0_ZCALBYP_MASK (0x20000000UL)
4914 #define DDRPHY_ZQ_CR0_ZCALBYP_SHIFT (29U)
4915 #define DDRPHY_ZQ_CR0_ZCALBYP_SET(x) (((uint32_t)(x) << DDRPHY_ZQ_CR0_ZCALBYP_SHIFT) & DDRPHY_ZQ_CR0_ZCALBYP_MASK)
4916 #define DDRPHY_ZQ_CR0_ZCALBYP_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_CR0_ZCALBYP_MASK) >> DDRPHY_ZQ_CR0_ZCALBYP_SHIFT)
4917 
4918 /*
4919  * ZDEN (R/W)
4920  *
4921  * Impedance Over-ride Enable: When this bit is set, it allows users to directly drive the impedance control using the data programmed in the ZDATA field. Otherwise, the control is generated automatically by the impedance control logic.
4922  */
4923 #define DDRPHY_ZQ_CR0_ZDEN_MASK (0x10000000UL)
4924 #define DDRPHY_ZQ_CR0_ZDEN_SHIFT (28U)
4925 #define DDRPHY_ZQ_CR0_ZDEN_SET(x) (((uint32_t)(x) << DDRPHY_ZQ_CR0_ZDEN_SHIFT) & DDRPHY_ZQ_CR0_ZDEN_MASK)
4926 #define DDRPHY_ZQ_CR0_ZDEN_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_CR0_ZDEN_MASK) >> DDRPHY_ZQ_CR0_ZDEN_SHIFT)
4927 
4928 /*
4929  * ZDATA (R/W)
4930  *
4931  * Impedance Over-Ride Data: Data used to directly drive the impedance control.
4932  * ZDATA field mapping for D3F I/Os is as follows:
4933  * ZDATA[27:21] is used to select the pull-up on-die termination impedance ZDATA[20:14] is used to select the pull-down on-die termination impedance ZDATA[13:7] is used to select the pull-up output impedance
4934  * ZDATA[6:0] is used to select the pull-down output impedance
4935  * ZDATA field mapping for D3A/B/R I/Os is as follows: ZDATA[27:20] is reserved and returns zeros on reads
4936  * ZDATA[19:15] is used to select the pull-up on-die termination impedance ZDATA[14:10] is used to select the pull-down on-die termination impedance ZDATA[9:5] is used to select the pull-up output impedance
4937  * ZDATA[4:0] is used to select the pull-down output impedance
4938  * The default value is 0x000014A for I/O type D3C/R and 0x0001830 for I/O type D3F.
4939  */
4940 #define DDRPHY_ZQ_CR0_ZDATA_MASK (0xFFFFFFFUL)
4941 #define DDRPHY_ZQ_CR0_ZDATA_SHIFT (0U)
4942 #define DDRPHY_ZQ_CR0_ZDATA_SET(x) (((uint32_t)(x) << DDRPHY_ZQ_CR0_ZDATA_SHIFT) & DDRPHY_ZQ_CR0_ZDATA_MASK)
4943 #define DDRPHY_ZQ_CR0_ZDATA_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_CR0_ZDATA_MASK) >> DDRPHY_ZQ_CR0_ZDATA_SHIFT)
4944 
4945 /* Bitfield definition for register of struct array ZQ: CR1 */
4946 /*
4947  * DFIPU1 (R/W)
4948  *
4949  * DFI Update Interface 1: Sets this impedance controller to be enabled for calibration when the DFI PHY update interface 1 (channel 1) requests an update. Only valid in shared-AC mode.
4950  */
4951 #define DDRPHY_ZQ_CR1_DFIPU1_MASK (0x20000UL)
4952 #define DDRPHY_ZQ_CR1_DFIPU1_SHIFT (17U)
4953 #define DDRPHY_ZQ_CR1_DFIPU1_SET(x) (((uint32_t)(x) << DDRPHY_ZQ_CR1_DFIPU1_SHIFT) & DDRPHY_ZQ_CR1_DFIPU1_MASK)
4954 #define DDRPHY_ZQ_CR1_DFIPU1_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_CR1_DFIPU1_MASK) >> DDRPHY_ZQ_CR1_DFIPU1_SHIFT)
4955 
4956 /*
4957  * DFIPU0 (R/W)
4958  *
4959  * DFI Update Interface 0: Sets this impedance controller to be enabled for calibration when the DFI PHY update interface 0 (channel 0) requests an update.
4960  */
4961 #define DDRPHY_ZQ_CR1_DFIPU0_MASK (0x10000UL)
4962 #define DDRPHY_ZQ_CR1_DFIPU0_SHIFT (16U)
4963 #define DDRPHY_ZQ_CR1_DFIPU0_SET(x) (((uint32_t)(x) << DDRPHY_ZQ_CR1_DFIPU0_SHIFT) & DDRPHY_ZQ_CR1_DFIPU0_MASK)
4964 #define DDRPHY_ZQ_CR1_DFIPU0_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_CR1_DFIPU0_MASK) >> DDRPHY_ZQ_CR1_DFIPU0_SHIFT)
4965 
4966 /*
4967  * DFICCU (R/W)
4968  *
4969  * DFI Concurrent Controller Update Interface: Sets this impedance controller to be enabled for calibration when both of the DFI controller update interfaces request an update on the same clock. This provides the ability to enable impedance calibration updates for the Address/Command lane. Only valid in shared-AC mode.
4970  */
4971 #define DDRPHY_ZQ_CR1_DFICCU_MASK (0x4000U)
4972 #define DDRPHY_ZQ_CR1_DFICCU_SHIFT (14U)
4973 #define DDRPHY_ZQ_CR1_DFICCU_SET(x) (((uint32_t)(x) << DDRPHY_ZQ_CR1_DFICCU_SHIFT) & DDRPHY_ZQ_CR1_DFICCU_MASK)
4974 #define DDRPHY_ZQ_CR1_DFICCU_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_CR1_DFICCU_MASK) >> DDRPHY_ZQ_CR1_DFICCU_SHIFT)
4975 
4976 /*
4977  * DFICU1 (R/W)
4978  *
4979  * DFI Controller Update Interface 1: Sets this impedance controller to be enabled for calibration when the DFI controller update interface 1 (channel 1) requests an update. Only valid in shared-AC mode.
4980  */
4981 #define DDRPHY_ZQ_CR1_DFICU1_MASK (0x2000U)
4982 #define DDRPHY_ZQ_CR1_DFICU1_SHIFT (13U)
4983 #define DDRPHY_ZQ_CR1_DFICU1_SET(x) (((uint32_t)(x) << DDRPHY_ZQ_CR1_DFICU1_SHIFT) & DDRPHY_ZQ_CR1_DFICU1_MASK)
4984 #define DDRPHY_ZQ_CR1_DFICU1_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_CR1_DFICU1_MASK) >> DDRPHY_ZQ_CR1_DFICU1_SHIFT)
4985 
4986 /*
4987  * DFICU0 (R/W)
4988  *
4989  * DFI Controller Update Interface 0: Sets this impedance controller to be enabled for calibration when the DFI controller update interface 0 (channel 0) requests an update.
4990  */
4991 #define DDRPHY_ZQ_CR1_DFICU0_MASK (0x1000U)
4992 #define DDRPHY_ZQ_CR1_DFICU0_SHIFT (12U)
4993 #define DDRPHY_ZQ_CR1_DFICU0_SET(x) (((uint32_t)(x) << DDRPHY_ZQ_CR1_DFICU0_SHIFT) & DDRPHY_ZQ_CR1_DFICU0_MASK)
4994 #define DDRPHY_ZQ_CR1_DFICU0_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_CR1_DFICU0_MASK) >> DDRPHY_ZQ_CR1_DFICU0_SHIFT)
4995 
4996 /*
4997  * ZPROG (R/W)
4998  *
4999  * Impedance Divide Ratio: Selects the external resistor divide ratio to be used to set the output impedance and the on-die termination as follows:
5000  * ZPROG[7:4] = On-die termination divide select ZPROG[3:0] = Output impedance divide select
5001  */
5002 #define DDRPHY_ZQ_CR1_ZPROG_MASK (0xFFU)
5003 #define DDRPHY_ZQ_CR1_ZPROG_SHIFT (0U)
5004 #define DDRPHY_ZQ_CR1_ZPROG_SET(x) (((uint32_t)(x) << DDRPHY_ZQ_CR1_ZPROG_SHIFT) & DDRPHY_ZQ_CR1_ZPROG_MASK)
5005 #define DDRPHY_ZQ_CR1_ZPROG_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_CR1_ZPROG_MASK) >> DDRPHY_ZQ_CR1_ZPROG_SHIFT)
5006 
5007 /* Bitfield definition for register of struct array ZQ: SR0 */
5008 /*
5009  * ZDONE (R)
5010  *
5011  * Impedance Calibration Done: Indicates that impedance calibration has completed.
5012  */
5013 #define DDRPHY_ZQ_SR0_ZDONE_MASK (0x80000000UL)
5014 #define DDRPHY_ZQ_SR0_ZDONE_SHIFT (31U)
5015 #define DDRPHY_ZQ_SR0_ZDONE_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_SR0_ZDONE_MASK) >> DDRPHY_ZQ_SR0_ZDONE_SHIFT)
5016 
5017 /*
5018  * ZERR (R)
5019  *
5020  * Impedance Calibration Error: If set, indicates that there was an error during impedance calibration.
5021  */
5022 #define DDRPHY_ZQ_SR0_ZERR_MASK (0x40000000UL)
5023 #define DDRPHY_ZQ_SR0_ZERR_SHIFT (30U)
5024 #define DDRPHY_ZQ_SR0_ZERR_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_SR0_ZERR_MASK) >> DDRPHY_ZQ_SR0_ZERR_SHIFT)
5025 
5026 /*
5027  * ZCTRL (R)
5028  *
5029  * Impedance Control: Current value of impedance control. ZCTRL field mapping for D3F I/Os is as follows:
5030  * ZCTRL[27:21] is used to select the pull-up on-die termination impedance ZCTRL[20:14] is used to select the pull-down on-die termination impedance ZCTRL[13:7] is used to select the pull-up output impedance
5031  * ZCTRL[6:0] is used to select the pull-down output impedance
5032  * ZCTRL field mapping for D3A/B/R I/Os is as follows: ZCTRL[27:20] is reserved and returns zeros on reads
5033  * ZCTRL[19:15] is used to select the pull-up on-die termination impedance ZCTRL[14:10] is used to select the pull-down on-die termination impedance ZCTRL[9:5] is used to select the pull-up output impedance
5034  * ZCTRL[4:0] is used to select the pull-down output impedance
5035  * Note: The default value is 0x000014A for I/O type D3C/D3R and 0x0001839 for I/O type D3F.
5036  */
5037 #define DDRPHY_ZQ_SR0_ZCTRL_MASK (0xFFFFFFFUL)
5038 #define DDRPHY_ZQ_SR0_ZCTRL_SHIFT (0U)
5039 #define DDRPHY_ZQ_SR0_ZCTRL_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_SR0_ZCTRL_MASK) >> DDRPHY_ZQ_SR0_ZCTRL_SHIFT)
5040 
5041 /* Bitfield definition for register of struct array ZQ: SR1 */
5042 /*
5043  * OPU (R)
5044  *
5045  * On-die termination (ODT) pull-up calibration status. Similar status encodings as ZPD.
5046  */
5047 #define DDRPHY_ZQ_SR1_OPU_MASK (0xC0U)
5048 #define DDRPHY_ZQ_SR1_OPU_SHIFT (6U)
5049 #define DDRPHY_ZQ_SR1_OPU_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_SR1_OPU_MASK) >> DDRPHY_ZQ_SR1_OPU_SHIFT)
5050 
5051 /*
5052  * OPD (R)
5053  *
5054  * On-die termination (ODT) pull-down calibration status. Similar status encodings as ZPD.
5055  */
5056 #define DDRPHY_ZQ_SR1_OPD_MASK (0x30U)
5057 #define DDRPHY_ZQ_SR1_OPD_SHIFT (4U)
5058 #define DDRPHY_ZQ_SR1_OPD_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_SR1_OPD_MASK) >> DDRPHY_ZQ_SR1_OPD_SHIFT)
5059 
5060 /*
5061  * ZPU (R)
5062  *
5063  * Output impedance pull-up calibration status. Similar status encodings as ZPD.
5064  */
5065 #define DDRPHY_ZQ_SR1_ZPU_MASK (0xCU)
5066 #define DDRPHY_ZQ_SR1_ZPU_SHIFT (2U)
5067 #define DDRPHY_ZQ_SR1_ZPU_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_SR1_ZPU_MASK) >> DDRPHY_ZQ_SR1_ZPU_SHIFT)
5068 
5069 /*
5070  * ZPD (R)
5071  *
5072  * Output impedance pull-down calibration status. Valid status encodings are: 00 = Completed with no errors
5073  * 01 = Overflow error 10 = Underflow error
5074  * 11 = Calibration in progress
5075  */
5076 #define DDRPHY_ZQ_SR1_ZPD_MASK (0x3U)
5077 #define DDRPHY_ZQ_SR1_ZPD_SHIFT (0U)
5078 #define DDRPHY_ZQ_SR1_ZPD_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_SR1_ZPD_MASK) >> DDRPHY_ZQ_SR1_ZPD_SHIFT)
5079 
5080 /* Bitfield definition for register of struct array DX: GCR */
5081 /*
5082  * CALBYP (R/W)
5083  *
5084  * Calibration Bypass: Prevents, if set, period measurement calibration from automatically triggering after PHY initialization.
5085  */
5086 #define DDRPHY_DX_GCR_CALBYP_MASK (0x80000000UL)
5087 #define DDRPHY_DX_GCR_CALBYP_SHIFT (31U)
5088 #define DDRPHY_DX_GCR_CALBYP_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_CALBYP_SHIFT) & DDRPHY_DX_GCR_CALBYP_MASK)
5089 #define DDRPHY_DX_GCR_CALBYP_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_CALBYP_MASK) >> DDRPHY_DX_GCR_CALBYP_SHIFT)
5090 
5091 /*
5092  * MDLEN (R/W)
5093  *
5094  * Master Delay Line Enable: Enables, if set, the DATX8 master delay line calibration to perform subsequent period measurements following the initial period measurements that are performed after reset or when calibration is manually triggered. These additional measurements are accumulated and filtered as long as this bit remains high. This bit is ANDed with the common DATX8 MDL enable bit.
5095  */
5096 #define DDRPHY_DX_GCR_MDLEN_MASK (0x40000000UL)
5097 #define DDRPHY_DX_GCR_MDLEN_SHIFT (30U)
5098 #define DDRPHY_DX_GCR_MDLEN_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_MDLEN_SHIFT) & DDRPHY_DX_GCR_MDLEN_MASK)
5099 #define DDRPHY_DX_GCR_MDLEN_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_MDLEN_MASK) >> DDRPHY_DX_GCR_MDLEN_SHIFT)
5100 
5101 /*
5102  * WLRKEN (R/W)
5103  *
5104  * Write Level Rank Enable: Specifies the ranks that should be write leveled for this byte. Write leveling responses from ranks that are not enabled for write leveling for a particular byte are ignored and write leveling is flagged as done for these ranks.
5105  * WLRKEN[0] enables rank 0, [1] enables rank 1, [2] enables rank 2, and [3] enables
5106  * rank 3.
5107  */
5108 #define DDRPHY_DX_GCR_WLRKEN_MASK (0x3C000000UL)
5109 #define DDRPHY_DX_GCR_WLRKEN_SHIFT (26U)
5110 #define DDRPHY_DX_GCR_WLRKEN_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_WLRKEN_SHIFT) & DDRPHY_DX_GCR_WLRKEN_MASK)
5111 #define DDRPHY_DX_GCR_WLRKEN_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_WLRKEN_MASK) >> DDRPHY_DX_GCR_WLRKEN_SHIFT)
5112 
5113 /*
5114  * PLLBYP (R/W)
5115  *
5116  * PLL Bypass: Puts the byte PLL in bypass mode by driving the PLL bypass pin. This bit is not self-clearing and a '0' must be written to de-assert the bypass. This bit is ORed with the global BYP configuration bit (see Table 3-10 on page 91).
5117  */
5118 #define DDRPHY_DX_GCR_PLLBYP_MASK (0x80000UL)
5119 #define DDRPHY_DX_GCR_PLLBYP_SHIFT (19U)
5120 #define DDRPHY_DX_GCR_PLLBYP_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_PLLBYP_SHIFT) & DDRPHY_DX_GCR_PLLBYP_MASK)
5121 #define DDRPHY_DX_GCR_PLLBYP_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_PLLBYP_MASK) >> DDRPHY_DX_GCR_PLLBYP_SHIFT)
5122 
5123 /*
5124  * GSHIFT (R/W)
5125  *
5126  * Gear Shift: Enables, if set, rapid locking mode on the byte PLL. This bit is ORed with the global GSHIFT configuration bit (see Table 3-10 on page 91).
5127  */
5128 #define DDRPHY_DX_GCR_GSHIFT_MASK (0x40000UL)
5129 #define DDRPHY_DX_GCR_GSHIFT_SHIFT (18U)
5130 #define DDRPHY_DX_GCR_GSHIFT_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_GSHIFT_SHIFT) & DDRPHY_DX_GCR_GSHIFT_MASK)
5131 #define DDRPHY_DX_GCR_GSHIFT_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_GSHIFT_MASK) >> DDRPHY_DX_GCR_GSHIFT_SHIFT)
5132 
5133 /*
5134  * PLLPD (R/W)
5135  *
5136  * PLL Power Down: Puts the byte PLL in power down mode by driving the PLL power down pin. This bit is not self-clearing and a '0' must be written to de-assert the power-down. This bit is ORed with the global PLLPD configuration bit (see
5137  * Table 3-10 on page 91).
5138  */
5139 #define DDRPHY_DX_GCR_PLLPD_MASK (0x20000UL)
5140 #define DDRPHY_DX_GCR_PLLPD_SHIFT (17U)
5141 #define DDRPHY_DX_GCR_PLLPD_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_PLLPD_SHIFT) & DDRPHY_DX_GCR_PLLPD_MASK)
5142 #define DDRPHY_DX_GCR_PLLPD_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_PLLPD_MASK) >> DDRPHY_DX_GCR_PLLPD_SHIFT)
5143 
5144 /*
5145  * PLLRST (R/W)
5146  *
5147  * PLL Rest: Resets the byte PLL by driving the PLL reset pin. This bit is not self- clearing and a '0' must be written to de-assert the reset. This bit is ORed with the global PLLRST configuration bit (see Table 3-10 on page 91).
5148  */
5149 #define DDRPHY_DX_GCR_PLLRST_MASK (0x10000UL)
5150 #define DDRPHY_DX_GCR_PLLRST_SHIFT (16U)
5151 #define DDRPHY_DX_GCR_PLLRST_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_PLLRST_SHIFT) & DDRPHY_DX_GCR_PLLRST_MASK)
5152 #define DDRPHY_DX_GCR_PLLRST_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_PLLRST_MASK) >> DDRPHY_DX_GCR_PLLRST_SHIFT)
5153 
5154 /*
5155  * DXOEO (R/W)
5156  *
5157  * Data Byte Output Enable Override: Specifies whether the output I/O output enable for the byte lane should be set to a fixed value. Valid values are:
5158  * 00 = No override. Output enable is controlled by DFI transactions 01 = output enable is asserted (I/O is forced to output mode).
5159  * 10 = Output enable is de-asserted (I/O is forced to input mode) 11 = Reserved
5160  */
5161 #define DDRPHY_DX_GCR_DXOEO_MASK (0xC000U)
5162 #define DDRPHY_DX_GCR_DXOEO_SHIFT (14U)
5163 #define DDRPHY_DX_GCR_DXOEO_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_DXOEO_SHIFT) & DDRPHY_DX_GCR_DXOEO_MASK)
5164 #define DDRPHY_DX_GCR_DXOEO_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_DXOEO_MASK) >> DDRPHY_DX_GCR_DXOEO_SHIFT)
5165 
5166 /*
5167  * RTTOAL (R/W)
5168  *
5169  * RTT On Additive Latency: Indicates when the ODT control of DQ/DQS SSTL I/Os is set to the value in DQODT/DQSODT during read cycles. Valid values are:
5170  * 0 = ODT control is set to DQSODT/DQODT almost two cycles before read data preamble
5171  * 1 = ODT control is set to DQSODT/DQODT almost one cycle before read data preamble
5172  */
5173 #define DDRPHY_DX_GCR_RTTOAL_MASK (0x2000U)
5174 #define DDRPHY_DX_GCR_RTTOAL_SHIFT (13U)
5175 #define DDRPHY_DX_GCR_RTTOAL_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_RTTOAL_SHIFT) & DDRPHY_DX_GCR_RTTOAL_MASK)
5176 #define DDRPHY_DX_GCR_RTTOAL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_RTTOAL_MASK) >> DDRPHY_DX_GCR_RTTOAL_SHIFT)
5177 
5178 /*
5179  * RTTOH (R/W)
5180  *
5181  * RTT Output Hold: Indicates the number of clock cycles (from 0 to 3) after the read data postamble for which ODT control should remain set to DQSODT for DQS or DQODT for DQ/DM before disabling it (setting it to ‘0’) when using dynamic ODT control. ODT is disabled almost RTTOH clock cycles after the read postamble.
5182  */
5183 #define DDRPHY_DX_GCR_RTTOH_MASK (0x1800U)
5184 #define DDRPHY_DX_GCR_RTTOH_SHIFT (11U)
5185 #define DDRPHY_DX_GCR_RTTOH_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_RTTOH_SHIFT) & DDRPHY_DX_GCR_RTTOH_MASK)
5186 #define DDRPHY_DX_GCR_RTTOH_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_RTTOH_MASK) >> DDRPHY_DX_GCR_RTTOH_SHIFT)
5187 
5188 /*
5189  * DQRTT (R/W)
5190  *
5191  * DQ Dynamic RTT Control: If set, the on die termination (ODT) control of the DQ/DM SSTL I/O is dynamically generated to enable the ODT during read operation and disabled otherwise. By setting this bit to '0' the dynamic ODT feature is disabled. To control ODT statically this bit must be set to '0' and DXnGCR0[2] (DQODT) is used to enable ODT (when set to '1') or disable ODT(when set to '0').
5192  */
5193 #define DDRPHY_DX_GCR_DQRTT_MASK (0x400U)
5194 #define DDRPHY_DX_GCR_DQRTT_SHIFT (10U)
5195 #define DDRPHY_DX_GCR_DQRTT_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_DQRTT_SHIFT) & DDRPHY_DX_GCR_DQRTT_MASK)
5196 #define DDRPHY_DX_GCR_DQRTT_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_DQRTT_MASK) >> DDRPHY_DX_GCR_DQRTT_SHIFT)
5197 
5198 /*
5199  * DQSRTT (R/W)
5200  *
5201  * DQS Dynamic RTT Control: If set, the on die termination (ODT) control of the DQS/DQS# SSTL I/O is dynamically generated to enable the ODT during read operation and disabled otherwise. By setting this bit to '0' the dynamic ODT feature is disabled. To control ODT statically this bit must be set to '0' and DXnGCR0[1] (DQSODT) is used to enable ODT (when set to '1') or disable ODT(when set to '0').
5202  */
5203 #define DDRPHY_DX_GCR_DQSRTT_MASK (0x200U)
5204 #define DDRPHY_DX_GCR_DQSRTT_SHIFT (9U)
5205 #define DDRPHY_DX_GCR_DQSRTT_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_DQSRTT_SHIFT) & DDRPHY_DX_GCR_DQSRTT_MASK)
5206 #define DDRPHY_DX_GCR_DQSRTT_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_DQSRTT_MASK) >> DDRPHY_DX_GCR_DQSRTT_SHIFT)
5207 
5208 /*
5209  * DSEN (R/W)
5210  *
5211  * Write DQS Enable: Controls whether the write DQS going to the SDRAM is enabled (toggling) or disabled (static value) and whether the DQS is inverted. DQS# is always the inversion of DQS. These values are valid only when DQS/DQS# output enable is on, otherwise the DQS/DQS# is tristated. Valid settings are:
5212  * 00 = Reserved
5213  * 01 = DQS toggling with normal polarity (This should be the default setting) 10 = Reserved
5214  * 11 = Reserved
5215  */
5216 #define DDRPHY_DX_GCR_DSEN_MASK (0x180U)
5217 #define DDRPHY_DX_GCR_DSEN_SHIFT (7U)
5218 #define DDRPHY_DX_GCR_DSEN_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_DSEN_SHIFT) & DDRPHY_DX_GCR_DSEN_MASK)
5219 #define DDRPHY_DX_GCR_DSEN_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_DSEN_MASK) >> DDRPHY_DX_GCR_DSEN_SHIFT)
5220 
5221 /*
5222  * DQSRPD (R/W)
5223  *
5224  * DQSR Power Down: Powers down, if set, the PDQSR cell. This bit is ORed with the common PDR configuration bit (see “DATX8 Common Configuration Register (DXCCR)” on page 99)
5225  */
5226 #define DDRPHY_DX_GCR_DQSRPD_MASK (0x40U)
5227 #define DDRPHY_DX_GCR_DQSRPD_SHIFT (6U)
5228 #define DDRPHY_DX_GCR_DQSRPD_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_DQSRPD_SHIFT) & DDRPHY_DX_GCR_DQSRPD_MASK)
5229 #define DDRPHY_DX_GCR_DQSRPD_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_DQSRPD_MASK) >> DDRPHY_DX_GCR_DQSRPD_SHIFT)
5230 
5231 /*
5232  * DXPDR (R/W)
5233  *
5234  * Data Power Down Receiver: Powers down, when set, the input receiver on I/O for DQ, DM, and DQS/DQS# pins of the byte. This bit is ORed with the common PDR configuration bit (see “DATX8 Common Configuration Register (DXCCR)” on page 99).
5235  */
5236 #define DDRPHY_DX_GCR_DXPDR_MASK (0x20U)
5237 #define DDRPHY_DX_GCR_DXPDR_SHIFT (5U)
5238 #define DDRPHY_DX_GCR_DXPDR_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_DXPDR_SHIFT) & DDRPHY_DX_GCR_DXPDR_MASK)
5239 #define DDRPHY_DX_GCR_DXPDR_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_DXPDR_MASK) >> DDRPHY_DX_GCR_DXPDR_SHIFT)
5240 
5241 /*
5242  * DXPDD1 (R/W)
5243  *
5244  * Data Power Down Driver: Powers down, when set, the output driver on I/O for DQ, DM, and DQS/DQS# pins of the byte. This bit is ORed with the common PDD configuration bit (see “DATX8 Common Configuration Register (DXCCR)” on page 99).
5245  */
5246 #define DDRPHY_DX_GCR_DXPDD1_MASK (0x10U)
5247 #define DDRPHY_DX_GCR_DXPDD1_SHIFT (4U)
5248 #define DDRPHY_DX_GCR_DXPDD1_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_DXPDD1_SHIFT) & DDRPHY_DX_GCR_DXPDD1_MASK)
5249 #define DDRPHY_DX_GCR_DXPDD1_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_DXPDD1_MASK) >> DDRPHY_DX_GCR_DXPDD1_SHIFT)
5250 
5251 /*
5252  * DXIOM (R/W)
5253  *
5254  * Data I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for DQ, DM, and DQS/DQS# pins of the byte. This bit is ORed with the IOM configuration bit of the individual DATX8(see “DATX8 Common Configuration Register (DXCCR)” on page 99).
5255  */
5256 #define DDRPHY_DX_GCR_DXIOM_MASK (0x8U)
5257 #define DDRPHY_DX_GCR_DXIOM_SHIFT (3U)
5258 #define DDRPHY_DX_GCR_DXIOM_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_DXIOM_SHIFT) & DDRPHY_DX_GCR_DXIOM_MASK)
5259 #define DDRPHY_DX_GCR_DXIOM_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_DXIOM_MASK) >> DDRPHY_DX_GCR_DXIOM_SHIFT)
5260 
5261 /*
5262  * DQODT (R/W)
5263  *
5264  * Data On-Die Termination: Enables, when set, the on-die termination on the I/O for DQ and DM pins of the byte. This bit is ORed with the common DATX8 ODT configuration bit (see “DATX8 Common Configuration Register (DXCCR)” on page 99).
5265  * Note: This bit is only valid when DXnGCR0[10] is '0'.
5266  */
5267 #define DDRPHY_DX_GCR_DQODT_MASK (0x4U)
5268 #define DDRPHY_DX_GCR_DQODT_SHIFT (2U)
5269 #define DDRPHY_DX_GCR_DQODT_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_DQODT_SHIFT) & DDRPHY_DX_GCR_DQODT_MASK)
5270 #define DDRPHY_DX_GCR_DQODT_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_DQODT_MASK) >> DDRPHY_DX_GCR_DQODT_SHIFT)
5271 
5272 /*
5273  * DQSODT (R/W)
5274  *
5275  * DQS On-Die Termination: Enables, when set, the on-die termination on the I/O for DQS/DQS# pin of the byte. This bit is ORed with the common DATX8 ODT configuration bit (see “DATX8 Common Configuration Register (DXCCR)” on page 99).
5276  * Note: This bit is only valid when DXnGCR0[9] is '0'.
5277  */
5278 #define DDRPHY_DX_GCR_DQSODT_MASK (0x2U)
5279 #define DDRPHY_DX_GCR_DQSODT_SHIFT (1U)
5280 #define DDRPHY_DX_GCR_DQSODT_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_DQSODT_SHIFT) & DDRPHY_DX_GCR_DQSODT_MASK)
5281 #define DDRPHY_DX_GCR_DQSODT_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_DQSODT_MASK) >> DDRPHY_DX_GCR_DQSODT_SHIFT)
5282 
5283 /*
5284  * DXEN (R/W)
5285  *
5286  * Data Byte Enable: Enables, if set, the data byte. Setting this bit to '0' disables the byte, i.e. the byte is not used in PHY initialization or training and is ignored during SDRAM read/write operations.
5287  */
5288 #define DDRPHY_DX_GCR_DXEN_MASK (0x1U)
5289 #define DDRPHY_DX_GCR_DXEN_SHIFT (0U)
5290 #define DDRPHY_DX_GCR_DXEN_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_DXEN_SHIFT) & DDRPHY_DX_GCR_DXEN_MASK)
5291 #define DDRPHY_DX_GCR_DXEN_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_DXEN_MASK) >> DDRPHY_DX_GCR_DXEN_SHIFT)
5292 
5293 /* Bitfield definition for register of struct array DX: GSR0 */
5294 /*
5295  * WLDQ (R)
5296  *
5297  * Write Leveling DQ Status: Captures the write leveling DQ status from the DRAM during software write leveling.
5298  */
5299 #define DDRPHY_DX_GSR0_WLDQ_MASK (0x10000000UL)
5300 #define DDRPHY_DX_GSR0_WLDQ_SHIFT (28U)
5301 #define DDRPHY_DX_GSR0_WLDQ_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR0_WLDQ_MASK) >> DDRPHY_DX_GSR0_WLDQ_SHIFT)
5302 
5303 /*
5304  * QSGERR (R)
5305  *
5306  * DQS Gate Training Error: Indicates, if set, that there is an error in DQS gate training. One bit for each of the up to 4 ranks.
5307  */
5308 #define DDRPHY_DX_GSR0_QSGERR_MASK (0xF000000UL)
5309 #define DDRPHY_DX_GSR0_QSGERR_SHIFT (24U)
5310 #define DDRPHY_DX_GSR0_QSGERR_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR0_QSGERR_MASK) >> DDRPHY_DX_GSR0_QSGERR_SHIFT)
5311 
5312 /*
5313  * GDQSPRD (R)
5314  *
5315  * Read DQS gating Period: Returns the DDR clock period measured by the read DQS gating LCDL during calibration. This value is PVT compensated.
5316  */
5317 #define DDRPHY_DX_GSR0_GDQSPRD_MASK (0xFF0000UL)
5318 #define DDRPHY_DX_GSR0_GDQSPRD_SHIFT (16U)
5319 #define DDRPHY_DX_GSR0_GDQSPRD_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR0_GDQSPRD_MASK) >> DDRPHY_DX_GSR0_GDQSPRD_SHIFT)
5320 
5321 /*
5322  * DPLOCK (R)
5323  *
5324  * DATX8 PLL Lock: Indicates, if set, that the DATX8 PLL has locked. This is a direct status of the DATX8 PLL lock pin.
5325  */
5326 #define DDRPHY_DX_GSR0_DPLOCK_MASK (0x8000U)
5327 #define DDRPHY_DX_GSR0_DPLOCK_SHIFT (15U)
5328 #define DDRPHY_DX_GSR0_DPLOCK_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR0_DPLOCK_MASK) >> DDRPHY_DX_GSR0_DPLOCK_SHIFT)
5329 
5330 /*
5331  * WLPRD (R)
5332  *
5333  * Write Leveling Period: Returns the DDR clock period measured by the write leveling LCDL during calibration. The measured period is used to generate the control of the write leveling pipeline which is a function of the write-leveling delay and the clock period. This value is PVT compensated.
5334  */
5335 #define DDRPHY_DX_GSR0_WLPRD_MASK (0x7F80U)
5336 #define DDRPHY_DX_GSR0_WLPRD_SHIFT (7U)
5337 #define DDRPHY_DX_GSR0_WLPRD_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR0_WLPRD_MASK) >> DDRPHY_DX_GSR0_WLPRD_SHIFT)
5338 
5339 /*
5340  * WLERR (R)
5341  *
5342  * Write Leveling Error: Indicates, if set, that there is a write leveling error in the DATX8.
5343  */
5344 #define DDRPHY_DX_GSR0_WLERR_MASK (0x40U)
5345 #define DDRPHY_DX_GSR0_WLERR_SHIFT (6U)
5346 #define DDRPHY_DX_GSR0_WLERR_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR0_WLERR_MASK) >> DDRPHY_DX_GSR0_WLERR_SHIFT)
5347 
5348 /*
5349  * WLDONE (R)
5350  *
5351  * Write Leveling Done: Indicates, if set, that the DATX8 has completed write leveling.
5352  */
5353 #define DDRPHY_DX_GSR0_WLDONE_MASK (0x20U)
5354 #define DDRPHY_DX_GSR0_WLDONE_SHIFT (5U)
5355 #define DDRPHY_DX_GSR0_WLDONE_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR0_WLDONE_MASK) >> DDRPHY_DX_GSR0_WLDONE_SHIFT)
5356 
5357 /*
5358  * WLCAL (R)
5359  *
5360  * Write Leveling Calibration: Indicates, if set, that the DATX8 has finished doing period measurement calibration for the write leveling slave delay line.
5361  */
5362 #define DDRPHY_DX_GSR0_WLCAL_MASK (0x10U)
5363 #define DDRPHY_DX_GSR0_WLCAL_SHIFT (4U)
5364 #define DDRPHY_DX_GSR0_WLCAL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR0_WLCAL_MASK) >> DDRPHY_DX_GSR0_WLCAL_SHIFT)
5365 
5366 /*
5367  * GDQSCAL (R)
5368  *
5369  * Read DQS gating Calibration: Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS gating LCDL.
5370  */
5371 #define DDRPHY_DX_GSR0_GDQSCAL_MASK (0x8U)
5372 #define DDRPHY_DX_GSR0_GDQSCAL_SHIFT (3U)
5373 #define DDRPHY_DX_GSR0_GDQSCAL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR0_GDQSCAL_MASK) >> DDRPHY_DX_GSR0_GDQSCAL_SHIFT)
5374 
5375 /*
5376  * RDQSNCAL (R)
5377  *
5378  * Read DQS# Calibration (Type B/B1 PHY Only): Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS# LCDL.
5379  */
5380 #define DDRPHY_DX_GSR0_RDQSNCAL_MASK (0x4U)
5381 #define DDRPHY_DX_GSR0_RDQSNCAL_SHIFT (2U)
5382 #define DDRPHY_DX_GSR0_RDQSNCAL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR0_RDQSNCAL_MASK) >> DDRPHY_DX_GSR0_RDQSNCAL_SHIFT)
5383 
5384 /*
5385  * RDQSCAL (R)
5386  *
5387  * Read DQS Calibration: Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS LCDL.
5388  */
5389 #define DDRPHY_DX_GSR0_RDQSCAL_MASK (0x2U)
5390 #define DDRPHY_DX_GSR0_RDQSCAL_SHIFT (1U)
5391 #define DDRPHY_DX_GSR0_RDQSCAL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR0_RDQSCAL_MASK) >> DDRPHY_DX_GSR0_RDQSCAL_SHIFT)
5392 
5393 /*
5394  * WDQCAL (R)
5395  *
5396  * Write DQ Calibration: Indicates, if set, that the DATX8 has finished doing period measurement calibration for the write DQ LCDL.
5397  */
5398 #define DDRPHY_DX_GSR0_WDQCAL_MASK (0x1U)
5399 #define DDRPHY_DX_GSR0_WDQCAL_SHIFT (0U)
5400 #define DDRPHY_DX_GSR0_WDQCAL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR0_WDQCAL_MASK) >> DDRPHY_DX_GSR0_WDQCAL_SHIFT)
5401 
5402 /* Bitfield definition for register of struct array DX: GSR1 */
5403 /*
5404  * DLTCODE (R)
5405  *
5406  * Delay Line Test Code: Returns the code measured by the PHY control block that corresponds to the period of the DATX8 delay line digital test output.
5407  */
5408 #define DDRPHY_DX_GSR1_DLTCODE_MASK (0x1FFFFFEUL)
5409 #define DDRPHY_DX_GSR1_DLTCODE_SHIFT (1U)
5410 #define DDRPHY_DX_GSR1_DLTCODE_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR1_DLTCODE_MASK) >> DDRPHY_DX_GSR1_DLTCODE_SHIFT)
5411 
5412 /*
5413  * DLTDONE (R)
5414  *
5415  * Delay Line Test Done: Indicates, if set, that the PHY control block has finished doing period measurement of the DATX8 delay line digital test output.
5416  */
5417 #define DDRPHY_DX_GSR1_DLTDONE_MASK (0x1U)
5418 #define DDRPHY_DX_GSR1_DLTDONE_SHIFT (0U)
5419 #define DDRPHY_DX_GSR1_DLTDONE_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR1_DLTDONE_MASK) >> DDRPHY_DX_GSR1_DLTDONE_SHIFT)
5420 
5421 /* Bitfield definition for register of struct array DX: BDLR0 */
5422 /*
5423  * DQ4WBD (R/W)
5424  *
5425  * DQ4 Write Bit Delay: Delay select for the BDL on DQ4 write path.
5426  */
5427 #define DDRPHY_DX_BDLR0_DQ4WBD_MASK (0x3F000000UL)
5428 #define DDRPHY_DX_BDLR0_DQ4WBD_SHIFT (24U)
5429 #define DDRPHY_DX_BDLR0_DQ4WBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR0_DQ4WBD_SHIFT) & DDRPHY_DX_BDLR0_DQ4WBD_MASK)
5430 #define DDRPHY_DX_BDLR0_DQ4WBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR0_DQ4WBD_MASK) >> DDRPHY_DX_BDLR0_DQ4WBD_SHIFT)
5431 
5432 /*
5433  * DQ3WBD (R/W)
5434  *
5435  * DQ3 Write Bit Delay: Delay select for the BDL on DQ3 write path
5436  */
5437 #define DDRPHY_DX_BDLR0_DQ3WBD_MASK (0xFC0000UL)
5438 #define DDRPHY_DX_BDLR0_DQ3WBD_SHIFT (18U)
5439 #define DDRPHY_DX_BDLR0_DQ3WBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR0_DQ3WBD_SHIFT) & DDRPHY_DX_BDLR0_DQ3WBD_MASK)
5440 #define DDRPHY_DX_BDLR0_DQ3WBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR0_DQ3WBD_MASK) >> DDRPHY_DX_BDLR0_DQ3WBD_SHIFT)
5441 
5442 /*
5443  * DQ2WBD (R/W)
5444  *
5445  * DQ2 Write Bit Delay: Delay select for the BDL on DQ2 write path.
5446  */
5447 #define DDRPHY_DX_BDLR0_DQ2WBD_MASK (0x3F000UL)
5448 #define DDRPHY_DX_BDLR0_DQ2WBD_SHIFT (12U)
5449 #define DDRPHY_DX_BDLR0_DQ2WBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR0_DQ2WBD_SHIFT) & DDRPHY_DX_BDLR0_DQ2WBD_MASK)
5450 #define DDRPHY_DX_BDLR0_DQ2WBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR0_DQ2WBD_MASK) >> DDRPHY_DX_BDLR0_DQ2WBD_SHIFT)
5451 
5452 /*
5453  * DQ1WBD (R/W)
5454  *
5455  * DQ1 Write Bit Delay: Delay select for the BDL on DQ1 write path.
5456  */
5457 #define DDRPHY_DX_BDLR0_DQ1WBD_MASK (0xFC0U)
5458 #define DDRPHY_DX_BDLR0_DQ1WBD_SHIFT (6U)
5459 #define DDRPHY_DX_BDLR0_DQ1WBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR0_DQ1WBD_SHIFT) & DDRPHY_DX_BDLR0_DQ1WBD_MASK)
5460 #define DDRPHY_DX_BDLR0_DQ1WBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR0_DQ1WBD_MASK) >> DDRPHY_DX_BDLR0_DQ1WBD_SHIFT)
5461 
5462 /*
5463  * DQ0WBD (R/W)
5464  *
5465  * DQ0 Write Bit Delay: Delay select for the BDL on DQ0 write path.
5466  */
5467 #define DDRPHY_DX_BDLR0_DQ0WBD_MASK (0x3FU)
5468 #define DDRPHY_DX_BDLR0_DQ0WBD_SHIFT (0U)
5469 #define DDRPHY_DX_BDLR0_DQ0WBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR0_DQ0WBD_SHIFT) & DDRPHY_DX_BDLR0_DQ0WBD_MASK)
5470 #define DDRPHY_DX_BDLR0_DQ0WBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR0_DQ0WBD_MASK) >> DDRPHY_DX_BDLR0_DQ0WBD_SHIFT)
5471 
5472 /* Bitfield definition for register of struct array DX: BDLR1 */
5473 /*
5474  * DSWBD (R/W)
5475  *
5476  * DQS Write Bit Delay: Delay select for the BDL on DQS write path
5477  */
5478 #define DDRPHY_DX_BDLR1_DSWBD_MASK (0x3F000000UL)
5479 #define DDRPHY_DX_BDLR1_DSWBD_SHIFT (24U)
5480 #define DDRPHY_DX_BDLR1_DSWBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR1_DSWBD_SHIFT) & DDRPHY_DX_BDLR1_DSWBD_MASK)
5481 #define DDRPHY_DX_BDLR1_DSWBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR1_DSWBD_MASK) >> DDRPHY_DX_BDLR1_DSWBD_SHIFT)
5482 
5483 /*
5484  * DMWBD (R/W)
5485  *
5486  * DM Write Bit Delay: Delay select for the BDL on DM write path.
5487  */
5488 #define DDRPHY_DX_BDLR1_DMWBD_MASK (0xFC0000UL)
5489 #define DDRPHY_DX_BDLR1_DMWBD_SHIFT (18U)
5490 #define DDRPHY_DX_BDLR1_DMWBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR1_DMWBD_SHIFT) & DDRPHY_DX_BDLR1_DMWBD_MASK)
5491 #define DDRPHY_DX_BDLR1_DMWBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR1_DMWBD_MASK) >> DDRPHY_DX_BDLR1_DMWBD_SHIFT)
5492 
5493 /*
5494  * DQ7WBD (R/W)
5495  *
5496  * DQ7 Write Bit Delay: Delay select for the BDL on DQ7 write path.
5497  */
5498 #define DDRPHY_DX_BDLR1_DQ7WBD_MASK (0x3F000UL)
5499 #define DDRPHY_DX_BDLR1_DQ7WBD_SHIFT (12U)
5500 #define DDRPHY_DX_BDLR1_DQ7WBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR1_DQ7WBD_SHIFT) & DDRPHY_DX_BDLR1_DQ7WBD_MASK)
5501 #define DDRPHY_DX_BDLR1_DQ7WBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR1_DQ7WBD_MASK) >> DDRPHY_DX_BDLR1_DQ7WBD_SHIFT)
5502 
5503 /*
5504  * DQ6WBD (R/W)
5505  *
5506  * DQ6 Write Bit Delay: Delay select for the BDL on DQ6 write path.
5507  */
5508 #define DDRPHY_DX_BDLR1_DQ6WBD_MASK (0xFC0U)
5509 #define DDRPHY_DX_BDLR1_DQ6WBD_SHIFT (6U)
5510 #define DDRPHY_DX_BDLR1_DQ6WBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR1_DQ6WBD_SHIFT) & DDRPHY_DX_BDLR1_DQ6WBD_MASK)
5511 #define DDRPHY_DX_BDLR1_DQ6WBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR1_DQ6WBD_MASK) >> DDRPHY_DX_BDLR1_DQ6WBD_SHIFT)
5512 
5513 /*
5514  * DQ5WBD (R/W)
5515  *
5516  * DQ5 Write Bit Delay: Delay select for the BDL on DQ5 write path.
5517  */
5518 #define DDRPHY_DX_BDLR1_DQ5WBD_MASK (0x3FU)
5519 #define DDRPHY_DX_BDLR1_DQ5WBD_SHIFT (0U)
5520 #define DDRPHY_DX_BDLR1_DQ5WBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR1_DQ5WBD_SHIFT) & DDRPHY_DX_BDLR1_DQ5WBD_MASK)
5521 #define DDRPHY_DX_BDLR1_DQ5WBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR1_DQ5WBD_MASK) >> DDRPHY_DX_BDLR1_DQ5WBD_SHIFT)
5522 
5523 /* Bitfield definition for register of struct array DX: BDLR2 */
5524 /*
5525  * DSNRBD (R/W)
5526  *
5527  * DQSN Read Bit Delay (Type B/B1 PHY Only): Delay select for the BDL on DQSN read path
5528  */
5529 #define DDRPHY_DX_BDLR2_DSNRBD_MASK (0xFC0000UL)
5530 #define DDRPHY_DX_BDLR2_DSNRBD_SHIFT (18U)
5531 #define DDRPHY_DX_BDLR2_DSNRBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR2_DSNRBD_SHIFT) & DDRPHY_DX_BDLR2_DSNRBD_MASK)
5532 #define DDRPHY_DX_BDLR2_DSNRBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR2_DSNRBD_MASK) >> DDRPHY_DX_BDLR2_DSNRBD_SHIFT)
5533 
5534 /*
5535  * DSRBD (R/W)
5536  *
5537  * DQS Read Bit Delay: Delay select for the BDL on DQS read path
5538  */
5539 #define DDRPHY_DX_BDLR2_DSRBD_MASK (0x3F000UL)
5540 #define DDRPHY_DX_BDLR2_DSRBD_SHIFT (12U)
5541 #define DDRPHY_DX_BDLR2_DSRBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR2_DSRBD_SHIFT) & DDRPHY_DX_BDLR2_DSRBD_MASK)
5542 #define DDRPHY_DX_BDLR2_DSRBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR2_DSRBD_MASK) >> DDRPHY_DX_BDLR2_DSRBD_SHIFT)
5543 
5544 /*
5545  * DQOEBD (R/W)
5546  *
5547  * DQ Output Enable Bit Delay: Delay select for the BDL on DQ/DM output enable path.
5548  */
5549 #define DDRPHY_DX_BDLR2_DQOEBD_MASK (0xFC0U)
5550 #define DDRPHY_DX_BDLR2_DQOEBD_SHIFT (6U)
5551 #define DDRPHY_DX_BDLR2_DQOEBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR2_DQOEBD_SHIFT) & DDRPHY_DX_BDLR2_DQOEBD_MASK)
5552 #define DDRPHY_DX_BDLR2_DQOEBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR2_DQOEBD_MASK) >> DDRPHY_DX_BDLR2_DQOEBD_SHIFT)
5553 
5554 /*
5555  * DSOEBD (R/W)
5556  *
5557  * DQS Output Enable Bit Delay: Delay select for the BDL on DQS output enable path
5558  */
5559 #define DDRPHY_DX_BDLR2_DSOEBD_MASK (0x3FU)
5560 #define DDRPHY_DX_BDLR2_DSOEBD_SHIFT (0U)
5561 #define DDRPHY_DX_BDLR2_DSOEBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR2_DSOEBD_SHIFT) & DDRPHY_DX_BDLR2_DSOEBD_MASK)
5562 #define DDRPHY_DX_BDLR2_DSOEBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR2_DSOEBD_MASK) >> DDRPHY_DX_BDLR2_DSOEBD_SHIFT)
5563 
5564 /* Bitfield definition for register of struct array DX: BDLR3 */
5565 /*
5566  * DQ4RBD (R/W)
5567  *
5568  * DQ4 Read Bit Delay: Delay select for the BDL on DQ4 read path.
5569  */
5570 #define DDRPHY_DX_BDLR3_DQ4RBD_MASK (0x3F000000UL)
5571 #define DDRPHY_DX_BDLR3_DQ4RBD_SHIFT (24U)
5572 #define DDRPHY_DX_BDLR3_DQ4RBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR3_DQ4RBD_SHIFT) & DDRPHY_DX_BDLR3_DQ4RBD_MASK)
5573 #define DDRPHY_DX_BDLR3_DQ4RBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR3_DQ4RBD_MASK) >> DDRPHY_DX_BDLR3_DQ4RBD_SHIFT)
5574 
5575 /*
5576  * DQ3RBD (R/W)
5577  *
5578  * DQ3 Read Bit Delay: Delay select for the BDL on DQ3 read path
5579  */
5580 #define DDRPHY_DX_BDLR3_DQ3RBD_MASK (0xFC0000UL)
5581 #define DDRPHY_DX_BDLR3_DQ3RBD_SHIFT (18U)
5582 #define DDRPHY_DX_BDLR3_DQ3RBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR3_DQ3RBD_SHIFT) & DDRPHY_DX_BDLR3_DQ3RBD_MASK)
5583 #define DDRPHY_DX_BDLR3_DQ3RBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR3_DQ3RBD_MASK) >> DDRPHY_DX_BDLR3_DQ3RBD_SHIFT)
5584 
5585 /*
5586  * DQ2RBD (R/W)
5587  *
5588  * DQ2 Read Bit Delay: Delay select for the BDL on DQ2 read path.
5589  */
5590 #define DDRPHY_DX_BDLR3_DQ2RBD_MASK (0x3F000UL)
5591 #define DDRPHY_DX_BDLR3_DQ2RBD_SHIFT (12U)
5592 #define DDRPHY_DX_BDLR3_DQ2RBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR3_DQ2RBD_SHIFT) & DDRPHY_DX_BDLR3_DQ2RBD_MASK)
5593 #define DDRPHY_DX_BDLR3_DQ2RBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR3_DQ2RBD_MASK) >> DDRPHY_DX_BDLR3_DQ2RBD_SHIFT)
5594 
5595 /*
5596  * DQ1RBD (R/W)
5597  *
5598  * DQ1 Read Bit Delay: Delay select for the BDL on DQ1 read path.
5599  */
5600 #define DDRPHY_DX_BDLR3_DQ1RBD_MASK (0xFC0U)
5601 #define DDRPHY_DX_BDLR3_DQ1RBD_SHIFT (6U)
5602 #define DDRPHY_DX_BDLR3_DQ1RBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR3_DQ1RBD_SHIFT) & DDRPHY_DX_BDLR3_DQ1RBD_MASK)
5603 #define DDRPHY_DX_BDLR3_DQ1RBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR3_DQ1RBD_MASK) >> DDRPHY_DX_BDLR3_DQ1RBD_SHIFT)
5604 
5605 /*
5606  * DQ0RBD (R/W)
5607  *
5608  * DQ0 Read Bit Delay: Delay select for the BDL on DQ0 read path.
5609  */
5610 #define DDRPHY_DX_BDLR3_DQ0RBD_MASK (0x3FU)
5611 #define DDRPHY_DX_BDLR3_DQ0RBD_SHIFT (0U)
5612 #define DDRPHY_DX_BDLR3_DQ0RBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR3_DQ0RBD_SHIFT) & DDRPHY_DX_BDLR3_DQ0RBD_MASK)
5613 #define DDRPHY_DX_BDLR3_DQ0RBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR3_DQ0RBD_MASK) >> DDRPHY_DX_BDLR3_DQ0RBD_SHIFT)
5614 
5615 /* Bitfield definition for register of struct array DX: BDLR4 */
5616 /*
5617  * DMRBD (R/W)
5618  *
5619  * DM Read Bit Delay: Delay select for the BDL on DM read path.
5620  */
5621 #define DDRPHY_DX_BDLR4_DMRBD_MASK (0xFC0000UL)
5622 #define DDRPHY_DX_BDLR4_DMRBD_SHIFT (18U)
5623 #define DDRPHY_DX_BDLR4_DMRBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR4_DMRBD_SHIFT) & DDRPHY_DX_BDLR4_DMRBD_MASK)
5624 #define DDRPHY_DX_BDLR4_DMRBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR4_DMRBD_MASK) >> DDRPHY_DX_BDLR4_DMRBD_SHIFT)
5625 
5626 /*
5627  * DQ7RBD (R/W)
5628  *
5629  * DQ7 Read Bit Delay: Delay select for the BDL on DQ7 read path.
5630  */
5631 #define DDRPHY_DX_BDLR4_DQ7RBD_MASK (0x3F000UL)
5632 #define DDRPHY_DX_BDLR4_DQ7RBD_SHIFT (12U)
5633 #define DDRPHY_DX_BDLR4_DQ7RBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR4_DQ7RBD_SHIFT) & DDRPHY_DX_BDLR4_DQ7RBD_MASK)
5634 #define DDRPHY_DX_BDLR4_DQ7RBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR4_DQ7RBD_MASK) >> DDRPHY_DX_BDLR4_DQ7RBD_SHIFT)
5635 
5636 /*
5637  * DQ6RBD (R/W)
5638  *
5639  * DQ6 Read Bit Delay: Delay select for the BDL on DQ6 read path.
5640  */
5641 #define DDRPHY_DX_BDLR4_DQ6RBD_MASK (0xFC0U)
5642 #define DDRPHY_DX_BDLR4_DQ6RBD_SHIFT (6U)
5643 #define DDRPHY_DX_BDLR4_DQ6RBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR4_DQ6RBD_SHIFT) & DDRPHY_DX_BDLR4_DQ6RBD_MASK)
5644 #define DDRPHY_DX_BDLR4_DQ6RBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR4_DQ6RBD_MASK) >> DDRPHY_DX_BDLR4_DQ6RBD_SHIFT)
5645 
5646 /*
5647  * DQ5RBD (R/W)
5648  *
5649  * DQ5 Read Bit Delay: Delay select for the BDL on DQ5 read path.
5650  */
5651 #define DDRPHY_DX_BDLR4_DQ5RBD_MASK (0x3FU)
5652 #define DDRPHY_DX_BDLR4_DQ5RBD_SHIFT (0U)
5653 #define DDRPHY_DX_BDLR4_DQ5RBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR4_DQ5RBD_SHIFT) & DDRPHY_DX_BDLR4_DQ5RBD_MASK)
5654 #define DDRPHY_DX_BDLR4_DQ5RBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR4_DQ5RBD_MASK) >> DDRPHY_DX_BDLR4_DQ5RBD_SHIFT)
5655 
5656 /* Bitfield definition for register of struct array DX: LCDLR0 */
5657 /*
5658  * R3WLD (R/W)
5659  *
5660  * Rank 3 Write Leveling Delay: Rank 3 delay select for the write leveling (WL) LCDL
5661  */
5662 #define DDRPHY_DX_LCDLR0_R3WLD_MASK (0xFF000000UL)
5663 #define DDRPHY_DX_LCDLR0_R3WLD_SHIFT (24U)
5664 #define DDRPHY_DX_LCDLR0_R3WLD_SET(x) (((uint32_t)(x) << DDRPHY_DX_LCDLR0_R3WLD_SHIFT) & DDRPHY_DX_LCDLR0_R3WLD_MASK)
5665 #define DDRPHY_DX_LCDLR0_R3WLD_GET(x) (((uint32_t)(x) & DDRPHY_DX_LCDLR0_R3WLD_MASK) >> DDRPHY_DX_LCDLR0_R3WLD_SHIFT)
5666 
5667 /*
5668  * R2WLD (R/W)
5669  *
5670  * Rank 2 Write Leveling Delay: Rank 2 delay select for the write leveling (WL) LCDL
5671  */
5672 #define DDRPHY_DX_LCDLR0_R2WLD_MASK (0xFF0000UL)
5673 #define DDRPHY_DX_LCDLR0_R2WLD_SHIFT (16U)
5674 #define DDRPHY_DX_LCDLR0_R2WLD_SET(x) (((uint32_t)(x) << DDRPHY_DX_LCDLR0_R2WLD_SHIFT) & DDRPHY_DX_LCDLR0_R2WLD_MASK)
5675 #define DDRPHY_DX_LCDLR0_R2WLD_GET(x) (((uint32_t)(x) & DDRPHY_DX_LCDLR0_R2WLD_MASK) >> DDRPHY_DX_LCDLR0_R2WLD_SHIFT)
5676 
5677 /*
5678  * R1WLD (R/W)
5679  *
5680  * Rank 1 Write Leveling Delay: Rank 1 delay select for the write leveling (WL) LCDL
5681  */
5682 #define DDRPHY_DX_LCDLR0_R1WLD_MASK (0xFF00U)
5683 #define DDRPHY_DX_LCDLR0_R1WLD_SHIFT (8U)
5684 #define DDRPHY_DX_LCDLR0_R1WLD_SET(x) (((uint32_t)(x) << DDRPHY_DX_LCDLR0_R1WLD_SHIFT) & DDRPHY_DX_LCDLR0_R1WLD_MASK)
5685 #define DDRPHY_DX_LCDLR0_R1WLD_GET(x) (((uint32_t)(x) & DDRPHY_DX_LCDLR0_R1WLD_MASK) >> DDRPHY_DX_LCDLR0_R1WLD_SHIFT)
5686 
5687 /*
5688  * R0WLD (R/W)
5689  *
5690  * Rank 0 Write Leveling Delay: Rank 0 delay select for the write leveling (WL) LCDL
5691  */
5692 #define DDRPHY_DX_LCDLR0_R0WLD_MASK (0xFFU)
5693 #define DDRPHY_DX_LCDLR0_R0WLD_SHIFT (0U)
5694 #define DDRPHY_DX_LCDLR0_R0WLD_SET(x) (((uint32_t)(x) << DDRPHY_DX_LCDLR0_R0WLD_SHIFT) & DDRPHY_DX_LCDLR0_R0WLD_MASK)
5695 #define DDRPHY_DX_LCDLR0_R0WLD_GET(x) (((uint32_t)(x) & DDRPHY_DX_LCDLR0_R0WLD_MASK) >> DDRPHY_DX_LCDLR0_R0WLD_SHIFT)
5696 
5697 /* Bitfield definition for register of struct array DX: LCDLR1 */
5698 /*
5699  * RDQSND (R/W)
5700  *
5701  * Read DQSN Delay (Type B/B1 PHY Only): Delay select for the read DQSN (RDQS) LCDL
5702  */
5703 #define DDRPHY_DX_LCDLR1_RDQSND_MASK (0xFF0000UL)
5704 #define DDRPHY_DX_LCDLR1_RDQSND_SHIFT (16U)
5705 #define DDRPHY_DX_LCDLR1_RDQSND_SET(x) (((uint32_t)(x) << DDRPHY_DX_LCDLR1_RDQSND_SHIFT) & DDRPHY_DX_LCDLR1_RDQSND_MASK)
5706 #define DDRPHY_DX_LCDLR1_RDQSND_GET(x) (((uint32_t)(x) & DDRPHY_DX_LCDLR1_RDQSND_MASK) >> DDRPHY_DX_LCDLR1_RDQSND_SHIFT)
5707 
5708 /*
5709  * RDQSD (R/W)
5710  *
5711  * Read DQS Delay: Delay select for the read DQS (RDQS) LCDL
5712  */
5713 #define DDRPHY_DX_LCDLR1_RDQSD_MASK (0xFF00U)
5714 #define DDRPHY_DX_LCDLR1_RDQSD_SHIFT (8U)
5715 #define DDRPHY_DX_LCDLR1_RDQSD_SET(x) (((uint32_t)(x) << DDRPHY_DX_LCDLR1_RDQSD_SHIFT) & DDRPHY_DX_LCDLR1_RDQSD_MASK)
5716 #define DDRPHY_DX_LCDLR1_RDQSD_GET(x) (((uint32_t)(x) & DDRPHY_DX_LCDLR1_RDQSD_MASK) >> DDRPHY_DX_LCDLR1_RDQSD_SHIFT)
5717 
5718 /*
5719  * WDQD (R/W)
5720  *
5721  * Write Data Delay: Delay select for the write data (WDQ) LCDL
5722  */
5723 #define DDRPHY_DX_LCDLR1_WDQD_MASK (0xFFU)
5724 #define DDRPHY_DX_LCDLR1_WDQD_SHIFT (0U)
5725 #define DDRPHY_DX_LCDLR1_WDQD_SET(x) (((uint32_t)(x) << DDRPHY_DX_LCDLR1_WDQD_SHIFT) & DDRPHY_DX_LCDLR1_WDQD_MASK)
5726 #define DDRPHY_DX_LCDLR1_WDQD_GET(x) (((uint32_t)(x) & DDRPHY_DX_LCDLR1_WDQD_MASK) >> DDRPHY_DX_LCDLR1_WDQD_SHIFT)
5727 
5728 /* Bitfield definition for register of struct array DX: LCDLR2 */
5729 /*
5730  * R3DQSGD (R/W)
5731  *
5732  * Rank 3 Read DQS Gating Delay: Rank 3 delay select for the read DQS gating (DQSG) LCDL
5733  */
5734 #define DDRPHY_DX_LCDLR2_R3DQSGD_MASK (0xFF000000UL)
5735 #define DDRPHY_DX_LCDLR2_R3DQSGD_SHIFT (24U)
5736 #define DDRPHY_DX_LCDLR2_R3DQSGD_SET(x) (((uint32_t)(x) << DDRPHY_DX_LCDLR2_R3DQSGD_SHIFT) & DDRPHY_DX_LCDLR2_R3DQSGD_MASK)
5737 #define DDRPHY_DX_LCDLR2_R3DQSGD_GET(x) (((uint32_t)(x) & DDRPHY_DX_LCDLR2_R3DQSGD_MASK) >> DDRPHY_DX_LCDLR2_R3DQSGD_SHIFT)
5738 
5739 /*
5740  * R2DQSGD (R/W)
5741  *
5742  * Rank 2 Read DQS Gating Delay: Rank 2 delay select for the read DQS gating (DQSG) LCDL
5743  */
5744 #define DDRPHY_DX_LCDLR2_R2DQSGD_MASK (0xFF0000UL)
5745 #define DDRPHY_DX_LCDLR2_R2DQSGD_SHIFT (16U)
5746 #define DDRPHY_DX_LCDLR2_R2DQSGD_SET(x) (((uint32_t)(x) << DDRPHY_DX_LCDLR2_R2DQSGD_SHIFT) & DDRPHY_DX_LCDLR2_R2DQSGD_MASK)
5747 #define DDRPHY_DX_LCDLR2_R2DQSGD_GET(x) (((uint32_t)(x) & DDRPHY_DX_LCDLR2_R2DQSGD_MASK) >> DDRPHY_DX_LCDLR2_R2DQSGD_SHIFT)
5748 
5749 /*
5750  * R1DQSGD (R/W)
5751  *
5752  * Rank 1 Read DQS Gating Delay: Rank 1 delay select for the read DQS gating (DQSG) LCDL
5753  */
5754 #define DDRPHY_DX_LCDLR2_R1DQSGD_MASK (0xFF00U)
5755 #define DDRPHY_DX_LCDLR2_R1DQSGD_SHIFT (8U)
5756 #define DDRPHY_DX_LCDLR2_R1DQSGD_SET(x) (((uint32_t)(x) << DDRPHY_DX_LCDLR2_R1DQSGD_SHIFT) & DDRPHY_DX_LCDLR2_R1DQSGD_MASK)
5757 #define DDRPHY_DX_LCDLR2_R1DQSGD_GET(x) (((uint32_t)(x) & DDRPHY_DX_LCDLR2_R1DQSGD_MASK) >> DDRPHY_DX_LCDLR2_R1DQSGD_SHIFT)
5758 
5759 /*
5760  * R0DQSGD (R/W)
5761  *
5762  * Rank 0 Read DQS Gating Delay: Rank 0 delay select for the read DQS gating (DQSG) LCDL
5763  */
5764 #define DDRPHY_DX_LCDLR2_R0DQSGD_MASK (0xFFU)
5765 #define DDRPHY_DX_LCDLR2_R0DQSGD_SHIFT (0U)
5766 #define DDRPHY_DX_LCDLR2_R0DQSGD_SET(x) (((uint32_t)(x) << DDRPHY_DX_LCDLR2_R0DQSGD_SHIFT) & DDRPHY_DX_LCDLR2_R0DQSGD_MASK)
5767 #define DDRPHY_DX_LCDLR2_R0DQSGD_GET(x) (((uint32_t)(x) & DDRPHY_DX_LCDLR2_R0DQSGD_MASK) >> DDRPHY_DX_LCDLR2_R0DQSGD_SHIFT)
5768 
5769 /* Bitfield definition for register of struct array DX: MDLR */
5770 /*
5771  * MDLD (R/W)
5772  *
5773  * MDL Delay: Delay select for the LCDL for the Master Delay Line.
5774  */
5775 #define DDRPHY_DX_MDLR_MDLD_MASK (0xFF0000UL)
5776 #define DDRPHY_DX_MDLR_MDLD_SHIFT (16U)
5777 #define DDRPHY_DX_MDLR_MDLD_SET(x) (((uint32_t)(x) << DDRPHY_DX_MDLR_MDLD_SHIFT) & DDRPHY_DX_MDLR_MDLD_MASK)
5778 #define DDRPHY_DX_MDLR_MDLD_GET(x) (((uint32_t)(x) & DDRPHY_DX_MDLR_MDLD_MASK) >> DDRPHY_DX_MDLR_MDLD_SHIFT)
5779 
5780 /*
5781  * TPRD (R/W)
5782  *
5783  * Target Period: Target period measured by the master delay line calibration for VT drift compensation. This is the current measured value of the period and is continuously updated if the MDL is enabled to do so.
5784  */
5785 #define DDRPHY_DX_MDLR_TPRD_MASK (0xFF00U)
5786 #define DDRPHY_DX_MDLR_TPRD_SHIFT (8U)
5787 #define DDRPHY_DX_MDLR_TPRD_SET(x) (((uint32_t)(x) << DDRPHY_DX_MDLR_TPRD_SHIFT) & DDRPHY_DX_MDLR_TPRD_MASK)
5788 #define DDRPHY_DX_MDLR_TPRD_GET(x) (((uint32_t)(x) & DDRPHY_DX_MDLR_TPRD_MASK) >> DDRPHY_DX_MDLR_TPRD_SHIFT)
5789 
5790 /*
5791  * IPRD (R/W)
5792  *
5793  * Initial Period: Initial period measured by the master delay line calibration for VT drift compensation. This value is used as the denominator when calculating the ratios of updates during VT compensation.
5794  */
5795 #define DDRPHY_DX_MDLR_IPRD_MASK (0xFFU)
5796 #define DDRPHY_DX_MDLR_IPRD_SHIFT (0U)
5797 #define DDRPHY_DX_MDLR_IPRD_SET(x) (((uint32_t)(x) << DDRPHY_DX_MDLR_IPRD_SHIFT) & DDRPHY_DX_MDLR_IPRD_MASK)
5798 #define DDRPHY_DX_MDLR_IPRD_GET(x) (((uint32_t)(x) & DDRPHY_DX_MDLR_IPRD_MASK) >> DDRPHY_DX_MDLR_IPRD_SHIFT)
5799 
5800 /* Bitfield definition for register of struct array DX: GTR */
5801 /*
5802  * R3WLSL (R/W)
5803  *
5804  */
5805 #define DDRPHY_DX_GTR_R3WLSL_MASK (0xC0000UL)
5806 #define DDRPHY_DX_GTR_R3WLSL_SHIFT (18U)
5807 #define DDRPHY_DX_GTR_R3WLSL_SET(x) (((uint32_t)(x) << DDRPHY_DX_GTR_R3WLSL_SHIFT) & DDRPHY_DX_GTR_R3WLSL_MASK)
5808 #define DDRPHY_DX_GTR_R3WLSL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GTR_R3WLSL_MASK) >> DDRPHY_DX_GTR_R3WLSL_SHIFT)
5809 
5810 /*
5811  * R2WLSL (R/W)
5812  *
5813  */
5814 #define DDRPHY_DX_GTR_R2WLSL_MASK (0x30000UL)
5815 #define DDRPHY_DX_GTR_R2WLSL_SHIFT (16U)
5816 #define DDRPHY_DX_GTR_R2WLSL_SET(x) (((uint32_t)(x) << DDRPHY_DX_GTR_R2WLSL_SHIFT) & DDRPHY_DX_GTR_R2WLSL_MASK)
5817 #define DDRPHY_DX_GTR_R2WLSL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GTR_R2WLSL_MASK) >> DDRPHY_DX_GTR_R2WLSL_SHIFT)
5818 
5819 /*
5820  * R1WLSL (R/W)
5821  *
5822  */
5823 #define DDRPHY_DX_GTR_R1WLSL_MASK (0xC000U)
5824 #define DDRPHY_DX_GTR_R1WLSL_SHIFT (14U)
5825 #define DDRPHY_DX_GTR_R1WLSL_SET(x) (((uint32_t)(x) << DDRPHY_DX_GTR_R1WLSL_SHIFT) & DDRPHY_DX_GTR_R1WLSL_MASK)
5826 #define DDRPHY_DX_GTR_R1WLSL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GTR_R1WLSL_MASK) >> DDRPHY_DX_GTR_R1WLSL_SHIFT)
5827 
5828 /*
5829  * R0WLSL (R/W)
5830  *
5831  * Rank n Write Leveling System Latency: This is used to adjust the write latency after write leveling. Power-up default is 01 (i.e. no extra clock cycles required). The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register. Every two bits of this register control the latency of each of the (up to) four ranks. R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on. Valid values:
5832  * 00 = Write latency = WL - 1 01 = Write latency = WL
5833  * 10 = Write latency = WL + 1 11 = Reserved
5834  */
5835 #define DDRPHY_DX_GTR_R0WLSL_MASK (0x3000U)
5836 #define DDRPHY_DX_GTR_R0WLSL_SHIFT (12U)
5837 #define DDRPHY_DX_GTR_R0WLSL_SET(x) (((uint32_t)(x) << DDRPHY_DX_GTR_R0WLSL_SHIFT) & DDRPHY_DX_GTR_R0WLSL_MASK)
5838 #define DDRPHY_DX_GTR_R0WLSL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GTR_R0WLSL_MASK) >> DDRPHY_DX_GTR_R0WLSL_SHIFT)
5839 
5840 /*
5841  * R3DGSL (R/W)
5842  *
5843  */
5844 #define DDRPHY_DX_GTR_R3DGSL_MASK (0xE00U)
5845 #define DDRPHY_DX_GTR_R3DGSL_SHIFT (9U)
5846 #define DDRPHY_DX_GTR_R3DGSL_SET(x) (((uint32_t)(x) << DDRPHY_DX_GTR_R3DGSL_SHIFT) & DDRPHY_DX_GTR_R3DGSL_MASK)
5847 #define DDRPHY_DX_GTR_R3DGSL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GTR_R3DGSL_MASK) >> DDRPHY_DX_GTR_R3DGSL_SHIFT)
5848 
5849 /*
5850  * R2DGSL (R/W)
5851  *
5852  */
5853 #define DDRPHY_DX_GTR_R2DGSL_MASK (0x1C0U)
5854 #define DDRPHY_DX_GTR_R2DGSL_SHIFT (6U)
5855 #define DDRPHY_DX_GTR_R2DGSL_SET(x) (((uint32_t)(x) << DDRPHY_DX_GTR_R2DGSL_SHIFT) & DDRPHY_DX_GTR_R2DGSL_MASK)
5856 #define DDRPHY_DX_GTR_R2DGSL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GTR_R2DGSL_MASK) >> DDRPHY_DX_GTR_R2DGSL_SHIFT)
5857 
5858 /*
5859  * R1DGSL (R/W)
5860  *
5861  */
5862 #define DDRPHY_DX_GTR_R1DGSL_MASK (0x38U)
5863 #define DDRPHY_DX_GTR_R1DGSL_SHIFT (3U)
5864 #define DDRPHY_DX_GTR_R1DGSL_SET(x) (((uint32_t)(x) << DDRPHY_DX_GTR_R1DGSL_SHIFT) & DDRPHY_DX_GTR_R1DGSL_MASK)
5865 #define DDRPHY_DX_GTR_R1DGSL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GTR_R1DGSL_MASK) >> DDRPHY_DX_GTR_R1DGSL_SHIFT)
5866 
5867 /*
5868  * R0DGSL (R/W)
5869  *
5870  * Rank n DQS Gating System Latency: This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles.
5871  * This is used to compensate for board delays and other system delays. Power-up default is 000 (i.e. no extra clock cycles required). The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register. Every three bits of this register control the latency of each of the (up to) four ranks. R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on. Valid values are 0 to 7:
5872  */
5873 #define DDRPHY_DX_GTR_R0DGSL_MASK (0x7U)
5874 #define DDRPHY_DX_GTR_R0DGSL_SHIFT (0U)
5875 #define DDRPHY_DX_GTR_R0DGSL_SET(x) (((uint32_t)(x) << DDRPHY_DX_GTR_R0DGSL_SHIFT) & DDRPHY_DX_GTR_R0DGSL_MASK)
5876 #define DDRPHY_DX_GTR_R0DGSL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GTR_R0DGSL_MASK) >> DDRPHY_DX_GTR_R0DGSL_SHIFT)
5877 
5878 /* Bitfield definition for register of struct array DX: GSR2 */
5879 /*
5880  * ESTAT (R/W)
5881  *
5882  * Error Status: If an error occurred for this lane as indicated by RDERR, WDERR, REERR or WEERR the error status code can provide additional information regard when the error occurred during the algorithm execution.
5883  */
5884 #define DDRPHY_DX_GSR2_ESTAT_MASK (0xF00U)
5885 #define DDRPHY_DX_GSR2_ESTAT_SHIFT (8U)
5886 #define DDRPHY_DX_GSR2_ESTAT_SET(x) (((uint32_t)(x) << DDRPHY_DX_GSR2_ESTAT_SHIFT) & DDRPHY_DX_GSR2_ESTAT_MASK)
5887 #define DDRPHY_DX_GSR2_ESTAT_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR2_ESTAT_MASK) >> DDRPHY_DX_GSR2_ESTAT_SHIFT)
5888 
5889 /*
5890  * WEWN (R/W)
5891  *
5892  * Write Data Eye Training Warning: Indicates, if set, that the DATX8 has encountered a warning during execution of the write data eye training.
5893  */
5894 #define DDRPHY_DX_GSR2_WEWN_MASK (0x80U)
5895 #define DDRPHY_DX_GSR2_WEWN_SHIFT (7U)
5896 #define DDRPHY_DX_GSR2_WEWN_SET(x) (((uint32_t)(x) << DDRPHY_DX_GSR2_WEWN_SHIFT) & DDRPHY_DX_GSR2_WEWN_MASK)
5897 #define DDRPHY_DX_GSR2_WEWN_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR2_WEWN_MASK) >> DDRPHY_DX_GSR2_WEWN_SHIFT)
5898 
5899 /*
5900  * WEERR (R/W)
5901  *
5902  * Write Data Eye Training Error: Indicates, if set, that the DATX8 has encountered an error during execution of the write data eye training.
5903  */
5904 #define DDRPHY_DX_GSR2_WEERR_MASK (0x40U)
5905 #define DDRPHY_DX_GSR2_WEERR_SHIFT (6U)
5906 #define DDRPHY_DX_GSR2_WEERR_SET(x) (((uint32_t)(x) << DDRPHY_DX_GSR2_WEERR_SHIFT) & DDRPHY_DX_GSR2_WEERR_MASK)
5907 #define DDRPHY_DX_GSR2_WEERR_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR2_WEERR_MASK) >> DDRPHY_DX_GSR2_WEERR_SHIFT)
5908 
5909 /*
5910  * REWN (R/W)
5911  *
5912  * Read Data Eye Training Warning: Indicates, if set, that the DATX8 has encountered a warning during execution of the read data eye training.
5913  */
5914 #define DDRPHY_DX_GSR2_REWN_MASK (0x20U)
5915 #define DDRPHY_DX_GSR2_REWN_SHIFT (5U)
5916 #define DDRPHY_DX_GSR2_REWN_SET(x) (((uint32_t)(x) << DDRPHY_DX_GSR2_REWN_SHIFT) & DDRPHY_DX_GSR2_REWN_MASK)
5917 #define DDRPHY_DX_GSR2_REWN_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR2_REWN_MASK) >> DDRPHY_DX_GSR2_REWN_SHIFT)
5918 
5919 /*
5920  * REERR (R/W)
5921  *
5922  * Read Data Eye Training Error: Indicates, if set, that the DATX8 has encountered an error during execution of the read data eye training.
5923  */
5924 #define DDRPHY_DX_GSR2_REERR_MASK (0x10U)
5925 #define DDRPHY_DX_GSR2_REERR_SHIFT (4U)
5926 #define DDRPHY_DX_GSR2_REERR_SET(x) (((uint32_t)(x) << DDRPHY_DX_GSR2_REERR_SHIFT) & DDRPHY_DX_GSR2_REERR_MASK)
5927 #define DDRPHY_DX_GSR2_REERR_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR2_REERR_MASK) >> DDRPHY_DX_GSR2_REERR_SHIFT)
5928 
5929 /*
5930  * WDWN (R/W)
5931  *
5932  * Write Bit Deskew Warning: Indicates, if set, that the DATX8 has encountered a warning during execution of the write bit deskew training.
5933  */
5934 #define DDRPHY_DX_GSR2_WDWN_MASK (0x8U)
5935 #define DDRPHY_DX_GSR2_WDWN_SHIFT (3U)
5936 #define DDRPHY_DX_GSR2_WDWN_SET(x) (((uint32_t)(x) << DDRPHY_DX_GSR2_WDWN_SHIFT) & DDRPHY_DX_GSR2_WDWN_MASK)
5937 #define DDRPHY_DX_GSR2_WDWN_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR2_WDWN_MASK) >> DDRPHY_DX_GSR2_WDWN_SHIFT)
5938 
5939 /*
5940  * WDERR (R/W)
5941  *
5942  * Write Bit Deskew Error: Indicates, if set, that the DATX8 has encountered an error during execution of the write bit deskew training.
5943  */
5944 #define DDRPHY_DX_GSR2_WDERR_MASK (0x4U)
5945 #define DDRPHY_DX_GSR2_WDERR_SHIFT (2U)
5946 #define DDRPHY_DX_GSR2_WDERR_SET(x) (((uint32_t)(x) << DDRPHY_DX_GSR2_WDERR_SHIFT) & DDRPHY_DX_GSR2_WDERR_MASK)
5947 #define DDRPHY_DX_GSR2_WDERR_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR2_WDERR_MASK) >> DDRPHY_DX_GSR2_WDERR_SHIFT)
5948 
5949 /*
5950  * RDWN (R/W)
5951  *
5952  * Read Bit Deskew Warning: Indicates, if set, that the DATX8 has encountered a warning during execution of the read bit deskew training.
5953  */
5954 #define DDRPHY_DX_GSR2_RDWN_MASK (0x2U)
5955 #define DDRPHY_DX_GSR2_RDWN_SHIFT (1U)
5956 #define DDRPHY_DX_GSR2_RDWN_SET(x) (((uint32_t)(x) << DDRPHY_DX_GSR2_RDWN_SHIFT) & DDRPHY_DX_GSR2_RDWN_MASK)
5957 #define DDRPHY_DX_GSR2_RDWN_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR2_RDWN_MASK) >> DDRPHY_DX_GSR2_RDWN_SHIFT)
5958 
5959 /*
5960  * RDERR (R/W)
5961  *
5962  * Read Bit Deskew Error: Indicates, if set, that the DATX8 has encountered an error during execution of the read bit deskew training.
5963  */
5964 #define DDRPHY_DX_GSR2_RDERR_MASK (0x1U)
5965 #define DDRPHY_DX_GSR2_RDERR_SHIFT (0U)
5966 #define DDRPHY_DX_GSR2_RDERR_SET(x) (((uint32_t)(x) << DDRPHY_DX_GSR2_RDERR_SHIFT) & DDRPHY_DX_GSR2_RDERR_MASK)
5967 #define DDRPHY_DX_GSR2_RDERR_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR2_RDERR_MASK) >> DDRPHY_DX_GSR2_RDERR_SHIFT)
5968 
5969 
5970 
5971 /* ZQ register group index macro definition */
5972 #define DDRPHY_ZQ_0 (0UL)
5973 #define DDRPHY_ZQ_1 (1UL)
5974 #define DDRPHY_ZQ_2 (2UL)
5975 #define DDRPHY_ZQ_3 (3UL)
5976 
5977 /* DX register group index macro definition */
5978 #define DDRPHY_DX_0 (0UL)
5979 #define DDRPHY_DX_1 (1UL)
5980 #define DDRPHY_DX_2 (2UL)
5981 #define DDRPHY_DX_3 (3UL)
5982 #define DDRPHY_DX_4 (4UL)
5983 #define DDRPHY_DX_5 (5UL)
5984 #define DDRPHY_DX_6 (6UL)
5985 #define DDRPHY_DX_7 (7UL)
5986 #define DDRPHY_DX_8 (8UL)
5987 
5988 
5989 #endif /* HPM_DDRPHY_H */
DDRPHY_Type
Definition: hpm_ddrphy_regs.h:12