hpm_ewdg_drv.h

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/*
 * Copyright (c) 2023-2024 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
 */
 
#ifndef HPM_EWDG_DRV_H
#define HPM_EWDG_DRV_H
 
#include "hpm_common.h"
#include "hpm_ewdg_regs.h"
#include "hpm_soc_feature.h"
 
#ifdef __cplusplus
extern "C" {
#endif
 
enum {
    status_ewdg_tick_out_of_range = MAKE_STATUS(status_group_ewdg, 0),  
    status_ewdg_div_out_of_range = MAKE_STATUS(status_group_ewdg, 1),   
    status_ewdg_feature_unsupported = MAKE_STATUS(status_group_ewdg, 2), 
};
 
#define EWDG_REFRESH_UNLOCK_PASSWORD_DEFAULT (0xED09U)          
#define EWDG_UPDATE_PASSWORD_DEFAULT         (0xECF9U)          
#define EWDG_REFRESH_UNLOCK_FIXED_KEY        (0x55AAU)          
#define EWDG_REFRESH_KEY                     (0x5A45524FUL)     
#define EWDG_EVENT_PARITY_ERROR                 (1UL << 6)    
#define EWDG_EVENT_TIMEOUT_RESET                (1UL << 5)    
#define EWDG_EVENT_TIMEOUT_INTERRUPT            (1UL << 4)    
#define EWDG_EVENT_CFG_REG_UPDATE_UNLOCK_FAIL   (1UL << 3)    
#define EWDG_EVENT_CFG_REG_UPDATE_VIOLATION     (1UL << 2)    
#define EWDG_EVENT_REFRESH_UNLOCK_FAIL          (1UL << 1)    
#define EWDG_EVENT_REFRESH_VIOLATION            (1UL << 0)    
#define EWDG_INT_PARITY_FAIL            (1UL << 2)      
#define EWDG_INT_CTRL_REG_UNLOCK_FAIL   (1UL << 4)      
#define EWDG_INT_CTRL_REG_UPDATE_FAIL   (1UL << 6)      
#define EWDG_INT_TIMEOUT                (1UL << 16)     
#define EWDG_INT_REFRESH_UNLOCK_FAIL    (1UL << 20)     
#define EWDG_INT_REFRESH_VIOLATION      (1UL << 22)     
#define EWDG_INT_ALL    (EWDG_INT_PARITY_FAIL | EWDG_INT_CTRL_REG_UNLOCK_FAIL | EWDG_INT_CTRL_REG_UPDATE_FAIL | \
                         EWDG_INT_TIMEOUT | EWDG_INT_REFRESH_UNLOCK_FAIL | EWDG_INT_REFRESH_VIOLATION)
#define EWDG_RST_PARITY_FAIL            (1UL << 3)      
#define EWDG_RST_CTRL_REG_UNLOCK_FAIL   (1UL << 5)      
#define EWDG_RST_CTRL_REG_UPDATE_FAIL   (1UL << 7)      
#define EWDG_RST_TIMEOUT                (1UL << 17)     
#define EWDG_RST_REFRESH_UNLOCK_FAIL    (1UL << 21)     
#define EWDG_RST_REFRESH_VIOLATION      (1UL << 23)     
#define EWDG_RST_ALL    (EWDG_RST_PARITY_FAIL | EWDG_RST_CTRL_REG_UNLOCK_FAIL | EWDG_RST_CTRL_REG_UPDATE_FAIL | \
                         EWDG_RST_TIMEOUT | EWDG_RST_REFRESH_UNLOCK_FAIL | EWDG_RST_REFRESH_VIOLATION)
typedef enum {
    ewdg_refresh_unlock_method_password = 0,
    ewdg_refresh_unlock_method_ring_left_shift_password_by_1 = 1,
    ewdg_refresh_unlock_method_fixed_key = 2,
    ewdg_refresh_unlock_method_ring_left_shift_password_by_1_bit0_xor_password_bit0 = 3,
    ewdg_refresh_unlock_method_max = ewdg_refresh_unlock_method_ring_left_shift_password_by_1_bit0_xor_password_bit0
} ewdg_refresh_unlock_method_t;
 
typedef enum {
    ewdg_cnt_clk_src_bus_clk,        
    ewdg_cnt_clk_src_ext_osc_clk,    
} ewdg_cnt_clk_sel_t;
 
typedef enum {
    ewdg_window_lower_timeout_period_8_div_16 = 0,
    ewdg_window_lower_timeout_period_10_div_16 = 1,
    ewdg_window_lower_timeout_period_12_div_16 = 2,
    ewdg_window_lower_timeout_period_14_div_16 = 3,
    ewdg_window_lower_timeout_period_max = ewdg_window_lower_timeout_period_14_div_16
} ewdg_window_low_limit_t;
 
typedef enum {
    ewdg_window_upper_timeout_period_8_div_16 = 0,     
    ewdg_window_upper_timeout_period_1_div_16 = 1,     
    ewdg_window_upper_timeout_period_2_div_16 = 2,     
    ewdg_window_upper_timeout_period_3_div_16 = 3,     
    ewdg_window_upper_timeout_period_4_div_16 = 4,     
    ewdg_window_upper_timeout_period_5_div_16 = 5,     
    ewdg_window_upper_timeout_period_6_div_16 = 6,     
    ewdg_window_upper_timeout_period_7_div_16 = 8,     
    ewdg_window_upper_timeout_period_max = ewdg_window_upper_timeout_period_7_div_16
} ewdg_window_upper_limit_t;
 
typedef enum {
    ewdg_low_power_mode_halt = 0,               
    ewdg_low_power_mode_work_clock_normal = 1,  
} ewdg_low_power_mode_t;
 
/***
 * @brief EWDG Function Control Configurations
 */
typedef struct {
    ewdg_cnt_clk_sel_t cnt_clk_sel;                     
    bool enable_window_mode;                            
    ewdg_window_low_limit_t window_lower_limit;         
    ewdg_window_upper_limit_t window_upper_limit;
 
    bool enable_config_lock;                            
    bool enable_refresh_period;                         
    bool enable_refresh_lock;                           
    ewdg_refresh_unlock_method_t refresh_unlock_method; 
    bool keep_running_in_debug_mode;                    
    ewdg_low_power_mode_t low_power_mode;               
    bool use_lowlevel_timeout;
    union {
        struct {
            uint32_t timeout_interrupt_us;  
            uint32_t timeout_reset_us;      
        };
        struct {
            uint32_t timeout_interrupt_val;           
            uint32_t timeout_reset_val;
            uint32_t clock_div_by_power_of_2; 
        };
    };
 
    uint16_t refresh_period_in_bus_cycles;              
    uint16_t refresh_unlock_password;                   
    uint16_t ctrl_reg_update_password;                  
    uint16_t ctrl_reg_update_period_bus_clk_x_128;      
} ewdg_func_ctrl_config_t;
 
typedef struct {
    bool enable_ctrl_parity_fail_interrupt;         
    bool enable_ctrl_parity_fail_reset;             
    bool enable_ctrl_unlock_fail_interrupt;         
    bool enable_ctrl_unlock_fail_reset;             
    bool enable_ctrl_update_violation_interrupt;    
    bool enable_ctrl_update_violation_reset;        
    bool enable_timeout_interrupt;                  
    bool enable_timeout_reset;                      
    bool enable_refresh_unlock_fail_interrupt;      
    bool enable_refresh_unlock_fail_reset;          
    bool enable_refresh_violation_interrupt;        
    bool enable_refresh_violation_reset;            
} ewdg_interrupt_reset_config_t;
 
typedef struct {
    ewdg_interrupt_reset_config_t int_rst_config;   
    ewdg_func_ctrl_config_t ctrl_config;            
    bool enable_watchdog;                           
    uint32_t cnt_src_freq;                          
} ewdg_config_t;
 
static inline bool ewdg_is_ctrl_reg_locked(EWDG_Type *ptr)
{
    return ((ptr->CTRL0 & EWDG_CTRL0_CFG_LOCK_MASK) != 0U);
}
 
static inline uint32_t ewdg_get_count_clk_divider(EWDG_Type *ptr)
{
    return (1UL << EWDG_CTRL0_DIV_VALUE_GET(ptr->CTRL0));
}
 
static inline bool ewdg_is_refresh_locked(EWDG_Type *ptr)
{
    return ((ptr->CTRL0 & EWDG_CTRL0_REF_LOCK_MASK) != 0U);
}
 
static inline void ewdg_unlock_ctrl_regs(EWDG_Type *ptr)
{
    uint32_t ctrl_update_prot = ptr->CFG_PROT;
    ptr->CFG_PROT = ctrl_update_prot;
}
 
static inline void ewdg_write_refresh_reg(EWDG_Type *ptr)
{
    ptr->WDT_REFRESH_REG = EWDG_REFRESH_KEY;
}
 
static inline uint32_t ewdg_get_timeout_reset_ticks(EWDG_Type *ptr)
{
    return ptr->OT_RST_VAL;
}
 
#if defined(HPM_IP_FEATURE_EWDG_SOC_SUPPORT_TIMEOUT_INTERRUPT) && (HPM_IP_FEATURE_EWDG_SOC_SUPPORT_TIMEOUT_INTERRUPT == 1)
static inline uint32_t ewdg_get_timeout_interrupt_ticks(EWDG_Type *ptr)
{
    return ptr->OT_INT_VAL;
}
#endif
 
static inline void ewdg_clear_status_flags(EWDG_Type *ptr, uint32_t mask)
{
    ptr->WDT_STATUS = mask;
}
 
static inline uint32_t ewdg_get_status_flags(EWDG_Type *ptr)
{
    return ptr->WDT_STATUS;
}
 
static inline ewdg_refresh_unlock_method_t ewdg_get_refresh_unlock_method(EWDG_Type *ptr)
{
    return (ewdg_refresh_unlock_method_t) (EWDG_CTRL0_REF_UNLOCK_MEC_GET(ptr->CTRL0));
}
 
void ewdg_enable(EWDG_Type *ptr);
 
 
void ewdg_disable(EWDG_Type *ptr);
 
hpm_stat_t ewdg_init_ctrl_func(EWDG_Type *ptr, ewdg_func_ctrl_config_t *config, uint32_t cnt_src_freq);
 
hpm_stat_t ewdg_init_interrupt_reset(EWDG_Type *ptr, ewdg_interrupt_reset_config_t *config);
 
void ewdg_get_default_config(EWDG_Type *ptr, ewdg_config_t *config);
 
hpm_stat_t ewdg_init(EWDG_Type *ptr, ewdg_config_t *config);
 
hpm_stat_t ewdg_unlock_refresh(EWDG_Type *ptr);
 
hpm_stat_t ewdg_refresh(EWDG_Type *ptr);
 
uint32_t ewdg_get_count_clock_freq(EWDG_Type *ptr, uint32_t src_clk_freq);
 
uint64_t ewdg_convert_timeout_us_to_timeout_ticks(uint32_t src_clk_freq, uint32_t timeout_us);
 
uint32_t ewdg_convert_timeout_ticks_to_timeout_us(EWDG_Type *ptr, uint32_t src_clk_freq, uint32_t timeout_ticks);
 
void ewdg_enable_interrupt(EWDG_Type *ptr, uint32_t mask);
 
void ewdg_disable_interrupt(EWDG_Type *ptr, uint32_t mask);
 
void ewdg_enable_reset(EWDG_Type *ptr, uint32_t mask);
 
void ewdg_disable_reset(EWDG_Type *ptr, uint32_t mask);
 
void ewdg_switch_clock_source(EWDG_Type *ptr, ewdg_cnt_clk_sel_t clk_sel);
 
 
#ifdef __cplusplus
}
#endif
 
#endif /* HPM_EWDG_DRV_H */