HPM SDK
HPMicro Software Development Kit
hpm_pla_regs.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_PLA_H
10 #define HPM_PLA_H
11 
12 typedef struct {
13  struct {
14  __RW uint32_t AOI_16TO8[8]; /* 0x0 - 0x1C: CHN AOI_16to8 AND logic cfg */
15  __RW uint32_t AOI_8TO7_00_01; /* 0x20: CHN AOI_16to8_00_01 OR logic cfg */
16  __RW uint32_t AOI_8TO7_02_03; /* 0x24: CHN AOI_16to8_02_03 OR logic cfg */
17  __RW uint32_t AOI_8TO7_04_05; /* 0x28: CHN AOI_16to8_04_05 OR logic cfg */
18  __RW uint32_t AOI_8TO7_06; /* 0x2C: CHN AOI_16to8_06 OR logic cfg */
19  __RW uint32_t FILTER_2ND[8]; /* 0x30 - 0x4C: CHN SECOND_FILTER cfg */
20  __RW uint32_t FILTER_3RD[7]; /* 0x50 - 0x68: CHN THIRD_FILTER cfg */
21  __RW uint32_t CFG_FF; /* 0x6C: CHN cfg ff */
22  } CHN[8];
23  __R uint8_t RESERVED0[64]; /* 0x380 - 0x3BF: Reserved */
24  __RW uint32_t FILTER_1ST_PLA_IN[8]; /* 0x3C0 - 0x3DC: FRIST_FILTER_PLA_IN setting */
25  __RW uint32_t FILTER_1ST_PLA_OUT[8]; /* 0x3E0 - 0x3FC: FRIST_FILTER_PLA_OUT setting */
26  __RW uint32_t CHN_CFG_ACTIVE[8]; /* 0x400 - 0x41C: CHN cfg active */
27 } PLA_Type;
28 
29 
30 /* Bitfield definition for register of struct array CHN: AOI_16TO8_00 */
31 /*
32  * AOI_16TO8_15 (RW)
33  *
34  * select value for AOI_16to8_15.
35  * 0: 0.
36  * 1: 1st_filter_out[15].
37  * 2: ~1st_filter_out[15].
38  * 3: 1
39  */
40 #define PLA_CHN_AOI_16TO8_AOI_16TO8_15_MASK (0xC0000000UL)
41 #define PLA_CHN_AOI_16TO8_AOI_16TO8_15_SHIFT (30U)
42 #define PLA_CHN_AOI_16TO8_AOI_16TO8_15_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_15_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_15_MASK)
43 #define PLA_CHN_AOI_16TO8_AOI_16TO8_15_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_15_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_15_SHIFT)
44 
45 /*
46  * AOI_16TO8_14 (RW)
47  *
48  * select value for AOI_16to8_14.
49  * 0: 0.
50  * 1: 1st_filter_out[14].
51  * 2: ~1st_filter_out[14].
52  * 3: 1
53  */
54 #define PLA_CHN_AOI_16TO8_AOI_16TO8_14_MASK (0x30000000UL)
55 #define PLA_CHN_AOI_16TO8_AOI_16TO8_14_SHIFT (28U)
56 #define PLA_CHN_AOI_16TO8_AOI_16TO8_14_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_14_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_14_MASK)
57 #define PLA_CHN_AOI_16TO8_AOI_16TO8_14_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_14_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_14_SHIFT)
58 
59 /*
60  * AOI_16TO8_13 (RW)
61  *
62  * select value for AOI_16to8_13.
63  * 0: 0.
64  * 1: 1st_filter_out[13].
65  * 2: ~1st_filter_out[13].
66  * 3: 1
67  */
68 #define PLA_CHN_AOI_16TO8_AOI_16TO8_13_MASK (0xC000000UL)
69 #define PLA_CHN_AOI_16TO8_AOI_16TO8_13_SHIFT (26U)
70 #define PLA_CHN_AOI_16TO8_AOI_16TO8_13_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_13_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_13_MASK)
71 #define PLA_CHN_AOI_16TO8_AOI_16TO8_13_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_13_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_13_SHIFT)
72 
73 /*
74  * AOI_16TO8_12 (RW)
75  *
76  * select value for AOI_16to8_12.
77  * 0: 0.
78  * 1: 1st_filter_out[12].
79  * 2: ~1st_filter_out[12].
80  * 3: 1
81  */
82 #define PLA_CHN_AOI_16TO8_AOI_16TO8_12_MASK (0x3000000UL)
83 #define PLA_CHN_AOI_16TO8_AOI_16TO8_12_SHIFT (24U)
84 #define PLA_CHN_AOI_16TO8_AOI_16TO8_12_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_12_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_12_MASK)
85 #define PLA_CHN_AOI_16TO8_AOI_16TO8_12_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_12_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_12_SHIFT)
86 
87 /*
88  * AOI_16TO8_11 (RW)
89  *
90  * select value for AOI_16to8_11.
91  * 0: 0.
92  * 1: 1st_filter_out[11].
93  * 2: ~1st_filter_out[11].
94  * 3: 1
95  */
96 #define PLA_CHN_AOI_16TO8_AOI_16TO8_11_MASK (0xC00000UL)
97 #define PLA_CHN_AOI_16TO8_AOI_16TO8_11_SHIFT (22U)
98 #define PLA_CHN_AOI_16TO8_AOI_16TO8_11_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_11_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_11_MASK)
99 #define PLA_CHN_AOI_16TO8_AOI_16TO8_11_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_11_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_11_SHIFT)
100 
101 /*
102  * AOI_16TO8_10 (RW)
103  *
104  * select value for AOI_16to8_10.
105  * 0: 0.
106  * 1: 1st_filter_out[10].
107  * 2: ~1st_filter_out[10].
108  * 3: 1
109  */
110 #define PLA_CHN_AOI_16TO8_AOI_16TO8_10_MASK (0x300000UL)
111 #define PLA_CHN_AOI_16TO8_AOI_16TO8_10_SHIFT (20U)
112 #define PLA_CHN_AOI_16TO8_AOI_16TO8_10_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_10_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_10_MASK)
113 #define PLA_CHN_AOI_16TO8_AOI_16TO8_10_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_10_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_10_SHIFT)
114 
115 /*
116  * AOI_16TO8_9 (RW)
117  *
118  * select value for AOI_16to8_9.
119  * 0: 0.
120  * 1: 1st_filter_out[9].
121  * 2: ~1st_filter_out[9].
122  * 3: 1
123  */
124 #define PLA_CHN_AOI_16TO8_AOI_16TO8_9_MASK (0xC0000UL)
125 #define PLA_CHN_AOI_16TO8_AOI_16TO8_9_SHIFT (18U)
126 #define PLA_CHN_AOI_16TO8_AOI_16TO8_9_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_9_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_9_MASK)
127 #define PLA_CHN_AOI_16TO8_AOI_16TO8_9_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_9_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_9_SHIFT)
128 
129 /*
130  * AOI_16TO8_8 (RW)
131  *
132  * select value for AOI_16to8_8.
133  * 0: 0.
134  * 1: 1st_filter_out[8].
135  * 2: ~1st_filter_out[8].
136  * 3: 1
137  */
138 #define PLA_CHN_AOI_16TO8_AOI_16TO8_8_MASK (0x30000UL)
139 #define PLA_CHN_AOI_16TO8_AOI_16TO8_8_SHIFT (16U)
140 #define PLA_CHN_AOI_16TO8_AOI_16TO8_8_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_8_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_8_MASK)
141 #define PLA_CHN_AOI_16TO8_AOI_16TO8_8_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_8_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_8_SHIFT)
142 
143 /*
144  * AOI_16TO8_7 (RW)
145  *
146  * select value for AOI_16to8_7.
147  * 0: 0.
148  * 1: 1st_filter_out[7].
149  * 2: ~1st_filter_out[7].
150  * 3: 1
151  */
152 #define PLA_CHN_AOI_16TO8_AOI_16TO8_7_MASK (0xC000U)
153 #define PLA_CHN_AOI_16TO8_AOI_16TO8_7_SHIFT (14U)
154 #define PLA_CHN_AOI_16TO8_AOI_16TO8_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_7_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_7_MASK)
155 #define PLA_CHN_AOI_16TO8_AOI_16TO8_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_7_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_7_SHIFT)
156 
157 /*
158  * AOI_16TO8_6 (RW)
159  *
160  * select value for AOI_16to8_6.
161  * 0: 0.
162  * 1: 1st_filter_out[6].
163  * 2: ~1st_filter_out[6].
164  * 3: 1
165  */
166 #define PLA_CHN_AOI_16TO8_AOI_16TO8_6_MASK (0x3000U)
167 #define PLA_CHN_AOI_16TO8_AOI_16TO8_6_SHIFT (12U)
168 #define PLA_CHN_AOI_16TO8_AOI_16TO8_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_6_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_6_MASK)
169 #define PLA_CHN_AOI_16TO8_AOI_16TO8_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_6_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_6_SHIFT)
170 
171 /*
172  * AOI_16TO8_5 (RW)
173  *
174  * select value for AOI_16to8_5.
175  * 0: 0.
176  * 1: 1st_filter_out[5].
177  * 2: ~1st_filter_out[5].
178  * 3: 1
179  */
180 #define PLA_CHN_AOI_16TO8_AOI_16TO8_5_MASK (0xC00U)
181 #define PLA_CHN_AOI_16TO8_AOI_16TO8_5_SHIFT (10U)
182 #define PLA_CHN_AOI_16TO8_AOI_16TO8_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_5_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_5_MASK)
183 #define PLA_CHN_AOI_16TO8_AOI_16TO8_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_5_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_5_SHIFT)
184 
185 /*
186  * AOI_16TO8_4 (RW)
187  *
188  * select value for AOI_16to8_4.
189  * 0: 0.
190  * 1: 1st_filter_out[4].
191  * 2: ~1st_filter_out[4].
192  * 3: 1
193  */
194 #define PLA_CHN_AOI_16TO8_AOI_16TO8_4_MASK (0x300U)
195 #define PLA_CHN_AOI_16TO8_AOI_16TO8_4_SHIFT (8U)
196 #define PLA_CHN_AOI_16TO8_AOI_16TO8_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_4_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_4_MASK)
197 #define PLA_CHN_AOI_16TO8_AOI_16TO8_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_4_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_4_SHIFT)
198 
199 /*
200  * AOI_16TO8_3 (RW)
201  *
202  * select value for AOI_16to8_3.
203  * 0: 0.
204  * 1: 1st_filter_out[3].
205  * 2: ~1st_filter_out[3].
206  * 3: 1
207  */
208 #define PLA_CHN_AOI_16TO8_AOI_16TO8_3_MASK (0xC0U)
209 #define PLA_CHN_AOI_16TO8_AOI_16TO8_3_SHIFT (6U)
210 #define PLA_CHN_AOI_16TO8_AOI_16TO8_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_3_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_3_MASK)
211 #define PLA_CHN_AOI_16TO8_AOI_16TO8_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_3_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_3_SHIFT)
212 
213 /*
214  * AOI_16TO8_2 (RW)
215  *
216  * select value for AOI_16to8_2.
217  * 0: 0.
218  * 1: 1st_filter_out[2].
219  * 2: ~1st_filter_out[2].
220  * 3: 1
221  */
222 #define PLA_CHN_AOI_16TO8_AOI_16TO8_2_MASK (0x30U)
223 #define PLA_CHN_AOI_16TO8_AOI_16TO8_2_SHIFT (4U)
224 #define PLA_CHN_AOI_16TO8_AOI_16TO8_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_2_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_2_MASK)
225 #define PLA_CHN_AOI_16TO8_AOI_16TO8_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_2_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_2_SHIFT)
226 
227 /*
228  * AOI_16TO8_1 (RW)
229  *
230  * select value for AOI_16to8_1.
231  * 0: 0.
232  * 1: 1st_filter_out[1].
233  * 2: ~1st_filter_out[1].
234  * 3: 1
235  */
236 #define PLA_CHN_AOI_16TO8_AOI_16TO8_1_MASK (0xCU)
237 #define PLA_CHN_AOI_16TO8_AOI_16TO8_1_SHIFT (2U)
238 #define PLA_CHN_AOI_16TO8_AOI_16TO8_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_1_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_1_MASK)
239 #define PLA_CHN_AOI_16TO8_AOI_16TO8_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_1_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_1_SHIFT)
240 
241 /*
242  * AOI_16TO8_0 (RW)
243  *
244  * select value for AOI_16to8_0.
245  * 0: 0.
246  * 1: 1st_filter_out[0].
247  * 2: ~1st_filter_out[0].
248  * 3: 1
249  */
250 #define PLA_CHN_AOI_16TO8_AOI_16TO8_0_MASK (0x3U)
251 #define PLA_CHN_AOI_16TO8_AOI_16TO8_0_SHIFT (0U)
252 #define PLA_CHN_AOI_16TO8_AOI_16TO8_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_0_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_0_MASK)
253 #define PLA_CHN_AOI_16TO8_AOI_16TO8_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_0_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_0_SHIFT)
254 
255 /* Bitfield definition for register of struct array CHN: AOI_8TO7_00_01 */
256 /*
257  * AOI_8TO7_01_7 (RW)
258  *
259  * select value for AOI_8to7_01_7.
260  * 0: 0.
261  * 1: 2nd_filter_out[7].
262  * 2: ~2nd_filter_out[7].
263  * 3: 1
264  */
265 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_MASK (0xC0000000UL)
266 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_SHIFT (30U)
267 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_MASK)
268 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_SHIFT)
269 
270 /*
271  * AOI_8TO7_01_6 (RW)
272  *
273  * select value for AOI_8to7_01_6.
274  * 0: 0.
275  * 1: 2nd_filter_out[6].
276  * 2: ~2nd_filter_out[6].
277  * 3: 1
278  */
279 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_MASK (0x30000000UL)
280 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_SHIFT (28U)
281 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_MASK)
282 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_SHIFT)
283 
284 /*
285  * AOI_8TO7_01_5 (RW)
286  *
287  * select value for AOI_8to7_01_5.
288  * 0: 0.
289  * 1: 2nd_filter_out[5].
290  * 2: ~2nd_filter_out[5].
291  * 3: 1
292  */
293 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_MASK (0xC000000UL)
294 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_SHIFT (26U)
295 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_MASK)
296 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_SHIFT)
297 
298 /*
299  * AOI_8TO7_01_4 (RW)
300  *
301  * select value for AOI_8to7_01_4.
302  * 0: 0.
303  * 1: 2nd_filter_out[4].
304  * 2: ~2nd_filter_out[4].
305  * 3: 1
306  */
307 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_MASK (0x3000000UL)
308 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_SHIFT (24U)
309 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_MASK)
310 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_SHIFT)
311 
312 /*
313  * AOI_8TO7_01_3 (RW)
314  *
315  * select value for AOI_8to7_01_3.
316  * 0: 0.
317  * 1: 2nd_filter_out[3].
318  * 2: ~2nd_filter_out[3].
319  * 3: 1
320  */
321 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_MASK (0xC00000UL)
322 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_SHIFT (22U)
323 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_MASK)
324 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_SHIFT)
325 
326 /*
327  * AOI_8TO7_01_2 (RW)
328  *
329  * select value for AOI_8to7_01_2.
330  * 0: 0.
331  * 1: 2nd_filter_out[2].
332  * 2: ~2nd_filter_out[2].
333  * 3: 1
334  */
335 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_MASK (0x300000UL)
336 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_SHIFT (20U)
337 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_MASK)
338 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_SHIFT)
339 
340 /*
341  * AOI_8TO7_01_1 (RW)
342  *
343  * select value for AOI_8to7_01_1.
344  * 0: 0.
345  * 1: 2nd_filter_out[1].
346  * 2: ~2nd_filter_out[1].
347  * 3: 1
348  */
349 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_MASK (0xC0000UL)
350 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_SHIFT (18U)
351 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_MASK)
352 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_SHIFT)
353 
354 /*
355  * AOI_8TO7_01_0 (RW)
356  *
357  * select value for AOI_8to7_01_0.
358  * 0: 0.
359  * 1: 2nd_filter_out[0].
360  * 2: ~2nd_filter_out[0].
361  * 3: 1
362  */
363 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_MASK (0x30000UL)
364 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_SHIFT (16U)
365 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_MASK)
366 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_SHIFT)
367 
368 /*
369  * AOI_8TO7_00_7 (RW)
370  *
371  * select value for AOI_8to7_00_7.
372  * 0: 0.
373  * 1: 2nd_filter_out[7].
374  * 2: ~2nd_filter_out[7].
375  * 3: 1
376  */
377 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_MASK (0xC000U)
378 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_SHIFT (14U)
379 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_MASK)
380 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_SHIFT)
381 
382 /*
383  * AOI_8TO7_00_6 (RW)
384  *
385  * select value for AOI_8to7_00_6.
386  * 0: 0.
387  * 1: 2nd_filter_out[6].
388  * 2: ~2nd_filter_out[6].
389  * 3: 1
390  */
391 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_MASK (0x3000U)
392 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_SHIFT (12U)
393 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_MASK)
394 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_SHIFT)
395 
396 /*
397  * AOI_8TO7_00_5 (RW)
398  *
399  * select value for AOI_8to7_00_5.
400  * 0: 0.
401  * 1: 2nd_filter_out[5].
402  * 2: ~2nd_filter_out[5].
403  * 3: 1
404  */
405 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_MASK (0xC00U)
406 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_SHIFT (10U)
407 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_MASK)
408 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_SHIFT)
409 
410 /*
411  * AOI_8TO7_00_4 (RW)
412  *
413  * select value for AOI_8to7_00_4.
414  * 0: 0.
415  * 1: 2nd_filter_out[4].
416  * 2: ~2nd_filter_out[4].
417  * 3: 1
418  */
419 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_MASK (0x300U)
420 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_SHIFT (8U)
421 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_MASK)
422 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_SHIFT)
423 
424 /*
425  * AOI_8TO7_00_3 (RW)
426  *
427  * select value for AOI_8to7_00_3.
428  * 0: 0.
429  * 1: 2nd_filter_out[3].
430  * 2: ~2nd_filter_out[3].
431  * 3: 1
432  */
433 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_MASK (0xC0U)
434 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_SHIFT (6U)
435 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_MASK)
436 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_SHIFT)
437 
438 /*
439  * AOI_8TO7_00_2 (RW)
440  *
441  * select value for AOI_8to7_00_2.
442  * 0: 0.
443  * 1: 2nd_filter_out[2].
444  * 2: ~2nd_filter_out[2].
445  * 3: 1
446  */
447 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_MASK (0x30U)
448 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_SHIFT (4U)
449 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_MASK)
450 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_SHIFT)
451 
452 /*
453  * AOI_8TO7_00_1 (RW)
454  *
455  * select value for AOI_8to7_00_1.
456  * 0: 0.
457  * 1: 2nd_filter_out[1].
458  * 2: ~2nd_filter_out[1].
459  * 3: 1
460  */
461 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_MASK (0xCU)
462 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_SHIFT (2U)
463 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_MASK)
464 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_SHIFT)
465 
466 /*
467  * AOI_8TO7_00_0 (RW)
468  *
469  * select value for AOI_8to7_00_0.
470  * 0: 0.
471  * 1: 2nd_filter_out[0].
472  * 2: ~2nd_filter_out[0].
473  * 3: 1
474  */
475 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_MASK (0x3U)
476 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_SHIFT (0U)
477 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_MASK)
478 #define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_SHIFT)
479 
480 /* Bitfield definition for register of struct array CHN: AOI_8TO7_02_03 */
481 /*
482  * AOI_8TO7_03_7 (RW)
483  *
484  * select value for AOI_8to7_03_7.
485  * 0: 0.
486  * 1: 2nd_filter_out[7].
487  * 2: ~2nd_filter_out[7].
488  * 3: 1
489  */
490 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_MASK (0xC0000000UL)
491 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_SHIFT (30U)
492 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_MASK)
493 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_SHIFT)
494 
495 /*
496  * AOI_8TO7_03_6 (RW)
497  *
498  * select value for AOI_8to7_03_6.
499  * 0: 0.
500  * 1: 2nd_filter_out[6].
501  * 2: ~2nd_filter_out[6].
502  * 3: 1
503  */
504 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_MASK (0x30000000UL)
505 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_SHIFT (28U)
506 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_MASK)
507 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_SHIFT)
508 
509 /*
510  * AOI_8TO7_03_5 (RW)
511  *
512  * select value for AOI_8to7_03_5.
513  * 0: 0.
514  * 1: 2nd_filter_out[5].
515  * 2: ~2nd_filter_out[5].
516  * 3: 1
517  */
518 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_MASK (0xC000000UL)
519 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_SHIFT (26U)
520 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_MASK)
521 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_SHIFT)
522 
523 /*
524  * AOI_8TO7_03_4 (RW)
525  *
526  * select value for AOI_8to7_03_4.
527  * 0: 0.
528  * 1: 2nd_filter_out[4].
529  * 2: ~2nd_filter_out[4].
530  * 3: 1
531  */
532 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_MASK (0x3000000UL)
533 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_SHIFT (24U)
534 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_MASK)
535 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_SHIFT)
536 
537 /*
538  * AOI_8TO7_03_3 (RW)
539  *
540  * select value for AOI_8to7_03_3.
541  * 0: 0.
542  * 1: 2nd_filter_out[3].
543  * 2: ~2nd_filter_out[3].
544  * 3: 1
545  */
546 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_MASK (0xC00000UL)
547 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_SHIFT (22U)
548 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_MASK)
549 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_SHIFT)
550 
551 /*
552  * AOI_8TO7_03_2 (RW)
553  *
554  * select value for AOI_8to7_03_2.
555  * 0: 0.
556  * 1: 2nd_filter_out[2].
557  * 2: ~2nd_filter_out[2].
558  * 3: 1
559  */
560 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_MASK (0x300000UL)
561 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_SHIFT (20U)
562 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_MASK)
563 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_SHIFT)
564 
565 /*
566  * AOI_8TO7_03_1 (RW)
567  *
568  * select value for AOI_8to7_03_1.
569  * 0: 0.
570  * 1: 2nd_filter_out[1].
571  * 2: ~2nd_filter_out[1].
572  * 3: 1
573  */
574 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_MASK (0xC0000UL)
575 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_SHIFT (18U)
576 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_MASK)
577 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_SHIFT)
578 
579 /*
580  * AOI_8TO7_03_0 (RW)
581  *
582  * select value for AOI_8to7_03_0.
583  * 0: 0.
584  * 1: 2nd_filter_out[0].
585  * 2: ~2nd_filter_out[0].
586  * 3: 1
587  */
588 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_MASK (0x30000UL)
589 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_SHIFT (16U)
590 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_MASK)
591 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_SHIFT)
592 
593 /*
594  * AOI_8TO7_02_7 (RW)
595  *
596  * select value for AOI_8to7_02_7.
597  * 0: 0.
598  * 1: 2nd_filter_out[7].
599  * 2: ~2nd_filter_out[7].
600  * 3: 1
601  */
602 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_MASK (0xC000U)
603 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_SHIFT (14U)
604 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_MASK)
605 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_SHIFT)
606 
607 /*
608  * AOI_8TO7_02_6 (RW)
609  *
610  * select value for AOI_8to7_02_6.
611  * 0: 0.
612  * 1: 2nd_filter_out[6].
613  * 2: ~2nd_filter_out[6].
614  * 3: 1
615  */
616 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_MASK (0x3000U)
617 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_SHIFT (12U)
618 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_MASK)
619 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_SHIFT)
620 
621 /*
622  * AOI_8TO7_02_5 (RW)
623  *
624  * select value for AOI_8to7_02_5.
625  * 0: 0.
626  * 1: 2nd_filter_out[5].
627  * 2: ~2nd_filter_out[5].
628  * 3: 1
629  */
630 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_MASK (0xC00U)
631 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_SHIFT (10U)
632 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_MASK)
633 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_SHIFT)
634 
635 /*
636  * AOI_8TO7_02_4 (RW)
637  *
638  * select value for AOI_8to7_02_4.
639  * 0: 0.
640  * 1: 2nd_filter_out[4].
641  * 2: ~2nd_filter_out[4].
642  * 3: 1
643  */
644 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_MASK (0x300U)
645 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_SHIFT (8U)
646 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_MASK)
647 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_SHIFT)
648 
649 /*
650  * AOI_8TO7_02_3 (RW)
651  *
652  * select value for AOI_8to7_02_3.
653  * 0: 0.
654  * 1: 2nd_filter_out[3].
655  * 2: ~2nd_filter_out[3].
656  * 3: 1
657  */
658 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_MASK (0xC0U)
659 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_SHIFT (6U)
660 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_MASK)
661 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_SHIFT)
662 
663 /*
664  * AOI_8TO7_02_2 (RW)
665  *
666  * select value for AOI_8to7_02_2.
667  * 0: 0.
668  * 1: 2nd_filter_out[2].
669  * 2: ~2nd_filter_out[2].
670  * 3: 1
671  */
672 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_MASK (0x30U)
673 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_SHIFT (4U)
674 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_MASK)
675 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_SHIFT)
676 
677 /*
678  * AOI_8TO7_02_1 (RW)
679  *
680  * select value for AOI_8to7_02_1.
681  * 0: 0.
682  * 1: 2nd_filter_out[1].
683  * 2: ~2nd_filter_out[1].
684  * 3: 1
685  */
686 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_MASK (0xCU)
687 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_SHIFT (2U)
688 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_MASK)
689 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_SHIFT)
690 
691 /*
692  * AOI_8TO7_02_0 (RW)
693  *
694  * select value for AOI_8to7_02_0.
695  * 0: 0.
696  * 1: 2nd_filter_out[0].
697  * 2: ~2nd_filter_out[0].
698  * 3: 1
699  */
700 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_MASK (0x3U)
701 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_SHIFT (0U)
702 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_MASK)
703 #define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_SHIFT)
704 
705 /* Bitfield definition for register of struct array CHN: AOI_8TO7_04_05 */
706 /*
707  * AOI_8TO7_05_7 (RW)
708  *
709  * select value for AOI_8to7_05_7.
710  * 0: 0.
711  * 1: 2nd_filter_out[7].
712  * 2: ~2nd_filter_out[7].
713  * 3: 1
714  */
715 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_MASK (0xC0000000UL)
716 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_SHIFT (30U)
717 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_MASK)
718 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_SHIFT)
719 
720 /*
721  * AOI_8TO7_05_6 (RW)
722  *
723  * select value for AOI_8to7_05_6.
724  * 0: 0.
725  * 1: 2nd_filter_out[6].
726  * 2: ~2nd_filter_out[6].
727  * 3: 1
728  */
729 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_MASK (0x30000000UL)
730 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_SHIFT (28U)
731 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_MASK)
732 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_SHIFT)
733 
734 /*
735  * AOI_8TO7_05_5 (RW)
736  *
737  * select value for AOI_8to7_05_5.
738  * 0: 0.
739  * 1: 2nd_filter_out[5].
740  * 2: ~2nd_filter_out[5].
741  * 3: 1
742  */
743 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_MASK (0xC000000UL)
744 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_SHIFT (26U)
745 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_MASK)
746 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_SHIFT)
747 
748 /*
749  * AOI_8TO7_05_4 (RW)
750  *
751  * select value for AOI_8to7_05_4.
752  * 0: 0.
753  * 1: 2nd_filter_out[4].
754  * 2: ~2nd_filter_out[4].
755  * 3: 1
756  */
757 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_MASK (0x3000000UL)
758 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_SHIFT (24U)
759 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_MASK)
760 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_SHIFT)
761 
762 /*
763  * AOI_8TO7_05_3 (RW)
764  *
765  * select value for AOI_8to7_05_3.
766  * 0: 0.
767  * 1: 2nd_filter_out[3].
768  * 2: ~2nd_filter_out[3].
769  * 3: 1
770  */
771 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_MASK (0xC00000UL)
772 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_SHIFT (22U)
773 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_MASK)
774 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_SHIFT)
775 
776 /*
777  * AOI_8TO7_05_2 (RW)
778  *
779  * select value for AOI_8to7_05_2.
780  * 0: 0.
781  * 1: 2nd_filter_out[2].
782  * 2: ~2nd_filter_out[2].
783  * 3: 1
784  */
785 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_MASK (0x300000UL)
786 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_SHIFT (20U)
787 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_MASK)
788 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_SHIFT)
789 
790 /*
791  * AOI_8TO7_05_1 (RW)
792  *
793  * select value for AOI_8to7_05_1.
794  * 0: 0.
795  * 1: 2nd_filter_out[1].
796  * 2: ~2nd_filter_out[1].
797  * 3: 1
798  */
799 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_MASK (0xC0000UL)
800 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_SHIFT (18U)
801 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_MASK)
802 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_SHIFT)
803 
804 /*
805  * AOI_8TO7_05_0 (RW)
806  *
807  * select value for AOI_8to7_05_0.
808  * 0: 0.
809  * 1: 2nd_filter_out[0].
810  * 2: ~2nd_filter_out[0].
811  * 3: 1
812  */
813 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_MASK (0x30000UL)
814 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_SHIFT (16U)
815 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_MASK)
816 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_SHIFT)
817 
818 /*
819  * AOI_8TO7_04_7 (RW)
820  *
821  * select value for AOI_8to7_04_7.
822  * 0: 0.
823  * 1: 2nd_filter_out[7].
824  * 2: ~2nd_filter_out[7].
825  * 3: 1
826  */
827 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_MASK (0xC000U)
828 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_SHIFT (14U)
829 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_MASK)
830 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_SHIFT)
831 
832 /*
833  * AOI_8TO7_04_6 (RW)
834  *
835  * select value for AOI_8to7_04_6.
836  * 0: 0.
837  * 1: 2nd_filter_out[6].
838  * 2: ~2nd_filter_out[6].
839  * 3: 1
840  */
841 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_MASK (0x3000U)
842 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_SHIFT (12U)
843 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_MASK)
844 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_SHIFT)
845 
846 /*
847  * AOI_8TO7_04_5 (RW)
848  *
849  * select value for AOI_8to7_04_5.
850  * 0: 0.
851  * 1: 2nd_filter_out[5].
852  * 2: ~2nd_filter_out[5].
853  * 3: 1
854  */
855 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_MASK (0xC00U)
856 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_SHIFT (10U)
857 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_MASK)
858 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_SHIFT)
859 
860 /*
861  * AOI_8TO7_04_4 (RW)
862  *
863  * select value for AOI_8to7_04_4.
864  * 0: 0.
865  * 1: 2nd_filter_out[4].
866  * 2: ~2nd_filter_out[4].
867  * 3: 1
868  */
869 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_MASK (0x300U)
870 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_SHIFT (8U)
871 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_MASK)
872 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_SHIFT)
873 
874 /*
875  * AOI_8TO7_04_3 (RW)
876  *
877  * select value for AOI_8to7_04_3.
878  * 0: 0.
879  * 1: 2nd_filter_out[3].
880  * 2: ~2nd_filter_out[3].
881  * 3: 1
882  */
883 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_MASK (0xC0U)
884 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_SHIFT (6U)
885 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_MASK)
886 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_SHIFT)
887 
888 /*
889  * AOI_8TO7_04_2 (RW)
890  *
891  * select value for AOI_8to7_04_2.
892  * 0: 0.
893  * 1: 2nd_filter_out[2].
894  * 2: ~2nd_filter_out[2].
895  * 3: 1
896  */
897 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_MASK (0x30U)
898 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_SHIFT (4U)
899 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_MASK)
900 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_SHIFT)
901 
902 /*
903  * AOI_8TO7_04_1 (RW)
904  *
905  * select value for AOI_8to7_04_1.
906  * 0: 0.
907  * 1: 2nd_filter_out[1].
908  * 2: ~2nd_filter_out[1].
909  * 3: 1
910  */
911 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_MASK (0xCU)
912 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_SHIFT (2U)
913 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_MASK)
914 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_SHIFT)
915 
916 /*
917  * AOI_8TO7_04_0 (RW)
918  *
919  * select value for AOI_8to7_04_0.
920  * 0: 0.
921  * 1: 2nd_filter_out[0].
922  * 2: ~2nd_filter_out[0].
923  * 3: 1
924  */
925 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_MASK (0x3U)
926 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_SHIFT (0U)
927 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_MASK)
928 #define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_SHIFT)
929 
930 /* Bitfield definition for register of struct array CHN: AOI_8TO7_06 */
931 /*
932  * AOI_8TO7_06_7 (RW)
933  *
934  * select value for AOI_8to7_06_7.
935  * 0: 0.
936  * 1: 2nd_filter_out[7].
937  * 2: ~2nd_filter_out[7].
938  * 3: 1
939  */
940 #define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_MASK (0xC000U)
941 #define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_SHIFT (14U)
942 #define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_MASK)
943 #define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_SHIFT)
944 
945 /*
946  * AOI_8TO7_06_6 (RW)
947  *
948  * select value for AOI_8to7_06_6.
949  * 0: 0.
950  * 1: 2nd_filter_out[6].
951  * 2: ~2nd_filter_out[6].
952  * 3: 1
953  */
954 #define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_MASK (0x3000U)
955 #define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_SHIFT (12U)
956 #define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_MASK)
957 #define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_SHIFT)
958 
959 /*
960  * AOI_8TO7_06_5 (RW)
961  *
962  * select value for AOI_8to7_06_5.
963  * 0: 0.
964  * 1: 2nd_filter_out[5].
965  * 2: ~2nd_filter_out[5].
966  * 3: 1
967  */
968 #define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_MASK (0xC00U)
969 #define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_SHIFT (10U)
970 #define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_MASK)
971 #define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_SHIFT)
972 
973 /*
974  * AOI_8TO7_06_4 (RW)
975  *
976  * select value for AOI_8to7_06_4.
977  * 0: 0.
978  * 1: 2nd_filter_out[4].
979  * 2: ~2nd_filter_out[4].
980  * 3: 1
981  */
982 #define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_MASK (0x300U)
983 #define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_SHIFT (8U)
984 #define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_MASK)
985 #define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_SHIFT)
986 
987 /*
988  * AOI_8TO7_06_3 (RW)
989  *
990  * select value for AOI_8to7_06_3.
991  * 0: 0.
992  * 1: 2nd_filter_out[3].
993  * 2: ~2nd_filter_out[3].
994  * 3: 1
995  */
996 #define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_MASK (0xC0U)
997 #define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_SHIFT (6U)
998 #define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_MASK)
999 #define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_SHIFT)
1000 
1001 /*
1002  * AOI_8TO7_06_2 (RW)
1003  *
1004  * select value for AOI_8to7_06_2.
1005  * 0: 0.
1006  * 1: 2nd_filter_out[2].
1007  * 2: ~2nd_filter_out[2].
1008  * 3: 1
1009  */
1010 #define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_MASK (0x30U)
1011 #define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_SHIFT (4U)
1012 #define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_MASK)
1013 #define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_SHIFT)
1014 
1015 /*
1016  * AOI_8TO7_06_1 (RW)
1017  *
1018  * select value for AOI_8to7_06_1.
1019  * 0: 0.
1020  * 1: 2nd_filter_out[1].
1021  * 2: ~2nd_filter_out[1].
1022  * 3: 1
1023  */
1024 #define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_MASK (0xCU)
1025 #define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_SHIFT (2U)
1026 #define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_MASK)
1027 #define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_SHIFT)
1028 
1029 /*
1030  * AOI_8TO7_06_0 (RW)
1031  *
1032  * select value for AOI_8to7_06_0.
1033  * 0: 0.
1034  * 1: 2nd_filter_out[0].
1035  * 2: ~2nd_filter_out[0].
1036  * 3: 1
1037  */
1038 #define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_MASK (0x3U)
1039 #define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_SHIFT (0U)
1040 #define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_MASK)
1041 #define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_SHIFT)
1042 
1043 /* Bitfield definition for register of struct array CHN: SECOND_FILTER_0 */
1044 /*
1045  * FILTER_EXT_COUNTER (RW)
1046  *
1047  * filter_ext counter value, cycles for filter or extent by system clock。
1048  * 0：0*apb_clk_period
1049  * 1：1*apb_clk_period
1050  * 2: 2*apb_clk_period
1051  * …
1052  * 65535: 65535*apb_clk_period
1053  */
1054 #define PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_MASK (0xFFFF0000UL)
1055 #define PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_SHIFT (16U)
1056 #define PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_SHIFT) & PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_MASK)
1057 #define PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_MASK) >> PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_SHIFT)
1058 
1059 /*
1060  * FILTER_EXT_TYPE (RW)
1061  *
1062  * filter extend type.
1063  * 0-3：nothing to do.
1064  * 4： input high level extend.
1065  * 5： input low level extend.
1066  * 6： output extend.
1067  * 7： input pulse extend.
1068  */
1069 #define PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_MASK (0x7000U)
1070 #define PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_SHIFT (12U)
1071 #define PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_SHIFT) & PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_MASK)
1072 #define PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_MASK) >> PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_SHIFT)
1073 
1074 /*
1075  * FILTER_EXT_ENABLE (RW)
1076  *
1077  * filter extend enable.
1078  * 0. bypass filter extend. all setting in bit31:12 are inactive
1079  * 1. enable filter extend, all setting in bit31:12 are active.
1080  */
1081 #define PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_MASK (0x100U)
1082 #define PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_SHIFT (8U)
1083 #define PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_SHIFT) & PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_MASK)
1084 #define PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_MASK) >> PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_SHIFT)
1085 
1086 /*
1087  * FILTER_SYNC_LEVEL (RW)
1088  *
1089  * synchroniser level.
1090  * 0: 2 level sync.
1091  * 1: 3 level sync
1092  */
1093 #define PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_MASK (0x80U)
1094 #define PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_SHIFT (7U)
1095 #define PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_SHIFT) & PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_MASK)
1096 #define PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_MASK) >> PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_SHIFT)
1097 
1098 /*
1099  * POSE_EDGE_DECT_ENABLE (RW)
1100  *
1101  * pose edge detector enable.
1102  * 0: disable.
1103  * 1: enable.
1104  */
1105 #define PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_MASK (0x40U)
1106 #define PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_SHIFT (6U)
1107 #define PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_SHIFT) & PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_MASK)
1108 #define PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_MASK) >> PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_SHIFT)
1109 
1110 /*
1111  * NEGE_EDGE_DECT_ENABLE (RW)
1112  *
1113  * nege edge detector enable.
1114  * 0: disable.
1115  * 1: enable.
1116  */
1117 #define PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_MASK (0x20U)
1118 #define PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_SHIFT (5U)
1119 #define PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_SHIFT) & PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_MASK)
1120 #define PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_MASK) >> PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_SHIFT)
1121 
1122 /*
1123  * EDGE_DECT_ENABLE (RW)
1124  *
1125  * edge detector enable.
1126  * 0: disable. bit6/bit5 setting inactive.
1127  * 1: enable. bit6/bit5 setting active.
1128  */
1129 #define PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_MASK (0x10U)
1130 #define PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_SHIFT (4U)
1131 #define PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_SHIFT) & PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_MASK)
1132 #define PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_MASK) >> PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_SHIFT)
1133 
1134 /*
1135  * FILTER_REVERSE (RW)
1136  *
1137  * reverse sync and edge detector filter's output.
1138  * 0: not reverse.
1139  * 1: reverse.
1140  */
1141 #define PLA_CHN_FILTER_2ND_FILTER_REVERSE_MASK (0x8U)
1142 #define PLA_CHN_FILTER_2ND_FILTER_REVERSE_SHIFT (3U)
1143 #define PLA_CHN_FILTER_2ND_FILTER_REVERSE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_FILTER_REVERSE_SHIFT) & PLA_CHN_FILTER_2ND_FILTER_REVERSE_MASK)
1144 #define PLA_CHN_FILTER_2ND_FILTER_REVERSE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_FILTER_REVERSE_MASK) >> PLA_CHN_FILTER_2ND_FILTER_REVERSE_SHIFT)
1145 
1146 /*
1147  * SOFTWARE_INJECT (RW)
1148  *
1149  * software inject value for sync and edge detector filter.
1150  * 0: inject low level.
1151  * 1: inject high level.
1152  * 2: not inject.
1153  * 3. inject high level.
1154  */
1155 #define PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_MASK (0x6U)
1156 #define PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_SHIFT (1U)
1157 #define PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_SHIFT) & PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_MASK)
1158 #define PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_MASK) >> PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_SHIFT)
1159 
1160 /*
1161  * SYNC_EDGE_FILTER_ENABLE (RW)
1162  *
1163  * sync and edge detector filter.
1164  * 0: disable.
1165  * 1: enable.
1166  */
1167 #define PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_MASK (0x1U)
1168 #define PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_SHIFT (0U)
1169 #define PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_SHIFT) & PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_MASK)
1170 #define PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_MASK) >> PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_SHIFT)
1171 
1172 /* Bitfield definition for register of struct array CHN: THIRD_FILTER_0 */
1173 /*
1174  * FILTER_EXT_COUNTER (RW)
1175  *
1176  * filter_ext counter value, cycles for filter or extent by system clock。
1177  * 0：0*apb_clk_period
1178  * 1：1*apb_clk_period
1179  * 2: 2*apb_clk_period
1180  * …
1181  * 65535: 65535*apb_clk_period
1182  */
1183 #define PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_MASK (0xFFFF0000UL)
1184 #define PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_SHIFT (16U)
1185 #define PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_SHIFT) & PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_MASK)
1186 #define PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_MASK) >> PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_SHIFT)
1187 
1188 /*
1189  * FILTER_EXT_TYPE (RW)
1190  *
1191  * filter extend type.
1192  * 0-3：nothing to do.
1193  * 4： input high level extend.
1194  * 5： input low level extend.
1195  * 6： output extend.
1196  * 7： input pulse extend.
1197  */
1198 #define PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_MASK (0x7000U)
1199 #define PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_SHIFT (12U)
1200 #define PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_SHIFT) & PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_MASK)
1201 #define PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_MASK) >> PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_SHIFT)
1202 
1203 /*
1204  * FILTER_EXT_ENABLE (RW)
1205  *
1206  * filter extend enable.
1207  * 0. bypass filter extend. all setting in bit31:12 are inactive
1208  * 1. enable filter extend, all setting in bit31:12 are active.
1209  */
1210 #define PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_MASK (0x100U)
1211 #define PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_SHIFT (8U)
1212 #define PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_SHIFT) & PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_MASK)
1213 #define PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_MASK) >> PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_SHIFT)
1214 
1215 /*
1216  * FILTER_SYNC_LEVEL (RW)
1217  *
1218  * synchroniser level.
1219  * 0: 2 level sync.
1220  * 1: 3 level sync
1221  */
1222 #define PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_MASK (0x80U)
1223 #define PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_SHIFT (7U)
1224 #define PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_SHIFT) & PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_MASK)
1225 #define PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_MASK) >> PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_SHIFT)
1226 
1227 /*
1228  * POSE_EDGE_DECT_ENABLE (RW)
1229  *
1230  * pose edge detector enable.
1231  * 0: disable.
1232  * 1: enable.
1233  */
1234 #define PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_MASK (0x40U)
1235 #define PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_SHIFT (6U)
1236 #define PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_SHIFT) & PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_MASK)
1237 #define PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_MASK) >> PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_SHIFT)
1238 
1239 /*
1240  * NEGE_EDGE_DECT_ENABLE (RW)
1241  *
1242  * nege edge detector enable.
1243  * 0: disable.
1244  * 1: enable.
1245  */
1246 #define PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_MASK (0x20U)
1247 #define PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_SHIFT (5U)
1248 #define PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_SHIFT) & PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_MASK)
1249 #define PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_MASK) >> PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_SHIFT)
1250 
1251 /*
1252  * EDGE_DECT_ENABLE (RW)
1253  *
1254  * edge detector enable.
1255  * 0: disable. bit6/bit5 setting inactive.
1256  * 1: enable. bit6/bit5 setting active.
1257  */
1258 #define PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_MASK (0x10U)
1259 #define PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_SHIFT (4U)
1260 #define PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_SHIFT) & PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_MASK)
1261 #define PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_MASK) >> PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_SHIFT)
1262 
1263 /*
1264  * FILTER_REVERSE (RW)
1265  *
1266  * reverse sync and edge detector filter's output.
1267  * 0: not reverse.
1268  * 1: reverse.
1269  */
1270 #define PLA_CHN_FILTER_3RD_FILTER_REVERSE_MASK (0x8U)
1271 #define PLA_CHN_FILTER_3RD_FILTER_REVERSE_SHIFT (3U)
1272 #define PLA_CHN_FILTER_3RD_FILTER_REVERSE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_FILTER_REVERSE_SHIFT) & PLA_CHN_FILTER_3RD_FILTER_REVERSE_MASK)
1273 #define PLA_CHN_FILTER_3RD_FILTER_REVERSE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_FILTER_REVERSE_MASK) >> PLA_CHN_FILTER_3RD_FILTER_REVERSE_SHIFT)
1274 
1275 /*
1276  * SOFTWARE_INJECT (RW)
1277  *
1278  * software inject value for sync and edge detector filter.
1279  * 0: inject low level.
1280  * 1: inject high level.
1281  * 2: not inject.
1282  * 3. inject high level.
1283  */
1284 #define PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_MASK (0x6U)
1285 #define PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_SHIFT (1U)
1286 #define PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_SHIFT) & PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_MASK)
1287 #define PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_MASK) >> PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_SHIFT)
1288 
1289 /*
1290  * SYNC_EDGE_FILTER_ENABLE (RW)
1291  *
1292  * sync and edge detector filter.
1293  * 0: disable.
1294  * 1: enable.
1295  */
1296 #define PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_MASK (0x1U)
1297 #define PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_SHIFT (0U)
1298 #define PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_SHIFT) & PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_MASK)
1299 #define PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_MASK) >> PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_SHIFT)
1300 
1301 /* Bitfield definition for register of struct array CHN: CFG_FF */
1302 /*
1303  * OSC_LOOP_CLAMP_VALUE (RW)
1304  *
1305  * osc loop clamp value when osc ring active.
1306  * 0: clamp 0.
1307  * 1: clamp 1.
1308  */
1309 #define PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_MASK (0x20000UL)
1310 #define PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_SHIFT (17U)
1311 #define PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_SET(x) (((uint32_t)(x) << PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_SHIFT) & PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_MASK)
1312 #define PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_GET(x) (((uint32_t)(x) & PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_MASK) >> PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_SHIFT)
1313 
1314 /*
1315  * DIS_OSC_LOOP_CLAMP (RW)
1316  *
1317  * disable osc loop clamp.
1318  * 0: enable osc loop clamp when osc ring active.
1319  * 1: disable or clean current osc loop clamp.
1320  */
1321 #define PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_MASK (0x10000UL)
1322 #define PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_SHIFT (16U)
1323 #define PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_SET(x) (((uint32_t)(x) << PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_SHIFT) & PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_MASK)
1324 #define PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_GET(x) (((uint32_t)(x) & PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_MASK) >> PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_SHIFT)
1325 
1326 /*
1327  * SEL_ADDER_MINUS (RW)
1328  *
1329  * 0: select adder when cfg_adder_minus active.
1330  * 1: select minus when cfg_adder_minus active.
1331  */
1332 #define PLA_CHN_CFG_FF_SEL_ADDER_MINUS_MASK (0x10U)
1333 #define PLA_CHN_CFG_FF_SEL_ADDER_MINUS_SHIFT (4U)
1334 #define PLA_CHN_CFG_FF_SEL_ADDER_MINUS_SET(x) (((uint32_t)(x) << PLA_CHN_CFG_FF_SEL_ADDER_MINUS_SHIFT) & PLA_CHN_CFG_FF_SEL_ADDER_MINUS_MASK)
1335 #define PLA_CHN_CFG_FF_SEL_ADDER_MINUS_GET(x) (((uint32_t)(x) & PLA_CHN_CFG_FF_SEL_ADDER_MINUS_MASK) >> PLA_CHN_CFG_FF_SEL_ADDER_MINUS_SHIFT)
1336 
1337 /*
1338  * SEL_CLK_SOURCE (RW)
1339  *
1340  * cfg_ff clock source.
1341  * 0: system clock.
1342  * 1: use 3rd_filter_2 as clock.
1343  */
1344 #define PLA_CHN_CFG_FF_SEL_CLK_SOURCE_MASK (0x8U)
1345 #define PLA_CHN_CFG_FF_SEL_CLK_SOURCE_SHIFT (3U)
1346 #define PLA_CHN_CFG_FF_SEL_CLK_SOURCE_SET(x) (((uint32_t)(x) << PLA_CHN_CFG_FF_SEL_CLK_SOURCE_SHIFT) & PLA_CHN_CFG_FF_SEL_CLK_SOURCE_MASK)
1347 #define PLA_CHN_CFG_FF_SEL_CLK_SOURCE_GET(x) (((uint32_t)(x) & PLA_CHN_CFG_FF_SEL_CLK_SOURCE_MASK) >> PLA_CHN_CFG_FF_SEL_CLK_SOURCE_SHIFT)
1348 
1349 /*
1350  * SEL_CFG_FF_TYPE (RW)
1351  *
1352  * cfg_ff type.
1353  * 0: DFF.
1354  * 1: 3rd_filter_0.
1355  * 2: dual-edge DFF.
1356  * 3: Trigger FF.
1357  * 4: JK FF.
1358  * 5. latch.
1359  * 6: full adder/minus.
1360  */
1361 #define PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_MASK (0x7U)
1362 #define PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_SHIFT (0U)
1363 #define PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_SET(x) (((uint32_t)(x) << PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_SHIFT) & PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_MASK)
1364 #define PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_GET(x) (((uint32_t)(x) & PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_MASK) >> PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_SHIFT)
1365 
1366 /* Bitfield definition for register array: FILTER_1ST_PLA_IN */
1367 /*
1368  * FILTER_EXT_COUNTER (RW)
1369  *
1370  * filter_ext counter value, cycles for filter or extent by system clock。
1371  * 0：0*apb_clk_period
1372  * 1：1*apb_clk_period
1373  * 2: 2*apb_clk_period
1374  * …
1375  * 65535: 65535*apb_clk_period
1376  */
1377 #define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_MASK (0xFFFF0000UL)
1378 #define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_SHIFT (16U)
1379 #define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_SHIFT) & PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_MASK)
1380 #define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_MASK) >> PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_SHIFT)
1381 
1382 /*
1383  * FILTER_EXT_TYPE (RW)
1384  *
1385  * filter extend type.
1386  * 0-3：nothing to do.
1387  * 4： input high level extend.
1388  * 5： input low level extend.
1389  * 6： output extend.
1390  * 7： input pulse extend.
1391  */
1392 #define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_MASK (0x7000U)
1393 #define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_SHIFT (12U)
1394 #define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_SHIFT) & PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_MASK)
1395 #define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_MASK) >> PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_SHIFT)
1396 
1397 /*
1398  * FILTER_EXT_ENABLE (RW)
1399  *
1400  * filter extend enable.
1401  * 0. bypass filter extend. all setting in bit31:12 are inactive
1402  * 1. enable filter extend, all setting in bit31:12 are active.
1403  */
1404 #define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_MASK (0x100U)
1405 #define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_SHIFT (8U)
1406 #define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_MASK)
1407 #define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_SHIFT)
1408 
1409 /*
1410  * FILTER_SYNC_LEVEL (RW)
1411  *
1412  * synchroniser level.
1413  * 0: 2 level sync.
1414  * 1: 3 level sync
1415  */
1416 #define PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_MASK (0x80U)
1417 #define PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_SHIFT (7U)
1418 #define PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_SHIFT) & PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_MASK)
1419 #define PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_MASK) >> PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_SHIFT)
1420 
1421 /*
1422  * POSE_EDGE_DECT_ENABLE (RW)
1423  *
1424  * pose edge detector enable.
1425  * 0: disable.
1426  * 1: enable.
1427  */
1428 #define PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_MASK (0x40U)
1429 #define PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_SHIFT (6U)
1430 #define PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_MASK)
1431 #define PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_SHIFT)
1432 
1433 /*
1434  * NEGE_EDGE_DECT_ENABLE (RW)
1435  *
1436  * nege edge detector enable.
1437  * 0: disable.
1438  * 1: enable.
1439  */
1440 #define PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_MASK (0x20U)
1441 #define PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_SHIFT (5U)
1442 #define PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_MASK)
1443 #define PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_SHIFT)
1444 
1445 /*
1446  * EDGE_DECT_ENABLE (RW)
1447  *
1448  * edge detector enable.
1449  * 0: disable. bit6/bit5 setting inactive.
1450  * 1: enable. bit6/bit5 setting active.
1451  */
1452 #define PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_MASK (0x10U)
1453 #define PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_SHIFT (4U)
1454 #define PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_MASK)
1455 #define PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_SHIFT)
1456 
1457 /*
1458  * FILTER_REVERSE (RW)
1459  *
1460  * reverse sync and edge detector filter's output.
1461  * 0: not reverse.
1462  * 1: reverse.
1463  */
1464 #define PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_MASK (0x8U)
1465 #define PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_SHIFT (3U)
1466 #define PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_SHIFT) & PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_MASK)
1467 #define PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_MASK) >> PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_SHIFT)
1468 
1469 /*
1470  * SOFTWARE_INJECT (RW)
1471  *
1472  * software inject value for sync and edge detector filter.
1473  * 0: inject low level.
1474  * 1: inject high level.
1475  * 2: not inject.
1476  * 3. inject high level.
1477  */
1478 #define PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_MASK (0x6U)
1479 #define PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_SHIFT (1U)
1480 #define PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_SHIFT) & PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_MASK)
1481 #define PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_MASK) >> PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_SHIFT)
1482 
1483 /*
1484  * SYNC_EDGE_FILTER_ENABLE (RW)
1485  *
1486  * sync and edge detector filter.
1487  * 0: disable.
1488  * 1: enable.
1489  */
1490 #define PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_MASK (0x1U)
1491 #define PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_SHIFT (0U)
1492 #define PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_MASK)
1493 #define PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_SHIFT)
1494 
1495 /* Bitfield definition for register array: FILTER_1ST_PLA_OUT */
1496 /*
1497  * FILTER_EXT_COUNTER (RW)
1498  *
1499  * filter_ext counter value, cycles for filter or extent by system clock。
1500  * 0：0*apb_clk_period
1501  * 1：1*apb_clk_period
1502  * 2: 2*apb_clk_period
1503  * …
1504  * 65535: 65535*apb_clk_period
1505  */
1506 #define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_MASK (0xFFFF0000UL)
1507 #define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_SHIFT (16U)
1508 #define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_SHIFT) & PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_MASK)
1509 #define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_MASK) >> PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_SHIFT)
1510 
1511 /*
1512  * FILTER_EXT_TYPE (RW)
1513  *
1514  * filter extend type.
1515  * 0-3：nothing to do.
1516  * 4： input high level extend.
1517  * 5： input low level extend.
1518  * 6： output extend.
1519  * 7： input pulse extend.
1520  */
1521 #define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_MASK (0x7000U)
1522 #define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_SHIFT (12U)
1523 #define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_MASK)
1524 #define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_MASK) >> PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_SHIFT)
1525 
1526 /*
1527  * FILTER_EXT_ENABLE (RW)
1528  *
1529  * filter extend enable.
1530  * 0. bypass filter extend. all setting in bit31:12 are inactive
1531  * 1. enable filter extend, all setting in bit31:12 are active.
1532  */
1533 #define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_MASK (0x100U)
1534 #define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_SHIFT (8U)
1535 #define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_MASK)
1536 #define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_SHIFT)
1537 
1538 /*
1539  * FILTER_SYNC_LEVEL (RW)
1540  *
1541  * synchroniser level.
1542  * 0: 2 level sync.
1543  * 1: 3 level sync
1544  */
1545 #define PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_MASK (0x80U)
1546 #define PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_SHIFT (7U)
1547 #define PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_SHIFT) & PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_MASK)
1548 #define PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_MASK) >> PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_SHIFT)
1549 
1550 /*
1551  * POSE_EDGE_DECT_ENABLE (RW)
1552  *
1553  * pose edge detector enable.
1554  * 0: disable.
1555  * 1: enable.
1556  */
1557 #define PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_MASK (0x40U)
1558 #define PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_SHIFT (6U)
1559 #define PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_MASK)
1560 #define PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_SHIFT)
1561 
1562 /*
1563  * NEGE_EDGE_DECT_ENABLE (RW)
1564  *
1565  * nege edge detector enable.
1566  * 0: disable.
1567  * 1: enable.
1568  */
1569 #define PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_MASK (0x20U)
1570 #define PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_SHIFT (5U)
1571 #define PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_MASK)
1572 #define PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_SHIFT)
1573 
1574 /*
1575  * EDGE_DECT_ENABLE (RW)
1576  *
1577  * edge detector enable.
1578  * 0: disable. bit6/bit5 setting inactive.
1579  * 1: enable. bit6/bit5 setting active.
1580  */
1581 #define PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_MASK (0x10U)
1582 #define PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_SHIFT (4U)
1583 #define PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_MASK)
1584 #define PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_SHIFT)
1585 
1586 /*
1587  * FILTER_REVERSE (RW)
1588  *
1589  * reverse sync and edge detector filter's output.
1590  * 0: not reverse.
1591  * 1: reverse.
1592  */
1593 #define PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_MASK (0x8U)
1594 #define PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_SHIFT (3U)
1595 #define PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_MASK)
1596 #define PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_MASK) >> PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_SHIFT)
1597 
1598 /*
1599  * SOFTWARE_INJECT (RW)
1600  *
1601  * software inject value for sync and edge detector filter.
1602  * 0: inject low level.
1603  * 1: inject high level.
1604  * 2: not inject.
1605  * 3. inject high level.
1606  */
1607 #define PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_MASK (0x6U)
1608 #define PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_SHIFT (1U)
1609 #define PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_SHIFT) & PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_MASK)
1610 #define PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_MASK) >> PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_SHIFT)
1611 
1612 /*
1613  * SYNC_EDGE_FILTER_ENABLE (RW)
1614  *
1615  * sync and edge detector filter.
1616  * 0: disable.
1617  * 1: enable.
1618  */
1619 #define PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_MASK (0x1U)
1620 #define PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_SHIFT (0U)
1621 #define PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_MASK)
1622 #define PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_SHIFT)
1623 
1624 /* Bitfield definition for register array: CHN_CFG_ACTIVE */
1625 /*
1626  * CFG_ACTIVE (RW)
1627  *
1628  * write 0xF00D to enable all setting. Otherwire, all setting inactive.
1629  */
1630 #define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_MASK (0xFFFFU)
1631 #define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_SHIFT (0U)
1632 #define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_SET(x) (((uint32_t)(x) << PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_SHIFT) & PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_MASK)
1633 #define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_GET(x) (((uint32_t)(x) & PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_MASK) >> PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_SHIFT)
1634 
1635 
1636 
1637 /* AOI_16TO8 register group index macro definition */
1638 #define PLA_CHN_AOI_16TO8_AOI_16TO8_00 (0UL)
1639 #define PLA_CHN_AOI_16TO8_AOI_16TO8_01 (1UL)
1640 #define PLA_CHN_AOI_16TO8_AOI_16TO8_02 (2UL)
1641 #define PLA_CHN_AOI_16TO8_AOI_16TO8_03 (3UL)
1642 #define PLA_CHN_AOI_16TO8_AOI_16TO8_04 (4UL)
1643 #define PLA_CHN_AOI_16TO8_AOI_16TO8_05 (5UL)
1644 #define PLA_CHN_AOI_16TO8_AOI_16TO8_06 (6UL)
1645 #define PLA_CHN_AOI_16TO8_AOI_16TO8_07 (7UL)
1646 
1647 /* FILTER_2ND register group index macro definition */
1648 #define PLA_CHN_FILTER_2ND_SECOND_FILTER_0 (0UL)
1649 #define PLA_CHN_FILTER_2ND_SECOND_FILTER_1 (1UL)
1650 #define PLA_CHN_FILTER_2ND_SECOND_FILTER_2 (2UL)
1651 #define PLA_CHN_FILTER_2ND_SECOND_FILTER_3 (3UL)
1652 #define PLA_CHN_FILTER_2ND_SECOND_FILTER_4 (4UL)
1653 #define PLA_CHN_FILTER_2ND_SECOND_FILTER_5 (5UL)
1654 #define PLA_CHN_FILTER_2ND_SECOND_FILTER_6 (6UL)
1655 #define PLA_CHN_FILTER_2ND_SECOND_FILTER_7 (7UL)
1656 
1657 /* FILTER_3RD register group index macro definition */
1658 #define PLA_CHN_FILTER_3RD_THIRD_FILTER_0 (0UL)
1659 #define PLA_CHN_FILTER_3RD_THIRD_FILTER_1 (1UL)
1660 #define PLA_CHN_FILTER_3RD_THIRD_FILTER_2 (2UL)
1661 #define PLA_CHN_FILTER_3RD_THIRD_FILTER_3 (3UL)
1662 #define PLA_CHN_FILTER_3RD_THIRD_FILTER_4 (4UL)
1663 #define PLA_CHN_FILTER_3RD_THIRD_FILTER_5 (5UL)
1664 #define PLA_CHN_FILTER_3RD_THIRD_FILTER_6 (6UL)
1665 
1666 /* CHN register group index macro definition */
1667 #define PLA_CHN_0 (0UL)
1668 #define PLA_CHN_1 (1UL)
1669 #define PLA_CHN_2 (2UL)
1670 #define PLA_CHN_3 (3UL)
1671 #define PLA_CHN_4 (4UL)
1672 #define PLA_CHN_5 (5UL)
1673 #define PLA_CHN_6 (6UL)
1674 #define PLA_CHN_7 (7UL)
1675 
1676 /* FILTER_1ST_PLA_IN register group index macro definition */
1677 #define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_0 (0UL)
1678 #define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_1 (1UL)
1679 #define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_2 (2UL)
1680 #define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_3 (3UL)
1681 #define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_4 (4UL)
1682 #define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_5 (5UL)
1683 #define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_6 (6UL)
1684 #define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_7 (7UL)
1685 
1686 /* FILTER_1ST_PLA_OUT register group index macro definition */
1687 #define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_IN_0 (0UL)
1688 #define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_0 (0UL)
1689 #define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_1 (1UL)
1690 #define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_2 (2UL)
1691 #define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_3 (3UL)
1692 #define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_4 (4UL)
1693 #define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_5 (5UL)
1694 #define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_6 (6UL)
1695 #define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_7 (7UL)
1696 
1697 /* CHN_CFG_ACTIVE register group index macro definition */
1698 #define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN0 (0UL)
1699 #define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN1 (1UL)
1700 #define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN2 (2UL)
1701 #define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN3 (3UL)
1702 #define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN4 (4UL)
1703 #define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN5 (5UL)
1704 #define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN6 (6UL)
1705 #define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN7 (7UL)
1706 
1707 
1708 #endif /* HPM_PLA_H */
PLA_Type
Definition: hpm_pla_regs.h:12