58 #if defined(__cplusplus)
80 #if defined(__cplusplus)
ppi_port_size_t
port size
Definition: hpm_ppi_drv.h:79
ppi_dq_pins_t
ppi dq pins enum
Definition: hpm_ppi.h:21
@ ppi_dq_pins_24_31
Definition: hpm_ppi.h:25
@ ppi_dq_pins_8_15
Definition: hpm_ppi.h:23
@ ppi_dq_pins_16_23
Definition: hpm_ppi.h:24
@ ppi_dq_pins_0_7
Definition: hpm_ppi.h:22
void ppi_config_async_sram(PPI_Type *ppi, uint8_t cs_index, uint8_t cmd_start_index, ppi_async_sram_config_t *config)
config async sram
Definition: hpm_ppi.c:43
void ppi_get_async_sram_defconfig(PPI_Type *ppi, ppi_async_sram_config_t *config)
get async sram default config
Definition: hpm_ppi.c:17
Definition: hpm_ppi_regs.h:12
ppi async sram config structure
Definition: hpm_ppi.h:32
uint32_t size_in_byte
Definition: hpm_ppi.h:34
uint16_t ah_in_ns
Definition: hpm_ppi.h:44
ppi_port_size_t port_size
Definition: hpm_ppi.h:35
uint8_t rel_ctrl_pin
Definition: hpm_ppi.h:41
uint16_t rel_in_ns
Definition: hpm_ppi.h:45
bool cs_valid_polarity
Definition: hpm_ppi.h:37
bool dm_valid_polarity
Definition: hpm_ppi.h:38
uint16_t reh_in_ns
Definition: hpm_ppi.h:46
uint8_t adv_ctrl_pin
Definition: hpm_ppi.h:40
uint16_t weh_in_ns
Definition: hpm_ppi.h:48
uint32_t base_address
Definition: hpm_ppi.h:33
uint8_t wel_ctrl_pin
Definition: hpm_ppi.h:42
bool ad_mux_mode
Definition: hpm_ppi.h:36
uint16_t wel_in_ns
Definition: hpm_ppi.h:47
bool addr_valid_polarity
Definition: hpm_ppi.h:39
uint16_t as_in_ns
Definition: hpm_ppi.h:43