hpm_ptpc_drv.h

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/*
 * Copyright (c) 2021 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
 */
 
#ifndef HPM_PTPC_DRV_H
#define HPM_PTPC_DRV_H
 
#include "hpm_common.h"
#include "hpm_ptpc_regs.h"
 
#define PTPC_EVENT_COMPARE0_MASK    PTPC_INT_STS_COMP_INT_STS0_MASK
#define PTPC_EVENT_CAPTURE0_MASK    PTPC_INT_STS_CAPTURE_INT_STS0_MASK
#define PTPC_EVENT_PPS0_MASK        PTPC_INT_STS_PPS_INT_STS0_MASK
#define PTPC_EVENT_COMPARE1_MASK    PTPC_INT_STS_COMP_INT_STS1_MASK
#define PTPC_EVENT_CAPTURE1_MASK    PTPC_INT_STS_CAPTURE_INT_STS1_MASK
#define PTPC_EVENT_PPS1_MASK        PTPC_INT_STS_PPS_INT_STS1_MASK
 
#define PTPC_MAX_NS_COUNTER (0x3B9ACA00UL)
 
typedef enum ptpc_ns_counter_rollover_type {
    ptpc_ns_counter_rollover_binary = 0, 
    ptpc_ns_counter_rollover_digital = 1, 
} ptpc_ns_counter_rollover_type_t;
 
typedef enum ptpc_capture_trigger_type {
    ptpc_capture_trigger_none = 0,
    ptpc_capture_trigger_on_rising_edge = PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK,
    ptpc_capture_trigger_on_failing_edge = PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK,
    ptpc_capture_trigger_on_both_edges = PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK
                                        | PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK,
} ptpc_capture_trigger_type_t;
 
typedef enum ptpc_counting_mode {
    ptpc_counting_increment = 0,            
    ptpc_counting_decrement = 1,            
} ptpc_counting_mode;
 
typedef struct {
    ptpc_capture_trigger_type_t capture_trigger;        
    ptpc_ns_counter_rollover_type_t ns_rollover_mode;   
    bool coarse_increment;                              
    bool capture_keep;                                  
    uint32_t src_frequency;                             
} ptpc_config_t;
 
#ifdef __cplusplus
extern "C" {
#endif
 
static inline void ptpc_set_ns_counter_rollover(PTPC_Type *ptr, uint8_t index,
                                ptpc_ns_counter_rollover_type_t rollover)
{
    ptr->PTPC[index].CTRL0 = (ptr->PTPC[index].CTRL0 & ~PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_MASK)
        | PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SET(rollover);
}
 
static inline void ptpc_enable_capture_keep(PTPC_Type *ptr, uint8_t index)
{
    ptr->PTPC[index].CTRL0 |= PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK;
}
 
static inline void ptpc_disable_capture_keep(PTPC_Type *ptr, uint8_t index)
{
    ptr->PTPC[index].CTRL0 &= ~PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK;
}
 
static inline void ptpc_set_ns_counter_update_type(PTPC_Type *ptr, uint8_t index, bool coarse_update)
{
    ptr->PTPC[index].CTRL0 = (ptr->PTPC[index].CTRL0 & ~PTPC_PTPC_CTRL0_FINE_COARSE_SEL_MASK)
        | PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SET(coarse_update);
}
 
static inline void ptpc_set_ns_counter_step(PTPC_Type *ptr, uint8_t index, uint32_t ns_step)
{
    ptr->PTPC[index].CTRL1 = PTPC_PTPC_CTRL1_SS_INCR_SET(ns_step);
}
 
static inline void ptpc_set_second_update(PTPC_Type *ptr, uint8_t index, uint32_t sec)
{
    ptr->PTPC[index].TS_UPDTH = PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SET(sec);
}
 
hpm_stat_t ptpc_set_ns_update(PTPC_Type *ptr, uint8_t index, uint32_t ns, ptpc_counting_mode mode);
 
static inline uint32_t ptpc_get_timestamp_second(PTPC_Type *ptr, uint8_t index)
{
    return PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_GET(ptr->PTPC[index].TIMEH);
}
 
static inline uint32_t ptpc_get_timestamp_ns(PTPC_Type *ptr, uint8_t index)
{
    return PTPC_PTPC_TIMEL_TIMESTAMP_LOW_GET(ptr->PTPC[index].TIMEL);
}
 
static inline void ptpc_config_compare(PTPC_Type *ptr, uint8_t index, uint32_t sec, uint32_t ns)
{
    ptr->PTPC[index].TARH = PTPC_PTPC_TARH_TARGET_TIME_HIGH_SET(sec);
    ptr->PTPC[index].TARL = PTPC_PTPC_TARL_TARGET_TIME_LOW_SET(ns);
    ptr->PTPC[index].CTRL0 |= PTPC_PTPC_CTRL0_COMP_EN_MASK;
}
 
static inline void ptpc_update_timestamp_second(PTPC_Type *ptr, uint8_t index, uint32_t sec)
{
    ptr->PTPC[index].TS_UPDTH = PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SET(sec);
}
 
static inline void ptpc_update_timestamp_ns(PTPC_Type *ptr, uint8_t index, uint32_t ns, ptpc_counting_mode mode)
{
    ptr->PTPC[index].TS_UPDTL = PTPC_PTPC_TS_UPDTL_NS_UPDATE_SET(ns) | PTPC_PTPC_TS_UPDTL_ADD_SUB_SET(mode);
}
 
static inline void ptpc_enable_timer(PTPC_Type *ptr, uint8_t index)
{
    ptr->PTPC[index].CTRL0 |= PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK;
}
 
static inline void ptpc_disable_timer(PTPC_Type *ptr, uint8_t index)
{
    ptr->PTPC[index].CTRL0 &= ~PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK;
}
 
static inline void ptpc_config_capture(PTPC_Type *ptr, uint8_t index,
                                ptpc_capture_trigger_type_t trigger)
{
    ptr->PTPC[index].CTRL0 = (ptr->PTPC[index].CTRL0 & ~(PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK
                | PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK)) | trigger;
}
 
static inline uint32_t ptpc_get_capture_ns(PTPC_Type *ptr, uint8_t index)
{
    return PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_GET(ptr->PTPC[index].CAPT_SNAPL);
}
 
static inline uint32_t ptpc_get_capture_second(PTPC_Type *ptr, uint8_t index)
{
    return PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_GET(ptr->PTPC[index].CAPT_SNAPH);
}
 
static inline void ptpc_clear_irq_status(PTPC_Type *ptr, uint32_t mask)
{
    ptr->INT_STS = mask;
}
 
static inline uint32_t ptpc_get_irq_status(PTPC_Type *ptr)
{
    return ptr->INT_STS;
}
 
static inline void ptpc_irq_disable(PTPC_Type *ptr, uint32_t mask)
{
    ptr->INT_EN &= ~mask;
}
 
static inline void ptpc_irq_enable(PTPC_Type *ptr, uint32_t mask)
{
    ptr->INT_EN |= mask;
}
 
hpm_stat_t ptpc_init(PTPC_Type *ptr, uint8_t index, ptpc_config_t *config);
 
hpm_stat_t ptpc_set_timer_output(PTPC_Type *ptr, uint8_t can_index, bool use_ptpc1);
 
void ptpc_get_default_config(PTPC_Type *ptr, ptpc_config_t *config);
 
void ptpc_init_timer(PTPC_Type *ptr, uint8_t index);
 
hpm_stat_t ptpc_init_timer_with_initial(PTPC_Type *ptr, uint8_t index, uint32_t sec, uint32_t ns, ptpc_counting_mode mode);
 
hpm_stat_t ptpc_update_timer(PTPC_Type *ptr, uint8_t index, uint32_t sec, uint32_t ns, ptpc_counting_mode mode);
 
hpm_stat_t ptpc_set_pps(PTPC_Type *ptr, uint8_t index, uint8_t p);
 
#ifdef __cplusplus
}
#endif
#endif /* HPM_PTPC_DRV_H */