hpm_qeov2_drv.h

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/*
 * Copyright (c) 2023 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
 */
 
#ifndef HPM_QEOV2_DRV_H
#define HPM_QEOV2_DRV_H
 
#include "hpm_common.h"
#include "hpm_qeov2_regs.h"
typedef enum {
    qeo_wave_cosine = 0,
    qeo_wave_saddle = 1,
    qeo_wave_abs_cosine = 2,
    qeo_wave_saw = 3,
} qeo_wave_type_t;
 
typedef enum {
    qeo_saddle_standard = 0,
    qeo_saddle_triple
} qeo_saddle_type_t;
 
typedef enum {
    qeo_wave_above_max_limit_max_val = 0,
    qeo_wave_above_max_limit_zero = 1,
    qeo_wave_above_max_limit_max_level0_val = 2,
 
    qeo_wave_high_area_limit_max_val = 0,
    qeo_wave_high_area_limit_max_level0_val = 1,
 
    qeo_wave_low_area_limit_zero = 0,
    qeo_wave_low_area_limit_min_level1_val = 1,
 
    qeo_wave_below_min_limit_zero = 0,
    qeo_wave_below_min_limit_max_val = 1,
    qeo_wave_below_min_limit_min_level1_val = 2,
} qeo_wave_limit_t;
 
typedef struct {
    qeo_wave_limit_t above_max_limit;
    qeo_wave_limit_t high_area0_limit;
    qeo_wave_limit_t high_area1_limit;
    qeo_wave_limit_t low_area0_limit;
    qeo_wave_limit_t low_area1_limit;
    qeo_wave_limit_t below_min_limit;
} qeo_wave_limit_config_t;
 
typedef struct {
    qeo_wave_limit_config_t wave0;
    qeo_wave_limit_config_t wave1;
    qeo_wave_limit_config_t wave2;
    bool dq_valid_trig_enable; 
    bool pos_valid_trig_enable; 
    bool vd_vq_inject_enable;
    bool vd_vq_from_sw; 
    qeo_wave_type_t wave_type;
    qeo_saddle_type_t saddle_type;
} qeo_wave_mode_t;
 
typedef enum {
    qeo_abz_output_abz = 0, 
    qeo_abz_output_pulse_revise = 1, 
    qeo_abz_output_up_down = 2, 
    qeo_abz_output_three_phase = 3, 
} qeo_abz_type_t;
 
typedef enum {
    qeo_z_as_zero_signal_mode0 = 0,
    qeo_z_as_zero_signal_mode1 = 1,
    qeo_z_as_no_output_signal = 2,
    qeo_z_as_third_phase_signal = 3,
} qeo_z_pulse_type_t;
 
typedef struct {
    bool z_inv_pol;
    bool b_inv_pol;
    bool a_inv_pol;
    bool enable_wdog;
    bool sync_step_position;
    bool reverse_align_clk_falling_edge;
    qeo_abz_type_t output_type; 
} qeo_abz_mode_t;
 
typedef struct {
    uint8_t type;
    uint32_t start_line;
    uint32_t end_line;
    uint8_t  start_step;
    uint8_t  end_step;
    uint32_t width;
} qeo_z_output_mode_t;
 
typedef enum {
    qeo_pwm_output_force_0 = 2,
    qeo_pwm_output_force_1 = 3,
    qeo_pwm_output_not_force = 0,
} qeo_pwm_force_output_t;
 
typedef enum {
    qeo_pwm_safety_output_0 = 0,
    qeo_pwm_safety_output_1 = 1,
    qeo_pwm_safety_output_highz = 2,
} qeo_pwm_safety_output_t;
 
typedef struct {
    qeo_pwm_force_output_t pwm0_output; 
    qeo_pwm_force_output_t pwm1_output;
    qeo_pwm_force_output_t pwm2_output;
    qeo_pwm_force_output_t pwm3_output;
    qeo_pwm_force_output_t pwm4_output;
    qeo_pwm_force_output_t pwm5_output;
    qeo_pwm_force_output_t pwm6_output;
    qeo_pwm_force_output_t pwm7_output;
} qeo_pwm_phase_output_table_t;
 
typedef struct {
    qeo_pwm_safety_output_t pwm0_output; 
    qeo_pwm_safety_output_t pwm1_output;
    qeo_pwm_safety_output_t pwm2_output;
    qeo_pwm_safety_output_t pwm3_output;
    qeo_pwm_safety_output_t pwm4_output;
    qeo_pwm_safety_output_t pwm5_output;
    qeo_pwm_safety_output_t pwm6_output;
    qeo_pwm_safety_output_t pwm7_output;
} qeo_pwm_safety_output_table_t;
 
typedef struct {
    uint8_t phase_num;
    bool shield_hardware_trig_safety;
    bool revise_pairs_output;
} qeo_pwm_mode_t;
 
#ifdef __cplusplus
extern "C" {
#endif
 
/* WAVE API */
static inline void qeo_wave_set_resolution_lines(QEOV2_Type *base, uint32_t lines)
{
    base->WAVE.RESOLUTION = QEOV2_WAVE_RESOLUTION_LINES_SET(lines);
}
 
static inline void qeo_wave_set_output_type(QEOV2_Type *base, qeo_wave_type_t type)
{
    base->WAVE.MODE = (base->WAVE.MODE & ~QEOV2_WAVE_MODE_WAVES_OUTPUT_TYPE_MASK) | QEOV2_WAVE_MODE_WAVES_OUTPUT_TYPE_SET(type);
}
 
static inline void qeo_wave_set_saddle_type(QEOV2_Type *base, bool standard)
{
    if (standard) {
        base->WAVE.MODE &= ~QEOV2_WAVE_MODE_SADDLE_TYPE_MASK;
    } else {
        base->WAVE.MODE |= QEOV2_WAVE_MODE_SADDLE_TYPE_MASK;
    }
}
 
static inline void qeo_wave_set_phase_shift(QEOV2_Type *base, uint8_t index, double angle)
{
    assert((angle >= 0) && (angle <= 360));
    uint32_t val = (uint32_t)(angle * 0x100000000UL / 360);
    base->WAVE.PHASE_SHIFT[index] = QEOV2_WAVE_PHASE_SHIFT_VAL_SET(val);
}
 
static inline void qeo_wave_enable_vd_vq_inject(QEOV2_Type *base, bool from_sw)
{
    if (from_sw) {
        base->WAVE.MODE |= QEOV2_WAVE_MODE_VD_VQ_SEL_MASK;
    } else {
        base->WAVE.MODE &= ~QEOV2_WAVE_MODE_VD_VQ_SEL_MASK;
    }
    base->WAVE.MODE |= QEOV2_WAVE_MODE_EN_WAVE_VD_VQ_INJECT_MASK;
}
 
static inline void qeo_wave_disable_vd_vq_inject(QEOV2_Type *base)
{
    base->WAVE.MODE &= ~QEOV2_WAVE_MODE_EN_WAVE_VD_VQ_INJECT_MASK;
}
 
static inline void qeo_wave_config_vd_vq_value(QEOV2_Type *base, int32_t vd_val, int32_t vq_val)
{
    base->WAVE.VD_INJECT = QEOV2_WAVE_VD_INJECT_VD_VAL_SET(vd_val);
    base->WAVE.VQ_INJECT = QEOV2_WAVE_VQ_INJECT_VQ_VAL_SET(vq_val);
}
 
static inline void qeo_wave_load_vd_vq(QEOV2_Type *base)
{
    base->WAVE.VD_VQ_LOAD = QEOV2_WAVE_VD_VQ_LOAD_LOAD_MASK;
}
 
static inline void qeo_wave_enable_amplitude(QEOV2_Type *base, uint8_t index, double amp)
{
    assert(amp > 0);
    uint32_t val = (uint32_t)(amp * (1U << 12U));
    base->WAVE.AMPLITUDE[index] = QEOV2_WAVE_AMPLITUDE_EN_SCAL_MASK | QEOV2_WAVE_AMPLITUDE_AMP_VAL_SET(val);
}
 
static inline void qeo_wave_disable_amplitude(QEOV2_Type *base, uint8_t index)
{
    base->WAVE.AMPLITUDE[index] &= ~QEOV2_WAVE_AMPLITUDE_EN_SCAL_MASK;
}
 
static inline void qeo_wave_set_mid_point_shift(QEOV2_Type *base, uint8_t index, double shift)
{
    int32_t val = (int32_t)(shift * (1U << 27U));
    base->WAVE.MID_POINT[index] = QEOV2_WAVE_MID_POINT_VAL_SET(val);
}
 
static inline void qeo_wave_set_max_limit(QEOV2_Type *base, uint8_t index, uint32_t limit0, uint32_t limit1)
{
    base->WAVE.LIMIT0[index].MAX_LEVEL0 = QEOV2_WAVE_LIMIT0_MAX_LEVEL0_LIMIT_LEVEL0_SET(limit0);
    base->WAVE.LIMIT1[index].MAX_LEVEL1 = QEOV2_WAVE_LIMIT1_MAX_LEVEL1_LIMIT_LEVEL1_SET(limit1);
}
 
static inline void qeo_wave_set_min_limit(QEOV2_Type *base, uint8_t index, uint32_t limit0, uint32_t limit1)
{
    base->WAVE.LIMIT0[index].MIN_LEVEL0 = QEOV2_WAVE_LIMIT0_MIN_LEVEL0_LIMIT_LEVEL0_SET(limit0);
    base->WAVE.LIMIT1[index].MIN_LEVEL1 = QEOV2_WAVE_LIMIT1_MIN_LEVEL1_LIMIT_LEVEL1_SET(limit1);
}
 
static inline void qeo_wave_set_deadzone_shift(QEOV2_Type *base, uint8_t index, int32_t shift)
{
    base->WAVE.DEADZONE_SHIFT[index] = QEOV2_WAVE_DEADZONE_SHIFT_VAL_SET(shift);
}
 
static inline void qeo_wave_set_pwm_cycle(QEOV2_Type *base, uint32_t cycle)
{
    base->WAVE.PWM_CYCLE = QEOV2_WAVE_PWM_CYCLE_VAL_SET(cycle);
}
 
static inline uint32_t qeo_get_wave_output_val(QEOV2_Type *base, uint8_t index)
{
    if (index == 0) {
        return QEOV2_DEBUG0_VALUE_DAC0_GET(base->DEBUG0);
    } else if (index == 1) {
        return QEOV2_DEBUG4_VALUE_DAC1_GET(base->DEBUG4);
    } else if (index  == 2) {
        return QEOV2_DEBUG5_VALUE_DAC2_GET(base->DEBUG5);
    }
    return 0;
}
 
void qeo_wave_get_default_mode_config(QEOV2_Type *base, qeo_wave_mode_t *config);
 
void qeo_wave_config_mode(QEOV2_Type *base, qeo_wave_mode_t *config);
 
/* ABZ API */
static inline void qeo_abz_set_resolution_lines(QEOV2_Type *base, uint32_t lines)
{
    base->ABZ.RESOLUTION = QEOV2_ABZ_RESOLUTION_LINES_SET(lines);
}
 
static inline void qeo_abz_set_phase_shift(QEOV2_Type *base, uint8_t index, double angle)
{
    assert((angle >= 0) && (angle <= 360));
    uint32_t val = (uint32_t)(angle * 0x100000000U / 360);
    base->ABZ.PHASE_SHIFT[index] = QEOV2_ABZ_PHASE_SHIFT_VAL_SET(val);
}
 
static inline void qeo_abz_set_offset(QEOV2_Type *base, double physical_angle)
{
    assert((physical_angle >= 0) && (physical_angle <= 360));
    uint32_t val = (uint32_t)(physical_angle * 0x100000000U / 360);
    base->ABZ.OVERALL_OFFSET = QEOV2_ABZ_OVERALL_OFFSET_VAL_SET(val);
}
 
hpm_stat_t qeo_abz_set_max_frequency(QEOV2_Type *base, uint32_t src_freq, uint32_t freq);
 
hpm_stat_t qeo_abz_set_wdog_frequency(QEOV2_Type *base, uint32_t src_freq, uint32_t freq);
 
static inline void qeo_abz_disable_wdog(QEOV2_Type *base)
{
    base->ABZ.MODE &= ~QEOV2_ABZ_MODE_EN_WDOG_MASK;
}
 
static inline void qeo_abz_config_reverse_edge(QEOV2_Type *base, bool speed_pulse_negedge)
{
    if (speed_pulse_negedge) {
        base->ABZ.MODE |= QEOV2_ABZ_MODE_REVERSE_EDGE_TYPE_MASK;
    } else {
        base->ABZ.MODE &= ~QEOV2_ABZ_MODE_REVERSE_EDGE_TYPE_MASK;
    }
}
 
void qeo_abz_get_default_mode_config(QEOV2_Type *base, qeo_abz_mode_t *config);
 
void qeo_abz_config_mode(QEOV2_Type *base, qeo_abz_mode_t *config);
 
static inline void qeo_abz_enable_output(QEOV2_Type *base)
{
    base->ABZ.MODE |= QEOV2_ABZ_MODE_ABZ_OUTPUT_ENABLE_MASK;
}
 
static inline void qeo_abz_disable_output(QEOV2_Type *base)
{
    base->ABZ.MODE &= ~QEOV2_ABZ_MODE_ABZ_OUTPUT_ENABLE_MASK;
}
 
static inline void qeo_abz_enable_position_sync(QEOV2_Type *base, bool sync_identical_pos)
{
    if (sync_identical_pos) {
        base->ABZ.MODE |= QEOV2_ABZ_MODE_POSITION_SYNC_MODE_MASK;
    } else {
        base->ABZ.MODE &= ~QEOV2_ABZ_MODE_POSITION_SYNC_MODE_MASK;
    }
 
    base->ABZ.POSTION_SYNC = QEOV2_ABZ_POSTION_SYNC_POSTION_MASK;
}
 
void qeo_abz_get_default_z_output_mode(QEOV2_Type *base, qeo_z_output_mode_t *mode);
 
void qeo_abz_config_z_output_mode(QEOV2_Type *base, qeo_z_output_mode_t *mode);
 
/* PWM API */
static inline void qeo_pwm_set_resolution_lines(QEOV2_Type *base, uint32_t lines)
{
    base->PWM.RESOLUTION = QEOV2_PWM_RESOLUTION_LINES_SET(lines);
}
 
static inline void qeo_pwm_set_phase_shift(QEOV2_Type *base, uint8_t index, double angle)
{
    assert((angle >= 0) && (angle <= 360));
    uint32_t val = (uint32_t)(angle * 0x1000010000U / 360);
    base->PWM.PHASE_SHIFT[index] = QEOV2_PWM_PHASE_SHIFT_VAL_SET(val);
}
 
static inline void qeo_pwm_enable_output(QEOV2_Type *base)
{
    base->PWM.MODE |= QEOV2_PWM_MODE_ENABLE_PWM_MASK;
}
 
static inline void qeo_pwm_disable_output(QEOV2_Type *base)
{
    base->PWM.MODE &= ~QEOV2_PWM_MODE_ENABLE_PWM_MASK;
}
 
static inline bool qeo_pwm_check_hardware_trig_safety(QEOV2_Type *base)
{
    return ((base->STATUS & QEOV2_STATUS_PWM_SAFETY_MASK) != 0) ? true : false;
}
 
static inline void qeo_pwm_select_phase_table(QEOV2_Type *base, bool positive)
{
    if (positive) {
        base->PWM.MODE &= ~QEOV2_PWM_MODE_REVISE_UP_DN_MASK;
    } else {
        base->PWM.MODE |= QEOV2_PWM_MODE_REVISE_UP_DN_MASK;
    }
}
 
static inline void qeo_pwm_software_enter_safety(QEOV2_Type *base)
{
    base->PWM.MODE |= QEOV2_PWM_MODE_PWM_ENTER_SAFETY_MODE_MASK;
}
 
static inline void qeo_pwm_software_exit_safety(QEOV2_Type *base)
{
    base->PWM.MODE &= ~QEOV2_PWM_MODE_PWM_ENTER_SAFETY_MODE_MASK;
}
 
void qeo_pwm_get_default_mode_config(QEOV2_Type *base, qeo_pwm_mode_t *config);
 
void qeo_pwm_config_mode(QEOV2_Type *base, qeo_pwm_mode_t *config);
 
void qeo_pwm_get_default_safety_table_config(QEOV2_Type *base, qeo_pwm_safety_output_table_t *table);
 
void qeo_pwm_get_default_phase_table_config(QEOV2_Type *base, qeo_pwm_phase_output_table_t *table);
 
void qeo_pwm_config_safety_table(QEOV2_Type *base, qeo_pwm_safety_output_table_t *table);
 
void qeo_pwm_config_phase_table(QEOV2_Type *base, uint8_t index, qeo_pwm_phase_output_table_t *table);
 
static inline void qeo_enable_software_position_inject(QEOV2_Type *base)
{
    base->POSTION_SEL |= QEOV2_POSTION_SEL_POSTION_SEL_MASK;
}
 
static inline void qeo_software_position_inject(QEOV2_Type *base, uint32_t position)
{
    base->POSTION_SOFTWARE = QEOV2_POSTION_SOFTWARE_POSTION_SOFTWAVE_SET(position);
}
 
static inline void qeo_disable_software_position_inject(QEOV2_Type *base)
{
    base->POSTION_SEL &= ~QEOV2_POSTION_SEL_POSTION_SEL_MASK;
}
 
static inline bool qeo_check_calculate_finish(QEOV2_Type *base)
{
    return (QEOV2_DEBUG1_QEO_FINISH_GET(base->DEBUG1) != 0) ? true : false;
}
 
#if defined(HPM_IP_FEATURE_QEOV2_POSITION_FILTER) && HPM_IP_FEATURE_QEOV2_POSITION_FILTER
static inline void qeo_wave_set_position_filter_threshold(QEOV2_Type *base, uint32_t threshold)
{
    base->WAVE.FILTER = QEOV2_WAVE_FILTER_VAL_SET(threshold);
}
 
static inline void qeo_abz_set_position_filter_threshold(QEOV2_Type *base, uint32_t threshold)
{
    base->ABZ.FILTER = QEOV2_ABZ_FILTER_VAL_SET(threshold);
}
 
static inline void qeo_pwm_set_position_filter_threshold(QEOV2_Type *base, uint32_t threshold)
{
    base->PWM.FILTER = QEOV2_PWM_FILTER_VAL_SET(threshold);
}
#endif
 
 
#ifdef __cplusplus
}
#endif
#endif /* HPM_QEOV2_DRV_H */