HPM SDK
HPMicro Software Development Kit
hpm_interrupt.h
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1 /*
2  * Copyright (c) 2023-2024 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 #ifndef HPM_INTERRUPT_H
9 #define HPM_INTERRUPT_H
10 #include "hpm_common.h"
11 #include "hpm_csr_drv.h"
12 #include "hpm_plic_drv.h"
13 
20 #define M_MODE 0
21 #define S_MODE 1
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26 
27 /* Machine mode API: these APIs are supposed to be called at machine mode */
28 
34 ATTR_ALWAYS_INLINE static inline void enable_global_irq(uint32_t mask)
35 {
36  set_csr(CSR_MSTATUS, mask);
37 }
38 
45 ATTR_ALWAYS_INLINE static inline uint32_t disable_global_irq(uint32_t mask)
46 {
47  return read_clear_csr(CSR_MSTATUS, mask);
48 }
49 
55 ATTR_ALWAYS_INLINE static inline void restore_global_irq(uint32_t mask)
56 {
57  set_csr(CSR_MSTATUS, mask);
58 }
59 
64 ATTR_ALWAYS_INLINE static inline void enable_irq_from_intc(void)
65 {
66  set_csr(CSR_MIE, CSR_MIE_MEIE_MASK);
67 }
68 
73 ATTR_ALWAYS_INLINE static inline void disable_irq_from_intc(void)
74 {
75  clear_csr(CSR_MIE, CSR_MIE_MEIE_MASK);
76 }
77 
81 ATTR_ALWAYS_INLINE static inline void enable_mchtmr_irq(void)
82 {
83  set_csr(CSR_MIE, CSR_MIE_MTIE_MASK);
84 }
85 
90 ATTR_ALWAYS_INLINE static inline void disable_mchtmr_irq(void)
91 {
92  clear_csr(CSR_MIE, CSR_MIE_MTIE_MASK);
93 }
94 
95 /*
96  * CPU Machine SWI control
97  *
98  * Machine SWI (MSIP) is connected to PLICSW irq 1.
99  */
100 #define PLICSWI 1
101 
106 ATTR_ALWAYS_INLINE static inline void intc_m_init_swi(void)
107 {
108  __plic_enable_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI);
109 }
110 
111 
116 ATTR_ALWAYS_INLINE static inline void intc_m_enable_swi(void)
117 {
118  set_csr(CSR_MIE, CSR_MIE_MSIE_MASK);
119 }
120 
121 
126 ATTR_ALWAYS_INLINE static inline void intc_m_disable_swi(void)
127 {
128  clear_csr(CSR_MIE, CSR_MIE_MSIE_MASK);
129 }
130 
131 
136 ATTR_ALWAYS_INLINE static inline void intc_m_trigger_swi(void)
137 {
138  __plic_set_irq_pending(HPM_PLICSW_BASE, PLICSWI);
139 }
140 
145 ATTR_ALWAYS_INLINE static inline void intc_m_claim_swi(void)
146 {
147  __plic_claim_irq(HPM_PLICSW_BASE, 0);
148 }
149 
154 ATTR_ALWAYS_INLINE static inline void intc_m_complete_swi(void)
155 {
156  __plic_complete_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI);
157 }
158 
159 /*
160  * @brief Enable IRQ for machine mode
161  *
162  * @param[in] irq Interrupt number
163  */
164 #define intc_m_enable_irq(irq) \
165  intc_enable_irq(HPM_PLIC_TARGET_M_MODE, irq)
166 
167 /*
168  * @brief Disable IRQ for machine mode
169  *
170  * @param[in] irq Interrupt number
171  */
172 #define intc_m_disable_irq(irq) \
173  intc_disable_irq(HPM_PLIC_TARGET_M_MODE, irq)
174 
175 #define intc_m_set_threshold(threshold) \
176  intc_set_threshold(HPM_PLIC_TARGET_M_MODE, threshold)
177 
178 /*
179  * @brief Complete IRQ for machine mode
180  *
181  * @param[in] irq Interrupt number
182  */
183 #define intc_m_complete_irq(irq) \
184  intc_complete_irq(HPM_PLIC_TARGET_M_MODE, irq)
185 
186 /*
187  * @brief Claim IRQ for machine mode
188  *
189  */
190 #define intc_m_claim_irq() intc_claim_irq(HPM_PLIC_TARGET_M_MODE)
191 
192 /*
193  * @brief Enable IRQ for machine mode with priority
194  *
195  * @param[in] irq Interrupt number
196  * @param[in] priority Priority of interrupt
197  */
198 #define intc_m_enable_irq_with_priority(irq, priority) \
199  do { \
200  intc_set_irq_priority(irq, priority); \
201  intc_m_enable_irq(irq); \
202  } while (0)
203 
204 /*
205  * @brief Enable specific interrupt
206  *
207  * @param[in] target Target to handle specific interrupt
208  * @param[in] irq Interrupt number
209  */
210 ATTR_ALWAYS_INLINE static inline void intc_enable_irq(uint32_t target, uint32_t irq)
211 {
212  __plic_enable_irq(HPM_PLIC_BASE, target, irq);
213 }
214 
221 ATTR_ALWAYS_INLINE static inline void intc_set_irq_priority(uint32_t irq, uint32_t priority)
222 {
223  __plic_set_irq_priority(HPM_PLIC_BASE, irq, priority);
224 }
225 
232 ATTR_ALWAYS_INLINE static inline void intc_disable_irq(uint32_t target, uint32_t irq)
233 {
234  __plic_disable_irq(HPM_PLIC_BASE, target, irq);
235 }
236 
243 ATTR_ALWAYS_INLINE static inline void intc_set_threshold(uint32_t target, uint32_t threshold)
244 {
245  __plic_set_threshold(HPM_PLIC_BASE, target, threshold);
246 }
247 
254 ATTR_ALWAYS_INLINE static inline uint32_t intc_claim_irq(uint32_t target)
255 {
256  return __plic_claim_irq(HPM_PLIC_BASE, target);
257 }
258 
266 ATTR_ALWAYS_INLINE static inline void intc_complete_irq(uint32_t target, uint32_t irq)
267 {
268  __plic_complete_irq(HPM_PLIC_BASE, target, irq);
269 }
270 
271 /*
272  * Vectored based irq install and uninstall
273  */
274 /* Machine mode */
275 extern int __vector_table[];
276 
277 extern void default_irq_entry(void);
278 
286 ATTR_ALWAYS_INLINE static inline void install_isr(uint32_t irq, uint32_t isr)
287 {
288  __vector_table[irq] = isr;
289 }
290 
297 ATTR_ALWAYS_INLINE static inline void uninstall_isr(uint32_t irq)
298 {
299  __vector_table[irq] = (int) default_irq_entry;
300 }
301 
302 /*
303  * Inline nested irq entry/exit macros
304  */
305 /*
306  * @brief Save CSR
307  * @param[in] r Target CSR to be saved
308  */
309 #define SAVE_CSR(r) register long __##r = read_csr(r);
310 
311 /*
312  * @brief Restore macro
313  *
314  * @param[in] r Target CSR to be restored
315  */
316 #define RESTORE_CSR(r) write_csr(r, __##r);
317 
318 #if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH
319 #define SAVE_MXSTATUS() SAVE_CSR(CSR_MXSTATUS)
320 #define RESTORE_MXSTATUS() RESTORE_CSR(CSR_MXSTATUS)
321 #else
322 #define SAVE_MXSTATUS()
323 #define RESTORE_MXSTATUS()
324 #endif
325 
326 #ifdef __riscv_flen
327 #define SAVE_FCSR() register int __fcsr = read_fcsr();
328 #define RESTORE_FCSR() write_fcsr(__fcsr);
329 #else
330 #define SAVE_FCSR()
331 #define RESTORE_FCSR()
332 #endif
333 
334 #ifdef __riscv_dsp
335 #define SAVE_UCODE() SAVE_CSR(CSR_UCODE)
336 #define RESTORE_UCODE() RESTORE_CSR(CSR_UCODE)
337 #else
338 #define SAVE_UCODE()
339 #define RESTORE_UCODE()
340 #endif
341 
342 #ifdef __riscv_flen
343 #if __riscv_flen == 32
344 /* RV32I caller registers + MCAUSE + MEPC + MSTATUS + 20 FPU caller registers */
345 #define CONTEXT_REG_NUM (4 * (16 + 4 + 20))
346 #else /* __riscv_flen = 64 */
347 /* RV32I caller registers + MCAUSE + MEPC + MSTATUS + 20 DFPU caller */
348 #define CONTEXT_REG_NUM (4*(16 + 4 + 20*2))
349 #endif
350 
351 #else
352 /* RV32I caller registers + MCAUSE + MEPC + MSTATUS */
353 #define CONTEXT_REG_NUM (4 * (16 + 4))
354 #endif
355 
356 #ifdef __riscv_flen
357 /*
358  * Save FPU caller registers:
359  * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack
360  */
361 #if __riscv_flen == 32
362 #ifdef __ICCRISCV__
363 #define SAVE_FPU_CONTEXT() { \
364  __asm volatile("\n\
365  c.fswsp ft0, 20*4\n\
366  c.fswsp ft1, 21*4 \n\
367  c.fswsp ft2, 22*4 \n\
368  c.fswsp ft3, 23*4 \n\
369  c.fswsp ft4, 24*4 \n\
370  c.fswsp ft5, 25*4 \n\
371  c.fswsp ft6, 26*4 \n\
372  c.fswsp ft7, 27*4 \n\
373  c.fswsp fa0, 28*4 \n\
374  c.fswsp fa1, 29*4 \n\
375  c.fswsp fa2, 30*4 \n\
376  c.fswsp fa3, 31*4 \n\
377  c.fswsp fa4, 32*4 \n\
378  c.fswsp fa5, 33*4 \n\
379  c.fswsp fa6, 34*4 \n\
380  c.fswsp fa7, 35*4 \n\
381  c.fswsp ft8, 36*4 \n\
382  c.fswsp ft9, 37*4 \n\
383  c.fswsp ft10, 38*4 \n\
384  c.fswsp ft11, 39*4 \n");\
385 }
386 
387 /*
388  * Restore FPU caller registers:
389  * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack
390  */
391 #define RESTORE_FPU_CONTEXT() { \
392  __asm volatile("\n\
393  c.flwsp ft0, 20*4\n\
394  c.flwsp ft1, 21*4 \n\
395  c.flwsp ft2, 22*4 \n\
396  c.flwsp ft3, 23*4 \n\
397  c.flwsp ft4, 24*4 \n\
398  c.flwsp ft5, 25*4 \n\
399  c.flwsp ft6, 26*4 \n\
400  c.flwsp ft7, 27*4 \n\
401  c.flwsp fa0, 28*4 \n\
402  c.flwsp fa1, 29*4 \n\
403  c.flwsp fa2, 30*4 \n\
404  c.flwsp fa3, 31*4 \n\
405  c.flwsp fa4, 32*4 \n\
406  c.flwsp fa5, 33*4 \n\
407  c.flwsp fa6, 34*4 \n\
408  c.flwsp fa7, 35*4 \n\
409  c.flwsp ft8, 36*4 \n\
410  c.flwsp ft9, 37*4 \n\
411  c.flwsp ft10, 38*4 \n\
412  c.flwsp ft11, 39*4 \n");\
413 }
414 #else /* __ICCRISCV__ not defined */
415 #define SAVE_FPU_CONTEXT() { \
416  __asm volatile("\n\
417  c.fswsp ft0, 20*4(sp)\n\
418  c.fswsp ft1, 21*4(sp) \n\
419  c.fswsp ft2, 22*4(sp) \n\
420  c.fswsp ft3, 23*4(sp) \n\
421  c.fswsp ft4, 24*4(sp) \n\
422  c.fswsp ft5, 25*4(sp) \n\
423  c.fswsp ft6, 26*4(sp) \n\
424  c.fswsp ft7, 27*4(sp) \n\
425  c.fswsp fa0, 28*4(sp) \n\
426  c.fswsp fa1, 29*4(sp) \n\
427  c.fswsp fa2, 30*4(sp) \n\
428  c.fswsp fa3, 31*4(sp) \n\
429  c.fswsp fa4, 32*4(sp) \n\
430  c.fswsp fa5, 33*4(sp) \n\
431  c.fswsp fa6, 34*4(sp) \n\
432  c.fswsp fa7, 35*4(sp) \n\
433  c.fswsp ft8, 36*4(sp) \n\
434  c.fswsp ft9, 37*4(sp) \n\
435  c.fswsp ft10, 38*4(sp) \n\
436  c.fswsp ft11, 39*4(sp) \n");\
437 }
438 
439 /*
440  * Restore FPU caller registers:
441  * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack
442  */
443 #define RESTORE_FPU_CONTEXT() { \
444  __asm volatile("\n\
445  c.flwsp ft0, 20*4(sp)\n\
446  c.flwsp ft1, 21*4(sp) \n\
447  c.flwsp ft2, 22*4(sp) \n\
448  c.flwsp ft3, 23*4(sp) \n\
449  c.flwsp ft4, 24*4(sp) \n\
450  c.flwsp ft5, 25*4(sp) \n\
451  c.flwsp ft6, 26*4(sp) \n\
452  c.flwsp ft7, 27*4(sp) \n\
453  c.flwsp fa0, 28*4(sp) \n\
454  c.flwsp fa1, 29*4(sp) \n\
455  c.flwsp fa2, 30*4(sp) \n\
456  c.flwsp fa3, 31*4(sp) \n\
457  c.flwsp fa4, 32*4(sp) \n\
458  c.flwsp fa5, 33*4(sp) \n\
459  c.flwsp fa6, 34*4(sp) \n\
460  c.flwsp fa7, 35*4(sp) \n\
461  c.flwsp ft8, 36*4(sp) \n\
462  c.flwsp ft9, 37*4(sp) \n\
463  c.flwsp ft10, 38*4(sp) \n\
464  c.flwsp ft11, 39*4(sp) \n");\
465 }
466 #endif
467 #else /*__riscv_flen == 64*/
468 #ifdef __ICCRISCV__
469 #define SAVE_FPU_CONTEXT() { \
470  __asm volatile("\n\
471  c.fsdsp ft0, 20*4\n\
472  c.fsdsp ft1, 22*4 \n\
473  c.fsdsp ft2, 24*4 \n\
474  c.fsdsp ft3, 26*4 \n\
475  c.fsdsp ft4, 28*4 \n\
476  c.fsdsp ft5, 30*4 \n\
477  c.fsdsp ft6, 32*4 \n\
478  c.fsdsp ft7, 34*4 \n\
479  c.fsdsp fa0, 36*4 \n\
480  c.fsdsp fa1, 38*4 \n\
481  c.fsdsp fa2, 40*4 \n\
482  c.fsdsp fa3, 42*4 \n\
483  c.fsdsp fa4, 44*4 \n\
484  c.fsdsp fa5, 46*4 \n\
485  c.fsdsp fa6, 48*4 \n\
486  c.fsdsp fa7, 50*4 \n\
487  c.fsdsp ft8, 52*4 \n\
488  c.fsdsp ft9, 54*4 \n\
489  c.fsdsp ft10, 56*4 \n\
490  c.fsdsp ft11, 58*4 \n");\
491 }
492 
493 /*
494  * Restore FPU caller registers:
495  * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack
496  */
497 #define RESTORE_FPU_CONTEXT() { \
498  __asm volatile("\n\
499  c.fldsp ft0, 20*4\n\
500  c.fldsp ft1, 22*4 \n\
501  c.fldsp ft2, 24*4 \n\
502  c.fldsp ft3, 26*4 \n\
503  c.fldsp ft4, 28*4 \n\
504  c.fldsp ft5, 30*4 \n\
505  c.fldsp ft6, 32*4 \n\
506  c.fldsp ft7, 34*4 \n\
507  c.fldsp fa0, 36*4 \n\
508  c.fldsp fa1, 38*4 \n\
509  c.fldsp fa2, 40*4 \n\
510  c.fldsp fa3, 42*4 \n\
511  c.fldsp fa4, 44*4 \n\
512  c.fldsp fa5, 46*4 \n\
513  c.fldsp fa6, 48*4 \n\
514  c.fldsp fa7, 50*4 \n\
515  c.fldsp ft8, 52*4 \n\
516  c.fldsp ft9, 54*4 \n\
517  c.fldsp ft10, 56*4 \n\
518  c.fldsp ft11, 58*4 \n");\
519 }
520 #else
521 #define SAVE_FPU_CONTEXT() { \
522  __asm volatile("\n\
523  c.fsdsp ft0, 20*4(sp)\n\
524  c.fsdsp ft1, 22*4(sp) \n\
525  c.fsdsp ft2, 24*4(sp) \n\
526  c.fsdsp ft3, 26*4(sp) \n\
527  c.fsdsp ft4, 28*4(sp) \n\
528  c.fsdsp ft5, 30*4(sp) \n\
529  c.fsdsp ft6, 32*4(sp) \n\
530  c.fsdsp ft7, 34*4(sp) \n\
531  c.fsdsp fa0, 36*4(sp) \n\
532  c.fsdsp fa1, 38*4(sp) \n\
533  c.fsdsp fa2, 40*4(sp) \n\
534  c.fsdsp fa3, 42*4(sp) \n\
535  c.fsdsp fa4, 44*4(sp) \n\
536  c.fsdsp fa5, 46*4(sp) \n\
537  c.fsdsp fa6, 48*4(sp) \n\
538  c.fsdsp fa7, 50*4(sp) \n\
539  c.fsdsp ft8, 52*4(sp) \n\
540  c.fsdsp ft9, 54*4(sp) \n\
541  c.fsdsp ft10, 56*4(sp) \n\
542  c.fsdsp ft11, 58*4(sp) \n");\
543 }
544 
545 /*
546  * Restore FPU caller registers:
547  * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack
548  */
549 #define RESTORE_FPU_CONTEXT() { \
550  __asm volatile("\n\
551  c.fldsp ft0, 20*4(sp)\n\
552  c.fldsp ft1, 22*4(sp) \n\
553  c.fldsp ft2, 24*4(sp) \n\
554  c.fldsp ft3, 26*4(sp) \n\
555  c.fldsp ft4, 28*4(sp) \n\
556  c.fldsp ft5, 30*4(sp) \n\
557  c.fldsp ft6, 32*4(sp) \n\
558  c.fldsp ft7, 34*4(sp) \n\
559  c.fldsp fa0, 36*4(sp) \n\
560  c.fldsp fa1, 38*4(sp) \n\
561  c.fldsp fa2, 40*4(sp) \n\
562  c.fldsp fa3, 42*4(sp) \n\
563  c.fldsp fa4, 44*4(sp) \n\
564  c.fldsp fa5, 46*4(sp) \n\
565  c.fldsp fa6, 48*4(sp) \n\
566  c.fldsp fa7, 50*4(sp) \n\
567  c.fldsp ft8, 52*4(sp) \n\
568  c.fldsp ft9, 54*4(sp) \n\
569  c.fldsp ft10, 56*4(sp) \n\
570  c.fldsp ft11, 58*4(sp) \n");\
571 }
572 #endif
573 #endif
574 #else
575 #define SAVE_FPU_CONTEXT()
576 #define RESTORE_FPU_CONTEXT()
577 #endif
578 
579 #ifdef __ICCRISCV__
583 #define SAVE_CALLER_CONTEXT() { \
584  __asm volatile("addi sp, sp, %0" : : "i"(-CONTEXT_REG_NUM) :);\
585  __asm volatile("\n\
586  c.swsp ra, 0*4 \n\
587  c.swsp t0, 1*4 \n\
588  c.swsp t1, 2*4 \n\
589  c.swsp t2, 3*4 \n\
590  c.swsp s0, 4*4 \n\
591  c.swsp s1, 5*4 \n\
592  c.swsp a0, 6*4 \n\
593  c.swsp a1, 7*4 \n\
594  c.swsp a2, 8*4 \n\
595  c.swsp a3, 9*4 \n\
596  c.swsp a4, 10*4 \n\
597  c.swsp a5, 11*4 \n\
598  c.swsp a6, 12*4 \n\
599  c.swsp a7, 13*4 \n\
600  c.swsp s2, 14*4 \n\
601  c.swsp s3, 15*4 \n\
602  c.swsp t3, 16*4 \n\
603  c.swsp t4, 17*4 \n\
604  c.swsp t5, 18*4 \n\
605  c.swsp t6, 19*4"); \
606  SAVE_FPU_CONTEXT(); \
607 }
608 
612 #define RESTORE_CALLER_CONTEXT() { \
613  __asm volatile("\n\
614  c.lwsp ra, 0*4 \n\
615  c.lwsp t0, 1*4 \n\
616  c.lwsp t1, 2*4 \n\
617  c.lwsp t2, 3*4 \n\
618  c.lwsp s0, 4*4 \n\
619  c.lwsp s1, 5*4 \n\
620  c.lwsp a0, 6*4 \n\
621  c.lwsp a1, 7*4 \n\
622  c.lwsp a2, 8*4 \n\
623  c.lwsp a3, 9*4 \n\
624  c.lwsp a4, 10*4 \n\
625  c.lwsp a5, 11*4 \n\
626  c.lwsp a6, 12*4 \n\
627  c.lwsp a7, 13*4 \n\
628  c.lwsp s2, 14*4 \n\
629  c.lwsp s3, 15*4 \n\
630  c.lwsp t3, 16*4 \n\
631  c.lwsp t4, 17*4 \n\
632  c.lwsp t5, 18*4 \n\
633  c.lwsp t6, 19*4 \n");\
634  RESTORE_FPU_CONTEXT(); \
635  __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\
636 }
637 #else
641 #define SAVE_CALLER_CONTEXT() { \
642  __asm volatile("addi sp, sp, %0" : : "i"(-CONTEXT_REG_NUM) :);\
643  __asm volatile("\n\
644  c.swsp ra, 0*4(sp) \n\
645  c.swsp t0, 1*4(sp) \n\
646  c.swsp t1, 2*4(sp) \n\
647  c.swsp t2, 3*4(sp) \n\
648  c.swsp s0, 4*4(sp) \n\
649  c.swsp s1, 5*4(sp) \n\
650  c.swsp a0, 6*4(sp) \n\
651  c.swsp a1, 7*4(sp) \n\
652  c.swsp a2, 8*4(sp) \n\
653  c.swsp a3, 9*4(sp) \n\
654  c.swsp a4, 10*4(sp) \n\
655  c.swsp a5, 11*4(sp) \n\
656  c.swsp a6, 12*4(sp) \n\
657  c.swsp a7, 13*4(sp) \n\
658  c.swsp s2, 14*4(sp) \n\
659  c.swsp s3, 15*4(sp) \n\
660  c.swsp t3, 16*4(sp) \n\
661  c.swsp t4, 17*4(sp) \n\
662  c.swsp t5, 18*4(sp) \n\
663  c.swsp t6, 19*4(sp)"); \
664  SAVE_FPU_CONTEXT(); \
665 }
666 
670 #define RESTORE_CALLER_CONTEXT() { \
671  __asm volatile("\n\
672  c.lwsp ra, 0*4(sp) \n\
673  c.lwsp t0, 1*4(sp) \n\
674  c.lwsp t1, 2*4(sp) \n\
675  c.lwsp t2, 3*4(sp) \n\
676  c.lwsp s0, 4*4(sp) \n\
677  c.lwsp s1, 5*4(sp) \n\
678  c.lwsp a0, 6*4(sp) \n\
679  c.lwsp a1, 7*4(sp) \n\
680  c.lwsp a2, 8*4(sp) \n\
681  c.lwsp a3, 9*4(sp) \n\
682  c.lwsp a4, 10*4(sp) \n\
683  c.lwsp a5, 11*4(sp) \n\
684  c.lwsp a6, 12*4(sp) \n\
685  c.lwsp a7, 13*4(sp) \n\
686  c.lwsp s2, 14*4(sp) \n\
687  c.lwsp s3, 15*4(sp) \n\
688  c.lwsp t3, 16*4(sp) \n\
689  c.lwsp t4, 17*4(sp) \n\
690  c.lwsp t5, 18*4(sp) \n\
691  c.lwsp t6, 19*4(sp) \n");\
692  RESTORE_FPU_CONTEXT(); \
693  __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\
694 }
695 #endif
696 
697 #ifdef __riscv_flen
698 #define SAVE_FPU_STATE() { \
699  __asm volatile("frcsr s1\n"); \
700 }
701 
702 #define RESTORE_FPU_STATE() { \
703  __asm volatile("fscsr s1\n"); \
704 }
705 #else
706 #define SAVE_FPU_STATE()
707 #define RESTORE_FPU_STATE()
708 #endif
709 
710 #ifdef __riscv_dsp
711 /*
712  * Save DSP context
713  * NOTE: DSP context registers are stored at word offset 41 in the stack
714  */
715 #define SAVE_DSP_CONTEXT() { \
716  __asm volatile("csrrs s0, %0, x0\n" ::"i"(CSR_UCODE):); \
717 }
718 /*
719  * @brief Restore DSP context
720  * @note DSP context registers are stored at word offset 41 in the stack
721  */
722 #define RESTORE_DSP_CONTEXT() {\
723  __asm volatile("csrw %0, s0\n" ::"i"(CSR_UCODE):); \
724 }
725 
726 #else
727 #define SAVE_DSP_CONTEXT()
728 #define RESTORE_DSP_CONTEXT()
729 #endif
730 
731 /*
732  * @brief Enter Nested IRQ Handling
733  * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below:
734  * MCAUSE - word offset 16 (not used in the vectored mode)
735  * EPC - word offset 17
736  * MSTATUS = word offset 18
737  * MXSTATUS = word offset 19
738  */
739 #define ENTER_NESTED_IRQ_HANDLING_M() { \
740  __asm volatile("\n\
741  csrr s2, mepc \n\
742  csrr s3, mstatus \n");\
743  SAVE_FPU_STATE(); \
744  SAVE_DSP_CONTEXT(); \
745  __asm volatile("csrsi mstatus, 8"); \
746 }
747 
748 /*
749  * @brief Complete IRQ Handling
750  */
751 #define COMPLETE_IRQ_HANDLING_M(irq_num) { \
752  __asm volatile("csrci mstatus, 8"); \
753  __asm volatile("lui a4, 0xe4200"); \
754  __asm volatile("li a3, %0" : : "i" (irq_num) :); \
755  __asm volatile("sw a3, 4(a4)"); \
756 }
757 
758 /*
759  * @brief Exit Nested IRQ Handling
760  * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below:
761  * MCAUSE - word offset 16 (not used in the vectored mode)
762  * EPC - word offset 17
763  * MSTATUS = word offset 18
764  * MXSTATUS = word offset 19
765  */
766 #define EXIT_NESTED_IRQ_HANDLING_M() { \
767  __asm volatile("\n\
768  csrw mstatus, s3 \n\
769  csrw mepc, s2 \n");\
770  RESTORE_FPU_STATE(); \
771  RESTORE_DSP_CONTEXT(); \
772 }
773 
774 /* @brief Nested IRQ entry macro : Save CSRs and enable global irq. */
775 #define NESTED_IRQ_ENTER() \
776  SAVE_CSR(CSR_MEPC) \
777  SAVE_CSR(CSR_MSTATUS) \
778  SAVE_MXSTATUS() \
779  SAVE_FCSR() \
780  SAVE_UCODE() \
781  set_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK);
782 
783 /* @brief Nested IRQ exit macro : Restore CSRs */
784 #define NESTED_IRQ_EXIT() \
785  RESTORE_CSR(CSR_MSTATUS) \
786  RESTORE_CSR(CSR_MEPC) \
787  RESTORE_MXSTATUS() \
788  RESTORE_FCSR() \
789  RESTORE_UCODE()
790 
791 #ifdef __cplusplus
792 #define HPM_EXTERN_C extern "C"
793 #else
794 #define HPM_EXTERN_C
795 #endif
796 
797 #define ISR_NAME_M(irq_num) default_isr_##irq_num
804 #if !defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0)
805 #if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS
806 #define FREERTOS_VECTOR_ISR_WRAPPER_NAME(irq_num) irq_handler_wrapper_##irq_num
807 #define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \
808 void isr(void) __attribute__((section(".isr_vector"))); \
809 EXTERN_C void FREERTOS_VECTOR_ISR_WRAPPER_NAME(irq_num)(void) __attribute__((section(".isr_vector"))); \
810 void FREERTOS_VECTOR_ISR_WRAPPER_NAME(irq_num)(void) \
811 { \
812  isr();\
813 }
814 #else
815 #define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \
816 void isr(void) __attribute__((section(".isr_vector")));\
817 HPM_EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\
818 void ISR_NAME_M(irq_num)(void) \
819 { \
820  SAVE_CALLER_CONTEXT(); \
821  ENTER_NESTED_IRQ_HANDLING_M();\
822  __asm volatile("la t1, %0\n\t" : : "i" (isr) : );\
823  __asm volatile("jalr t1\n");\
824  COMPLETE_IRQ_HANDLING_M(irq_num);\
825  EXIT_NESTED_IRQ_HANDLING_M();\
826  RESTORE_CALLER_CONTEXT();\
827  __asm volatile("fence io, io");\
828  __asm volatile("mret\n");\
829 }
830 #endif
831 #else
832 #define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \
833 void isr(void) __attribute__((section(".isr_vector")));\
834 HPM_EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\
835 void ISR_NAME_M(irq_num)(void) \
836 { \
837  isr(); \
838 }
839 #endif
840 
841 
847 #define SDK_DECLARE_MCHTMR_ISR(isr) \
848 void isr(void) __attribute__((section(".isr_vector")));\
849 HPM_EXTERN_C void mchtmr_isr(void) __attribute__((section(".isr_vector"))); \
850 void mchtmr_isr(void) \
851 { \
852  isr();\
853 }
854 
860 #define SDK_DECLARE_SWI_ISR(isr)\
861 void isr(void) __attribute__((section(".isr_vector")));\
862 HPM_EXTERN_C void swi_isr(void) __attribute__((section(".isr_vector"))); \
863 void swi_isr(void) \
864 { \
865  isr();\
866 }
867 
868 
869 #ifdef __cplusplus
870 }
871 #endif
872 
876 #endif /* HPM_INTERRUPT_H */
CSR_MIE_MEIE_MASK
#define CSR_MIE_MEIE_MASK
Definition: hpm_csr_regs.h:734
CSR_MSTATUS
#define CSR_MSTATUS
Definition: hpm_csr_regs.h:21
CSR_MIE_MTIE_MASK
#define CSR_MIE_MTIE_MASK
Definition: hpm_csr_regs.h:758
CSR_MIE
#define CSR_MIE
Definition: hpm_csr_regs.h:23
CSR_MIE_MSIE_MASK
#define CSR_MIE_MSIE_MASK
Definition: hpm_csr_regs.h:782
HPM_PLICSW_BASE
#define HPM_PLICSW_BASE
Definition: hpm_soc.h:94
HPM_PLIC_BASE
#define HPM_PLIC_BASE
Definition: hpm_soc.h:80
hpm_plic_drv.h
intc_complete_irq
static ATTR_ALWAYS_INLINE void intc_complete_irq(uint32_t target, uint32_t irq)
Complete IRQ.
Definition: hpm_interrupt.h:266
enable_global_irq
static ATTR_ALWAYS_INLINE void enable_global_irq(uint32_t mask)
Enable global IRQ with mask.
Definition: hpm_interrupt.h:34
intc_m_disable_swi
static ATTR_ALWAYS_INLINE void intc_m_disable_swi(void)
Disable software interrupt.
Definition: hpm_interrupt.h:126
disable_irq_from_intc
static ATTR_ALWAYS_INLINE void disable_irq_from_intc(void)
Disable IRQ from interrupt controller.
Definition: hpm_interrupt.h:73
intc_set_irq_priority
static ATTR_ALWAYS_INLINE void intc_set_irq_priority(uint32_t irq, uint32_t priority)
Set interrupt priority.
Definition: hpm_interrupt.h:221
intc_disable_irq
static ATTR_ALWAYS_INLINE void intc_disable_irq(uint32_t target, uint32_t irq)
Disable specific interrupt.
Definition: hpm_interrupt.h:232
intc_m_trigger_swi
static ATTR_ALWAYS_INLINE void intc_m_trigger_swi(void)
Trigger software interrupt.
Definition: hpm_interrupt.h:136
install_isr
static ATTR_ALWAYS_INLINE void install_isr(uint32_t irq, uint32_t isr)
Install ISR for certain IRQ for ram based vector table.
Definition: hpm_interrupt.h:286
default_irq_entry
void default_irq_entry(void)
enable_irq_from_intc
static ATTR_ALWAYS_INLINE void enable_irq_from_intc(void)
Enable IRQ from interrupt controller.
Definition: hpm_interrupt.h:64
restore_global_irq
static ATTR_ALWAYS_INLINE void restore_global_irq(uint32_t mask)
Restore global IRQ with mask.
Definition: hpm_interrupt.h:55
intc_enable_irq
static ATTR_ALWAYS_INLINE void intc_enable_irq(uint32_t target, uint32_t irq)
Definition: hpm_interrupt.h:210
PLICSWI
#define PLICSWI
Definition: hpm_interrupt.h:100
disable_mchtmr_irq
static ATTR_ALWAYS_INLINE void disable_mchtmr_irq(void)
Disable machine timer IRQ.
Definition: hpm_interrupt.h:90
intc_m_init_swi
static ATTR_ALWAYS_INLINE void intc_m_init_swi(void)
Initialize software interrupt.
Definition: hpm_interrupt.h:106
intc_m_enable_swi
static ATTR_ALWAYS_INLINE void intc_m_enable_swi(void)
Enable software interrupt.
Definition: hpm_interrupt.h:116
intc_m_complete_swi
static ATTR_ALWAYS_INLINE void intc_m_complete_swi(void)
Complete software interrupt.
Definition: hpm_interrupt.h:154
intc_set_threshold
static ATTR_ALWAYS_INLINE void intc_set_threshold(uint32_t target, uint32_t threshold)
Set interrupt threshold.
Definition: hpm_interrupt.h:243
uninstall_isr
static ATTR_ALWAYS_INLINE void uninstall_isr(uint32_t irq)
Uninstall ISR for certain IRQ for ram based vector table.
Definition: hpm_interrupt.h:297
intc_claim_irq
static ATTR_ALWAYS_INLINE uint32_t intc_claim_irq(uint32_t target)
Claim IRQ.
Definition: hpm_interrupt.h:254
intc_m_claim_swi
static ATTR_ALWAYS_INLINE void intc_m_claim_swi(void)
Claim software interrupt.
Definition: hpm_interrupt.h:145
disable_global_irq
static ATTR_ALWAYS_INLINE uint32_t disable_global_irq(uint32_t mask)
Disable global IRQ with mask and return mstatus.
Definition: hpm_interrupt.h:45
enable_mchtmr_irq
static ATTR_ALWAYS_INLINE void enable_mchtmr_irq(void)
Enable machine timer IRQ.
Definition: hpm_interrupt.h:81
HPM_PLIC_TARGET_M_MODE
#define HPM_PLIC_TARGET_M_MODE
Definition: hpm_plic_drv.h:17
hpm_common.h
hpm_csr_drv.h
set_csr
#define set_csr(csr_num, bit)
set bits in csr
Definition: riscv_core.h:58
clear_csr
#define clear_csr(csr_num, bit)
clear bits in csr
Definition: riscv_core.h:30
read_clear_csr
#define read_clear_csr(csr_num, bit)
read and clear bits in csr
Definition: riscv_core.h:40