hpm_i2c_drv.h

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/*
 * Copyright (c) 2021 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
 */
 
#ifndef HPM_I2C_DRV_H
#define HPM_I2C_DRV_H
#include "hpm_common.h"
#include "hpm_i2c_regs.h"
#include "hpm_soc_feature.h"
 
enum {
    status_i2c_no_ack = MAKE_STATUS(status_group_i2c, 1),
    status_i2c_invalid_data = MAKE_STATUS(status_group_i2c, 2),
    status_i2c_no_addr_hit = MAKE_STATUS(status_group_i2c, 3),
    status_i2c_transmit_not_completed = MAKE_STATUS(status_group_i2c, 4),
    status_i2c_not_supported = MAKE_STATUS(status_group_i2c, 9),
};
 
/* convert data count value into register(CTRL[DATACNT] and CTRL[DATACNT_HIGH] if exist) */
/* x range from 1 to I2C_SOC_TRANSFER_COUNT_MAX */
/* 0 for I2C_SOC_TRANSFER_COUNT_MAX */
#define I2C_DATACNT_MAP(x) (((x) == I2C_SOC_TRANSFER_COUNT_MAX) ? 0 : x)
 
#define I2C_CMD_NO_ACTION (I2C_CMD_CMD_SET(0))
#define I2C_CMD_ISSUE_DATA_TRANSMISSION (I2C_CMD_CMD_SET(1))
#define I2C_CMD_ACK (I2C_CMD_CMD_SET(2))
#define I2C_CMD_NACK (I2C_CMD_CMD_SET(3))
#define I2C_CMD_CLEAR_FIFO (I2C_CMD_CMD_SET(4))
#define I2C_CMD_RESET (I2C_CMD_CMD_SET(5))
 
#define I2C_DIR_MASTER_WRITE (0U)
#define I2C_DIR_MASTER_READ (1U)
#define I2C_DIR_SLAVE_READ (0U)
#define I2C_DIR_SLAVE_WRITE (1U)
 
#define I2C_EVENT_TRANSACTION_COMPLETE  I2C_INTEN_CMPL_MASK
#define I2C_EVENT_BYTE_RECEIVED         I2C_INTEN_BYTERECV_MASK
#define I2C_EVENT_BYTE_TRANSMIT         I2C_INTEN_BYTETRANS_MASK
#define I2C_EVENT_START_CONDITION       I2C_INTEN_START_MASK
#define I2C_EVENT_STOP_CONDITION        I2C_INTEN_STOP_MASK
#define I2C_EVENT_LOSS_ARBITRATION      I2C_INTEN_ARBLOSE_MASK
#define I2C_EVENT_ADDRESS_HIT           I2C_INTEN_ADDRHIT_MASK
#define I2C_EVENT_FIFO_HALF             I2C_INTEN_FIFOHALF_MASK
#define I2C_EVENT_FIFO_FULL             I2C_INTEN_FIFOFULL_MASK
#define I2C_EVENT_FIFO_EMPTY            I2C_INTEN_FIFOEMPTY_MASK
 
#define I2C_EVENT_ALL_MASK          (I2C_INTEN_CMPL_MASK \
                                        | I2C_INTEN_BYTERECV_MASK \
                                        | I2C_INTEN_BYTETRANS_MASK \
                                        | I2C_INTEN_START_MASK \
                                        | I2C_INTEN_STOP_MASK \
                                        | I2C_INTEN_ARBLOSE_MASK \
                                        | I2C_INTEN_ADDRHIT_MASK \
                                        | I2C_INTEN_FIFOHALF_MASK \
                                        | I2C_INTEN_FIFOFULL_MASK \
                                        | I2C_INTEN_FIFOEMPTY_MASK)
#define I2C_STATUS_LINE_SDA             I2C_STATUS_LINESDA_MASK
#define I2C_STATUS_LINE_SCL             I2C_STATUS_LINESCL_MASK
#define I2C_STATUS_GENERAL_CALL         I2C_STATUS_GENCALL_MASK
#define I2C_STATUS_BUS_BUSY             I2C_STATUS_BUSBUSY_MASK
#define I2C_STATUS_ACK                  I2C_STATUS_ACK_MASK
 
#define I2C_WR                0x0000    /* not operable with read flags*/
#define I2C_RD               (1u << 0)  /* not operable with write flags*/
#define I2C_ADDR_10BIT       (1u << 2)  /* this is a ten bit chip address */
#define I2C_NO_START         (1u << 4)  /* no start */
#define I2C_NO_READ_ACK      (1u << 6)  /* when I2C reading, we do not ACK */
#define I2C_NO_STOP          (1u << 7)  /* no stop */
#define I2C_WRITE_CHECK_ACK  (1u << 8)  /* when I2C writing, need check the slave returns ack */
 
typedef struct {
    bool is_10bit_addressing;
    uint8_t i2c_mode;
} i2c_config_t;
 
typedef enum i2c_mode {
    i2c_mode_normal,
    i2c_mode_fast,
    i2c_mode_fast_plus,
} i2c_mode_t;
 
typedef enum i2c_seq_transfer_opt {
    i2c_frist_frame = 0,
    i2c_next_frame,
    i2c_last_frame,
} i2c_seq_transfer_opt_t;
 
#ifdef __cplusplus
extern "C" {
#endif
 
static inline void i2c_respond_Nack(I2C_Type *ptr)
{
    ptr->CMD = I2C_CMD_NACK;
}
 
static inline void i2c_respond_ack(I2C_Type *ptr)
{
    ptr->CMD = I2C_CMD_ACK;
}
 
static inline void i2c_clear_fifo(I2C_Type *ptr)
{
    ptr->CMD = I2C_CMD_CLEAR_FIFO;
}
 
static inline uint16_t i2c_get_data_count(I2C_Type *ptr)
{
    uint32_t i2c_ctrl = ptr->CTRL;
#ifdef I2C_CTRL_DATACNT_HIGH_MASK
    return (I2C_CTRL_DATACNT_HIGH_GET(i2c_ctrl) << 8U) + I2C_CTRL_DATACNT_GET(i2c_ctrl);
#else
    return I2C_CTRL_DATACNT_GET(i2c_ctrl);
#endif
}
 
static inline bool i2c_fifo_is_full(I2C_Type *ptr)
{
    return ptr->STATUS & I2C_STATUS_FIFOFULL_MASK;
}
 
static inline bool i2c_fifo_is_half(I2C_Type *ptr)
{
    return ptr->STATUS & I2C_STATUS_FIFOHALF_MASK;
}
 
static inline bool i2c_fifo_is_empty(I2C_Type *ptr)
{
    return ptr->STATUS & I2C_STATUS_FIFOEMPTY_MASK;
}
 
static inline bool i2c_is_writing(I2C_Type *ptr)
{
    return (ptr->CTRL & I2C_CTRL_DIR_MASK);
}
 
static inline bool i2c_is_reading(I2C_Type *ptr)
{
    return !i2c_is_writing(ptr);
}
 
static inline bool i2c_get_line_sda_status(I2C_Type *ptr)
{
    return I2C_STATUS_LINESDA_GET(ptr->STATUS);
}
 
static inline bool i2c_get_line_scl_status(I2C_Type *ptr)
{
    return I2C_STATUS_LINESCL_GET(ptr->STATUS);
}
 
static inline void i2c_clear_status(I2C_Type *ptr, uint32_t mask)
{
    ptr->STATUS = mask;
}
 
static inline uint32_t i2c_get_status(I2C_Type *ptr)
{
    return ptr->STATUS;
}
 
static inline uint32_t i2c_get_irq_setting(I2C_Type *ptr)
{
    return ptr->INTEN;
}
 
static inline void i2c_disable_irq(I2C_Type *ptr, uint32_t mask)
{
    ptr->INTEN &= ~mask;
}
 
static inline void i2c_enable_irq(I2C_Type *ptr, uint32_t mask)
{
    ptr->INTEN |= mask;
}
 
static inline void i2c_disable_auto_ack(I2C_Type *ptr)
{
    ptr->INTEN &= ~I2C_EVENT_BYTE_RECEIVED;
}
 
static inline void i2c_enable_auto_ack(I2C_Type *ptr)
{
    ptr->INTEN |= I2C_EVENT_BYTE_RECEIVED;
}
 
static inline void i2c_enable_10bit_address_mode(I2C_Type *ptr, bool enable)
{
    ptr->SETUP |= I2C_SETUP_ADDRESSING_SET(enable);
}
 
hpm_stat_t i2c_init_master(I2C_Type *ptr,
                           uint32_t src_clk_in_hz,
                           i2c_config_t *config);
 
hpm_stat_t i2c_master_address_write(I2C_Type *ptr,
                            const uint16_t device_address,
                            uint8_t *addr,
                            uint32_t addr_size_in_byte,
                            uint8_t *buf,
                            const uint32_t size_in_byte);
 
hpm_stat_t i2c_master_address_read(I2C_Type *ptr,
                           const uint16_t device_address,
                           uint8_t *addr,
                           uint32_t addr_size_in_byte,
                           uint8_t *buf,
                           const uint32_t size_in_byte);
 
hpm_stat_t i2c_master_write(I2C_Type *ptr,
                            const uint16_t device_address,
                            uint8_t *buf,
                            const uint32_t size);
 
hpm_stat_t i2c_master_start_dma_write(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size);
 
hpm_stat_t i2c_master_start_dma_read(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size);
 
hpm_stat_t i2c_master_read(I2C_Type *ptr,
                           const uint16_t device_address,
                           uint8_t *buf,
                           const uint32_t size);
hpm_stat_t i2c_init_slave(I2C_Type *ptr, uint32_t src_clk_in_hz,
                          i2c_config_t *config, const uint16_t slave_address);
 
hpm_stat_t i2c_slave_read(I2C_Type *ptr, uint8_t *buf, const uint32_t size);
 
hpm_stat_t i2c_slave_write(I2C_Type *ptr, uint8_t *buf, const uint32_t size);
 
void i2c_reset(I2C_Type *ptr);
 
static inline void i2c_dma_enable(I2C_Type *ptr)
{
    ptr->SETUP |= I2C_SETUP_DMAEN_MASK;
}
 
static inline void i2c_dma_disable(I2C_Type *ptr)
{
    ptr->SETUP &= ~I2C_SETUP_DMAEN_MASK;
}
 
hpm_stat_t i2c_slave_dma_transfer(I2C_Type *ptr,  const uint32_t size);
 
static inline void i2c_write_byte(I2C_Type *ptr, uint8_t data)
{
    ptr->DATA = I2C_DATA_DATA_SET(data);
}
 
static inline uint8_t i2c_read_byte(I2C_Type *ptr)
{
    return (uint8_t)I2C_DATA_DATA_GET(ptr->DATA);
}
 
static inline uint8_t i2c_get_direction(I2C_Type *ptr)
{
    return (uint8_t)I2C_CTRL_DIR_GET(ptr->CTRL);
}
 
hpm_stat_t i2c_master_configure_transfer(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size, bool read);
 
hpm_stat_t i2c_master_seq_transmit_check_ack(I2C_Type *ptr, const uint16_t device_address,
                                   uint8_t *buf, const uint32_t size, i2c_seq_transfer_opt_t opt, bool ack_check);
 
#define i2c_master_seq_transmit(ptr, device_address, buf, size, opt)  i2c_master_seq_transmit_check_ack(ptr, device_address, buf, size, opt, false)
 
hpm_stat_t i2c_master_seq_receive(I2C_Type *ptr, const uint16_t device_address,
                                  uint8_t *buf, const uint32_t size, i2c_seq_transfer_opt_t opt);
 
#if defined(HPM_IP_FEATURE_I2C_SUPPORT_RESET) && (HPM_IP_FEATURE_I2C_SUPPORT_RESET == 1)
static inline void i2c_gen_reset_signal(I2C_Type *ptr, uint8_t clk_len)
{
    ptr->CTRL = (ptr->CTRL & ~I2C_CTRL_RESET_LEN_MASK) | I2C_CTRL_RESET_LEN_SET(clk_len) \
                | I2C_CTRL_RESET_HOLD_SCKIN_MASK | I2C_CTRL_RESET_ON_MASK;
}
#endif
 
hpm_stat_t i2c_master_transfer(I2C_Type *ptr, const uint16_t device_address,
                                    uint8_t *buf, const uint32_t size,  uint16_t flags);
#ifdef __cplusplus
}
#endif
 
#endif /* HPM_I2C_DRV_H */